Commit | Line | Data |
---|---|---|
ed63aa17 AV |
1 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
2 | Michael Collison <michael.collison@arm.com> | |
3 | ||
4 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
5 | (enum mve_undefined): Add new reasons. | |
6 | (is_mve_encoding_conflict): Handle new instructions. | |
7 | (is_mve_undefined): Likewise. | |
8 | (is_mve_unpredictable): Likewise. | |
9 | (print_mve_undefined): Likewise. | |
10 | (print_mve_size): Likewise. | |
11 | (print_mve_shift_n): Likewise. | |
12 | (print_insn_mve): Likewise. | |
13 | ||
897b9bbc AV |
14 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
15 | Michael Collison <michael.collison@arm.com> | |
16 | ||
17 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
18 | (is_mve_encoding_conflict): Handle new instructions. | |
19 | (is_mve_unpredictable): Likewise. | |
20 | (print_mve_rotate): Likewise. | |
21 | (print_mve_size): Likewise. | |
22 | (print_insn_mve): Likewise. | |
23 | ||
1c8f2df8 AV |
24 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
25 | Michael Collison <michael.collison@arm.com> | |
26 | ||
27 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
28 | (is_mve_encoding_conflict): Handle new instructions. | |
29 | (is_mve_unpredictable): Likewise. | |
30 | (print_mve_size): Likewise. | |
31 | (print_insn_mve): Likewise. | |
32 | ||
d3b63143 AV |
33 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
34 | Michael Collison <michael.collison@arm.com> | |
35 | ||
36 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
37 | (enum mve_undefined): Add new reasons. | |
38 | (is_mve_encoding_conflict): Handle new instructions. | |
39 | (is_mve_undefined): Likewise. | |
40 | (is_mve_unpredictable): Likewise. | |
41 | (print_mve_undefined): Likewise. | |
42 | (print_mve_size): Likewise. | |
43 | (print_insn_mve): Likewise. | |
44 | ||
14925797 AV |
45 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
46 | Michael Collison <michael.collison@arm.com> | |
47 | ||
48 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
49 | (is_mve_encoding_conflict): Handle new instructions. | |
50 | (is_mve_undefined): Likewise. | |
51 | (is_mve_unpredictable): Likewise. | |
52 | (print_mve_size): Likewise. | |
53 | (print_insn_mve): Likewise. | |
54 | ||
c507f10b AV |
55 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
56 | Michael Collison <michael.collison@arm.com> | |
57 | ||
58 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
59 | (enum mve_unpredictable): Add new reasons. | |
60 | (enum mve_undefined): Likewise. | |
61 | (is_mve_okay_in_it): Handle new isntructions. | |
62 | (is_mve_encoding_conflict): Likewise. | |
63 | (is_mve_undefined): Likewise. | |
64 | (is_mve_unpredictable): Likewise. | |
65 | (print_mve_vmov_index): Likewise. | |
66 | (print_simd_imm8): Likewise. | |
67 | (print_mve_undefined): Likewise. | |
68 | (print_mve_unpredictable): Likewise. | |
69 | (print_mve_size): Likewise. | |
70 | (print_insn_mve): Likewise. | |
71 | ||
bf0b396d AV |
72 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
73 | Michael Collison <michael.collison@arm.com> | |
74 | ||
75 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
76 | (enum mve_unpredictable): Add new reasons. | |
77 | (enum mve_undefined): Likewise. | |
78 | (is_mve_encoding_conflict): Handle new instructions. | |
79 | (is_mve_undefined): Likewise. | |
80 | (is_mve_unpredictable): Likewise. | |
81 | (print_mve_undefined): Likewise. | |
82 | (print_mve_unpredictable): Likewise. | |
83 | (print_mve_rounding_mode): Likewise. | |
84 | (print_mve_vcvt_size): Likewise. | |
85 | (print_mve_size): Likewise. | |
86 | (print_insn_mve): Likewise. | |
87 | ||
ef1576a1 AV |
88 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
89 | Michael Collison <michael.collison@arm.com> | |
90 | ||
91 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
92 | (enum mve_unpredictable): Add new reasons. | |
93 | (enum mve_undefined): Likewise. | |
94 | (is_mve_undefined): Handle new instructions. | |
95 | (is_mve_unpredictable): Likewise. | |
96 | (print_mve_undefined): Likewise. | |
97 | (print_mve_unpredictable): Likewise. | |
98 | (print_mve_size): Likewise. | |
99 | (print_insn_mve): Likewise. | |
100 | ||
aef6d006 AV |
101 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
102 | Michael Collison <michael.collison@arm.com> | |
103 | ||
104 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
105 | (enum mve_undefined): Add new reasons. | |
106 | (insns): Add new instructions. | |
107 | (is_mve_encoding_conflict): | |
108 | (print_mve_vld_str_addr): New print function. | |
109 | (is_mve_undefined): Handle new instructions. | |
110 | (is_mve_unpredictable): Likewise. | |
111 | (print_mve_undefined): Likewise. | |
112 | (print_mve_size): Likewise. | |
113 | (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. | |
114 | (print_insn_mve): Handle new operands. | |
115 | ||
04d54ace AV |
116 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
117 | Michael Collison <michael.collison@arm.com> | |
118 | ||
119 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
120 | (enum mve_unpredictable): Add new reasons. | |
121 | (is_mve_encoding_conflict): Handle new instructions. | |
122 | (is_mve_unpredictable): Likewise. | |
123 | (mve_opcodes): Add new instructions. | |
124 | (print_mve_unpredictable): Handle new reasons. | |
125 | (print_mve_register_blocks): New print function. | |
126 | (print_mve_size): Handle new instructions. | |
127 | (print_insn_mve): Likewise. | |
128 | ||
9743db03 AV |
129 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
130 | Michael Collison <michael.collison@arm.com> | |
131 | ||
132 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
133 | (enum mve_unpredictable): Add new reasons. | |
134 | (enum mve_undefined): Likewise. | |
135 | (is_mve_encoding_conflict): Handle new instructions. | |
136 | (is_mve_undefined): Likewise. | |
137 | (is_mve_unpredictable): Likewise. | |
138 | (coprocessor_opcodes): Move NEON VDUP from here... | |
139 | (neon_opcodes): ... to here. | |
140 | (mve_opcodes): Add new instructions. | |
141 | (print_mve_undefined): Handle new reasons. | |
142 | (print_mve_unpredictable): Likewise. | |
143 | (print_mve_size): Handle new instructions. | |
144 | (print_insn_neon): Handle vdup. | |
145 | (print_insn_mve): Handle new operands. | |
146 | ||
143275ea AV |
147 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
148 | Michael Collison <michael.collison@arm.com> | |
149 | ||
150 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
151 | (enum mve_unpredictable): Add new values. | |
152 | (mve_opcodes): Add new instructions. | |
153 | (vec_condnames): New array with vector conditions. | |
154 | (mve_predicatenames): New array with predicate suffixes. | |
155 | (mve_vec_sizename): New array with vector sizes. | |
156 | (enum vpt_pred_state): New enum with vector predication states. | |
157 | (struct vpt_block): New struct type for vpt blocks. | |
158 | (vpt_block_state): Global struct to keep track of state. | |
159 | (mve_extract_pred_mask): New helper function. | |
160 | (num_instructions_vpt_block): Likewise. | |
161 | (mark_outside_vpt_block): Likewise. | |
162 | (mark_inside_vpt_block): Likewise. | |
163 | (invert_next_predicate_state): Likewise. | |
164 | (update_next_predicate_state): Likewise. | |
165 | (update_vpt_block_state): Likewise. | |
166 | (is_vpt_instruction): Likewise. | |
167 | (is_mve_encoding_conflict): Add entries for new instructions. | |
168 | (is_mve_unpredictable): Likewise. | |
169 | (print_mve_unpredictable): Handle new cases. | |
170 | (print_instruction_predicate): Likewise. | |
171 | (print_mve_size): New function. | |
172 | (print_vec_condition): New function. | |
173 | (print_insn_mve): Handle vpt blocks and new print operands. | |
174 | ||
f08d8ce3 AV |
175 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
176 | ||
177 | * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors | |
178 | 8, 14 and 15 for Armv8.1-M Mainline. | |
179 | ||
73cd51e5 AV |
180 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
181 | Michael Collison <michael.collison@arm.com> | |
182 | ||
183 | * arm-dis.c (enum mve_instructions): New enum. | |
184 | (enum mve_unpredictable): Likewise. | |
185 | (enum mve_undefined): Likewise. | |
186 | (struct mopcode32): New struct. | |
187 | (is_mve_okay_in_it): New function. | |
188 | (is_mve_architecture): Likewise. | |
189 | (arm_decode_field): Likewise. | |
190 | (arm_decode_field_multiple): Likewise. | |
191 | (is_mve_encoding_conflict): Likewise. | |
192 | (is_mve_undefined): Likewise. | |
193 | (is_mve_unpredictable): Likewise. | |
194 | (print_mve_undefined): Likewise. | |
195 | (print_mve_unpredictable): Likewise. | |
196 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. | |
197 | (print_insn_mve): New function. | |
198 | (print_insn_thumb32): Handle MVE architecture. | |
199 | (select_arm_features): Force thumb for Armv8.1-m Mainline. | |
200 | ||
3076e594 NC |
201 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
202 | ||
203 | PR 24538 | |
204 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the | |
205 | end of the table prematurely. | |
206 | ||
387e7624 FS |
207 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
208 | ||
209 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB | |
210 | macros for R6. | |
211 | ||
0067be51 AM |
212 | 2019-05-11 Alan Modra <amodra@gmail.com> |
213 | ||
214 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands | |
215 | when -Mraw is in effect. | |
216 | ||
42e6288f MM |
217 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
218 | ||
219 | * aarch64-dis-2.c: Regenerate. | |
220 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
221 | (OP_SVE_BBB): New variant set. | |
222 | (OP_SVE_DDDD): New variant set. | |
223 | (OP_SVE_HHH): New variant set. | |
224 | (OP_SVE_HHHU): New variant set. | |
225 | (OP_SVE_SSS): New variant set. | |
226 | (OP_SVE_SSSU): New variant set. | |
227 | (OP_SVE_SHH): New variant set. | |
228 | (OP_SVE_SBBU): New variant set. | |
229 | (OP_SVE_DSS): New variant set. | |
230 | (OP_SVE_DHHU): New variant set. | |
231 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
232 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
233 | (OP_SVE_VVVU_SD_BH): New variant set. | |
234 | (OP_SVE_VVVU_BHSD): New variant set. | |
235 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
236 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
237 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
238 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
239 | (OP_SVE_VV_BHS_HSD): New variant set. | |
240 | (OP_SVE_VVV_SD): New variant set. | |
241 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
242 | (OP_SVE_VZVV_SD): New variant set. | |
243 | (OP_SVE_VZVV_BH): New variant set. | |
244 | (OP_SVE_VZV_SD): New variant set. | |
245 | (aarch64_opcode_table): Add sve2 instructions. | |
246 | ||
28ed815a MM |
247 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
248 | ||
249 | * aarch64-asm-2.c: Regenerated. | |
250 | * aarch64-dis-2.c: Regenerated. | |
251 | * aarch64-opc-2.c: Regenerated. | |
252 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
253 | for SVE_SHLIMM_UNPRED_22. | |
254 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
255 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
256 | operand. | |
257 | ||
fd1dc4a0 MM |
258 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
259 | ||
260 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
261 | sve_size_tsz_bhs iclass encode. | |
262 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
263 | sve_size_tsz_bhs iclass decode. | |
264 | ||
31e36ab3 MM |
265 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
266 | ||
267 | * aarch64-asm-2.c: Regenerated. | |
268 | * aarch64-dis-2.c: Regenerated. | |
269 | * aarch64-opc-2.c: Regenerated. | |
270 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
271 | for SVE_Zm4_11_INDEX. | |
272 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
273 | (fields): Handle SVE_i2h field. | |
274 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
275 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
276 | ||
1be5f94f MM |
277 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
278 | ||
279 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
280 | sve_shift_tsz_bhsd iclass encode. | |
281 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
282 | sve_shift_tsz_bhsd iclass decode. | |
283 | ||
3c17238b MM |
284 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
285 | ||
286 | * aarch64-asm-2.c: Regenerated. | |
287 | * aarch64-dis-2.c: Regenerated. | |
288 | * aarch64-opc-2.c: Regenerated. | |
289 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
290 | (aarch64_encode_variant_using_iclass): Handle | |
291 | sve_shift_tsz_hsd iclass encode. | |
292 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
293 | sve_shift_tsz_hsd iclass decode. | |
294 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
295 | for SVE_SHRIMM_UNPRED_22. | |
296 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
297 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
298 | operand. | |
299 | ||
cd50a87a MM |
300 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
301 | ||
302 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
303 | sve_size_013 iclass encode. | |
304 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
305 | sve_size_013 iclass decode. | |
306 | ||
3c705960 MM |
307 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
308 | ||
309 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
310 | sve_size_bh iclass encode. | |
311 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
312 | sve_size_bh iclass decode. | |
313 | ||
0a57e14f MM |
314 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
315 | ||
316 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
317 | sve_size_sd2 iclass encode. | |
318 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
319 | sve_size_sd2 iclass decode. | |
320 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
321 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
322 | ||
c469c864 MM |
323 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
324 | ||
325 | * aarch64-asm-2.c: Regenerated. | |
326 | * aarch64-dis-2.c: Regenerated. | |
327 | * aarch64-opc-2.c: Regenerated. | |
328 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
329 | for SVE_ADDR_ZX. | |
330 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
331 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
332 | ||
116adc27 MM |
333 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
334 | ||
335 | * aarch64-asm-2.c: Regenerated. | |
336 | * aarch64-dis-2.c: Regenerated. | |
337 | * aarch64-opc-2.c: Regenerated. | |
338 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
339 | for SVE_Zm3_11_INDEX. | |
340 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
341 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
342 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
343 | fields. | |
344 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
345 | ||
3bd82c86 MM |
346 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
347 | ||
348 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
349 | sve_size_hsd2 iclass encode. | |
350 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
351 | sve_size_hsd2 iclass decode. | |
352 | * aarch64-opc.c (fields): Handle SVE_size field. | |
353 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
354 | ||
adccc507 MM |
355 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
356 | ||
357 | * aarch64-asm-2.c: Regenerated. | |
358 | * aarch64-dis-2.c: Regenerated. | |
359 | * aarch64-opc-2.c: Regenerated. | |
360 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
361 | for SVE_IMM_ROT3. | |
362 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
363 | (fields): Handle SVE_rot3 field. | |
364 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
365 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
366 | ||
5cd99750 MM |
367 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
368 | ||
369 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
370 | instructions. | |
371 | ||
7ce2460a MM |
372 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
373 | ||
374 | * aarch64-tbl.h | |
375 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
376 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
377 | aarch64_feature_sve2bitperm): New feature sets. | |
378 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
379 | for feature set addresses. | |
380 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
381 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
382 | ||
41cee089 FS |
383 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
384 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
385 | ||
386 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
387 | argument and set ASE_EVA_R6 appropriately. | |
388 | (set_default_mips_dis_options): Pass ISA to above. | |
389 | (parse_mips_dis_option): Likewise. | |
390 | * mips-opc.c (EVAR6): New macro. | |
391 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
392 | ||
b83b4b13 SD |
393 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
394 | ||
395 | * aarch64-asm-2.c: Regenerated. | |
396 | * aarch64-dis-2.c: Regenerated. | |
397 | * aarch64-opc-2.c: Regenerated. | |
398 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
399 | AARCH64_OPND_TME_UIMM16. | |
400 | (aarch64_print_operand): Likewise. | |
401 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
402 | (TME): New. | |
403 | (_TME_INSN): New. | |
404 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
405 | ||
4a90ce95 JD |
406 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
407 | ||
408 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
409 | ||
a45328b9 AB |
410 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
411 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
412 | ||
413 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
414 | ||
d10be0cb JD |
415 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
416 | ||
417 | * s12z-opc.h: Add extern "C" bracketing to help | |
418 | users who wish to use this interface in c++ code. | |
419 | ||
a679f24e JD |
420 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
421 | ||
422 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
423 | "reserved0" mode. | |
424 | ||
32c36c3c AV |
425 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
426 | ||
427 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
428 | specifier. Add entries for VLDR and VSTR of system registers. | |
429 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
430 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
431 | of %J and %K format specifier. | |
432 | ||
efd6b359 AV |
433 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
434 | ||
435 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
436 | Add new entries for VSCCLRM instruction. | |
437 | (print_insn_coprocessor): Handle new %C format control code. | |
438 | ||
6b0dd094 AV |
439 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
440 | ||
441 | * arm-dis.c (enum isa): New enum. | |
442 | (struct sopcode32): New structure. | |
443 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
444 | set isa field of all current entries to ANY. | |
445 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
446 | Only match an entry if its isa field allows the current mode. | |
447 | ||
4b5a202f AV |
448 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
449 | ||
450 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
451 | CLRM. | |
452 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
453 | ||
60f993ce AV |
454 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
455 | ||
456 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
457 | and %Q patterns. | |
458 | ||
f6b2b12d AV |
459 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
460 | ||
461 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
462 | (print_insn_thumb32): Edit the switch case for %Z. | |
463 | ||
1889da70 AV |
464 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
465 | ||
466 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
467 | ||
65d1bc05 AV |
468 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
469 | ||
470 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
471 | ||
1caf72a5 AV |
472 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
473 | ||
474 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
475 | ||
f1c7f421 AV |
476 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
477 | ||
478 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
479 | Arm register with r13 and r15 unpredictable. | |
480 | (thumb32_opcodes): New instructions for bfx and bflx. | |
481 | ||
4389b29a AV |
482 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
483 | ||
484 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
485 | ||
e5d6e09e AV |
486 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
487 | ||
488 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
489 | ||
e12437dc AV |
490 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
491 | ||
492 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
493 | ||
031254f2 AV |
494 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
495 | ||
496 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
497 | ||
e5a557ac JD |
498 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
499 | ||
500 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
501 | "optr". ("operator" is a reserved word in c++). | |
502 | ||
bd7ceb8d SD |
503 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
504 | ||
505 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
506 | AARCH64_OPND_Rt_SP. | |
507 | (verify_constraints): Likewise. | |
508 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
509 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
510 | to accept Rt|SP as first operand. | |
511 | (AARCH64_OPERANDS): Add new Rt_SP. | |
512 | * aarch64-asm-2.c: Regenerated. | |
513 | * aarch64-dis-2.c: Regenerated. | |
514 | * aarch64-opc-2.c: Regenerated. | |
515 | ||
e54010f1 SD |
516 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
517 | ||
518 | * aarch64-asm-2.c: Regenerated. | |
519 | * aarch64-dis-2.c: Likewise. | |
520 | * aarch64-opc-2.c: Likewise. | |
521 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
522 | ||
7e96e219 RS |
523 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
524 | ||
525 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
526 | ||
6f2791d5 L |
527 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
528 | ||
529 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
530 | * i386-init.h: Regenerated. | |
531 | ||
e392bad3 AM |
532 | 2019-04-07 Alan Modra <amodra@gmail.com> |
533 | ||
534 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
535 | op_separator to control printing of spaces, comma and parens | |
536 | rather than need_comma, need_paren and spaces vars. | |
537 | ||
dffaa15c AM |
538 | 2019-04-07 Alan Modra <amodra@gmail.com> |
539 | ||
540 | PR 24421 | |
541 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
542 | (print_insn_neon, print_insn_arm): Likewise. | |
543 | ||
d6aab7a1 XG |
544 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
545 | ||
546 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
547 | instructions. | |
548 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
549 | and EVEX_W_0F3872_P_3. | |
550 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
551 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
552 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
553 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
554 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
555 | * i386-init.h: Regenerated. | |
556 | * i386-tbl.h: Likewise. | |
557 | ||
66e85460 AM |
558 | 2019-04-05 Alan Modra <amodra@gmail.com> |
559 | ||
560 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
561 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
562 | to favour printing of "-" branch hint when using the "y" bit. | |
563 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
564 | ||
c2b1c275 AM |
565 | 2019-04-05 Alan Modra <amodra@gmail.com> |
566 | ||
567 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
568 | opcode until first operand is output. | |
569 | ||
aae9718e PB |
570 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
571 | ||
572 | PR gas/24349 | |
573 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
574 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
575 | (insert_bo): Only error on branch on ctr. | |
576 | (get_bo_hint_mask): New function. | |
577 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
578 | for inserting 'at' branch hints. | |
579 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
580 | for extracting 'at' branch hints. | |
581 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
582 | (BOE): Delete operand. | |
583 | (BOM, BOP): New operands. | |
584 | (RM): Update value. | |
585 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
586 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
587 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
588 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
589 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
590 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
591 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
592 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
593 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
594 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
595 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
596 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
597 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
598 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
599 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
600 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
601 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
602 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
603 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
604 | bttarl+>: New extended mnemonics. | |
605 | ||
96a86c01 AM |
606 | 2019-03-28 Alan Modra <amodra@gmail.com> |
607 | ||
608 | PR 24390 | |
609 | * ppc-opc.c (BTF): Define. | |
610 | (powerpc_opcodes): Use for mtfsb*. | |
611 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
612 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
613 | ||
796d6298 TC |
614 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
615 | ||
616 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
617 | (mapping_symbol_for_insn): Implement new algorithm. | |
618 | (print_insn): Remove duplicate code. | |
619 | ||
60df3720 TC |
620 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
621 | ||
622 | * aarch64-dis.c (print_insn_aarch64): | |
623 | Implement override. | |
624 | ||
51457761 TC |
625 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
626 | ||
627 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
628 | order. | |
629 | ||
53b2f36b TC |
630 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
631 | ||
632 | * aarch64-dis.c (last_stop_offset): New. | |
633 | (print_insn_aarch64): Use stop_offset. | |
634 | ||
89199bb5 L |
635 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
636 | ||
637 | PR gas/24359 | |
638 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
639 | CPU_ANY_AVX2_FLAGS. | |
640 | * i386-init.h: Regenerated. | |
641 | ||
97ed31ae L |
642 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
643 | ||
644 | PR gas/24348 | |
645 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
646 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
647 | * i386-tbl.h: Regenerated. | |
648 | ||
0919bfe9 AK |
649 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
650 | ||
651 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
652 | from vstrszb, vstrszh, and vstrszf. | |
653 | ||
654 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
655 | ||
656 | * s390-opc.txt: Add instruction descriptions. | |
657 | ||
21820ebe JW |
658 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
659 | ||
660 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
661 | <bne>: Likewise. | |
662 | ||
f7dd2fb2 TC |
663 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
664 | ||
665 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
666 | ||
6456d318 TC |
667 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
668 | ||
669 | PR binutils/23212 | |
670 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
671 | * aarch64-opc.c (verify_elem_sd): New. | |
672 | (fields): Add FLD_sz entr. | |
673 | * aarch64-tbl.h (_SIMD_INSN): New. | |
674 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
675 | fmulx scalar and vector by element isns. | |
676 | ||
4a83b610 NC |
677 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
678 | ||
679 | * po/sv.po: Updated Swedish translation. | |
680 | ||
fc60b8c8 AK |
681 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
682 | ||
683 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
684 | * s390-opc.c: Add new instruction formats and instruction opcode | |
685 | masks. | |
686 | * s390-opc.txt: Add new arch13 instructions. | |
687 | ||
e10620d3 TC |
688 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
689 | ||
690 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
691 | (aarch64_opcode): Change encoding for stg, stzg | |
692 | st2g and st2zg. | |
693 | * aarch64-asm-2.c: Regenerated. | |
694 | * aarch64-dis-2.c: Regenerated. | |
695 | * aarch64-opc-2.c: Regenerated. | |
696 | ||
20a4ca55 SD |
697 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
698 | ||
699 | * aarch64-asm-2.c: Regenerated. | |
700 | * aarch64-dis-2.c: Likewise. | |
701 | * aarch64-opc-2.c: Likewise. | |
702 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
703 | ||
550fd7bf SD |
704 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
705 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
706 | ||
707 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
708 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
709 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
710 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
711 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
712 | case for ldstgv_indexed. | |
713 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
714 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
715 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
716 | * aarch64-asm-2.c: Regenerated. | |
717 | * aarch64-dis-2.c: Regenerated. | |
718 | * aarch64-opc-2.c: Regenerated. | |
719 | ||
d9938630 NC |
720 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
721 | ||
722 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
723 | ||
375cd423 NC |
724 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
725 | ||
726 | * po/de.po: Updated German translation. | |
727 | * po/uk.po: Updated Ukranian translation. | |
728 | ||
57299f48 CX |
729 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
730 | * mips-dis.c (mips_arch_choices): Fix typo in | |
731 | gs464, gs464e and gs264e descriptors. | |
732 | ||
f48dfe41 NC |
733 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
734 | ||
735 | * configure: Regenerate. | |
736 | * po/opcodes.pot: Regenerate. | |
737 | ||
f974f26c NC |
738 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
739 | ||
740 | 2.32 branch created. | |
741 | ||
39f286cd JD |
742 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
743 | ||
448b8ca8 JD |
744 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
745 | if it is null. | |
746 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
39f286cd JD |
747 | zero. |
748 | ||
3107326d AP |
749 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
750 | ||
751 | * configure: Regenerate. | |
752 | ||
7e9ca91e AM |
753 | 2019-01-07 Alan Modra <amodra@gmail.com> |
754 | ||
755 | * configure: Regenerate. | |
756 | * po/POTFILES.in: Regenerate. | |
757 | ||
ef1ad42b JD |
758 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
759 | ||
760 | * s12z-opc.c: New file. | |
761 | * s12z-opc.h: New file. | |
762 | * s12z-dis.c: Removed all code not directly related to display | |
763 | of instructions. Used the interface provided by the new files | |
764 | instead. | |
765 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
7e9ca91e | 766 | * Makefile.in: Regenerate. |
ef1ad42b | 767 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
7e9ca91e | 768 | * configure: Regenerate. |
ef1ad42b | 769 | |
82704155 AM |
770 | 2019-01-01 Alan Modra <amodra@gmail.com> |
771 | ||
772 | Update year range in copyright notice of all files. | |
773 | ||
d5c04e1b | 774 | For older changes see ChangeLog-2018 |
3499769a | 775 | \f |
d5c04e1b | 776 | Copyright (C) 2019 Free Software Foundation, Inc. |
3499769a AM |
777 | |
778 | Copying and distribution of this file, with or without modification, | |
779 | are permitted in any medium without royalty provided the copyright | |
780 | notice and this notice are preserved. | |
781 | ||
782 | Local Variables: | |
783 | mode: change-log | |
784 | left-margin: 8 | |
785 | fill-column: 74 | |
786 | version-control: never | |
787 | End: |