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S/390: Sync with IBM z14 POP - SI_RD format
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ee6767da
AK		 12017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
2
3 * s390-opc.c (INSTR_SI_RD): New macro.
4 (INSTR_S_RD): Adjust example instruction.
5 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
6 SI_RD.
7
d2e6c9a3
AF		 82017-10-01 Alexander Fedotov <alfedotov@gmail.com>
9
10 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
11 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
12 VLE multimple load/store instructions. Old e_ldm* variants are
13 kept as aliases.
14 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
15
8e43602e
NC		 162017-09-27 Nick Clifton <nickc@redhat.com>
17
18 PR 22179
19 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
20 names for the fmv.x.s and fmv.s.x instructions respectively.
21
58a0b827
NC		 222017-09-26 do <do@nerilex.org>
23
24 PR 22123
25 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
26 be used on CPUs that have emacs support.
27
57a024f4
SDJ		 282017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
29
30 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
31
4ec521f2
KLC		 322017-09-09 Kamil Rytarowski <n54@gmx.com>
33
34 * nds32-asm.c: Rename __BIT() to N32_BIT().
35 * nds32-asm.h: Likewise.
36 * nds32-dis.c: Likewise.
37
4e9ac44a
L		 382017-09-09 H.J. Lu <hongjiu.lu@intel.com>
39
40 * i386-dis.c (last_active_prefix): Removed.
41 (ckprefix): Don't set last_active_prefix.
42 (NOTRACK_Fixup): Don't check last_active_prefix.
43
b55f3386
NC		 442017-08-31 Nick Clifton <nickc@redhat.com>
45
46 * po/fr.po: Updated French translation.
47
59e8523b
JB		 482017-08-31 James Bowman <james.bowman@ftdichip.com>
49
50 * ft32-dis.c (print_insn_ft32): Correct display of non-address
51 fields.
52
74081948
AF		 532017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
54 Edmar Wienskoski <edmar.wienskoski@nxp.com>
55
56 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
57 PPC_OPCODE_EFS2 flag to "e200z4" entry.
58 New entries efs2 and spe2.
59 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
60 (SPE2_OPCD_SEGS): New macro.
61 (spe2_opcd_indices): New.
62 (disassemble_init_powerpc): Handle SPE2 opcodes.
63 (lookup_spe2): New function.
64 (print_insn_powerpc): call lookup_spe2.
65 * ppc-opc.c (insert_evuimm1_ex0): New function.
66 (extract_evuimm1_ex0): Likewise.
67 (insert_evuimm_lt8): Likewise.
68 (extract_evuimm_lt8): Likewise.
69 (insert_off_spe2): Likewise.
70 (extract_off_spe2): Likewise.
71 (insert_Ddd): Likewise.
72 (extract_Ddd): Likewise.
73 (DD): New operand.
74 (EVUIMM_LT8): Likewise.
75 (EVUIMM_LT16): Adjust.
76 (MMMM): New operand.
77 (EVUIMM_1): Likewise.
78 (EVUIMM_1_EX0): Likewise.
79 (EVUIMM_2): Adjust.
80 (NNN): New operand.
81 (VX_OFF_SPE2): Likewise.
82 (BBB): Likewise.
83 (DDD): Likewise.
84 (VX_MASK_DDD): New mask.
85 (HH): New operand.
86 (VX_RA_CONST): New macro.
87 (VX_RA_CONST_MASK): Likewise.
88 (VX_RB_CONST): Likewise.
89 (VX_RB_CONST_MASK): Likewise.
90 (VX_OFF_SPE2_MASK): Likewise.
91 (VX_SPE_CRFD): Likewise.
92 (VX_SPE_CRFD_MASK VX): Likewise.
93 (VX_SPE2_CLR): Likewise.
94 (VX_SPE2_CLR_MASK): Likewise.
95 (VX_SPE2_SPLATB): Likewise.
96 (VX_SPE2_SPLATB_MASK): Likewise.
97 (VX_SPE2_OCTET): Likewise.
98 (VX_SPE2_OCTET_MASK): Likewise.
99 (VX_SPE2_DDHH): Likewise.
100 (VX_SPE2_DDHH_MASK): Likewise.
101 (VX_SPE2_HH): Likewise.
102 (VX_SPE2_HH_MASK): Likewise.
103 (VX_SPE2_EVMAR): Likewise.
104 (VX_SPE2_EVMAR_MASK): Likewise.
105 (PPCSPE2): Likewise.
106 (PPCEFS2): Likewise.
107 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
108 (powerpc_macros): Map old SPE instructions have new names
109 with the same opcodes. Add SPE2 instructions which just are
110 mapped to SPE2.
111 (spe2_opcodes): Add SPE2 opcodes.
112
b80c7270
AM		 1132017-08-23 Alan Modra <amodra@gmail.com>
114
115 * ppc-opc.c: Formatting and comment fixes. Move insert and
116 extract functions earlier, deleting forward declarations.
117 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
118 RA_MASK.
119
67d888f5
PD		 1202017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
121
122 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
123
e3c2f928
AF		 1242017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
125 Edmar Wienskoski <edmar.wienskoski@nxp.com>
126
127 * ppc-opc.c (insert_evuimm2_ex0): New function.
128 (extract_evuimm2_ex0): Likewise.
129 (insert_evuimm4_ex0): Likewise.
130 (extract_evuimm4_ex0): Likewise.
131 (insert_evuimm8_ex0): Likewise.
132 (extract_evuimm8_ex0): Likewise.
133 (insert_evuimm_lt16): Likewise.
134 (extract_evuimm_lt16): Likewise.
135 (insert_rD_rS_even): Likewise.
136 (extract_rD_rS_even): Likewise.
137 (insert_off_lsp): Likewise.
138 (extract_off_lsp): Likewise.
139 (RD_EVEN): New operand.
140 (RS_EVEN): Likewise.
141 (RSQ): Adjust.
142 (EVUIMM_LT16): New operand.
143 (HTM_SI): Adjust.
144 (EVUIMM_2_EX0): New operand.
145 (EVUIMM_4): Adjust.
146 (EVUIMM_4_EX0): New operand.
147 (EVUIMM_8): Adjust.
148 (EVUIMM_8_EX0): New operand.
149 (WS): Adjust.
150 (VX_OFF): New operand.
151 (VX_LSP): New macro.
152 (VX_LSP_MASK): Likewise.
153 (VX_LSP_OFF_MASK): Likewise.
154 (PPC_OPCODE_LSP): Likewise.
155 (vle_opcodes): Add LSP opcodes.
156 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
157
cc4a945a
JW		 1582017-08-09 Jiong Wang <jiong.wang@arm.com>
159
160 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
161 register operands in CRC instructions.
162 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
163 comments.
164
b28b8b5e
L		 1652017-08-07 H.J. Lu <hongjiu.lu@intel.com>
166
167 * disassemble.c (disassembler): Mark big and mach with
168 ATTRIBUTE_UNUSED.
169
e347efc3
MR		 1702017-08-07 Maciej W. Rozycki <macro@imgtec.com>
171
172 * disassemble.c (disassembler): Remove arch/mach/endian
173 assertions.
174
7cbc739c
NC		 1752017-07-25 Nick Clifton <nickc@redhat.com>
176
177 PR 21739
178 * arc-opc.c (insert_rhv2): Use lower case first letter in error
179 message.
180 (insert_r0): Likewise.
181 (insert_r1): Likewise.
182 (insert_r2): Likewise.
183 (insert_r3): Likewise.
184 (insert_sp): Likewise.
185 (insert_gp): Likewise.
186 (insert_pcl): Likewise.
187 (insert_blink): Likewise.
188 (insert_ilink1): Likewise.
189 (insert_ilink2): Likewise.
190 (insert_ras): Likewise.
191 (insert_rbs): Likewise.
192 (insert_rcs): Likewise.
193 (insert_simm3s): Likewise.
194 (insert_rrange): Likewise.
195 (insert_r13el): Likewise.
196 (insert_fpel): Likewise.
197 (insert_blinkel): Likewise.
198 (insert_pclel): Likewise.
199 (insert_nps_bitop_size_2b): Likewise.
200 (insert_nps_imm_offset): Likewise.
201 (insert_nps_imm_entry): Likewise.
202 (insert_nps_size_16bit): Likewise.
203 (insert_nps_##NAME##_pos): Likewise.
204 (insert_nps_##NAME): Likewise.
205 (insert_nps_bitop_ins_ext): Likewise.
206 (insert_nps_##NAME): Likewise.
207 (insert_nps_min_hofs): Likewise.
208 (insert_nps_##NAME): Likewise.
209 (insert_nps_rbdouble_64): Likewise.
210 (insert_nps_misc_imm_offset): Likewise.
211 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
212 option description.
213
7684e580
JW		 2142017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
215 Jiong Wang <jiong.wang@arm.com>
216
217 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
218 correct the print.
219 * aarch64-dis-2.c: Regenerated.
220
47826cdb
AK		 2212017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
222
223 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
224 table.
225
2d2dbad0
NC		 2262017-07-20 Nick Clifton <nickc@redhat.com>
227
228 * po/de.po: Updated German translation.
229
70b448ba 2302017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
231
232 * arc-regs.h (sec_stat): New aux register.
233 (aux_kernel_sp): Likewise.
234 (aux_sec_u_sp): Likewise.
235 (aux_sec_k_sp): Likewise.
236 (sec_vecbase_build): Likewise.
237 (nsc_table_top): Likewise.
238 (nsc_table_base): Likewise.
239 (ersec_stat): Likewise.
240 (aux_sec_except): Likewise.
241
7179e0e6
CZ		 2422017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
243
244 * arc-opc.c (extract_uimm12_20): New function.
245 (UIMM12_20): New operand.
246 (SIMM3_5_S): Adjust.
247 * arc-tbl.h (sjli): Add new instruction.
248
684d5a10
JEM		 2492017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
250 John Eric Martin <John.Martin@emmicro-us.com>
251
252 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
253 (UIMM3_23): Adjust accordingly.
254 * arc-regs.h: Add/correct jli_base register.
255 * arc-tbl.h (jli_s): Likewise.
256
de194d85
YC		 2572017-07-18 Nick Clifton <nickc@redhat.com>
258
259 PR 21775
260 * aarch64-opc.c: Fix spelling typos.
261 * i386-dis.c: Likewise.
262
0f6329bd
RB		 2632017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
264
265 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
266 max_addr_offset and octets variables to size_t.
267
429d795d
AM		 2682017-07-12 Alan Modra <amodra@gmail.com>
269
270 * po/da.po: Update from translationproject.org/latest/opcodes/.
271 * po/de.po: Likewise.
272 * po/es.po: Likewise.
273 * po/fi.po: Likewise.
274 * po/fr.po: Likewise.
275 * po/id.po: Likewise.
276 * po/it.po: Likewise.
277 * po/nl.po: Likewise.
278 * po/pt_BR.po: Likewise.
279 * po/ro.po: Likewise.
280 * po/sv.po: Likewise.
281 * po/tr.po: Likewise.
282 * po/uk.po: Likewise.
283 * po/vi.po: Likewise.
284 * po/zh_CN.po: Likewise.
285
4162bb66
AM		 2862017-07-11 Yao Qi <yao.qi@linaro.org>
287 Alan Modra <amodra@gmail.com>
288
289 * cgen.sh: Mark generated files read-only.
290 * epiphany-asm.c: Regenerate.
291 * epiphany-desc.c: Regenerate.
292 * epiphany-desc.h: Regenerate.
293 * epiphany-dis.c: Regenerate.
294 * epiphany-ibld.c: Regenerate.
295 * epiphany-opc.c: Regenerate.
296 * epiphany-opc.h: Regenerate.
297 * fr30-asm.c: Regenerate.
298 * fr30-desc.c: Regenerate.
299 * fr30-desc.h: Regenerate.
300 * fr30-dis.c: Regenerate.
301 * fr30-ibld.c: Regenerate.
302 * fr30-opc.c: Regenerate.
303 * fr30-opc.h: Regenerate.
304 * frv-asm.c: Regenerate.
305 * frv-desc.c: Regenerate.
306 * frv-desc.h: Regenerate.
307 * frv-dis.c: Regenerate.
308 * frv-ibld.c: Regenerate.
309 * frv-opc.c: Regenerate.
310 * frv-opc.h: Regenerate.
311 * ip2k-asm.c: Regenerate.
312 * ip2k-desc.c: Regenerate.
313 * ip2k-desc.h: Regenerate.
314 * ip2k-dis.c: Regenerate.
315 * ip2k-ibld.c: Regenerate.
316 * ip2k-opc.c: Regenerate.
317 * ip2k-opc.h: Regenerate.
318 * iq2000-asm.c: Regenerate.
319 * iq2000-desc.c: Regenerate.
320 * iq2000-desc.h: Regenerate.
321 * iq2000-dis.c: Regenerate.
322 * iq2000-ibld.c: Regenerate.
323 * iq2000-opc.c: Regenerate.
324 * iq2000-opc.h: Regenerate.
325 * lm32-asm.c: Regenerate.
326 * lm32-desc.c: Regenerate.
327 * lm32-desc.h: Regenerate.
328 * lm32-dis.c: Regenerate.
329 * lm32-ibld.c: Regenerate.
330 * lm32-opc.c: Regenerate.
331 * lm32-opc.h: Regenerate.
332 * lm32-opinst.c: Regenerate.
333 * m32c-asm.c: Regenerate.
334 * m32c-desc.c: Regenerate.
335 * m32c-desc.h: Regenerate.
336 * m32c-dis.c: Regenerate.
337 * m32c-ibld.c: Regenerate.
338 * m32c-opc.c: Regenerate.
339 * m32c-opc.h: Regenerate.
340 * m32r-asm.c: Regenerate.
341 * m32r-desc.c: Regenerate.
342 * m32r-desc.h: Regenerate.
343 * m32r-dis.c: Regenerate.
344 * m32r-ibld.c: Regenerate.
345 * m32r-opc.c: Regenerate.
346 * m32r-opc.h: Regenerate.
347 * m32r-opinst.c: Regenerate.
348 * mep-asm.c: Regenerate.
349 * mep-desc.c: Regenerate.
350 * mep-desc.h: Regenerate.
351 * mep-dis.c: Regenerate.
352 * mep-ibld.c: Regenerate.
353 * mep-opc.c: Regenerate.
354 * mep-opc.h: Regenerate.
355 * mt-asm.c: Regenerate.
356 * mt-desc.c: Regenerate.
357 * mt-desc.h: Regenerate.
358 * mt-dis.c: Regenerate.
359 * mt-ibld.c: Regenerate.
360 * mt-opc.c: Regenerate.
361 * mt-opc.h: Regenerate.
362 * or1k-asm.c: Regenerate.
363 * or1k-desc.c: Regenerate.
364 * or1k-desc.h: Regenerate.
365 * or1k-dis.c: Regenerate.
366 * or1k-ibld.c: Regenerate.
367 * or1k-opc.c: Regenerate.
368 * or1k-opc.h: Regenerate.
369 * or1k-opinst.c: Regenerate.
370 * xc16x-asm.c: Regenerate.
371 * xc16x-desc.c: Regenerate.
372 * xc16x-desc.h: Regenerate.
373 * xc16x-dis.c: Regenerate.
374 * xc16x-ibld.c: Regenerate.
375 * xc16x-opc.c: Regenerate.
376 * xc16x-opc.h: Regenerate.
377 * xstormy16-asm.c: Regenerate.
378 * xstormy16-desc.c: Regenerate.
379 * xstormy16-desc.h: Regenerate.
380 * xstormy16-dis.c: Regenerate.
381 * xstormy16-ibld.c: Regenerate.
382 * xstormy16-opc.c: Regenerate.
383 * xstormy16-opc.h: Regenerate.
384
7639175c
AM		 3852017-07-07 Alan Modra <amodra@gmail.com>
386
387 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
388 * m32c-dis.c: Regenerate.
389 * mep-dis.c: Regenerate.
390
e4bdd679
BP		 3912017-07-05 Borislav Petkov <bp@suse.de>
392
393 * i386-dis.c: Enable ModRM.reg /6 aliases.
394
60c96dbf
RR		 3952017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
396
397 * opcodes/arm-dis.c: Support MVFR2 in disassembly
398 with vmrs and vmsr.
399
0d702cfe
TG		 4002017-07-04 Tristan Gingold <gingold@adacore.com>
401
402 * configure: Regenerate.
403
15e6ed8c
TG		 4042017-07-03 Tristan Gingold <gingold@adacore.com>
405
406 * po/opcodes.pot: Regenerate.
407
b1d3c886
MR		 4082017-06-30 Maciej W. Rozycki <macro@imgtec.com>
409
410 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
411 entries to the MSA ASE instruction block.
412
909b4e3d
MR		 4132017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
414 Maciej W. Rozycki <macro@imgtec.com>
415
416 * micromips-opc.c (XPA, XPAVZ): New macros.
417 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
418 "mthgc0".
419
f5b2fd52
MR		 4202017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
421 Maciej W. Rozycki <macro@imgtec.com>
422
423 * micromips-opc.c (I36): New macro.
424 (micromips_opcodes): Add "eretnc".
425
9785fc2a
MR		 4262017-06-30 Maciej W. Rozycki <macro@imgtec.com>
427 Andrew Bennett <andrew.bennett@imgtec.com>
428
429 * mips-dis.c (mips_calculate_combination_ases): Handle the
430 ASE_XPA_VIRT flag.
431 (parse_mips_ase_option): New function.
432 (parse_mips_dis_option): Factor out ASE option handling to the
433 new function. Call `mips_calculate_combination_ases'.
434 * mips-opc.c (XPAVZ): New macro.
435 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
436 "mfhgc0", "mthc0" and "mthgc0".
437
60804c53
MR		 4382017-06-29 Maciej W. Rozycki <macro@imgtec.com>
439
440 * mips-dis.c (mips_calculate_combination_ases): New function.
441 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
442 calculation to the new function.
443 (set_default_mips_dis_options): Call the new function.
444
2e74f9dd
AK		 4452017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
446
447 * arc-dis.c (parse_disassembler_options): Use
448 FOR_EACH_DISASSEMBLER_OPTION.
449
e1e94c49
AK		 4502017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
451
452 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
453 disassembler option strings.
454 (parse_cpu_option): Likewise.
455
65a55fbb
TC		 4562017-06-28 Tamar Christina <tamar.christina@arm.com>
457
458 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
459 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
460 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
461 (aarch64_feature_dotprod, DOT_INSN): New.
462 (udot, sdot): New.
463 * aarch64-dis-2.c: Regenerated.
464
c604a79a
JW		 4652017-06-28 Jiong Wang <jiong.wang@arm.com>
466
467 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
468
38bf472a
MR		 4692017-06-28 Maciej W. Rozycki <macro@imgtec.com>
470 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 471 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 472
473 * mips-formats.h (INT_BIAS): New macro.
474 (INT_ADJ): Redefine in INT_BIAS terms.
475 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
476 (mips_print_save_restore): New function.
477 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
478 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
479 call.
480 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
481 (print_mips16_insn_arg): Call `mips_print_save_restore' for
482 OP_SAVE_RESTORE_LIST handling, factored out from here.
483 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
484 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
485 (mips_builtin_opcodes): Add "restore" and "save" entries.
486 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
487 (IAMR2): New macro.
488 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
489
9bdfdbf9
AW		 4902017-06-23 Andrew Waterman <andrew@sifive.com>
491
492 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
493 alias; do not mark SLTI instruction as an alias.
494
2234eee6
L		 4952017-06-21 H.J. Lu <hongjiu.lu@intel.com>
496
497 * i386-dis.c (RM_0FAE_REG_5): Removed.
498 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
499 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
500 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
501 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
502 PREFIX_MOD_3_0F01_REG_5_RM_0.
503 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
504 PREFIX_MOD_3_0FAE_REG_5.
505 (mod_table): Update MOD_0FAE_REG_5.
506 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
507 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
508 * i386-tbl.h: Regenerated.
509
c2f76402
L		 5102017-06-21 H.J. Lu <hongjiu.lu@intel.com>
511
512 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
513 * i386-opc.tbl: Likewise.
514 * i386-tbl.h: Regenerated.
515
9fef80d6
L		 5162017-06-21 H.J. Lu <hongjiu.lu@intel.com>
517
518 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
519 and "jmp{&|}".
520 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
521 prefix.
522
0f6d864d
NC		 5232017-06-19 Nick Clifton <nickc@redhat.com>
524
525 PR binutils/21614
526 * score-dis.c (score_opcodes): Add sentinel.
527
e197589b
AM		 5282017-06-16 Alan Modra <amodra@gmail.com>
529
530 * rx-decode.c: Regenerate.
531
0d96e4df
L		 5322017-06-15 H.J. Lu <hongjiu.lu@intel.com>
533
534 PR binutils/21594
535 * i386-dis.c (OP_E_register): Check valid bnd register.
536 (OP_G): Likewise.
537
cd3ea7c6
NC		 5382017-06-15 Nick Clifton <nickc@redhat.com>
539
540 PR binutils/21595
541 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
542 range value.
543
63323b5b
NC		 5442017-06-15 Nick Clifton <nickc@redhat.com>
545
546 PR binutils/21588
547 * rl78-decode.opc (OP_BUF_LEN): Define.
548 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
549 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
550 array.
551 * rl78-decode.c: Regenerate.
552
08c7881b
NC		 5532017-06-15 Nick Clifton <nickc@redhat.com>
554
555 PR binutils/21586
556 * bfin-dis.c (gregs): Clip index to prevent overflow.
557 (regs): Likewise.
558 (regs_lo): Likewise.
559 (regs_hi): Likewise.
560
e64519d1
NC		 5612017-06-14 Nick Clifton <nickc@redhat.com>
562
563 PR binutils/21576
564 * score7-dis.c (score_opcodes): Add sentinel.
565
6394c606
YQ		 5662017-06-14 Yao Qi <yao.qi@linaro.org>
567
568 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
569 * arm-dis.c: Likewise.
570 * ia64-dis.c: Likewise.
571 * mips-dis.c: Likewise.
572 * spu-dis.c: Likewise.
573 * disassemble.h (print_insn_aarch64): New declaration, moved from
574 include/dis-asm.h.
575 (print_insn_big_arm, print_insn_big_mips): Likewise.
576 (print_insn_i386, print_insn_ia64): Likewise.
577 (print_insn_little_arm, print_insn_little_mips): Likewise.
578
db5fa770
NC		 5792017-06-14 Nick Clifton <nickc@redhat.com>
580
581 PR binutils/21587
582 * rx-decode.opc: Include libiberty.h
583 (GET_SCALE): New macro - validates access to SCALE array.
584 (GET_PSCALE): New macro - validates access to PSCALE array.
585 (DIs, SIs, S2Is, rx_disp): Use new macros.
586 * rx-decode.c: Regenerate.
587
05c966f3
AV		 5882017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
589
590 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
591
10045478
AK		 5922017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
593
594 * arc-dis.c (enforced_isa_mask): Declare.
595 (cpu_types): Likewise.
596 (parse_cpu_option): New function.
597 (parse_disassembler_options): Use it.
598 (print_insn_arc): Use enforced_isa_mask.
599 (print_arc_disassembler_options): Document new options.
600
88c1242d
YQ		 6012017-05-24 Yao Qi <yao.qi@linaro.org>
602
603 * alpha-dis.c: Include disassemble.h, don't include
604 dis-asm.h.
605 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
606 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
607 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
608 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
609 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
610 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
611 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
612 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
613 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
614 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
615 * moxie-dis.c, msp430-dis.c, mt-dis.c:
616 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
617 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
618 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
619 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
620 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
621 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
622 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
623 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
624 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
625 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
626 * z80-dis.c, z8k-dis.c: Likewise.
627 * disassemble.h: New file.
628
ab20fa4a
YQ		 6292017-05-24 Yao Qi <yao.qi@linaro.org>
630
631 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
632 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
633
003ca0fd
YQ		 6342017-05-24 Yao Qi <yao.qi@linaro.org>
635
636 * disassemble.c (disassembler): Add arguments a, big and mach.
637 Use them.
638
04ef582a
L		 6392017-05-22 H.J. Lu <hongjiu.lu@intel.com>
640
641 * i386-dis.c (NOTRACK_Fixup): New.
642 (NOTRACK): Likewise.
643 (NOTRACK_PREFIX): Likewise.
644 (last_active_prefix): Likewise.
645 (reg_table): Use NOTRACK on indirect call and jmp.
646 (ckprefix): Set last_active_prefix.
647 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
648 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
649 * i386-opc.h (NoTrackPrefixOk): New.
650 (i386_opcode_modifier): Add notrackprefixok.
651 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
652 Add notrack.
653 * i386-tbl.h: Regenerated.
654
64517994
JM		 6552017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
656
657 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
658 (X_IMM2): Define.
659 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
660 bfd_mach_sparc_v9m8.
661 (print_insn_sparc): Handle new operand types.
662 * sparc-opc.c (MASK_M8): Define.
663 (v6): Add MASK_M8.
664 (v6notlet): Likewise.
665 (v7): Likewise.
666 (v8): Likewise.
667 (v9): Likewise.
668 (v9a): Likewise.
669 (v9b): Likewise.
670 (v9c): Likewise.
671 (v9d): Likewise.
672 (v9e): Likewise.
673 (v9v): Likewise.
674 (v9m): Likewise.
675 (v9andleon): Likewise.
676 (m8): Define.
677 (HWS_VM8): Define.
678 (HWS2_VM8): Likewise.
679 (sparc_opcode_archs): Add entry for "m8".
680 (sparc_opcodes): Add OSA2017 and M8 instructions
681 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
682 fpx{ll,ra,rl}64x,
683 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
684 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
685 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
686 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
687 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
688 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
689 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
690 ASI_CORE_SELECT_COMMIT_NHT.
691
535b785f
AM		 6922017-05-18 Alan Modra <amodra@gmail.com>
693
694 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
695 * aarch64-dis.c: Likewise.
696 * aarch64-gen.c: Likewise.
697 * aarch64-opc.c: Likewise.
698
25499ac7
MR		 6992017-05-15 Maciej W. Rozycki <macro@imgtec.com>
700 Matthew Fortune <matthew.fortune@imgtec.com>
701
702 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
703 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
704 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
705 (print_insn_arg) <OP_REG28>: Add handler.
706 (validate_insn_args) <OP_REG28>: Handle.
707 (print_mips16_insn_arg): Handle MIPS16 instructions that require
708 32-bit encoding and 9-bit immediates.
709 (print_insn_mips16): Handle MIPS16 instructions that require
710 32-bit encoding and MFC0/MTC0 operand decoding.
711 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
712 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
713 (RD_C0, WR_C0, E2, E2MT): New macros.
714 (mips16_opcodes): Add entries for MIPS16e2 instructions:
715 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
716 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
717 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
718 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
719 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
720 instructions, "swl", "swr", "sync" and its "sync_acquire",
721 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
722 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
723 regular/extended entries for original MIPS16 ISA revision
724 instructions whose extended forms are subdecoded in the MIPS16e2
725 ISA revision: "li", "sll" and "srl".
726
fdfb4752
MR		 7272017-05-15 Maciej W. Rozycki <macro@imgtec.com>
728
729 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
730 reference in CP0 move operand decoding.
731
a4f89915
MR		 7322017-05-12 Maciej W. Rozycki <macro@imgtec.com>
733
734 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
735 type to hexadecimal.
736 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
737
99e2d67a
MR		 7382017-05-11 Maciej W. Rozycki <macro@imgtec.com>
739
740 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
741 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
742 "sync_rmb" and "sync_wmb" as aliases.
743 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
744 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
745
53a346d8
CZ		 7462017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
747
748 * arc-dis.c (parse_option): Update quarkse_em option..
749 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
750 QUARKSE1.
751 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
752
f91d48de
KC		 7532017-05-03 Kito Cheng <kito.cheng@gmail.com>
754
755 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
756
43e379d7
MC		 7572017-05-01 Michael Clark <michaeljclark@mac.com>
758
759 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
760 register.
761
a4ddc54e
MR		 7622017-05-02 Maciej W. Rozycki <macro@imgtec.com>
763
764 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
765 and branches and not synthetic data instructions.
766
fe50e98c
BE		 7672017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
768
769 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
770
126124cc
CZ		 7712017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
772
773 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
774 * arc-opc.c (insert_r13el): New function.
775 (R13_EL): Define.
776 * arc-tbl.h: Add new enter/leave variants.
777
be6a24d8
CZ		 7782017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
779
780 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
781
0348fd79
MR		 7822017-04-25 Maciej W. Rozycki <macro@imgtec.com>
783
784 * mips-dis.c (print_mips_disassembler_options): Add
785 `no-aliases'.
786
6e3d1f07
MR		 7872017-04-25 Maciej W. Rozycki <macro@imgtec.com>
788
789 * mips16-opc.c (AL): New macro.
790 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
791 of "ld" and "lw" as aliases.
792
957f6b39
TC		 7932017-04-24 Tamar Christina <tamar.christina@arm.com>
794
795 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
796 arguments.
797
a8cc8a54
AM		 7982017-04-22 Alexander Fedotov <alfedotov@gmail.com>
799 Alan Modra <amodra@gmail.com>
800
801 * ppc-opc.c (ELEV): Define.
802 (vle_opcodes): Add se_rfgi and e_sc.
803 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
804 for E200Z4.
805
3ab87b68
JM		 8062017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
807
808 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
809
792f174f
NC		 8102017-04-21 Nick Clifton <nickc@redhat.com>
811
812 PR binutils/21380
813 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
814 LD3R and LD4R.
815
42742084
AM		 8162017-04-13 Alan Modra <amodra@gmail.com>
817
818 * epiphany-desc.c: Regenerate.
819 * fr30-desc.c: Regenerate.
820 * frv-desc.c: Regenerate.
821 * ip2k-desc.c: Regenerate.
822 * iq2000-desc.c: Regenerate.
823 * lm32-desc.c: Regenerate.
824 * m32c-desc.c: Regenerate.
825 * m32r-desc.c: Regenerate.
826 * mep-desc.c: Regenerate.
827 * mt-desc.c: Regenerate.
828 * or1k-desc.c: Regenerate.
829 * xc16x-desc.c: Regenerate.
830 * xstormy16-desc.c: Regenerate.
831
9a85b496
AM		 8322017-04-11 Alan Modra <amodra@gmail.com>
833
ef85eab0 834 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 835 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
836 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 837 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
838 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 839 (PPCVSX2): Define as PPC_OPCODE_POWER8.
840 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 841 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 842 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 843
62adc510
AM		 8442017-04-10 Alan Modra <amodra@gmail.com>
845
846 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
847 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
848 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
849 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
850
aa808707
PC		 8512017-04-09 Pip Cet <pipcet@gmail.com>
852
853 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
854 appropriate floating-point precision directly.
855
ac8f0f72
AM		 8562017-04-07 Alan Modra <amodra@gmail.com>
857
858 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
859 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
860 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
861 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
862 vector instructions with E6500 not PPCVEC2.
863
62ecb94c
PC		 8642017-04-06 Pip Cet <pipcet@gmail.com>
865
866 * Makefile.am: Add wasm32-dis.c.
867 * configure.ac: Add wasm32-dis.c to wasm32 target.
868 * disassemble.c: Add wasm32 disassembler code.
869 * wasm32-dis.c: New file.
870 * Makefile.in: Regenerate.
871 * configure: Regenerate.
872 * po/POTFILES.in: Regenerate.
873 * po/opcodes.pot: Regenerate.
874
f995bbe8
PA		 8752017-04-05 Pedro Alves <palves@redhat.com>
876
877 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
878 * arm-dis.c (parse_arm_disassembler_options): Constify.
879 * ppc-dis.c (powerpc_init_dialect): Constify local.
880 * vax-dis.c (parse_disassembler_options): Constify.
881
b5292032
PD		 8822017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
883
884 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
885 RISCV_GP_SYMBOL.
886
f96bd6c2
PC		 8872017-03-30 Pip Cet <pipcet@gmail.com>
888
889 * configure.ac: Add (empty) bfd_wasm32_arch target.
890 * configure: Regenerate
891 * po/opcodes.pot: Regenerate.
892
f7c514a3
JM		 8932017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
894
895 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
896 OSA2015.
897 * opcodes/sparc-opc.c (asi_table): New ASIs.
898
52be03fd
AM		 8992017-03-29 Alan Modra <amodra@gmail.com>
900
901 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
902 "raw" option.
903 (lookup_powerpc): Don't special case -1 dialect. Handle
904 PPC_OPCODE_RAW.
905 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
906 lookup_powerpc call, pass it on second.
907
9b753937
AM		 9082017-03-27 Alan Modra <amodra@gmail.com>
909
910 PR 21303
911 * ppc-dis.c (struct ppc_mopt): Comment.
912 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
913
c0c31e91
RZ		 9142017-03-27 Rinat Zelig <rinat@mellanox.com>
915
916 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
917 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
918 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
919 (insert_nps_misc_imm_offset): New function.
920 (extract_nps_misc imm_offset): New function.
921 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
922 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
923
2253c8f0
AK		 9242017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
925
926 * s390-mkopc.c (main): Remove vx2 check.
927 * s390-opc.txt: Remove vx2 instruction flags.
928
645d3342
RZ		 9292017-03-21 Rinat Zelig <rinat@mellanox.com>
930
931 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
932 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
933 (insert_nps_imm_offset): New function.
934 (extract_nps_imm_offset): New function.
935 (insert_nps_imm_entry): New function.
936 (extract_nps_imm_entry): New function.
937
4b94dd2d
AM		 9382017-03-17 Alan Modra <amodra@gmail.com>
939
940 PR 21248
941 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
942 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
943 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
944
b416fe87
KC		 9452017-03-14 Kito Cheng <kito.cheng@gmail.com>
946
947 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
948 <c.andi>: Likewise.
949 <c.addiw> Likewise.
950
03b039a5
KC		 9512017-03-14 Kito Cheng <kito.cheng@gmail.com>
952
953 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
954
2c232b83
AW		 9552017-03-13 Andrew Waterman <andrew@sifive.com>
956
957 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
958 <srl> Likewise.
959 <srai> Likewise.
960 <sra> Likewise.
961
86fa6981
L		 9622017-03-09 H.J. Lu <hongjiu.lu@intel.com>
963
964 * i386-gen.c (opcode_modifiers): Replace S with Load.
965 * i386-opc.h (S): Removed.
966 (Load): New.
967 (i386_opcode_modifier): Replace s with load.
968 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
969 and {evex}. Replace S with Load.
970 * i386-tbl.h: Regenerated.
971
c1fe188b
L		 9722017-03-09 H.J. Lu <hongjiu.lu@intel.com>
973
974 * i386-opc.tbl: Use CpuCET on rdsspq.
975 * i386-tbl.h: Regenerated.
976
4b8b687e
PB		 9772017-03-08 Peter Bergner <bergner@vnet.ibm.com>
978
979 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
980 <vsx>: Do not use PPC_OPCODE_VSX3;
981
1437d063
PB		 9822017-03-08 Peter Bergner <bergner@vnet.ibm.com>
983
984 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
985
603555e5
L		 9862017-03-06 H.J. Lu <hongjiu.lu@intel.com>
987
988 * i386-dis.c (REG_0F1E_MOD_3): New enum.
989 (MOD_0F1E_PREFIX_1): Likewise.
990 (MOD_0F38F5_PREFIX_2): Likewise.
991 (MOD_0F38F6_PREFIX_0): Likewise.
992 (RM_0F1E_MOD_3_REG_7): Likewise.
993 (PREFIX_MOD_0_0F01_REG_5): Likewise.
994 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
995 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
996 (PREFIX_0F1E): Likewise.
997 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
998 (PREFIX_0F38F5): Likewise.
999 (dis386_twobyte): Use PREFIX_0F1E.
1000 (reg_table): Add REG_0F1E_MOD_3.
1001 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1002 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1003 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1004 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1005 (three_byte_table): Use PREFIX_0F38F5.
1006 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1007 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1008 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1009 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1010 PREFIX_MOD_3_0F01_REG_5_RM_2.
1011 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1012 (cpu_flags): Add CpuCET.
1013 * i386-opc.h (CpuCET): New enum.
1014 (CpuUnused): Commented out.
1015 (i386_cpu_flags): Add cpucet.
1016 * i386-opc.tbl: Add Intel CET instructions.
1017 * i386-init.h: Regenerated.
1018 * i386-tbl.h: Likewise.
1019
73f07bff
AM		 10202017-03-06 Alan Modra <amodra@gmail.com>
1021
1022 PR 21124
1023 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1024 (extract_raq, extract_ras, extract_rbx): New functions.
1025 (powerpc_operands): Use opposite corresponding insert function.
1026 (Q_MASK): Define.
1027 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1028 register restriction.
1029
65b48a81
PB		 10302017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1031
1032 * disassemble.c Include "safe-ctype.h".
1033 (disassemble_init_for_target): Handle s390 init.
1034 (remove_whitespace_and_extra_commas): New function.
1035 (disassembler_options_cmp): Likewise.
1036 * arm-dis.c: Include "libiberty.h".
1037 (NUM_ELEM): Delete.
1038 (regnames): Use long disassembler style names.
1039 Add force-thumb and no-force-thumb options.
1040 (NUM_ARM_REGNAMES): Rename from this...
1041 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1042 (get_arm_regname_num_options): Delete.
1043 (set_arm_regname_option): Likewise.
1044 (get_arm_regnames): Likewise.
1045 (parse_disassembler_options): Likewise.
1046 (parse_arm_disassembler_option): Rename from this...
1047 (parse_arm_disassembler_options): ...to this. Make static.
1048 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1049 (print_insn): Use parse_arm_disassembler_options.
1050 (disassembler_options_arm): New function.
1051 (print_arm_disassembler_options): Handle updated regnames.
1052 * ppc-dis.c: Include "libiberty.h".
1053 (ppc_opts): Add "32" and "64" entries.
1054 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1055 (powerpc_init_dialect): Add break to switch statement.
1056 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1057 (disassembler_options_powerpc): New function.
1058 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1059 Remove printing of "32" and "64".
1060 * s390-dis.c: Include "libiberty.h".
1061 (init_flag): Remove unneeded variable.
1062 (struct s390_options_t): New structure type.
1063 (options): New structure.
1064 (init_disasm): Rename from this...
1065 (disassemble_init_s390): ...to this. Add initializations for
1066 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1067 (print_insn_s390): Delete call to init_disasm.
1068 (disassembler_options_s390): New function.
1069 (print_s390_disassembler_options): Print using information from
1070 struct 'options'.
1071 * po/opcodes.pot: Regenerate.
1072
15c7c1d8
JB		 10732017-02-28 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-dis.c (PCMPESTR_Fixup): New.
1076 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1077 (prefix_table): Use PCMPESTR_Fixup.
1078 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1079 PCMPESTR_Fixup.
1080 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1081 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1082 Split 64-bit and non-64-bit variants.
1083 * opcodes/i386-tbl.h: Re-generate.
1084
582e12bf
RS		 10852017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1086
1087 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1088 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1089 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1090 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1091 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1092 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1093 (OP_SVE_V_HSD): New macros.
1094 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1095 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1096 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1097 (aarch64_opcode_table): Add new SVE instructions.
1098 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1099 for rotation operands. Add new SVE operands.
1100 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1101 (ins_sve_quad_index): Likewise.
1102 (ins_imm_rotate): Split into...
1103 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1104 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1105 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1106 functions.
1107 (aarch64_ins_sve_addr_ri_s4): New function.
1108 (aarch64_ins_sve_quad_index): Likewise.
1109 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1110 * aarch64-asm-2.c: Regenerate.
1111 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1112 (ext_sve_quad_index): Likewise.
1113 (ext_imm_rotate): Split into...
1114 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1115 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1116 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1117 functions.
1118 (aarch64_ext_sve_addr_ri_s4): New function.
1119 (aarch64_ext_sve_quad_index): Likewise.
1120 (aarch64_ext_sve_index): Allow quad indices.
1121 (do_misc_decoding): Likewise.
1122 * aarch64-dis-2.c: Regenerate.
1123 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1124 aarch64_field_kinds.
1125 (OPD_F_OD_MASK): Widen by one bit.
1126 (OPD_F_NO_ZR): Bump accordingly.
1127 (get_operand_field_width): New function.
1128 * aarch64-opc.c (fields): Add new SVE fields.
1129 (operand_general_constraint_met_p): Handle new SVE operands.
1130 (aarch64_print_operand): Likewise.
1131 * aarch64-opc-2.c: Regenerate.
1132
f482d304
RS		 11332017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1134
1135 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1136 (aarch64_feature_compnum): ...this.
1137 (SIMD_V8_3): Replace with...
1138 (COMPNUM): ...this.
1139 (CNUM_INSN): New macro.
1140 (aarch64_opcode_table): Use it for the complex number instructions.
1141
7db2c588
JB		 11422017-02-24 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1145
1e9d41d4
SL		 11462017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1147
1148 Add support for associating SPARC ASIs with an architecture level.
1149 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1150 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1151 decoding of SPARC ASIs.
1152
53c4d625
JB		 11532017-02-23 Jan Beulich <jbeulich@suse.com>
1154
1155 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1156 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1157
11648de5
JB		 11582017-02-21 Jan Beulich <jbeulich@suse.com>
1159
1160 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1161 1 (instead of to itself). Correct typo.
1162
f98d33be
AW		 11632017-02-14 Andrew Waterman <andrew@sifive.com>
1164
1165 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1166 pseudoinstructions.
1167
773fb663
RS		 11682017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1169
1170 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1171 (aarch64_sys_reg_supported_p): Handle them.
1172
cc07cda6
CZ		 11732017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1174
1175 * arc-opc.c (UIMM6_20R): Define.
1176 (SIMM12_20): Use above.
1177 (SIMM12_20R): Define.
1178 (SIMM3_5_S): Use above.
1179 (UIMM7_A32_11R_S): Define.
1180 (UIMM7_9_S): Use above.
1181 (UIMM3_13R_S): Define.
1182 (SIMM11_A32_7_S): Use above.
1183 (SIMM9_8R): Define.
1184 (UIMM10_A32_8_S): Use above.
1185 (UIMM8_8R_S): Define.
1186 (W6): Use above.
1187 (arc_relax_opcodes): Use all above defines.
1188
66a5a740
VG		 11892017-02-15 Vineet Gupta <vgupta@synopsys.com>
1190
1191 * arc-regs.h: Distinguish some of the registers different on
1192 ARC700 and HS38 cpus.
1193
7e0de605
AM		 11942017-02-14 Alan Modra <amodra@gmail.com>
1195
1196 PR 21118
1197 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1198 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1199
54064fdb
AM		 12002017-02-11 Stafford Horne <shorne@gmail.com>
1201 Alan Modra <amodra@gmail.com>
1202
1203 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1204 Use insn_bytes_value and insn_int_value directly instead. Don't
1205 free allocated memory until function exit.
1206
dce75bf9
NP		 12072017-02-10 Nicholas Piggin <npiggin@gmail.com>
1208
1209 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1210
1b7e3d2f
NC		 12112017-02-03 Nick Clifton <nickc@redhat.com>
1212
1213 PR 21096
1214 * aarch64-opc.c (print_register_list): Ensure that the register
1215 list index will fir into the tb buffer.
1216 (print_register_offset_address): Likewise.
1217 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1218
8ec5cf65
AD		 12192017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1220
1221 PR 21056
1222 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1223 instructions when the previous fetch packet ends with a 32-bit
1224 instruction.
1225
a1aa5e81
DD		 12262017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1227
1228 * pru-opc.c: Remove vague reference to a future GDB port.
1229
add3afb2
NC		 12302017-01-20 Nick Clifton <nickc@redhat.com>
1231
1232 * po/ga.po: Updated Irish translation.
1233
c13a63b0
SN		 12342017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1235
1236 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1237
9608051a
YQ		 12382017-01-13 Yao Qi <yao.qi@linaro.org>
1239
1240 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1241 if FETCH_DATA returns 0.
1242 (m68k_scan_mask): Likewise.
1243 (print_insn_m68k): Update code to handle -1 return value.
1244
f622ea96
YQ		 12452017-01-13 Yao Qi <yao.qi@linaro.org>
1246
1247 * m68k-dis.c (enum print_insn_arg_error): New.
1248 (NEXTBYTE): Replace -3 with
1249 PRINT_INSN_ARG_MEMORY_ERROR.
1250 (NEXTULONG): Likewise.
1251 (NEXTSINGLE): Likewise.
1252 (NEXTDOUBLE): Likewise.
1253 (NEXTDOUBLE): Likewise.
1254 (NEXTPACKED): Likewise.
1255 (FETCH_ARG): Likewise.
1256 (FETCH_DATA): Update comments.
1257 (print_insn_arg): Update comments. Replace magic numbers with
1258 enum.
1259 (match_insn_m68k): Likewise.
1260
620214f7
IT		 12612017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1262
1263 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1264 * i386-dis-evex.h (evex_table): Updated.
1265 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1266 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1267 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1268 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1269 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1270 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1271 * i386-init.h: Regenerate.
1272 * i386-tbl.h: Ditto.
1273
d95014a2
YQ		 12742017-01-12 Yao Qi <yao.qi@linaro.org>
1275
1276 * msp430-dis.c (msp430_singleoperand): Return -1 if
1277 msp430dis_opcode_signed returns false.
1278 (msp430_doubleoperand): Likewise.
1279 (msp430_branchinstr): Return -1 if
1280 msp430dis_opcode_unsigned returns false.
1281 (msp430x_calla_instr): Likewise.
1282 (print_insn_msp430): Likewise.
1283
0ae60c3e
NC		 12842017-01-05 Nick Clifton <nickc@redhat.com>
1285
1286 PR 20946
1287 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1288 could not be matched.
1289 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1290 NULL.
1291
d74d4880
SN		 12922017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1293
1294 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1295 (aarch64_opcode_table): Use RCPC_INSN.
1296
cc917fd9
KC		 12972017-01-03 Kito Cheng <kito.cheng@gmail.com>
1298
1299 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1300 extension.
1301 * riscv-opcodes/all-opcodes: Likewise.
1302
b52d3cfc
DP		 13032017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1304
1305 * riscv-dis.c (print_insn_args): Add fall through comment.
1306
f90c58d5
NC		 13072017-01-03 Nick Clifton <nickc@redhat.com>
1308
1309 * po/sr.po: New Serbian translation.
1310 * configure.ac (ALL_LINGUAS): Add sr.
1311 * configure: Regenerate.
1312
f47b0d4a
AM		 13132017-01-02 Alan Modra <amodra@gmail.com>
1314
1315 * epiphany-desc.h: Regenerate.
1316 * epiphany-opc.h: Regenerate.
1317 * fr30-desc.h: Regenerate.
1318 * fr30-opc.h: Regenerate.
1319 * frv-desc.h: Regenerate.
1320 * frv-opc.h: Regenerate.
1321 * ip2k-desc.h: Regenerate.
1322 * ip2k-opc.h: Regenerate.
1323 * iq2000-desc.h: Regenerate.
1324 * iq2000-opc.h: Regenerate.
1325 * lm32-desc.h: Regenerate.
1326 * lm32-opc.h: Regenerate.
1327 * m32c-desc.h: Regenerate.
1328 * m32c-opc.h: Regenerate.
1329 * m32r-desc.h: Regenerate.
1330 * m32r-opc.h: Regenerate.
1331 * mep-desc.h: Regenerate.
1332 * mep-opc.h: Regenerate.
1333 * mt-desc.h: Regenerate.
1334 * mt-opc.h: Regenerate.
1335 * or1k-desc.h: Regenerate.
1336 * or1k-opc.h: Regenerate.
1337 * xc16x-desc.h: Regenerate.
1338 * xc16x-opc.h: Regenerate.
1339 * xstormy16-desc.h: Regenerate.
1340 * xstormy16-opc.h: Regenerate.
1341
2571583a
AM		 13422017-01-02 Alan Modra <amodra@gmail.com>
1343
1344 Update year range in copyright notice of all files.
1345
5c1ad6b5 1346For older changes see ChangeLog-2016
3499769a 1347\f
5c1ad6b5 1348Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1349
1350Copying and distribution of this file, with or without modification,
1351are permitted in any medium without royalty provided the copyright
1352notice and this notice are preserved.
1353
1354Local Variables:
1355mode: change-log
1356left-margin: 8
1357fill-column: 74
1358version-control: never
1359End:
GDB Binutils - Deliverables
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