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MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
353abf7c
MR		 12016-12-14 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
4 `pinfo2' with SP-relative "sd" entries.
5
63e014fc
MR		 62016-12-14 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
9 compact jumps.
10
a6a51754
RL		 112016-12-13 Renlin Li <renlin.li@arm.com>
12
13 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
14 qualifier.
15 (operand_general_constraint_met_p): Remove case for CP_REG.
16 (aarch64_print_operand): Print CRn, CRm operand using imm field.
17 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
18 (QL_SYSL): Likewise.
19 (aarch64_opcode_table): Change CRn, CRm operand class and type.
20 * aarch64-opc-2.c : Regenerate.
21 * aarch64-asm-2.c : Likewise.
22 * aarch64-dis-2.c : Likewise.
23
029e9d52
YQ		 242016-12-12 Yao Qi <yao.qi@linaro.org>
25
26 * rx-dis.c: Include <setjmp.h>
27 (struct private): New.
28 (rx_get_byte): Check return value of read_memory_func, and
29 call memory_error_func and OPCODES_SIGLONGJMP on error.
30 (print_insn_rx): Call OPCODES_SIGSETJMP.
31
3a0b8f7d
YQ		 322016-12-12 Yao Qi <yao.qi@linaro.org>
33
34 * rl78-dis.c: Include <setjmp.h>.
35 (struct private): New.
36 (rl78_get_byte): Check return value of read_memory_func, and
37 call memory_error_func and OPCODES_SIGLONGJMP on error.
38 (print_insn_rl78_common): Call OPCODES_SIGJMP.
39
64c11183
MR		 402016-12-09 Maciej W. Rozycki <macro@imgtec.com>
41
42 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
43
f17ecb4b
MR		 442016-12-09 Maciej W. Rozycki <macro@imgtec.com>
45
46 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
47 than UINT.
48
55af4784
MR		 492016-12-09 Maciej W. Rozycki <macro@imgtec.com>
50
51 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
52 to separate `extend' and its uninterpreted argument output.
53 Separate hexadecimal halves of undecoded extended instructions
54 output.
55
39f66f3a
MR		 562016-12-08 Maciej W. Rozycki <macro@imgtec.com>
57
58 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
59 indentation space across.
60
860b03a8
MR		 612016-12-08 Maciej W. Rozycki <macro@imgtec.com>
62
63 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
64 adjustment for PC-relative operations following MIPS16e compact
65 jumps or undefined RR/J(AL)R(C) encodings.
66
329d01f7
MR		 672016-12-08 Maciej W. Rozycki <macro@imgtec.com>
68
69 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
70 variable to `reglane_index'.
71
3a2488dd
LM		 722016-12-08 Luis Machado <lgustavo@codesourcery.com>
73
74 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
75
5f5c6e03
MR		 762016-12-07 Maciej W. Rozycki <macro@imgtec.com>
77
78 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
79
343fa690
MR		 802016-12-07 Maciej W. Rozycki <macro@imgtec.com>
81
82 * mips16-opc.c (mips16_opcodes): Update comment naming structure
83 members.
84
6725647c
MR		 852016-12-07 Maciej W. Rozycki <macro@imgtec.com>
86
87 * mips-dis.c (print_mips_disassembler_options): Reformat output.
88
c28eeff2
SN		 892016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
90
91 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
92 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
93
49e8a725
SN		 942016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
95
96 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
97
a37a2806
NC		 982016-12-01 Nick Clifton <nickc@redhat.com>
99
100 PR binutils/20893
101 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
102 opcode designator.
103
abe7c33b
CZ		 1042016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
105
106 * arc-opc.c (insert_ra_chk): New function.
107 (insert_rb_chk): Likewise.
108 (insert_rad): Update text error message.
109 (insert_rcd): Likewise.
110 (insert_rhv2): Likewise.
111 (insert_r0): Likewise.
112 (insert_r1): Likewise.
113 (insert_r2): Likewise.
114 (insert_r3): Likewise.
115 (insert_sp): Likewise.
116 (insert_gp): Likewise.
117 (insert_pcl): Likewise.
118 (insert_blink): Likewise.
119 (insert_ilink1): Likewise.
120 (insert_ilink2): Likewise.
121 (insert_ras): Likewise.
122 (insert_rbs): Likewise.
123 (insert_rcs): Likewise.
124 (insert_simm3s): Likewise.
125 (insert_rrange): Likewise.
126 (insert_fpel): Likewise.
127 (insert_blinkel): Likewise.
128 (insert_pcel): Likewise.
129 (insert_nps_3bit_dst): Likewise.
130 (insert_nps_3bit_dst_short): Likewise.
131 (insert_nps_3bit_src2_short): Likewise.
132 (insert_nps_bitop_size_2b): Likewise.
133 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
134 (RA_CHK): Define.
135 (RB): Adjust.
136 (RB_CHK): Define.
137 (RC): Adjust.
138 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
139 * arc-tbl.h (div, divu): All instructions are DIVREM class.
140 Change first insn argument to check for LP_COUNT usage.
141 (rem): Likewise.
142 (ld, ldd): All instructions are LOAD class. Change first insn
143 argument to check for LP_COUNT usage.
144 (st, std): All instructions are STORE class.
145 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
146 Change first insn argument to check for LP_COUNT usage.
147 (mov): All instructions are MOVE class. Change first insn
148 argument to check for LP_COUNT usage.
149
ee881e5d
CZ		 1502016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
151
152 * arc-dis.c (is_compatible_p): Remove function.
153 (skip_this_opcode): Don't add any decoding class to decode list.
154 Remove warning.
155 (find_format_from_table): Go through all opcodes, and warn if we
156 use a guessed mnemonic.
157
abfcb414
AP		 1582016-11-28 Ramiro Polla <ramiro@hex-rays.com>
159 Amit Pawar <amit.pawar@amd.com>
160
161 PR binutils/20637
162 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
163 instructions.
164
96fe4562
AM		 1652016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
166
167 * configure: Regenerate.
168
6884417a
JM		 1692016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
170
171 * sparc-opc.c (HWS_V8): Definition moved from
172 gas/config/tc-sparc.c.
173 (HWS_V9): Likewise.
174 (HWS_VA): Likewise.
175 (HWS_VB): Likewise.
176 (HWS_VC): Likewise.
177 (HWS_VD): Likewise.
178 (HWS_VE): Likewise.
179 (HWS_VV): Likewise.
180 (HWS_VM): Likewise.
181 (HWS2_VM): Likewise.
182 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
183 existing entries.
184
c4b943d7
CZ		 1852016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
186
187 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
188 instructions.
189
c2c4ff8d
SN		 1902016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
191
192 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
193 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
194 (aarch64_opcode_table): Add fcmla and fcadd.
195 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
196 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
197 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
198 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
199 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
200 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
201 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
202 (operand_general_constraint_met_p): Rotate and index range check.
203 (aarch64_print_operand): Handle rotate operand.
204 * aarch64-asm-2.c: Regenerate.
205 * aarch64-dis-2.c: Likewise.
206 * aarch64-opc-2.c: Likewise.
207
28617675
SN		 2082016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
209
210 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
211 * aarch64-asm-2.c: Regenerate.
212 * aarch64-dis-2.c: Regenerate.
213 * aarch64-opc-2.c: Regenerate.
214
ccfc90a3
SN		 2152016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
216
217 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
218 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
219 * aarch64-asm-2.c: Regenerate.
220 * aarch64-dis-2.c: Regenerate.
221 * aarch64-opc-2.c: Regenerate.
222
3f06e550
SN		 2232016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
224
225 * aarch64-tbl.h (QL_X1NIL): New.
226 (arch64_opcode_table): Add ldraa, ldrab.
227 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
228 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
229 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
230 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
231 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
232 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
233 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
234 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
235 (aarch64_print_operand): Likewise.
236 * aarch64-asm-2.c: Regenerate.
237 * aarch64-dis-2.c: Regenerate.
238 * aarch64-opc-2.c: Regenerate.
239
74f5402d
SN		 2402016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
241
242 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
243 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
244 * aarch64-asm-2.c: Regenerate.
245 * aarch64-dis-2.c: Regenerate.
246 * aarch64-opc-2.c: Regenerate.
247
c84364ec
SN		 2482016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
249
250 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
251 (AARCH64_OPERANDS): Add Rm_SP.
252 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
253 * aarch64-asm-2.c: Regenerate.
254 * aarch64-dis-2.c: Regenerate.
255 * aarch64-opc-2.c: Regenerate.
256
a2cfc830
SN		 2572016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
258
259 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
260 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
261 autdzb, xpaci, xpacd.
262 * aarch64-asm-2.c: Regenerate.
263 * aarch64-dis-2.c: Regenerate.
264 * aarch64-opc-2.c: Regenerate.
265
b0bfa7b5
SN		 2662016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
267
268 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
269 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
270 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
271 (aarch64_sys_reg_supported_p): Add feature test for new registers.
272
8787d804
SN		 2732016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
274
275 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
276 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
277 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
278 autibsp.
279 * aarch64-asm-2.c: Regenerate.
280 * aarch64-dis-2.c: Regenerate.
281
3d731f69
SN		 2822016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
283
284 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
285
60227d64
L		 2862016-11-09 H.J. Lu <hongjiu.lu@intel.com>
287
288 PR binutils/20799
289 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
290 * i386-dis.c (EdqwS): Removed.
291 (dqw_swap_mode): Likewise.
292 (intel_operand_size): Don't check dqw_swap_mode.
293 (OP_E_register): Likewise.
294 (OP_E_memory): Likewise.
295 (OP_G): Likewise.
296 (OP_EX): Likewise.
297 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
298 * i386-tbl.h: Regerated.
299
7efeed17
L		 3002016-11-09 H.J. Lu <hongjiu.lu@intel.com>
301
302 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 303 * i386-tbl.h: Regerated.
7efeed17 304
1f334aeb
L		 3052016-11-08 H.J. Lu <hongjiu.lu@intel.com>
306
307 PR binutils/20701
308 * i386-dis.c (THREE_BYTE_0F7A): Removed.
309 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
310 (three_byte_table): Remove THREE_BYTE_0F7A.
311
48c97fa1
L		 3122016-11-07 H.J. Lu <hongjiu.lu@intel.com>
313
314 PR binutils/20775
315 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
316 (FGRPd9_4): Replace 1 with 2.
317 (FGRPd9_5): Replace 2 with 3.
318 (FGRPd9_6): Replace 3 with 4.
319 (FGRPd9_7): Replace 4 with 5.
320 (FGRPda_5): Replace 5 with 6.
321 (FGRPdb_4): Replace 6 with 7.
322 (FGRPde_3): Replace 7 with 8.
323 (FGRPdf_4): Replace 8 with 9.
324 (fgrps): Add an entry for Bad_Opcode.
325
b437d035
AB		 3262016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
327
328 * arc-opc.c (arc_flag_operands): Add F_DI14.
329 (arc_flag_classes): Add C_DI14.
330 * arc-nps400-tbl.h: Add new exc instructions.
331
5a736821
GM		 3322016-11-03 Graham Markall <graham.markall@embecosm.com>
333
334 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
335 major opcode 0xa.
336 * arc-nps-400-tbl.h: Add dcmac instruction.
337 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
338 (insert_nps_rbdouble_64): Added.
339 (extract_nps_rbdouble_64): Added.
340 (insert_nps_proto_size): Added.
341 (extract_nps_proto_size): Added.
342
bdfe53e3
AB		 3432016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
344
345 * arc-dis.c (struct arc_operand_iterator): Remove all fields
346 relating to long instruction processing, add new limm field.
347 (OPCODE): Rename to...
348 (OPCODE_32BIT_INSN): ...this.
349 (OPCODE_AC): Delete.
350 (skip_this_opcode): Handle different instruction lengths, update
351 macro name.
352 (special_flag_p): Update parameter type.
353 (find_format_from_table): Update for more instruction lengths.
354 (find_format_long_instructions): Delete.
355 (find_format): Update for more instruction lengths.
356 (arc_insn_length): Likewise.
357 (extract_operand_value): Update for more instruction lengths.
358 (operand_iterator_next): Remove code relating to long
359 instructions.
360 (arc_opcode_to_insn_type): New function.
361 (print_insn_arc):Update for more instructions lengths.
362 * arc-ext.c (extInstruction_t): Change argument type.
363 * arc-ext.h (extInstruction_t): Change argument type.
364 * arc-fxi.h: Change type unsigned to unsigned long long
365 extensively throughout.
366 * arc-nps400-tbl.h: Add long instructions taken from
367 arc_long_opcodes table in arc-opc.c.
368 * arc-opc.c: Update parameter types on insert/extract handlers.
369 (arc_long_opcodes): Delete.
370 (arc_num_long_opcodes): Delete.
371 (arc_opcode_len): Update for more instruction lengths.
372
90f61cce
GM		 3732016-11-03 Graham Markall <graham.markall@embecosm.com>
374
375 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
376
06fe285f
GM		 3772016-11-03 Graham Markall <graham.markall@embecosm.com>
378
379 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
380 with arc_opcode_len.
381 (find_format_long_instructions): Likewise.
382 * arc-opc.c (arc_opcode_len): New function.
383
ecf64ec6
AB		 3842016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
385
386 * arc-nps400-tbl.h: Fix some instruction masks.
387
d039fef3
L		 3882016-11-03 H.J. Lu <hongjiu.lu@intel.com>
389
390 * i386-dis.c (REG_82): Removed.
391 (X86_64_82_REG_0): Likewise.
392 (X86_64_82_REG_1): Likewise.
393 (X86_64_82_REG_2): Likewise.
394 (X86_64_82_REG_3): Likewise.
395 (X86_64_82_REG_4): Likewise.
396 (X86_64_82_REG_5): Likewise.
397 (X86_64_82_REG_6): Likewise.
398 (X86_64_82_REG_7): Likewise.
399 (X86_64_82): New.
400 (dis386): Use X86_64_82 instead of REG_82.
401 (reg_table): Remove REG_82.
402 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
403 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
404 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
405 X86_64_82_REG_7.
406
8b89fe14
L		 4072016-11-03 H.J. Lu <hongjiu.lu@intel.com>
408
409 PR binutils/20754
410 * i386-dis.c (REG_82): New.
411 (X86_64_82_REG_0): Likewise.
412 (X86_64_82_REG_1): Likewise.
413 (X86_64_82_REG_2): Likewise.
414 (X86_64_82_REG_3): Likewise.
415 (X86_64_82_REG_4): Likewise.
416 (X86_64_82_REG_5): Likewise.
417 (X86_64_82_REG_6): Likewise.
418 (X86_64_82_REG_7): Likewise.
419 (dis386): Use REG_82.
420 (reg_table): Add REG_82.
421 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
422 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
423 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
424
7148c369
L		 4252016-11-03 H.J. Lu <hongjiu.lu@intel.com>
426
427 * i386-dis.c (REG_82): Renamed to ...
428 (REG_83): This.
429 (dis386): Updated.
430 (reg_table): Likewise.
431
47acf0bd
IT		 4322016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
433
434 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
435 * i386-dis-evex.h (evex_table): Updated.
436 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
437 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
438 (cpu_flags): Add CpuAVX512_4VNNIW.
439 * i386-opc.h (enum): (AVX512_4VNNIW): New.
440 (i386_cpu_flags): Add cpuavx512_4vnniw.
441 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
442 * i386-init.h: Regenerate.
443 * i386-tbl.h: Ditto.
444
920d2ddc
IT		 4452016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
446
447 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
448 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
449 * i386-dis-evex.h (evex_table): Updated.
450 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
451 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
452 (cpu_flags): Add CpuAVX512_4FMAPS.
453 (opcode_modifiers): Add ImplicitQuadGroup modifier.
454 * i386-opc.h (AVX512_4FMAP): New.
455 (i386_cpu_flags): Add cpuavx512_4fmaps.
456 (ImplicitQuadGroup): New.
457 (i386_opcode_modifier): Add implicitquadgroup.
458 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
459 * i386-init.h: Regenerate.
460 * i386-tbl.h: Ditto.
461
e23eba97
NC		 4622016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
463 Andrew Waterman <andrew@sifive.com>
464
465 Add support for RISC-V architecture.
466 * configure.ac: Add entry for bfd_riscv_arch.
467 * configure: Regenerate.
468 * disassemble.c (disassembler): Add support for riscv.
469 (disassembler_usage): Likewise.
470 * riscv-dis.c: New file.
471 * riscv-opc.c: New file.
472
b5cefcca
L		 4732016-10-21 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
476 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
477 (rm_table): Update the RM_0FAE_REG_7 entry.
478 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
479 (cpu_flags): Remove CpuPCOMMIT.
480 * i386-opc.h (CpuPCOMMIT): Removed.
481 (i386_cpu_flags): Remove cpupcommit.
482 * i386-opc.tbl: Remove pcommit.
483 * i386-init.h: Regenerated.
484 * i386-tbl.h: Likewise.
485
9889cbb1
L		 4862016-10-20 H.J. Lu <hongjiu.lu@intel.com>
487
488 PR binutis/20705
489 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
490 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
491 32-bit mode. Don't check vex.register_specifier in 32-bit
492 mode.
493 (OP_VEX): Check for invalid mask registers.
494
28596323
L		 4952016-10-18 H.J. Lu <hongjiu.lu@intel.com>
496
497 PR binutis/20699
498 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
499 sizeflag.
500
da8d7d66
L		 5012016-10-18 H.J. Lu <hongjiu.lu@intel.com>
502
503 PR binutis/20704
504 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
505
eaf02703
MR		 5062016-10-18 Maciej W. Rozycki <macro@imgtec.com>
507
508 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
509 local variable to `index_regno'.
510
decf5bd1
CM		 5112016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
512
513 * arc-tbl.h: Removed any "inv.+" instructions from the table.
514
e5b06ef0
CZ		 5152016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
516
517 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
518 usage on ISA basis.
519
93562a34
JW		 5202016-10-11 Jiong Wang <jiong.wang@arm.com>
521
522 PR target/20666
523 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
524
362c0c4d
JW		 5252016-10-07 Jiong Wang <jiong.wang@arm.com>
526
527 PR target/20667
528 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
529 available.
530
1047201f
AM		 5312016-10-07 Alan Modra <amodra@gmail.com>
532
533 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
534
1a0670f3
AM		 5352016-10-06 Alan Modra <amodra@gmail.com>
536
537 * aarch64-opc.c: Spell fall through comments consistently.
538 * i386-dis.c: Likewise.
539 * aarch64-dis.c: Add missing fall through comments.
540 * aarch64-opc.c: Likewise.
541 * arc-dis.c: Likewise.
542 * arm-dis.c: Likewise.
543 * i386-dis.c: Likewise.
544 * m68k-dis.c: Likewise.
545 * mep-asm.c: Likewise.
546 * ns32k-dis.c: Likewise.
547 * sh-dis.c: Likewise.
548 * tic4x-dis.c: Likewise.
549 * tic6x-dis.c: Likewise.
550 * vax-dis.c: Likewise.
551
2b804145
AM		 5522016-10-06 Alan Modra <amodra@gmail.com>
553
554 * arc-ext.c (create_map): Add missing break.
555 * msp430-decode.opc (encode_as): Likewise.
556 * msp430-decode.c: Regenerate.
557
616ec358
AM		 5582016-10-06 Alan Modra <amodra@gmail.com>
559
560 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
561 * crx-dis.c (print_insn_crx): Likewise.
562
72da393d
L		 5632016-09-30 H.J. Lu <hongjiu.lu@intel.com>
564
565 PR binutils/20657
566 * i386-dis.c (putop): Don't assign alt twice.
567
744ce302
JW		 5682016-09-29 Jiong Wang <jiong.wang@arm.com>
569
570 PR target/20553
571 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
572
a5721ba2
AM		 5732016-09-29 Alan Modra <amodra@gmail.com>
574
575 * ppc-opc.c (L): Make compulsory.
576 (LOPT): New, optional form of L.
577 (HTM_R): Define as LOPT.
578 (L0, L1): Delete.
579 (L32OPT): New, optional for 32-bit L.
580 (L2OPT): New, 2-bit L for dcbf.
581 (SVC_LEC): Update.
582 (L2): Define.
583 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
584 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
585 <dcbf>: Use L2OPT.
586 <tlbiel, tlbie>: Use LOPT.
587 <wclr, wclrall>: Use L2.
588
c5da1932
VZ		 5892016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
590
591 * Makefile.in: Regenerate.
592 * configure: Likewise.
593
2b848ebd
CZ		 5942016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
595
596 * arc-ext-tbl.h (EXTINSN2OPF): Define.
597 (EXTINSN2OP): Use EXTINSN2OPF.
598 (bspeekm, bspop, modapp): New extension instructions.
599 * arc-opc.c (F_DNZ_ND): Define.
600 (F_DNZ_D): Likewise.
601 (F_SIZEB1): Changed.
602 (C_DNZ_D): Define.
603 (C_HARD): Changed.
604 * arc-tbl.h (dbnz): New instruction.
605 (prealloc): Allow it for ARC EM.
606 (xbfu): Likewise.
607
ad43e107
RS		 6082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
609
610 * aarch64-opc.c (print_immediate_offset_address): Print spaces
611 after commas in addresses.
612 (aarch64_print_operand): Likewise.
613
ab3b8fcf
RS		 6142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
615
616 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
617 rather than "should be" or "expected to be" in error messages.
618
bb7eff52
RS		 6192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620
621 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
622 (print_mnemonic_name): ...here.
623 (print_comment): New function.
624 (print_aarch64_insn): Call it.
625 * aarch64-opc.c (aarch64_conds): Add SVE names.
626 (aarch64_print_operand): Print alternative condition names in
627 a comment.
628
c0890d26
RS		 6292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
630
631 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
632 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
633 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
634 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
635 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
636 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
637 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
638 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
639 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
640 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
641 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
642 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
643 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
644 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
645 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
646 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
647 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
648 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
649 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
650 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
651 (OP_SVE_XWU, OP_SVE_XXU): New macros.
652 (aarch64_feature_sve): New variable.
653 (SVE): New macro.
654 (_SVE_INSN): Likewise.
655 (aarch64_opcode_table): Add SVE instructions.
656 * aarch64-opc.h (extract_fields): Declare.
657 * aarch64-opc-2.c: Regenerate.
658 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
659 * aarch64-asm-2.c: Regenerate.
660 * aarch64-dis.c (extract_fields): Make global.
661 (do_misc_decoding): Handle the new SVE aarch64_ops.
662 * aarch64-dis-2.c: Regenerate.
663
116b6019
RS		 6642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
665
666 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
667 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
668 aarch64_field_kinds.
669 * aarch64-opc.c (fields): Add corresponding entries.
670 * aarch64-asm.c (aarch64_get_variant): New function.
671 (aarch64_encode_variant_using_iclass): Likewise.
672 (aarch64_opcode_encode): Call it.
673 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
674 (aarch64_opcode_decode): Call it.
675
047cd301
RS		 6762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
677
678 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
679 and FP register operands.
680 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
681 (FLD_SVE_Vn): New aarch64_field_kinds.
682 * aarch64-opc.c (fields): Add corresponding entries.
683 (aarch64_print_operand): Handle the new SVE core and FP register
684 operands.
685 * aarch64-opc-2.c: Regenerate.
686 * aarch64-asm-2.c: Likewise.
687 * aarch64-dis-2.c: Likewise.
688
165d4950
RS		 6892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
690
691 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
692 immediate operands.
693 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
694 * aarch64-opc.c (fields): Add corresponding entry.
695 (operand_general_constraint_met_p): Handle the new SVE FP immediate
696 operands.
697 (aarch64_print_operand): Likewise.
698 * aarch64-opc-2.c: Regenerate.
699 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
700 (ins_sve_float_zero_one): New inserters.
701 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
702 (aarch64_ins_sve_float_half_two): Likewise.
703 (aarch64_ins_sve_float_zero_one): Likewise.
704 * aarch64-asm-2.c: Regenerate.
705 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
706 (ext_sve_float_zero_one): New extractors.
707 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
708 (aarch64_ext_sve_float_half_two): Likewise.
709 (aarch64_ext_sve_float_zero_one): Likewise.
710 * aarch64-dis-2.c: Regenerate.
711
e950b345
RS		 7122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
713
714 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
715 integer immediate operands.
716 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
717 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
718 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
719 * aarch64-opc.c (fields): Add corresponding entries.
720 (operand_general_constraint_met_p): Handle the new SVE integer
721 immediate operands.
722 (aarch64_print_operand): Likewise.
723 (aarch64_sve_dupm_mov_immediate_p): New function.
724 * aarch64-opc-2.c: Regenerate.
725 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
726 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
727 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
728 (aarch64_ins_limm): ...here.
729 (aarch64_ins_inv_limm): New function.
730 (aarch64_ins_sve_aimm): Likewise.
731 (aarch64_ins_sve_asimm): Likewise.
732 (aarch64_ins_sve_limm_mov): Likewise.
733 (aarch64_ins_sve_shlimm): Likewise.
734 (aarch64_ins_sve_shrimm): Likewise.
735 * aarch64-asm-2.c: Regenerate.
736 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
737 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
738 * aarch64-dis.c (decode_limm): New function, split out from...
739 (aarch64_ext_limm): ...here.
740 (aarch64_ext_inv_limm): New function.
741 (decode_sve_aimm): Likewise.
742 (aarch64_ext_sve_aimm): Likewise.
743 (aarch64_ext_sve_asimm): Likewise.
744 (aarch64_ext_sve_limm_mov): Likewise.
745 (aarch64_top_bit): Likewise.
746 (aarch64_ext_sve_shlimm): Likewise.
747 (aarch64_ext_sve_shrimm): Likewise.
748 * aarch64-dis-2.c: Regenerate.
749
98907a70
RS		 7502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
751
752 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
753 operands.
754 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
755 the AARCH64_MOD_MUL_VL entry.
756 (value_aligned_p): Cope with non-power-of-two alignments.
757 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
758 (print_immediate_offset_address): Likewise.
759 (aarch64_print_operand): Likewise.
760 * aarch64-opc-2.c: Regenerate.
761 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
762 (ins_sve_addr_ri_s9xvl): New inserters.
763 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
764 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
765 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
766 * aarch64-asm-2.c: Regenerate.
767 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
768 (ext_sve_addr_ri_s9xvl): New extractors.
769 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
770 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
771 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
772 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
773 * aarch64-dis-2.c: Regenerate.
774
4df068de
RS		 7752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
776
777 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
778 address operands.
779 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
780 (FLD_SVE_xs_22): New aarch64_field_kinds.
781 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
782 (get_operand_specific_data): New function.
783 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
784 FLD_SVE_xs_14 and FLD_SVE_xs_22.
785 (operand_general_constraint_met_p): Handle the new SVE address
786 operands.
787 (sve_reg): New array.
788 (get_addr_sve_reg_name): New function.
789 (aarch64_print_operand): Handle the new SVE address operands.
790 * aarch64-opc-2.c: Regenerate.
791 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
792 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
793 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
794 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
795 (aarch64_ins_sve_addr_rr_lsl): Likewise.
796 (aarch64_ins_sve_addr_rz_xtw): Likewise.
797 (aarch64_ins_sve_addr_zi_u5): Likewise.
798 (aarch64_ins_sve_addr_zz): Likewise.
799 (aarch64_ins_sve_addr_zz_lsl): Likewise.
800 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
801 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
802 * aarch64-asm-2.c: Regenerate.
803 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
804 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
805 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
806 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
807 (aarch64_ext_sve_addr_ri_u6): Likewise.
808 (aarch64_ext_sve_addr_rr_lsl): Likewise.
809 (aarch64_ext_sve_addr_rz_xtw): Likewise.
810 (aarch64_ext_sve_addr_zi_u5): Likewise.
811 (aarch64_ext_sve_addr_zz): Likewise.
812 (aarch64_ext_sve_addr_zz_lsl): Likewise.
813 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
814 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
815 * aarch64-dis-2.c: Regenerate.
816
2442d846
RS		 8172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
818
819 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
820 AARCH64_OPND_SVE_PATTERN_SCALED.
821 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
822 * aarch64-opc.c (fields): Add a corresponding entry.
823 (set_multiplier_out_of_range_error): New function.
824 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
825 (operand_general_constraint_met_p): Handle
826 AARCH64_OPND_SVE_PATTERN_SCALED.
827 (print_register_offset_address): Use PRIi64 to print the
828 shift amount.
829 (aarch64_print_operand): Likewise. Handle
830 AARCH64_OPND_SVE_PATTERN_SCALED.
831 * aarch64-opc-2.c: Regenerate.
832 * aarch64-asm.h (ins_sve_scale): New inserter.
833 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
834 * aarch64-asm-2.c: Regenerate.
835 * aarch64-dis.h (ext_sve_scale): New inserter.
836 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
837 * aarch64-dis-2.c: Regenerate.
838
245d2e3f
RS		 8392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
840
841 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
842 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
843 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
844 (FLD_SVE_prfop): Likewise.
845 * aarch64-opc.c: Include libiberty.h.
846 (aarch64_sve_pattern_array): New variable.
847 (aarch64_sve_prfop_array): Likewise.
848 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
849 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
850 AARCH64_OPND_SVE_PRFOP.
851 * aarch64-asm-2.c: Regenerate.
852 * aarch64-dis-2.c: Likewise.
853 * aarch64-opc-2.c: Likewise.
854
d50c751e
RS		 8552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
856
857 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
858 AARCH64_OPND_QLF_P_[ZM].
859 (aarch64_print_operand): Print /z and /m where appropriate.
860
f11ad6bc
RS		 8612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
862
863 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
864 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
865 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
866 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
867 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
868 * aarch64-opc.c (fields): Add corresponding entries here.
869 (operand_general_constraint_met_p): Check that SVE register lists
870 have the correct length. Check the ranges of SVE index registers.
871 Check for cases where p8-p15 are used in 3-bit predicate fields.
872 (aarch64_print_operand): Handle the new SVE operands.
873 * aarch64-opc-2.c: Regenerate.
874 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
875 * aarch64-asm.c (aarch64_ins_sve_index): New function.
876 (aarch64_ins_sve_reglist): Likewise.
877 * aarch64-asm-2.c: Regenerate.
878 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
879 * aarch64-dis.c (aarch64_ext_sve_index): New function.
880 (aarch64_ext_sve_reglist): Likewise.
881 * aarch64-dis-2.c: Regenerate.
882
0c608d6b
RS		 8832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
884
885 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
886 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
887 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
888 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
889 tied operands.
890
01dbfe4c
RS		 8912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
892
893 * aarch64-opc.c (get_offset_int_reg_name): New function.
894 (print_immediate_offset_address): Likewise.
895 (print_register_offset_address): Take the base and offset
896 registers as parameters.
897 (aarch64_print_operand): Update caller accordingly. Use
898 print_immediate_offset_address.
899
72e9f319
RS		 9002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
901
902 * aarch64-opc.c (BANK): New macro.
903 (R32, R64): Take a register number as argument
904 (int_reg): Use BANK.
905
8a7f0c1b
RS		 9062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
907
908 * aarch64-opc.c (print_register_list): Add a prefix parameter.
909 (aarch64_print_operand): Update accordingly.
910
aa2aa4c6
RS		 9112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
912
913 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
914 for FPIMM.
915 * aarch64-asm.h (ins_fpimm): New inserter.
916 * aarch64-asm.c (aarch64_ins_fpimm): New function.
917 * aarch64-asm-2.c: Regenerate.
918 * aarch64-dis.h (ext_fpimm): New extractor.
919 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
920 (aarch64_ext_fpimm): New function.
921 * aarch64-dis-2.c: Regenerate.
922
b5464a68
RS		 9232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
924
925 * aarch64-asm.c: Include libiberty.h.
926 (insert_fields): New function.
927 (aarch64_ins_imm): Use it.
928 * aarch64-dis.c (extract_fields): New function.
929 (aarch64_ext_imm): Use it.
930
42408347
RS		 9312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
932
933 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
934 with an esize parameter.
935 (operand_general_constraint_met_p): Update accordingly.
936 Fix misindented code.
937 * aarch64-asm.c (aarch64_ins_limm): Update call to
938 aarch64_logical_immediate_p.
939
4989adac
RS		 9402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
941
942 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
943
bd11d5d8
RS		 9442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
945
946 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
947
f807f43d
CZ		 9482016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
949
950 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
951
fd486b63
PB		 9522016-09-14 Peter Bergner <bergner@vnet.ibm.com>
953
954 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
955 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
956 xor3>: Delete mnemonics.
957 <cp_abort>: Rename mnemonic from ...
958 <cpabort>: ...to this.
959 <setb>: Change to a X form instruction.
960 <sync>: Change to 1 operand form.
961 <copy>: Delete mnemonic.
962 <copy_first>: Rename mnemonic from ...
963 <copy>: ...to this.
964 <paste, paste.>: Delete mnemonics.
965 <paste_last>: Rename mnemonic from ...
966 <paste.>: ...to this.
967
dce08442
AK		 9682016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
969
970 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
971
952c3f51
AK		 9722016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
973
974 * s390-mkopc.c (main): Support alternate arch strings.
975
8b71537b
PS		 9762016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
977
978 * s390-opc.txt: Fix kmctr instruction type.
979
5b64d091
L		 9802016-09-07 H.J. Lu <hongjiu.lu@intel.com>
981
982 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
983 * i386-init.h: Regenerated.
984
7763838e
CM		 9852016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
986
987 * opcodes/arc-dis.c (print_insn_arc): Changed.
988
1b8b6532
JM		 9892016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
990
991 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
992 camellia_fl.
993
1a336194
TP		 9942016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
995
996 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
997 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
998 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
999
6b40c462
L		 10002016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1001
1002 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1003 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1004 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1005 PREFIX_MOD_3_0FAE_REG_4.
1006 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1007 PREFIX_MOD_3_0FAE_REG_4.
1008 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1009 (cpu_flags): Add CpuPTWRITE.
1010 * i386-opc.h (CpuPTWRITE): New.
1011 (i386_cpu_flags): Add cpuptwrite.
1012 * i386-opc.tbl: Add ptwrite instruction.
1013 * i386-init.h: Regenerated.
1014 * i386-tbl.h: Likewise.
1015
ab548d2d
AK		 10162016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1017
1018 * arc-dis.h: Wrap around in extern "C".
1019
344bde0a
RS		 10202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1021
1022 * aarch64-tbl.h (V8_2_INSN): New macro.
1023 (aarch64_opcode_table): Use it.
1024
5ce912d8
RS		 10252016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1026
1027 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1028 CORE_INSN, __FP_INSN and SIMD_INSN.
1029
9d30b0bd
RS		 10302016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1031
1032 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1033 (aarch64_opcode_table): Update uses accordingly.
1034
dfdaec14
AJ		 10352016-07-25 Andrew Jenner <andrew@codesourcery.com>
1036 Kwok Cheung Yeung <kcy@codesourcery.com>
1037
1038 opcodes/
1039 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1040 'e_cmplwi' to 'e_cmpli' instead.
1041 (OPVUPRT, OPVUPRT_MASK): Define.
1042 (powerpc_opcodes): Add E200Z4 insns.
1043 (vle_opcodes): Add context save/restore insns.
1044
7bd374a4
MR		 10452016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1046
1047 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1048 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1049 "j".
1050
db18dbab
GM		 10512016-07-27 Graham Markall <graham.markall@embecosm.com>
1052
1053 * arc-nps400-tbl.h: Change block comments to GNU format.
1054 * arc-dis.c: Add new globals addrtypenames,
1055 addrtypenames_max, and addtypeunknown.
1056 (get_addrtype): New function.
1057 (print_insn_arc): Print colons and address types when
1058 required.
1059 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1060 define insert and extract functions for all address types.
1061 (arc_operands): Add operands for colon and all address
1062 types.
1063 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1064 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1065 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1066 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1067 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1068 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1069
fecd57f9
L		 10702016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 * configure: Regenerated.
1073
37fd5ef3
CZ		 10742016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1075
1076 * arc-dis.c (skipclass): New structure.
1077 (decodelist): New variable.
1078 (is_compatible_p): New function.
1079 (new_element): Likewise.
1080 (skip_class_p): Likewise.
1081 (find_format_from_table): Use skip_class_p function.
1082 (find_format): Decode first the extension instructions.
1083 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1084 e_flags.
1085 (parse_option): New function.
1086 (parse_disassembler_options): Likewise.
1087 (print_arc_disassembler_options): Likewise.
1088 (print_insn_arc): Use parse_disassembler_options function. Proper
1089 select ARCv2 cpu variant.
1090 * disassemble.c (disassembler_usage): Add ARC disassembler
1091 options.
1092
92281a5b
MR		 10932016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1094
1095 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1096 annotation from the "nal" entry and reorder it beyond "bltzal".
1097
6e7ced37
JM		 10982016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1099
1100 * sparc-opc.c (ldtxa): New macro.
1101 (sparc_opcodes): Use the macro defined above to add entries for
1102 the LDTXA instructions.
1103 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1104 instruction.
1105
2f831b9a 11062016-07-07 James Bowman <james.bowman@ftdichip.com>
1107
1108 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1109 and "jmpc".
1110
c07315e0
JB		 11112016-07-01 Jan Beulich <jbeulich@suse.com>
1112
1113 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1114 (movzb): Adjust to cover all permitted suffixes.
1115 (movzw): New.
1116 * i386-tbl.h: Re-generate.
1117
9243100a
JB		 11182016-07-01 Jan Beulich <jbeulich@suse.com>
1119
1120 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1121 (lgdt): Remove Tbyte from non-64-bit variant.
1122 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1123 xsaves64, xsavec64): Remove Disp16.
1124 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1125 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1126 64-bit variants.
1127 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1128 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1129 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1130 64-bit variants.
1131 * i386-tbl.h: Re-generate.
1132
8325cc63
JB		 11332016-07-01 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1136 * i386-tbl.h: Re-generate.
1137
838441e4
YQ		 11382016-06-30 Yao Qi <yao.qi@linaro.org>
1139
1140 * arm-dis.c (print_insn): Fix typo in comment.
1141
dab26bf4
RS		 11422016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1143
1144 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1145 range of ldst_elemlist operands.
1146 (print_register_list): Use PRIi64 to print the index.
1147 (aarch64_print_operand): Likewise.
1148
5703197e
TS		 11492016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1150
1151 * mcore-opc.h: Remove sentinal.
1152 * mcore-dis.c (print_insn_mcore): Adjust.
1153
ce440d63
GM		 11542016-06-23 Graham Markall <graham.markall@embecosm.com>
1155
1156 * arc-opc.c: Correct description of availability of NPS400
1157 features.
1158
6fd3a02d
PB		 11592016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1160
1161 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1162 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1163 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1164 xor3>: New mnemonics.
1165 <setb>: Change to a VX form instruction.
1166 (insert_sh6): Add support for rldixor.
1167 (extract_sh6): Likewise.
1168
6b477896
TS		 11692016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1170
1171 * arc-ext.h: Wrap in extern C.
1172
bdd582db
GM		 11732016-06-21 Graham Markall <graham.markall@embecosm.com>
1174
1175 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1176 Use same method for determining instruction length on ARC700 and
1177 NPS-400.
1178 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1179 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1180 with the NPS400 subclass.
1181 * arc-opc.c: Likewise.
1182
96074adc
JM		 11832016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1184
1185 * sparc-opc.c (rdasr): New macro.
1186 (wrasr): Likewise.
1187 (rdpr): Likewise.
1188 (wrpr): Likewise.
1189 (rdhpr): Likewise.
1190 (wrhpr): Likewise.
1191 (sparc_opcodes): Use the macros above to fix and expand the
1192 definition of read/write instructions from/to
1193 asr/privileged/hyperprivileged instructions.
1194 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1195 %hva_mask_nz. Prefer softint_set and softint_clear over
1196 set_softint and clear_softint.
1197 (print_insn_sparc): Support %ver in Rd.
1198
7a10c22f
JM		 11992016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1200
1201 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1202 architecture according to the hardware capabilities they require.
1203
4f26fb3a
JM		 12042016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1205
1206 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1207 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1208 bfd_mach_sparc_v9{c,d,e,v,m}.
1209 * sparc-opc.c (MASK_V9C): Define.
1210 (MASK_V9D): Likewise.
1211 (MASK_V9E): Likewise.
1212 (MASK_V9V): Likewise.
1213 (MASK_V9M): Likewise.
1214 (v6): Add MASK_V9{C,D,E,V,M}.
1215 (v6notlet): Likewise.
1216 (v7): Likewise.
1217 (v8): Likewise.
1218 (v9): Likewise.
1219 (v9andleon): Likewise.
1220 (v9a): Likewise.
1221 (v9b): Likewise.
1222 (v9c): Define.
1223 (v9d): Likewise.
1224 (v9e): Likewise.
1225 (v9v): Likewise.
1226 (v9m): Likewise.
1227 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1228
3ee6e4fb
NC		 12292016-06-15 Nick Clifton <nickc@redhat.com>
1230
1231 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1232 constants to match expected behaviour.
1233 (nds32_parse_opcode): Likewise. Also for whitespace.
1234
02f3be19
AB		 12352016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1236
1237 * arc-opc.c (extract_rhv1): Extract value from insn.
1238
6f9f37ed 12392016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1240
1241 * arc-nps400-tbl.h: Add ldbit instruction.
1242 * arc-opc.c: Add flag classes required for ldbit.
1243
6f9f37ed 12442016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1245
1246 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1247 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1248 support the above instructions.
1249
6f9f37ed 12502016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1251
1252 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1253 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1254 csma, cbba, zncv, and hofs.
1255 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1256 support the above instructions.
1257
12582016-06-06 Graham Markall <graham.markall@embecosm.com>
1259
1260 * arc-nps400-tbl.h: Add andab and orab instructions.
1261
12622016-06-06 Graham Markall <graham.markall@embecosm.com>
1263
1264 * arc-nps400-tbl.h: Add addl-like instructions.
1265
12662016-06-06 Graham Markall <graham.markall@embecosm.com>
1267
1268 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1269
12702016-06-06 Graham Markall <graham.markall@embecosm.com>
1271
1272 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1273 instructions.
1274
b2cc3f6f
AK		 12752016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1276
1277 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1278 variable.
1279 (init_disasm): Handle new command line option "insnlength".
1280 (print_s390_disassembler_options): Mention new option in help
1281 output.
1282 (print_insn_s390): Use the encoded insn length when dumping
1283 unknown instructions.
1284
1857fe72
DC		 12852016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1286
1287 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1288 to the address and set as symbol address for LDS/ STS immediate operands.
1289
14b57c7c
AM		 12902016-06-07 Alan Modra <amodra@gmail.com>
1291
1292 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1293 cpu for "vle" to e500.
1294 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1295 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1296 (PPCNONE): Delete, substitute throughout.
1297 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1298 except for major opcode 4 and 31.
1299 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1300
4d1464f2
MW		 13012016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1302
1303 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1304 ARM_EXT_RAS in relevant entries.
1305
026122a6
PB		 13062016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1307
1308 PR binutils/20196
1309 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1310 opcodes for E6500.
1311
07f5af7d
L		 13122016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1313
1314 PR binutis/18386
1315 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1316 (indir_v_mode): New.
1317 Add comments for '&'.
1318 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1319 (putop): Handle '&'.
1320 (intel_operand_size): Handle indir_v_mode.
1321 (OP_E_register): Likewise.
1322 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1323 64-bit indirect call/jmp for AMD64.
1324 * i386-tbl.h: Regenerated
1325
4eb6f892
AB		 13262016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1327
1328 * arc-dis.c (struct arc_operand_iterator): New structure.
1329 (find_format_from_table): All the old content from find_format,
1330 with some minor adjustments, and parameter renaming.
1331 (find_format_long_instructions): New function.
1332 (find_format): Rewritten.
1333 (arc_insn_length): Add LSB parameter.
1334 (extract_operand_value): New function.
1335 (operand_iterator_next): New function.
1336 (print_insn_arc): Use new functions to find opcode, and iterator
1337 over operands.
1338 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1339 (extract_nps_3bit_dst_short): New function.
1340 (insert_nps_3bit_src2_short): New function.
1341 (extract_nps_3bit_src2_short): New function.
1342 (insert_nps_bitop1_size): New function.
1343 (extract_nps_bitop1_size): New function.
1344 (insert_nps_bitop2_size): New function.
1345 (extract_nps_bitop2_size): New function.
1346 (insert_nps_bitop_mod4_msb): New function.
1347 (extract_nps_bitop_mod4_msb): New function.
1348 (insert_nps_bitop_mod4_lsb): New function.
1349 (extract_nps_bitop_mod4_lsb): New function.
1350 (insert_nps_bitop_dst_pos3_pos4): New function.
1351 (extract_nps_bitop_dst_pos3_pos4): New function.
1352 (insert_nps_bitop_ins_ext): New function.
1353 (extract_nps_bitop_ins_ext): New function.
1354 (arc_operands): Add new operands.
1355 (arc_long_opcodes): New global array.
1356 (arc_num_long_opcodes): New global.
1357 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1358
1fe0971e
TS		 13592016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1360
1361 * nds32-asm.h: Add extern "C".
1362 * sh-opc.h: Likewise.
1363
315f180f
GM		 13642016-06-01 Graham Markall <graham.markall@embecosm.com>
1365
1366 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1367 0,b,limm to the rflt instruction.
1368
a2b5fccc
TS		 13692016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1370
1371 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1372 constant.
1373
0cbd0046
L		 13742016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 PR gas/20145
1377 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1378 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1379 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1380 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1381 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1382 * i386-init.h: Regenerated.
1383
1848e567
L		 13842016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1385
1386 PR gas/20145
1387 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1388 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1389 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1390 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1391 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1392 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1393 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1394 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1395 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1396 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1397 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1398 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1399 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1400 CpuRegMask for AVX512.
1401 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1402 and CpuRegMask.
1403 (set_bitfield_from_cpu_flag_init): New function.
1404 (set_bitfield): Remove const on f. Call
1405 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1406 * i386-opc.h (CpuRegMMX): New.
1407 (CpuRegXMM): Likewise.
1408 (CpuRegYMM): Likewise.
1409 (CpuRegZMM): Likewise.
1410 (CpuRegMask): Likewise.
1411 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1412 and cpuregmask.
1413 * i386-init.h: Regenerated.
1414 * i386-tbl.h: Likewise.
1415
e92bae62
L		 14162016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1417
1418 PR gas/20154
1419 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1420 (opcode_modifiers): Add AMD64 and Intel64.
1421 (main): Properly verify CpuMax.
1422 * i386-opc.h (CpuAMD64): Removed.
1423 (CpuIntel64): Likewise.
1424 (CpuMax): Set to CpuNo64.
1425 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1426 (AMD64): New.
1427 (Intel64): Likewise.
1428 (i386_opcode_modifier): Add amd64 and intel64.
1429 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1430 on call and jmp.
1431 * i386-init.h: Regenerated.
1432 * i386-tbl.h: Likewise.
1433
e89c5eaa
L		 14342016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1435
1436 PR gas/20154
1437 * i386-gen.c (main): Fail if CpuMax is incorrect.
1438 * i386-opc.h (CpuMax): Set to CpuIntel64.
1439 * i386-tbl.h: Regenerated.
1440
77d66e7b
NC		 14412016-05-27 Nick Clifton <nickc@redhat.com>
1442
1443 PR target/20150
1444 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1445 (msp430dis_opcode_unsigned): New function.
1446 (msp430dis_opcode_signed): New function.
1447 (msp430_singleoperand): Use the new opcode reading functions.
1448 Only disassenmble bytes if they were successfully read.
1449 (msp430_doubleoperand): Likewise.
1450 (msp430_branchinstr): Likewise.
1451 (msp430x_callx_instr): Likewise.
1452 (print_insn_msp430): Check that it is safe to read bytes before
1453 attempting disassembly. Use the new opcode reading functions.
1454
19dfcc89
PB		 14552016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1456
1457 * ppc-opc.c (CY): New define. Document it.
1458 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1459
f3ad7637
L		 14602016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1461
1462 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1463 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1464 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1465 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1466 CPU_ANY_AVX_FLAGS.
1467 * i386-init.h: Regenerated.
1468
f1360d58
L		 14692016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1470
1471 PR gas/20141
1472 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1473 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1474 * i386-init.h: Regenerated.
1475
293f5f65
L		 14762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1477
1478 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1479 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1480 * i386-init.h: Regenerated.
1481
d9eca1df
CZ		 14822016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1483
1484 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1485 information.
1486 (print_insn_arc): Set insn_type information.
1487 * arc-opc.c (C_CC): Add F_CLASS_COND.
1488 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1489 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1490 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1491 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1492 (brne, brne_s, jeq_s, jne_s): Likewise.
1493
87789e08
CZ		 14942016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1495
1496 * arc-tbl.h (neg): New instruction variant.
1497
c810e0b8
CZ		 14982016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1499
1500 * arc-dis.c (find_format, find_format, get_auxreg)
1501 (print_insn_arc): Changed.
1502 * arc-ext.h (INSERT_XOP): Likewise.
1503
3d207518
TS		 15042016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1505
1506 * tic54x-dis.c (sprint_mmr): Adjust.
1507 * tic54x-opc.c: Likewise.
1508
514e58b7
AM		 15092016-05-19 Alan Modra <amodra@gmail.com>
1510
1511 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1512
e43de63c
AM		 15132016-05-19 Alan Modra <amodra@gmail.com>
1514
1515 * ppc-opc.c: Formatting.
1516 (NSISIGNOPT): Define.
1517 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1518
1401d2fe
MR		 15192016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1520
1521 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1522 replacing references to `micromips_ase' throughout.
1523 (_print_insn_mips): Don't use file-level microMIPS annotation to
1524 determine the disassembly mode with the symbol table.
1525
1178da44
PB		 15262016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1527
1528 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1529
8f4f9071
MF		 15302016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1531
1532 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1533 mips64r6.
1534 * mips-opc.c (D34): New macro.
1535 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1536
8bc52696
AF		 15372016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1538
1539 * i386-dis.c (prefix_table): Add RDPID instruction.
1540 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1541 (cpu_flags): Add RDPID bitfield.
1542 * i386-opc.h (enum): Add RDPID element.
1543 (i386_cpu_flags): Add RDPID field.
1544 * i386-opc.tbl: Add RDPID instruction.
1545 * i386-init.h: Regenerate.
1546 * i386-tbl.h: Regenerate.
1547
39d911fc
TP		 15482016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1549
1550 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1551 branch type of a symbol.
1552 (print_insn): Likewise.
1553
16a1fa25
TP		 15542016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1555
1556 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1557 Mainline Security Extensions instructions.
1558 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1559 Extensions instructions.
1560 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1561 instructions.
1562 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1563 special registers.
1564
d751b79e
JM		 15652016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1566
1567 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1568
945e0f82
CZ		 15692016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1570
1571 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1572 (arcExtMap_genOpcode): Likewise.
1573 * arc-opc.c (arg_32bit_rc): Define new variable.
1574 (arg_32bit_u6): Likewise.
1575 (arg_32bit_limm): Likewise.
1576
20f55f38
SN		 15772016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1578
1579 * aarch64-gen.c (VERIFIER): Define.
1580 * aarch64-opc.c (VERIFIER): Define.
1581 (verify_ldpsw): Use static linkage.
1582 * aarch64-opc.h (verify_ldpsw): Remove.
1583 * aarch64-tbl.h: Use VERIFIER for verifiers.
1584
4bd13cde
NC		 15852016-04-28 Nick Clifton <nickc@redhat.com>
1586
1587 PR target/19722
1588 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1589 * aarch64-opc.c (verify_ldpsw): New function.
1590 * aarch64-opc.h (verify_ldpsw): New prototype.
1591 * aarch64-tbl.h: Add initialiser for verifier field.
1592 (LDPSW): Set verifier to verify_ldpsw.
1593
c0f92bf9
L		 15942016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1595
1596 PR binutils/19983
1597 PR binutils/19984
1598 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1599 smaller than address size.
1600
e6c7cdec
TS		 16012016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1602
1603 * alpha-dis.c: Regenerate.
1604 * crx-dis.c: Likewise.
1605 * disassemble.c: Likewise.
1606 * epiphany-opc.c: Likewise.
1607 * fr30-opc.c: Likewise.
1608 * frv-opc.c: Likewise.
1609 * ip2k-opc.c: Likewise.
1610 * iq2000-opc.c: Likewise.
1611 * lm32-opc.c: Likewise.
1612 * lm32-opinst.c: Likewise.
1613 * m32c-opc.c: Likewise.
1614 * m32r-opc.c: Likewise.
1615 * m32r-opinst.c: Likewise.
1616 * mep-opc.c: Likewise.
1617 * mt-opc.c: Likewise.
1618 * or1k-opc.c: Likewise.
1619 * or1k-opinst.c: Likewise.
1620 * tic80-opc.c: Likewise.
1621 * xc16x-opc.c: Likewise.
1622 * xstormy16-opc.c: Likewise.
1623
537aefaf
AB		 16242016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1625
1626 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1627 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1628 calcsd, and calcxd instructions.
1629 * arc-opc.c (insert_nps_bitop_size): Delete.
1630 (extract_nps_bitop_size): Delete.
1631 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1632 (extract_nps_qcmp_m3): Define.
1633 (extract_nps_qcmp_m2): Define.
1634 (extract_nps_qcmp_m1): Define.
1635 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1636 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1637 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1638 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1639 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1640 NPS_QCMP_M3.
1641
c8f785f2
AB		 16422016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1643
1644 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1645
6fd8e7c2
L		 16462016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1647
1648 * Makefile.in: Regenerated with automake 1.11.6.
1649 * aclocal.m4: Likewise.
1650
4b0c052e
AB		 16512016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1652
1653 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1654 instructions.
1655 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1656 (extract_nps_cmem_uimm16): New function.
1657 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1658
cb040366
AB		 16592016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1660
1661 * arc-dis.c (arc_insn_length): New function.
1662 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1663 (find_format): Change insnLen parameter to unsigned.
1664
accc0180
NC		 16652016-04-13 Nick Clifton <nickc@redhat.com>
1666
1667 PR target/19937
1668 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1669 the LD.B and LD.BU instructions.
1670
f36e33da
CZ		 16712016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1672
1673 * arc-dis.c (find_format): Check for extension flags.
1674 (print_flags): New function.
1675 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1676 .extAuxRegister.
1677 * arc-ext.c (arcExtMap_coreRegName): Use
1678 LAST_EXTENSION_CORE_REGISTER.
1679 (arcExtMap_coreReadWrite): Likewise.
1680 (dump_ARC_extmap): Update printing.
1681 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1682 (arc_aux_regs): Add cpu field.
1683 * arc-regs.h: Add cpu field, lower case name aux registers.
1684
1c2e355e
CZ		 16852016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1686
1687 * arc-tbl.h: Add rtsc, sleep with no arguments.
1688
b99747ae
CZ		 16892016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1690
1691 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1692 Initialize.
1693 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1694 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1695 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1696 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1697 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1698 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1699 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1700 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1701 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1702 (arc_opcode arc_opcodes): Null terminate the array.
1703 (arc_num_opcodes): Remove.
1704 * arc-ext.h (INSERT_XOP): Define.
1705 (extInstruction_t): Likewise.
1706 (arcExtMap_instName): Delete.
1707 (arcExtMap_insn): New function.
1708 (arcExtMap_genOpcode): Likewise.
1709 * arc-ext.c (ExtInstruction): Remove.
1710 (create_map): Zero initialize instruction fields.
1711 (arcExtMap_instName): Remove.
1712 (arcExtMap_insn): New function.
1713 (dump_ARC_extmap): More info while debuging.
1714 (arcExtMap_genOpcode): New function.
1715 * arc-dis.c (find_format): New function.
1716 (print_insn_arc): Use find_format.
1717 (arc_get_disassembler): Enable dump_ARC_extmap only when
1718 debugging.
1719
92708cec
MR		 17202016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1721
1722 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1723 instruction bits out.
1724
a42a4f84
AB		 17252016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1726
1727 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1728 * arc-opc.c (arc_flag_operands): Add new flags.
1729 (arc_flag_classes): Add new classes.
1730
1328504b
AB		 17312016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1732
1733 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1734
820f03ff
AB		 17352016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1736
1737 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1738 encode1, rflt, crc16, and crc32 instructions.
1739 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1740 (arc_flag_classes): Add C_NPS_R.
1741 (insert_nps_bitop_size_2b): New function.
1742 (extract_nps_bitop_size_2b): Likewise.
1743 (insert_nps_bitop_uimm8): Likewise.
1744 (extract_nps_bitop_uimm8): Likewise.
1745 (arc_operands): Add new operand entries.
1746
8ddf6b2a
CZ		 17472016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1748
b99747ae
CZ		 1749 * arc-regs.h: Add a new subclass field. Add double assist
1750 accumulator register values.
1751 * arc-tbl.h: Use DPA subclass to mark the double assist
1752 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1753 * arc-opc.c (RSP): Define instead of SP.
1754 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1755
589a7d88
JW		 17562016-04-05 Jiong Wang <jiong.wang@arm.com>
1757
1758 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1759
0a191de9 17602016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1761
1762 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1763 NPS_R_SRC1.
1764
0a106562
AB		 17652016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1766
1767 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1768 issues. No functional changes.
1769
bd05ac5f
CZ		 17702016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1771
b99747ae
CZ		 1772 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1773 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1774 (RTT): Remove duplicate.
1775 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1776 (PCT_CONFIG*): Remove.
1777 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1778
9885948f
CZ		 17792016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1780
b99747ae 1781 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1782
f2dd8838
CZ		 17832016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1784
b99747ae
CZ		 1785 * arc-tbl.h (invld07): Remove.
1786 * arc-ext-tbl.h: New file.
1787 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1788 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1789
0d2f91fe
JK		 17902016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1791
1792 Fix -Wstack-usage warnings.
1793 * aarch64-dis.c (print_operands): Substitute size.
1794 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1795
a6b71f42
JM		 17962016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1797
1798 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1799 to get a proper diagnostic when an invalid ASR register is used.
1800
9780e045
NC		 18012016-03-22 Nick Clifton <nickc@redhat.com>
1802
1803 * configure: Regenerate.
1804
e23e8ebe
AB		 18052016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1806
1807 * arc-nps400-tbl.h: New file.
1808 * arc-opc.c: Add top level comment.
1809 (insert_nps_3bit_dst): New function.
1810 (extract_nps_3bit_dst): New function.
1811 (insert_nps_3bit_src2): New function.
1812 (extract_nps_3bit_src2): New function.
1813 (insert_nps_bitop_size): New function.
1814 (extract_nps_bitop_size): New function.
1815 (arc_flag_operands): Add nps400 entries.
1816 (arc_flag_classes): Add nps400 entries.
1817 (arc_operands): Add nps400 entries.
1818 (arc_opcodes): Add nps400 include.
1819
1ae8ab47
AB		 18202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1821
1822 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1823 the new class enum values.
1824
8699fc3e
AB		 18252016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1826
1827 * arc-dis.c (print_insn_arc): Handle nps400.
1828
24740d83
AB		 18292016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1830
1831 * arc-opc.c (BASE): Delete.
1832
8678914f
NC		 18332016-03-18 Nick Clifton <nickc@redhat.com>
1834
1835 PR target/19721
1836 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1837 of MOV insn that aliases an ORR insn.
1838
cc933301
JW		 18392016-03-16 Jiong Wang <jiong.wang@arm.com>
1840
1841 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1842
f86f5863
TS		 18432016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1844
1845 * mcore-opc.h: Add const qualifiers.
1846 * microblaze-opc.h (struct op_code_struct): Likewise.
1847 * sh-opc.h: Likewise.
1848 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1849 (tic4x_print_op): Likewise.
1850
62de1c63
AM		 18512016-03-02 Alan Modra <amodra@gmail.com>
1852
d11698cd 1853 * or1k-desc.h: Regenerate.
62de1c63 1854 * fr30-ibld.c: Regenerate.
c697cf0b 1855 * rl78-decode.c: Regenerate.
62de1c63 1856
020efce5
NC		 18572016-03-01 Nick Clifton <nickc@redhat.com>
1858
1859 PR target/19747
1860 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1861
b0c11777
RL		 18622016-02-24 Renlin Li <renlin.li@arm.com>
1863
1864 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1865 (print_insn_coprocessor): Support fp16 instructions.
1866
3e309328
RL		 18672016-02-24 Renlin Li <renlin.li@arm.com>
1868
1869 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1870 vminnm, vrint(mpna).
1871
8afc7bea
RL		 18722016-02-24 Renlin Li <renlin.li@arm.com>
1873
1874 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1875 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1876
4fd7268a
L		 18772016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1878
1879 * i386-dis.c (print_insn): Parenthesize expression to prevent
1880 truncated addresses.
1881 (OP_J): Likewise.
1882
4670103e
CZ		 18832016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1884 Janek van Oirschot <jvanoirs@synopsys.com>
1885
b99747ae
CZ		 1886 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1887 variable.
4670103e 1888
c1d9289f
NC		 18892016-02-04 Nick Clifton <nickc@redhat.com>
1890
1891 PR target/19561
1892 * msp430-dis.c (print_insn_msp430): Add a special case for
1893 decoding an RRC instruction with the ZC bit set in the extension
1894 word.
1895
a143b004
AB		 18962016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1897
1898 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1899 * epiphany-ibld.c: Regenerate.
1900 * fr30-ibld.c: Regenerate.
1901 * frv-ibld.c: Regenerate.
1902 * ip2k-ibld.c: Regenerate.
1903 * iq2000-ibld.c: Regenerate.
1904 * lm32-ibld.c: Regenerate.
1905 * m32c-ibld.c: Regenerate.
1906 * m32r-ibld.c: Regenerate.
1907 * mep-ibld.c: Regenerate.
1908 * mt-ibld.c: Regenerate.
1909 * or1k-ibld.c: Regenerate.
1910 * xc16x-ibld.c: Regenerate.
1911 * xstormy16-ibld.c: Regenerate.
1912
b89807c6
AB		 19132016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1914
1915 * epiphany-dis.c: Regenerated from latest cpu files.
1916
d8c823c8
MM		 19172016-02-01 Michael McConville <mmcco@mykolab.com>
1918
1919 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1920 test bit.
1921
5bc5ae88
RL		 19222016-01-25 Renlin Li <renlin.li@arm.com>
1923
1924 * arm-dis.c (mapping_symbol_for_insn): New function.
1925 (find_ifthen_state): Call mapping_symbol_for_insn().
1926
0bff6e2d
MW		 19272016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1928
1929 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1930 of MSR UAO immediate operand.
1931
100b4f2e
MR		 19322016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1933
1934 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1935 instruction support.
1936
5c14705f
AM		 19372016-01-17 Alan Modra <amodra@gmail.com>
1938
1939 * configure: Regenerate.
1940
4d82fe66
NC		 19412016-01-14 Nick Clifton <nickc@redhat.com>
1942
1943 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1944 instructions that can support stack pointer operations.
1945 * rl78-decode.c: Regenerate.
1946 * rl78-dis.c: Fix display of stack pointer in MOVW based
1947 instructions.
1948
651657fa
MW		 19492016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1950
1951 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1952 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1953 erxtatus_el1 and erxaddr_el1.
1954
105bde57
MW		 19552016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1956
1957 * arm-dis.c (arm_opcodes): Add "esb".
1958 (thumb_opcodes): Likewise.
1959
afa8d405
PB		 19602016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1961
1962 * ppc-opc.c <xscmpnedp>: Delete.
1963 <xvcmpnedp>: Likewise.
1964 <xvcmpnedp.>: Likewise.
1965 <xvcmpnesp>: Likewise.
1966 <xvcmpnesp.>: Likewise.
1967
83c3256e
AS		 19682016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1969
1970 PR gas/13050
1971 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1972 addition to ISA_A.
1973
6f2750fe
AM		 19742016-01-01 Alan Modra <amodra@gmail.com>
1975
1976 Update year range in copyright notice of all files.
1977
3499769a
AM		 1978For older changes see ChangeLog-2015
1979\f
1980Copyright (C) 2016 Free Software Foundation, Inc.
1981
1982Copying and distribution of this file, with or without modification,
1983are permitted in any medium without royalty provided the copyright
1984notice and this notice are preserved.
1985
1986Local Variables:
1987mode: change-log
1988left-margin: 8
1989fill-column: 74
1990version-control: never
1991End:
GDB Binutils - Deliverables
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