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[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f1c7f421
AV		 12019-04-15 Sudakshina Das <sudi.das@arm.com>
2
3 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
4 Arm register with r13 and r15 unpredictable.
5 (thumb32_opcodes): New instructions for bfx and bflx.
6
4389b29a
AV		 72019-04-15 Sudakshina Das <sudi.das@arm.com>
8
9 * arm-dis.c (thumb32_opcodes): New instructions for bf.
10
e5d6e09e
AV		 112019-04-15 Sudakshina Das <sudi.das@arm.com>
12
13 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
14
e12437dc
AV		 152019-04-15 Sudakshina Das <sudi.das@arm.com>
16
17 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
18
031254f2
AV		 192019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
20
21 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
22
e5a557ac
JD		 232019-04-12 John Darrington <john@darrington.wattle.id.au>
24
25 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
26 "optr". ("operator" is a reserved word in c++).
27
bd7ceb8d
SD		 282019-04-11 Sudakshina Das <sudi.das@arm.com>
29
30 * aarch64-opc.c (aarch64_print_operand): Add case for
31 AARCH64_OPND_Rt_SP.
32 (verify_constraints): Likewise.
33 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
34 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
35 to accept Rt|SP as first operand.
36 (AARCH64_OPERANDS): Add new Rt_SP.
37 * aarch64-asm-2.c: Regenerated.
38 * aarch64-dis-2.c: Regenerated.
39 * aarch64-opc-2.c: Regenerated.
40
e54010f1
SD		 412019-04-11 Sudakshina Das <sudi.das@arm.com>
42
43 * aarch64-asm-2.c: Regenerated.
44 * aarch64-dis-2.c: Likewise.
45 * aarch64-opc-2.c: Likewise.
46 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
47
7e96e219
RS		 482019-04-09 Robert Suchanek <robert.suchanek@mips.com>
49
50 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
51
6f2791d5
L		 522019-04-08 H.J. Lu <hongjiu.lu@intel.com>
53
54 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
55 * i386-init.h: Regenerated.
56
e392bad3
AM		 572019-04-07 Alan Modra <amodra@gmail.com>
58
59 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
60 op_separator to control printing of spaces, comma and parens
61 rather than need_comma, need_paren and spaces vars.
62
dffaa15c
AM		 632019-04-07 Alan Modra <amodra@gmail.com>
64
65 PR 24421
66 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
67 (print_insn_neon, print_insn_arm): Likewise.
68
d6aab7a1
XG		 692019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
70
71 * i386-dis-evex.h (evex_table): Updated to support BF16
72 instructions.
73 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
74 and EVEX_W_0F3872_P_3.
75 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
76 (cpu_flags): Add bitfield for CpuAVX512_BF16.
77 * i386-opc.h (enum): Add CpuAVX512_BF16.
78 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
79 * i386-opc.tbl: Add AVX512 BF16 instructions.
80 * i386-init.h: Regenerated.
81 * i386-tbl.h: Likewise.
82
66e85460
AM		 832019-04-05 Alan Modra <amodra@gmail.com>
84
85 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
86 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
87 to favour printing of "-" branch hint when using the "y" bit.
88 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
89
c2b1c275
AM		 902019-04-05 Alan Modra <amodra@gmail.com>
91
92 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
93 opcode until first operand is output.
94
aae9718e
PB		 952019-04-04 Peter Bergner <bergner@linux.ibm.com>
96
97 PR gas/24349
98 * ppc-opc.c (valid_bo_pre_v2): Add comments.
99 (valid_bo_post_v2): Add support for 'at' branch hints.
100 (insert_bo): Only error on branch on ctr.
101 (get_bo_hint_mask): New function.
102 (insert_boe): Add new 'branch_taken' formal argument. Add support
103 for inserting 'at' branch hints.
104 (extract_boe): Add new 'branch_taken' formal argument. Add support
105 for extracting 'at' branch hints.
106 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
107 (BOE): Delete operand.
108 (BOM, BOP): New operands.
109 (RM): Update value.
110 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
111 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
112 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
113 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
114 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
115 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
116 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
117 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
118 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
119 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
120 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
121 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
122 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
123 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
124 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
125 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
126 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
127 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
128 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
129 bttarl+>: New extended mnemonics.
130
96a86c01
AM		 1312019-03-28 Alan Modra <amodra@gmail.com>
132
133 PR 24390
134 * ppc-opc.c (BTF): Define.
135 (powerpc_opcodes): Use for mtfsb*.
136 * ppc-dis.c (print_insn_powerpc): Print fields with both
137 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
138
796d6298
TC		 1392019-03-25 Tamar Christina <tamar.christina@arm.com>
140
141 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
142 (mapping_symbol_for_insn): Implement new algorithm.
143 (print_insn): Remove duplicate code.
144
60df3720
TC		 1452019-03-25 Tamar Christina <tamar.christina@arm.com>
146
147 * aarch64-dis.c (print_insn_aarch64):
148 Implement override.
149
51457761
TC		 1502019-03-25 Tamar Christina <tamar.christina@arm.com>
151
152 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
153 order.
154
53b2f36b
TC		 1552019-03-25 Tamar Christina <tamar.christina@arm.com>
156
157 * aarch64-dis.c (last_stop_offset): New.
158 (print_insn_aarch64): Use stop_offset.
159
89199bb5
L		 1602019-03-19 H.J. Lu <hongjiu.lu@intel.com>
161
162 PR gas/24359
163 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
164 CPU_ANY_AVX2_FLAGS.
165 * i386-init.h: Regenerated.
166
97ed31ae
L		 1672019-03-18 H.J. Lu <hongjiu.lu@intel.com>
168
169 PR gas/24348
170 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
171 vmovdqu16, vmovdqu32 and vmovdqu64.
172 * i386-tbl.h: Regenerated.
173
0919bfe9
AK		 1742019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
175
176 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
177 from vstrszb, vstrszh, and vstrszf.
178
1792019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
180
181 * s390-opc.txt: Add instruction descriptions.
182
21820ebe
JW		 1832019-02-08 Jim Wilson <jimw@sifive.com>
184
185 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
186 <bne>: Likewise.
187
f7dd2fb2
TC		 1882019-02-07 Tamar Christina <tamar.christina@arm.com>
189
190 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
191
6456d318
TC		 1922019-02-07 Tamar Christina <tamar.christina@arm.com>
193
194 PR binutils/23212
195 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
196 * aarch64-opc.c (verify_elem_sd): New.
197 (fields): Add FLD_sz entr.
198 * aarch64-tbl.h (_SIMD_INSN): New.
199 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
200 fmulx scalar and vector by element isns.
201
4a83b610
NC		 2022019-02-07 Nick Clifton <nickc@redhat.com>
203
204 * po/sv.po: Updated Swedish translation.
205
fc60b8c8
AK		 2062019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
207
208 * s390-mkopc.c (main): Accept arch13 as cpu string.
209 * s390-opc.c: Add new instruction formats and instruction opcode
210 masks.
211 * s390-opc.txt: Add new arch13 instructions.
212
e10620d3
TC		 2132019-01-25 Sudakshina Das <sudi.das@arm.com>
214
215 * aarch64-tbl.h (QL_LDST_AT): Update macro.
216 (aarch64_opcode): Change encoding for stg, stzg
217 st2g and st2zg.
218 * aarch64-asm-2.c: Regenerated.
219 * aarch64-dis-2.c: Regenerated.
220 * aarch64-opc-2.c: Regenerated.
221
20a4ca55
SD		 2222019-01-25 Sudakshina Das <sudi.das@arm.com>
223
224 * aarch64-asm-2.c: Regenerated.
225 * aarch64-dis-2.c: Likewise.
226 * aarch64-opc-2.c: Likewise.
227 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
228
550fd7bf
SD		 2292019-01-25 Sudakshina Das <sudi.das@arm.com>
230 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
231
232 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
233 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
234 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
235 * aarch64-dis.h (ext_addr_simple_2): Likewise.
236 * aarch64-opc.c (operand_general_constraint_met_p): Remove
237 case for ldstgv_indexed.
238 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
239 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
240 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
241 * aarch64-asm-2.c: Regenerated.
242 * aarch64-dis-2.c: Regenerated.
243 * aarch64-opc-2.c: Regenerated.
244
d9938630
NC		 2452019-01-23 Nick Clifton <nickc@redhat.com>
246
247 * po/pt_BR.po: Updated Brazilian Portuguese translation.
248
375cd423
NC		 2492019-01-21 Nick Clifton <nickc@redhat.com>
250
251 * po/de.po: Updated German translation.
252 * po/uk.po: Updated Ukranian translation.
253
57299f48
CX		 2542019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
255 * mips-dis.c (mips_arch_choices): Fix typo in
256 gs464, gs464e and gs264e descriptors.
257
f48dfe41
NC		 2582019-01-19 Nick Clifton <nickc@redhat.com>
259
260 * configure: Regenerate.
261 * po/opcodes.pot: Regenerate.
262
f974f26c
NC		 2632018-06-24 Nick Clifton <nickc@redhat.com>
264
265 2.32 branch created.
266
39f286cd
JD		 2672019-01-09 John Darrington <john@darrington.wattle.id.au>
268
448b8ca8
JD		 269 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
270 if it is null.
271 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 272 zero.
273
3107326d
AP		 2742019-01-09 Andrew Paprocki <andrew@ishiboo.com>
275
276 * configure: Regenerate.
277
7e9ca91e
AM		 2782019-01-07 Alan Modra <amodra@gmail.com>
279
280 * configure: Regenerate.
281 * po/POTFILES.in: Regenerate.
282
ef1ad42b
JD		 2832019-01-03 John Darrington <john@darrington.wattle.id.au>
284
285 * s12z-opc.c: New file.
286 * s12z-opc.h: New file.
287 * s12z-dis.c: Removed all code not directly related to display
288 of instructions. Used the interface provided by the new files
289 instead.
290 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 291 * Makefile.in: Regenerate.
ef1ad42b 292 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 293 * configure: Regenerate.
ef1ad42b 294
82704155
AM		 2952019-01-01 Alan Modra <amodra@gmail.com>
296
297 Update year range in copyright notice of all files.
298
d5c04e1b 299For older changes see ChangeLog-2018
3499769a 300\f
d5c04e1b 301Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 302
303Copying and distribution of this file, with or without modification,
304are permitted in any medium without royalty provided the copyright
305notice and this notice are preserved.
306
307Local Variables:
308mode: change-log
309left-margin: 8
310fill-column: 74
311version-control: never
312End:
GDB Binutils - Deliverables
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