[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
f21cce2c MW	1	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	2
	3	* aarch64-opc.c (F_ARCHEXT): New.
	4	(aarch64_sys_regs): Add "pan".
	5	(aarch64_sys_reg_supported_p): New.
	6	(aarch64_pstatefields): Add "pan".
	7	(aarch64_pstatefield_supported_p): New.
	8
d194d186 JB	9	2015-06-01 Jan Beulich <jbeulich@suse.com>
	10
	11	* i386-tbl.h: Regenerate.
	12
3a8547d2 JB	13	2015-06-01 Jan Beulich <jbeulich@suse.com>
	14
	15	* i386-dis.c (print_insn): Swap rounding mode specifier and
	16	general purpose register in Intel mode.
	17
015c54d5 JB	18	2015-06-01 Jan Beulich <jbeulich@suse.com>
	19
	20	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	21	* i386-tbl.h: Regenerate.
	22
071f0063 L	23	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	24
	25	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	26	* i386-init.h: Regenerated.
	27
5db04b09 L	28	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	29
	30	PR binutis/18386
	31	* i386-dis.c: Add comments for '@'.
	32	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	33	(enum x86_64_isa): New.
	34	(isa64): Likewise.
	35	(print_i386_disassembler_options): Add amd64 and intel64.
	36	(print_insn): Handle amd64 and intel64.
	37	(putop): Handle '@'.
	38	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	39	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	40	* i386-opc.h (AMD64): New.
	41	(CpuIntel64): Likewise.
	42	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	43	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	44	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	45	* i386-init.h: Regenerated.
	46	* i386-tbl.h: Likewise.
	47
4bc0608a PB	48	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	49
	50	* ppc-opc.c (IH) New define.
	51	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	52	<tlbie>: Add RS operand for POWER7.
	53	<slbia>: Add IH operand for POWER6.
	54
70cead07 L	55	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	56
	57	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	58	direct branch.
	59	(jmp): Likewise.
	60	* i386-tbl.h: Regenerated.
	61
7b6d09fb L	62	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	63
	64	* configure.ac: Support bfd_iamcu_arch.
	65	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	66	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	67	CPU_IAMCU_COMPAT_FLAGS.
	68	(cpu_flags): Add CpuIAMCU.
	69	* i386-opc.h (CpuIAMCU): New.
	70	(i386_cpu_flags): Add cpuiamcu.
	71	* configure: Regenerated.
	72	* i386-init.h: Likewise.
	73	* i386-tbl.h: Likewise.
	74
31955f99 L	75	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	76
	77	PR binutis/18386
	78	* i386-dis.c (X86_64_E8): New.
	79	(X86_64_E9): Likewise.
	80	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	81	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	82	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	83	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	84	(putop): Handle '^'.
	85	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	86	REX_W.
	87
0952813b DD	88	2015-04-30 DJ Delorie <dj@redhat.com>
	89
	90	* disassemble.c (disassembler): Choose suitable disassembler based
	91	on E_ABI.
	92	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	93	it to decode mul/div insns.
	94	* rl78-decode.c: Regenerate.
	95	* rl78-dis.c (print_insn_rl78): Rename to...
	96	(print_insn_rl78_common): ...this, take ISA parameter.
	97	(print_insn_rl78): New.
	98	(print_insn_rl78_g10): New.
	99	(print_insn_rl78_g13): New.
	100	(print_insn_rl78_g14): New.
	101	(rl78_get_disassembler): New.
	102
f9d3ecaa NC	103	2015-04-29 Nick Clifton <nickc@redhat.com>
	104
	105	* po/fr.po: Updated French translation.
	106
4fff86c5 PB	107	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	108
	109	* ppc-opc.c (DCBT_EO): New define.
	110	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	111	<lharx>: Likewise.
	112	<stbcx.>: Likewise.
	113	<sthcx.>: Likewise.
	114	<waitrsv>: Do not enable for POWER7 and later.
	115	<waitimpl>: Likewise.
	116	<dcbt>: Default to the two operand form of the instruction for all
	117	"old" cpus. For "new" cpus, use the operand ordering that matches
	118	whether the cpu is server or embedded.
	119	<dcbtst>: Likewise.
	120
3b78cfe1 AK	121	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	122
	123	* s390-opc.c: New instruction type VV0UU2.
	124	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	125	and WFC.
	126
04d824a4 JB	127	2015-04-23 Jan Beulich <jbeulich@suse.com>
	128
	129	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	130	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	131	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	132	(vfpclasspd, vfpclassps): Add %XZ.
	133
09708981 L	134	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	135
	136	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	137	(PREFIX_UD_REPZ): Likewise.
	138	(PREFIX_UD_REPNZ): Likewise.
	139	(PREFIX_UD_DATA): Likewise.
	140	(PREFIX_UD_ADDR): Likewise.
	141	(PREFIX_UD_LOCK): Likewise.
	142
3888916d L	143	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	144
	145	* i386-dis.c (prefix_requirement): Removed.
	146	(print_insn): Don't set prefix_requirement. Check
	147	dp->prefix_requirement instead of prefix_requirement.
	148
f24bcbaa L	149	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	150
	151	PR binutils/17898
	152	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	153	(PREFIX_MOD_0_0FC7_REG_6): This.
	154	(PREFIX_MOD_3_0FC7_REG_6): New.
	155	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	156	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	157	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	158	PREFIX_MOD_3_0FC7_REG_7.
	159	(mod_table): Replace PREFIX_0FC7_REG_6 with
	160	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	161	PREFIX_MOD_3_0FC7_REG_7.
	162
507bd325 L	163	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	164
	165	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	166	(PREFIX_MANDATORY_REPNZ): Likewise.
	167	(PREFIX_MANDATORY_DATA): Likewise.
	168	(PREFIX_MANDATORY_ADDR): Likewise.
	169	(PREFIX_MANDATORY_LOCK): Likewise.
	170	(PREFIX_MANDATORY): Likewise.
	171	(PREFIX_UD_SHIFT): Set to 8
	172	(PREFIX_UD_REPZ): Updated.
	173	(PREFIX_UD_REPNZ): Likewise.
	174	(PREFIX_UD_DATA): Likewise.
	175	(PREFIX_UD_ADDR): Likewise.
	176	(PREFIX_UD_LOCK): Likewise.
	177	(PREFIX_IGNORED_SHIFT): New.
	178	(PREFIX_IGNORED_REPZ): Likewise.
	179	(PREFIX_IGNORED_REPNZ): Likewise.
	180	(PREFIX_IGNORED_DATA): Likewise.
	181	(PREFIX_IGNORED_ADDR): Likewise.
	182	(PREFIX_IGNORED_LOCK): Likewise.
	183	(PREFIX_OPCODE): Likewise.
	184	(PREFIX_IGNORED): Likewise.
	185	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	186	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	187	(three_byte_table): Likewise.
	188	(mod_table): Likewise.
	189	(mandatory_prefix): Renamed to ...
	190	(prefix_requirement): This.
	191	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	192	Update PREFIX_90 entry.
	193	(get_valid_dis386): Check prefix_requirement to see if a prefix
	194	should be ignored.
	195	(print_insn): Replace mandatory_prefix with prefix_requirement.
	196
f0fba320 RL	197	2015-04-15 Renlin Li <renlin.li@arm.com>
	198
	199	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	200	use it for ssat and ssat16.
	201	(print_insn_thumb32): Add handle case for 'D' control code.
	202
bf890a93 IT	203	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	204	H.J. Lu <hongjiu.lu@intel.com>
	205
	206	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	207	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	208	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	209	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	210	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	211	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	212	Fill prefix_requirement field.
	213	(struct dis386): Add prefix_requirement field.
	214	(dis386): Fill prefix_requirement field.
	215	(dis386_twobyte): Ditto.
	216	(twobyte_has_mandatory_prefix_: Remove.
	217	(reg_table): Fill prefix_requirement field.
	218	(prefix_table): Ditto.
	219	(x86_64_table): Ditto.
	220	(three_byte_table): Ditto.
	221	(xop_table): Ditto.
	222	(vex_table): Ditto.
	223	(vex_len_table): Ditto.
	224	(vex_w_table): Ditto.
	225	(mod_table): Ditto.
	226	(bad_opcode): Ditto.
	227	(print_insn): Use prefix_requirement.
	228	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	229	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	230	(float_reg): Ditto.
	231
2f783c1f MF	232	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	233
	234	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	235
b9d94d62 L	236	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	237
	238	* Makefile.in: Regenerated.
	239
27c49e9a AB	240	2015-03-25 Anton Blanchard <anton@samba.org>
	241
	242	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	243	powerpc_opcd_indices and vle_opcd_indices once.
	244
c4e676f1 AB	245	2015-03-25 Anton Blanchard <anton@samba.org>
	246
	247	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	248
823d2571 TG	249	2015-03-24 Terry Guo <terry.guo@arm.com>
	250
	251	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	252	(opcode16): Likewise.
	253	(coprocessor_opcodes): Replace bit with feature struct.
	254	(neon_opcodes): Likewise.
	255	(arm_opcodes): Likewise.
	256	(thumb_opcodes): Likewise.
	257	(thumb32_opcodes): Likewise.
	258	(print_insn_coprocessor): Likewise.
	259	(print_insn_arm): Likewise.
	260	(select_arm_features): Follow new feature struct.
	261
029f3522 GG	262	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	263
	264	* i386-dis.c (rm_table): Add clzero.
	265	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	266	Add CPU_CLZERO_FLAGS.
	267	(cpu_flags): Add CpuCLZERO.
	268	* i386-opc.h: Add CpuCLZERO.
	269	* i386-opc.tbl: Add clzero.
	270	* i386-init.h: Re-generated.
	271	* i386-tbl.h: Re-generated.
	272
6914869a AB	273	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	274
	275	* mips-opc.c (decode_mips_operand): Fix constraint issues
	276	with u and y operands.
	277
21e20815 AB	278	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	279
	280	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	281
6b1d7593 AK	282	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	283
	284	* s390-opc.c: Add new IBM z13 instructions.
	285	* s390-opc.txt: Likewise.
	286
c8f89a34 JW	287	2015-03-10 Renlin Li <renlin.li@arm.com>
	288
	289	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	290	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	291	related alias.
	292	* aarch64-asm-2.c: Regenerate.
	293	* aarch64-dis-2.c: Likewise.
	294	* aarch64-opc-2.c: Likewise.
	295
d8282f0e JW	296	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	297
	298	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	299
ac994365 OE	300	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	301
	302	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	303	arch_sh_up.
	304	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	305	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	306
fd63f640 V	307	2015-02-23 Vinay <Vinay.G@kpit.com>
	308
	309	* rl78-decode.opc (MOV): Added space between two operands for
	310	'mov' instruction in index addressing mode.
	311	* rl78-decode.c: Regenerate.
	312
f63c1776 PA	313	2015-02-19 Pedro Alves <palves@redhat.com>
	314
	315	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	316
07774fcc PA	317	2015-02-10 Pedro Alves <palves@redhat.com>
	318	Tom Tromey <tromey@redhat.com>
	319
	320	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	321	microblaze_and, microblaze_xor.
	322	* microblaze-opc.h (opcodes): Adjust.
	323
3f8107ab AM	324	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	325
	326	* Makefile.am: Add FT32 files.
	327	* configure.ac: Handle FT32.
	328	* disassemble.c (disassembler): Call print_insn_ft32.
	329	* ft32-dis.c: New file.
	330	* ft32-opc.c: New file.
	331	* Makefile.in: Regenerate.
	332	* configure: Regenerate.
	333	* po/POTFILES.in: Regenerate.
	334
e5fe4957 KLC	335	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	336
	337	* nds32-asm.c (keyword_sr): Add new system registers.
	338
1e2e8c52 AK	339	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	340
	341	* s390-dis.c (s390_extract_operand): Support vector register
	342	operands.
	343	(s390_print_insn_with_opcode): Support new operands types and add
	344	new handling of optional operands.
	345	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	346	and include opcode/s390.h instead.
	347	(struct op_struct): New field `flags'.
	348	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	349	(dumpTable): Dump flags.
	350	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	351	string.
	352	* s390-opc.c: Add new operands types, instruction formats, and
	353	instruction masks.
	354	(s390_opformats): Add new formats for .insn.
	355	* s390-opc.txt: Add new instructions.
	356
b90efa5b	357	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	358
b90efa5b	359	Update year range in copyright notice of all files.
bffb6004	360
b90efa5b	361	For older changes see ChangeLog-2014
252b5132	362	\f
b90efa5b	363	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	364
	365	Copying and distribution of this file, with or without modification,
	366	are permitted in any medium without royalty provided the copyright
	367	notice and this notice are preserved.
	368
252b5132	369	Local Variables:
2f6d2f85 NC	370	mode: change-log
	371	left-margin: 8
	372	fill-column: 74
252b5132 RH	373	version-control: never
252b5132 RH	374	End: