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testsuite: Fix recent GCC FAIL: gdb.arch/i386-signal.exp
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
72da393d
L		 12016-09-30 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR binutils/20657
4 * i386-dis.c (putop): Don't assign alt twice.
5
744ce302
JW		 62016-09-29 Jiong Wang <jiong.wang@arm.com>
7
8 PR target/20553
9 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
10
a5721ba2
AM		 112016-09-29 Alan Modra <amodra@gmail.com>
12
13 * ppc-opc.c (L): Make compulsory.
14 (LOPT): New, optional form of L.
15 (HTM_R): Define as LOPT.
16 (L0, L1): Delete.
17 (L32OPT): New, optional for 32-bit L.
18 (L2OPT): New, 2-bit L for dcbf.
19 (SVC_LEC): Update.
20 (L2): Define.
21 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
22 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
23 <dcbf>: Use L2OPT.
24 <tlbiel, tlbie>: Use LOPT.
25 <wclr, wclrall>: Use L2.
26
c5da1932
VZ		 272016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
28
29 * Makefile.in: Regenerate.
30 * configure: Likewise.
31
2b848ebd
CZ		 322016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
33
34 * arc-ext-tbl.h (EXTINSN2OPF): Define.
35 (EXTINSN2OP): Use EXTINSN2OPF.
36 (bspeekm, bspop, modapp): New extension instructions.
37 * arc-opc.c (F_DNZ_ND): Define.
38 (F_DNZ_D): Likewise.
39 (F_SIZEB1): Changed.
40 (C_DNZ_D): Define.
41 (C_HARD): Changed.
42 * arc-tbl.h (dbnz): New instruction.
43 (prealloc): Allow it for ARC EM.
44 (xbfu): Likewise.
45
ad43e107
RS		 462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
47
48 * aarch64-opc.c (print_immediate_offset_address): Print spaces
49 after commas in addresses.
50 (aarch64_print_operand): Likewise.
51
ab3b8fcf
RS		 522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
53
54 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
55 rather than "should be" or "expected to be" in error messages.
56
bb7eff52
RS		 572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
58
59 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
60 (print_mnemonic_name): ...here.
61 (print_comment): New function.
62 (print_aarch64_insn): Call it.
63 * aarch64-opc.c (aarch64_conds): Add SVE names.
64 (aarch64_print_operand): Print alternative condition names in
65 a comment.
66
c0890d26
RS		 672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
68
69 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
70 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
71 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
72 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
73 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
74 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
75 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
76 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
77 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
78 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
79 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
80 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
81 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
82 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
83 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
84 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
85 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
86 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
87 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
88 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
89 (OP_SVE_XWU, OP_SVE_XXU): New macros.
90 (aarch64_feature_sve): New variable.
91 (SVE): New macro.
92 (_SVE_INSN): Likewise.
93 (aarch64_opcode_table): Add SVE instructions.
94 * aarch64-opc.h (extract_fields): Declare.
95 * aarch64-opc-2.c: Regenerate.
96 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
97 * aarch64-asm-2.c: Regenerate.
98 * aarch64-dis.c (extract_fields): Make global.
99 (do_misc_decoding): Handle the new SVE aarch64_ops.
100 * aarch64-dis-2.c: Regenerate.
101
116b6019
RS		 1022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
103
104 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
105 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
106 aarch64_field_kinds.
107 * aarch64-opc.c (fields): Add corresponding entries.
108 * aarch64-asm.c (aarch64_get_variant): New function.
109 (aarch64_encode_variant_using_iclass): Likewise.
110 (aarch64_opcode_encode): Call it.
111 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
112 (aarch64_opcode_decode): Call it.
113
047cd301
RS		 1142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
115
116 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
117 and FP register operands.
118 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
119 (FLD_SVE_Vn): New aarch64_field_kinds.
120 * aarch64-opc.c (fields): Add corresponding entries.
121 (aarch64_print_operand): Handle the new SVE core and FP register
122 operands.
123 * aarch64-opc-2.c: Regenerate.
124 * aarch64-asm-2.c: Likewise.
125 * aarch64-dis-2.c: Likewise.
126
165d4950
RS		 1272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
128
129 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
130 immediate operands.
131 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
132 * aarch64-opc.c (fields): Add corresponding entry.
133 (operand_general_constraint_met_p): Handle the new SVE FP immediate
134 operands.
135 (aarch64_print_operand): Likewise.
136 * aarch64-opc-2.c: Regenerate.
137 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
138 (ins_sve_float_zero_one): New inserters.
139 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
140 (aarch64_ins_sve_float_half_two): Likewise.
141 (aarch64_ins_sve_float_zero_one): Likewise.
142 * aarch64-asm-2.c: Regenerate.
143 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
144 (ext_sve_float_zero_one): New extractors.
145 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
146 (aarch64_ext_sve_float_half_two): Likewise.
147 (aarch64_ext_sve_float_zero_one): Likewise.
148 * aarch64-dis-2.c: Regenerate.
149
e950b345
RS		 1502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
151
152 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
153 integer immediate operands.
154 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
155 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
156 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
157 * aarch64-opc.c (fields): Add corresponding entries.
158 (operand_general_constraint_met_p): Handle the new SVE integer
159 immediate operands.
160 (aarch64_print_operand): Likewise.
161 (aarch64_sve_dupm_mov_immediate_p): New function.
162 * aarch64-opc-2.c: Regenerate.
163 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
164 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
165 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
166 (aarch64_ins_limm): ...here.
167 (aarch64_ins_inv_limm): New function.
168 (aarch64_ins_sve_aimm): Likewise.
169 (aarch64_ins_sve_asimm): Likewise.
170 (aarch64_ins_sve_limm_mov): Likewise.
171 (aarch64_ins_sve_shlimm): Likewise.
172 (aarch64_ins_sve_shrimm): Likewise.
173 * aarch64-asm-2.c: Regenerate.
174 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
175 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
176 * aarch64-dis.c (decode_limm): New function, split out from...
177 (aarch64_ext_limm): ...here.
178 (aarch64_ext_inv_limm): New function.
179 (decode_sve_aimm): Likewise.
180 (aarch64_ext_sve_aimm): Likewise.
181 (aarch64_ext_sve_asimm): Likewise.
182 (aarch64_ext_sve_limm_mov): Likewise.
183 (aarch64_top_bit): Likewise.
184 (aarch64_ext_sve_shlimm): Likewise.
185 (aarch64_ext_sve_shrimm): Likewise.
186 * aarch64-dis-2.c: Regenerate.
187
98907a70
RS		 1882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
189
190 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
191 operands.
192 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
193 the AARCH64_MOD_MUL_VL entry.
194 (value_aligned_p): Cope with non-power-of-two alignments.
195 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
196 (print_immediate_offset_address): Likewise.
197 (aarch64_print_operand): Likewise.
198 * aarch64-opc-2.c: Regenerate.
199 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
200 (ins_sve_addr_ri_s9xvl): New inserters.
201 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
202 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
203 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
204 * aarch64-asm-2.c: Regenerate.
205 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
206 (ext_sve_addr_ri_s9xvl): New extractors.
207 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
208 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
209 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
210 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
211 * aarch64-dis-2.c: Regenerate.
212
4df068de
RS		 2132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
214
215 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
216 address operands.
217 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
218 (FLD_SVE_xs_22): New aarch64_field_kinds.
219 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
220 (get_operand_specific_data): New function.
221 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
222 FLD_SVE_xs_14 and FLD_SVE_xs_22.
223 (operand_general_constraint_met_p): Handle the new SVE address
224 operands.
225 (sve_reg): New array.
226 (get_addr_sve_reg_name): New function.
227 (aarch64_print_operand): Handle the new SVE address operands.
228 * aarch64-opc-2.c: Regenerate.
229 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
230 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
231 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
232 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
233 (aarch64_ins_sve_addr_rr_lsl): Likewise.
234 (aarch64_ins_sve_addr_rz_xtw): Likewise.
235 (aarch64_ins_sve_addr_zi_u5): Likewise.
236 (aarch64_ins_sve_addr_zz): Likewise.
237 (aarch64_ins_sve_addr_zz_lsl): Likewise.
238 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
239 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
242 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
243 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
244 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
245 (aarch64_ext_sve_addr_ri_u6): Likewise.
246 (aarch64_ext_sve_addr_rr_lsl): Likewise.
247 (aarch64_ext_sve_addr_rz_xtw): Likewise.
248 (aarch64_ext_sve_addr_zi_u5): Likewise.
249 (aarch64_ext_sve_addr_zz): Likewise.
250 (aarch64_ext_sve_addr_zz_lsl): Likewise.
251 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
252 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
253 * aarch64-dis-2.c: Regenerate.
254
2442d846
RS		 2552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
256
257 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
258 AARCH64_OPND_SVE_PATTERN_SCALED.
259 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
260 * aarch64-opc.c (fields): Add a corresponding entry.
261 (set_multiplier_out_of_range_error): New function.
262 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
263 (operand_general_constraint_met_p): Handle
264 AARCH64_OPND_SVE_PATTERN_SCALED.
265 (print_register_offset_address): Use PRIi64 to print the
266 shift amount.
267 (aarch64_print_operand): Likewise. Handle
268 AARCH64_OPND_SVE_PATTERN_SCALED.
269 * aarch64-opc-2.c: Regenerate.
270 * aarch64-asm.h (ins_sve_scale): New inserter.
271 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
272 * aarch64-asm-2.c: Regenerate.
273 * aarch64-dis.h (ext_sve_scale): New inserter.
274 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
275 * aarch64-dis-2.c: Regenerate.
276
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RS		 2772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
278
279 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
280 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
281 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
282 (FLD_SVE_prfop): Likewise.
283 * aarch64-opc.c: Include libiberty.h.
284 (aarch64_sve_pattern_array): New variable.
285 (aarch64_sve_prfop_array): Likewise.
286 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
287 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
288 AARCH64_OPND_SVE_PRFOP.
289 * aarch64-asm-2.c: Regenerate.
290 * aarch64-dis-2.c: Likewise.
291 * aarch64-opc-2.c: Likewise.
292
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RS		 2932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
294
295 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
296 AARCH64_OPND_QLF_P_[ZM].
297 (aarch64_print_operand): Print /z and /m where appropriate.
298
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RS		 2992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
300
301 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
302 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
303 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
304 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
305 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
306 * aarch64-opc.c (fields): Add corresponding entries here.
307 (operand_general_constraint_met_p): Check that SVE register lists
308 have the correct length. Check the ranges of SVE index registers.
309 Check for cases where p8-p15 are used in 3-bit predicate fields.
310 (aarch64_print_operand): Handle the new SVE operands.
311 * aarch64-opc-2.c: Regenerate.
312 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
313 * aarch64-asm.c (aarch64_ins_sve_index): New function.
314 (aarch64_ins_sve_reglist): Likewise.
315 * aarch64-asm-2.c: Regenerate.
316 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
317 * aarch64-dis.c (aarch64_ext_sve_index): New function.
318 (aarch64_ext_sve_reglist): Likewise.
319 * aarch64-dis-2.c: Regenerate.
320
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RS		 3212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
322
323 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
324 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
325 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
326 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
327 tied operands.
328
01dbfe4c
RS		 3292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
330
331 * aarch64-opc.c (get_offset_int_reg_name): New function.
332 (print_immediate_offset_address): Likewise.
333 (print_register_offset_address): Take the base and offset
334 registers as parameters.
335 (aarch64_print_operand): Update caller accordingly. Use
336 print_immediate_offset_address.
337
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RS		 3382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
339
340 * aarch64-opc.c (BANK): New macro.
341 (R32, R64): Take a register number as argument
342 (int_reg): Use BANK.
343
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RS		 3442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
345
346 * aarch64-opc.c (print_register_list): Add a prefix parameter.
347 (aarch64_print_operand): Update accordingly.
348
aa2aa4c6
RS		 3492016-09-21 Richard Sandiford <richard.sandiford@arm.com>
350
351 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
352 for FPIMM.
353 * aarch64-asm.h (ins_fpimm): New inserter.
354 * aarch64-asm.c (aarch64_ins_fpimm): New function.
355 * aarch64-asm-2.c: Regenerate.
356 * aarch64-dis.h (ext_fpimm): New extractor.
357 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
358 (aarch64_ext_fpimm): New function.
359 * aarch64-dis-2.c: Regenerate.
360
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RS		 3612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
362
363 * aarch64-asm.c: Include libiberty.h.
364 (insert_fields): New function.
365 (aarch64_ins_imm): Use it.
366 * aarch64-dis.c (extract_fields): New function.
367 (aarch64_ext_imm): Use it.
368
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RS		 3692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
370
371 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
372 with an esize parameter.
373 (operand_general_constraint_met_p): Update accordingly.
374 Fix misindented code.
375 * aarch64-asm.c (aarch64_ins_limm): Update call to
376 aarch64_logical_immediate_p.
377
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RS		 3782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
379
380 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
381
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RS		 3822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
383
384 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
385
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CZ		 3862016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
387
388 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
389
fd486b63
PB		 3902016-09-14 Peter Bergner <bergner@vnet.ibm.com>
391
392 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
393 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
394 xor3>: Delete mnemonics.
395 <cp_abort>: Rename mnemonic from ...
396 <cpabort>: ...to this.
397 <setb>: Change to a X form instruction.
398 <sync>: Change to 1 operand form.
399 <copy>: Delete mnemonic.
400 <copy_first>: Rename mnemonic from ...
401 <copy>: ...to this.
402 <paste, paste.>: Delete mnemonics.
403 <paste_last>: Rename mnemonic from ...
404 <paste.>: ...to this.
405
dce08442
AK		 4062016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
407
408 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
409
952c3f51
AK		 4102016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
411
412 * s390-mkopc.c (main): Support alternate arch strings.
413
8b71537b
PS		 4142016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
415
416 * s390-opc.txt: Fix kmctr instruction type.
417
5b64d091
L		 4182016-09-07 H.J. Lu <hongjiu.lu@intel.com>
419
420 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
421 * i386-init.h: Regenerated.
422
7763838e
CM		 4232016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
424
425 * opcodes/arc-dis.c (print_insn_arc): Changed.
426
1b8b6532
JM		 4272016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
428
429 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
430 camellia_fl.
431
1a336194
TP		 4322016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
433
434 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
435 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
436 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
437
6b40c462
L		 4382016-08-24 H.J. Lu <hongjiu.lu@intel.com>
439
440 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
441 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
442 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
443 PREFIX_MOD_3_0FAE_REG_4.
444 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
445 PREFIX_MOD_3_0FAE_REG_4.
446 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
447 (cpu_flags): Add CpuPTWRITE.
448 * i386-opc.h (CpuPTWRITE): New.
449 (i386_cpu_flags): Add cpuptwrite.
450 * i386-opc.tbl: Add ptwrite instruction.
451 * i386-init.h: Regenerated.
452 * i386-tbl.h: Likewise.
453
ab548d2d
AK		 4542016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
455
456 * arc-dis.h: Wrap around in extern "C".
457
344bde0a
RS		 4582016-08-23 Richard Sandiford <richard.sandiford@arm.com>
459
460 * aarch64-tbl.h (V8_2_INSN): New macro.
461 (aarch64_opcode_table): Use it.
462
5ce912d8
RS		 4632016-08-23 Richard Sandiford <richard.sandiford@arm.com>
464
465 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
466 CORE_INSN, __FP_INSN and SIMD_INSN.
467
9d30b0bd
RS		 4682016-08-23 Richard Sandiford <richard.sandiford@arm.com>
469
470 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
471 (aarch64_opcode_table): Update uses accordingly.
472
dfdaec14
AJ		 4732016-07-25 Andrew Jenner <andrew@codesourcery.com>
474 Kwok Cheung Yeung <kcy@codesourcery.com>
475
476 opcodes/
477 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
478 'e_cmplwi' to 'e_cmpli' instead.
479 (OPVUPRT, OPVUPRT_MASK): Define.
480 (powerpc_opcodes): Add E200Z4 insns.
481 (vle_opcodes): Add context save/restore insns.
482
7bd374a4
MR		 4832016-07-27 Maciej W. Rozycki <macro@imgtec.com>
484
485 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
486 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
487 "j".
488
db18dbab
GM		 4892016-07-27 Graham Markall <graham.markall@embecosm.com>
490
491 * arc-nps400-tbl.h: Change block comments to GNU format.
492 * arc-dis.c: Add new globals addrtypenames,
493 addrtypenames_max, and addtypeunknown.
494 (get_addrtype): New function.
495 (print_insn_arc): Print colons and address types when
496 required.
497 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
498 define insert and extract functions for all address types.
499 (arc_operands): Add operands for colon and all address
500 types.
501 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
502 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
503 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
504 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
505 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
506 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
507
fecd57f9
L		 5082016-07-21 H.J. Lu <hongjiu.lu@intel.com>
509
510 * configure: Regenerated.
511
37fd5ef3
CZ		 5122016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
513
514 * arc-dis.c (skipclass): New structure.
515 (decodelist): New variable.
516 (is_compatible_p): New function.
517 (new_element): Likewise.
518 (skip_class_p): Likewise.
519 (find_format_from_table): Use skip_class_p function.
520 (find_format): Decode first the extension instructions.
521 (print_insn_arc): Select either ARCEM or ARCHS based on elf
522 e_flags.
523 (parse_option): New function.
524 (parse_disassembler_options): Likewise.
525 (print_arc_disassembler_options): Likewise.
526 (print_insn_arc): Use parse_disassembler_options function. Proper
527 select ARCv2 cpu variant.
528 * disassemble.c (disassembler_usage): Add ARC disassembler
529 options.
530
92281a5b
MR		 5312016-07-13 Maciej W. Rozycki <macro@imgtec.com>
532
533 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
534 annotation from the "nal" entry and reorder it beyond "bltzal".
535
6e7ced37
JM		 5362016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
537
538 * sparc-opc.c (ldtxa): New macro.
539 (sparc_opcodes): Use the macro defined above to add entries for
540 the LDTXA instructions.
541 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
542 instruction.
543
2f831b9a 5442016-07-07 James Bowman <james.bowman@ftdichip.com>
545
546 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
547 and "jmpc".
548
c07315e0
JB		 5492016-07-01 Jan Beulich <jbeulich@suse.com>
550
551 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
552 (movzb): Adjust to cover all permitted suffixes.
553 (movzw): New.
554 * i386-tbl.h: Re-generate.
555
9243100a
JB		 5562016-07-01 Jan Beulich <jbeulich@suse.com>
557
558 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
559 (lgdt): Remove Tbyte from non-64-bit variant.
560 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
561 xsaves64, xsavec64): Remove Disp16.
562 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
563 Remove Disp32S from non-64-bit variants. Remove Disp16 from
564 64-bit variants.
565 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
566 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
567 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
568 64-bit variants.
569 * i386-tbl.h: Re-generate.
570
8325cc63
JB		 5712016-07-01 Jan Beulich <jbeulich@suse.com>
572
573 * i386-opc.tbl (xlat): Remove RepPrefixOk.
574 * i386-tbl.h: Re-generate.
575
838441e4
YQ		 5762016-06-30 Yao Qi <yao.qi@linaro.org>
577
578 * arm-dis.c (print_insn): Fix typo in comment.
579
dab26bf4
RS		 5802016-06-28 Richard Sandiford <richard.sandiford@arm.com>
581
582 * aarch64-opc.c (operand_general_constraint_met_p): Check the
583 range of ldst_elemlist operands.
584 (print_register_list): Use PRIi64 to print the index.
585 (aarch64_print_operand): Likewise.
586
5703197e
TS		 5872016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
588
589 * mcore-opc.h: Remove sentinal.
590 * mcore-dis.c (print_insn_mcore): Adjust.
591
ce440d63
GM		 5922016-06-23 Graham Markall <graham.markall@embecosm.com>
593
594 * arc-opc.c: Correct description of availability of NPS400
595 features.
596
6fd3a02d
PB		 5972016-06-22 Peter Bergner <bergner@vnet.ibm.com>
598
599 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
600 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
601 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
602 xor3>: New mnemonics.
603 <setb>: Change to a VX form instruction.
604 (insert_sh6): Add support for rldixor.
605 (extract_sh6): Likewise.
606
6b477896
TS		 6072016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
608
609 * arc-ext.h: Wrap in extern C.
610
bdd582db
GM		 6112016-06-21 Graham Markall <graham.markall@embecosm.com>
612
613 * arc-dis.c (arc_insn_length): Add comment on instruction length.
614 Use same method for determining instruction length on ARC700 and
615 NPS-400.
616 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
617 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
618 with the NPS400 subclass.
619 * arc-opc.c: Likewise.
620
96074adc
JM		 6212016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
622
623 * sparc-opc.c (rdasr): New macro.
624 (wrasr): Likewise.
625 (rdpr): Likewise.
626 (wrpr): Likewise.
627 (rdhpr): Likewise.
628 (wrhpr): Likewise.
629 (sparc_opcodes): Use the macros above to fix and expand the
630 definition of read/write instructions from/to
631 asr/privileged/hyperprivileged instructions.
632 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
633 %hva_mask_nz. Prefer softint_set and softint_clear over
634 set_softint and clear_softint.
635 (print_insn_sparc): Support %ver in Rd.
636
7a10c22f
JM		 6372016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
638
639 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
640 architecture according to the hardware capabilities they require.
641
4f26fb3a
JM		 6422016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
643
644 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
645 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
646 bfd_mach_sparc_v9{c,d,e,v,m}.
647 * sparc-opc.c (MASK_V9C): Define.
648 (MASK_V9D): Likewise.
649 (MASK_V9E): Likewise.
650 (MASK_V9V): Likewise.
651 (MASK_V9M): Likewise.
652 (v6): Add MASK_V9{C,D,E,V,M}.
653 (v6notlet): Likewise.
654 (v7): Likewise.
655 (v8): Likewise.
656 (v9): Likewise.
657 (v9andleon): Likewise.
658 (v9a): Likewise.
659 (v9b): Likewise.
660 (v9c): Define.
661 (v9d): Likewise.
662 (v9e): Likewise.
663 (v9v): Likewise.
664 (v9m): Likewise.
665 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
666
3ee6e4fb
NC		 6672016-06-15 Nick Clifton <nickc@redhat.com>
668
669 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
670 constants to match expected behaviour.
671 (nds32_parse_opcode): Likewise. Also for whitespace.
672
02f3be19
AB		 6732016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
674
675 * arc-opc.c (extract_rhv1): Extract value from insn.
676
6f9f37ed 6772016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 678
679 * arc-nps400-tbl.h: Add ldbit instruction.
680 * arc-opc.c: Add flag classes required for ldbit.
681
6f9f37ed 6822016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 683
684 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
685 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
686 support the above instructions.
687
6f9f37ed 6882016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 689
690 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
691 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
692 csma, cbba, zncv, and hofs.
693 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
694 support the above instructions.
695
6962016-06-06 Graham Markall <graham.markall@embecosm.com>
697
698 * arc-nps400-tbl.h: Add andab and orab instructions.
699
7002016-06-06 Graham Markall <graham.markall@embecosm.com>
701
702 * arc-nps400-tbl.h: Add addl-like instructions.
703
7042016-06-06 Graham Markall <graham.markall@embecosm.com>
705
706 * arc-nps400-tbl.h: Add mxb and imxb instructions.
707
7082016-06-06 Graham Markall <graham.markall@embecosm.com>
709
710 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
711 instructions.
712
b2cc3f6f
AK		 7132016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
714
715 * s390-dis.c (option_use_insn_len_bits_p): New file scope
716 variable.
717 (init_disasm): Handle new command line option "insnlength".
718 (print_s390_disassembler_options): Mention new option in help
719 output.
720 (print_insn_s390): Use the encoded insn length when dumping
721 unknown instructions.
722
1857fe72
DC		 7232016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
724
725 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
726 to the address and set as symbol address for LDS/ STS immediate operands.
727
14b57c7c
AM		 7282016-06-07 Alan Modra <amodra@gmail.com>
729
730 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
731 cpu for "vle" to e500.
732 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
733 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
734 (PPCNONE): Delete, substitute throughout.
735 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
736 except for major opcode 4 and 31.
737 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
738
4d1464f2
MW		 7392016-06-07 Matthew Wahab <matthew.wahab@arm.com>
740
741 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
742 ARM_EXT_RAS in relevant entries.
743
026122a6
PB		 7442016-06-03 Peter Bergner <bergner@vnet.ibm.com>
745
746 PR binutils/20196
747 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
748 opcodes for E6500.
749
07f5af7d
L		 7502016-06-03 H.J. Lu <hongjiu.lu@intel.com>
751
752 PR binutis/18386
753 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
754 (indir_v_mode): New.
755 Add comments for '&'.
756 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
757 (putop): Handle '&'.
758 (intel_operand_size): Handle indir_v_mode.
759 (OP_E_register): Likewise.
760 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
761 64-bit indirect call/jmp for AMD64.
762 * i386-tbl.h: Regenerated
763
4eb6f892
AB		 7642016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
765
766 * arc-dis.c (struct arc_operand_iterator): New structure.
767 (find_format_from_table): All the old content from find_format,
768 with some minor adjustments, and parameter renaming.
769 (find_format_long_instructions): New function.
770 (find_format): Rewritten.
771 (arc_insn_length): Add LSB parameter.
772 (extract_operand_value): New function.
773 (operand_iterator_next): New function.
774 (print_insn_arc): Use new functions to find opcode, and iterator
775 over operands.
776 * arc-opc.c (insert_nps_3bit_dst_short): New function.
777 (extract_nps_3bit_dst_short): New function.
778 (insert_nps_3bit_src2_short): New function.
779 (extract_nps_3bit_src2_short): New function.
780 (insert_nps_bitop1_size): New function.
781 (extract_nps_bitop1_size): New function.
782 (insert_nps_bitop2_size): New function.
783 (extract_nps_bitop2_size): New function.
784 (insert_nps_bitop_mod4_msb): New function.
785 (extract_nps_bitop_mod4_msb): New function.
786 (insert_nps_bitop_mod4_lsb): New function.
787 (extract_nps_bitop_mod4_lsb): New function.
788 (insert_nps_bitop_dst_pos3_pos4): New function.
789 (extract_nps_bitop_dst_pos3_pos4): New function.
790 (insert_nps_bitop_ins_ext): New function.
791 (extract_nps_bitop_ins_ext): New function.
792 (arc_operands): Add new operands.
793 (arc_long_opcodes): New global array.
794 (arc_num_long_opcodes): New global.
795 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
796
1fe0971e
TS		 7972016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
798
799 * nds32-asm.h: Add extern "C".
800 * sh-opc.h: Likewise.
801
315f180f
GM		 8022016-06-01 Graham Markall <graham.markall@embecosm.com>
803
804 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
805 0,b,limm to the rflt instruction.
806
a2b5fccc
TS		 8072016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
808
809 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
810 constant.
811
0cbd0046
L		 8122016-05-29 H.J. Lu <hongjiu.lu@intel.com>
813
814 PR gas/20145
815 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
816 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
817 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
818 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
819 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
820 * i386-init.h: Regenerated.
821
1848e567
L		 8222016-05-27 H.J. Lu <hongjiu.lu@intel.com>
823
824 PR gas/20145
825 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
826 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
827 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
828 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
829 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
830 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
831 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
832 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
833 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
834 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
835 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
836 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
837 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
838 CpuRegMask for AVX512.
839 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
840 and CpuRegMask.
841 (set_bitfield_from_cpu_flag_init): New function.
842 (set_bitfield): Remove const on f. Call
843 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
844 * i386-opc.h (CpuRegMMX): New.
845 (CpuRegXMM): Likewise.
846 (CpuRegYMM): Likewise.
847 (CpuRegZMM): Likewise.
848 (CpuRegMask): Likewise.
849 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
850 and cpuregmask.
851 * i386-init.h: Regenerated.
852 * i386-tbl.h: Likewise.
853
e92bae62
L		 8542016-05-27 H.J. Lu <hongjiu.lu@intel.com>
855
856 PR gas/20154
857 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
858 (opcode_modifiers): Add AMD64 and Intel64.
859 (main): Properly verify CpuMax.
860 * i386-opc.h (CpuAMD64): Removed.
861 (CpuIntel64): Likewise.
862 (CpuMax): Set to CpuNo64.
863 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
864 (AMD64): New.
865 (Intel64): Likewise.
866 (i386_opcode_modifier): Add amd64 and intel64.
867 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
868 on call and jmp.
869 * i386-init.h: Regenerated.
870 * i386-tbl.h: Likewise.
871
e89c5eaa
L		 8722016-05-27 H.J. Lu <hongjiu.lu@intel.com>
873
874 PR gas/20154
875 * i386-gen.c (main): Fail if CpuMax is incorrect.
876 * i386-opc.h (CpuMax): Set to CpuIntel64.
877 * i386-tbl.h: Regenerated.
878
77d66e7b
NC		 8792016-05-27 Nick Clifton <nickc@redhat.com>
880
881 PR target/20150
882 * msp430-dis.c (msp430dis_read_two_bytes): New function.
883 (msp430dis_opcode_unsigned): New function.
884 (msp430dis_opcode_signed): New function.
885 (msp430_singleoperand): Use the new opcode reading functions.
886 Only disassenmble bytes if they were successfully read.
887 (msp430_doubleoperand): Likewise.
888 (msp430_branchinstr): Likewise.
889 (msp430x_callx_instr): Likewise.
890 (print_insn_msp430): Check that it is safe to read bytes before
891 attempting disassembly. Use the new opcode reading functions.
892
19dfcc89
PB		 8932016-05-26 Peter Bergner <bergner@vnet.ibm.com>
894
895 * ppc-opc.c (CY): New define. Document it.
896 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
897
f3ad7637
L		 8982016-05-25 H.J. Lu <hongjiu.lu@intel.com>
899
900 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
901 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
902 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
903 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
904 CPU_ANY_AVX_FLAGS.
905 * i386-init.h: Regenerated.
906
f1360d58
L		 9072016-05-25 H.J. Lu <hongjiu.lu@intel.com>
908
909 PR gas/20141
910 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
911 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
912 * i386-init.h: Regenerated.
913
293f5f65
L		 9142016-05-25 H.J. Lu <hongjiu.lu@intel.com>
915
916 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
917 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
918 * i386-init.h: Regenerated.
919
d9eca1df
CZ		 9202016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
921
922 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
923 information.
924 (print_insn_arc): Set insn_type information.
925 * arc-opc.c (C_CC): Add F_CLASS_COND.
926 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
927 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
928 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
929 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
930 (brne, brne_s, jeq_s, jne_s): Likewise.
931
87789e08
CZ		 9322016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
933
934 * arc-tbl.h (neg): New instruction variant.
935
c810e0b8
CZ		 9362016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
937
938 * arc-dis.c (find_format, find_format, get_auxreg)
939 (print_insn_arc): Changed.
940 * arc-ext.h (INSERT_XOP): Likewise.
941
3d207518
TS		 9422016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
943
944 * tic54x-dis.c (sprint_mmr): Adjust.
945 * tic54x-opc.c: Likewise.
946
514e58b7
AM		 9472016-05-19 Alan Modra <amodra@gmail.com>
948
949 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
950
e43de63c
AM		 9512016-05-19 Alan Modra <amodra@gmail.com>
952
953 * ppc-opc.c: Formatting.
954 (NSISIGNOPT): Define.
955 (powerpc_opcodes <subis>): Use NSISIGNOPT.
956
1401d2fe
MR		 9572016-05-18 Maciej W. Rozycki <macro@imgtec.com>
958
959 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
960 replacing references to `micromips_ase' throughout.
961 (_print_insn_mips): Don't use file-level microMIPS annotation to
962 determine the disassembly mode with the symbol table.
963
1178da44
PB		 9642016-05-13 Peter Bergner <bergner@vnet.ibm.com>
965
966 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
967
8f4f9071
MF		 9682016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
969
970 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
971 mips64r6.
972 * mips-opc.c (D34): New macro.
973 (mips_builtin_opcodes): Define bposge32c for DSPr3.
974
8bc52696
AF		 9752016-05-10 Alexander Fomin <alexander.fomin@intel.com>
976
977 * i386-dis.c (prefix_table): Add RDPID instruction.
978 * i386-gen.c (cpu_flag_init): Add RDPID flag.
979 (cpu_flags): Add RDPID bitfield.
980 * i386-opc.h (enum): Add RDPID element.
981 (i386_cpu_flags): Add RDPID field.
982 * i386-opc.tbl: Add RDPID instruction.
983 * i386-init.h: Regenerate.
984 * i386-tbl.h: Regenerate.
985
39d911fc
TP		 9862016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
987
988 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
989 branch type of a symbol.
990 (print_insn): Likewise.
991
16a1fa25
TP		 9922016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
993
994 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
995 Mainline Security Extensions instructions.
996 (thumb_opcodes): Add entries for narrow ARMv8-M Security
997 Extensions instructions.
998 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
999 instructions.
1000 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1001 special registers.
1002
d751b79e
JM		 10032016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1004
1005 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1006
945e0f82
CZ		 10072016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1008
1009 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1010 (arcExtMap_genOpcode): Likewise.
1011 * arc-opc.c (arg_32bit_rc): Define new variable.
1012 (arg_32bit_u6): Likewise.
1013 (arg_32bit_limm): Likewise.
1014
20f55f38
SN		 10152016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1016
1017 * aarch64-gen.c (VERIFIER): Define.
1018 * aarch64-opc.c (VERIFIER): Define.
1019 (verify_ldpsw): Use static linkage.
1020 * aarch64-opc.h (verify_ldpsw): Remove.
1021 * aarch64-tbl.h: Use VERIFIER for verifiers.
1022
4bd13cde
NC		 10232016-04-28 Nick Clifton <nickc@redhat.com>
1024
1025 PR target/19722
1026 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1027 * aarch64-opc.c (verify_ldpsw): New function.
1028 * aarch64-opc.h (verify_ldpsw): New prototype.
1029 * aarch64-tbl.h: Add initialiser for verifier field.
1030 (LDPSW): Set verifier to verify_ldpsw.
1031
c0f92bf9
L		 10322016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1033
1034 PR binutils/19983
1035 PR binutils/19984
1036 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1037 smaller than address size.
1038
e6c7cdec
TS		 10392016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1040
1041 * alpha-dis.c: Regenerate.
1042 * crx-dis.c: Likewise.
1043 * disassemble.c: Likewise.
1044 * epiphany-opc.c: Likewise.
1045 * fr30-opc.c: Likewise.
1046 * frv-opc.c: Likewise.
1047 * ip2k-opc.c: Likewise.
1048 * iq2000-opc.c: Likewise.
1049 * lm32-opc.c: Likewise.
1050 * lm32-opinst.c: Likewise.
1051 * m32c-opc.c: Likewise.
1052 * m32r-opc.c: Likewise.
1053 * m32r-opinst.c: Likewise.
1054 * mep-opc.c: Likewise.
1055 * mt-opc.c: Likewise.
1056 * or1k-opc.c: Likewise.
1057 * or1k-opinst.c: Likewise.
1058 * tic80-opc.c: Likewise.
1059 * xc16x-opc.c: Likewise.
1060 * xstormy16-opc.c: Likewise.
1061
537aefaf
AB		 10622016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1063
1064 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1065 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1066 calcsd, and calcxd instructions.
1067 * arc-opc.c (insert_nps_bitop_size): Delete.
1068 (extract_nps_bitop_size): Delete.
1069 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1070 (extract_nps_qcmp_m3): Define.
1071 (extract_nps_qcmp_m2): Define.
1072 (extract_nps_qcmp_m1): Define.
1073 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1074 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1075 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1076 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1077 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1078 NPS_QCMP_M3.
1079
c8f785f2
AB		 10802016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1081
1082 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1083
6fd8e7c2
L		 10842016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1085
1086 * Makefile.in: Regenerated with automake 1.11.6.
1087 * aclocal.m4: Likewise.
1088
4b0c052e
AB		 10892016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1090
1091 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1092 instructions.
1093 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1094 (extract_nps_cmem_uimm16): New function.
1095 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1096
cb040366
AB		 10972016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1098
1099 * arc-dis.c (arc_insn_length): New function.
1100 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1101 (find_format): Change insnLen parameter to unsigned.
1102
accc0180
NC		 11032016-04-13 Nick Clifton <nickc@redhat.com>
1104
1105 PR target/19937
1106 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1107 the LD.B and LD.BU instructions.
1108
f36e33da
CZ		 11092016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1110
1111 * arc-dis.c (find_format): Check for extension flags.
1112 (print_flags): New function.
1113 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1114 .extAuxRegister.
1115 * arc-ext.c (arcExtMap_coreRegName): Use
1116 LAST_EXTENSION_CORE_REGISTER.
1117 (arcExtMap_coreReadWrite): Likewise.
1118 (dump_ARC_extmap): Update printing.
1119 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1120 (arc_aux_regs): Add cpu field.
1121 * arc-regs.h: Add cpu field, lower case name aux registers.
1122
1c2e355e
CZ		 11232016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1124
1125 * arc-tbl.h: Add rtsc, sleep with no arguments.
1126
b99747ae
CZ		 11272016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1128
1129 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1130 Initialize.
1131 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1132 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1133 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1134 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1135 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1136 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1137 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1138 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1139 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1140 (arc_opcode arc_opcodes): Null terminate the array.
1141 (arc_num_opcodes): Remove.
1142 * arc-ext.h (INSERT_XOP): Define.
1143 (extInstruction_t): Likewise.
1144 (arcExtMap_instName): Delete.
1145 (arcExtMap_insn): New function.
1146 (arcExtMap_genOpcode): Likewise.
1147 * arc-ext.c (ExtInstruction): Remove.
1148 (create_map): Zero initialize instruction fields.
1149 (arcExtMap_instName): Remove.
1150 (arcExtMap_insn): New function.
1151 (dump_ARC_extmap): More info while debuging.
1152 (arcExtMap_genOpcode): New function.
1153 * arc-dis.c (find_format): New function.
1154 (print_insn_arc): Use find_format.
1155 (arc_get_disassembler): Enable dump_ARC_extmap only when
1156 debugging.
1157
92708cec
MR		 11582016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1159
1160 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1161 instruction bits out.
1162
a42a4f84
AB		 11632016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1164
1165 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1166 * arc-opc.c (arc_flag_operands): Add new flags.
1167 (arc_flag_classes): Add new classes.
1168
1328504b
AB		 11692016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1170
1171 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1172
820f03ff
AB		 11732016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1174
1175 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1176 encode1, rflt, crc16, and crc32 instructions.
1177 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1178 (arc_flag_classes): Add C_NPS_R.
1179 (insert_nps_bitop_size_2b): New function.
1180 (extract_nps_bitop_size_2b): Likewise.
1181 (insert_nps_bitop_uimm8): Likewise.
1182 (extract_nps_bitop_uimm8): Likewise.
1183 (arc_operands): Add new operand entries.
1184
8ddf6b2a
CZ		 11852016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1186
b99747ae
CZ		 1187 * arc-regs.h: Add a new subclass field. Add double assist
1188 accumulator register values.
1189 * arc-tbl.h: Use DPA subclass to mark the double assist
1190 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1191 * arc-opc.c (RSP): Define instead of SP.
1192 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1193
589a7d88
JW		 11942016-04-05 Jiong Wang <jiong.wang@arm.com>
1195
1196 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1197
0a191de9 11982016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1199
1200 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1201 NPS_R_SRC1.
1202
0a106562
AB		 12032016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1204
1205 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1206 issues. No functional changes.
1207
bd05ac5f
CZ		 12082016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1209
b99747ae
CZ		 1210 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1211 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1212 (RTT): Remove duplicate.
1213 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1214 (PCT_CONFIG*): Remove.
1215 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1216
9885948f
CZ		 12172016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1218
b99747ae 1219 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1220
f2dd8838
CZ		 12212016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1222
b99747ae
CZ		 1223 * arc-tbl.h (invld07): Remove.
1224 * arc-ext-tbl.h: New file.
1225 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1226 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1227
0d2f91fe
JK		 12282016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1229
1230 Fix -Wstack-usage warnings.
1231 * aarch64-dis.c (print_operands): Substitute size.
1232 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1233
a6b71f42
JM		 12342016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1235
1236 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1237 to get a proper diagnostic when an invalid ASR register is used.
1238
9780e045
NC		 12392016-03-22 Nick Clifton <nickc@redhat.com>
1240
1241 * configure: Regenerate.
1242
e23e8ebe
AB		 12432016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1244
1245 * arc-nps400-tbl.h: New file.
1246 * arc-opc.c: Add top level comment.
1247 (insert_nps_3bit_dst): New function.
1248 (extract_nps_3bit_dst): New function.
1249 (insert_nps_3bit_src2): New function.
1250 (extract_nps_3bit_src2): New function.
1251 (insert_nps_bitop_size): New function.
1252 (extract_nps_bitop_size): New function.
1253 (arc_flag_operands): Add nps400 entries.
1254 (arc_flag_classes): Add nps400 entries.
1255 (arc_operands): Add nps400 entries.
1256 (arc_opcodes): Add nps400 include.
1257
1ae8ab47
AB		 12582016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1259
1260 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1261 the new class enum values.
1262
8699fc3e
AB		 12632016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1264
1265 * arc-dis.c (print_insn_arc): Handle nps400.
1266
24740d83
AB		 12672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1268
1269 * arc-opc.c (BASE): Delete.
1270
8678914f
NC		 12712016-03-18 Nick Clifton <nickc@redhat.com>
1272
1273 PR target/19721
1274 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1275 of MOV insn that aliases an ORR insn.
1276
cc933301
JW		 12772016-03-16 Jiong Wang <jiong.wang@arm.com>
1278
1279 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1280
f86f5863
TS		 12812016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1282
1283 * mcore-opc.h: Add const qualifiers.
1284 * microblaze-opc.h (struct op_code_struct): Likewise.
1285 * sh-opc.h: Likewise.
1286 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1287 (tic4x_print_op): Likewise.
1288
62de1c63
AM		 12892016-03-02 Alan Modra <amodra@gmail.com>
1290
d11698cd 1291 * or1k-desc.h: Regenerate.
62de1c63 1292 * fr30-ibld.c: Regenerate.
c697cf0b 1293 * rl78-decode.c: Regenerate.
62de1c63 1294
020efce5
NC		 12952016-03-01 Nick Clifton <nickc@redhat.com>
1296
1297 PR target/19747
1298 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1299
b0c11777
RL		 13002016-02-24 Renlin Li <renlin.li@arm.com>
1301
1302 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1303 (print_insn_coprocessor): Support fp16 instructions.
1304
3e309328
RL		 13052016-02-24 Renlin Li <renlin.li@arm.com>
1306
1307 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1308 vminnm, vrint(mpna).
1309
8afc7bea
RL		 13102016-02-24 Renlin Li <renlin.li@arm.com>
1311
1312 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1313 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1314
4fd7268a
L		 13152016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1316
1317 * i386-dis.c (print_insn): Parenthesize expression to prevent
1318 truncated addresses.
1319 (OP_J): Likewise.
1320
4670103e
CZ		 13212016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1322 Janek van Oirschot <jvanoirs@synopsys.com>
1323
b99747ae
CZ		 1324 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1325 variable.
4670103e 1326
c1d9289f
NC		 13272016-02-04 Nick Clifton <nickc@redhat.com>
1328
1329 PR target/19561
1330 * msp430-dis.c (print_insn_msp430): Add a special case for
1331 decoding an RRC instruction with the ZC bit set in the extension
1332 word.
1333
a143b004
AB		 13342016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1335
1336 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1337 * epiphany-ibld.c: Regenerate.
1338 * fr30-ibld.c: Regenerate.
1339 * frv-ibld.c: Regenerate.
1340 * ip2k-ibld.c: Regenerate.
1341 * iq2000-ibld.c: Regenerate.
1342 * lm32-ibld.c: Regenerate.
1343 * m32c-ibld.c: Regenerate.
1344 * m32r-ibld.c: Regenerate.
1345 * mep-ibld.c: Regenerate.
1346 * mt-ibld.c: Regenerate.
1347 * or1k-ibld.c: Regenerate.
1348 * xc16x-ibld.c: Regenerate.
1349 * xstormy16-ibld.c: Regenerate.
1350
b89807c6
AB		 13512016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1352
1353 * epiphany-dis.c: Regenerated from latest cpu files.
1354
d8c823c8
MM		 13552016-02-01 Michael McConville <mmcco@mykolab.com>
1356
1357 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1358 test bit.
1359
5bc5ae88
RL		 13602016-01-25 Renlin Li <renlin.li@arm.com>
1361
1362 * arm-dis.c (mapping_symbol_for_insn): New function.
1363 (find_ifthen_state): Call mapping_symbol_for_insn().
1364
0bff6e2d
MW		 13652016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1366
1367 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1368 of MSR UAO immediate operand.
1369
100b4f2e
MR		 13702016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1371
1372 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1373 instruction support.
1374
5c14705f
AM		 13752016-01-17 Alan Modra <amodra@gmail.com>
1376
1377 * configure: Regenerate.
1378
4d82fe66
NC		 13792016-01-14 Nick Clifton <nickc@redhat.com>
1380
1381 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1382 instructions that can support stack pointer operations.
1383 * rl78-decode.c: Regenerate.
1384 * rl78-dis.c: Fix display of stack pointer in MOVW based
1385 instructions.
1386
651657fa
MW		 13872016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1388
1389 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1390 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1391 erxtatus_el1 and erxaddr_el1.
1392
105bde57
MW		 13932016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1394
1395 * arm-dis.c (arm_opcodes): Add "esb".
1396 (thumb_opcodes): Likewise.
1397
afa8d405
PB		 13982016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1399
1400 * ppc-opc.c <xscmpnedp>: Delete.
1401 <xvcmpnedp>: Likewise.
1402 <xvcmpnedp.>: Likewise.
1403 <xvcmpnesp>: Likewise.
1404 <xvcmpnesp.>: Likewise.
1405
83c3256e
AS		 14062016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1407
1408 PR gas/13050
1409 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1410 addition to ISA_A.
1411
6f2750fe
AM		 14122016-01-01 Alan Modra <amodra@gmail.com>
1413
1414 Update year range in copyright notice of all files.
1415
3499769a
AM		 1416For older changes see ChangeLog-2015
1417\f
1418Copyright (C) 2016 Free Software Foundation, Inc.
1419
1420Copying and distribution of this file, with or without modification,
1421are permitted in any medium without royalty provided the copyright
1422notice and this notice are preserved.
1423
1424Local Variables:
1425mode: change-log
1426left-margin: 8
1427fill-column: 74
1428version-control: never
1429End:
GDB Binutils - Deliverables
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