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[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f3aa142b
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_V2SAMEH): New.
7 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
8 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
9 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
10 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
11 and fsqrt to the vector register misc. group.
12
6b4680fb
MW		 132015-12-14 Matthew Wahab <matthew.wahab@arm.com>
14
15 * aarch64-asm-2.c: Regenerate.
16 * aarch64-dis-2.c: Regenerate.
17 * aarch64-opc-2.c: Regenerate.
18 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
19 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
20 to the scalar three same group.
21
51d543ed
MW		 222015-12-14 Matthew Wahab <matthew.wahab@arm.com>
23
24 * aarch64-asm-2.c: Regenerate.
25 * aarch64-dis-2.c: Regenerate.
26 * aarch64-opc-2.c: Regenerate.
27 * aarch64-tbl.h (QL_V3SAMEH): New.
28 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
29 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
30 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
31 fcmgt, facgt and fminp to the vector three same group.
32
40d16a76
MW		 332015-12-14 Matthew Wahab <matthew.wahab@arm.com>
34
35 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
36 (SIMD_F16): New.
37
63511907
MW		 382015-12-14 Matthew Wahab <matthew.wahab@arm.com>
39
40 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
41 removed statement.
42 (aarch64_pstatefield_supported_p): Move feature checks for AT
43 registers ..
44 (aarch64_sys_ins_reg_supported_p): .. to here.
45
b817670b
AM		 462015-12-12 Alan Modra <amodra@gmail.com>
47
48 PR 19359
49 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
50 (powerpc_opcodes): Remove single-operand mfcr.
51
9ed608f9
MW		 522015-12-11 Matthew Wahab <matthew.wahab@arm.com>
53
54 * aarch64-asm.c (aarch64_ins_hint): New.
55 * aarch64-asm.h (aarch64_ins_hint): Declare.
56 * aarch64-dis.c (aarch64_ext_hint): New.
57 * aarch64-dis.h (aarch64_ext_hint): Declare.
58 * aarch64-opc-2.c: Regenerate.
59 * aarch64-opc.c (aarch64_hint_options): New.
60 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
61
a0f7013a
MW		 622015-12-11 Matthew Wahab <matthew.wahab@arm.com>
63
64 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
65
55c144e6
MW		 662015-12-11 Matthew Wahab <matthew.wahab@arm.com>
67
68 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
69 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
70 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
71 pmscr_el2.
72 (aarch64_sys_reg_supported_p): Add architecture feature tests for
73 the new registers.
74
22a5455c
MW		 752015-12-10 Matthew Wahab <matthew.wahab@arm.com>
76
77 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
78 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
79 feature test for "s1e1rp" and "s1e1wp".
80
d6bf7ce6
MW		 812015-12-10 Matthew Wahab <matthew.wahab@arm.com>
82
83 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
84 (aarch64_sys_ins_reg_supported_p): New.
85
ea2deeec
MW		 862015-12-10 Matthew Wahab <matthew.wahab@arm.com>
87
88 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
89 with aarch64_sys_ins_reg_has_xt.
90 (aarch64_ext_sysins_op): Likewise.
91 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
92 (F_HASXT): New.
93 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
94 (aarch64_sys_regs_dc): Likewise.
95 (aarch64_sys_regs_at): Likewise.
96 (aarch64_sys_regs_tlbi): Likewise.
97 (aarch64_sys_ins_reg_has_xt): New.
98
6479e48e
MW		 992015-12-10 Matthew Wahab <matthew.wahab@arm.com>
100
101 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
102 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
103 (aarch64_pstatefields): Add "uao".
104 (aarch64_pstatefield_supported_p): Add checks for "uao".
105
47f81142
MW		 1062015-12-10 Matthew Wahab <matthew.wahab@arm.com>
107
108 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
109 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
110 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
111 (aarch64_sys_reg_supported_p): Add architecture feature tests for
112 new registers.
113
c8a6db6f
MW		 1142015-12-10 Matthew Wahab <matthew.wahab@arm.com>
115
116 * aarch64-asm-2.c: Regenerate.
117 * aarch64-dis-2.c: Regenerate.
118 * aarch64-tbl.h (aarch64_feature_ras): New.
119 (RAS): New.
120 (aarch64_opcode_table): Add "esb".
121
8eab4136
L		 1222015-12-09 H.J. Lu <hongjiu.lu@intel.com>
123
124 * i386-dis.c (MOD_0F01_REG_5): New.
125 (RM_0F01_REG_5): Likewise.
126 (reg_table): Use MOD_0F01_REG_5.
127 (mod_table): Add MOD_0F01_REG_5.
128 (rm_table): Add RM_0F01_REG_5.
129 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
130 (cpu_flags): Add CpuOSPKE.
131 * i386-opc.h (CpuOSPKE): New.
132 (i386_cpu_flags): Add cpuospke.
133 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
134 * i386-init.h: Regenerated.
135 * i386-tbl.h: Likewise.
136
1eac08cc
DD		 1372015-12-07 DJ Delorie <dj@redhat.com>
138
139 * rl78-decode.opc: Enable MULU for all ISAs.
140 * rl78-decode.c: Regenerate.
141
dd2887fc
AM		 1422015-12-07 Alan Modra <amodra@gmail.com>
143
144 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
145 major opcode/xop.
146
24b368f8
CZ		 1472015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
148
149 * arc-dis.c (special_flag_p): Match full mnemonic.
150 * arc-opc.c (print_insn_arc): Check section size to read
151 appropriate number of bytes. Fix printing.
152 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
153 arguments.
154
3395762e
AV		 1552015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
156
157 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
158 <ldah>: ... to this.
159
622b9eb1
MW		 1602015-11-27 Matthew Wahab <matthew.wahab@arm.com>
161
162 * aarch64-asm-2.c: Regenerate.
163 * aarch64-dis-2.c: Regenerate.
164 * aarch64-opc-2.c: Regenerate.
165 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
166 (QL_INT2FP_H, QL_FP2INT_H): New.
167 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
168 (QL_DST_H): New.
169 (QL_FCCMP_H): New.
170 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
171 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
172 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
173 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
174 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
175 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
176 fcsel.
177
cf86120b
MW		 1782015-11-27 Matthew Wahab <matthew.wahab@arm.com>
179
180 * aarch64-opc.c (half_conv_t): New.
181 (expand_fp_imm): Replace is_dp flag with the parameter size to
182 specify the number of bytes for the required expansion. Treat
183 a 16-bit expansion like a 32-bit expansion. Add check for an
184 unsupported size request. Update comment.
185 (aarch64_print_operand): Update to support 16-bit floating point
186 values. Update for changes to expand_fp_imm.
187
3bd894a7
MW		 1882015-11-27 Matthew Wahab <matthew.wahab@arm.com>
189
190 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
191 (FP_F16): New.
192
64357d2e
MW		 1932015-11-27 Matthew Wahab <matthew.wahab@arm.com>
194
195 * aarch64-asm-2.c: Regenerate.
196 * aarch64-dis-2.c: Regenerate.
197 * aarch64-opc-2.c: Regenerate.
198 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
199 "rev64".
200
d685192a
MW		 2012015-11-27 Matthew Wahab <matthew.wahab@arm.com>
202
203 * aarch64-asm-2.c: Regenerate.
204 * aarch64-asm.c (convert_bfc_to_bfm): New.
205 (convert_to_real): Add case for OP_BFC.
206 * aarch64-dis-2.c: Regenerate.
207 * aarch64-dis.c: (convert_bfm_to_bfc): New.
208 (convert_to_alias): Add case for OP_BFC.
209 * aarch64-opc-2.c: Regenerate.
210 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
211 to allow width operand in three-operand instructions.
212 * aarch64-tbl.h (QL_BF1): New.
213 (aarch64_feature_v8_2): New.
214 (ARMV8_2): New.
215 (aarch64_opcode_table): Add "bfc".
216
35822b38
MW		 2172015-11-27 Matthew Wahab <matthew.wahab@arm.com>
218
219 * aarch64-asm-2.c: Regenerate.
220 * aarch64-dis-2.c: Regenerate.
221 * aarch64-dis.c: Weaken assert.
222 * aarch64-gen.c: Include the instruction in the list of its
223 possible aliases.
224
1a04d1a7
MW		 2252015-11-27 Matthew Wahab <matthew.wahab@arm.com>
226
227 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
228 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
229 feature test.
230
e49d43ff
TG		 2312015-11-23 Tristan Gingold <gingold@adacore.com>
232
233 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
234
250aafa4
MW		 2352015-11-20 Matthew Wahab <matthew.wahab@arm.com>
236
237 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
238 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
239 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
240 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
241 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
242 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
243 cnthv_ctl_el2, cnthv_cval_el2.
244 (aarch64_sys_reg_supported_p): Update for the new system
245 registers.
246
a915c10f
NC		 2472015-11-20 Nick Clifton <nickc@redhat.com>
248
249 PR binutils/19224
250 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
251
f8c2a965
NC		 2522015-11-20 Nick Clifton <nickc@redhat.com>
253
254 * po/zh_CN.po: Updated simplified Chinese translation.
255
c2825638
MW		 2562015-11-19 Matthew Wahab <matthew.wahab@arm.com>
257
258 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
259 of MSR PAN immediate operand.
260
e7286c56
NC		 2612015-11-16 Nick Clifton <nickc@redhat.com>
262
263 * rx-dis.c (condition_names): Replace always and never with
264 invalid, since the always/never conditions can never be legal.
265
d8bd95ef
TG		 2662015-11-13 Tristan Gingold <gingold@adacore.com>
267
268 * configure: Regenerate.
269
a680de9a
PB		 2702015-11-11 Alan Modra <amodra@gmail.com>
271 Peter Bergner <bergner@vnet.ibm.com>
272
273 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
274 Add PPC_OPCODE_VSX3 to the vsx entry.
275 (powerpc_init_dialect): Set default dialect to power9.
276 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
277 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
278 extract_l1 insert_xtq6, extract_xtq6): New static functions.
279 (insert_esync): Test for illegal L operand value.
280 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
281 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
282 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
283 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
284 PPCVSX3): New defines.
285 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
286 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
287 <mcrxr>: Use XBFRARB_MASK.
288 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
289 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
290 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
291 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
292 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
293 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
294 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
295 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
296 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
297 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
298 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
299 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
300 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
301 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
302 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
303 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
304 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
305 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
306 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
307 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
308 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
309 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
310 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
311 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
312 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
313 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
314 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
315 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
316 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
317 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
318 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
319 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
320
854eb72b
NC		 3212015-11-02 Nick Clifton <nickc@redhat.com>
322
323 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
324 instructions.
325 * rx-decode.c: Regenerate.
326
e292aa7a
NC		 3272015-11-02 Nick Clifton <nickc@redhat.com>
328
329 * rx-decode.opc (rx_disp): If the displacement is zero, set the
330 type to RX_Operand_Zero_Indirect.
331 * rx-decode.c: Regenerate.
332 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
333
43cdf5ae
YQ		 3342015-10-28 Yao Qi <yao.qi@linaro.org>
335
336 * aarch64-dis.c (aarch64_decode_insn): Add one argument
337 noaliases_p. Update comments. Pass noaliases_p rather than
338 no_aliases to aarch64_opcode_decode.
339 (print_insn_aarch64_word): Pass no_aliases to
340 aarch64_decode_insn.
341
c2f28758
VK		 3422015-10-27 Vinay <Vinay.G@kpit.com>
343
344 PR binutils/19159
345 * rl78-decode.opc (MOV): Added offset to DE register in index
346 addressing mode.
347 * rl78-decode.c: Regenerate.
348
46662804
VK		 3492015-10-27 Vinay Kumar <vinay.g@kpit.com>
350
351 PR binutils/19158
352 * rl78-decode.opc: Add 's' print operator to instructions that
353 access system registers.
354 * rl78-decode.c: Regenerate.
355 * rl78-dis.c (print_insn_rl78_common): Decode all system
356 registers.
357
02f12cd4
VK		 3582015-10-27 Vinay Kumar <vinay.g@kpit.com>
359
360 PR binutils/19157
361 * rl78-decode.opc: Add 'a' print operator to mov instructions
362 using stack pointer plus index addressing.
363 * rl78-decode.c: Regenerate.
364
485f23cf
AK		 3652015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
366
367 * s390-opc.c: Fix comment.
368 * s390-opc.txt: Change instruction type for troo, trot, trto, and
369 trtt to RRF_U0RER since the second parameter does not need to be a
370 register pair.
371
3f94e60d
NC		 3722015-10-08 Nick Clifton <nickc@redhat.com>
373
374 * arc-dis.c (print_insn_arc): Initiallise insn array.
375
875880c6
YQ		 3762015-10-07 Yao Qi <yao.qi@linaro.org>
377
378 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
379 'name' rather than 'template'.
380 * aarch64-opc.c (aarch64_print_operand): Likewise.
381
886a2506
NC		 3822015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
383
384 * arc-dis.c: Revamped file for ARC support
385 * arc-dis.h: Likewise.
386 * arc-ext.c: Likewise.
387 * arc-ext.h: Likewise.
388 * arc-opc.c: Likewise.
389 * arc-fxi.h: New file.
390 * arc-regs.h: Likewise.
391 * arc-tbl.h: Likewise.
392
36f4aab1
YQ		 3932015-10-02 Yao Qi <yao.qi@linaro.org>
394
395 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
396 argument insn type to aarch64_insn. Rename to ...
397 (aarch64_decode_insn): ... it.
398 (print_insn_aarch64_word): Caller updated.
399
7232d389
YQ		 4002015-10-02 Yao Qi <yao.qi@linaro.org>
401
402 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
403 (print_insn_aarch64_word): Caller updated.
404
7ecc513a
DV		 4052015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
406
407 * s390-mkopc.c (main): Parse htm and vx flag.
408 * s390-opc.txt: Mark instructions from the hardware transactional
409 memory and vector facilities with the "htm"/"vx" flag.
410
b08b78e7
NC		 4112015-09-28 Nick Clifton <nickc@redhat.com>
412
413 * po/de.po: Updated German translation.
414
36f7a941
TR		 4152015-09-28 Tom Rix <tom@bumblecow.com>
416
417 * ppc-opc.c (PPC500): Mark some opcodes as invalid
418
b6518b38
NC		 4192015-09-23 Nick Clifton <nickc@redhat.com>
420
421 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
422 function.
423 * tic30-dis.c (print_branch): Likewise.
424 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
425 value before left shifting.
426 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
427 * hppa-dis.c (print_insn_hppa): Likewise.
428 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
429 array.
430 * msp430-dis.c (msp430_singleoperand): Likewise.
431 (msp430_doubleoperand): Likewise.
432 (print_insn_msp430): Likewise.
433 * nds32-asm.c (parse_operand): Likewise.
434 * sh-opc.h (MASK): Likewise.
435 * v850-dis.c (get_operand_value): Likewise.
436
f04265ec
NC		 4372015-09-22 Nick Clifton <nickc@redhat.com>
438
439 * rx-decode.opc (bwl): Use RX_Bad_Size.
440 (sbwl): Likewise.
441 (ubwl): Likewise. Rename to ubw.
442 (uBWL): Rename to uBW.
443 Replace all references to uBWL with uBW.
444 * rx-decode.c: Regenerate.
445 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
446 (opsize_names): Likewise.
447 (print_insn_rx): Detect and report RX_Bad_Size.
448
6dca4fd1
AB		 4492015-09-22 Anton Blanchard <anton@samba.org>
450
451 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
452
38074311
JM		 4532015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
454
455 * sparc-dis.c (print_insn_sparc): Handle the privileged register
456 %pmcdper.
457
5f40e14d
JS		 4582015-08-24 Jan Stancek <jstancek@redhat.com>
459
460 * i386-dis.c (print_insn): Fix decoding of three byte operands.
461
ab4e4ed5
AF		 4622015-08-21 Alexander Fomin <alexander.fomin@intel.com>
463
464 PR binutils/18257
465 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
466 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
467 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
468 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
469 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
470 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
471 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
472 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
473 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
474 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
475 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
476 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
477 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
478 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
479 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
480 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
481 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
482 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
483 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
484 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
485 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
486 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
487 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
488 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
489 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
490 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
491 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
492 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
493 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
494 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
495 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
496 (vex_w_table): Replace terminals with MOD_TABLE entries for
497 most of mask instructions.
498
919b75f7
AM		 4992015-08-17 Alan Modra <amodra@gmail.com>
500
501 * cgen.sh: Trim trailing space from cgen output.
502 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
503 (print_dis_table): Likewise.
504 * opc2c.c (dump_lines): Likewise.
505 (orig_filename): Warning fix.
506 * ia64-asmtab.c: Regenerate.
507
4ab90a7a
AV		 5082015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
509
510 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
511 and higher with ARM instruction set will now mark the 26-bit
512 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
513 (arm_opcodes): Fix for unpredictable nop being recognized as a
514 teq.
515
40fc1451
SD		 5162015-08-12 Simon Dardis <simon.dardis@imgtec.com>
517
518 * micromips-opc.c (micromips_opcodes): Re-order table so that move
519 based on 'or' is first.
520 * mips-opc.c (mips_builtin_opcodes): Ditto.
521
922c5db5
NC		 5222015-08-11 Nick Clifton <nickc@redhat.com>
523
524 PR 18800
525 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
526 instruction.
527
75fb7498
RS		 5282015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
529
530 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
531
36aed29d
AP		 5322015-08-07 Amit Pawar <Amit.Pawar@amd.com>
533
534 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
535 * i386-init.h: Regenerated.
536
a8484f96
L		 5372015-07-30 H.J. Lu <hongjiu.lu@intel.com>
538
539 PR binutils/13571
540 * i386-dis.c (MOD_0FC3): New.
541 (PREFIX_0FC3): Renamed to ...
542 (PREFIX_MOD_0_0FC3): This.
543 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
544 (prefix_table): Replace Ma with Ev on movntiS.
545 (mod_table): Add MOD_0FC3.
546
37a42ee9
L		 5472015-07-27 H.J. Lu <hongjiu.lu@intel.com>
548
549 * configure: Regenerated.
550
070fe95d
AM		 5512015-07-23 Alan Modra <amodra@gmail.com>
552
553 PR 18708
554 * i386-dis.c (get64): Avoid signed integer overflow.
555
20c2a615
L		 5562015-07-22 Alexander Fomin <alexander.fomin@intel.com>
557
558 PR binutils/18631
559 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
560 "EXEvexHalfBcstXmmq" for the second operand.
561 (EVEX_W_0F79_P_2): Likewise.
562 (EVEX_W_0F7A_P_2): Likewise.
563 (EVEX_W_0F7B_P_2): Likewise.
564
6f1c2142
AM		 5652015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
566
567 * arm-dis.c (print_insn_coprocessor): Added support for quarter
568 float bitfield format.
569 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
570 quarter float bitfield format.
571
8a643cc3
L		 5722015-07-14 H.J. Lu <hongjiu.lu@intel.com>
573
574 * configure: Regenerated.
575
ef5a96d5
AM		 5762015-07-03 Alan Modra <amodra@gmail.com>
577
578 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
579 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
580 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
581
c8c8175b
SL		 5822015-07-01 Sandra Loosemore <sandra@codesourcery.com>
583 Cesar Philippidis <cesar@codesourcery.com>
584
585 * nios2-dis.c (nios2_extract_opcode): New.
586 (nios2_disassembler_state): New.
587 (nios2_find_opcode_hash): Use mach parameter to select correct
588 disassembler state.
589 (nios2_print_insn_arg): Extend to support new R2 argument letters
590 and formats.
591 (print_insn_nios2): Check for 16-bit instruction at end of memory.
592 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
593 (NIOS2_NUM_OPCODES): Rename to...
594 (NIOS2_NUM_R1_OPCODES): This.
595 (nios2_r2_opcodes): New.
596 (NIOS2_NUM_R2_OPCODES): New.
597 (nios2_num_r2_opcodes): New.
598 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
599 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
600 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
601 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
602 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
603
9916071f
AP		 6042015-06-30 Amit Pawar <Amit.Pawar@amd.com>
605
606 * i386-dis.c (OP_Mwaitx): New.
607 (rm_table): Add monitorx/mwaitx.
608 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
609 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
610 (operand_type_init): Add CpuMWAITX.
611 * i386-opc.h (CpuMWAITX): New.
612 (i386_cpu_flags): Add cpumwaitx.
613 * i386-opc.tbl: Add monitorx and mwaitx.
614 * i386-init.h: Regenerated.
615 * i386-tbl.h: Likewise.
616
7b934113
PB		 6172015-06-22 Peter Bergner <bergner@vnet.ibm.com>
618
619 * ppc-opc.c (insert_ls): Test for invalid LS operands.
620 (insert_esync): New function.
621 (LS, WC): Use insert_ls.
622 (ESYNC): Use insert_esync.
623
bdc4de1b
NC		 6242015-06-22 Nick Clifton <nickc@redhat.com>
625
626 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
627 requested region lies beyond it.
628 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
629 looking for 32-bit insns.
630 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
631 data.
632 * sh-dis.c (print_insn_sh): Likewise.
633 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
634 blocks of instructions.
635 * vax-dis.c (print_insn_vax): Check that the requested address
636 does not clash with the stop_vma.
637
11a0cf2e
PB		 6382015-06-19 Peter Bergner <bergner@vnet.ibm.com>
639
070fe95d 640 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 641 * ppc-opc.c (FXM4): Add non-zero optional value.
642 (TBR): Likewise.
643 (SXL): Likewise.
644 (insert_fxm): Handle new default operand value.
645 (extract_fxm): Likewise.
646 (insert_tbr): Likewise.
647 (extract_tbr): Likewise.
648
bdfa8b95
MW		 6492015-06-16 Matthew Wahab <matthew.wahab@arm.com>
650
651 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
652
24b4cf66
SN		 6532015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
654
655 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
656
99a2c561
PB		 6572015-06-12 Peter Bergner <bergner@vnet.ibm.com>
658
659 * ppc-opc.c: Add comment accidentally removed by old commit.
660 (MTMSRD_L): Delete.
661
40f77f82
AM		 6622015-06-04 Peter Bergner <bergner@vnet.ibm.com>
663
664 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
665
13be46a2
NC		 6662015-06-04 Nick Clifton <nickc@redhat.com>
667
668 PR 18474
669 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
670
ddfded2f
MW		 6712015-06-02 Matthew Wahab <matthew.wahab@arm.com>
672
673 * arm-dis.c (arm_opcodes): Add "setpan".
674 (thumb_opcodes): Add "setpan".
675
1af1dd51
MW		 6762015-06-02 Matthew Wahab <matthew.wahab@arm.com>
677
678 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
679 macros.
680
9e1f0fa7
MW		 6812015-06-02 Matthew Wahab <matthew.wahab@arm.com>
682
683 * aarch64-tbl.h (aarch64_feature_rdma): New.
684 (RDMA): New.
685 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
686 * aarch64-asm-2.c: Regenerate.
687 * aarch64-dis-2.c: Regenerate.
688 * aarch64-opc-2.c: Regenerate.
689
290806fd
MW		 6902015-06-02 Matthew Wahab <matthew.wahab@arm.com>
691
692 * aarch64-tbl.h (aarch64_feature_lor): New.
693 (LOR): New.
694 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
695 "stllrb", "stllrh".
696 * aarch64-asm-2.c: Regenerate.
697 * aarch64-dis-2.c: Regenerate.
698 * aarch64-opc-2.c: Regenerate.
699
f21cce2c
MW		 7002015-06-01 Matthew Wahab <matthew.wahab@arm.com>
701
702 * aarch64-opc.c (F_ARCHEXT): New.
703 (aarch64_sys_regs): Add "pan".
704 (aarch64_sys_reg_supported_p): New.
705 (aarch64_pstatefields): Add "pan".
706 (aarch64_pstatefield_supported_p): New.
707
d194d186
JB		 7082015-06-01 Jan Beulich <jbeulich@suse.com>
709
710 * i386-tbl.h: Regenerate.
711
3a8547d2
JB		 7122015-06-01 Jan Beulich <jbeulich@suse.com>
713
714 * i386-dis.c (print_insn): Swap rounding mode specifier and
715 general purpose register in Intel mode.
716
015c54d5
JB		 7172015-06-01 Jan Beulich <jbeulich@suse.com>
718
719 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
720 * i386-tbl.h: Regenerate.
721
071f0063
L		 7222015-05-18 H.J. Lu <hongjiu.lu@intel.com>
723
724 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
725 * i386-init.h: Regenerated.
726
5db04b09
L		 7272015-05-15 H.J. Lu <hongjiu.lu@intel.com>
728
729 PR binutis/18386
730 * i386-dis.c: Add comments for '@'.
731 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
732 (enum x86_64_isa): New.
733 (isa64): Likewise.
734 (print_i386_disassembler_options): Add amd64 and intel64.
735 (print_insn): Handle amd64 and intel64.
736 (putop): Handle '@'.
737 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
738 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
739 * i386-opc.h (AMD64): New.
740 (CpuIntel64): Likewise.
741 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
742 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
743 Mark direct call/jmp without Disp16|Disp32 as Intel64.
744 * i386-init.h: Regenerated.
745 * i386-tbl.h: Likewise.
746
4bc0608a
PB		 7472015-05-14 Peter Bergner <bergner@vnet.ibm.com>
748
749 * ppc-opc.c (IH) New define.
750 (powerpc_opcodes) <wait>: Do not enable for POWER7.
751 <tlbie>: Add RS operand for POWER7.
752 <slbia>: Add IH operand for POWER6.
753
70cead07
L		 7542015-05-11 H.J. Lu <hongjiu.lu@intel.com>
755
756 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
757 direct branch.
758 (jmp): Likewise.
759 * i386-tbl.h: Regenerated.
760
7b6d09fb
L		 7612015-05-11 H.J. Lu <hongjiu.lu@intel.com>
762
763 * configure.ac: Support bfd_iamcu_arch.
764 * disassemble.c (disassembler): Support bfd_iamcu_arch.
765 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
766 CPU_IAMCU_COMPAT_FLAGS.
767 (cpu_flags): Add CpuIAMCU.
768 * i386-opc.h (CpuIAMCU): New.
769 (i386_cpu_flags): Add cpuiamcu.
770 * configure: Regenerated.
771 * i386-init.h: Likewise.
772 * i386-tbl.h: Likewise.
773
31955f99
L		 7742015-05-08 H.J. Lu <hongjiu.lu@intel.com>
775
776 PR binutis/18386
777 * i386-dis.c (X86_64_E8): New.
778 (X86_64_E9): Likewise.
779 Update comments on 'T', 'U', 'V'. Add comments for '^'.
780 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
781 (x86_64_table): Add X86_64_E8 and X86_64_E9.
782 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
783 (putop): Handle '^'.
784 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
785 REX_W.
786
0952813b
DD		 7872015-04-30 DJ Delorie <dj@redhat.com>
788
789 * disassemble.c (disassembler): Choose suitable disassembler based
790 on E_ABI.
791 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
792 it to decode mul/div insns.
793 * rl78-decode.c: Regenerate.
794 * rl78-dis.c (print_insn_rl78): Rename to...
795 (print_insn_rl78_common): ...this, take ISA parameter.
796 (print_insn_rl78): New.
797 (print_insn_rl78_g10): New.
798 (print_insn_rl78_g13): New.
799 (print_insn_rl78_g14): New.
800 (rl78_get_disassembler): New.
801
f9d3ecaa
NC		 8022015-04-29 Nick Clifton <nickc@redhat.com>
803
804 * po/fr.po: Updated French translation.
805
4fff86c5
PB		 8062015-04-27 Peter Bergner <bergner@vnet.ibm.com>
807
808 * ppc-opc.c (DCBT_EO): New define.
809 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
810 <lharx>: Likewise.
811 <stbcx.>: Likewise.
812 <sthcx.>: Likewise.
813 <waitrsv>: Do not enable for POWER7 and later.
814 <waitimpl>: Likewise.
815 <dcbt>: Default to the two operand form of the instruction for all
816 "old" cpus. For "new" cpus, use the operand ordering that matches
817 whether the cpu is server or embedded.
818 <dcbtst>: Likewise.
819
3b78cfe1
AK		 8202015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
821
822 * s390-opc.c: New instruction type VV0UU2.
823 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
824 and WFC.
825
04d824a4
JB		 8262015-04-23 Jan Beulich <jbeulich@suse.com>
827
828 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
829 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
830 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
831 (vfpclasspd, vfpclassps): Add %XZ.
832
09708981
L		 8332015-04-15 H.J. Lu <hongjiu.lu@intel.com>
834
835 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
836 (PREFIX_UD_REPZ): Likewise.
837 (PREFIX_UD_REPNZ): Likewise.
838 (PREFIX_UD_DATA): Likewise.
839 (PREFIX_UD_ADDR): Likewise.
840 (PREFIX_UD_LOCK): Likewise.
841
3888916d
L		 8422015-04-15 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-dis.c (prefix_requirement): Removed.
845 (print_insn): Don't set prefix_requirement. Check
846 dp->prefix_requirement instead of prefix_requirement.
847
f24bcbaa
L		 8482015-04-15 H.J. Lu <hongjiu.lu@intel.com>
849
850 PR binutils/17898
851 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
852 (PREFIX_MOD_0_0FC7_REG_6): This.
853 (PREFIX_MOD_3_0FC7_REG_6): New.
854 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
855 (prefix_table): Replace PREFIX_0FC7_REG_6 with
856 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
857 PREFIX_MOD_3_0FC7_REG_7.
858 (mod_table): Replace PREFIX_0FC7_REG_6 with
859 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
860 PREFIX_MOD_3_0FC7_REG_7.
861
507bd325
L		 8622015-04-15 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
865 (PREFIX_MANDATORY_REPNZ): Likewise.
866 (PREFIX_MANDATORY_DATA): Likewise.
867 (PREFIX_MANDATORY_ADDR): Likewise.
868 (PREFIX_MANDATORY_LOCK): Likewise.
869 (PREFIX_MANDATORY): Likewise.
870 (PREFIX_UD_SHIFT): Set to 8
871 (PREFIX_UD_REPZ): Updated.
872 (PREFIX_UD_REPNZ): Likewise.
873 (PREFIX_UD_DATA): Likewise.
874 (PREFIX_UD_ADDR): Likewise.
875 (PREFIX_UD_LOCK): Likewise.
876 (PREFIX_IGNORED_SHIFT): New.
877 (PREFIX_IGNORED_REPZ): Likewise.
878 (PREFIX_IGNORED_REPNZ): Likewise.
879 (PREFIX_IGNORED_DATA): Likewise.
880 (PREFIX_IGNORED_ADDR): Likewise.
881 (PREFIX_IGNORED_LOCK): Likewise.
882 (PREFIX_OPCODE): Likewise.
883 (PREFIX_IGNORED): Likewise.
884 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
885 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
886 (three_byte_table): Likewise.
887 (mod_table): Likewise.
888 (mandatory_prefix): Renamed to ...
889 (prefix_requirement): This.
890 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
891 Update PREFIX_90 entry.
892 (get_valid_dis386): Check prefix_requirement to see if a prefix
893 should be ignored.
894 (print_insn): Replace mandatory_prefix with prefix_requirement.
895
f0fba320
RL		 8962015-04-15 Renlin Li <renlin.li@arm.com>
897
898 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
899 use it for ssat and ssat16.
900 (print_insn_thumb32): Add handle case for 'D' control code.
901
bf890a93
IT		 9022015-04-06 Ilya Tocar <ilya.tocar@intel.com>
903 H.J. Lu <hongjiu.lu@intel.com>
904
905 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
906 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
907 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
908 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
909 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
910 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
911 Fill prefix_requirement field.
912 (struct dis386): Add prefix_requirement field.
913 (dis386): Fill prefix_requirement field.
914 (dis386_twobyte): Ditto.
915 (twobyte_has_mandatory_prefix_: Remove.
916 (reg_table): Fill prefix_requirement field.
917 (prefix_table): Ditto.
918 (x86_64_table): Ditto.
919 (three_byte_table): Ditto.
920 (xop_table): Ditto.
921 (vex_table): Ditto.
922 (vex_len_table): Ditto.
923 (vex_w_table): Ditto.
924 (mod_table): Ditto.
925 (bad_opcode): Ditto.
926 (print_insn): Use prefix_requirement.
927 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
928 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
929 (float_reg): Ditto.
930
2f783c1f
MF		 9312015-03-30 Mike Frysinger <vapier@gentoo.org>
932
933 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
934
b9d94d62
L		 9352015-03-29 H.J. Lu <hongjiu.lu@intel.com>
936
937 * Makefile.in: Regenerated.
938
27c49e9a
AB		 9392015-03-25 Anton Blanchard <anton@samba.org>
940
941 * ppc-dis.c (disassemble_init_powerpc): Only initialise
942 powerpc_opcd_indices and vle_opcd_indices once.
943
c4e676f1
AB		 9442015-03-25 Anton Blanchard <anton@samba.org>
945
946 * ppc-opc.c (powerpc_opcodes): Add slbfee.
947
823d2571
TG		 9482015-03-24 Terry Guo <terry.guo@arm.com>
949
950 * arm-dis.c (opcode32): Updated to use new arm feature struct.
951 (opcode16): Likewise.
952 (coprocessor_opcodes): Replace bit with feature struct.
953 (neon_opcodes): Likewise.
954 (arm_opcodes): Likewise.
955 (thumb_opcodes): Likewise.
956 (thumb32_opcodes): Likewise.
957 (print_insn_coprocessor): Likewise.
958 (print_insn_arm): Likewise.
959 (select_arm_features): Follow new feature struct.
960
029f3522
GG		 9612015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
962
963 * i386-dis.c (rm_table): Add clzero.
964 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
965 Add CPU_CLZERO_FLAGS.
966 (cpu_flags): Add CpuCLZERO.
967 * i386-opc.h: Add CpuCLZERO.
968 * i386-opc.tbl: Add clzero.
969 * i386-init.h: Re-generated.
970 * i386-tbl.h: Re-generated.
971
6914869a
AB		 9722015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
973
974 * mips-opc.c (decode_mips_operand): Fix constraint issues
975 with u and y operands.
976
21e20815
AB		 9772015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
978
979 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
980
6b1d7593
AK		 9812015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
982
983 * s390-opc.c: Add new IBM z13 instructions.
984 * s390-opc.txt: Likewise.
985
c8f89a34
JW		 9862015-03-10 Renlin Li <renlin.li@arm.com>
987
988 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
989 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
990 related alias.
991 * aarch64-asm-2.c: Regenerate.
992 * aarch64-dis-2.c: Likewise.
993 * aarch64-opc-2.c: Likewise.
994
d8282f0e
JW		 9952015-03-03 Jiong Wang <jiong.wang@arm.com>
996
997 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
998
ac994365
OE		 9992015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1000
1001 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1002 arch_sh_up.
1003 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1004 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1005
fd63f640
V		 10062015-02-23 Vinay <Vinay.G@kpit.com>
1007
1008 * rl78-decode.opc (MOV): Added space between two operands for
1009 'mov' instruction in index addressing mode.
1010 * rl78-decode.c: Regenerate.
1011
f63c1776
PA		 10122015-02-19 Pedro Alves <palves@redhat.com>
1013
1014 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1015
07774fcc
PA		 10162015-02-10 Pedro Alves <palves@redhat.com>
1017 Tom Tromey <tromey@redhat.com>
1018
1019 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1020 microblaze_and, microblaze_xor.
1021 * microblaze-opc.h (opcodes): Adjust.
1022
3f8107ab
AM		 10232015-01-28 James Bowman <james.bowman@ftdichip.com>
1024
1025 * Makefile.am: Add FT32 files.
1026 * configure.ac: Handle FT32.
1027 * disassemble.c (disassembler): Call print_insn_ft32.
1028 * ft32-dis.c: New file.
1029 * ft32-opc.c: New file.
1030 * Makefile.in: Regenerate.
1031 * configure: Regenerate.
1032 * po/POTFILES.in: Regenerate.
1033
e5fe4957
KLC		 10342015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1035
1036 * nds32-asm.c (keyword_sr): Add new system registers.
1037
1e2e8c52
AK		 10382015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1039
1040 * s390-dis.c (s390_extract_operand): Support vector register
1041 operands.
1042 (s390_print_insn_with_opcode): Support new operands types and add
1043 new handling of optional operands.
1044 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1045 and include opcode/s390.h instead.
1046 (struct op_struct): New field `flags'.
1047 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1048 (dumpTable): Dump flags.
1049 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1050 string.
1051 * s390-opc.c: Add new operands types, instruction formats, and
1052 instruction masks.
1053 (s390_opformats): Add new formats for .insn.
1054 * s390-opc.txt: Add new instructions.
1055
b90efa5b 10562015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1057
b90efa5b 1058 Update year range in copyright notice of all files.
bffb6004 1059
b90efa5b 1060For older changes see ChangeLog-2014
252b5132 1061\f
b90efa5b 1062Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1063
1064Copying and distribution of this file, with or without modification,
1065are permitted in any medium without royalty provided the copyright
1066notice and this notice are preserved.
1067
252b5132 1068Local Variables:
2f6d2f85
NC		 1069mode: change-log
1070left-margin: 8
1071fill-column: 74
252b5132
RH		 1072version-control: never
1073End:
GDB Binutils - Deliverables
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