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x86: also allow D on 3-operand insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f5eb1d70
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
4 store templates, adding D.
5 * i386-tbl.h: Re-generate.
6
dbbc8b7e
JB		 72018-09-13 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
10 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
11 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
12 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
13 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
14 Fold load and store templates where possible, adding D. Drop
15 IgnoreSize where it was pointlessly present. Drop redundant
16 *word.
17 * i386-tbl.h: Re-generate.
18
d276ec69
JB		 192018-09-13 Jan Beulich <jbeulich@suse.com>
20
21 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
22 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
23 (intel_operand_size): Handle v_bndmk_mode.
24 (OP_E_memory): Likewise. Produce (bad) when also riprel.
25
9da4dfd6
JD		 262018-09-08 John Darrington <john@darrington.wattle.id.au>
27
28 * disassemble.c (ARCH_s12z): Define if ARCH_all.
29
be192bc2
JW		 302018-08-31 Kito Cheng <kito@andestech.com>
31
32 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
33 compressed floating point instructions.
34
43135d3b
JW		 352018-08-30 Kito Cheng <kito@andestech.com>
36
37 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
38 riscv_opcode.xlen_requirement.
39 * riscv-opc.c (riscv_opcodes): Update for struct change.
40
df28970f
MA		 412018-08-29 Martin Aberg <maberg@gaisler.com>
42
43 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
44 psr (PWRPSR) instruction.
45
9108bc33
CX		 462018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
47
48 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
49
bd782c07
CX		 502018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
51
52 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
53
ac8cb70f
CX		 542018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
55
56 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
57 loongson3a as an alias of gs464 for compatibility.
58 * mips-opc.c (mips_opcodes): Change Comments.
59
a693765e
CX		 602018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
61
62 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
63 option.
64 (print_mips_disassembler_options): Document -M loongson-ext.
65 * mips-opc.c (LEXT2): New macro.
66 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
67
bdc6c06e
CX		 682018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
69
70 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
71 descriptors.
72 (parse_mips_ase_option): Handle -M loongson-ext option.
73 (print_mips_disassembler_options): Document -M loongson-ext.
74 * mips-opc.c (IL3A): Delete.
75 * mips-opc.c (LEXT): New macro.
76 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
77 instructions.
78
716c08de
CX		 792018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
80
81 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
82 descriptors.
83 (parse_mips_ase_option): Handle -M loongson-cam option.
84 (print_mips_disassembler_options): Document -M loongson-cam.
85 * mips-opc.c (LCAM): New macro.
86 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
87 instructions.
88
9cf7e568
AM		 892018-08-21 Alan Modra <amodra@gmail.com>
90
91 * ppc-dis.c (operand_value_powerpc): Init "invalid".
92 (skip_optional_operands): Count optional operands, and update
93 ppc_optional_operand_value call.
94 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
95 (extract_vlensi): Likewise.
96 (extract_fxm): Return default value for missing optional operand.
97 (extract_ls, extract_raq, extract_tbr): Likewise.
98 (insert_sxl, extract_sxl): New functions.
99 (insert_esync, extract_esync): Remove Power9 handling and simplify.
100 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
101 flag and extra entry.
102 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
103 extract_sxl.
104
d203b41a 1052018-08-20 Alan Modra <amodra@gmail.com>
f4107842 106
d203b41a 107 * sh-opc.h (MASK): Simplify.
f4107842 108
08a8fe2f 1092018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 110
d203b41a
AM		 111 * s12z-dis.c (bm_decode): Deal with cases where the mode is
112 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 113 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 114
08a8fe2f 1152018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 116
117 * s12z.h: Delete.
7ba3ba91 118
1bc60e56
L		 1192018-08-14 H.J. Lu <hongjiu.lu@intel.com>
120
121 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
122 address with the addr32 prefix and without base nor index
123 registers.
124
d871f3f4
L		 1252018-08-11 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
128 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
129 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
130 (cpu_flags): Add CpuCMOV and CpuFXSR.
131 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
132 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
133 * i386-init.h: Regenerated.
134 * i386-tbl.h: Likewise.
135
b6523c37 1362018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
137
138 * arc-regs.h: Update auxiliary registers.
139
e968fc9b
JB		 1402018-08-06 Jan Beulich <jbeulich@suse.com>
141
142 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
143 (RegIP, RegIZ): Define.
144 * i386-reg.tbl: Adjust comments.
145 (rip): Use Qword instead of BaseIndex. Use RegIP.
146 (eip): Use Dword instead of BaseIndex. Use RegIP.
147 (riz): Add Qword. Use RegIZ.
148 (eiz): Add Dword. Use RegIZ.
149 * i386-tbl.h: Re-generate.
150
dbf8be89
JB		 1512018-08-03 Jan Beulich <jbeulich@suse.com>
152
153 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
154 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
155 vpmovzxdq, vpmovzxwd): Remove NoRex64.
156 * i386-tbl.h: Re-generate.
157
c48dadc9
JB		 1582018-08-03 Jan Beulich <jbeulich@suse.com>
159
160 * i386-gen.c (operand_types): Remove Mem field.
161 * i386-opc.h (union i386_operand_type): Remove mem field.
162 * i386-init.h, i386-tbl.h: Re-generate.
163
cb86a42a
AM		 1642018-08-01 Alan Modra <amodra@gmail.com>
165
166 * po/POTFILES.in: Regenerate.
167
07cc0450
NC		 1682018-07-31 Nick Clifton <nickc@redhat.com>
169
170 * po/sv.po: Updated Swedish translation.
171
1424ad86
JB		 1722018-07-31 Jan Beulich <jbeulich@suse.com>
173
174 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
175 * i386-init.h, i386-tbl.h: Re-generate.
176
ae2387fe
JB		 1772018-07-31 Jan Beulich <jbeulich@suse.com>
178
179 * i386-opc.h (ZEROING_MASKING) Rename to ...
180 (DYNAMIC_MASKING): ... this. Adjust comment.
181 * i386-opc.tbl (MaskingMorZ): Define.
182 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
183 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
184 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
185 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
186 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
187 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
188 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
189 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
190 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
191
6ff00b5e
JB		 1922018-07-31 Jan Beulich <jbeulich@suse.com>
193
194 * i386-opc.tbl: Use element rather than vector size for AVX512*
195 scatter/gather insns.
196 * i386-tbl.h: Re-generate.
197
e951d5ca
JB		 1982018-07-31 Jan Beulich <jbeulich@suse.com>
199
200 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
201 (cpu_flags): Drop CpuVREX.
202 * i386-opc.h (CpuVREX): Delete.
203 (union i386_cpu_flags): Remove cpuvrex.
204 * i386-init.h, i386-tbl.h: Re-generate.
205
eb41b248
JW		 2062018-07-30 Jim Wilson <jimw@sifive.com>
207
208 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
209 fields.
210 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
211
b8891f8d
AJ		 2122018-07-30 Andrew Jenner <andrew@codesourcery.com>
213
214 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
215 * Makefile.in: Regenerated.
216 * configure.ac: Add C-SKY.
217 * configure: Regenerated.
218 * csky-dis.c: New file.
219 * csky-opc.h: New file.
220 * disassemble.c (ARCH_csky): Define.
221 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
222 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
223
16065af1
AM		 2242018-07-27 Alan Modra <amodra@gmail.com>
225
226 * ppc-opc.c (insert_sprbat): Correct function parameter and
227 return type.
228 (extract_sprbat): Likewise, variable too.
229
fa758a70
AC		 2302018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
231 Alan Modra <amodra@gmail.com>
232
233 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
234 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
235 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
236 support disjointed BAT.
237 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
238 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
239 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
240
4a1b91ea
L		 2412018-07-25 H.J. Lu <hongjiu.lu@intel.com>
242 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
243
244 * i386-gen.c (adjust_broadcast_modifier): New function.
245 (process_i386_opcode_modifier): Add an argument for operands.
246 Adjust the Broadcast value based on operands.
247 (output_i386_opcode): Pass operand_types to
248 process_i386_opcode_modifier.
249 (process_i386_opcodes): Pass NULL as operands to
250 process_i386_opcode_modifier.
251 * i386-opc.h (BYTE_BROADCAST): New.
252 (WORD_BROADCAST): Likewise.
253 (DWORD_BROADCAST): Likewise.
254 (QWORD_BROADCAST): Likewise.
255 (i386_opcode_modifier): Expand broadcast to 3 bits.
256 * i386-tbl.h: Regenerated.
257
67ce483b
AM		 2582018-07-24 Alan Modra <amodra@gmail.com>
259
260 PR 23430
261 * or1k-desc.h: Regenerate.
262
4174bfff
JB		 2632018-07-24 Jan Beulich <jbeulich@suse.com>
264
265 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
266 vcvtusi2ss, and vcvtusi2sd.
267 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
268 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
269 * i386-tbl.h: Re-generate.
270
04e65276
CZ		 2712018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
272
273 * arc-opc.c (extract_w6): Fix extending the sign.
274
47e6f81c
CZ		 2752018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
276
277 * arc-tbl.h (vewt): Allow it for ARC EM family.
278
bb71536f
AM		 2792018-07-23 Alan Modra <amodra@gmail.com>
280
281 PR 23419
282 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
283 opcode variants for mtspr/mfspr encodings.
284
8095d2f7
CX		 2852018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
286 Maciej W. Rozycki <macro@mips.com>
287
288 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
289 loongson3a descriptors.
290 (parse_mips_ase_option): Handle -M loongson-mmi option.
291 (print_mips_disassembler_options): Document -M loongson-mmi.
292 * mips-opc.c (LMMI): New macro.
293 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
294 instructions.
295
5f32791e
JB		 2962018-07-19 Jan Beulich <jbeulich@suse.com>
297
298 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
299 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
300 IgnoreSize and [XYZ]MMword where applicable.
301 * i386-tbl.h: Re-generate.
302
625cbd7a
JB		 3032018-07-19 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
306 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
307 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
308 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
309 * i386-tbl.h: Re-generate.
310
86b15c32
JB		 3112018-07-19 Jan Beulich <jbeulich@suse.com>
312
313 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
314 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
315 VPCLMULQDQ templates into their respective AVX512VL counterparts
316 where possible, using Disp8ShiftVL and CheckRegSize instead of
317 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
318 * i386-tbl.h: Re-generate.
319
cf769ed5
JB		 3202018-07-19 Jan Beulich <jbeulich@suse.com>
321
322 * i386-opc.tbl: Fold AVX512DQ templates into their respective
323 AVX512VL counterparts where possible, using Disp8ShiftVL and
324 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
325 IgnoreSize) as appropriate.
326 * i386-tbl.h: Re-generate.
327
8282b7ad
JB		 3282018-07-19 Jan Beulich <jbeulich@suse.com>
329
330 * i386-opc.tbl: Fold AVX512BW templates into their respective
331 AVX512VL counterparts where possible, using Disp8ShiftVL and
332 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
333 IgnoreSize) as appropriate.
334 * i386-tbl.h: Re-generate.
335
755908cc
JB		 3362018-07-19 Jan Beulich <jbeulich@suse.com>
337
338 * i386-opc.tbl: Fold AVX512CD templates into their respective
339 AVX512VL counterparts where possible, using Disp8ShiftVL and
340 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
341 IgnoreSize) as appropriate.
342 * i386-tbl.h: Re-generate.
343
7091c612
JB		 3442018-07-19 Jan Beulich <jbeulich@suse.com>
345
346 * i386-opc.h (DISP8_SHIFT_VL): New.
347 * i386-opc.tbl (Disp8ShiftVL): Define.
348 (various): Fold AVX512VL templates into their respective
349 AVX512F counterparts where possible, using Disp8ShiftVL and
350 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
351 IgnoreSize) as appropriate.
352 * i386-tbl.h: Re-generate.
353
c30be56e
JB		 3542018-07-19 Jan Beulich <jbeulich@suse.com>
355
356 * Makefile.am: Change dependencies and rule for
357 $(srcdir)/i386-init.h.
358 * Makefile.in: Re-generate.
359 * i386-gen.c (process_i386_opcodes): New local variable
360 "marker". Drop opening of input file. Recognize marker and line
361 number directives.
362 * i386-opc.tbl (OPCODE_I386_H): Define.
363 (i386-opc.h): Include it.
364 (None): Undefine.
365
11a322db
L		 3662018-07-18 H.J. Lu <hongjiu.lu@intel.com>
367
368 PR gas/23418
369 * i386-opc.h (Byte): Update comments.
370 (Word): Likewise.
371 (Dword): Likewise.
372 (Fword): Likewise.
373 (Qword): Likewise.
374 (Tbyte): Likewise.
375 (Xmmword): Likewise.
376 (Ymmword): Likewise.
377 (Zmmword): Likewise.
378 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
379 vcvttps2uqq.
380 * i386-tbl.h: Regenerated.
381
cde3679e
NC		 3822018-07-12 Sudakshina Das <sudi.das@arm.com>
383
384 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
385 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
386 * aarch64-asm-2.c: Regenerate.
387 * aarch64-dis-2.c: Regenerate.
388 * aarch64-opc-2.c: Regenerate.
389
45a28947
TC		 3902018-07-12 Tamar Christina <tamar.christina@arm.com>
391
392 PR binutils/23192
393 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
394 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
395 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
396 sqdmulh, sqrdmulh): Use Em16.
397
c597cc3d
SD		 3982018-07-11 Sudakshina Das <sudi.das@arm.com>
399
400 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
401 csdb together with them.
402 (thumb32_opcodes): Likewise.
403
a79eaed6
JB		 4042018-07-11 Jan Beulich <jbeulich@suse.com>
405
406 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
407 requiring 32-bit registers as operands 2 and 3. Improve
408 comments.
409 (mwait, mwaitx): Fold templates. Improve comments.
410 OPERAND_TYPE_INOUTPORTREG.
411 * i386-tbl.h: Re-generate.
412
2fb5be8d
JB		 4132018-07-11 Jan Beulich <jbeulich@suse.com>
414
415 * i386-gen.c (operand_type_init): Remove
416 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
417 OPERAND_TYPE_INOUTPORTREG.
418 * i386-init.h: Re-generate.
419
7f5cad30
JB		 4202018-07-11 Jan Beulich <jbeulich@suse.com>
421
422 * i386-opc.tbl (wrssd, wrussd): Add Dword.
423 (wrssq, wrussq): Add Qword.
424 * i386-tbl.h: Re-generate.
425
f0a85b07
JB		 4262018-07-11 Jan Beulich <jbeulich@suse.com>
427
428 * i386-opc.h: Rename OTMax to OTNum.
429 (OTNumOfUints): Adjust calculation.
430 (OTUnused): Directly alias to OTNum.
431
9dcb0ba4
MR		 4322018-07-09 Maciej W. Rozycki <macro@mips.com>
433
434 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
435 `reg_xys'.
436 (lea_reg_xys): Likewise.
437 (print_insn_loop_primitive): Rename `reg' local variable to
438 `reg_dxy'.
439
f311ba7e
TC		 4402018-07-06 Tamar Christina <tamar.christina@arm.com>
441
442 PR binutils/23242
443 * aarch64-tbl.h (ldarh): Fix disassembly mask.
444
cba05feb
TC		 4452018-07-06 Tamar Christina <tamar.christina@arm.com>
446
447 PR binutils/23369
448 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
449 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
450
471b9d15
MR		 4512018-07-02 Maciej W. Rozycki <macro@mips.com>
452
453 PR tdep/8282
454 * mips-dis.c (mips_option_arg_t): New enumeration.
455 (mips_options): New variable.
456 (disassembler_options_mips): New function.
457 (print_mips_disassembler_options): Reimplement in terms of
458 `disassembler_options_mips'.
459 * arm-dis.c (disassembler_options_arm): Adapt to using the
460 `disasm_options_and_args_t' structure.
461 * ppc-dis.c (disassembler_options_powerpc): Likewise.
462 * s390-dis.c (disassembler_options_s390): Likewise.
463
c0c468d5
TP		 4642018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
465
466 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
467 expected result.
468 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
469 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
470 * testsuite/ld-arm/tls-longplt.d: Likewise.
471
369c9167
TC		 4722018-06-29 Tamar Christina <tamar.christina@arm.com>
473
474 PR binutils/23192
475 * aarch64-asm-2.c: Regenerate.
476 * aarch64-dis-2.c: Likewise.
477 * aarch64-opc-2.c: Likewise.
478 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
479 * aarch64-opc.c (operand_general_constraint_met_p,
480 aarch64_print_operand): Likewise.
481 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
482 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
483 fmlal2, fmlsl2.
484 (AARCH64_OPERANDS): Add Em2.
485
30aa1306
NC		 4862018-06-26 Nick Clifton <nickc@redhat.com>
487
488 * po/uk.po: Updated Ukranian translation.
489 * po/de.po: Updated German translation.
490 * po/pt_BR.po: Updated Brazilian Portuguese translation.
491
eca4b721
NC		 4922018-06-26 Nick Clifton <nickc@redhat.com>
493
494 * nfp-dis.c: Fix spelling mistake.
495
71300e2c
NC		 4962018-06-24 Nick Clifton <nickc@redhat.com>
497
498 * configure: Regenerate.
499 * po/opcodes.pot: Regenerate.
500
719d8288
NC		 5012018-06-24 Nick Clifton <nickc@redhat.com>
502
503 2.31 branch created.
504
514cd3a0
TC		 5052018-06-19 Tamar Christina <tamar.christina@arm.com>
506
507 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
508 * aarch64-asm-2.c: Regenerate.
509 * aarch64-dis-2.c: Likewise.
510
385e4d0f
MR		 5112018-06-21 Maciej W. Rozycki <macro@mips.com>
512
513 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
514 `-M ginv' option description.
515
160d1b3d
SH		 5162018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
517
518 PR gas/23305
519 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
520 la and lla.
521
d0ac1c44
SM		 5222018-06-19 Simon Marchi <simon.marchi@ericsson.com>
523
524 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
525 * configure.ac: Remove AC_PREREQ.
526 * Makefile.in: Re-generate.
527 * aclocal.m4: Re-generate.
528 * configure: Re-generate.
529
6f20c942
FS		 5302018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
531
532 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
533 mips64r6 descriptors.
534 (parse_mips_ase_option): Handle -Mginv option.
535 (print_mips_disassembler_options): Document -Mginv.
536 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
537 (GINV): New macro.
538 (mips_opcodes): Define ginvi and ginvt.
539
730c3174
SE		 5402018-06-13 Scott Egerton <scott.egerton@imgtec.com>
541 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
542
543 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
544 * mips-opc.c (CRC, CRC64): New macros.
545 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
546 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
547 crc32cd for CRC64.
548
cb366992
EB		 5492018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
550
551 PR 20319
552 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
553 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
554
ce72cd46
AM		 5552018-06-06 Alan Modra <amodra@gmail.com>
556
557 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
558 setjmp. Move init for some other vars later too.
559
4b8e28c7
MF		 5602018-06-04 Max Filippov <jcmvbkbc@gmail.com>
561
562 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
563 (dis_private): Add new fields for property section tracking.
564 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
565 (xtensa_instruction_fits): New functions.
566 (fetch_data): Bump minimal fetch size to 4.
567 (print_insn_xtensa): Make struct dis_private static.
568 Load and prepare property table on section change.
569 Don't disassemble literals. Don't disassemble instructions that
570 cross property table boundaries.
571
55e99962
L		 5722018-06-01 H.J. Lu <hongjiu.lu@intel.com>
573
574 * configure: Regenerated.
575
733bd0ab
JB		 5762018-06-01 Jan Beulich <jbeulich@suse.com>
577
578 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
579 * i386-tbl.h: Re-generate.
580
dfd27d41
JB		 5812018-06-01 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.tbl (sldt, str): Add NoRex64.
584 * i386-tbl.h: Re-generate.
585
64795710
JB		 5862018-06-01 Jan Beulich <jbeulich@suse.com>
587
588 * i386-opc.tbl (invpcid): Add Oword.
589 * i386-tbl.h: Re-generate.
590
030157d8
AM		 5912018-06-01 Alan Modra <amodra@gmail.com>
592
593 * sysdep.h (_bfd_error_handler): Don't declare.
594 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
595 * rl78-decode.opc: Likewise.
596 * msp430-decode.c: Regenerate.
597 * rl78-decode.c: Regenerate.
598
a9660a6f
AP		 5992018-05-30 Amit Pawar <Amit.Pawar@amd.com>
600
601 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
602 * i386-init.h : Regenerated.
603
277eb7f6
AM		 6042018-05-25 Alan Modra <amodra@gmail.com>
605
606 * Makefile.in: Regenerate.
607 * po/POTFILES.in: Regenerate.
608
98553ad3
PB		 6092018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
610
611 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
612 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
613 (insert_bab, extract_bab, insert_btab, extract_btab,
614 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
615 (BAT, BBA VBA RBS XB6S): Delete macros.
616 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
617 (BB, BD, RBX, XC6): Update for new macros.
618 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
619 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
620 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
621 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
622
7b4ae824
JD		 6232018-05-18 John Darrington <john@darrington.wattle.id.au>
624
625 * Makefile.am: Add support for s12z architecture.
626 * configure.ac: Likewise.
627 * disassemble.c: Likewise.
628 * disassemble.h: Likewise.
629 * Makefile.in: Regenerate.
630 * configure: Regenerate.
631 * s12z-dis.c: New file.
632 * s12z.h: New file.
633
29e0f0a1
AM		 6342018-05-18 Alan Modra <amodra@gmail.com>
635
636 * nfp-dis.c: Don't #include libbfd.h.
637 (init_nfp3200_priv): Use bfd_get_section_contents.
638 (nit_nfp6000_mecsr_sec): Likewise.
639
809276d2
NC		 6402018-05-17 Nick Clifton <nickc@redhat.com>
641
642 * po/zh_CN.po: Updated simplified Chinese translation.
643
ff329288
TC		 6442018-05-16 Tamar Christina <tamar.christina@arm.com>
645
646 PR binutils/23109
647 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
648 * aarch64-dis-2.c: Regenerate.
649
f9830ec1
TC		 6502018-05-15 Tamar Christina <tamar.christina@arm.com>
651
652 PR binutils/21446
653 * aarch64-asm.c (opintl.h): Include.
654 (aarch64_ins_sysreg): Enforce read/write constraints.
655 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
656 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
657 (F_REG_READ, F_REG_WRITE): New.
658 * aarch64-opc.c (aarch64_print_operand): Generate notes for
659 AARCH64_OPND_SYSREG.
660 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
661 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
662 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
663 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
664 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
665 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
666 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
667 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
668 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
669 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
670 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
671 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
672 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
673 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
674 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
675 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
676 msr (F_SYS_WRITE), mrs (F_SYS_READ).
677
7d02540a
TC		 6782018-05-15 Tamar Christina <tamar.christina@arm.com>
679
680 PR binutils/21446
681 * aarch64-dis.c (no_notes: New.
682 (parse_aarch64_dis_option): Support notes.
683 (aarch64_decode_insn, print_operands): Likewise.
684 (print_aarch64_disassembler_options): Document notes.
685 * aarch64-opc.c (aarch64_print_operand): Support notes.
686
561a72d4
TC		 6872018-05-15 Tamar Christina <tamar.christina@arm.com>
688
689 PR binutils/21446
690 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
691 and take error struct.
692 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
693 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
694 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
695 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
696 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
697 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
698 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
699 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
700 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
701 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
702 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
703 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
704 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
705 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
706 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
707 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
708 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
709 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
710 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
711 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
712 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
713 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
714 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
715 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
716 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
717 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
718 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
719 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
720 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
721 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
722 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
723 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
724 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
725 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
726 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
727 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
728 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
729 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
730 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
731 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
732 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
733 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
734 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
735 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
736 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
737 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
738 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
739 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
740 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
741 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
742 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
743 (determine_disassembling_preference, aarch64_decode_insn,
744 print_insn_aarch64_word, print_insn_data): Take errors struct.
745 (print_insn_aarch64): Use errors.
746 * aarch64-asm-2.c: Regenerate.
747 * aarch64-dis-2.c: Regenerate.
748 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
749 boolean in aarch64_insert_operan.
750 (print_operand_extractor): Likewise.
751 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
752
1678bd35
FT		 7532018-05-15 Francois H. Theron <francois.theron@netronome.com>
754
755 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
756
06cfb1c8
L		 7572018-05-09 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
760
84f9f8c3
AM		 7612018-05-09 Sebastian Rasmussen <sebras@gmail.com>
762
763 * cr16-opc.c (cr16_instruction): Comment typo fix.
764 * hppa-dis.c (print_insn_hppa): Likewise.
765
e6f372ba
JW		 7662018-05-08 Jim Wilson <jimw@sifive.com>
767
768 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
769 (match_c_slli64, match_srxi_as_c_srxi): New.
770 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
771 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
772 <c.slli, c.srli, c.srai>: Use match_s_slli.
773 <c.slli64, c.srli64, c.srai64>: New.
774
f413a913
AM		 7752018-05-08 Alan Modra <amodra@gmail.com>
776
777 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
778 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
779 partition opcode space for index lookup.
780
a87a6478
PB		 7812018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
782
783 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
784 <insn_length>: ...with this. Update usage.
785 Remove duplicate call to *info->memory_error_func.
786
c0a30a9f
L		 7872018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
788 H.J. Lu <hongjiu.lu@intel.com>
789
790 * i386-dis.c (Gva): New.
791 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
792 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
793 (prefix_table): New instructions (see prefix above).
794 (mod_table): New instructions (see prefix above).
795 (OP_G): Handle va_mode.
796 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
797 CPU_MOVDIR64B_FLAGS.
798 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
799 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
800 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
801 * i386-opc.tbl: Add movidir{i,64b}.
802 * i386-init.h: Regenerated.
803 * i386-tbl.h: Likewise.
804
75c0a438
L		 8052018-05-07 H.J. Lu <hongjiu.lu@intel.com>
806
807 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
808 AddrPrefixOpReg.
809 * i386-opc.h (AddrPrefixOp0): Renamed to ...
810 (AddrPrefixOpReg): This.
811 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
812 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
813
2ceb7719
PB		 8142018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
815
816 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
817 (vle_num_opcodes): Likewise.
818 (spe2_num_opcodes): Likewise.
819 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
820 initialization loop.
821 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
822 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
823 only once.
824
b3ac5c6c
TC		 8252018-05-01 Tamar Christina <tamar.christina@arm.com>
826
827 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
828
fe944acf
FT		 8292018-04-30 Francois H. Theron <francois.theron@netronome.com>
830
831 Makefile.am: Added nfp-dis.c.
832 configure.ac: Added bfd_nfp_arch.
833 disassemble.h: Added print_insn_nfp prototype.
834 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
835 nfp-dis.c: New, for NFP support.
836 po/POTFILES.in: Added nfp-dis.c to the list.
837 Makefile.in: Regenerate.
838 configure: Regenerate.
839
e2195274
JB		 8402018-04-26 Jan Beulich <jbeulich@suse.com>
841
842 * i386-opc.tbl: Fold various non-memory operand AVX512VL
843 templates into their base ones.
844 * i386-tlb.h: Re-generate.
845
59ef5df4
JB		 8462018-04-26 Jan Beulich <jbeulich@suse.com>
847
848 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
849 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
850 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
851 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
852 * i386-init.h: Re-generate.
853
6e041cf4
JB		 8542018-04-26 Jan Beulich <jbeulich@suse.com>
855
856 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
857 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
858 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
859 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
860 comment.
861 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
862 and CpuRegMask.
863 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
864 CpuRegMask: Delete.
865 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
866 cpuregzmm, and cpuregmask.
867 * i386-init.h: Re-generate.
868 * i386-tbl.h: Re-generate.
869
0e0eea78
JB		 8702018-04-26 Jan Beulich <jbeulich@suse.com>
871
872 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
873 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
874 * i386-init.h: Re-generate.
875
2f1bada2
JB		 8762018-04-26 Jan Beulich <jbeulich@suse.com>
877
878 * i386-gen.c (VexImmExt): Delete.
879 * i386-opc.h (VexImmExt, veximmext): Delete.
880 * i386-opc.tbl: Drop all VexImmExt uses.
881 * i386-tlb.h: Re-generate.
882
bacd1457
JB		 8832018-04-25 Jan Beulich <jbeulich@suse.com>
884
885 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
886 register-only forms.
887 * i386-tlb.h: Re-generate.
888
10bba94b
TC		 8892018-04-25 Tamar Christina <tamar.christina@arm.com>
890
891 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
892
c48935d7
IT		 8932018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
894
895 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
896 PREFIX_0F1C.
897 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
898 (cpu_flags): Add CpuCLDEMOTE.
899 * i386-init.h: Regenerate.
900 * i386-opc.h (enum): Add CpuCLDEMOTE,
901 (i386_cpu_flags): Add cpucldemote.
902 * i386-opc.tbl: Add cldemote.
903 * i386-tbl.h: Regenerate.
904
211dc24b
AM		 9052018-04-16 Alan Modra <amodra@gmail.com>
906
907 * Makefile.am: Remove sh5 and sh64 support.
908 * configure.ac: Likewise.
909 * disassemble.c: Likewise.
910 * disassemble.h: Likewise.
911 * sh-dis.c: Likewise.
912 * sh64-dis.c: Delete.
913 * sh64-opc.c: Delete.
914 * sh64-opc.h: Delete.
915 * Makefile.in: Regenerate.
916 * configure: Regenerate.
917 * po/POTFILES.in: Regenerate.
918
a9a4b302
AM		 9192018-04-16 Alan Modra <amodra@gmail.com>
920
921 * Makefile.am: Remove w65 support.
922 * configure.ac: Likewise.
923 * disassemble.c: Likewise.
924 * disassemble.h: Likewise.
925 * w65-dis.c: Delete.
926 * w65-opc.h: Delete.
927 * Makefile.in: Regenerate.
928 * configure: Regenerate.
929 * po/POTFILES.in: Regenerate.
930
04cb01fd
AM		 9312018-04-16 Alan Modra <amodra@gmail.com>
932
933 * configure.ac: Remove we32k support.
934 * configure: Regenerate.
935
c2bf1eec
AM		 9362018-04-16 Alan Modra <amodra@gmail.com>
937
938 * Makefile.am: Remove m88k support.
939 * configure.ac: Likewise.
940 * disassemble.c: Likewise.
941 * disassemble.h: Likewise.
942 * m88k-dis.c: Delete.
943 * Makefile.in: Regenerate.
944 * configure: Regenerate.
945 * po/POTFILES.in: Regenerate.
946
6793974d
AM		 9472018-04-16 Alan Modra <amodra@gmail.com>
948
949 * Makefile.am: Remove i370 support.
950 * configure.ac: Likewise.
951 * disassemble.c: Likewise.
952 * disassemble.h: Likewise.
953 * i370-dis.c: Delete.
954 * i370-opc.c: Delete.
955 * Makefile.in: Regenerate.
956 * configure: Regenerate.
957 * po/POTFILES.in: Regenerate.
958
e82aa794
AM		 9592018-04-16 Alan Modra <amodra@gmail.com>
960
961 * Makefile.am: Remove h8500 support.
962 * configure.ac: Likewise.
963 * disassemble.c: Likewise.
964 * disassemble.h: Likewise.
965 * h8500-dis.c: Delete.
966 * h8500-opc.h: Delete.
967 * Makefile.in: Regenerate.
968 * configure: Regenerate.
969 * po/POTFILES.in: Regenerate.
970
fceadf09
AM		 9712018-04-16 Alan Modra <amodra@gmail.com>
972
973 * configure.ac: Remove tahoe support.
974 * configure: Regenerate.
975
ae1d3843
L		 9762018-04-15 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
979 umwait.
980 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
981 64-bit mode.
982 * i386-tbl.h: Regenerated.
983
de89d0a3
IT		 9842018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
985
986 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
987 PREFIX_MOD_1_0FAE_REG_6.
988 (va_mode): New.
989 (OP_E_register): Use va_mode.
990 * i386-dis-evex.h (prefix_table):
991 New instructions (see prefixes above).
992 * i386-gen.c (cpu_flag_init): Add WAITPKG.
993 (cpu_flags): Likewise.
994 * i386-opc.h (enum): Likewise.
995 (i386_cpu_flags): Likewise.
996 * i386-opc.tbl: Add umonitor, umwait, tpause.
997 * i386-init.h: Regenerate.
998 * i386-tbl.h: Likewise.
999
a8eb42a8
AM		 10002018-04-11 Alan Modra <amodra@gmail.com>
1001
1002 * opcodes/i860-dis.c: Delete.
1003 * opcodes/i960-dis.c: Delete.
1004 * Makefile.am: Remove i860 and i960 support.
1005 * configure.ac: Likewise.
1006 * disassemble.c: Likewise.
1007 * disassemble.h: Likewise.
1008 * Makefile.in: Regenerate.
1009 * configure: Regenerate.
1010 * po/POTFILES.in: Regenerate.
1011
caf0678c
L		 10122018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 PR binutils/23025
1015 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1016 to 0.
1017 (print_insn): Clear vex instead of vex.evex.
1018
4fb0d2b9
NC		 10192018-04-04 Nick Clifton <nickc@redhat.com>
1020
1021 * po/es.po: Updated Spanish translation.
1022
c39e5b26
JB		 10232018-03-28 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-gen.c (opcode_modifiers): Delete VecESize.
1026 * i386-opc.h (VecESize): Delete.
1027 (struct i386_opcode_modifier): Delete vecesize.
1028 * i386-opc.tbl: Drop VecESize.
1029 * i386-tlb.h: Re-generate.
1030
8e6e0792
JB		 10312018-03-28 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1034 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1035 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1036 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1037 * i386-tlb.h: Re-generate.
1038
9f123b91
JB		 10392018-03-28 Jan Beulich <jbeulich@suse.com>
1040
1041 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1042 Fold AVX512 forms
1043 * i386-tlb.h: Re-generate.
1044
9646c87b
JB		 10452018-03-28 Jan Beulich <jbeulich@suse.com>
1046
1047 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1048 (vex_len_table): Drop Y for vcvt*2si.
1049 (putop): Replace plain 'Y' handling by abort().
1050
c8d59609
NC		 10512018-03-28 Nick Clifton <nickc@redhat.com>
1052
1053 PR 22988
1054 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1055 instructions with only a base address register.
1056 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1057 handle AARHC64_OPND_SVE_ADDR_R.
1058 (aarch64_print_operand): Likewise.
1059 * aarch64-asm-2.c: Regenerate.
1060 * aarch64_dis-2.c: Regenerate.
1061 * aarch64-opc-2.c: Regenerate.
1062
b8c169f3
JB		 10632018-03-22 Jan Beulich <jbeulich@suse.com>
1064
1065 * i386-opc.tbl: Drop VecESize from register only insn forms and
1066 memory forms not allowing broadcast.
1067 * i386-tlb.h: Re-generate.
1068
96bc132a
JB		 10692018-03-22 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1072 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1073 sha256*): Drop Disp<N>.
1074
9f79e886
JB		 10752018-03-22 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-dis.c (EbndS, bnd_swap_mode): New.
1078 (prefix_table): Use EbndS.
1079 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1080 * i386-opc.tbl (bndmov): Move misplaced Load.
1081 * i386-tlb.h: Re-generate.
1082
d6793fa1
JB		 10832018-03-22 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1086 templates allowing memory operands and folded ones for register
1087 only flavors.
1088 * i386-tlb.h: Re-generate.
1089
f7768225
JB		 10902018-03-22 Jan Beulich <jbeulich@suse.com>
1091
1092 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1093 256-bit templates. Drop redundant leftover Disp<N>.
1094 * i386-tlb.h: Re-generate.
1095
0e35537d
JW		 10962018-03-14 Kito Cheng <kito.cheng@gmail.com>
1097
1098 * riscv-opc.c (riscv_insn_types): New.
1099
b4a3689a
NC		 11002018-03-13 Nick Clifton <nickc@redhat.com>
1101
1102 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1103
d3d50934
L		 11042018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1105
1106 * i386-opc.tbl: Add Optimize to clr.
1107 * i386-tbl.h: Regenerated.
1108
bd5dea88
L		 11092018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1110
1111 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1112 * i386-opc.h (OldGcc): Removed.
1113 (i386_opcode_modifier): Remove oldgcc.
1114 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1115 instructions for old (<= 2.8.1) versions of gcc.
1116 * i386-tbl.h: Regenerated.
1117
e771e7c9
JB		 11182018-03-08 Jan Beulich <jbeulich@suse.com>
1119
1120 * i386-opc.h (EVEXDYN): New.
1121 * i386-opc.tbl: Fold various AVX512VL templates.
1122 * i386-tlb.h: Re-generate.
1123
ed438a93
JB		 11242018-03-08 Jan Beulich <jbeulich@suse.com>
1125
1126 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1127 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1128 vpexpandd, vpexpandq): Fold AFX512VF templates.
1129 * i386-tlb.h: Re-generate.
1130
454172a9
JB		 11312018-03-08 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1134 Fold 128- and 256-bit VEX-encoded templates.
1135 * i386-tlb.h: Re-generate.
1136
36824150
JB		 11372018-03-08 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1140 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1141 vpexpandd, vpexpandq): Fold AVX512F templates.
1142 * i386-tlb.h: Re-generate.
1143
e7f5c0a9
JB		 11442018-03-08 Jan Beulich <jbeulich@suse.com>
1145
1146 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1147 64-bit templates. Drop Disp<N>.
1148 * i386-tlb.h: Re-generate.
1149
25a4277f
JB		 11502018-03-08 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1153 and 256-bit templates.
1154 * i386-tlb.h: Re-generate.
1155
d2224064
JB		 11562018-03-08 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1159 * i386-tlb.h: Re-generate.
1160
1b193f0b
JB		 11612018-03-08 Jan Beulich <jbeulich@suse.com>
1162
1163 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1164 Drop NoAVX.
1165 * i386-tlb.h: Re-generate.
1166
f2f6a710
JB		 11672018-03-08 Jan Beulich <jbeulich@suse.com>
1168
1169 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1170 * i386-tlb.h: Re-generate.
1171
38e314eb
JB		 11722018-03-08 Jan Beulich <jbeulich@suse.com>
1173
1174 * i386-gen.c (opcode_modifiers): Delete FloatD.
1175 * i386-opc.h (FloatD): Delete.
1176 (struct i386_opcode_modifier): Delete floatd.
1177 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1178 FloatD by D.
1179 * i386-tlb.h: Re-generate.
1180
d53e6b98
JB		 11812018-03-08 Jan Beulich <jbeulich@suse.com>
1182
1183 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1184
2907c2f5
JB		 11852018-03-08 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1188 * i386-tlb.h: Re-generate.
1189
73053c1f
JB		 11902018-03-08 Jan Beulich <jbeulich@suse.com>
1191
1192 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1193 forms.
1194 * i386-tlb.h: Re-generate.
1195
52fe4420
AM		 11962018-03-07 Alan Modra <amodra@gmail.com>
1197
1198 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1199 bfd_arch_rs6000.
1200 * disassemble.h (print_insn_rs6000): Delete.
1201 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1202 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1203 (print_insn_rs6000): Delete.
1204
a6743a54
AM		 12052018-03-03 Alan Modra <amodra@gmail.com>
1206
1207 * sysdep.h (opcodes_error_handler): Define.
1208 (_bfd_error_handler): Declare.
1209 * Makefile.am: Remove stray #.
1210 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1211 EDIT" comment.
1212 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1213 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1214 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1215 opcodes_error_handler to print errors. Standardize error messages.
1216 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1217 and include opintl.h.
1218 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1219 * i386-gen.c: Standardize error messages.
1220 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1221 * Makefile.in: Regenerate.
1222 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1223 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1224 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1225 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1226 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1227 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1228 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1229 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1230 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1231 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1232 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1233 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1234 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1235
8305403a
L		 12362018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1237
1238 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1239 vpsub[bwdq] instructions.
1240 * i386-tbl.h: Regenerated.
1241
e184813f
AM		 12422018-03-01 Alan Modra <amodra@gmail.com>
1243
1244 * configure.ac (ALL_LINGUAS): Sort.
1245 * configure: Regenerate.
1246
5b616bef
TP		 12472018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1248
1249 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1250 macro by assignements.
1251
b6f8c7c4
L		 12522018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 PR gas/22871
1255 * i386-gen.c (opcode_modifiers): Add Optimize.
1256 * i386-opc.h (Optimize): New enum.
1257 (i386_opcode_modifier): Add optimize.
1258 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1259 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1260 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1261 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1262 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1263 vpxord and vpxorq.
1264 * i386-tbl.h: Regenerated.
1265
e95b887f
AM		 12662018-02-26 Alan Modra <amodra@gmail.com>
1267
1268 * crx-dis.c (getregliststring): Allocate a large enough buffer
1269 to silence false positive gcc8 warning.
1270
0bccfb29
JW		 12712018-02-22 Shea Levy <shea@shealevy.com>
1272
1273 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1274
6b6b6807
L		 12752018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1276
1277 * i386-opc.tbl: Add {rex},
1278 * i386-tbl.h: Regenerated.
1279
75f31665
MR		 12802018-02-20 Maciej W. Rozycki <macro@mips.com>
1281
1282 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1283 (mips16_opcodes): Replace `M' with `m' for "restore".
1284
e207bc53
TP		 12852018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1286
1287 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1288
87993319
MR		 12892018-02-13 Maciej W. Rozycki <macro@mips.com>
1290
1291 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1292 variable to `function_index'.
1293
68d20676
NC		 12942018-02-13 Nick Clifton <nickc@redhat.com>
1295
1296 PR 22823
1297 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1298 about truncation of printing.
1299
d2159fdc
HW		 13002018-02-12 Henry Wong <henry@stuffedcow.net>
1301
1302 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1303
f174ef9f
NC		 13042018-02-05 Nick Clifton <nickc@redhat.com>
1305
1306 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1307
be3a8dca
IT		 13082018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1309
1310 * i386-dis.c (enum): Add pconfig.
1311 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1312 (cpu_flags): Add CpuPCONFIG.
1313 * i386-opc.h (enum): Add CpuPCONFIG.
1314 (i386_cpu_flags): Add cpupconfig.
1315 * i386-opc.tbl: Add PCONFIG instruction.
1316 * i386-init.h: Regenerate.
1317 * i386-tbl.h: Likewise.
1318
3233d7d0
IT		 13192018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1320
1321 * i386-dis.c (enum): Add PREFIX_0F09.
1322 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1323 (cpu_flags): Add CpuWBNOINVD.
1324 * i386-opc.h (enum): Add CpuWBNOINVD.
1325 (i386_cpu_flags): Add cpuwbnoinvd.
1326 * i386-opc.tbl: Add WBNOINVD instruction.
1327 * i386-init.h: Regenerate.
1328 * i386-tbl.h: Likewise.
1329
e925c834
JW		 13302018-01-17 Jim Wilson <jimw@sifive.com>
1331
1332 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1333
d777820b
IT		 13342018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1335
1336 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1337 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1338 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1339 (cpu_flags): Add CpuIBT, CpuSHSTK.
1340 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1341 (i386_cpu_flags): Add cpuibt, cpushstk.
1342 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1343 * i386-init.h: Regenerate.
1344 * i386-tbl.h: Likewise.
1345
f6efed01
NC		 13462018-01-16 Nick Clifton <nickc@redhat.com>
1347
1348 * po/pt_BR.po: Updated Brazilian Portugese translation.
1349 * po/de.po: Updated German translation.
1350
2721d702
JW		 13512018-01-15 Jim Wilson <jimw@sifive.com>
1352
1353 * riscv-opc.c (match_c_nop): New.
1354 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1355
616dcb87
NC		 13562018-01-15 Nick Clifton <nickc@redhat.com>
1357
1358 * po/uk.po: Updated Ukranian translation.
1359
3957a496
NC		 13602018-01-13 Nick Clifton <nickc@redhat.com>
1361
1362 * po/opcodes.pot: Regenerated.
1363
769c7ea5
NC		 13642018-01-13 Nick Clifton <nickc@redhat.com>
1365
1366 * configure: Regenerate.
1367
faf766e3
NC		 13682018-01-13 Nick Clifton <nickc@redhat.com>
1369
1370 2.30 branch created.
1371
888a89da
IT		 13722018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1373
1374 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1375 * i386-tbl.h: Regenerate.
1376
cbda583a
JB		 13772018-01-10 Jan Beulich <jbeulich@suse.com>
1378
1379 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1380 * i386-tbl.h: Re-generate.
1381
c9e92278
JB		 13822018-01-10 Jan Beulich <jbeulich@suse.com>
1383
1384 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1385 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1386 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1387 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1388 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1389 Disp8MemShift of AVX512VL forms.
1390 * i386-tbl.h: Re-generate.
1391
35fd2b2b
JW		 13922018-01-09 Jim Wilson <jimw@sifive.com>
1393
1394 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1395 then the hi_addr value is zero.
1396
91d8b670
JG		 13972018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1398
1399 * arm-dis.c (arm_opcodes): Add csdb.
1400 (thumb32_opcodes): Add csdb.
1401
be2e7d95
JG		 14022018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1403
1404 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1405 * aarch64-asm-2.c: Regenerate.
1406 * aarch64-dis-2.c: Regenerate.
1407 * aarch64-opc-2.c: Regenerate.
1408
704a705d
L		 14092018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1410
1411 PR gas/22681
1412 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1413 Remove AVX512 vmovd with 64-bit operands.
1414 * i386-tbl.h: Regenerated.
1415
35eeb78f
JW		 14162018-01-05 Jim Wilson <jimw@sifive.com>
1417
1418 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1419 jalr.
1420
219d1afa
AM		 14212018-01-03 Alan Modra <amodra@gmail.com>
1422
1423 Update year range in copyright notice of all files.
1424
1508bbf5
JB		 14252018-01-02 Jan Beulich <jbeulich@suse.com>
1426
1427 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1428 and OPERAND_TYPE_REGZMM entries.
1429
1e563868 1430For older changes see ChangeLog-2017
3499769a 1431\f
1e563868 1432Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1433
1434Copying and distribution of this file, with or without modification,
1435are permitted in any medium without royalty provided the copyright
1436notice and this notice are preserved.
1437
1438Local Variables:
1439mode: change-log
1440left-margin: 8
1441fill-column: 74
1442version-control: never
1443End:
GDB Binutils - Deliverables
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