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gas/ELF: slightly relax elf/file*.d expectations
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1eac08cc
DD		 12015-12-07 DJ Delorie <dj@redhat.com>
2
3 * rl78-decode.opc: Enable MULU for all ISAs.
4 * rl78-decode.c: Regenerate.
5
dd2887fc
AM		 62015-12-07 Alan Modra <amodra@gmail.com>
7
8 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
9 major opcode/xop.
10
24b368f8
CZ		 112015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
12
13 * arc-dis.c (special_flag_p): Match full mnemonic.
14 * arc-opc.c (print_insn_arc): Check section size to read
15 appropriate number of bytes. Fix printing.
16 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
17 arguments.
18
3395762e
AV		 192015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
20
21 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
22 <ldah>: ... to this.
23
622b9eb1
MW		 242015-11-27 Matthew Wahab <matthew.wahab@arm.com>
25
26 * aarch64-asm-2.c: Regenerate.
27 * aarch64-dis-2.c: Regenerate.
28 * aarch64-opc-2.c: Regenerate.
29 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
30 (QL_INT2FP_H, QL_FP2INT_H): New.
31 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
32 (QL_DST_H): New.
33 (QL_FCCMP_H): New.
34 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
35 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
36 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
37 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
38 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
39 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
40 fcsel.
41
cf86120b
MW		 422015-11-27 Matthew Wahab <matthew.wahab@arm.com>
43
44 * aarch64-opc.c (half_conv_t): New.
45 (expand_fp_imm): Replace is_dp flag with the parameter size to
46 specify the number of bytes for the required expansion. Treat
47 a 16-bit expansion like a 32-bit expansion. Add check for an
48 unsupported size request. Update comment.
49 (aarch64_print_operand): Update to support 16-bit floating point
50 values. Update for changes to expand_fp_imm.
51
3bd894a7
MW		 522015-11-27 Matthew Wahab <matthew.wahab@arm.com>
53
54 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
55 (FP_F16): New.
56
64357d2e
MW		 572015-11-27 Matthew Wahab <matthew.wahab@arm.com>
58
59 * aarch64-asm-2.c: Regenerate.
60 * aarch64-dis-2.c: Regenerate.
61 * aarch64-opc-2.c: Regenerate.
62 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
63 "rev64".
64
d685192a
MW		 652015-11-27 Matthew Wahab <matthew.wahab@arm.com>
66
67 * aarch64-asm-2.c: Regenerate.
68 * aarch64-asm.c (convert_bfc_to_bfm): New.
69 (convert_to_real): Add case for OP_BFC.
70 * aarch64-dis-2.c: Regenerate.
71 * aarch64-dis.c: (convert_bfm_to_bfc): New.
72 (convert_to_alias): Add case for OP_BFC.
73 * aarch64-opc-2.c: Regenerate.
74 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
75 to allow width operand in three-operand instructions.
76 * aarch64-tbl.h (QL_BF1): New.
77 (aarch64_feature_v8_2): New.
78 (ARMV8_2): New.
79 (aarch64_opcode_table): Add "bfc".
80
35822b38
MW		 812015-11-27 Matthew Wahab <matthew.wahab@arm.com>
82
83 * aarch64-asm-2.c: Regenerate.
84 * aarch64-dis-2.c: Regenerate.
85 * aarch64-dis.c: Weaken assert.
86 * aarch64-gen.c: Include the instruction in the list of its
87 possible aliases.
88
1a04d1a7
MW		 892015-11-27 Matthew Wahab <matthew.wahab@arm.com>
90
91 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
92 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
93 feature test.
94
e49d43ff
TG		 952015-11-23 Tristan Gingold <gingold@adacore.com>
96
97 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
98
250aafa4
MW		 992015-11-20 Matthew Wahab <matthew.wahab@arm.com>
100
101 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
102 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
103 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
104 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
105 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
106 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
107 cnthv_ctl_el2, cnthv_cval_el2.
108 (aarch64_sys_reg_supported_p): Update for the new system
109 registers.
110
a915c10f
NC		 1112015-11-20 Nick Clifton <nickc@redhat.com>
112
113 PR binutils/19224
114 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
115
f8c2a965
NC		 1162015-11-20 Nick Clifton <nickc@redhat.com>
117
118 * po/zh_CN.po: Updated simplified Chinese translation.
119
c2825638
MW		 1202015-11-19 Matthew Wahab <matthew.wahab@arm.com>
121
122 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
123 of MSR PAN immediate operand.
124
e7286c56
NC		 1252015-11-16 Nick Clifton <nickc@redhat.com>
126
127 * rx-dis.c (condition_names): Replace always and never with
128 invalid, since the always/never conditions can never be legal.
129
d8bd95ef
TG		 1302015-11-13 Tristan Gingold <gingold@adacore.com>
131
132 * configure: Regenerate.
133
a680de9a
PB		 1342015-11-11 Alan Modra <amodra@gmail.com>
135 Peter Bergner <bergner@vnet.ibm.com>
136
137 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
138 Add PPC_OPCODE_VSX3 to the vsx entry.
139 (powerpc_init_dialect): Set default dialect to power9.
140 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
141 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
142 extract_l1 insert_xtq6, extract_xtq6): New static functions.
143 (insert_esync): Test for illegal L operand value.
144 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
145 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
146 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
147 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
148 PPCVSX3): New defines.
149 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
150 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
151 <mcrxr>: Use XBFRARB_MASK.
152 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
153 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
154 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
155 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
156 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
157 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
158 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
159 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
160 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
161 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
162 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
163 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
164 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
165 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
166 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
167 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
168 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
169 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
170 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
171 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
172 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
173 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
174 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
175 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
176 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
177 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
178 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
179 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
180 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
181 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
182 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
183 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
184
854eb72b
NC		 1852015-11-02 Nick Clifton <nickc@redhat.com>
186
187 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
188 instructions.
189 * rx-decode.c: Regenerate.
190
e292aa7a
NC		 1912015-11-02 Nick Clifton <nickc@redhat.com>
192
193 * rx-decode.opc (rx_disp): If the displacement is zero, set the
194 type to RX_Operand_Zero_Indirect.
195 * rx-decode.c: Regenerate.
196 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
197
43cdf5ae
YQ		 1982015-10-28 Yao Qi <yao.qi@linaro.org>
199
200 * aarch64-dis.c (aarch64_decode_insn): Add one argument
201 noaliases_p. Update comments. Pass noaliases_p rather than
202 no_aliases to aarch64_opcode_decode.
203 (print_insn_aarch64_word): Pass no_aliases to
204 aarch64_decode_insn.
205
c2f28758
VK		 2062015-10-27 Vinay <Vinay.G@kpit.com>
207
208 PR binutils/19159
209 * rl78-decode.opc (MOV): Added offset to DE register in index
210 addressing mode.
211 * rl78-decode.c: Regenerate.
212
46662804
VK		 2132015-10-27 Vinay Kumar <vinay.g@kpit.com>
214
215 PR binutils/19158
216 * rl78-decode.opc: Add 's' print operator to instructions that
217 access system registers.
218 * rl78-decode.c: Regenerate.
219 * rl78-dis.c (print_insn_rl78_common): Decode all system
220 registers.
221
02f12cd4
VK		 2222015-10-27 Vinay Kumar <vinay.g@kpit.com>
223
224 PR binutils/19157
225 * rl78-decode.opc: Add 'a' print operator to mov instructions
226 using stack pointer plus index addressing.
227 * rl78-decode.c: Regenerate.
228
485f23cf
AK		 2292015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
230
231 * s390-opc.c: Fix comment.
232 * s390-opc.txt: Change instruction type for troo, trot, trto, and
233 trtt to RRF_U0RER since the second parameter does not need to be a
234 register pair.
235
3f94e60d
NC		 2362015-10-08 Nick Clifton <nickc@redhat.com>
237
238 * arc-dis.c (print_insn_arc): Initiallise insn array.
239
875880c6
YQ		 2402015-10-07 Yao Qi <yao.qi@linaro.org>
241
242 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
243 'name' rather than 'template'.
244 * aarch64-opc.c (aarch64_print_operand): Likewise.
245
886a2506
NC		 2462015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
247
248 * arc-dis.c: Revamped file for ARC support
249 * arc-dis.h: Likewise.
250 * arc-ext.c: Likewise.
251 * arc-ext.h: Likewise.
252 * arc-opc.c: Likewise.
253 * arc-fxi.h: New file.
254 * arc-regs.h: Likewise.
255 * arc-tbl.h: Likewise.
256
36f4aab1
YQ		 2572015-10-02 Yao Qi <yao.qi@linaro.org>
258
259 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
260 argument insn type to aarch64_insn. Rename to ...
261 (aarch64_decode_insn): ... it.
262 (print_insn_aarch64_word): Caller updated.
263
7232d389
YQ		 2642015-10-02 Yao Qi <yao.qi@linaro.org>
265
266 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
267 (print_insn_aarch64_word): Caller updated.
268
7ecc513a
DV		 2692015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
270
271 * s390-mkopc.c (main): Parse htm and vx flag.
272 * s390-opc.txt: Mark instructions from the hardware transactional
273 memory and vector facilities with the "htm"/"vx" flag.
274
b08b78e7
NC		 2752015-09-28 Nick Clifton <nickc@redhat.com>
276
277 * po/de.po: Updated German translation.
278
36f7a941
TR		 2792015-09-28 Tom Rix <tom@bumblecow.com>
280
281 * ppc-opc.c (PPC500): Mark some opcodes as invalid
282
b6518b38
NC		 2832015-09-23 Nick Clifton <nickc@redhat.com>
284
285 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
286 function.
287 * tic30-dis.c (print_branch): Likewise.
288 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
289 value before left shifting.
290 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
291 * hppa-dis.c (print_insn_hppa): Likewise.
292 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
293 array.
294 * msp430-dis.c (msp430_singleoperand): Likewise.
295 (msp430_doubleoperand): Likewise.
296 (print_insn_msp430): Likewise.
297 * nds32-asm.c (parse_operand): Likewise.
298 * sh-opc.h (MASK): Likewise.
299 * v850-dis.c (get_operand_value): Likewise.
300
f04265ec
NC		 3012015-09-22 Nick Clifton <nickc@redhat.com>
302
303 * rx-decode.opc (bwl): Use RX_Bad_Size.
304 (sbwl): Likewise.
305 (ubwl): Likewise. Rename to ubw.
306 (uBWL): Rename to uBW.
307 Replace all references to uBWL with uBW.
308 * rx-decode.c: Regenerate.
309 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
310 (opsize_names): Likewise.
311 (print_insn_rx): Detect and report RX_Bad_Size.
312
6dca4fd1
AB		 3132015-09-22 Anton Blanchard <anton@samba.org>
314
315 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
316
38074311
JM		 3172015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
318
319 * sparc-dis.c (print_insn_sparc): Handle the privileged register
320 %pmcdper.
321
5f40e14d
JS		 3222015-08-24 Jan Stancek <jstancek@redhat.com>
323
324 * i386-dis.c (print_insn): Fix decoding of three byte operands.
325
ab4e4ed5
AF		 3262015-08-21 Alexander Fomin <alexander.fomin@intel.com>
327
328 PR binutils/18257
329 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
330 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
331 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
332 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
333 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
334 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
335 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
336 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
337 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
338 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
339 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
340 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
341 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
342 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
343 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
344 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
345 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
346 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
347 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
348 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
349 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
350 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
351 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
352 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
353 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
354 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
355 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
356 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
357 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
358 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
359 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
360 (vex_w_table): Replace terminals with MOD_TABLE entries for
361 most of mask instructions.
362
919b75f7
AM		 3632015-08-17 Alan Modra <amodra@gmail.com>
364
365 * cgen.sh: Trim trailing space from cgen output.
366 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
367 (print_dis_table): Likewise.
368 * opc2c.c (dump_lines): Likewise.
369 (orig_filename): Warning fix.
370 * ia64-asmtab.c: Regenerate.
371
4ab90a7a
AV		 3722015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
373
374 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
375 and higher with ARM instruction set will now mark the 26-bit
376 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
377 (arm_opcodes): Fix for unpredictable nop being recognized as a
378 teq.
379
40fc1451
SD		 3802015-08-12 Simon Dardis <simon.dardis@imgtec.com>
381
382 * micromips-opc.c (micromips_opcodes): Re-order table so that move
383 based on 'or' is first.
384 * mips-opc.c (mips_builtin_opcodes): Ditto.
385
922c5db5
NC		 3862015-08-11 Nick Clifton <nickc@redhat.com>
387
388 PR 18800
389 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
390 instruction.
391
75fb7498
RS		 3922015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
393
394 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
395
36aed29d
AP		 3962015-08-07 Amit Pawar <Amit.Pawar@amd.com>
397
398 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
399 * i386-init.h: Regenerated.
400
a8484f96
L		 4012015-07-30 H.J. Lu <hongjiu.lu@intel.com>
402
403 PR binutils/13571
404 * i386-dis.c (MOD_0FC3): New.
405 (PREFIX_0FC3): Renamed to ...
406 (PREFIX_MOD_0_0FC3): This.
407 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
408 (prefix_table): Replace Ma with Ev on movntiS.
409 (mod_table): Add MOD_0FC3.
410
37a42ee9
L		 4112015-07-27 H.J. Lu <hongjiu.lu@intel.com>
412
413 * configure: Regenerated.
414
070fe95d
AM		 4152015-07-23 Alan Modra <amodra@gmail.com>
416
417 PR 18708
418 * i386-dis.c (get64): Avoid signed integer overflow.
419
20c2a615
L		 4202015-07-22 Alexander Fomin <alexander.fomin@intel.com>
421
422 PR binutils/18631
423 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
424 "EXEvexHalfBcstXmmq" for the second operand.
425 (EVEX_W_0F79_P_2): Likewise.
426 (EVEX_W_0F7A_P_2): Likewise.
427 (EVEX_W_0F7B_P_2): Likewise.
428
6f1c2142
AM		 4292015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
430
431 * arm-dis.c (print_insn_coprocessor): Added support for quarter
432 float bitfield format.
433 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
434 quarter float bitfield format.
435
8a643cc3
L		 4362015-07-14 H.J. Lu <hongjiu.lu@intel.com>
437
438 * configure: Regenerated.
439
ef5a96d5
AM		 4402015-07-03 Alan Modra <amodra@gmail.com>
441
442 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
443 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
444 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
445
c8c8175b
SL		 4462015-07-01 Sandra Loosemore <sandra@codesourcery.com>
447 Cesar Philippidis <cesar@codesourcery.com>
448
449 * nios2-dis.c (nios2_extract_opcode): New.
450 (nios2_disassembler_state): New.
451 (nios2_find_opcode_hash): Use mach parameter to select correct
452 disassembler state.
453 (nios2_print_insn_arg): Extend to support new R2 argument letters
454 and formats.
455 (print_insn_nios2): Check for 16-bit instruction at end of memory.
456 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
457 (NIOS2_NUM_OPCODES): Rename to...
458 (NIOS2_NUM_R1_OPCODES): This.
459 (nios2_r2_opcodes): New.
460 (NIOS2_NUM_R2_OPCODES): New.
461 (nios2_num_r2_opcodes): New.
462 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
463 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
464 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
465 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
466 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
467
9916071f
AP		 4682015-06-30 Amit Pawar <Amit.Pawar@amd.com>
469
470 * i386-dis.c (OP_Mwaitx): New.
471 (rm_table): Add monitorx/mwaitx.
472 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
473 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
474 (operand_type_init): Add CpuMWAITX.
475 * i386-opc.h (CpuMWAITX): New.
476 (i386_cpu_flags): Add cpumwaitx.
477 * i386-opc.tbl: Add monitorx and mwaitx.
478 * i386-init.h: Regenerated.
479 * i386-tbl.h: Likewise.
480
7b934113
PB		 4812015-06-22 Peter Bergner <bergner@vnet.ibm.com>
482
483 * ppc-opc.c (insert_ls): Test for invalid LS operands.
484 (insert_esync): New function.
485 (LS, WC): Use insert_ls.
486 (ESYNC): Use insert_esync.
487
bdc4de1b
NC		 4882015-06-22 Nick Clifton <nickc@redhat.com>
489
490 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
491 requested region lies beyond it.
492 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
493 looking for 32-bit insns.
494 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
495 data.
496 * sh-dis.c (print_insn_sh): Likewise.
497 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
498 blocks of instructions.
499 * vax-dis.c (print_insn_vax): Check that the requested address
500 does not clash with the stop_vma.
501
11a0cf2e
PB		 5022015-06-19 Peter Bergner <bergner@vnet.ibm.com>
503
070fe95d 504 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 505 * ppc-opc.c (FXM4): Add non-zero optional value.
506 (TBR): Likewise.
507 (SXL): Likewise.
508 (insert_fxm): Handle new default operand value.
509 (extract_fxm): Likewise.
510 (insert_tbr): Likewise.
511 (extract_tbr): Likewise.
512
bdfa8b95
MW		 5132015-06-16 Matthew Wahab <matthew.wahab@arm.com>
514
515 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
516
24b4cf66
SN		 5172015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
518
519 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
520
99a2c561
PB		 5212015-06-12 Peter Bergner <bergner@vnet.ibm.com>
522
523 * ppc-opc.c: Add comment accidentally removed by old commit.
524 (MTMSRD_L): Delete.
525
40f77f82
AM		 5262015-06-04 Peter Bergner <bergner@vnet.ibm.com>
527
528 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
529
13be46a2
NC		 5302015-06-04 Nick Clifton <nickc@redhat.com>
531
532 PR 18474
533 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
534
ddfded2f
MW		 5352015-06-02 Matthew Wahab <matthew.wahab@arm.com>
536
537 * arm-dis.c (arm_opcodes): Add "setpan".
538 (thumb_opcodes): Add "setpan".
539
1af1dd51
MW		 5402015-06-02 Matthew Wahab <matthew.wahab@arm.com>
541
542 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
543 macros.
544
9e1f0fa7
MW		 5452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
546
547 * aarch64-tbl.h (aarch64_feature_rdma): New.
548 (RDMA): New.
549 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
550 * aarch64-asm-2.c: Regenerate.
551 * aarch64-dis-2.c: Regenerate.
552 * aarch64-opc-2.c: Regenerate.
553
290806fd
MW		 5542015-06-02 Matthew Wahab <matthew.wahab@arm.com>
555
556 * aarch64-tbl.h (aarch64_feature_lor): New.
557 (LOR): New.
558 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
559 "stllrb", "stllrh".
560 * aarch64-asm-2.c: Regenerate.
561 * aarch64-dis-2.c: Regenerate.
562 * aarch64-opc-2.c: Regenerate.
563
f21cce2c
MW		 5642015-06-01 Matthew Wahab <matthew.wahab@arm.com>
565
566 * aarch64-opc.c (F_ARCHEXT): New.
567 (aarch64_sys_regs): Add "pan".
568 (aarch64_sys_reg_supported_p): New.
569 (aarch64_pstatefields): Add "pan".
570 (aarch64_pstatefield_supported_p): New.
571
d194d186
JB		 5722015-06-01 Jan Beulich <jbeulich@suse.com>
573
574 * i386-tbl.h: Regenerate.
575
3a8547d2
JB		 5762015-06-01 Jan Beulich <jbeulich@suse.com>
577
578 * i386-dis.c (print_insn): Swap rounding mode specifier and
579 general purpose register in Intel mode.
580
015c54d5
JB		 5812015-06-01 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
584 * i386-tbl.h: Regenerate.
585
071f0063
L		 5862015-05-18 H.J. Lu <hongjiu.lu@intel.com>
587
588 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
589 * i386-init.h: Regenerated.
590
5db04b09
L		 5912015-05-15 H.J. Lu <hongjiu.lu@intel.com>
592
593 PR binutis/18386
594 * i386-dis.c: Add comments for '@'.
595 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
596 (enum x86_64_isa): New.
597 (isa64): Likewise.
598 (print_i386_disassembler_options): Add amd64 and intel64.
599 (print_insn): Handle amd64 and intel64.
600 (putop): Handle '@'.
601 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
602 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
603 * i386-opc.h (AMD64): New.
604 (CpuIntel64): Likewise.
605 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
606 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
607 Mark direct call/jmp without Disp16|Disp32 as Intel64.
608 * i386-init.h: Regenerated.
609 * i386-tbl.h: Likewise.
610
4bc0608a
PB		 6112015-05-14 Peter Bergner <bergner@vnet.ibm.com>
612
613 * ppc-opc.c (IH) New define.
614 (powerpc_opcodes) <wait>: Do not enable for POWER7.
615 <tlbie>: Add RS operand for POWER7.
616 <slbia>: Add IH operand for POWER6.
617
70cead07
L		 6182015-05-11 H.J. Lu <hongjiu.lu@intel.com>
619
620 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
621 direct branch.
622 (jmp): Likewise.
623 * i386-tbl.h: Regenerated.
624
7b6d09fb
L		 6252015-05-11 H.J. Lu <hongjiu.lu@intel.com>
626
627 * configure.ac: Support bfd_iamcu_arch.
628 * disassemble.c (disassembler): Support bfd_iamcu_arch.
629 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
630 CPU_IAMCU_COMPAT_FLAGS.
631 (cpu_flags): Add CpuIAMCU.
632 * i386-opc.h (CpuIAMCU): New.
633 (i386_cpu_flags): Add cpuiamcu.
634 * configure: Regenerated.
635 * i386-init.h: Likewise.
636 * i386-tbl.h: Likewise.
637
31955f99
L		 6382015-05-08 H.J. Lu <hongjiu.lu@intel.com>
639
640 PR binutis/18386
641 * i386-dis.c (X86_64_E8): New.
642 (X86_64_E9): Likewise.
643 Update comments on 'T', 'U', 'V'. Add comments for '^'.
644 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
645 (x86_64_table): Add X86_64_E8 and X86_64_E9.
646 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
647 (putop): Handle '^'.
648 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
649 REX_W.
650
0952813b
DD		 6512015-04-30 DJ Delorie <dj@redhat.com>
652
653 * disassemble.c (disassembler): Choose suitable disassembler based
654 on E_ABI.
655 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
656 it to decode mul/div insns.
657 * rl78-decode.c: Regenerate.
658 * rl78-dis.c (print_insn_rl78): Rename to...
659 (print_insn_rl78_common): ...this, take ISA parameter.
660 (print_insn_rl78): New.
661 (print_insn_rl78_g10): New.
662 (print_insn_rl78_g13): New.
663 (print_insn_rl78_g14): New.
664 (rl78_get_disassembler): New.
665
f9d3ecaa
NC		 6662015-04-29 Nick Clifton <nickc@redhat.com>
667
668 * po/fr.po: Updated French translation.
669
4fff86c5
PB		 6702015-04-27 Peter Bergner <bergner@vnet.ibm.com>
671
672 * ppc-opc.c (DCBT_EO): New define.
673 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
674 <lharx>: Likewise.
675 <stbcx.>: Likewise.
676 <sthcx.>: Likewise.
677 <waitrsv>: Do not enable for POWER7 and later.
678 <waitimpl>: Likewise.
679 <dcbt>: Default to the two operand form of the instruction for all
680 "old" cpus. For "new" cpus, use the operand ordering that matches
681 whether the cpu is server or embedded.
682 <dcbtst>: Likewise.
683
3b78cfe1
AK		 6842015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
685
686 * s390-opc.c: New instruction type VV0UU2.
687 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
688 and WFC.
689
04d824a4
JB		 6902015-04-23 Jan Beulich <jbeulich@suse.com>
691
692 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
693 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
694 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
695 (vfpclasspd, vfpclassps): Add %XZ.
696
09708981
L		 6972015-04-15 H.J. Lu <hongjiu.lu@intel.com>
698
699 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
700 (PREFIX_UD_REPZ): Likewise.
701 (PREFIX_UD_REPNZ): Likewise.
702 (PREFIX_UD_DATA): Likewise.
703 (PREFIX_UD_ADDR): Likewise.
704 (PREFIX_UD_LOCK): Likewise.
705
3888916d
L		 7062015-04-15 H.J. Lu <hongjiu.lu@intel.com>
707
708 * i386-dis.c (prefix_requirement): Removed.
709 (print_insn): Don't set prefix_requirement. Check
710 dp->prefix_requirement instead of prefix_requirement.
711
f24bcbaa
L		 7122015-04-15 H.J. Lu <hongjiu.lu@intel.com>
713
714 PR binutils/17898
715 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
716 (PREFIX_MOD_0_0FC7_REG_6): This.
717 (PREFIX_MOD_3_0FC7_REG_6): New.
718 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
719 (prefix_table): Replace PREFIX_0FC7_REG_6 with
720 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
721 PREFIX_MOD_3_0FC7_REG_7.
722 (mod_table): Replace PREFIX_0FC7_REG_6 with
723 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
724 PREFIX_MOD_3_0FC7_REG_7.
725
507bd325
L		 7262015-04-15 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
729 (PREFIX_MANDATORY_REPNZ): Likewise.
730 (PREFIX_MANDATORY_DATA): Likewise.
731 (PREFIX_MANDATORY_ADDR): Likewise.
732 (PREFIX_MANDATORY_LOCK): Likewise.
733 (PREFIX_MANDATORY): Likewise.
734 (PREFIX_UD_SHIFT): Set to 8
735 (PREFIX_UD_REPZ): Updated.
736 (PREFIX_UD_REPNZ): Likewise.
737 (PREFIX_UD_DATA): Likewise.
738 (PREFIX_UD_ADDR): Likewise.
739 (PREFIX_UD_LOCK): Likewise.
740 (PREFIX_IGNORED_SHIFT): New.
741 (PREFIX_IGNORED_REPZ): Likewise.
742 (PREFIX_IGNORED_REPNZ): Likewise.
743 (PREFIX_IGNORED_DATA): Likewise.
744 (PREFIX_IGNORED_ADDR): Likewise.
745 (PREFIX_IGNORED_LOCK): Likewise.
746 (PREFIX_OPCODE): Likewise.
747 (PREFIX_IGNORED): Likewise.
748 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
749 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
750 (three_byte_table): Likewise.
751 (mod_table): Likewise.
752 (mandatory_prefix): Renamed to ...
753 (prefix_requirement): This.
754 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
755 Update PREFIX_90 entry.
756 (get_valid_dis386): Check prefix_requirement to see if a prefix
757 should be ignored.
758 (print_insn): Replace mandatory_prefix with prefix_requirement.
759
f0fba320
RL		 7602015-04-15 Renlin Li <renlin.li@arm.com>
761
762 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
763 use it for ssat and ssat16.
764 (print_insn_thumb32): Add handle case for 'D' control code.
765
bf890a93
IT		 7662015-04-06 Ilya Tocar <ilya.tocar@intel.com>
767 H.J. Lu <hongjiu.lu@intel.com>
768
769 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
770 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
771 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
772 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
773 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
774 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
775 Fill prefix_requirement field.
776 (struct dis386): Add prefix_requirement field.
777 (dis386): Fill prefix_requirement field.
778 (dis386_twobyte): Ditto.
779 (twobyte_has_mandatory_prefix_: Remove.
780 (reg_table): Fill prefix_requirement field.
781 (prefix_table): Ditto.
782 (x86_64_table): Ditto.
783 (three_byte_table): Ditto.
784 (xop_table): Ditto.
785 (vex_table): Ditto.
786 (vex_len_table): Ditto.
787 (vex_w_table): Ditto.
788 (mod_table): Ditto.
789 (bad_opcode): Ditto.
790 (print_insn): Use prefix_requirement.
791 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
792 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
793 (float_reg): Ditto.
794
2f783c1f
MF		 7952015-03-30 Mike Frysinger <vapier@gentoo.org>
796
797 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
798
b9d94d62
L		 7992015-03-29 H.J. Lu <hongjiu.lu@intel.com>
800
801 * Makefile.in: Regenerated.
802
27c49e9a
AB		 8032015-03-25 Anton Blanchard <anton@samba.org>
804
805 * ppc-dis.c (disassemble_init_powerpc): Only initialise
806 powerpc_opcd_indices and vle_opcd_indices once.
807
c4e676f1
AB		 8082015-03-25 Anton Blanchard <anton@samba.org>
809
810 * ppc-opc.c (powerpc_opcodes): Add slbfee.
811
823d2571
TG		 8122015-03-24 Terry Guo <terry.guo@arm.com>
813
814 * arm-dis.c (opcode32): Updated to use new arm feature struct.
815 (opcode16): Likewise.
816 (coprocessor_opcodes): Replace bit with feature struct.
817 (neon_opcodes): Likewise.
818 (arm_opcodes): Likewise.
819 (thumb_opcodes): Likewise.
820 (thumb32_opcodes): Likewise.
821 (print_insn_coprocessor): Likewise.
822 (print_insn_arm): Likewise.
823 (select_arm_features): Follow new feature struct.
824
029f3522
GG		 8252015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
826
827 * i386-dis.c (rm_table): Add clzero.
828 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
829 Add CPU_CLZERO_FLAGS.
830 (cpu_flags): Add CpuCLZERO.
831 * i386-opc.h: Add CpuCLZERO.
832 * i386-opc.tbl: Add clzero.
833 * i386-init.h: Re-generated.
834 * i386-tbl.h: Re-generated.
835
6914869a
AB		 8362015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
837
838 * mips-opc.c (decode_mips_operand): Fix constraint issues
839 with u and y operands.
840
21e20815
AB		 8412015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
842
843 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
844
6b1d7593
AK		 8452015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
846
847 * s390-opc.c: Add new IBM z13 instructions.
848 * s390-opc.txt: Likewise.
849
c8f89a34
JW		 8502015-03-10 Renlin Li <renlin.li@arm.com>
851
852 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
853 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
854 related alias.
855 * aarch64-asm-2.c: Regenerate.
856 * aarch64-dis-2.c: Likewise.
857 * aarch64-opc-2.c: Likewise.
858
d8282f0e
JW		 8592015-03-03 Jiong Wang <jiong.wang@arm.com>
860
861 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
862
ac994365
OE		 8632015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
864
865 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
866 arch_sh_up.
867 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
868 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
869
fd63f640
V		 8702015-02-23 Vinay <Vinay.G@kpit.com>
871
872 * rl78-decode.opc (MOV): Added space between two operands for
873 'mov' instruction in index addressing mode.
874 * rl78-decode.c: Regenerate.
875
f63c1776
PA		 8762015-02-19 Pedro Alves <palves@redhat.com>
877
878 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
879
07774fcc
PA		 8802015-02-10 Pedro Alves <palves@redhat.com>
881 Tom Tromey <tromey@redhat.com>
882
883 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
884 microblaze_and, microblaze_xor.
885 * microblaze-opc.h (opcodes): Adjust.
886
3f8107ab
AM		 8872015-01-28 James Bowman <james.bowman@ftdichip.com>
888
889 * Makefile.am: Add FT32 files.
890 * configure.ac: Handle FT32.
891 * disassemble.c (disassembler): Call print_insn_ft32.
892 * ft32-dis.c: New file.
893 * ft32-opc.c: New file.
894 * Makefile.in: Regenerate.
895 * configure: Regenerate.
896 * po/POTFILES.in: Regenerate.
897
e5fe4957
KLC		 8982015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
899
900 * nds32-asm.c (keyword_sr): Add new system registers.
901
1e2e8c52
AK		 9022015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
903
904 * s390-dis.c (s390_extract_operand): Support vector register
905 operands.
906 (s390_print_insn_with_opcode): Support new operands types and add
907 new handling of optional operands.
908 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
909 and include opcode/s390.h instead.
910 (struct op_struct): New field `flags'.
911 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
912 (dumpTable): Dump flags.
913 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
914 string.
915 * s390-opc.c: Add new operands types, instruction formats, and
916 instruction masks.
917 (s390_opformats): Add new formats for .insn.
918 * s390-opc.txt: Add new instructions.
919
b90efa5b 9202015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 921
b90efa5b 922 Update year range in copyright notice of all files.
bffb6004 923
b90efa5b 924For older changes see ChangeLog-2014
252b5132 925\f
b90efa5b 926Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 927
928Copying and distribution of this file, with or without modification,
929are permitted in any medium without royalty provided the copyright
930notice and this notice are preserved.
931
252b5132 932Local Variables:
2f6d2f85
NC		 933mode: change-log
934left-margin: 8
935fill-column: 74
252b5132
RH		 936version-control: never
937End:
GDB Binutils - Deliverables
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