projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bfd_section_* macros
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
fd361982
AM		 12019-09-18 Alan Modra <amodra@gmail.com>
2
3 * arc-ext.c: Update throughout for bfd section macro changes.
4
e0b2a78c
SM		 52019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
6
7 * Makefile.in: Re-generate.
8 * configure: Re-generate.
9
7e9ad3a3
JW		 102019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
11
12 * riscv-opc.c (riscv_opcodes): Change subset field
13 to insn_class field for all instructions.
14 (riscv_insn_types): Likewise.
15
bb695960
PB		 162019-09-16 Phil Blundell <pb@pbcl.net>
17
18 * configure: Regenerated.
19
8063ab7e
MV		 202019-09-10 Miod Vallat <miod@online.fr>
21
22 PR 24982
23 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
24
60391a25
PB		 252019-09-09 Phil Blundell <pb@pbcl.net>
26
27 binutils 2.33 branch created.
28
f44b758d
NC		 292019-09-03 Nick Clifton <nickc@redhat.com>
30
31 PR 24961
32 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
33 greater than zero before indexing via (bufcnt -1).
34
1e4b5e7d
NC		 352019-09-03 Nick Clifton <nickc@redhat.com>
36
37 PR 24958
38 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
39 (MAX_SPEC_REG_NAME_LEN): Define.
40 (struct mmix_dis_info): Use defined constants for array lengths.
41 (get_reg_name): New function.
42 (get_sprec_reg_name): New function.
43 (print_insn_mmix): Use new functions.
44
c4a23bf8
SP		 452019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
46
47 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
48 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
49 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
50
a051e2f3
KT		 512019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
52
53 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
54 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
55 (aarch64_sys_reg_supported_p): Update checks for the above.
56
08132bdd
SP		 572019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
58
59 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
60 cases MVE_SQRSHRL and MVE_UQRSHLL.
61 (print_insn_mve): Add case for specifier 'k' to check
62 specific bit of the instruction.
63
d88bdcb4
PA		 642019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
65
66 PR 24854
67 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
68 encountering an unknown machine type.
69 (print_insn_arc): Handle arc_insn_length returning 0. In error
70 cases return -1 rather than calling abort.
71
bc750500
JB		 722019-08-07 Jan Beulich <jbeulich@suse.com>
73
74 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
75 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
76 IgnoreSize.
77 * i386-tbl.h: Re-generate.
78
23d188c7
BW		 792019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
80
81 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
82 instructions.
83
c0d6f62f
JW		 842019-07-30 Mel Chen <mel.chen@sifive.com>
85
86 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
87 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
88
89 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
90 fscsr.
91
0f3f7167
CZ		 922019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
93
94 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
95 and MPY class instructions.
96 (parse_option): Add nps400 option.
97 (print_arc_disassembler_options): Add nps400 info.
98
7e126ba3
CZ		 992019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
100
101 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
102 (bspop): Likewise.
103 (modapp): Likewise.
104 * arc-opc.c (RAD_CHK): Add.
105 * arc-tbl.h: Regenerate.
106
a028026d
KT		 1072019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
108
109 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
110 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
111
ac79ff9e
NC		 1122019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
113
114 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
115 instructions as UNPREDICTABLE.
116
231097b0
JM		 1172019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
118
119 * bpf-desc.c: Regenerated.
120
1d942ae9
JB		 1212019-07-17 Jan Beulich <jbeulich@suse.com>
122
123 * i386-gen.c (static_assert): Define.
124 (main): Use it.
125 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
126 (Opcode_Modifier_Num): ... this.
127 (Mem): Delete.
128
dfd69174
JB		 1292019-07-16 Jan Beulich <jbeulich@suse.com>
130
131 * i386-gen.c (operand_types): Move RegMem ...
132 (opcode_modifiers): ... here.
133 * i386-opc.h (RegMem): Move to opcode modifer enum.
134 (union i386_operand_type): Move regmem field ...
135 (struct i386_opcode_modifier): ... here.
136 * i386-opc.tbl (RegMem): Define.
137 (mov, movq): Move RegMem on segment, control, debug, and test
138 register flavors.
139 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
140 to non-SSE2AVX flavor.
141 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
142 Move RegMem on register only flavors. Drop IgnoreSize from
143 legacy encoding flavors.
144 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
145 flavors.
146 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
147 register only flavors.
148 (vmovd): Move RegMem and drop IgnoreSize on register only
149 flavor. Change opcode and operand order to store form.
150 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
151
21df382b
JB		 1522019-07-16 Jan Beulich <jbeulich@suse.com>
153
154 * i386-gen.c (operand_type_init, operand_types): Replace SReg
155 entries.
156 * i386-opc.h (SReg2, SReg3): Replace by ...
157 (SReg): ... this.
158 (union i386_operand_type): Replace sreg fields.
159 * i386-opc.tbl (mov, ): Use SReg.
160 (push, pop): Likewies. Drop i386 and x86-64 specific segment
161 register flavors.
162 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
163 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
164
3719fd55
JM		 1652019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
166
167 * bpf-desc.c: Regenerate.
168 * bpf-opc.c: Likewise.
169 * bpf-opc.h: Likewise.
170
92434a14
JM		 1712019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
172
173 * bpf-desc.c: Regenerate.
174 * bpf-opc.c: Likewise.
175
43dd7626
HPN		 1762019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
177
178 * arm-dis.c (print_insn_coprocessor): Rename index to
179 index_operand.
180
98602811
JW		 1812019-07-05 Kito Cheng <kito.cheng@sifive.com>
182
183 * riscv-opc.c (riscv_insn_types): Add r4 type.
184
185 * riscv-opc.c (riscv_insn_types): Add b and j type.
186
187 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
188 format for sb type and correct s type.
189
01c1ee4a
RS		 1902019-07-02 Richard Sandiford <richard.sandiford@arm.com>
191
192 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
193 SVE FMOV alias of FCPY.
194
83adff69
RS		 1952019-07-02 Richard Sandiford <richard.sandiford@arm.com>
196
197 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
198 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
199
89418844
RS		 2002019-07-02 Richard Sandiford <richard.sandiford@arm.com>
201
202 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
203 registers in an instruction prefixed by MOVPRFX.
204
41be57ca
MM		 2052019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
206
207 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
208 sve_size_13 icode to account for variant behaviour of
209 pmull{t,b}.
210 * aarch64-dis-2.c: Regenerate.
211 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
212 sve_size_13 icode to account for variant behaviour of
213 pmull{t,b}.
214 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
215 (OP_SVE_VVV_Q_D): Add new qualifier.
216 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
217 (struct aarch64_opcode): Split pmull{t,b} into those requiring
218 AES and those not.
219
9d3bf266
JB		 2202019-07-01 Jan Beulich <jbeulich@suse.com>
221
222 * opcodes/i386-gen.c (operand_type_init): Remove
223 OPERAND_TYPE_VEC_IMM4 entry.
224 (operand_types): Remove Vec_Imm4.
225 * opcodes/i386-opc.h (Vec_Imm4): Delete.
226 (union i386_operand_type): Remove vec_imm4.
227 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
228 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
229
c3949f43
JB		 2302019-07-01 Jan Beulich <jbeulich@suse.com>
231
232 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
233 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
234 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
235 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
236 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
237 monitorx, mwaitx): Drop ImmExt from operand-less forms.
238 * i386-tbl.h: Re-generate.
239
5641ec01
JB		 2402019-07-01 Jan Beulich <jbeulich@suse.com>
241
242 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
243 register operands.
244 * i386-tbl.h: Re-generate.
245
79dec6b7
JB		 2462019-07-01 Jan Beulich <jbeulich@suse.com>
247
248 * i386-opc.tbl (C): New.
249 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
250 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
251 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
252 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
253 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
254 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
255 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
256 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
257 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
258 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
259 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
260 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
261 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
262 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
263 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
264 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
265 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
266 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
267 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
268 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
269 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
270 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
271 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
272 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
273 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
274 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
275 flavors.
276 * i386-tbl.h: Re-generate.
277
a0a1771e
JB		 2782019-07-01 Jan Beulich <jbeulich@suse.com>
279
280 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
281 register operands.
282 * i386-tbl.h: Re-generate.
283
cd546e7b
JB		 2842019-07-01 Jan Beulich <jbeulich@suse.com>
285
286 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
287 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
288 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
289 * i386-tbl.h: Re-generate.
290
e3bba3fc
JB		 2912019-07-01 Jan Beulich <jbeulich@suse.com>
292
293 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
294 Disp8MemShift from register only templates.
295 * i386-tbl.h: Re-generate.
296
36cc073e
JB		 2972019-07-01 Jan Beulich <jbeulich@suse.com>
298
299 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
300 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
301 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
302 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
303 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
304 EVEX_W_0F11_P_3_M_1): Delete.
305 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
306 EVEX_W_0F11_P_3): New.
307 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
308 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
309 MOD_EVEX_0F11_PREFIX_3 table entries.
310 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
311 PREFIX_EVEX_0F11 table entries.
312 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
313 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
314 EVEX_W_0F11_P_3_M_{0,1} table entries.
315
219920a7
JB		 3162019-07-01 Jan Beulich <jbeulich@suse.com>
317
318 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
319 Delete.
320
e395f487
L		 3212019-06-27 H.J. Lu <hongjiu.lu@intel.com>
322
323 PR binutils/24719
324 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
325 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
326 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
327 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
328 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
329 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
330 EVEX_LEN_0F38C7_R_6_P_2_W_1.
331 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
332 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
333 PREFIX_EVEX_0F38C6_REG_6 entries.
334 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
335 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
336 EVEX_W_0F38C7_R_6_P_2 entries.
337 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
338 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
339 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
340 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
341 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
342 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
343 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
344
2b7bcc87
JB		 3452019-06-27 Jan Beulich <jbeulich@suse.com>
346
347 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
348 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
349 VEX_LEN_0F2D_P_3): Delete.
350 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
351 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
352 (prefix_table): ... here.
353
c1dc7af5
JB		 3542019-06-27 Jan Beulich <jbeulich@suse.com>
355
356 * i386-dis.c (Iq): Delete.
357 (Id): New.
358 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
359 TBM insns.
360 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
361 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
362 (OP_E_memory): Also honor needindex when deciding whether an
363 address size prefix needs printing.
364 (OP_I): Remove handling of q_mode. Add handling of d_mode.
365
d7560e2d
JW		 3662019-06-26 Jim Wilson <jimw@sifive.com>
367
368 PR binutils/24739
369 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
370 Set info->display_endian to info->endian_code.
371
2c703856
JB		 3722019-06-25 Jan Beulich <jbeulich@suse.com>
373
374 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
375 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
376 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
377 OPERAND_TYPE_ACC64 entries.
378 * i386-init.h: Re-generate.
379
54fbadc0
JB		 3802019-06-25 Jan Beulich <jbeulich@suse.com>
381
382 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
383 Delete.
384 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
385 of dqa_mode.
386 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
387 entries here.
388 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
389 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
390
a280ab8e
JB		 3912019-06-25 Jan Beulich <jbeulich@suse.com>
392
393 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
394 variables.
395
e1a1babd
JB		 3962019-06-25 Jan Beulich <jbeulich@suse.com>
397
398 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
399 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
400 movnti.
d7560e2d 401 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 402 * i386-tbl.h: Re-generate.
403
b8364fa7
JB		 4042019-06-25 Jan Beulich <jbeulich@suse.com>
405
406 * i386-opc.tbl (and): Mark Imm8S form for optimization.
407 * i386-tbl.h: Re-generate.
408
ad692897
L		 4092019-06-21 H.J. Lu <hongjiu.lu@intel.com>
410
411 * i386-dis-evex.h: Break into ...
412 * i386-dis-evex-len.h: New file.
413 * i386-dis-evex-mod.h: Likewise.
414 * i386-dis-evex-prefix.h: Likewise.
415 * i386-dis-evex-reg.h: Likewise.
416 * i386-dis-evex-w.h: Likewise.
417 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
418 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
419 i386-dis-evex-mod.h.
420
f0a6222e
L		 4212019-06-19 H.J. Lu <hongjiu.lu@intel.com>
422
423 PR binutils/24700
424 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
425 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
426 EVEX_W_0F385B_P_2.
427 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
428 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
429 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
430 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
431 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
432 EVEX_LEN_0F385B_P_2_W_1.
433 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
434 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
435 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
436 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
437 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
438 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
439 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
440 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
441 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
442 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
443
6e1c90b7
L		 4442019-06-17 H.J. Lu <hongjiu.lu@intel.com>
445
446 PR binutils/24691
447 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
448 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
449 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
450 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
451 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
452 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
453 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
454 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
455 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
456 EVEX_LEN_0F3A43_P_2_W_1.
457 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
458 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
459 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
460 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
461 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
462 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
463 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
464 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
465 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
466 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
467 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
468 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
469
bcc5a6eb
NC		 4702019-06-14 Nick Clifton <nickc@redhat.com>
471
472 * po/fr.po; Updated French translation.
473
e4c4ac46
SH		 4742019-06-13 Stafford Horne <shorne@gmail.com>
475
476 * or1k-asm.c: Regenerated.
477 * or1k-desc.c: Regenerated.
478 * or1k-desc.h: Regenerated.
479 * or1k-dis.c: Regenerated.
480 * or1k-ibld.c: Regenerated.
481 * or1k-opc.c: Regenerated.
482 * or1k-opc.h: Regenerated.
483 * or1k-opinst.c: Regenerated.
484
a0e44ef5
PB		 4852019-06-12 Peter Bergner <bergner@linux.ibm.com>
486
487 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
488
12efd68d
L		 4892019-06-05 H.J. Lu <hongjiu.lu@intel.com>
490
491 PR binutils/24633
492 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
493 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
494 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
495 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
496 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
497 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
498 EVEX_LEN_0F3A1B_P_2_W_1.
499 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
500 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
501 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
502 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
503 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
504 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
505 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
506 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
507
63c6fc6c
L		 5082019-06-04 H.J. Lu <hongjiu.lu@intel.com>
509
510 PR binutils/24626
511 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
512 EVEX.vvvv when disassembling VEX and EVEX instructions.
513 (OP_VEX): Set vex.register_specifier to 0 after readding
514 vex.register_specifier.
515 (OP_Vex_2src_1): Likewise.
516 (OP_Vex_2src_2): Likewise.
517 (OP_LWP_E): Likewise.
518 (OP_EX_Vex): Don't check vex.register_specifier.
519 (OP_XMM_Vex): Likewise.
520
9186c494
L		 5212019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
522 Lili Cui <lili.cui@intel.com>
523
524 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
525 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
526 instructions.
527 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
528 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
529 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
530 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
531 (i386_cpu_flags): Add cpuavx512_vp2intersect.
532 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
533 * i386-init.h: Regenerated.
534 * i386-tbl.h: Likewise.
535
5d79adc4
L		 5362019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
537 Lili Cui <lili.cui@intel.com>
538
539 * doc/c-i386.texi: Document enqcmd.
540 * testsuite/gas/i386/enqcmd-intel.d: New file.
541 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
542 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
543 * testsuite/gas/i386/enqcmd.d: Likewise.
544 * testsuite/gas/i386/enqcmd.s: Likewise.
545 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
546 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
547 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
548 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
549 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
550 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
551 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
552 and x86-64-enqcmd.
553
a9d96ab9
AH		 5542019-06-04 Alan Hayward <alan.hayward@arm.com>
555
556 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
557
4f6d070a
AM		 5582019-06-03 Alan Modra <amodra@gmail.com>
559
560 * ppc-dis.c (prefix_opcd_indices): Correct size.
561
a2f4b66c
L		 5622019-05-28 H.J. Lu <hongjiu.lu@intel.com>
563
564 PR gas/24625
565 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
566 Disp8ShiftVL.
567 * i386-tbl.h: Regenerated.
568
405b5bd8
AM		 5692019-05-24 Alan Modra <amodra@gmail.com>
570
571 * po/POTFILES.in: Regenerate.
572
8acf1435
PB		 5732019-05-24 Peter Bergner <bergner@linux.ibm.com>
574 Alan Modra <amodra@gmail.com>
575
576 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
577 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
578 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
579 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
580 XTOP>): Define and add entries.
581 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
582 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
583 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
584 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
585
dd7efa79
PB		 5862019-05-24 Peter Bergner <bergner@linux.ibm.com>
587 Alan Modra <amodra@gmail.com>
588
589 * ppc-dis.c (ppc_opts): Add "future" entry.
590 (PREFIX_OPCD_SEGS): Define.
591 (prefix_opcd_indices): New array.
592 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
593 (lookup_prefix): New function.
594 (print_insn_powerpc): Handle 64-bit prefix instructions.
595 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
596 (PMRR, POWERXX): Define.
597 (prefix_opcodes): New instruction table.
598 (prefix_num_opcodes): New constant.
599
79472b45
JM		 6002019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
601
602 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
603 * configure: Regenerated.
604 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
605 and cpu/bpf.opc.
606 (HFILES): Add bpf-desc.h and bpf-opc.h.
607 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
608 bpf-ibld.c and bpf-opc.c.
609 (BPF_DEPS): Define.
610 * Makefile.in: Regenerated.
611 * disassemble.c (ARCH_bpf): Define.
612 (disassembler): Add case for bfd_arch_bpf.
613 (disassemble_init_for_target): Likewise.
614 (enum epbf_isa_attr): Define.
615 * disassemble.h: extern print_insn_bpf.
616 * bpf-asm.c: Generated.
617 * bpf-opc.h: Likewise.
618 * bpf-opc.c: Likewise.
619 * bpf-ibld.c: Likewise.
620 * bpf-dis.c: Likewise.
621 * bpf-desc.h: Likewise.
622 * bpf-desc.c: Likewise.
623
ba6cd17f
SD		 6242019-05-21 Sudakshina Das <sudi.das@arm.com>
625
626 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
627 and VMSR with the new operands.
628
e39c1607
SD		 6292019-05-21 Sudakshina Das <sudi.das@arm.com>
630
631 * arm-dis.c (enum mve_instructions): New enum
632 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
633 and cneg.
634 (mve_opcodes): New instructions as above.
635 (is_mve_encoding_conflict): Add cases for csinc, csinv,
636 csneg and csel.
637 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
638
23d00a41
SD		 6392019-05-21 Sudakshina Das <sudi.das@arm.com>
640
641 * arm-dis.c (emun mve_instructions): Updated for new instructions.
642 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
643 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
644 uqshl, urshrl and urshr.
645 (is_mve_okay_in_it): Add new instructions to TRUE list.
646 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
647 (print_insn_mve): Updated to accept new %j,
648 %<bitfield>m and %<bitfield>n patterns.
649
cd4797ee
FS		 6502019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
651
652 * mips-opc.c (mips_builtin_opcodes): Change source register
653 constraint for DAUI.
654
999b073b
NC		 6552019-05-20 Nick Clifton <nickc@redhat.com>
656
657 * po/fr.po: Updated French translation.
658
14b456f2
AV		 6592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
660 Michael Collison <michael.collison@arm.com>
661
662 * arm-dis.c (thumb32_opcodes): Add new instructions.
663 (enum mve_instructions): Likewise.
664 (enum mve_undefined): Add new reasons.
665 (is_mve_encoding_conflict): Handle new instructions.
666 (is_mve_undefined): Likewise.
667 (is_mve_unpredictable): Likewise.
668 (print_mve_undefined): Likewise.
669 (print_mve_size): Likewise.
670
f49bb598
AV		 6712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
672 Michael Collison <michael.collison@arm.com>
673
674 * arm-dis.c (thumb32_opcodes): Add new instructions.
675 (enum mve_instructions): Likewise.
676 (is_mve_encoding_conflict): Handle new instructions.
677 (is_mve_undefined): Likewise.
678 (is_mve_unpredictable): Likewise.
679 (print_mve_size): Likewise.
680
56858bea
AV		 6812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
682 Michael Collison <michael.collison@arm.com>
683
684 * arm-dis.c (thumb32_opcodes): Add new instructions.
685 (enum mve_instructions): Likewise.
686 (is_mve_encoding_conflict): Likewise.
687 (is_mve_unpredictable): Likewise.
688 (print_mve_size): Likewise.
689
e523f101
AV		 6902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
691 Michael Collison <michael.collison@arm.com>
692
693 * arm-dis.c (thumb32_opcodes): Add new instructions.
694 (enum mve_instructions): Likewise.
695 (is_mve_encoding_conflict): Handle new instructions.
696 (is_mve_undefined): Likewise.
697 (is_mve_unpredictable): Likewise.
698 (print_mve_size): Likewise.
699
66dcaa5d
AV		 7002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
701 Michael Collison <michael.collison@arm.com>
702
703 * arm-dis.c (thumb32_opcodes): Add new instructions.
704 (enum mve_instructions): Likewise.
705 (is_mve_encoding_conflict): Handle new instructions.
706 (is_mve_undefined): Likewise.
707 (is_mve_unpredictable): Likewise.
708 (print_mve_size): Likewise.
709 (print_insn_mve): Likewise.
710
d052b9b7
AV		 7112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
712 Michael Collison <michael.collison@arm.com>
713
714 * arm-dis.c (thumb32_opcodes): Add new instructions.
715 (print_insn_thumb32): Handle new instructions.
716
ed63aa17
AV		 7172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
718 Michael Collison <michael.collison@arm.com>
719
720 * arm-dis.c (enum mve_instructions): Add new instructions.
721 (enum mve_undefined): Add new reasons.
722 (is_mve_encoding_conflict): Handle new instructions.
723 (is_mve_undefined): Likewise.
724 (is_mve_unpredictable): Likewise.
725 (print_mve_undefined): Likewise.
726 (print_mve_size): Likewise.
727 (print_mve_shift_n): Likewise.
728 (print_insn_mve): Likewise.
729
897b9bbc
AV		 7302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
731 Michael Collison <michael.collison@arm.com>
732
733 * arm-dis.c (enum mve_instructions): Add new instructions.
734 (is_mve_encoding_conflict): Handle new instructions.
735 (is_mve_unpredictable): Likewise.
736 (print_mve_rotate): Likewise.
737 (print_mve_size): Likewise.
738 (print_insn_mve): Likewise.
739
1c8f2df8
AV		 7402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
741 Michael Collison <michael.collison@arm.com>
742
743 * arm-dis.c (enum mve_instructions): Add new instructions.
744 (is_mve_encoding_conflict): Handle new instructions.
745 (is_mve_unpredictable): Likewise.
746 (print_mve_size): Likewise.
747 (print_insn_mve): Likewise.
748
d3b63143
AV		 7492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
750 Michael Collison <michael.collison@arm.com>
751
752 * arm-dis.c (enum mve_instructions): Add new instructions.
753 (enum mve_undefined): Add new reasons.
754 (is_mve_encoding_conflict): Handle new instructions.
755 (is_mve_undefined): Likewise.
756 (is_mve_unpredictable): Likewise.
757 (print_mve_undefined): Likewise.
758 (print_mve_size): Likewise.
759 (print_insn_mve): Likewise.
760
14925797
AV		 7612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
762 Michael Collison <michael.collison@arm.com>
763
764 * arm-dis.c (enum mve_instructions): Add new instructions.
765 (is_mve_encoding_conflict): Handle new instructions.
766 (is_mve_undefined): Likewise.
767 (is_mve_unpredictable): Likewise.
768 (print_mve_size): Likewise.
769 (print_insn_mve): Likewise.
770
c507f10b
AV		 7712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
772 Michael Collison <michael.collison@arm.com>
773
774 * arm-dis.c (enum mve_instructions): Add new instructions.
775 (enum mve_unpredictable): Add new reasons.
776 (enum mve_undefined): Likewise.
777 (is_mve_okay_in_it): Handle new isntructions.
778 (is_mve_encoding_conflict): Likewise.
779 (is_mve_undefined): Likewise.
780 (is_mve_unpredictable): Likewise.
781 (print_mve_vmov_index): Likewise.
782 (print_simd_imm8): Likewise.
783 (print_mve_undefined): Likewise.
784 (print_mve_unpredictable): Likewise.
785 (print_mve_size): Likewise.
786 (print_insn_mve): Likewise.
787
bf0b396d
AV		 7882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
789 Michael Collison <michael.collison@arm.com>
790
791 * arm-dis.c (enum mve_instructions): Add new instructions.
792 (enum mve_unpredictable): Add new reasons.
793 (enum mve_undefined): Likewise.
794 (is_mve_encoding_conflict): Handle new instructions.
795 (is_mve_undefined): Likewise.
796 (is_mve_unpredictable): Likewise.
797 (print_mve_undefined): Likewise.
798 (print_mve_unpredictable): Likewise.
799 (print_mve_rounding_mode): Likewise.
800 (print_mve_vcvt_size): Likewise.
801 (print_mve_size): Likewise.
802 (print_insn_mve): Likewise.
803
ef1576a1
AV		 8042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
805 Michael Collison <michael.collison@arm.com>
806
807 * arm-dis.c (enum mve_instructions): Add new instructions.
808 (enum mve_unpredictable): Add new reasons.
809 (enum mve_undefined): Likewise.
810 (is_mve_undefined): Handle new instructions.
811 (is_mve_unpredictable): Likewise.
812 (print_mve_undefined): Likewise.
813 (print_mve_unpredictable): Likewise.
814 (print_mve_size): Likewise.
815 (print_insn_mve): Likewise.
816
aef6d006
AV		 8172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
818 Michael Collison <michael.collison@arm.com>
819
820 * arm-dis.c (enum mve_instructions): Add new instructions.
821 (enum mve_undefined): Add new reasons.
822 (insns): Add new instructions.
823 (is_mve_encoding_conflict):
824 (print_mve_vld_str_addr): New print function.
825 (is_mve_undefined): Handle new instructions.
826 (is_mve_unpredictable): Likewise.
827 (print_mve_undefined): Likewise.
828 (print_mve_size): Likewise.
829 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
830 (print_insn_mve): Handle new operands.
831
04d54ace
AV		 8322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
833 Michael Collison <michael.collison@arm.com>
834
835 * arm-dis.c (enum mve_instructions): Add new instructions.
836 (enum mve_unpredictable): Add new reasons.
837 (is_mve_encoding_conflict): Handle new instructions.
838 (is_mve_unpredictable): Likewise.
839 (mve_opcodes): Add new instructions.
840 (print_mve_unpredictable): Handle new reasons.
841 (print_mve_register_blocks): New print function.
842 (print_mve_size): Handle new instructions.
843 (print_insn_mve): Likewise.
844
9743db03
AV		 8452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
846 Michael Collison <michael.collison@arm.com>
847
848 * arm-dis.c (enum mve_instructions): Add new instructions.
849 (enum mve_unpredictable): Add new reasons.
850 (enum mve_undefined): Likewise.
851 (is_mve_encoding_conflict): Handle new instructions.
852 (is_mve_undefined): Likewise.
853 (is_mve_unpredictable): Likewise.
854 (coprocessor_opcodes): Move NEON VDUP from here...
855 (neon_opcodes): ... to here.
856 (mve_opcodes): Add new instructions.
857 (print_mve_undefined): Handle new reasons.
858 (print_mve_unpredictable): Likewise.
859 (print_mve_size): Handle new instructions.
860 (print_insn_neon): Handle vdup.
861 (print_insn_mve): Handle new operands.
862
143275ea
AV		 8632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
864 Michael Collison <michael.collison@arm.com>
865
866 * arm-dis.c (enum mve_instructions): Add new instructions.
867 (enum mve_unpredictable): Add new values.
868 (mve_opcodes): Add new instructions.
869 (vec_condnames): New array with vector conditions.
870 (mve_predicatenames): New array with predicate suffixes.
871 (mve_vec_sizename): New array with vector sizes.
872 (enum vpt_pred_state): New enum with vector predication states.
873 (struct vpt_block): New struct type for vpt blocks.
874 (vpt_block_state): Global struct to keep track of state.
875 (mve_extract_pred_mask): New helper function.
876 (num_instructions_vpt_block): Likewise.
877 (mark_outside_vpt_block): Likewise.
878 (mark_inside_vpt_block): Likewise.
879 (invert_next_predicate_state): Likewise.
880 (update_next_predicate_state): Likewise.
881 (update_vpt_block_state): Likewise.
882 (is_vpt_instruction): Likewise.
883 (is_mve_encoding_conflict): Add entries for new instructions.
884 (is_mve_unpredictable): Likewise.
885 (print_mve_unpredictable): Handle new cases.
886 (print_instruction_predicate): Likewise.
887 (print_mve_size): New function.
888 (print_vec_condition): New function.
889 (print_insn_mve): Handle vpt blocks and new print operands.
890
f08d8ce3
AV		 8912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
892
893 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
894 8, 14 and 15 for Armv8.1-M Mainline.
895
73cd51e5
AV		 8962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
897 Michael Collison <michael.collison@arm.com>
898
899 * arm-dis.c (enum mve_instructions): New enum.
900 (enum mve_unpredictable): Likewise.
901 (enum mve_undefined): Likewise.
902 (struct mopcode32): New struct.
903 (is_mve_okay_in_it): New function.
904 (is_mve_architecture): Likewise.
905 (arm_decode_field): Likewise.
906 (arm_decode_field_multiple): Likewise.
907 (is_mve_encoding_conflict): Likewise.
908 (is_mve_undefined): Likewise.
909 (is_mve_unpredictable): Likewise.
910 (print_mve_undefined): Likewise.
911 (print_mve_unpredictable): Likewise.
912 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
913 (print_insn_mve): New function.
914 (print_insn_thumb32): Handle MVE architecture.
915 (select_arm_features): Force thumb for Armv8.1-m Mainline.
916
3076e594
NC		 9172019-05-10 Nick Clifton <nickc@redhat.com>
918
919 PR 24538
920 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
921 end of the table prematurely.
922
387e7624
FS		 9232019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
924
925 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
926 macros for R6.
927
0067be51
AM		 9282019-05-11 Alan Modra <amodra@gmail.com>
929
930 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
931 when -Mraw is in effect.
932
42e6288f
MM		 9332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
934
935 * aarch64-dis-2.c: Regenerate.
936 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
937 (OP_SVE_BBB): New variant set.
938 (OP_SVE_DDDD): New variant set.
939 (OP_SVE_HHH): New variant set.
940 (OP_SVE_HHHU): New variant set.
941 (OP_SVE_SSS): New variant set.
942 (OP_SVE_SSSU): New variant set.
943 (OP_SVE_SHH): New variant set.
944 (OP_SVE_SBBU): New variant set.
945 (OP_SVE_DSS): New variant set.
946 (OP_SVE_DHHU): New variant set.
947 (OP_SVE_VMV_HSD_BHS): New variant set.
948 (OP_SVE_VVU_HSD_BHS): New variant set.
949 (OP_SVE_VVVU_SD_BH): New variant set.
950 (OP_SVE_VVVU_BHSD): New variant set.
951 (OP_SVE_VVV_QHD_DBS): New variant set.
952 (OP_SVE_VVV_HSD_BHS): New variant set.
953 (OP_SVE_VVV_HSD_BHS2): New variant set.
954 (OP_SVE_VVV_BHS_HSD): New variant set.
955 (OP_SVE_VV_BHS_HSD): New variant set.
956 (OP_SVE_VVV_SD): New variant set.
957 (OP_SVE_VVU_BHS_HSD): New variant set.
958 (OP_SVE_VZVV_SD): New variant set.
959 (OP_SVE_VZVV_BH): New variant set.
960 (OP_SVE_VZV_SD): New variant set.
961 (aarch64_opcode_table): Add sve2 instructions.
962
28ed815a
MM		 9632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
964
965 * aarch64-asm-2.c: Regenerated.
966 * aarch64-dis-2.c: Regenerated.
967 * aarch64-opc-2.c: Regenerated.
968 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
969 for SVE_SHLIMM_UNPRED_22.
970 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
971 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
972 operand.
973
fd1dc4a0
MM		 9742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975
976 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
977 sve_size_tsz_bhs iclass encode.
978 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
979 sve_size_tsz_bhs iclass decode.
980
31e36ab3
MM		 9812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
982
983 * aarch64-asm-2.c: Regenerated.
984 * aarch64-dis-2.c: Regenerated.
985 * aarch64-opc-2.c: Regenerated.
986 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
987 for SVE_Zm4_11_INDEX.
988 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
989 (fields): Handle SVE_i2h field.
990 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
991 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
992
1be5f94f
MM		 9932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
994
995 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
996 sve_shift_tsz_bhsd iclass encode.
997 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
998 sve_shift_tsz_bhsd iclass decode.
999
3c17238b
MM		 10002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1001
1002 * aarch64-asm-2.c: Regenerated.
1003 * aarch64-dis-2.c: Regenerated.
1004 * aarch64-opc-2.c: Regenerated.
1005 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1006 (aarch64_encode_variant_using_iclass): Handle
1007 sve_shift_tsz_hsd iclass encode.
1008 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1009 sve_shift_tsz_hsd iclass decode.
1010 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1011 for SVE_SHRIMM_UNPRED_22.
1012 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1013 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1014 operand.
1015
cd50a87a
MM		 10162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1017
1018 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1019 sve_size_013 iclass encode.
1020 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1021 sve_size_013 iclass decode.
1022
3c705960
MM		 10232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1024
1025 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1026 sve_size_bh iclass encode.
1027 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1028 sve_size_bh iclass decode.
1029
0a57e14f
MM		 10302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1031
1032 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1033 sve_size_sd2 iclass encode.
1034 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1035 sve_size_sd2 iclass decode.
1036 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1037 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1038
c469c864
MM		 10392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1040
1041 * aarch64-asm-2.c: Regenerated.
1042 * aarch64-dis-2.c: Regenerated.
1043 * aarch64-opc-2.c: Regenerated.
1044 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1045 for SVE_ADDR_ZX.
1046 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1047 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1048
116adc27
MM		 10492019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1050
1051 * aarch64-asm-2.c: Regenerated.
1052 * aarch64-dis-2.c: Regenerated.
1053 * aarch64-opc-2.c: Regenerated.
1054 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1055 for SVE_Zm3_11_INDEX.
1056 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1057 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1058 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1059 fields.
1060 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1061
3bd82c86
MM		 10622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1063
1064 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1065 sve_size_hsd2 iclass encode.
1066 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1067 sve_size_hsd2 iclass decode.
1068 * aarch64-opc.c (fields): Handle SVE_size field.
1069 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1070
adccc507
MM		 10712019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1072
1073 * aarch64-asm-2.c: Regenerated.
1074 * aarch64-dis-2.c: Regenerated.
1075 * aarch64-opc-2.c: Regenerated.
1076 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1077 for SVE_IMM_ROT3.
1078 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1079 (fields): Handle SVE_rot3 field.
1080 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1081 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1082
5cd99750
MM		 10832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1084
1085 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1086 instructions.
1087
7ce2460a
MM		 10882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1089
1090 * aarch64-tbl.h
1091 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1092 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1093 aarch64_feature_sve2bitperm): New feature sets.
1094 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1095 for feature set addresses.
1096 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1097 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1098
41cee089
FS		 10992019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1100 Faraz Shahbazker <fshahbazker@wavecomp.com>
1101
1102 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1103 argument and set ASE_EVA_R6 appropriately.
1104 (set_default_mips_dis_options): Pass ISA to above.
1105 (parse_mips_dis_option): Likewise.
1106 * mips-opc.c (EVAR6): New macro.
1107 (mips_builtin_opcodes): Add llwpe, scwpe.
1108
b83b4b13
SD		 11092019-05-01 Sudakshina Das <sudi.das@arm.com>
1110
1111 * aarch64-asm-2.c: Regenerated.
1112 * aarch64-dis-2.c: Regenerated.
1113 * aarch64-opc-2.c: Regenerated.
1114 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1115 AARCH64_OPND_TME_UIMM16.
1116 (aarch64_print_operand): Likewise.
1117 * aarch64-tbl.h (QL_IMM_NIL): New.
1118 (TME): New.
1119 (_TME_INSN): New.
1120 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1121
4a90ce95
JD		 11222019-04-29 John Darrington <john@darrington.wattle.id.au>
1123
1124 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1125
a45328b9
AB		 11262019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1127 Faraz Shahbazker <fshahbazker@wavecomp.com>
1128
1129 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1130
d10be0cb
JD		 11312019-04-24 John Darrington <john@darrington.wattle.id.au>
1132
1133 * s12z-opc.h: Add extern "C" bracketing to help
1134 users who wish to use this interface in c++ code.
1135
a679f24e
JD		 11362019-04-24 John Darrington <john@darrington.wattle.id.au>
1137
1138 * s12z-opc.c (bm_decode): Handle bit map operations with the
1139 "reserved0" mode.
1140
32c36c3c
AV		 11412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1142
1143 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1144 specifier. Add entries for VLDR and VSTR of system registers.
1145 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1146 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1147 of %J and %K format specifier.
1148
efd6b359
AV		 11492019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1150
1151 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1152 Add new entries for VSCCLRM instruction.
1153 (print_insn_coprocessor): Handle new %C format control code.
1154
6b0dd094
AV		 11552019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1156
1157 * arm-dis.c (enum isa): New enum.
1158 (struct sopcode32): New structure.
1159 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1160 set isa field of all current entries to ANY.
1161 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1162 Only match an entry if its isa field allows the current mode.
1163
4b5a202f
AV		 11642019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1165
1166 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1167 CLRM.
1168 (print_insn_thumb32): Add logic to print %n CLRM register list.
1169
60f993ce
AV		 11702019-04-15 Sudakshina Das <sudi.das@arm.com>
1171
1172 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1173 and %Q patterns.
1174
f6b2b12d
AV		 11752019-04-15 Sudakshina Das <sudi.das@arm.com>
1176
1177 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1178 (print_insn_thumb32): Edit the switch case for %Z.
1179
1889da70
AV		 11802019-04-15 Sudakshina Das <sudi.das@arm.com>
1181
1182 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1183
65d1bc05
AV		 11842019-04-15 Sudakshina Das <sudi.das@arm.com>
1185
1186 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1187
1caf72a5
AV		 11882019-04-15 Sudakshina Das <sudi.das@arm.com>
1189
1190 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1191
f1c7f421
AV		 11922019-04-15 Sudakshina Das <sudi.das@arm.com>
1193
1194 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1195 Arm register with r13 and r15 unpredictable.
1196 (thumb32_opcodes): New instructions for bfx and bflx.
1197
4389b29a
AV		 11982019-04-15 Sudakshina Das <sudi.das@arm.com>
1199
1200 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1201
e5d6e09e
AV		 12022019-04-15 Sudakshina Das <sudi.das@arm.com>
1203
1204 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1205
e12437dc
AV		 12062019-04-15 Sudakshina Das <sudi.das@arm.com>
1207
1208 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1209
031254f2
AV		 12102019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1211
1212 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1213
e5a557ac
JD		 12142019-04-12 John Darrington <john@darrington.wattle.id.au>
1215
1216 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1217 "optr". ("operator" is a reserved word in c++).
1218
bd7ceb8d
SD		 12192019-04-11 Sudakshina Das <sudi.das@arm.com>
1220
1221 * aarch64-opc.c (aarch64_print_operand): Add case for
1222 AARCH64_OPND_Rt_SP.
1223 (verify_constraints): Likewise.
1224 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1225 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1226 to accept Rt|SP as first operand.
1227 (AARCH64_OPERANDS): Add new Rt_SP.
1228 * aarch64-asm-2.c: Regenerated.
1229 * aarch64-dis-2.c: Regenerated.
1230 * aarch64-opc-2.c: Regenerated.
1231
e54010f1
SD		 12322019-04-11 Sudakshina Das <sudi.das@arm.com>
1233
1234 * aarch64-asm-2.c: Regenerated.
1235 * aarch64-dis-2.c: Likewise.
1236 * aarch64-opc-2.c: Likewise.
1237 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1238
7e96e219
RS		 12392019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1240
1241 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1242
6f2791d5
L		 12432019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1244
1245 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1246 * i386-init.h: Regenerated.
1247
e392bad3
AM		 12482019-04-07 Alan Modra <amodra@gmail.com>
1249
1250 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1251 op_separator to control printing of spaces, comma and parens
1252 rather than need_comma, need_paren and spaces vars.
1253
dffaa15c
AM		 12542019-04-07 Alan Modra <amodra@gmail.com>
1255
1256 PR 24421
1257 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1258 (print_insn_neon, print_insn_arm): Likewise.
1259
d6aab7a1
XG		 12602019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1261
1262 * i386-dis-evex.h (evex_table): Updated to support BF16
1263 instructions.
1264 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1265 and EVEX_W_0F3872_P_3.
1266 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1267 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1268 * i386-opc.h (enum): Add CpuAVX512_BF16.
1269 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1270 * i386-opc.tbl: Add AVX512 BF16 instructions.
1271 * i386-init.h: Regenerated.
1272 * i386-tbl.h: Likewise.
1273
66e85460
AM		 12742019-04-05 Alan Modra <amodra@gmail.com>
1275
1276 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1277 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1278 to favour printing of "-" branch hint when using the "y" bit.
1279 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1280
c2b1c275
AM		 12812019-04-05 Alan Modra <amodra@gmail.com>
1282
1283 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1284 opcode until first operand is output.
1285
aae9718e
PB		 12862019-04-04 Peter Bergner <bergner@linux.ibm.com>
1287
1288 PR gas/24349
1289 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1290 (valid_bo_post_v2): Add support for 'at' branch hints.
1291 (insert_bo): Only error on branch on ctr.
1292 (get_bo_hint_mask): New function.
1293 (insert_boe): Add new 'branch_taken' formal argument. Add support
1294 for inserting 'at' branch hints.
1295 (extract_boe): Add new 'branch_taken' formal argument. Add support
1296 for extracting 'at' branch hints.
1297 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1298 (BOE): Delete operand.
1299 (BOM, BOP): New operands.
1300 (RM): Update value.
1301 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1302 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1303 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1304 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1305 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1306 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1307 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1308 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1309 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1310 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1311 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1312 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1313 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1314 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1315 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1316 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1317 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1318 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1319 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1320 bttarl+>: New extended mnemonics.
1321
96a86c01
AM		 13222019-03-28 Alan Modra <amodra@gmail.com>
1323
1324 PR 24390
1325 * ppc-opc.c (BTF): Define.
1326 (powerpc_opcodes): Use for mtfsb*.
1327 * ppc-dis.c (print_insn_powerpc): Print fields with both
1328 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1329
796d6298
TC		 13302019-03-25 Tamar Christina <tamar.christina@arm.com>
1331
1332 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1333 (mapping_symbol_for_insn): Implement new algorithm.
1334 (print_insn): Remove duplicate code.
1335
60df3720
TC		 13362019-03-25 Tamar Christina <tamar.christina@arm.com>
1337
1338 * aarch64-dis.c (print_insn_aarch64):
1339 Implement override.
1340
51457761
TC		 13412019-03-25 Tamar Christina <tamar.christina@arm.com>
1342
1343 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1344 order.
1345
53b2f36b
TC		 13462019-03-25 Tamar Christina <tamar.christina@arm.com>
1347
1348 * aarch64-dis.c (last_stop_offset): New.
1349 (print_insn_aarch64): Use stop_offset.
1350
89199bb5
L		 13512019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1352
1353 PR gas/24359
1354 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1355 CPU_ANY_AVX2_FLAGS.
1356 * i386-init.h: Regenerated.
1357
97ed31ae
L		 13582019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1359
1360 PR gas/24348
1361 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1362 vmovdqu16, vmovdqu32 and vmovdqu64.
1363 * i386-tbl.h: Regenerated.
1364
0919bfe9
AK		 13652019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1366
1367 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1368 from vstrszb, vstrszh, and vstrszf.
1369
13702019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1371
1372 * s390-opc.txt: Add instruction descriptions.
1373
21820ebe
JW		 13742019-02-08 Jim Wilson <jimw@sifive.com>
1375
1376 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1377 <bne>: Likewise.
1378
f7dd2fb2
TC		 13792019-02-07 Tamar Christina <tamar.christina@arm.com>
1380
1381 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1382
6456d318
TC		 13832019-02-07 Tamar Christina <tamar.christina@arm.com>
1384
1385 PR binutils/23212
1386 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1387 * aarch64-opc.c (verify_elem_sd): New.
1388 (fields): Add FLD_sz entr.
1389 * aarch64-tbl.h (_SIMD_INSN): New.
1390 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1391 fmulx scalar and vector by element isns.
1392
4a83b610
NC		 13932019-02-07 Nick Clifton <nickc@redhat.com>
1394
1395 * po/sv.po: Updated Swedish translation.
1396
fc60b8c8
AK		 13972019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1398
1399 * s390-mkopc.c (main): Accept arch13 as cpu string.
1400 * s390-opc.c: Add new instruction formats and instruction opcode
1401 masks.
1402 * s390-opc.txt: Add new arch13 instructions.
1403
e10620d3
TC		 14042019-01-25 Sudakshina Das <sudi.das@arm.com>
1405
1406 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1407 (aarch64_opcode): Change encoding for stg, stzg
1408 st2g and st2zg.
1409 * aarch64-asm-2.c: Regenerated.
1410 * aarch64-dis-2.c: Regenerated.
1411 * aarch64-opc-2.c: Regenerated.
1412
20a4ca55
SD		 14132019-01-25 Sudakshina Das <sudi.das@arm.com>
1414
1415 * aarch64-asm-2.c: Regenerated.
1416 * aarch64-dis-2.c: Likewise.
1417 * aarch64-opc-2.c: Likewise.
1418 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1419
550fd7bf
SD		 14202019-01-25 Sudakshina Das <sudi.das@arm.com>
1421 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1422
1423 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1424 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1425 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1426 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1427 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1428 case for ldstgv_indexed.
1429 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1430 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1431 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1432 * aarch64-asm-2.c: Regenerated.
1433 * aarch64-dis-2.c: Regenerated.
1434 * aarch64-opc-2.c: Regenerated.
1435
d9938630
NC		 14362019-01-23 Nick Clifton <nickc@redhat.com>
1437
1438 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1439
375cd423
NC		 14402019-01-21 Nick Clifton <nickc@redhat.com>
1441
1442 * po/de.po: Updated German translation.
1443 * po/uk.po: Updated Ukranian translation.
1444
57299f48
CX		 14452019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1446 * mips-dis.c (mips_arch_choices): Fix typo in
1447 gs464, gs464e and gs264e descriptors.
1448
f48dfe41
NC		 14492019-01-19 Nick Clifton <nickc@redhat.com>
1450
1451 * configure: Regenerate.
1452 * po/opcodes.pot: Regenerate.
1453
f974f26c
NC		 14542018-06-24 Nick Clifton <nickc@redhat.com>
1455
1456 2.32 branch created.
1457
39f286cd
JD		 14582019-01-09 John Darrington <john@darrington.wattle.id.au>
1459
448b8ca8
JD		 1460 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1461 if it is null.
1462 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1463 zero.
1464
3107326d
AP		 14652019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1466
1467 * configure: Regenerate.
1468
7e9ca91e
AM		 14692019-01-07 Alan Modra <amodra@gmail.com>
1470
1471 * configure: Regenerate.
1472 * po/POTFILES.in: Regenerate.
1473
ef1ad42b
JD		 14742019-01-03 John Darrington <john@darrington.wattle.id.au>
1475
1476 * s12z-opc.c: New file.
1477 * s12z-opc.h: New file.
1478 * s12z-dis.c: Removed all code not directly related to display
1479 of instructions. Used the interface provided by the new files
1480 instead.
1481 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1482 * Makefile.in: Regenerate.
ef1ad42b 1483 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1484 * configure: Regenerate.
ef1ad42b 1485
82704155
AM		 14862019-01-01 Alan Modra <amodra@gmail.com>
1487
1488 Update year range in copyright notice of all files.
1489
d5c04e1b 1490For older changes see ChangeLog-2018
3499769a 1491\f
d5c04e1b 1492Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1493
1494Copying and distribution of this file, with or without modification,
1495are permitted in any medium without royalty provided the copyright
1496notice and this notice are preserved.
1497
1498Local Variables:
1499mode: change-log
1500left-margin: 8
1501fill-column: 74
1502version-control: never
1503End:
GDB Binutils - Deliverables
This page took 0.432279 seconds and 4 git commands to generate.