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CommitLineData
d203b41a 12018-08-20 Alan Modra <amodra@gmail.com>
f4107842 2
d203b41a 3 * sh-opc.h (MASK): Simplify.
f4107842 4
d203b41a 52018-07-28 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 6
d203b41a
AM		 7 * s12z-dis.c (bm_decode): Deal with cases where the mode is
8 BM_RESERVED0 or BM_RESERVED1
9 * s12z-dis.c (bm_rel_decode): ditto
10 * s12z-dis.c (bm_n_bytes): ditto
11
122018-07-28 John Darrington <john@darrington.wattle.id.au>
13
14 * s12z.h: Delete.
7ba3ba91 15
1bc60e56
L		 162018-08-14 H.J. Lu <hongjiu.lu@intel.com>
17
18 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
19 address with the addr32 prefix and without base nor index
20 registers.
21
d871f3f4
L		 222018-08-11 H.J. Lu <hongjiu.lu@intel.com>
23
24 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
25 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
26 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
27 (cpu_flags): Add CpuCMOV and CpuFXSR.
28 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
29 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
30 * i386-init.h: Regenerated.
31 * i386-tbl.h: Likewise.
32
b6523c37 332018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
34
35 * arc-regs.h: Update auxiliary registers.
36
e968fc9b
JB		 372018-08-06 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
40 (RegIP, RegIZ): Define.
41 * i386-reg.tbl: Adjust comments.
42 (rip): Use Qword instead of BaseIndex. Use RegIP.
43 (eip): Use Dword instead of BaseIndex. Use RegIP.
44 (riz): Add Qword. Use RegIZ.
45 (eiz): Add Dword. Use RegIZ.
46 * i386-tbl.h: Re-generate.
47
dbf8be89
JB		 482018-08-03 Jan Beulich <jbeulich@suse.com>
49
50 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
51 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
52 vpmovzxdq, vpmovzxwd): Remove NoRex64.
53 * i386-tbl.h: Re-generate.
54
c48dadc9
JB		 552018-08-03 Jan Beulich <jbeulich@suse.com>
56
57 * i386-gen.c (operand_types): Remove Mem field.
58 * i386-opc.h (union i386_operand_type): Remove mem field.
59 * i386-init.h, i386-tbl.h: Re-generate.
60
cb86a42a
AM		 612018-08-01 Alan Modra <amodra@gmail.com>
62
63 * po/POTFILES.in: Regenerate.
64
07cc0450
NC		 652018-07-31 Nick Clifton <nickc@redhat.com>
66
67 * po/sv.po: Updated Swedish translation.
68
1424ad86
JB		 692018-07-31 Jan Beulich <jbeulich@suse.com>
70
71 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
72 * i386-init.h, i386-tbl.h: Re-generate.
73
ae2387fe
JB		 742018-07-31 Jan Beulich <jbeulich@suse.com>
75
76 * i386-opc.h (ZEROING_MASKING) Rename to ...
77 (DYNAMIC_MASKING): ... this. Adjust comment.
78 * i386-opc.tbl (MaskingMorZ): Define.
79 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
80 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
81 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
82 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
83 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
84 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
85 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
86 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
87 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
88
6ff00b5e
JB		 892018-07-31 Jan Beulich <jbeulich@suse.com>
90
91 * i386-opc.tbl: Use element rather than vector size for AVX512*
92 scatter/gather insns.
93 * i386-tbl.h: Re-generate.
94
e951d5ca
JB		 952018-07-31 Jan Beulich <jbeulich@suse.com>
96
97 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
98 (cpu_flags): Drop CpuVREX.
99 * i386-opc.h (CpuVREX): Delete.
100 (union i386_cpu_flags): Remove cpuvrex.
101 * i386-init.h, i386-tbl.h: Re-generate.
102
eb41b248
JW		 1032018-07-30 Jim Wilson <jimw@sifive.com>
104
105 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
106 fields.
107 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
108
b8891f8d
AJ		 1092018-07-30 Andrew Jenner <andrew@codesourcery.com>
110
111 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
112 * Makefile.in: Regenerated.
113 * configure.ac: Add C-SKY.
114 * configure: Regenerated.
115 * csky-dis.c: New file.
116 * csky-opc.h: New file.
117 * disassemble.c (ARCH_csky): Define.
118 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
119 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
120
16065af1
AM		 1212018-07-27 Alan Modra <amodra@gmail.com>
122
123 * ppc-opc.c (insert_sprbat): Correct function parameter and
124 return type.
125 (extract_sprbat): Likewise, variable too.
126
fa758a70
AC		 1272018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
128 Alan Modra <amodra@gmail.com>
129
130 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
131 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
132 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
133 support disjointed BAT.
134 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
135 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
136 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
137
4a1b91ea
L		 1382018-07-25 H.J. Lu <hongjiu.lu@intel.com>
139 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
140
141 * i386-gen.c (adjust_broadcast_modifier): New function.
142 (process_i386_opcode_modifier): Add an argument for operands.
143 Adjust the Broadcast value based on operands.
144 (output_i386_opcode): Pass operand_types to
145 process_i386_opcode_modifier.
146 (process_i386_opcodes): Pass NULL as operands to
147 process_i386_opcode_modifier.
148 * i386-opc.h (BYTE_BROADCAST): New.
149 (WORD_BROADCAST): Likewise.
150 (DWORD_BROADCAST): Likewise.
151 (QWORD_BROADCAST): Likewise.
152 (i386_opcode_modifier): Expand broadcast to 3 bits.
153 * i386-tbl.h: Regenerated.
154
67ce483b
AM		 1552018-07-24 Alan Modra <amodra@gmail.com>
156
157 PR 23430
158 * or1k-desc.h: Regenerate.
159
4174bfff
JB		 1602018-07-24 Jan Beulich <jbeulich@suse.com>
161
162 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
163 vcvtusi2ss, and vcvtusi2sd.
164 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
165 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
166 * i386-tbl.h: Re-generate.
167
04e65276
CZ		 1682018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
169
170 * arc-opc.c (extract_w6): Fix extending the sign.
171
47e6f81c
CZ		 1722018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
173
174 * arc-tbl.h (vewt): Allow it for ARC EM family.
175
bb71536f
AM		 1762018-07-23 Alan Modra <amodra@gmail.com>
177
178 PR 23419
179 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
180 opcode variants for mtspr/mfspr encodings.
181
8095d2f7
CX		 1822018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
183 Maciej W. Rozycki <macro@mips.com>
184
185 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
186 loongson3a descriptors.
187 (parse_mips_ase_option): Handle -M loongson-mmi option.
188 (print_mips_disassembler_options): Document -M loongson-mmi.
189 * mips-opc.c (LMMI): New macro.
190 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
191 instructions.
192
5f32791e
JB		 1932018-07-19 Jan Beulich <jbeulich@suse.com>
194
195 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
196 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
197 IgnoreSize and [XYZ]MMword where applicable.
198 * i386-tbl.h: Re-generate.
199
625cbd7a
JB		 2002018-07-19 Jan Beulich <jbeulich@suse.com>
201
202 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
203 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
204 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
205 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
206 * i386-tbl.h: Re-generate.
207
86b15c32
JB		 2082018-07-19 Jan Beulich <jbeulich@suse.com>
209
210 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
211 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
212 VPCLMULQDQ templates into their respective AVX512VL counterparts
213 where possible, using Disp8ShiftVL and CheckRegSize instead of
214 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
215 * i386-tbl.h: Re-generate.
216
cf769ed5
JB		 2172018-07-19 Jan Beulich <jbeulich@suse.com>
218
219 * i386-opc.tbl: Fold AVX512DQ templates into their respective
220 AVX512VL counterparts where possible, using Disp8ShiftVL and
221 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
222 IgnoreSize) as appropriate.
223 * i386-tbl.h: Re-generate.
224
8282b7ad
JB		 2252018-07-19 Jan Beulich <jbeulich@suse.com>
226
227 * i386-opc.tbl: Fold AVX512BW templates into their respective
228 AVX512VL counterparts where possible, using Disp8ShiftVL and
229 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
230 IgnoreSize) as appropriate.
231 * i386-tbl.h: Re-generate.
232
755908cc
JB		 2332018-07-19 Jan Beulich <jbeulich@suse.com>
234
235 * i386-opc.tbl: Fold AVX512CD templates into their respective
236 AVX512VL counterparts where possible, using Disp8ShiftVL and
237 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
238 IgnoreSize) as appropriate.
239 * i386-tbl.h: Re-generate.
240
7091c612
JB		 2412018-07-19 Jan Beulich <jbeulich@suse.com>
242
243 * i386-opc.h (DISP8_SHIFT_VL): New.
244 * i386-opc.tbl (Disp8ShiftVL): Define.
245 (various): Fold AVX512VL templates into their respective
246 AVX512F counterparts where possible, using Disp8ShiftVL and
247 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
248 IgnoreSize) as appropriate.
249 * i386-tbl.h: Re-generate.
250
c30be56e
JB		 2512018-07-19 Jan Beulich <jbeulich@suse.com>
252
253 * Makefile.am: Change dependencies and rule for
254 $(srcdir)/i386-init.h.
255 * Makefile.in: Re-generate.
256 * i386-gen.c (process_i386_opcodes): New local variable
257 "marker". Drop opening of input file. Recognize marker and line
258 number directives.
259 * i386-opc.tbl (OPCODE_I386_H): Define.
260 (i386-opc.h): Include it.
261 (None): Undefine.
262
11a322db
L		 2632018-07-18 H.J. Lu <hongjiu.lu@intel.com>
264
265 PR gas/23418
266 * i386-opc.h (Byte): Update comments.
267 (Word): Likewise.
268 (Dword): Likewise.
269 (Fword): Likewise.
270 (Qword): Likewise.
271 (Tbyte): Likewise.
272 (Xmmword): Likewise.
273 (Ymmword): Likewise.
274 (Zmmword): Likewise.
275 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
276 vcvttps2uqq.
277 * i386-tbl.h: Regenerated.
278
cde3679e
NC		 2792018-07-12 Sudakshina Das <sudi.das@arm.com>
280
281 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
282 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis-2.c: Regenerate.
285 * aarch64-opc-2.c: Regenerate.
286
45a28947
TC		 2872018-07-12 Tamar Christina <tamar.christina@arm.com>
288
289 PR binutils/23192
290 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
291 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
292 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
293 sqdmulh, sqrdmulh): Use Em16.
294
c597cc3d
SD		 2952018-07-11 Sudakshina Das <sudi.das@arm.com>
296
297 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
298 csdb together with them.
299 (thumb32_opcodes): Likewise.
300
a79eaed6
JB		 3012018-07-11 Jan Beulich <jbeulich@suse.com>
302
303 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
304 requiring 32-bit registers as operands 2 and 3. Improve
305 comments.
306 (mwait, mwaitx): Fold templates. Improve comments.
307 OPERAND_TYPE_INOUTPORTREG.
308 * i386-tbl.h: Re-generate.
309
2fb5be8d
JB		 3102018-07-11 Jan Beulich <jbeulich@suse.com>
311
312 * i386-gen.c (operand_type_init): Remove
313 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
314 OPERAND_TYPE_INOUTPORTREG.
315 * i386-init.h: Re-generate.
316
7f5cad30
JB		 3172018-07-11 Jan Beulich <jbeulich@suse.com>
318
319 * i386-opc.tbl (wrssd, wrussd): Add Dword.
320 (wrssq, wrussq): Add Qword.
321 * i386-tbl.h: Re-generate.
322
f0a85b07
JB		 3232018-07-11 Jan Beulich <jbeulich@suse.com>
324
325 * i386-opc.h: Rename OTMax to OTNum.
326 (OTNumOfUints): Adjust calculation.
327 (OTUnused): Directly alias to OTNum.
328
9dcb0ba4
MR		 3292018-07-09 Maciej W. Rozycki <macro@mips.com>
330
331 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
332 `reg_xys'.
333 (lea_reg_xys): Likewise.
334 (print_insn_loop_primitive): Rename `reg' local variable to
335 `reg_dxy'.
336
f311ba7e
TC		 3372018-07-06 Tamar Christina <tamar.christina@arm.com>
338
339 PR binutils/23242
340 * aarch64-tbl.h (ldarh): Fix disassembly mask.
341
cba05feb
TC		 3422018-07-06 Tamar Christina <tamar.christina@arm.com>
343
344 PR binutils/23369
345 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
346 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
347
471b9d15
MR		 3482018-07-02 Maciej W. Rozycki <macro@mips.com>
349
350 PR tdep/8282
351 * mips-dis.c (mips_option_arg_t): New enumeration.
352 (mips_options): New variable.
353 (disassembler_options_mips): New function.
354 (print_mips_disassembler_options): Reimplement in terms of
355 `disassembler_options_mips'.
356 * arm-dis.c (disassembler_options_arm): Adapt to using the
357 `disasm_options_and_args_t' structure.
358 * ppc-dis.c (disassembler_options_powerpc): Likewise.
359 * s390-dis.c (disassembler_options_s390): Likewise.
360
c0c468d5
TP		 3612018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
362
363 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
364 expected result.
365 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
366 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
367 * testsuite/ld-arm/tls-longplt.d: Likewise.
368
369c9167
TC		 3692018-06-29 Tamar Christina <tamar.christina@arm.com>
370
371 PR binutils/23192
372 * aarch64-asm-2.c: Regenerate.
373 * aarch64-dis-2.c: Likewise.
374 * aarch64-opc-2.c: Likewise.
375 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
376 * aarch64-opc.c (operand_general_constraint_met_p,
377 aarch64_print_operand): Likewise.
378 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
379 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
380 fmlal2, fmlsl2.
381 (AARCH64_OPERANDS): Add Em2.
382
30aa1306
NC		 3832018-06-26 Nick Clifton <nickc@redhat.com>
384
385 * po/uk.po: Updated Ukranian translation.
386 * po/de.po: Updated German translation.
387 * po/pt_BR.po: Updated Brazilian Portuguese translation.
388
eca4b721
NC		 3892018-06-26 Nick Clifton <nickc@redhat.com>
390
391 * nfp-dis.c: Fix spelling mistake.
392
71300e2c
NC		 3932018-06-24 Nick Clifton <nickc@redhat.com>
394
395 * configure: Regenerate.
396 * po/opcodes.pot: Regenerate.
397
719d8288
NC		 3982018-06-24 Nick Clifton <nickc@redhat.com>
399
400 2.31 branch created.
401
514cd3a0
TC		 4022018-06-19 Tamar Christina <tamar.christina@arm.com>
403
404 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
405 * aarch64-asm-2.c: Regenerate.
406 * aarch64-dis-2.c: Likewise.
407
385e4d0f
MR		 4082018-06-21 Maciej W. Rozycki <macro@mips.com>
409
410 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
411 `-M ginv' option description.
412
160d1b3d
SH		 4132018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
414
415 PR gas/23305
416 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
417 la and lla.
418
d0ac1c44
SM		 4192018-06-19 Simon Marchi <simon.marchi@ericsson.com>
420
421 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
422 * configure.ac: Remove AC_PREREQ.
423 * Makefile.in: Re-generate.
424 * aclocal.m4: Re-generate.
425 * configure: Re-generate.
426
6f20c942
FS		 4272018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
428
429 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
430 mips64r6 descriptors.
431 (parse_mips_ase_option): Handle -Mginv option.
432 (print_mips_disassembler_options): Document -Mginv.
433 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
434 (GINV): New macro.
435 (mips_opcodes): Define ginvi and ginvt.
436
730c3174
SE		 4372018-06-13 Scott Egerton <scott.egerton@imgtec.com>
438 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
439
440 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
441 * mips-opc.c (CRC, CRC64): New macros.
442 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
443 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
444 crc32cd for CRC64.
445
cb366992
EB		 4462018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
447
448 PR 20319
449 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
450 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
451
ce72cd46
AM		 4522018-06-06 Alan Modra <amodra@gmail.com>
453
454 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
455 setjmp. Move init for some other vars later too.
456
4b8e28c7
MF		 4572018-06-04 Max Filippov <jcmvbkbc@gmail.com>
458
459 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
460 (dis_private): Add new fields for property section tracking.
461 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
462 (xtensa_instruction_fits): New functions.
463 (fetch_data): Bump minimal fetch size to 4.
464 (print_insn_xtensa): Make struct dis_private static.
465 Load and prepare property table on section change.
466 Don't disassemble literals. Don't disassemble instructions that
467 cross property table boundaries.
468
55e99962
L		 4692018-06-01 H.J. Lu <hongjiu.lu@intel.com>
470
471 * configure: Regenerated.
472
733bd0ab
JB		 4732018-06-01 Jan Beulich <jbeulich@suse.com>
474
475 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
476 * i386-tbl.h: Re-generate.
477
dfd27d41
JB		 4782018-06-01 Jan Beulich <jbeulich@suse.com>
479
480 * i386-opc.tbl (sldt, str): Add NoRex64.
481 * i386-tbl.h: Re-generate.
482
64795710
JB		 4832018-06-01 Jan Beulich <jbeulich@suse.com>
484
485 * i386-opc.tbl (invpcid): Add Oword.
486 * i386-tbl.h: Re-generate.
487
030157d8
AM		 4882018-06-01 Alan Modra <amodra@gmail.com>
489
490 * sysdep.h (_bfd_error_handler): Don't declare.
491 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
492 * rl78-decode.opc: Likewise.
493 * msp430-decode.c: Regenerate.
494 * rl78-decode.c: Regenerate.
495
a9660a6f
AP		 4962018-05-30 Amit Pawar <Amit.Pawar@amd.com>
497
498 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
499 * i386-init.h : Regenerated.
500
277eb7f6
AM		 5012018-05-25 Alan Modra <amodra@gmail.com>
502
503 * Makefile.in: Regenerate.
504 * po/POTFILES.in: Regenerate.
505
98553ad3
PB		 5062018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
507
508 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
509 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
510 (insert_bab, extract_bab, insert_btab, extract_btab,
511 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
512 (BAT, BBA VBA RBS XB6S): Delete macros.
513 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
514 (BB, BD, RBX, XC6): Update for new macros.
515 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
516 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
517 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
518 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
519
7b4ae824
JD		 5202018-05-18 John Darrington <john@darrington.wattle.id.au>
521
522 * Makefile.am: Add support for s12z architecture.
523 * configure.ac: Likewise.
524 * disassemble.c: Likewise.
525 * disassemble.h: Likewise.
526 * Makefile.in: Regenerate.
527 * configure: Regenerate.
528 * s12z-dis.c: New file.
529 * s12z.h: New file.
530
29e0f0a1
AM		 5312018-05-18 Alan Modra <amodra@gmail.com>
532
533 * nfp-dis.c: Don't #include libbfd.h.
534 (init_nfp3200_priv): Use bfd_get_section_contents.
535 (nit_nfp6000_mecsr_sec): Likewise.
536
809276d2
NC		 5372018-05-17 Nick Clifton <nickc@redhat.com>
538
539 * po/zh_CN.po: Updated simplified Chinese translation.
540
ff329288
TC		 5412018-05-16 Tamar Christina <tamar.christina@arm.com>
542
543 PR binutils/23109
544 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
545 * aarch64-dis-2.c: Regenerate.
546
f9830ec1
TC		 5472018-05-15 Tamar Christina <tamar.christina@arm.com>
548
549 PR binutils/21446
550 * aarch64-asm.c (opintl.h): Include.
551 (aarch64_ins_sysreg): Enforce read/write constraints.
552 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
553 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
554 (F_REG_READ, F_REG_WRITE): New.
555 * aarch64-opc.c (aarch64_print_operand): Generate notes for
556 AARCH64_OPND_SYSREG.
557 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
558 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
559 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
560 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
561 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
562 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
563 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
564 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
565 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
566 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
567 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
568 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
569 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
570 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
571 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
572 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
573 msr (F_SYS_WRITE), mrs (F_SYS_READ).
574
7d02540a
TC		 5752018-05-15 Tamar Christina <tamar.christina@arm.com>
576
577 PR binutils/21446
578 * aarch64-dis.c (no_notes: New.
579 (parse_aarch64_dis_option): Support notes.
580 (aarch64_decode_insn, print_operands): Likewise.
581 (print_aarch64_disassembler_options): Document notes.
582 * aarch64-opc.c (aarch64_print_operand): Support notes.
583
561a72d4
TC		 5842018-05-15 Tamar Christina <tamar.christina@arm.com>
585
586 PR binutils/21446
587 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
588 and take error struct.
589 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
590 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
591 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
592 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
593 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
594 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
595 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
596 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
597 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
598 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
599 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
600 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
601 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
602 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
603 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
604 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
605 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
606 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
607 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
608 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
609 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
610 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
611 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
612 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
613 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
614 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
615 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
616 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
617 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
618 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
619 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
620 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
621 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
622 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
623 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
624 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
625 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
626 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
627 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
628 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
629 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
630 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
631 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
632 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
633 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
634 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
635 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
636 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
637 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
638 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
639 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
640 (determine_disassembling_preference, aarch64_decode_insn,
641 print_insn_aarch64_word, print_insn_data): Take errors struct.
642 (print_insn_aarch64): Use errors.
643 * aarch64-asm-2.c: Regenerate.
644 * aarch64-dis-2.c: Regenerate.
645 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
646 boolean in aarch64_insert_operan.
647 (print_operand_extractor): Likewise.
648 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
649
1678bd35
FT		 6502018-05-15 Francois H. Theron <francois.theron@netronome.com>
651
652 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
653
06cfb1c8
L		 6542018-05-09 H.J. Lu <hongjiu.lu@intel.com>
655
656 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
657
84f9f8c3
AM		 6582018-05-09 Sebastian Rasmussen <sebras@gmail.com>
659
660 * cr16-opc.c (cr16_instruction): Comment typo fix.
661 * hppa-dis.c (print_insn_hppa): Likewise.
662
e6f372ba
JW		 6632018-05-08 Jim Wilson <jimw@sifive.com>
664
665 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
666 (match_c_slli64, match_srxi_as_c_srxi): New.
667 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
668 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
669 <c.slli, c.srli, c.srai>: Use match_s_slli.
670 <c.slli64, c.srli64, c.srai64>: New.
671
f413a913
AM		 6722018-05-08 Alan Modra <amodra@gmail.com>
673
674 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
675 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
676 partition opcode space for index lookup.
677
a87a6478
PB		 6782018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
679
680 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
681 <insn_length>: ...with this. Update usage.
682 Remove duplicate call to *info->memory_error_func.
683
c0a30a9f
L		 6842018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
685 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-dis.c (Gva): New.
688 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
689 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
690 (prefix_table): New instructions (see prefix above).
691 (mod_table): New instructions (see prefix above).
692 (OP_G): Handle va_mode.
693 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
694 CPU_MOVDIR64B_FLAGS.
695 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
696 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
697 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
698 * i386-opc.tbl: Add movidir{i,64b}.
699 * i386-init.h: Regenerated.
700 * i386-tbl.h: Likewise.
701
75c0a438
L		 7022018-05-07 H.J. Lu <hongjiu.lu@intel.com>
703
704 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
705 AddrPrefixOpReg.
706 * i386-opc.h (AddrPrefixOp0): Renamed to ...
707 (AddrPrefixOpReg): This.
708 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
709 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
710
2ceb7719
PB		 7112018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
712
713 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
714 (vle_num_opcodes): Likewise.
715 (spe2_num_opcodes): Likewise.
716 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
717 initialization loop.
718 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
719 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
720 only once.
721
b3ac5c6c
TC		 7222018-05-01 Tamar Christina <tamar.christina@arm.com>
723
724 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
725
fe944acf
FT		 7262018-04-30 Francois H. Theron <francois.theron@netronome.com>
727
728 Makefile.am: Added nfp-dis.c.
729 configure.ac: Added bfd_nfp_arch.
730 disassemble.h: Added print_insn_nfp prototype.
731 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
732 nfp-dis.c: New, for NFP support.
733 po/POTFILES.in: Added nfp-dis.c to the list.
734 Makefile.in: Regenerate.
735 configure: Regenerate.
736
e2195274
JB		 7372018-04-26 Jan Beulich <jbeulich@suse.com>
738
739 * i386-opc.tbl: Fold various non-memory operand AVX512VL
740 templates into their base ones.
741 * i386-tlb.h: Re-generate.
742
59ef5df4
JB		 7432018-04-26 Jan Beulich <jbeulich@suse.com>
744
745 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
746 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
747 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
748 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
749 * i386-init.h: Re-generate.
750
6e041cf4
JB		 7512018-04-26 Jan Beulich <jbeulich@suse.com>
752
753 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
754 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
755 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
756 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
757 comment.
758 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
759 and CpuRegMask.
760 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
761 CpuRegMask: Delete.
762 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
763 cpuregzmm, and cpuregmask.
764 * i386-init.h: Re-generate.
765 * i386-tbl.h: Re-generate.
766
0e0eea78
JB		 7672018-04-26 Jan Beulich <jbeulich@suse.com>
768
769 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
770 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
771 * i386-init.h: Re-generate.
772
2f1bada2
JB		 7732018-04-26 Jan Beulich <jbeulich@suse.com>
774
775 * i386-gen.c (VexImmExt): Delete.
776 * i386-opc.h (VexImmExt, veximmext): Delete.
777 * i386-opc.tbl: Drop all VexImmExt uses.
778 * i386-tlb.h: Re-generate.
779
bacd1457
JB		 7802018-04-25 Jan Beulich <jbeulich@suse.com>
781
782 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
783 register-only forms.
784 * i386-tlb.h: Re-generate.
785
10bba94b
TC		 7862018-04-25 Tamar Christina <tamar.christina@arm.com>
787
788 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
789
c48935d7
IT		 7902018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
791
792 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
793 PREFIX_0F1C.
794 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
795 (cpu_flags): Add CpuCLDEMOTE.
796 * i386-init.h: Regenerate.
797 * i386-opc.h (enum): Add CpuCLDEMOTE,
798 (i386_cpu_flags): Add cpucldemote.
799 * i386-opc.tbl: Add cldemote.
800 * i386-tbl.h: Regenerate.
801
211dc24b
AM		 8022018-04-16 Alan Modra <amodra@gmail.com>
803
804 * Makefile.am: Remove sh5 and sh64 support.
805 * configure.ac: Likewise.
806 * disassemble.c: Likewise.
807 * disassemble.h: Likewise.
808 * sh-dis.c: Likewise.
809 * sh64-dis.c: Delete.
810 * sh64-opc.c: Delete.
811 * sh64-opc.h: Delete.
812 * Makefile.in: Regenerate.
813 * configure: Regenerate.
814 * po/POTFILES.in: Regenerate.
815
a9a4b302
AM		 8162018-04-16 Alan Modra <amodra@gmail.com>
817
818 * Makefile.am: Remove w65 support.
819 * configure.ac: Likewise.
820 * disassemble.c: Likewise.
821 * disassemble.h: Likewise.
822 * w65-dis.c: Delete.
823 * w65-opc.h: Delete.
824 * Makefile.in: Regenerate.
825 * configure: Regenerate.
826 * po/POTFILES.in: Regenerate.
827
04cb01fd
AM		 8282018-04-16 Alan Modra <amodra@gmail.com>
829
830 * configure.ac: Remove we32k support.
831 * configure: Regenerate.
832
c2bf1eec
AM		 8332018-04-16 Alan Modra <amodra@gmail.com>
834
835 * Makefile.am: Remove m88k support.
836 * configure.ac: Likewise.
837 * disassemble.c: Likewise.
838 * disassemble.h: Likewise.
839 * m88k-dis.c: Delete.
840 * Makefile.in: Regenerate.
841 * configure: Regenerate.
842 * po/POTFILES.in: Regenerate.
843
6793974d
AM		 8442018-04-16 Alan Modra <amodra@gmail.com>
845
846 * Makefile.am: Remove i370 support.
847 * configure.ac: Likewise.
848 * disassemble.c: Likewise.
849 * disassemble.h: Likewise.
850 * i370-dis.c: Delete.
851 * i370-opc.c: Delete.
852 * Makefile.in: Regenerate.
853 * configure: Regenerate.
854 * po/POTFILES.in: Regenerate.
855
e82aa794
AM		 8562018-04-16 Alan Modra <amodra@gmail.com>
857
858 * Makefile.am: Remove h8500 support.
859 * configure.ac: Likewise.
860 * disassemble.c: Likewise.
861 * disassemble.h: Likewise.
862 * h8500-dis.c: Delete.
863 * h8500-opc.h: Delete.
864 * Makefile.in: Regenerate.
865 * configure: Regenerate.
866 * po/POTFILES.in: Regenerate.
867
fceadf09
AM		 8682018-04-16 Alan Modra <amodra@gmail.com>
869
870 * configure.ac: Remove tahoe support.
871 * configure: Regenerate.
872
ae1d3843
L		 8732018-04-15 H.J. Lu <hongjiu.lu@intel.com>
874
875 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
876 umwait.
877 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
878 64-bit mode.
879 * i386-tbl.h: Regenerated.
880
de89d0a3
IT		 8812018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
882
883 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
884 PREFIX_MOD_1_0FAE_REG_6.
885 (va_mode): New.
886 (OP_E_register): Use va_mode.
887 * i386-dis-evex.h (prefix_table):
888 New instructions (see prefixes above).
889 * i386-gen.c (cpu_flag_init): Add WAITPKG.
890 (cpu_flags): Likewise.
891 * i386-opc.h (enum): Likewise.
892 (i386_cpu_flags): Likewise.
893 * i386-opc.tbl: Add umonitor, umwait, tpause.
894 * i386-init.h: Regenerate.
895 * i386-tbl.h: Likewise.
896
a8eb42a8
AM		 8972018-04-11 Alan Modra <amodra@gmail.com>
898
899 * opcodes/i860-dis.c: Delete.
900 * opcodes/i960-dis.c: Delete.
901 * Makefile.am: Remove i860 and i960 support.
902 * configure.ac: Likewise.
903 * disassemble.c: Likewise.
904 * disassemble.h: Likewise.
905 * Makefile.in: Regenerate.
906 * configure: Regenerate.
907 * po/POTFILES.in: Regenerate.
908
caf0678c
L		 9092018-04-04 H.J. Lu <hongjiu.lu@intel.com>
910
911 PR binutils/23025
912 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
913 to 0.
914 (print_insn): Clear vex instead of vex.evex.
915
4fb0d2b9
NC		 9162018-04-04 Nick Clifton <nickc@redhat.com>
917
918 * po/es.po: Updated Spanish translation.
919
c39e5b26
JB		 9202018-03-28 Jan Beulich <jbeulich@suse.com>
921
922 * i386-gen.c (opcode_modifiers): Delete VecESize.
923 * i386-opc.h (VecESize): Delete.
924 (struct i386_opcode_modifier): Delete vecesize.
925 * i386-opc.tbl: Drop VecESize.
926 * i386-tlb.h: Re-generate.
927
8e6e0792
JB		 9282018-03-28 Jan Beulich <jbeulich@suse.com>
929
930 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
931 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
932 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
933 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
934 * i386-tlb.h: Re-generate.
935
9f123b91
JB		 9362018-03-28 Jan Beulich <jbeulich@suse.com>
937
938 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
939 Fold AVX512 forms
940 * i386-tlb.h: Re-generate.
941
9646c87b
JB		 9422018-03-28 Jan Beulich <jbeulich@suse.com>
943
944 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
945 (vex_len_table): Drop Y for vcvt*2si.
946 (putop): Replace plain 'Y' handling by abort().
947
c8d59609
NC		 9482018-03-28 Nick Clifton <nickc@redhat.com>
949
950 PR 22988
951 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
952 instructions with only a base address register.
953 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
954 handle AARHC64_OPND_SVE_ADDR_R.
955 (aarch64_print_operand): Likewise.
956 * aarch64-asm-2.c: Regenerate.
957 * aarch64_dis-2.c: Regenerate.
958 * aarch64-opc-2.c: Regenerate.
959
b8c169f3
JB		 9602018-03-22 Jan Beulich <jbeulich@suse.com>
961
962 * i386-opc.tbl: Drop VecESize from register only insn forms and
963 memory forms not allowing broadcast.
964 * i386-tlb.h: Re-generate.
965
96bc132a
JB		 9662018-03-22 Jan Beulich <jbeulich@suse.com>
967
968 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
969 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
970 sha256*): Drop Disp<N>.
971
9f79e886
JB		 9722018-03-22 Jan Beulich <jbeulich@suse.com>
973
974 * i386-dis.c (EbndS, bnd_swap_mode): New.
975 (prefix_table): Use EbndS.
976 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
977 * i386-opc.tbl (bndmov): Move misplaced Load.
978 * i386-tlb.h: Re-generate.
979
d6793fa1
JB		 9802018-03-22 Jan Beulich <jbeulich@suse.com>
981
982 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
983 templates allowing memory operands and folded ones for register
984 only flavors.
985 * i386-tlb.h: Re-generate.
986
f7768225
JB		 9872018-03-22 Jan Beulich <jbeulich@suse.com>
988
989 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
990 256-bit templates. Drop redundant leftover Disp<N>.
991 * i386-tlb.h: Re-generate.
992
0e35537d
JW		 9932018-03-14 Kito Cheng <kito.cheng@gmail.com>
994
995 * riscv-opc.c (riscv_insn_types): New.
996
b4a3689a
NC		 9972018-03-13 Nick Clifton <nickc@redhat.com>
998
999 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1000
d3d50934
L		 10012018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1002
1003 * i386-opc.tbl: Add Optimize to clr.
1004 * i386-tbl.h: Regenerated.
1005
bd5dea88
L		 10062018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1007
1008 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1009 * i386-opc.h (OldGcc): Removed.
1010 (i386_opcode_modifier): Remove oldgcc.
1011 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1012 instructions for old (<= 2.8.1) versions of gcc.
1013 * i386-tbl.h: Regenerated.
1014
e771e7c9
JB		 10152018-03-08 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-opc.h (EVEXDYN): New.
1018 * i386-opc.tbl: Fold various AVX512VL templates.
1019 * i386-tlb.h: Re-generate.
1020
ed438a93
JB		 10212018-03-08 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1024 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1025 vpexpandd, vpexpandq): Fold AFX512VF templates.
1026 * i386-tlb.h: Re-generate.
1027
454172a9
JB		 10282018-03-08 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1031 Fold 128- and 256-bit VEX-encoded templates.
1032 * i386-tlb.h: Re-generate.
1033
36824150
JB		 10342018-03-08 Jan Beulich <jbeulich@suse.com>
1035
1036 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1037 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1038 vpexpandd, vpexpandq): Fold AVX512F templates.
1039 * i386-tlb.h: Re-generate.
1040
e7f5c0a9
JB		 10412018-03-08 Jan Beulich <jbeulich@suse.com>
1042
1043 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1044 64-bit templates. Drop Disp<N>.
1045 * i386-tlb.h: Re-generate.
1046
25a4277f
JB		 10472018-03-08 Jan Beulich <jbeulich@suse.com>
1048
1049 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1050 and 256-bit templates.
1051 * i386-tlb.h: Re-generate.
1052
d2224064
JB		 10532018-03-08 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1056 * i386-tlb.h: Re-generate.
1057
1b193f0b
JB		 10582018-03-08 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1061 Drop NoAVX.
1062 * i386-tlb.h: Re-generate.
1063
f2f6a710
JB		 10642018-03-08 Jan Beulich <jbeulich@suse.com>
1065
1066 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1067 * i386-tlb.h: Re-generate.
1068
38e314eb
JB		 10692018-03-08 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-gen.c (opcode_modifiers): Delete FloatD.
1072 * i386-opc.h (FloatD): Delete.
1073 (struct i386_opcode_modifier): Delete floatd.
1074 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1075 FloatD by D.
1076 * i386-tlb.h: Re-generate.
1077
d53e6b98
JB		 10782018-03-08 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1081
2907c2f5
JB		 10822018-03-08 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1085 * i386-tlb.h: Re-generate.
1086
73053c1f
JB		 10872018-03-08 Jan Beulich <jbeulich@suse.com>
1088
1089 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1090 forms.
1091 * i386-tlb.h: Re-generate.
1092
52fe4420
AM		 10932018-03-07 Alan Modra <amodra@gmail.com>
1094
1095 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1096 bfd_arch_rs6000.
1097 * disassemble.h (print_insn_rs6000): Delete.
1098 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1099 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1100 (print_insn_rs6000): Delete.
1101
a6743a54
AM		 11022018-03-03 Alan Modra <amodra@gmail.com>
1103
1104 * sysdep.h (opcodes_error_handler): Define.
1105 (_bfd_error_handler): Declare.
1106 * Makefile.am: Remove stray #.
1107 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1108 EDIT" comment.
1109 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1110 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1111 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1112 opcodes_error_handler to print errors. Standardize error messages.
1113 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1114 and include opintl.h.
1115 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1116 * i386-gen.c: Standardize error messages.
1117 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1118 * Makefile.in: Regenerate.
1119 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1120 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1121 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1122 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1123 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1124 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1125 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1126 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1127 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1128 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1129 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1130 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1131 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1132
8305403a
L		 11332018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1134
1135 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1136 vpsub[bwdq] instructions.
1137 * i386-tbl.h: Regenerated.
1138
e184813f
AM		 11392018-03-01 Alan Modra <amodra@gmail.com>
1140
1141 * configure.ac (ALL_LINGUAS): Sort.
1142 * configure: Regenerate.
1143
5b616bef
TP		 11442018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1145
1146 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1147 macro by assignements.
1148
b6f8c7c4
L		 11492018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1150
1151 PR gas/22871
1152 * i386-gen.c (opcode_modifiers): Add Optimize.
1153 * i386-opc.h (Optimize): New enum.
1154 (i386_opcode_modifier): Add optimize.
1155 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1156 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1157 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1158 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1159 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1160 vpxord and vpxorq.
1161 * i386-tbl.h: Regenerated.
1162
e95b887f
AM		 11632018-02-26 Alan Modra <amodra@gmail.com>
1164
1165 * crx-dis.c (getregliststring): Allocate a large enough buffer
1166 to silence false positive gcc8 warning.
1167
0bccfb29
JW		 11682018-02-22 Shea Levy <shea@shealevy.com>
1169
1170 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1171
6b6b6807
L		 11722018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1173
1174 * i386-opc.tbl: Add {rex},
1175 * i386-tbl.h: Regenerated.
1176
75f31665
MR		 11772018-02-20 Maciej W. Rozycki <macro@mips.com>
1178
1179 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1180 (mips16_opcodes): Replace `M' with `m' for "restore".
1181
e207bc53
TP		 11822018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1183
1184 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1185
87993319
MR		 11862018-02-13 Maciej W. Rozycki <macro@mips.com>
1187
1188 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1189 variable to `function_index'.
1190
68d20676
NC		 11912018-02-13 Nick Clifton <nickc@redhat.com>
1192
1193 PR 22823
1194 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1195 about truncation of printing.
1196
d2159fdc
HW		 11972018-02-12 Henry Wong <henry@stuffedcow.net>
1198
1199 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1200
f174ef9f
NC		 12012018-02-05 Nick Clifton <nickc@redhat.com>
1202
1203 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1204
be3a8dca
IT		 12052018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1206
1207 * i386-dis.c (enum): Add pconfig.
1208 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1209 (cpu_flags): Add CpuPCONFIG.
1210 * i386-opc.h (enum): Add CpuPCONFIG.
1211 (i386_cpu_flags): Add cpupconfig.
1212 * i386-opc.tbl: Add PCONFIG instruction.
1213 * i386-init.h: Regenerate.
1214 * i386-tbl.h: Likewise.
1215
3233d7d0
IT		 12162018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1217
1218 * i386-dis.c (enum): Add PREFIX_0F09.
1219 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1220 (cpu_flags): Add CpuWBNOINVD.
1221 * i386-opc.h (enum): Add CpuWBNOINVD.
1222 (i386_cpu_flags): Add cpuwbnoinvd.
1223 * i386-opc.tbl: Add WBNOINVD instruction.
1224 * i386-init.h: Regenerate.
1225 * i386-tbl.h: Likewise.
1226
e925c834
JW		 12272018-01-17 Jim Wilson <jimw@sifive.com>
1228
1229 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1230
d777820b
IT		 12312018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1232
1233 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1234 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1235 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1236 (cpu_flags): Add CpuIBT, CpuSHSTK.
1237 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1238 (i386_cpu_flags): Add cpuibt, cpushstk.
1239 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1240 * i386-init.h: Regenerate.
1241 * i386-tbl.h: Likewise.
1242
f6efed01
NC		 12432018-01-16 Nick Clifton <nickc@redhat.com>
1244
1245 * po/pt_BR.po: Updated Brazilian Portugese translation.
1246 * po/de.po: Updated German translation.
1247
2721d702
JW		 12482018-01-15 Jim Wilson <jimw@sifive.com>
1249
1250 * riscv-opc.c (match_c_nop): New.
1251 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1252
616dcb87
NC		 12532018-01-15 Nick Clifton <nickc@redhat.com>
1254
1255 * po/uk.po: Updated Ukranian translation.
1256
3957a496
NC		 12572018-01-13 Nick Clifton <nickc@redhat.com>
1258
1259 * po/opcodes.pot: Regenerated.
1260
769c7ea5
NC		 12612018-01-13 Nick Clifton <nickc@redhat.com>
1262
1263 * configure: Regenerate.
1264
faf766e3
NC		 12652018-01-13 Nick Clifton <nickc@redhat.com>
1266
1267 2.30 branch created.
1268
888a89da
IT		 12692018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1270
1271 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1272 * i386-tbl.h: Regenerate.
1273
cbda583a
JB		 12742018-01-10 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1277 * i386-tbl.h: Re-generate.
1278
c9e92278
JB		 12792018-01-10 Jan Beulich <jbeulich@suse.com>
1280
1281 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1282 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1283 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1284 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1285 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1286 Disp8MemShift of AVX512VL forms.
1287 * i386-tbl.h: Re-generate.
1288
35fd2b2b
JW		 12892018-01-09 Jim Wilson <jimw@sifive.com>
1290
1291 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1292 then the hi_addr value is zero.
1293
91d8b670
JG		 12942018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1295
1296 * arm-dis.c (arm_opcodes): Add csdb.
1297 (thumb32_opcodes): Add csdb.
1298
be2e7d95
JG		 12992018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1300
1301 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1302 * aarch64-asm-2.c: Regenerate.
1303 * aarch64-dis-2.c: Regenerate.
1304 * aarch64-opc-2.c: Regenerate.
1305
704a705d
L		 13062018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1307
1308 PR gas/22681
1309 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1310 Remove AVX512 vmovd with 64-bit operands.
1311 * i386-tbl.h: Regenerated.
1312
35eeb78f
JW		 13132018-01-05 Jim Wilson <jimw@sifive.com>
1314
1315 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1316 jalr.
1317
219d1afa
AM		 13182018-01-03 Alan Modra <amodra@gmail.com>
1319
1320 Update year range in copyright notice of all files.
1321
1508bbf5
JB		 13222018-01-02 Jan Beulich <jbeulich@suse.com>
1323
1324 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1325 and OPERAND_TYPE_REGZMM entries.
1326
1e563868 1327For older changes see ChangeLog-2017
3499769a 1328\f
1e563868 1329Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1330
1331Copying and distribution of this file, with or without modification,
1332are permitted in any medium without royalty provided the copyright
1333notice and this notice are preserved.
1334
1335Local Variables:
1336mode: change-log
1337left-margin: 8
1338fill-column: 74
1339version-control: never
1340End:
GDB Binutils - Deliverables
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