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Adding Mike Wrighton to gdb/MAINTAINERS.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b132a67d
DE		 12012-09-14 David Edelsohn <dje.gcc@gmail.com>
2
3 * configure: Regenerate.
4
1f9b75dd
AG		 52012-09-14 Anthony Green <green@moxielogic.com>
6
7 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
8 the address after the branch instruction.
9
e202fa84
AG		 102012-09-13 Anthony Green <green@moxielogic.com>
11
12 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
13
00716ab1
AM		 142012-09-10 Matthias Klose <doko@ubuntu.com>
15
16 * config.in: Disable sanity check for kfreebsd.
17
6d2920c8
L		 182012-09-10 H.J. Lu <hongjiu.lu@intel.com>
19
20 * configure: Regenerated.
21
b3e14eda
L		 222012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
23
24 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
25 * ia64-gen.c: Promote completer index type to longlong.
26 (irf_operand): Add new register recognition.
27 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
28 (lookup_specifier): Add new resource recognition.
29 (insert_bit_table_ent): Relax abort condition according to the
30 changed completer index type.
31 (print_dis_table): Fix printf format for completer index.
32 * ia64-ic.tbl: Add a new instruction class.
33 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
34 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
35 * ia64-opc.h: Define short names for new operand types.
36 * ia64-raw.tbl: Add new RAW resource for DAHR register.
37 * ia64-waw.tbl: Add new WAW resource for DAHR register.
38 * ia64-asmtab.c: Regenerate.
39
382c72e9
PB		 402012-08-29 Peter Bergner <bergner@vnet.ibm.com>
41
42 * ppc-opc.c (VXASHB_MASK): New define.
43 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
44
fb048c26
PB		 452012-08-28 Peter Bergner <bergner@vnet.ibm.com>
46
47 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
48 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
49 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
50 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
51 vupklsh>: Use VXVA_MASK.
52 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
53 <mfvscr>: Use VXVAVB_MASK.
54 <mtvscr>: Use VXVDVA_MASK.
55 <vspltb>: Use VXUIMM4_MASK.
56 <vsplth>: Use VXUIMM3_MASK.
57 <vspltw>: Use VXUIMM2_MASK.
58
3c9017d2
MGD		 592012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
60
61 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
62
48adcd8e
MGD		 632012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
64
65 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
66
4f51b4bd
MGD		 672012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
68
69 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
70
91ff7894
MGD		 712012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
72
73 * arm-dis.c (neon_opcodes): Add support for AES instructions.
74
c70a8987
MGD		 752012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
76
77 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
78 conversions.
79
30bdf752
MGD		 802012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
81
82 * arm-dis.c (coprocessor_opcodes): Add VRINT.
83 (neon_opcodes): Likewise.
84
7e8e6784
MGD		 852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
86
87 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
88 variants.
89 (neon_opcodes): Likewise.
90
73924fbc
MGD		 912012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
92
93 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
94 (neon_opcodes): Likewise.
95
33399f07
MGD		 962012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
97
98 * arm-dis.c (coprocessor_opcodes): Add VSEL.
99 (print_insn_coprocessor): Add new %<>c bitfield format
100 specifier.
101
9eb6c0f1
MGD		 1022012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
103
104 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
105 (thumb32_opcodes): Likewise.
106 (print_arm_insn): Add support for %<>T formatter.
107
8884b720
MGD		 1082012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
109
110 * arm-dis.c (arm_opcodes): Add HLT.
111 (thumb_opcodes): Likewise.
112
b79f7053
MGD		 1132012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
114
115 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
116
53c4b28b
MGD		 1172012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
118
119 * arm-dis.c (arm_opcodes): Add SEVL.
120 (thumb_opcodes): Likewise.
121 (thumb32_opcodes): Likewise.
122
e797f7e0
MGD		 1232012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
124
125 * arm-dis.c (data_barrier_option): New function.
126 (print_insn_arm): Use data_barrier_option.
127 (print_insn_thumb32): Use data_barrier_option.
128
e2efe87d
MGD		 1292012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
130
131 * arm-dis.c (COND_UNCOND): New constant.
132 (print_insn_coprocessor): Add support for %u format specifier.
133 (print_insn_neon): Likewise.
134
2c63854f
DM		 1352012-08-21 David S. Miller <davem@davemloft.net>
136
137 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
138 F3F4 macro.
139
e67ed0e8
AM		 1402012-08-20 Edmar Wienskoski <edmar@freescale.com>
141
142 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
143 vabsduh, vabsduw, mviwsplt.
144
7b458c12
L		 1452012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
146
147 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
148 CPU_BTVER2_FLAGS.
149
e67ed0e8 150 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 151
152 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
153 * i386-init.h: Regenerated.
154 * i386-tbl.h: Likewise.
155
eb80cb87
NC		 1562012-08-17 Nick Clifton <nickc@redhat.com>
157
158 * po/uk.po: New Ukranian translation.
159 * configure.in (ALL_LINGUAS): Add uk.
160 * configure: Regenerate.
161
8baf7b78
PB		 1622012-08-16 Peter Bergner <bergner@vnet.ibm.com>
163
164 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
165 RBX for the third operand.
166 <"lswi">: Use RAX for second and NBI for the third operand.
167
3d557b4c
DD		 1682012-08-15 DJ Delorie <dj@redhat.com>
169
170 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
171 operands, so that data addresses can be corrected when not
172 ES-overridden.
173 * rl78-decode.c: Regenerate.
174 * rl78-dis.c (print_insn_rl78): Make order of modifiers
175 irrelevent. When the 'e' specifier is used on an operand and no
176 ES prefix is provided, adjust address to make it absolute.
177
588925d0
PB		 1782012-08-15 Peter Bergner <bergner@vnet.ibm.com>
179
180 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
181
9f6a6cc0
PB		 1822012-08-15 Peter Bergner <bergner@vnet.ibm.com>
183
184 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
185
fc8c4fd1
MR		 1862012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
187
188 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
189 macros, use local variables for info struct member accesses,
190 update the type of the variable used to hold the instruction
191 word.
192 (print_insn_mips, print_mips16_insn_arg): Likewise.
193 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
194 local variables for info struct member accesses.
195 (print_insn_micromips): Add GET_OP_S local macro.
196 (_print_insn_mips): Update the type of the variable used to hold
197 the instruction word.
198
a06ea964 1992012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 200 Laurent Desnogues <laurent.desnogues@arm.com>
201 Jim MacArthur <jim.macarthur@arm.com>
202 Marcus Shawcroft <marcus.shawcroft@arm.com>
203 Nigel Stephens <nigel.stephens@arm.com>
204 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
205 Richard Earnshaw <rearnsha@arm.com>
206 Sofiane Naci <sofiane.naci@arm.com>
207 Tejas Belagod <tejas.belagod@arm.com>
208 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 209
210 * Makefile.am: Add AArch64.
211 * Makefile.in: Regenerate.
212 * aarch64-asm.c: New file.
213 * aarch64-asm.h: New file.
214 * aarch64-dis.c: New file.
215 * aarch64-dis.h: New file.
216 * aarch64-gen.c: New file.
217 * aarch64-opc.c: New file.
218 * aarch64-opc.h: New file.
219 * aarch64-tbl.h: New file.
220 * configure.in: Add AArch64.
221 * configure: Regenerate.
222 * disassemble.c: Add AArch64.
223 * aarch64-asm-2.c: New file (automatically generated).
224 * aarch64-dis-2.c: New file (automatically generated).
225 * aarch64-opc-2.c: New file (automatically generated).
226 * po/POTFILES.in: Regenerate.
227
35d0a169
MR		 2282012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
229
230 * micromips-opc.c (micromips_opcodes): Update comment.
231 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
232 instructions for IOCT as appropriate.
233 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
234 opcode_is_member.
235 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
236 the result of a check for the -Wno-missing-field-initializers
237 GCC option.
238 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
239 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
240 compilation.
241 (mips16-opc.lo): Likewise.
242 (micromips-opc.lo): Likewise.
243 * aclocal.m4: Regenerate.
244 * configure: Regenerate.
245 * Makefile.in: Regenerate.
246
5c5acbbd
L		 2472012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
248
249 PR gas/14423
250 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
251 * i386-init.h: Regenerated.
252
3c892704
NC		 2532012-08-09 Nick Clifton <nickc@redhat.com>
254
255 * po/vi.po: Updated Vietnamese translation.
256
d7189fa5
RM		 2572012-08-07 Roland McGrath <mcgrathr@google.com>
258
259 * i386-dis.c (reg_table): Fill out REG_0F0D table with
260 AMD-reserved cases as "prefetch".
261 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
262 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
263 (reg_table): Use those under REG_0F18.
264 (mod_table): Add those cases as "nop/reserved".
265
4c692bc7
JB		 2662012-08-07 Jan Beulich <jbeulich@suse.com>
267
268 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
269
de882298
RM		 2702012-08-06 Roland McGrath <mcgrathr@google.com>
271
272 * i386-dis.c (print_insn): Print spaces between multiple excess
273 prefixes. Return actual number of excess prefixes consumed,
274 not always one.
275
276 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
277
7bb15c6f
RM		 2782012-08-06 Roland McGrath <mcgrathr@google.com>
279 Victor Khimenko <khim@google.com>
280 H.J. Lu <hongjiu.lu@intel.com>
281
282 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
283 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
284 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
285 (OP_E_register): Likewise.
286 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
287
3843081d
JBG		 2882012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
289
290 * configure.in: Formatting.
291 * configure: Regenerate.
292
48891606
AM		 2932012-08-01 Alan Modra <amodra@gmail.com>
294
295 * h8300-dis.c: Fix printf arg warnings.
296 * i960-dis.c: Likewise.
297 * mips-dis.c: Likewise.
298 * pdp11-dis.c: Likewise.
299 * sh-dis.c: Likewise.
300 * v850-dis.c: Likewise.
301 * configure.in: Formatting.
302 * configure: Regenerate.
303 * rl78-decode.c: Regenerate.
304 * po/POTFILES.in: Regenerate.
305
03f66e8a 3062012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 307 Catherine Moore <clm@codesourcery.com>
308 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 309
310 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
311 (DSP_VOLA): Likewise.
312 (D32, D33): Likewise.
313 (micromips_opcodes): Add DSP ASE instructions.
48891606 314 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 315 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
316
94948e64
JB		 3172012-07-31 Jan Beulich <jbeulich@suse.com>
318
319 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
320 instruction group. Mark as requiring AVX2.
321 * i386-tbl.h: Re-generate.
322
a6dc81d2
NC		 3232012-07-30 Nick Clifton <nickc@redhat.com>
324
325 * po/opcodes.pot: Updated template.
326 * po/es.po: Updated Spanish translation.
327 * po/fi.po: Updated Finnish translation.
328
c4dd807e
MF		 3292012-07-27 Mike Frysinger <vapier@gentoo.org>
330
331 * configure.in (BFD_VERSION): Run bfd/configure --version and
332 parse the output of that.
333 * configure: Regenerate.
334
03edbe3b
JL		 3352012-07-25 James Lemke <jwlemke@codesourcery.com>
336
337 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
338
63d08c68
NC		 3392012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
340 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 341
342 PR binutils/13135
343 * arm-dis.c: Add necessary casts for printing integer values.
344 Use %s when printing string values.
345 * hppa-dis.c: Likewise.
346 * m68k-dis.c: Likewise.
347 * microblaze-dis.c: Likewise.
348 * mips-dis.c: Likewise.
349 * sparc-dis.c: Likewise.
350
ff688e1f
L		 3512012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
352
353 PR binutils/14355
354 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
355 (VEX_LEN_0FXOP_08_CD): Likewise.
356 (VEX_LEN_0FXOP_08_CE): Likewise.
357 (VEX_LEN_0FXOP_08_CF): Likewise.
358 (VEX_LEN_0FXOP_08_EC): Likewise.
359 (VEX_LEN_0FXOP_08_ED): Likewise.
360 (VEX_LEN_0FXOP_08_EE): Likewise.
361 (VEX_LEN_0FXOP_08_EF): Likewise.
362 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
363 vpcomub, vpcomuw, vpcomud, vpcomuq.
364 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
365 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
366 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
367 VEX_LEN_0FXOP_08_EF.
368
e2e1fcde
L		 3692012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
370
371 * i386-dis.c (PREFIX_0F38F6): New.
372 (prefix_table): Add adcx, adox instructions.
373 (three_byte_table): Use PREFIX_0F38F6.
374 (mod_table): Add rdseed instruction.
375 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
376 (cpu_flags): Likewise.
377 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
378 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
379 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
380 prefetchw.
381 * i386-tbl.h: Regenerate.
382 * i386-init.h: Likewise.
383
8b99bf0b
TS		 3842012-07-05 Thomas Schwinge <thomas@codesourcery.com>
385
f4263ca2 386 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 387
416cf80a
SK		 3882012-07-05 Sean Keys <skeys@ipdatasys.com>
389
390 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 391 always be false due to overlapping operand masks.
392 * xgate-opc.c: Corrected 'com' opcode entry and
393 fixed spacing.
416cf80a 394
9fa0f14a
RM		 3952012-07-02 Roland McGrath <mcgrathr@google.com>
396
397 * i386-opc.tbl: Add RepPrefixOk to nop.
398 * i386-tbl.h: Regenerate.
399
4c6a93d3
NC		 4002012-06-28 Nick Clifton <nickc@redhat.com>
401
402 * po/vi.po: Updated Vietnamese translation.
403
29c048b6
RM		 4042012-06-22 Roland McGrath <mcgrathr@google.com>
405
fe13e45b
RM		 406 * i386-opc.tbl: Add RepPrefixOk to ret.
407 * i386-tbl.h: Regenerate.
408
29c048b6
RM		 409 * i386-opc.h (RepPrefixOk): New enum constant.
410 (i386_opcode_modifier): New bitfield 'repprefixok'.
411 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
412 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
413 instructions that have IsString.
414 * i386-tbl.h: Regenerate.
415
c7a8dbf9
AS		 4162012-06-11 Andreas Schwab <schwab@linux-m68k.org>
417
418 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
419 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
420 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
421 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
422 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
423 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
424 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
425 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
426 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
427
94caa966
AM		 4282012-05-19 Alan Modra <amodra@gmail.com>
429
430 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
431 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
432
5eb3690e
AM		 4332012-05-18 Alan Modra <amodra@gmail.com>
434
71fe7bab
AM		 435 * ia64-opc.c: Remove #include "ansidecl.h".
436 * z8kgen.c: Include sysdep.h first.
437
5eb3690e
AM		 438 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
439 * bfin-dis.c: Likewise.
440 * i860-dis.c: Likewise.
441 * ia64-dis.c: Likewise.
442 * ia64-gen.c: Likewise.
443 * m68hc11-dis.c: Likewise.
444 * mmix-dis.c: Likewise.
445 * msp430-dis.c: Likewise.
446 * or32-dis.c: Likewise.
447 * rl78-dis.c: Likewise.
448 * rx-dis.c: Likewise.
449 * tic4x-dis.c: Likewise.
450 * tilegx-opc.c: Likewise.
451 * tilepro-opc.c: Likewise.
452 * rx-decode.c: Regenerate.
453
a4ebc835
AM		 4542012-05-17 James Lemke <jwlemke@codesourcery.com>
455
456 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
457
98c76446
AM		 4582012-05-17 James Lemke <jwlemke@codesourcery.com>
459
460 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
461
df7b86aa
NC		 4622012-05-17 Daniel Richard G. <skunk@iskunk.org>
463 Nick Clifton <nickc@redhat.com>
464
465 PR 14072
466 * configure.in: Add check that sysdep.h has been included before
467 any system header files.
468 * configure: Regenerate.
469 * config.in: Regenerate.
470 * sysdep.h: Generate an error if included before config.h.
471 * alpha-opc.c: Include sysdep.h before any other header file.
472 * alpha-dis.c: Likewise.
473 * avr-dis.c: Likewise.
474 * cgen-opc.c: Likewise.
475 * cr16-dis.c: Likewise.
476 * cris-dis.c: Likewise.
477 * crx-dis.c: Likewise.
478 * d10v-dis.c: Likewise.
479 * d10v-opc.c: Likewise.
480 * d30v-dis.c: Likewise.
481 * d30v-opc.c: Likewise.
482 * h8500-dis.c: Likewise.
483 * i370-dis.c: Likewise.
484 * i370-opc.c: Likewise.
485 * m10200-dis.c: Likewise.
486 * m10300-dis.c: Likewise.
487 * micromips-opc.c: Likewise.
488 * mips-opc.c: Likewise.
489 * mips61-opc.c: Likewise.
490 * moxie-dis.c: Likewise.
491 * or32-opc.c: Likewise.
492 * pj-dis.c: Likewise.
493 * ppc-dis.c: Likewise.
494 * ppc-opc.c: Likewise.
495 * s390-dis.c: Likewise.
496 * sh-dis.c: Likewise.
497 * sh64-dis.c: Likewise.
498 * sparc-dis.c: Likewise.
499 * sparc-opc.c: Likewise.
500 * spu-dis.c: Likewise.
501 * tic30-dis.c: Likewise.
502 * tic54x-dis.c: Likewise.
503 * tic80-dis.c: Likewise.
504 * tic80-opc.c: Likewise.
505 * tilegx-dis.c: Likewise.
506 * tilepro-dis.c: Likewise.
507 * v850-dis.c: Likewise.
508 * v850-opc.c: Likewise.
509 * vax-dis.c: Likewise.
510 * w65-dis.c: Likewise.
511 * xgate-dis.c: Likewise.
512 * xtensa-dis.c: Likewise.
513 * rl78-decode.opc: Likewise.
514 * rl78-decode.c: Regenerate.
515 * rx-decode.opc: Likewise.
516 * rx-decode.c: Regenerate.
517
e1dad58d
AM		 5182012-05-17 Alan Modra <amodra@gmail.com>
519
520 * ppc_dis.c: Don't include elf/ppc.h.
521
101af531
NC		 5222012-05-16 Meador Inge <meadori@codesourcery.com>
523
524 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
525 to PUSH/POP {reg}.
526
6927f982
NC		 5272012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
528 Stephane Carrez <stcarrez@nerim.fr>
529
530 * configure.in: Add S12X and XGATE co-processor support to m68hc11
531 target.
532 * disassemble.c: Likewise.
533 * configure: Regenerate.
534 * m68hc11-dis.c: Make objdump output more consistent, use hex
535 instead of decimal and use 0x prefix for hex.
536 * m68hc11-opc.c: Add S12X and XGATE opcodes.
537
b9c361e0
JL		 5382012-05-14 James Lemke <jwlemke@codesourcery.com>
539
540 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
541 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
542 (vle_opcd_indices): New array.
543 (lookup_vle): New function.
544 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
545 (print_insn_powerpc): Likewise.
546 * ppc-opc.c: Likewise.
547
5482012-05-14 Catherine Moore <clm@codesourcery.com>
549 Maciej W. Rozycki <macro@codesourcery.com>
550 Rhonda Wittels <rhonda@codesourcery.com>
551 Nathan Froyd <froydnj@codesourcery.com>
552
553 * ppc-opc.c (insert_arx, extract_arx): New functions.
554 (insert_ary, extract_ary): New functions.
555 (insert_li20, extract_li20): New functions.
556 (insert_rx, extract_rx): New functions.
557 (insert_ry, extract_ry): New functions.
558 (insert_sci8, extract_sci8): New functions.
559 (insert_sci8n, extract_sci8n): New functions.
560 (insert_sd4h, extract_sd4h): New functions.
561 (insert_sd4w, extract_sd4w): New functions.
562 (insert_vlesi, extract_vlesi): New functions.
563 (insert_vlensi, extract_vlensi): New functions.
564 (insert_vleui, extract_vleui): New functions.
565 (insert_vleil, extract_vleil): New functions.
566 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
567 (BI16, BI32, BO32, B8): New.
568 (B15, B24, CRD32, CRS): New.
569 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
570 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
571 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
572 (SH6_MASK): Use PPC_OPSHIFT_INV.
573 (SI8, UI5, OIMM5, UI7, BO16): New.
574 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
575 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
576 (ALLOW8_SPRG): New.
577 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
578 (OPVUP, OPVUP_MASK OPVUP): New
579 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
580 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
581 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
582 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
583 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
584 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
585 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
586 (SE_IM5, SE_IM5_MASK): New.
587 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
588 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
589 (BO32DNZ, BO32DZ): New.
590 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
591 (PPCVLE): New.
592 (powerpc_opcodes): Add new VLE instructions. Update existing
593 instruction to include PPCVLE if supported.
594 * ppc-dis.c (ppc_opts): Add vle entry.
595 (get_powerpc_dialect): New function.
596 (powerpc_init_dialect): VLE support.
597 (print_insn_big_powerpc): Call get_powerpc_dialect.
598 (print_insn_little_powerpc): Likewise.
599 (operand_value_powerpc): Handle negative shift counts.
600 (print_insn_powerpc): Handle 2-byte instruction lengths.
601
208a4923
NC		 6022012-05-11 Daniel Richard G. <skunk@iskunk.org>
603
604 PR binutils/14028
605 * configure.in: Invoke ACX_HEADER_STRING.
606 * configure: Regenerate.
607 * config.in: Regenerate.
608 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
609 string.h and strings.h.
610
6750a3a7
NC		 6112012-05-11 Nick Clifton <nickc@redhat.com>
612
613 PR binutils/14006
614 * arm-dis.c (print_insn): Fix detection of instruction mode in
615 files containing multiple executable sections.
616
f6c1a2d5
NC		 6172012-05-03 Sean Keys <skeys@ipdatasys.com>
618
619 * Makefile.in, configure: regenerate
620 * disassemble.c (disassembler): Recognize ARCH_XGATE.
621 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
622 New functions.
623 * configure.in: Recognize xgate.
624 * xgate-dis.c, xgate-opc.c: New files for support of xgate
625 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
626 and opcode generation for xgate.
627
78e98aab
DD		 6282012-04-30 DJ Delorie <dj@redhat.com>
629
630 * rx-decode.opc (MOV): Do not sign-extend immediates which are
631 already the maximum bit size.
632 * rx-decode.c: Regenerate.
633
ec668d69
DM		 6342012-04-27 David S. Miller <davem@davemloft.net>
635
2e52845b
DM		 636 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
637 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
638
58004e23
DM		 639 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
640 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
641
698544e1
DM		 642 * sparc-opc.c (CBCOND): New define.
643 (CBCOND_XCC): Likewise.
644 (cbcond): New helper macro.
645 (sparc_opcodes): Add compare-and-branch instructions.
646
6cda1326
DM		 647 * sparc-dis.c (print_insn_sparc): Handle ')'.
648 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
649
ec668d69
DM		 650 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
651 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
652
2615994e
DM		 6532012-04-12 David S. Miller <davem@davemloft.net>
654
655 * sparc-dis.c (X_DISP10): Define.
656 (print_insn_sparc): Handle '='.
657
5de10af0
MF		 6582012-04-01 Mike Frysinger <vapier@gentoo.org>
659
660 * bfin-dis.c (fmtconst): Replace decimal handling with a single
661 sprintf call and the '*' field width.
662
55a36193
MK		 6632012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
664
665 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
666
d6688282
AM		 6672012-03-16 Alan Modra <amodra@gmail.com>
668
669 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
670 (powerpc_opcd_indices): Bump array size.
671 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
672 corresponding to unused opcodes to following entry.
673 (lookup_powerpc): New function, extracted and optimised from..
674 (print_insn_powerpc): ..here.
675
b240011a
AM		 6762012-03-15 Alan Modra <amodra@gmail.com>
677 James Lemke <jwlemke@codesourcery.com>
678
679 * disassemble.c (disassemble_init_for_target): Handle ppc init.
680 * ppc-dis.c (private): New var.
681 (powerpc_init_dialect): Don't return calloc failure, instead use
682 private.
683 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
684 (powerpc_opcd_indices): New array.
685 (disassemble_init_powerpc): New function.
686 (print_insn_big_powerpc): Don't init dialect here.
687 (print_insn_little_powerpc): Likewise.
688 (print_insn_powerpc): Start search using powerpc_opcd_indices.
689
aea77599
AM		 6902012-03-10 Edmar Wienskoski <edmar@freescale.com>
691
692 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
693 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
694 (PPCVEC2, PPCTMR, E6500): New short names.
695 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
696 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
697 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
698 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
699 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
700 optional operands on sync instruction for E6500 target.
701
5333187a
AK		 7022012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
703
704 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
705
a597d2d3
AM		 7062012-02-27 Alan Modra <amodra@gmail.com>
707
708 * mt-dis.c: Regenerate.
709
3f26eb3a
AM		 7102012-02-27 Alan Modra <amodra@gmail.com>
711
712 * v850-opc.c (extract_v8): Rearrange to make it obvious this
713 is the inverse of corresponding insert function.
714 (extract_d22, extract_u9, extract_r4): Likewise.
715 (extract_d9): Correct sign extension.
716 (extract_d16_15): Don't assume "long" is 32 bits, and don't
717 rely on implementation defined behaviour for shift right of
718 signed types.
719 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
720 (extract_d23): Likewise, and correct mask.
721
1f42f8b3
AM		 7222012-02-27 Alan Modra <amodra@gmail.com>
723
724 * crx-dis.c (print_arg): Mask constant to 32 bits.
725 * crx-opc.c (cst4_map): Use int array.
726
cdb06235
AM		 7272012-02-27 Alan Modra <amodra@gmail.com>
728
729 * arc-dis.c (BITS): Don't use shifts to mask off bits.
730 (FIELDD): Sign extend with xor,sub.
731
6f7be959
WL		 7322012-02-25 Walter Lee <walt@tilera.com>
733
734 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
735 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
736 TILEPRO_OPC_LW_TLS_SN.
737
82c2def5
L		 7382012-02-21 H.J. Lu <hongjiu.lu@intel.com>
739
740 * i386-opc.h (HLEPrefixNone): New.
741 (HLEPrefixLock): Likewise.
742 (HLEPrefixAny): Likewise.
743 (HLEPrefixRelease): Likewise.
744
42164a71
L		 7452012-02-08 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386-dis.c (HLE_Fixup1): New.
748 (HLE_Fixup2): Likewise.
749 (HLE_Fixup3): Likewise.
750 (Ebh1): Likewise.
751 (Evh1): Likewise.
752 (Ebh2): Likewise.
753 (Evh2): Likewise.
754 (Ebh3): Likewise.
755 (Evh3): Likewise.
756 (MOD_C6_REG_7): Likewise.
757 (MOD_C7_REG_7): Likewise.
758 (RM_C6_REG_7): Likewise.
759 (RM_C7_REG_7): Likewise.
760 (XACQUIRE_PREFIX): Likewise.
761 (XRELEASE_PREFIX): Likewise.
762 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
763 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
764 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
765 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
766 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
767 MOD_C6_REG_7 and MOD_C7_REG_7.
768 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
769 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
770 xtest.
771 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
772 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
773
774 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
775 CPU_RTM_FLAGS.
776 (cpu_flags): Add CpuHLE and CpuRTM.
777 (opcode_modifiers): Add HLEPrefixOk.
778
779 * i386-opc.h (CpuHLE): New.
780 (CpuRTM): Likewise.
781 (HLEPrefixOk): Likewise.
782 (i386_cpu_flags): Add cpuhle and cpurtm.
783 (i386_opcode_modifier): Add hleprefixok.
784
785 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
786 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
787 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
788 operand. Add xacquire, xrelease, xabort, xbegin, xend and
789 xtest.
790 * i386-init.h: Regenerated.
791 * i386-tbl.h: Likewise.
792
21abe33a
DD		 7932012-01-24 DJ Delorie <dj@redhat.com>
794
795 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
796 * rl78-decode.c: Regenerate.
797
e20cc039
AM		 7982012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
799
800 PR binutils/10173
801 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
802
e143d25c
AS		 8032012-01-17 Andreas Schwab <schwab@linux-m68k.org>
804
805 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
806 register and move them after pmove with PSR/PCSR register.
807
8729a6f6
L		 8082012-01-13 H.J. Lu <hongjiu.lu@intel.com>
809
810 * i386-dis.c (mod_table): Add vmfunc.
811
812 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
813 (cpu_flags): CpuVMFUNC.
814
815 * i386-opc.h (CpuVMFUNC): New.
816 (i386_cpu_flags): Add cpuvmfunc.
817
818 * i386-opc.tbl: Add vmfunc.
819 * i386-init.h: Regenerated.
820 * i386-tbl.h: Likewise.
5011093d 821
23e1d329 822For older changes see ChangeLog-2011
252b5132
RH		 823\f
824Local Variables:
2f6d2f85
NC		 825mode: change-log
826left-margin: 8
827fill-column: 74
252b5132
RH		 828version-control: never
829End:
GDB Binutils - Deliverables
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