[deliverable/binutils-gdb.git] / opcodes / a29k-dis.c

/* Instruction printing code for the AMD 29000
   Copyright (C) 1990 Free Software Foundation, Inc.
   Contributed by Cygnus Support.  Written by Jim Kingdon.

This file is part of GDB.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */

#include "dis-asm.h"
#include "opcode/a29k.h"

/* Print a symbolic representation of a general-purpose
   register number NUM on STREAM.
   NUM is a number as found in the instruction, not as found in
   debugging symbols; it must be in the range 0-255.  */
static void
print_general (num, info)
     int num;
     struct disassemble_info *info;
{
  if (num < 128)
    (*info->fprintf_func) (info->stream, "gr%d", num);
  else
    (*info->fprintf_func) (info->stream, "lr%d", num - 128);
}

/* Like print_general but a special-purpose register.
   
   The mnemonics used by the AMD assembler are not quite the same
   as the ones in the User's Manual.  We use the ones that the
   assembler uses.  */
static void
print_special (num, info)
     int num;
     struct disassemble_info *info;
{
  /* Register names of registers 0-SPEC0_NUM-1.  */
  static char *spec0_names[] = {
    "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
    "pc0", "pc1", "pc2", "mmu", "lru"
    };
#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))

  /* Register names of registers 128-128+SPEC128_NUM-1.  */
  static char *spec128_names[] = {
    "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
    };
#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))

  /* Register names of registers 160-160+SPEC160_NUM-1.  */
  static char *spec160_names[] = {
    "fpe", "inte", "fps", "sr163", "exop"
    };
#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))

  if (num < SPEC0_NUM)
    (*info->fprintf_func) (info->stream, spec0_names[num]);
  else if (num >= 128 && num < 128 + SPEC128_NUM)
    (*info->fprintf_func) (info->stream, spec128_names[num-128]);
  else if (num >= 160 && num < 160 + SPEC160_NUM)
    (*info->fprintf_func) (info->stream, spec160_names[num-160]);
  else
    (*info->fprintf_func) (info->stream, "sr%d", num);
}

/* Is an instruction with OPCODE a delayed branch?  */
static int
is_delayed_branch (opcode)
     int opcode;
{
  return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1
	  || opcode == 0xa4 || opcode == 0xa5
	  || opcode == 0xb4 || opcode == 0xb5
	  || opcode == 0xc4 || opcode == 0xc0
	  || opcode == 0xac || opcode == 0xad
	  || opcode == 0xcc);
}

/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}.  */
static void
find_bytes_big (insn, insn0, insn8, insn16, insn24)
     char *insn;
     unsigned char *insn0;
     unsigned char *insn8;
     unsigned char *insn16;
     unsigned char *insn24;
{
  *insn24 = insn[0];
  *insn16 = insn[1];
  *insn8  = insn[2];
  *insn0  = insn[3];
}

static void
find_bytes_little (insn, insn0, insn8, insn16, insn24)
     char *insn;
     unsigned char *insn0;
     unsigned char *insn8;
     unsigned char *insn16;
     unsigned char *insn24;
{
  *insn24 = insn[3];
  *insn16 = insn[2];
  *insn8 = insn[1];
  *insn0 = insn[0];
}

typedef (*find_byte_func_type)
     PARAMS ((char *, unsigned char *, unsigned char *,
	      unsigned char *, unsigned char *));

/* Print one instruction from MEMADDR on INFO->STREAM.
   Return the size of the instruction (always 4 on a29k).  */

static int
print_insn (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  /* The raw instruction.  */
  char insn[4];

  /* The four bytes of the instruction.  */
  unsigned char insn24, insn16, insn8, insn0;

  find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data;

  struct a29k_opcode CONST * opcode;

  {
    int status =
      (*info->read_memory_func) (memaddr, (bfd_byte *) &insn[0], 4, info);
    if (status != 0)
      {
	(*info->memory_error_func) (status, memaddr, info);
	return -1;
      }
  }

  (*find_byte_func) (insn, &insn0, &insn8, &insn16, &insn24);

  /* Handle the nop (aseq 0x40,gr1,gr1) specially */
  if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) {
    (*info->fprintf_func) (info->stream,"nop");
    return 4;
  }

  /* The opcode is always in insn24.  */
  for (opcode = &a29k_opcodes[0];
       opcode < &a29k_opcodes[num_opcodes];
       ++opcode)
    {
      if ((insn24<<24) == opcode->opcode)
	{
	  char *s;
	  
	  (*info->fprintf_func) (info->stream, "%s ", opcode->name);
	  for (s = opcode->args; *s != '\0'; ++s)
	    {
	      switch (*s)
		{
		case 'a':
		  print_general (insn8, info);
		  break;
		  
		case 'b':
		  print_general (insn0, info);
		  break;

		case 'c':
		  print_general (insn16, info);
		  break;

		case 'i':
		  (*info->fprintf_func) (info->stream, "%d", insn0);
		  break;

		case 'x':
		  (*info->fprintf_func) (info->stream, "%d", (insn16 << 8) + insn0);
		  break;

		case 'h':
		  /* This used to be %x for binutils.  */
		  (*info->fprintf_func) (info->stream, "0x%x",
				    (insn16 << 24) + (insn0 << 16));
		  break;

		case 'X':
		  (*info->fprintf_func) (info->stream, "%d",
				    ((insn16 << 8) + insn0) | 0xffff0000);
		  break;

		case 'P':
		  /* This output looks just like absolute addressing, but
		     maybe that's OK (it's what the GDB m68k and EBMON
		     a29k disassemblers do).  */
		  /* All the shifting is to sign-extend it.  p*/
		  (*info->print_address_func)
		    (memaddr +
		     (((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14),
		     info);
		  break;

		case 'A':
		  (*info->print_address_func)
		    ((insn16 << 10) + (insn0 << 2), info);
		  break;

		case 'e':
		  (*info->fprintf_func) (info->stream, "%d", insn16 >> 7);
		  break;

		case 'n':
		  (*info->fprintf_func) (info->stream, "0x%x", insn16 & 0x7f);
		  break;

		case 'v':
		  (*info->fprintf_func) (info->stream, "0x%x", insn16);
		  break;

		case 's':
		  print_special (insn8, info);
		  break;

		case 'u':
		  (*info->fprintf_func) (info->stream, "%d", insn0 >> 7);
		  break;

		case 'r':
		  (*info->fprintf_func) (info->stream, "%d", (insn0 >> 4) & 7);
		  break;

		case 'd':
		  (*info->fprintf_func) (info->stream, "%d", (insn0 >> 2) & 3);
		  break;

		case 'f':
		  (*info->fprintf_func) (info->stream, "%d", insn0 & 3);
		  break;

		case 'F':
		  (*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15);
		  break;

		case 'C':
		  (*info->fprintf_func) (info->stream, "%d", insn16 & 3);
		  break;

		default:
		  (*info->fprintf_func) (info->stream, "%c", *s);
		}
	    }

	  /* Now we look for a const,consth pair of instructions,
	     in which case we try to print the symbolic address.  */
	  if (insn24 == 2)  /* consth */
	    {
	      int errcode;
	      char prev_insn[4];
	      unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24;
	      
	      errcode = (*info->read_memory_func) (memaddr - 4,
						   (bfd_byte *) &prev_insn[0],
						   4,
						   info);
	      if (errcode == 0)
		{
		  /* If it is a delayed branch, we need to look at the
		     instruction before the delayed brach to handle
		     things like
		     
		     const _foo
		     call _printf
		     consth _foo
		     */
		  (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
				     &prev_insn16, &prev_insn24);
		  if (is_delayed_branch (prev_insn24))
		    {
		      errcode = (*info->read_memory_func)
			(memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info);
		      (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
					 &prev_insn16, &prev_insn24);
		    }
		}
		  
	      /* If there was a problem reading memory, then assume
		 the previous instruction was not const.  */
	      if (errcode == 0)
		{
		  /* Is it const to the same register?  */
		  if (prev_insn24 == 3
		      && prev_insn8 == insn8)
		    {
		      (*info->fprintf_func) (info->stream, "\t; ");
		      (*info->print_address_func)
			(((insn16 << 24) + (insn0 << 16)
			  + (prev_insn16 << 8) + (prev_insn0)),
			 info);
		    }
		}
	    }

	  return 4;
	}
    }
  /* This used to be %8x for binutils.  */
  (*info->fprintf_func)
    (info->stream, ".word 0x%08x",
     (insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0);
  return 4;
}

/* Disassemble an big-endian a29k instruction.  */
int
print_insn_big_a29k (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  info->private_data = (PTR) find_bytes_big;
  return print_insn (memaddr, info);
}

/* Disassemble a little-endian a29k instruction.  */
int
print_insn_little_a29k (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  info->private_data = (PTR) find_bytes_little;
  return print_insn (memaddr, info);
}
Commit	Line	Data
2013f9b4 SC	1	/* Instruction printing code for the AMD 29000
	2	Copyright (C) 1990 Free Software Foundation, Inc.
	3	Contributed by Cygnus Support. Written by Jim Kingdon.
	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
720b3aed JK	9	the Free Software Foundation; either version 2 of the License, or
720b3aed JK	10	(at your option) any later version.
2013f9b4 SC	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
720b3aed JK	18	along with this program; if not, write to the Free Software
720b3aed JK	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
2013f9b4	20
720b3aed JK	21	#include "dis-asm.h"
720b3aed JK	22	#include "opcode/a29k.h"
2013f9b4 SC	23
	24	/* Print a symbolic representation of a general-purpose
	25	register number NUM on STREAM.
	26	NUM is a number as found in the instruction, not as found in
	27	debugging symbols; it must be in the range 0-255. */
	28	static void
720b3aed	29	print_general (num, info)
2013f9b4	30	int num;
720b3aed	31	struct disassemble_info *info;
2013f9b4 SC	32	{
2013f9b4 SC	33	if (num < 128)
720b3aed	34	(*info->fprintf_func) (info->stream, "gr%d", num);
2013f9b4	35	else
720b3aed	36	(*info->fprintf_func) (info->stream, "lr%d", num - 128);
2013f9b4 SC	37	}
	38
	39	/* Like print_general but a special-purpose register.
	40
	41	The mnemonics used by the AMD assembler are not quite the same
	42	as the ones in the User's Manual. We use the ones that the
	43	assembler uses. */
	44	static void
720b3aed	45	print_special (num, info)
2013f9b4	46	int num;
720b3aed	47	struct disassemble_info *info;
2013f9b4 SC	48	{
	49	/* Register names of registers 0-SPEC0_NUM-1. */
	50	static char *spec0_names[] = {
	51	"vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
	52	"pc0", "pc1", "pc2", "mmu", "lru"
	53	};
	54	#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
	55
	56	/* Register names of registers 128-128+SPEC128_NUM-1. */
	57	static char *spec128_names[] = {
	58	"ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
	59	};
	60	#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
	61
	62	/* Register names of registers 160-160+SPEC160_NUM-1. */
	63	static char *spec160_names[] = {
	64	"fpe", "inte", "fps", "sr163", "exop"
	65	};
	66	#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
	67
	68	if (num < SPEC0_NUM)
720b3aed	69	(*info->fprintf_func) (info->stream, spec0_names[num]);
2013f9b4	70	else if (num >= 128 && num < 128 + SPEC128_NUM)
720b3aed	71	(*info->fprintf_func) (info->stream, spec128_names[num-128]);
2013f9b4	72	else if (num >= 160 && num < 160 + SPEC160_NUM)
720b3aed	73	(*info->fprintf_func) (info->stream, spec160_names[num-160]);
2013f9b4	74	else
720b3aed	75	(*info->fprintf_func) (info->stream, "sr%d", num);
2013f9b4 SC	76	}
	77
	78	/* Is an instruction with OPCODE a delayed branch? */
	79	static int
	80	is_delayed_branch (opcode)
	81	int opcode;
	82	{
	83	return (opcode == 0xa8 \|\| opcode == 0xa9 \|\| opcode == 0xa0 \|\| opcode == 0xa1
	84	\|\| opcode == 0xa4 \|\| opcode == 0xa5
	85	\|\| opcode == 0xb4 \|\| opcode == 0xb5
	86	\|\| opcode == 0xc4 \|\| opcode == 0xc0
	87	\|\| opcode == 0xac \|\| opcode == 0xad
	88	\|\| opcode == 0xcc);
	89	}
	90
720b3aed	91	/* Now find the four bytes of INSN and put them in INSN{0,8,16,24}. /
2013f9b4	92	static void
720b3aed	93	find_bytes_big (insn, insn0, insn8, insn16, insn24)
2013f9b4 SC	94	char *insn;
	95	unsigned char *insn0;
	96	unsigned char *insn8;
	97	unsigned char *insn16;
	98	unsigned char *insn24;
	99	{
2013f9b4 SC	100	*insn24 = insn[0];
	101	*insn16 = insn[1];
	102	*insn8 = insn[2];
	103	*insn0 = insn[3];
720b3aed JK	104	}
	105
	106	static void
	107	find_bytes_little (insn, insn0, insn8, insn16, insn24)
	108	char *insn;
	109	unsigned char *insn0;
	110	unsigned char *insn8;
	111	unsigned char *insn16;
	112	unsigned char *insn24;
	113	{
2013f9b4 SC	114	*insn24 = insn[3];
	115	*insn16 = insn[2];
	116	*insn8 = insn[1];
	117	*insn0 = insn[0];
2013f9b4 SC	118	}
2013f9b4 SC	119
720b3aed JK	120	typedef (*find_byte_func_type)
	121	PARAMS ((char , unsigned char , unsigned char *,
	122	unsigned char , unsigned char ));
	123
4b2febd3	124	/* Print one instruction from MEMADDR on INFO->STREAM.
720b3aed	125	Return the size of the instruction (always 4 on a29k). */
4b2febd3	126
720b3aed JK	127	static int
720b3aed JK	128	print_insn (memaddr, info)
2013f9b4	129	bfd_vma memaddr;
720b3aed	130	struct disassemble_info *info;
2013f9b4 SC	131	{
	132	/* The raw instruction. */
	133	char insn[4];
	134
	135	/* The four bytes of the instruction. */
	136	unsigned char insn24, insn16, insn8, insn0;
2013f9b4	137
720b3aed JK	138	find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data;
720b3aed JK	139
e9aff87e	140	struct a29k_opcode CONST * opcode;
2013f9b4	141
720b3aed JK	142	{
720b3aed JK	143	int status =
0e57a495	144	(info->read_memory_func) (memaddr, (bfd_byte ) &insn[0], 4, info);
720b3aed JK	145	if (status != 0)
	146	{
	147	(*info->memory_error_func) (status, memaddr, info);
	148	return -1;
	149	}
	150	}
	151
	152	(*find_byte_func) (insn, &insn0, &insn8, &insn16, &insn24);
2013f9b4 SC	153
	154	/* Handle the nop (aseq 0x40,gr1,gr1) specially */
	155	if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) {
720b3aed	156	(*info->fprintf_func) (info->stream,"nop");
2013f9b4 SC	157	return 4;
	158	}
	159
2013f9b4	160	/* The opcode is always in insn24. */
720b3aed JK	161	for (opcode = &a29k_opcodes[0];
720b3aed JK	162	opcode < &a29k_opcodes[num_opcodes];
2013f9b4 SC	163	++opcode)
2013f9b4 SC	164	{
720b3aed	165	if ((insn24<<24) == opcode->opcode)
2013f9b4 SC	166	{
	167	char *s;
	168
720b3aed	169	(*info->fprintf_func) (info->stream, "%s ", opcode->name);
2013f9b4 SC	170	for (s = opcode->args; *s != '\0'; ++s)
	171	{
	172	switch (*s)
	173	{
	174	case 'a':
720b3aed	175	print_general (insn8, info);
2013f9b4 SC	176	break;
	177
	178	case 'b':
720b3aed	179	print_general (insn0, info);
2013f9b4 SC	180	break;
	181
	182	case 'c':
720b3aed	183	print_general (insn16, info);
2013f9b4 SC	184	break;
	185
	186	case 'i':
720b3aed	187	(*info->fprintf_func) (info->stream, "%d", insn0);
2013f9b4 SC	188	break;
	189
	190	case 'x':
720b3aed	191	(*info->fprintf_func) (info->stream, "%d", (insn16 << 8) + insn0);
2013f9b4 SC	192	break;
	193
	194	case 'h':
720b3aed JK	195	/* This used to be %x for binutils. */
720b3aed JK	196	(*info->fprintf_func) (info->stream, "0x%x",
2013f9b4 SC	197	(insn16 << 24) + (insn0 << 16));
	198	break;
	199
	200	case 'X':
720b3aed	201	(*info->fprintf_func) (info->stream, "%d",
2013f9b4 SC	202	((insn16 << 8) + insn0) \| 0xffff0000);
	203	break;
	204
	205	case 'P':
	206	/* This output looks just like absolute addressing, but
720b3aed JK	207	maybe that's OK (it's what the GDB m68k and EBMON
720b3aed JK	208	a29k disassemblers do). */
2013f9b4	209	/* All the shifting is to sign-extend it. p*/
720b3aed	210	(*info->print_address_func)
2013f9b4 SC	211	(memaddr +
2013f9b4 SC	212	(((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14),
720b3aed	213	info);
2013f9b4 SC	214	break;
	215
	216	case 'A':
720b3aed JK	217	(*info->print_address_func)
720b3aed JK	218	((insn16 << 10) + (insn0 << 2), info);
2013f9b4 SC	219	break;
	220
	221	case 'e':
720b3aed	222	(*info->fprintf_func) (info->stream, "%d", insn16 >> 7);
2013f9b4 SC	223	break;
	224
	225	case 'n':
720b3aed	226	(*info->fprintf_func) (info->stream, "0x%x", insn16 & 0x7f);
2013f9b4 SC	227	break;
	228
	229	case 'v':
720b3aed	230	(*info->fprintf_func) (info->stream, "0x%x", insn16);
2013f9b4 SC	231	break;
	232
	233	case 's':
720b3aed	234	print_special (insn8, info);
2013f9b4 SC	235	break;
	236
	237	case 'u':
720b3aed	238	(*info->fprintf_func) (info->stream, "%d", insn0 >> 7);
2013f9b4 SC	239	break;
	240
	241	case 'r':
720b3aed	242	(*info->fprintf_func) (info->stream, "%d", (insn0 >> 4) & 7);
2013f9b4 SC	243	break;
	244
	245	case 'd':
720b3aed	246	(*info->fprintf_func) (info->stream, "%d", (insn0 >> 2) & 3);
2013f9b4 SC	247	break;
	248
	249	case 'f':
720b3aed	250	(*info->fprintf_func) (info->stream, "%d", insn0 & 3);
2013f9b4 SC	251	break;
	252
	253	case 'F':
720b3aed	254	(*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15);
2013f9b4 SC	255	break;
	256
	257	case 'C':
720b3aed	258	(*info->fprintf_func) (info->stream, "%d", insn16 & 3);
2013f9b4 SC	259	break;
	260
	261	default:
720b3aed	262	(info->fprintf_func) (info->stream, "%c", s);
2013f9b4 SC	263	}
	264	}
	265
	266	/* Now we look for a const,consth pair of instructions,
	267	in which case we try to print the symbolic address. */
	268	if (insn24 == 2) /* consth */
	269	{
	270	int errcode;
	271	char prev_insn[4];
	272	unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24;
	273
720b3aed	274	errcode = (*info->read_memory_func) (memaddr - 4,
0e57a495	275	(bfd_byte *) &prev_insn[0],
720b3aed JK	276	4,
720b3aed JK	277	info);
2013f9b4 SC	278	if (errcode == 0)
	279	{
	280	/* If it is a delayed branch, we need to look at the
	281	instruction before the delayed brach to handle
	282	things like
	283
	284	const _foo
	285	call _printf
	286	consth _foo
	287	*/
720b3aed JK	288	(*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
720b3aed JK	289	&prev_insn16, &prev_insn24);
2013f9b4 SC	290	if (is_delayed_branch (prev_insn24))
2013f9b4 SC	291	{
720b3aed	292	errcode = (*info->read_memory_func)
0e57a495	293	(memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info);
720b3aed JK	294	(*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
720b3aed JK	295	&prev_insn16, &prev_insn24);
2013f9b4 SC	296	}
	297	}
	298
	299	/* If there was a problem reading memory, then assume
	300	the previous instruction was not const. */
	301	if (errcode == 0)
	302	{
	303	/* Is it const to the same register? */
	304	if (prev_insn24 == 3
	305	&& prev_insn8 == insn8)
	306	{
720b3aed JK	307	(*info->fprintf_func) (info->stream, "\t; ");
	308	(*info->print_address_func)
	309	(((insn16 << 24) + (insn0 << 16)
	310	+ (prev_insn16 << 8) + (prev_insn0)),
	311	info);
2013f9b4 SC	312	}
	313	}
	314	}
	315
	316	return 4;
	317	}
	318	}
720b3aed JK	319	/* This used to be %8x for binutils. */
720b3aed JK	320	(*info->fprintf_func)
d75a406d	321	(info->stream, ".word 0x%08x",
720b3aed	322	(insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0);
2013f9b4 SC	323	return 4;
2013f9b4 SC	324	}
720b3aed JK	325
	326	/* Disassemble an big-endian a29k instruction. */
	327	int
	328	print_insn_big_a29k (memaddr, info)
	329	bfd_vma memaddr;
	330	struct disassemble_info *info;
	331	{
	332	info->private_data = (PTR) find_bytes_big;
	333	return print_insn (memaddr, info);
	334	}
	335
	336	/* Disassemble a little-endian a29k instruction. */
	337	int
	338	print_insn_little_a29k (memaddr, info)
	339	bfd_vma memaddr;
	340	struct disassemble_info *info;
	341	{
	342	info->private_data = (PTR) find_bytes_little;
	343	return print_insn (memaddr, info);
	344	}