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a06ea964 | 1 | /* aarch64-dis.c -- AArch64 disassembler. |
219d1afa | 2 | Copyright (C) 2009-2018 Free Software Foundation, Inc. |
a06ea964 NC |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "sysdep.h" | |
22 | #include "bfd_stdint.h" | |
6394c606 | 23 | #include "disassemble.h" |
a06ea964 NC |
24 | #include "libiberty.h" |
25 | #include "opintl.h" | |
26 | #include "aarch64-dis.h" | |
a06ea964 | 27 | #include "elf-bfd.h" |
a06ea964 NC |
28 | |
29 | #define ERR_OK 0 | |
30 | #define ERR_UND -1 | |
31 | #define ERR_UNP -3 | |
32 | #define ERR_NYI -5 | |
33 | ||
34 | #define INSNLEN 4 | |
35 | ||
36 | /* Cached mapping symbol state. */ | |
37 | enum map_type | |
38 | { | |
39 | MAP_INSN, | |
40 | MAP_DATA | |
41 | }; | |
42 | ||
43 | static enum map_type last_type; | |
44 | static int last_mapping_sym = -1; | |
45 | static bfd_vma last_mapping_addr = 0; | |
46 | ||
47 | /* Other options */ | |
48 | static int no_aliases = 0; /* If set disassemble as most general inst. */ | |
7d02540a TC |
49 | \fstatic int no_notes = 1; /* If set do not print disassemble notes in the |
50 | output as comments. */ | |
a06ea964 NC |
51 | |
52 | static void | |
53 | set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) | |
54 | { | |
55 | } | |
56 | ||
57 | static void | |
58 | parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED) | |
59 | { | |
60 | /* Try to match options that are simple flags */ | |
61 | if (CONST_STRNEQ (option, "no-aliases")) | |
62 | { | |
63 | no_aliases = 1; | |
64 | return; | |
65 | } | |
66 | ||
67 | if (CONST_STRNEQ (option, "aliases")) | |
68 | { | |
69 | no_aliases = 0; | |
70 | return; | |
71 | } | |
72 | ||
7d02540a TC |
73 | if (CONST_STRNEQ (option, "no-notes")) |
74 | { | |
75 | no_notes = 1; | |
76 | return; | |
77 | } | |
78 | ||
79 | if (CONST_STRNEQ (option, "notes")) | |
80 | { | |
81 | no_notes = 0; | |
82 | return; | |
83 | } | |
84 | ||
a06ea964 NC |
85 | #ifdef DEBUG_AARCH64 |
86 | if (CONST_STRNEQ (option, "debug_dump")) | |
87 | { | |
88 | debug_dump = 1; | |
89 | return; | |
90 | } | |
91 | #endif /* DEBUG_AARCH64 */ | |
92 | ||
93 | /* Invalid option. */ | |
a6743a54 | 94 | opcodes_error_handler (_("unrecognised disassembler option: %s"), option); |
a06ea964 NC |
95 | } |
96 | ||
97 | static void | |
98 | parse_aarch64_dis_options (const char *options) | |
99 | { | |
100 | const char *option_end; | |
101 | ||
102 | if (options == NULL) | |
103 | return; | |
104 | ||
105 | while (*options != '\0') | |
106 | { | |
107 | /* Skip empty options. */ | |
108 | if (*options == ',') | |
109 | { | |
110 | options++; | |
111 | continue; | |
112 | } | |
113 | ||
114 | /* We know that *options is neither NUL or a comma. */ | |
115 | option_end = options + 1; | |
116 | while (*option_end != ',' && *option_end != '\0') | |
117 | option_end++; | |
118 | ||
119 | parse_aarch64_dis_option (options, option_end - options); | |
120 | ||
121 | /* Go on to the next one. If option_end points to a comma, it | |
122 | will be skipped above. */ | |
123 | options = option_end; | |
124 | } | |
125 | } | |
126 | \f | |
127 | /* Functions doing the instruction disassembling. */ | |
128 | ||
129 | /* The unnamed arguments consist of the number of fields and information about | |
130 | these fields where the VALUE will be extracted from CODE and returned. | |
131 | MASK can be zero or the base mask of the opcode. | |
132 | ||
133 | N.B. the fields are required to be in such an order than the most signficant | |
134 | field for VALUE comes the first, e.g. the <index> in | |
135 | SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
9aff4b7a | 136 | is encoded in H:L:M in some cases, the fields H:L:M should be passed in |
a06ea964 NC |
137 | the order of H, L, M. */ |
138 | ||
c0890d26 | 139 | aarch64_insn |
a06ea964 NC |
140 | extract_fields (aarch64_insn code, aarch64_insn mask, ...) |
141 | { | |
142 | uint32_t num; | |
143 | const aarch64_field *field; | |
144 | enum aarch64_field_kind kind; | |
145 | va_list va; | |
146 | ||
147 | va_start (va, mask); | |
148 | num = va_arg (va, uint32_t); | |
149 | assert (num <= 5); | |
150 | aarch64_insn value = 0x0; | |
151 | while (num--) | |
152 | { | |
153 | kind = va_arg (va, enum aarch64_field_kind); | |
154 | field = &fields[kind]; | |
155 | value <<= field->width; | |
156 | value |= extract_field (kind, code, mask); | |
157 | } | |
158 | return value; | |
159 | } | |
160 | ||
b5464a68 RS |
161 | /* Extract the value of all fields in SELF->fields from instruction CODE. |
162 | The least significant bit comes from the final field. */ | |
163 | ||
164 | static aarch64_insn | |
165 | extract_all_fields (const aarch64_operand *self, aarch64_insn code) | |
166 | { | |
167 | aarch64_insn value; | |
168 | unsigned int i; | |
169 | enum aarch64_field_kind kind; | |
170 | ||
171 | value = 0; | |
172 | for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) | |
173 | { | |
174 | kind = self->fields[i]; | |
175 | value <<= fields[kind].width; | |
176 | value |= extract_field (kind, code, 0); | |
177 | } | |
178 | return value; | |
179 | } | |
180 | ||
a06ea964 NC |
181 | /* Sign-extend bit I of VALUE. */ |
182 | static inline int32_t | |
183 | sign_extend (aarch64_insn value, unsigned i) | |
184 | { | |
185 | uint32_t ret = value; | |
186 | ||
187 | assert (i < 32); | |
188 | if ((value >> i) & 0x1) | |
189 | { | |
190 | uint32_t val = (uint32_t)(-1) << i; | |
191 | ret = ret | val; | |
192 | } | |
193 | return (int32_t) ret; | |
194 | } | |
195 | ||
196 | /* N.B. the following inline helpfer functions create a dependency on the | |
197 | order of operand qualifier enumerators. */ | |
198 | ||
199 | /* Given VALUE, return qualifier for a general purpose register. */ | |
200 | static inline enum aarch64_opnd_qualifier | |
201 | get_greg_qualifier_from_value (aarch64_insn value) | |
202 | { | |
203 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value; | |
204 | assert (value <= 0x1 | |
205 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
206 | return qualifier; | |
207 | } | |
208 | ||
3067d3b9 MW |
209 | /* Given VALUE, return qualifier for a vector register. This does not support |
210 | decoding instructions that accept the 2H vector type. */ | |
211 | ||
a06ea964 NC |
212 | static inline enum aarch64_opnd_qualifier |
213 | get_vreg_qualifier_from_value (aarch64_insn value) | |
214 | { | |
215 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value; | |
216 | ||
3067d3b9 MW |
217 | /* Instructions using vector type 2H should not call this function. Skip over |
218 | the 2H qualifier. */ | |
219 | if (qualifier >= AARCH64_OPND_QLF_V_2H) | |
220 | qualifier += 1; | |
221 | ||
a06ea964 NC |
222 | assert (value <= 0x8 |
223 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
224 | return qualifier; | |
225 | } | |
226 | ||
227 | /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */ | |
228 | static inline enum aarch64_opnd_qualifier | |
229 | get_sreg_qualifier_from_value (aarch64_insn value) | |
230 | { | |
231 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value; | |
232 | ||
233 | assert (value <= 0x4 | |
234 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
235 | return qualifier; | |
236 | } | |
237 | ||
238 | /* Given the instruction in *INST which is probably half way through the | |
239 | decoding and our caller wants to know the expected qualifier for operand | |
240 | I. Return such a qualifier if we can establish it; otherwise return | |
241 | AARCH64_OPND_QLF_NIL. */ | |
242 | ||
243 | static aarch64_opnd_qualifier_t | |
244 | get_expected_qualifier (const aarch64_inst *inst, int i) | |
245 | { | |
246 | aarch64_opnd_qualifier_seq_t qualifiers; | |
247 | /* Should not be called if the qualifier is known. */ | |
248 | assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); | |
249 | if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, | |
250 | i, qualifiers)) | |
251 | return qualifiers[i]; | |
252 | else | |
253 | return AARCH64_OPND_QLF_NIL; | |
254 | } | |
255 | ||
256 | /* Operand extractors. */ | |
257 | ||
561a72d4 | 258 | bfd_boolean |
a06ea964 NC |
259 | aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, |
260 | const aarch64_insn code, | |
561a72d4 TC |
261 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
262 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
263 | { |
264 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
561a72d4 | 265 | return TRUE; |
a06ea964 NC |
266 | } |
267 | ||
561a72d4 | 268 | bfd_boolean |
ee804238 JW |
269 | aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, |
270 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
561a72d4 TC |
271 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
272 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
ee804238 JW |
273 | { |
274 | assert (info->idx == 1 | |
275 | || info->idx ==3); | |
276 | info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; | |
561a72d4 | 277 | return TRUE; |
ee804238 JW |
278 | } |
279 | ||
a06ea964 | 280 | /* e.g. IC <ic_op>{, <Xt>}. */ |
561a72d4 | 281 | bfd_boolean |
a06ea964 NC |
282 | aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, |
283 | const aarch64_insn code, | |
561a72d4 TC |
284 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
285 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
286 | { |
287 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
288 | assert (info->idx == 1 | |
289 | && (aarch64_get_operand_class (inst->operands[0].type) | |
290 | == AARCH64_OPND_CLASS_SYSTEM)); | |
291 | /* This will make the constraint checking happy and more importantly will | |
292 | help the disassembler determine whether this operand is optional or | |
293 | not. */ | |
ea2deeec | 294 | info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op); |
a06ea964 | 295 | |
561a72d4 | 296 | return TRUE; |
a06ea964 NC |
297 | } |
298 | ||
299 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
561a72d4 | 300 | bfd_boolean |
a06ea964 NC |
301 | aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, |
302 | const aarch64_insn code, | |
561a72d4 TC |
303 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
304 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
305 | { |
306 | /* regno */ | |
307 | info->reglane.regno = extract_field (self->fields[0], code, | |
308 | inst->opcode->mask); | |
309 | ||
310 | /* Index and/or type. */ | |
311 | if (inst->opcode->iclass == asisdone | |
312 | || inst->opcode->iclass == asimdins) | |
313 | { | |
314 | if (info->type == AARCH64_OPND_En | |
315 | && inst->opcode->operands[0] == AARCH64_OPND_Ed) | |
316 | { | |
317 | unsigned shift; | |
318 | /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ | |
319 | assert (info->idx == 1); /* Vn */ | |
320 | aarch64_insn value = extract_field (FLD_imm4, code, 0); | |
321 | /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ | |
322 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
323 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
324 | info->reglane.index = value >> shift; | |
325 | } | |
326 | else | |
327 | { | |
328 | /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>]. | |
329 | imm5<3:0> <V> | |
330 | 0000 RESERVED | |
331 | xxx1 B | |
332 | xx10 H | |
333 | x100 S | |
334 | 1000 D */ | |
335 | int pos = -1; | |
336 | aarch64_insn value = extract_field (FLD_imm5, code, 0); | |
337 | while (++pos <= 3 && (value & 0x1) == 0) | |
338 | value >>= 1; | |
339 | if (pos > 3) | |
561a72d4 | 340 | return FALSE; |
a06ea964 NC |
341 | info->qualifier = get_sreg_qualifier_from_value (pos); |
342 | info->reglane.index = (unsigned) (value >> 1); | |
343 | } | |
344 | } | |
65a55fbb TC |
345 | else if (inst->opcode->iclass == dotproduct) |
346 | { | |
347 | /* Need information in other operand(s) to help decoding. */ | |
348 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
349 | switch (info->qualifier) | |
350 | { | |
00c2093f | 351 | case AARCH64_OPND_QLF_S_4B: |
65a55fbb TC |
352 | /* L:H */ |
353 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
354 | info->reglane.regno &= 0x1f; | |
355 | break; | |
356 | default: | |
561a72d4 | 357 | return FALSE; |
65a55fbb TC |
358 | } |
359 | } | |
f42f1a1d TC |
360 | else if (inst->opcode->iclass == cryptosm3) |
361 | { | |
362 | /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */ | |
363 | info->reglane.index = extract_field (FLD_SM3_imm2, code, 0); | |
364 | } | |
a06ea964 NC |
365 | else |
366 | { | |
367 | /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
368 | or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
369 | ||
370 | /* Need information in other operand(s) to help decoding. */ | |
371 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
372 | switch (info->qualifier) | |
373 | { | |
374 | case AARCH64_OPND_QLF_S_H: | |
375 | /* h:l:m */ | |
376 | info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, | |
377 | FLD_M); | |
378 | info->reglane.regno &= 0xf; | |
379 | break; | |
380 | case AARCH64_OPND_QLF_S_S: | |
381 | /* h:l */ | |
382 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
383 | break; | |
384 | case AARCH64_OPND_QLF_S_D: | |
385 | /* H */ | |
386 | info->reglane.index = extract_field (FLD_H, code, 0); | |
387 | break; | |
388 | default: | |
561a72d4 | 389 | return FALSE; |
a06ea964 | 390 | } |
c2c4ff8d SN |
391 | |
392 | if (inst->opcode->op == OP_FCMLA_ELEM) | |
393 | { | |
394 | /* Complex operand takes two elements. */ | |
395 | if (info->reglane.index & 1) | |
561a72d4 | 396 | return FALSE; |
c2c4ff8d SN |
397 | info->reglane.index /= 2; |
398 | } | |
a06ea964 NC |
399 | } |
400 | ||
561a72d4 | 401 | return TRUE; |
a06ea964 NC |
402 | } |
403 | ||
561a72d4 | 404 | bfd_boolean |
a06ea964 NC |
405 | aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, |
406 | const aarch64_insn code, | |
561a72d4 TC |
407 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
408 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
409 | { |
410 | /* R */ | |
411 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
412 | /* len */ | |
413 | info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1; | |
561a72d4 | 414 | return TRUE; |
a06ea964 NC |
415 | } |
416 | ||
417 | /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */ | |
561a72d4 | 418 | bfd_boolean |
a06ea964 NC |
419 | aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
420 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
421 | const aarch64_inst *inst, |
422 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
423 | { |
424 | aarch64_insn value; | |
425 | /* Number of elements in each structure to be loaded/stored. */ | |
426 | unsigned expected_num = get_opcode_dependent_value (inst->opcode); | |
427 | ||
428 | struct | |
429 | { | |
430 | unsigned is_reserved; | |
431 | unsigned num_regs; | |
432 | unsigned num_elements; | |
433 | } data [] = | |
434 | { {0, 4, 4}, | |
435 | {1, 4, 4}, | |
436 | {0, 4, 1}, | |
437 | {0, 4, 2}, | |
438 | {0, 3, 3}, | |
439 | {1, 3, 3}, | |
440 | {0, 3, 1}, | |
441 | {0, 1, 1}, | |
442 | {0, 2, 2}, | |
443 | {1, 2, 2}, | |
444 | {0, 2, 1}, | |
445 | }; | |
446 | ||
447 | /* Rt */ | |
448 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
449 | /* opcode */ | |
450 | value = extract_field (FLD_opcode, code, 0); | |
cd3ea7c6 NC |
451 | /* PR 21595: Check for a bogus value. */ |
452 | if (value >= ARRAY_SIZE (data)) | |
561a72d4 | 453 | return FALSE; |
a06ea964 | 454 | if (expected_num != data[value].num_elements || data[value].is_reserved) |
561a72d4 | 455 | return FALSE; |
a06ea964 NC |
456 | info->reglist.num_regs = data[value].num_regs; |
457 | ||
561a72d4 | 458 | return TRUE; |
a06ea964 NC |
459 | } |
460 | ||
461 | /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all | |
462 | lanes instructions. */ | |
561a72d4 | 463 | bfd_boolean |
a06ea964 NC |
464 | aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, |
465 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
466 | const aarch64_inst *inst, |
467 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
468 | { |
469 | aarch64_insn value; | |
470 | ||
471 | /* Rt */ | |
472 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
473 | /* S */ | |
474 | value = extract_field (FLD_S, code, 0); | |
475 | ||
476 | /* Number of registers is equal to the number of elements in | |
477 | each structure to be loaded/stored. */ | |
478 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
479 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
480 | ||
481 | /* Except when it is LD1R. */ | |
482 | if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) | |
483 | info->reglist.num_regs = 2; | |
484 | ||
561a72d4 | 485 | return TRUE; |
a06ea964 NC |
486 | } |
487 | ||
488 | /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD | |
489 | load/store single element instructions. */ | |
561a72d4 | 490 | bfd_boolean |
a06ea964 NC |
491 | aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
492 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
493 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
494 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
495 | { |
496 | aarch64_field field = {0, 0}; | |
497 | aarch64_insn QSsize; /* fields Q:S:size. */ | |
498 | aarch64_insn opcodeh2; /* opcode<2:1> */ | |
499 | ||
500 | /* Rt */ | |
501 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
502 | ||
503 | /* Decode the index, opcode<2:1> and size. */ | |
504 | gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); | |
505 | opcodeh2 = extract_field_2 (&field, code, 0); | |
506 | QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); | |
507 | switch (opcodeh2) | |
508 | { | |
509 | case 0x0: | |
510 | info->qualifier = AARCH64_OPND_QLF_S_B; | |
511 | /* Index encoded in "Q:S:size". */ | |
512 | info->reglist.index = QSsize; | |
513 | break; | |
514 | case 0x1: | |
76dfed02 YZ |
515 | if (QSsize & 0x1) |
516 | /* UND. */ | |
561a72d4 | 517 | return FALSE; |
a06ea964 NC |
518 | info->qualifier = AARCH64_OPND_QLF_S_H; |
519 | /* Index encoded in "Q:S:size<1>". */ | |
520 | info->reglist.index = QSsize >> 1; | |
521 | break; | |
522 | case 0x2: | |
76dfed02 YZ |
523 | if ((QSsize >> 1) & 0x1) |
524 | /* UND. */ | |
561a72d4 | 525 | return FALSE; |
a06ea964 NC |
526 | if ((QSsize & 0x1) == 0) |
527 | { | |
528 | info->qualifier = AARCH64_OPND_QLF_S_S; | |
529 | /* Index encoded in "Q:S". */ | |
530 | info->reglist.index = QSsize >> 2; | |
531 | } | |
532 | else | |
533 | { | |
a06ea964 NC |
534 | if (extract_field (FLD_S, code, 0)) |
535 | /* UND */ | |
561a72d4 | 536 | return FALSE; |
76dfed02 YZ |
537 | info->qualifier = AARCH64_OPND_QLF_S_D; |
538 | /* Index encoded in "Q". */ | |
539 | info->reglist.index = QSsize >> 3; | |
a06ea964 NC |
540 | } |
541 | break; | |
542 | default: | |
561a72d4 | 543 | return FALSE; |
a06ea964 NC |
544 | } |
545 | ||
546 | info->reglist.has_index = 1; | |
547 | info->reglist.num_regs = 0; | |
548 | /* Number of registers is equal to the number of elements in | |
549 | each structure to be loaded/stored. */ | |
550 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
551 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
552 | ||
561a72d4 | 553 | return TRUE; |
a06ea964 NC |
554 | } |
555 | ||
556 | /* Decode fields immh:immb and/or Q for e.g. | |
557 | SSHR <Vd>.<T>, <Vn>.<T>, #<shift> | |
558 | or SSHR <V><d>, <V><n>, #<shift>. */ | |
559 | ||
561a72d4 | 560 | bfd_boolean |
a06ea964 NC |
561 | aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, |
562 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
563 | const aarch64_inst *inst, |
564 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
565 | { |
566 | int pos; | |
567 | aarch64_insn Q, imm, immh; | |
568 | enum aarch64_insn_class iclass = inst->opcode->iclass; | |
569 | ||
570 | immh = extract_field (FLD_immh, code, 0); | |
571 | if (immh == 0) | |
561a72d4 | 572 | return FALSE; |
a06ea964 NC |
573 | imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); |
574 | pos = 4; | |
575 | /* Get highest set bit in immh. */ | |
576 | while (--pos >= 0 && (immh & 0x8) == 0) | |
577 | immh <<= 1; | |
578 | ||
579 | assert ((iclass == asimdshf || iclass == asisdshf) | |
580 | && (info->type == AARCH64_OPND_IMM_VLSR | |
581 | || info->type == AARCH64_OPND_IMM_VLSL)); | |
582 | ||
583 | if (iclass == asimdshf) | |
584 | { | |
585 | Q = extract_field (FLD_Q, code, 0); | |
586 | /* immh Q <T> | |
587 | 0000 x SEE AdvSIMD modified immediate | |
588 | 0001 0 8B | |
589 | 0001 1 16B | |
590 | 001x 0 4H | |
591 | 001x 1 8H | |
592 | 01xx 0 2S | |
593 | 01xx 1 4S | |
594 | 1xxx 0 RESERVED | |
595 | 1xxx 1 2D */ | |
596 | info->qualifier = | |
597 | get_vreg_qualifier_from_value ((pos << 1) | (int) Q); | |
598 | } | |
599 | else | |
600 | info->qualifier = get_sreg_qualifier_from_value (pos); | |
601 | ||
602 | if (info->type == AARCH64_OPND_IMM_VLSR) | |
603 | /* immh <shift> | |
604 | 0000 SEE AdvSIMD modified immediate | |
605 | 0001 (16-UInt(immh:immb)) | |
606 | 001x (32-UInt(immh:immb)) | |
607 | 01xx (64-UInt(immh:immb)) | |
608 | 1xxx (128-UInt(immh:immb)) */ | |
609 | info->imm.value = (16 << pos) - imm; | |
610 | else | |
611 | /* immh:immb | |
612 | immh <shift> | |
613 | 0000 SEE AdvSIMD modified immediate | |
614 | 0001 (UInt(immh:immb)-8) | |
615 | 001x (UInt(immh:immb)-16) | |
616 | 01xx (UInt(immh:immb)-32) | |
617 | 1xxx (UInt(immh:immb)-64) */ | |
618 | info->imm.value = imm - (8 << pos); | |
619 | ||
561a72d4 | 620 | return TRUE; |
a06ea964 NC |
621 | } |
622 | ||
623 | /* Decode shift immediate for e.g. sshr (imm). */ | |
561a72d4 | 624 | bfd_boolean |
a06ea964 NC |
625 | aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, |
626 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
627 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
628 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
629 | { |
630 | int64_t imm; | |
631 | aarch64_insn val; | |
632 | val = extract_field (FLD_size, code, 0); | |
633 | switch (val) | |
634 | { | |
635 | case 0: imm = 8; break; | |
636 | case 1: imm = 16; break; | |
637 | case 2: imm = 32; break; | |
561a72d4 | 638 | default: return FALSE; |
a06ea964 NC |
639 | } |
640 | info->imm.value = imm; | |
561a72d4 | 641 | return TRUE; |
a06ea964 NC |
642 | } |
643 | ||
644 | /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. | |
645 | value in the field(s) will be extracted as unsigned immediate value. */ | |
561a72d4 | 646 | bfd_boolean |
a06ea964 NC |
647 | aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, |
648 | const aarch64_insn code, | |
561a72d4 TC |
649 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
650 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
651 | { |
652 | int64_t imm; | |
a06ea964 | 653 | |
b5464a68 | 654 | imm = extract_all_fields (self, code); |
a06ea964 | 655 | |
a06ea964 NC |
656 | if (operand_need_sign_extension (self)) |
657 | imm = sign_extend (imm, get_operand_fields_width (self) - 1); | |
658 | ||
659 | if (operand_need_shift_by_two (self)) | |
660 | imm <<= 2; | |
661 | ||
662 | if (info->type == AARCH64_OPND_ADDR_ADRP) | |
663 | imm <<= 12; | |
664 | ||
665 | info->imm.value = imm; | |
561a72d4 | 666 | return TRUE; |
a06ea964 NC |
667 | } |
668 | ||
669 | /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ | |
561a72d4 | 670 | bfd_boolean |
a06ea964 NC |
671 | aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, |
672 | const aarch64_insn code, | |
561a72d4 TC |
673 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
674 | aarch64_operand_error *errors) | |
a06ea964 | 675 | { |
561a72d4 | 676 | aarch64_ext_imm (self, info, code, inst, errors); |
a06ea964 NC |
677 | info->shifter.kind = AARCH64_MOD_LSL; |
678 | info->shifter.amount = extract_field (FLD_hw, code, 0) << 4; | |
561a72d4 | 679 | return TRUE; |
a06ea964 NC |
680 | } |
681 | ||
682 | /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g. | |
683 | MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ | |
561a72d4 | 684 | bfd_boolean |
a06ea964 NC |
685 | aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, |
686 | aarch64_opnd_info *info, | |
687 | const aarch64_insn code, | |
561a72d4 TC |
688 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
689 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
690 | { |
691 | uint64_t imm; | |
692 | enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; | |
693 | aarch64_field field = {0, 0}; | |
694 | ||
695 | assert (info->idx == 1); | |
696 | ||
697 | if (info->type == AARCH64_OPND_SIMD_FPIMM) | |
698 | info->imm.is_fp = 1; | |
699 | ||
700 | /* a:b:c:d:e:f:g:h */ | |
701 | imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh); | |
702 | if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8) | |
703 | { | |
704 | /* Either MOVI <Dd>, #<imm> | |
705 | or MOVI <Vd>.2D, #<imm>. | |
706 | <imm> is a 64-bit immediate | |
707 | 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', | |
708 | encoded in "a:b:c:d:e:f:g:h". */ | |
709 | int i; | |
710 | unsigned abcdefgh = imm; | |
711 | for (imm = 0ull, i = 0; i < 8; i++) | |
712 | if (((abcdefgh >> i) & 0x1) != 0) | |
713 | imm |= 0xffull << (8 * i); | |
714 | } | |
715 | info->imm.value = imm; | |
716 | ||
717 | /* cmode */ | |
718 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
719 | switch (info->qualifier) | |
720 | { | |
721 | case AARCH64_OPND_QLF_NIL: | |
722 | /* no shift */ | |
723 | info->shifter.kind = AARCH64_MOD_NONE; | |
724 | return 1; | |
725 | case AARCH64_OPND_QLF_LSL: | |
726 | /* shift zeros */ | |
727 | info->shifter.kind = AARCH64_MOD_LSL; | |
728 | switch (aarch64_get_qualifier_esize (opnd0_qualifier)) | |
729 | { | |
730 | case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ | |
731 | case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ | |
f5555712 | 732 | case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ |
561a72d4 | 733 | default: assert (0); return FALSE; |
a06ea964 NC |
734 | } |
735 | /* 00: 0; 01: 8; 10:16; 11:24. */ | |
736 | info->shifter.amount = extract_field_2 (&field, code, 0) << 3; | |
737 | break; | |
738 | case AARCH64_OPND_QLF_MSL: | |
739 | /* shift ones */ | |
740 | info->shifter.kind = AARCH64_MOD_MSL; | |
741 | gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ | |
742 | info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; | |
743 | break; | |
744 | default: | |
745 | assert (0); | |
561a72d4 | 746 | return FALSE; |
a06ea964 NC |
747 | } |
748 | ||
561a72d4 | 749 | return TRUE; |
a06ea964 NC |
750 | } |
751 | ||
aa2aa4c6 | 752 | /* Decode an 8-bit floating-point immediate. */ |
561a72d4 | 753 | bfd_boolean |
aa2aa4c6 RS |
754 | aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, |
755 | const aarch64_insn code, | |
561a72d4 TC |
756 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
757 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
aa2aa4c6 RS |
758 | { |
759 | info->imm.value = extract_all_fields (self, code); | |
760 | info->imm.is_fp = 1; | |
561a72d4 | 761 | return TRUE; |
aa2aa4c6 RS |
762 | } |
763 | ||
582e12bf | 764 | /* Decode a 1-bit rotate immediate (#90 or #270). */ |
561a72d4 | 765 | bfd_boolean |
582e12bf RS |
766 | aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info, |
767 | const aarch64_insn code, | |
561a72d4 TC |
768 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
769 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
c2c4ff8d SN |
770 | { |
771 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
582e12bf RS |
772 | assert (rot < 2U); |
773 | info->imm.value = rot * 180 + 90; | |
561a72d4 | 774 | return TRUE; |
582e12bf | 775 | } |
c2c4ff8d | 776 | |
582e12bf | 777 | /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */ |
561a72d4 | 778 | bfd_boolean |
582e12bf RS |
779 | aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info, |
780 | const aarch64_insn code, | |
561a72d4 TC |
781 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
782 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
783 | { |
784 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
785 | assert (rot < 4U); | |
c2c4ff8d | 786 | info->imm.value = rot * 90; |
561a72d4 | 787 | return TRUE; |
c2c4ff8d SN |
788 | } |
789 | ||
a06ea964 | 790 | /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ |
561a72d4 | 791 | bfd_boolean |
a06ea964 NC |
792 | aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, |
793 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
794 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
795 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
796 | { |
797 | info->imm.value = 64- extract_field (FLD_scale, code, 0); | |
561a72d4 | 798 | return TRUE; |
a06ea964 NC |
799 | } |
800 | ||
801 | /* Decode arithmetic immediate for e.g. | |
802 | SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ | |
561a72d4 | 803 | bfd_boolean |
a06ea964 NC |
804 | aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, |
805 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
806 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
807 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
808 | { |
809 | aarch64_insn value; | |
810 | ||
811 | info->shifter.kind = AARCH64_MOD_LSL; | |
812 | /* shift */ | |
813 | value = extract_field (FLD_shift, code, 0); | |
814 | if (value >= 2) | |
561a72d4 | 815 | return FALSE; |
a06ea964 NC |
816 | info->shifter.amount = value ? 12 : 0; |
817 | /* imm12 (unsigned) */ | |
818 | info->imm.value = extract_field (FLD_imm12, code, 0); | |
819 | ||
561a72d4 | 820 | return TRUE; |
a06ea964 NC |
821 | } |
822 | ||
e950b345 RS |
823 | /* Return true if VALUE is a valid logical immediate encoding, storing the |
824 | decoded value in *RESULT if so. ESIZE is the number of bytes in the | |
825 | decoded immediate. */ | |
561a72d4 | 826 | static bfd_boolean |
e950b345 | 827 | decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) |
a06ea964 NC |
828 | { |
829 | uint64_t imm, mask; | |
a06ea964 NC |
830 | uint32_t N, R, S; |
831 | unsigned simd_size; | |
a06ea964 NC |
832 | |
833 | /* value is N:immr:imms. */ | |
834 | S = value & 0x3f; | |
835 | R = (value >> 6) & 0x3f; | |
836 | N = (value >> 12) & 0x1; | |
837 | ||
a06ea964 NC |
838 | /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R |
839 | (in other words, right rotated by R), then replicated. */ | |
840 | if (N != 0) | |
841 | { | |
842 | simd_size = 64; | |
843 | mask = 0xffffffffffffffffull; | |
844 | } | |
845 | else | |
846 | { | |
847 | switch (S) | |
848 | { | |
849 | case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break; | |
850 | case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break; | |
851 | case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; | |
852 | case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; | |
853 | case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; | |
561a72d4 | 854 | default: return FALSE; |
a06ea964 NC |
855 | } |
856 | mask = (1ull << simd_size) - 1; | |
857 | /* Top bits are IGNORED. */ | |
858 | R &= simd_size - 1; | |
859 | } | |
e950b345 RS |
860 | |
861 | if (simd_size > esize * 8) | |
561a72d4 | 862 | return FALSE; |
e950b345 | 863 | |
a06ea964 NC |
864 | /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ |
865 | if (S == simd_size - 1) | |
561a72d4 | 866 | return FALSE; |
a06ea964 NC |
867 | /* S+1 consecutive bits to 1. */ |
868 | /* NOTE: S can't be 63 due to detection above. */ | |
869 | imm = (1ull << (S + 1)) - 1; | |
870 | /* Rotate to the left by simd_size - R. */ | |
871 | if (R != 0) | |
872 | imm = ((imm << (simd_size - R)) & mask) | (imm >> R); | |
873 | /* Replicate the value according to SIMD size. */ | |
874 | switch (simd_size) | |
875 | { | |
876 | case 2: imm = (imm << 2) | imm; | |
1a0670f3 | 877 | /* Fall through. */ |
a06ea964 | 878 | case 4: imm = (imm << 4) | imm; |
1a0670f3 | 879 | /* Fall through. */ |
a06ea964 | 880 | case 8: imm = (imm << 8) | imm; |
1a0670f3 | 881 | /* Fall through. */ |
a06ea964 | 882 | case 16: imm = (imm << 16) | imm; |
1a0670f3 | 883 | /* Fall through. */ |
a06ea964 | 884 | case 32: imm = (imm << 32) | imm; |
1a0670f3 | 885 | /* Fall through. */ |
a06ea964 NC |
886 | case 64: break; |
887 | default: assert (0); return 0; | |
888 | } | |
889 | ||
e950b345 RS |
890 | *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); |
891 | ||
561a72d4 | 892 | return TRUE; |
e950b345 RS |
893 | } |
894 | ||
895 | /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */ | |
561a72d4 | 896 | bfd_boolean |
e950b345 RS |
897 | aarch64_ext_limm (const aarch64_operand *self, |
898 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
899 | const aarch64_inst *inst, |
900 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
e950b345 RS |
901 | { |
902 | uint32_t esize; | |
903 | aarch64_insn value; | |
904 | ||
905 | value = extract_fields (code, 0, 3, self->fields[0], self->fields[1], | |
906 | self->fields[2]); | |
907 | esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
908 | return decode_limm (esize, value, &info->imm.value); | |
909 | } | |
a06ea964 | 910 | |
e950b345 | 911 | /* Decode a logical immediate for the BIC alias of AND (etc.). */ |
561a72d4 | 912 | bfd_boolean |
e950b345 RS |
913 | aarch64_ext_inv_limm (const aarch64_operand *self, |
914 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
915 | const aarch64_inst *inst, |
916 | aarch64_operand_error *errors) | |
e950b345 | 917 | { |
561a72d4 TC |
918 | if (!aarch64_ext_limm (self, info, code, inst, errors)) |
919 | return FALSE; | |
e950b345 | 920 | info->imm.value = ~info->imm.value; |
561a72d4 | 921 | return TRUE; |
a06ea964 NC |
922 | } |
923 | ||
924 | /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] | |
925 | or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ | |
561a72d4 | 926 | bfd_boolean |
a06ea964 NC |
927 | aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, |
928 | aarch64_opnd_info *info, | |
561a72d4 TC |
929 | const aarch64_insn code, const aarch64_inst *inst, |
930 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
931 | { |
932 | aarch64_insn value; | |
933 | ||
934 | /* Rt */ | |
935 | info->reg.regno = extract_field (FLD_Rt, code, 0); | |
936 | ||
937 | /* size */ | |
938 | value = extract_field (FLD_ldst_size, code, 0); | |
939 | if (inst->opcode->iclass == ldstpair_indexed | |
940 | || inst->opcode->iclass == ldstnapair_offs | |
941 | || inst->opcode->iclass == ldstpair_off | |
942 | || inst->opcode->iclass == loadlit) | |
943 | { | |
944 | enum aarch64_opnd_qualifier qualifier; | |
945 | switch (value) | |
946 | { | |
947 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
948 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
949 | case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; | |
561a72d4 | 950 | default: return FALSE; |
a06ea964 NC |
951 | } |
952 | info->qualifier = qualifier; | |
953 | } | |
954 | else | |
955 | { | |
956 | /* opc1:size */ | |
957 | value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); | |
958 | if (value > 0x4) | |
561a72d4 | 959 | return FALSE; |
a06ea964 NC |
960 | info->qualifier = get_sreg_qualifier_from_value (value); |
961 | } | |
962 | ||
561a72d4 | 963 | return TRUE; |
a06ea964 NC |
964 | } |
965 | ||
966 | /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
561a72d4 | 967 | bfd_boolean |
a06ea964 NC |
968 | aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, |
969 | aarch64_opnd_info *info, | |
970 | aarch64_insn code, | |
561a72d4 TC |
971 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
972 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
973 | { |
974 | /* Rn */ | |
975 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
561a72d4 | 976 | return TRUE; |
a06ea964 NC |
977 | } |
978 | ||
f42f1a1d TC |
979 | /* Decode the address operand for e.g. |
980 | stlur <Xt>, [<Xn|SP>{, <amount>}]. */ | |
561a72d4 | 981 | bfd_boolean |
f42f1a1d TC |
982 | aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, |
983 | aarch64_opnd_info *info, | |
561a72d4 TC |
984 | aarch64_insn code, const aarch64_inst *inst, |
985 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f42f1a1d TC |
986 | { |
987 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
988 | ||
989 | /* Rn */ | |
990 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
991 | ||
992 | /* simm9 */ | |
993 | aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]); | |
994 | info->addr.offset.imm = sign_extend (imm, 8); | |
995 | if (extract_field (self->fields[2], code, 0) == 1) { | |
996 | info->addr.writeback = 1; | |
997 | info->addr.preind = 1; | |
998 | } | |
561a72d4 | 999 | return TRUE; |
f42f1a1d TC |
1000 | } |
1001 | ||
a06ea964 NC |
1002 | /* Decode the address operand for e.g. |
1003 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1004 | bfd_boolean |
a06ea964 NC |
1005 | aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1006 | aarch64_opnd_info *info, | |
561a72d4 TC |
1007 | aarch64_insn code, const aarch64_inst *inst, |
1008 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1009 | { |
1010 | aarch64_insn S, value; | |
1011 | ||
1012 | /* Rn */ | |
1013 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1014 | /* Rm */ | |
1015 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1016 | /* option */ | |
1017 | value = extract_field (FLD_option, code, 0); | |
1018 | info->shifter.kind = | |
1019 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1020 | /* Fix-up the shifter kind; although the table-driven approach is | |
1021 | efficient, it is slightly inflexible, thus needing this fix-up. */ | |
1022 | if (info->shifter.kind == AARCH64_MOD_UXTX) | |
1023 | info->shifter.kind = AARCH64_MOD_LSL; | |
1024 | /* S */ | |
1025 | S = extract_field (FLD_S, code, 0); | |
1026 | if (S == 0) | |
1027 | { | |
1028 | info->shifter.amount = 0; | |
1029 | info->shifter.amount_present = 0; | |
1030 | } | |
1031 | else | |
1032 | { | |
1033 | int size; | |
1034 | /* Need information in other operand(s) to help achieve the decoding | |
1035 | from 'S' field. */ | |
1036 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1037 | /* Get the size of the data element that is accessed, which may be | |
1038 | different from that of the source register size, e.g. in strb/ldrb. */ | |
1039 | size = aarch64_get_qualifier_esize (info->qualifier); | |
1040 | info->shifter.amount = get_logsz (size); | |
1041 | info->shifter.amount_present = 1; | |
1042 | } | |
1043 | ||
561a72d4 | 1044 | return TRUE; |
a06ea964 NC |
1045 | } |
1046 | ||
1047 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */ | |
561a72d4 | 1048 | bfd_boolean |
a06ea964 | 1049 | aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, |
561a72d4 TC |
1050 | aarch64_insn code, const aarch64_inst *inst, |
1051 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1052 | { |
1053 | aarch64_insn imm; | |
1054 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1055 | ||
1056 | /* Rn */ | |
1057 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1058 | /* simm (imm9 or imm7) */ | |
1059 | imm = extract_field (self->fields[0], code, 0); | |
1060 | info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1); | |
1061 | if (self->fields[0] == FLD_imm7) | |
1062 | /* scaled immediate in ld/st pair instructions. */ | |
1063 | info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); | |
1064 | /* qualifier */ | |
1065 | if (inst->opcode->iclass == ldst_unscaled | |
1066 | || inst->opcode->iclass == ldstnapair_offs | |
1067 | || inst->opcode->iclass == ldstpair_off | |
1068 | || inst->opcode->iclass == ldst_unpriv) | |
1069 | info->addr.writeback = 0; | |
1070 | else | |
1071 | { | |
1072 | /* pre/post- index */ | |
1073 | info->addr.writeback = 1; | |
1074 | if (extract_field (self->fields[1], code, 0) == 1) | |
1075 | info->addr.preind = 1; | |
1076 | else | |
1077 | info->addr.postind = 1; | |
1078 | } | |
1079 | ||
561a72d4 | 1080 | return TRUE; |
a06ea964 NC |
1081 | } |
1082 | ||
1083 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */ | |
561a72d4 | 1084 | bfd_boolean |
a06ea964 NC |
1085 | aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, |
1086 | aarch64_insn code, | |
561a72d4 TC |
1087 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1088 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1089 | { |
1090 | int shift; | |
1091 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1092 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
1093 | /* Rn */ | |
1094 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1095 | /* uimm12 */ | |
1096 | info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; | |
561a72d4 | 1097 | return TRUE; |
a06ea964 NC |
1098 | } |
1099 | ||
3f06e550 | 1100 | /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ |
561a72d4 | 1101 | bfd_boolean |
3f06e550 SN |
1102 | aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, |
1103 | aarch64_insn code, | |
561a72d4 TC |
1104 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1105 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
3f06e550 SN |
1106 | { |
1107 | aarch64_insn imm; | |
1108 | ||
1109 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1110 | /* Rn */ | |
1111 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1112 | /* simm10 */ | |
1113 | imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]); | |
1114 | info->addr.offset.imm = sign_extend (imm, 9) << 3; | |
1115 | if (extract_field (self->fields[3], code, 0) == 1) { | |
1116 | info->addr.writeback = 1; | |
1117 | info->addr.preind = 1; | |
1118 | } | |
561a72d4 | 1119 | return TRUE; |
3f06e550 SN |
1120 | } |
1121 | ||
a06ea964 NC |
1122 | /* Decode the address operand for e.g. |
1123 | LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ | |
561a72d4 | 1124 | bfd_boolean |
a06ea964 NC |
1125 | aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1126 | aarch64_opnd_info *info, | |
561a72d4 TC |
1127 | aarch64_insn code, const aarch64_inst *inst, |
1128 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1129 | { |
1130 | /* The opcode dependent area stores the number of elements in | |
1131 | each structure to be loaded/stored. */ | |
1132 | int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; | |
1133 | ||
1134 | /* Rn */ | |
1135 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1136 | /* Rm | #<amount> */ | |
1137 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1138 | if (info->addr.offset.regno == 31) | |
1139 | { | |
1140 | if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) | |
1141 | /* Special handling of loading single structure to all lane. */ | |
1142 | info->addr.offset.imm = (is_ld1r ? 1 | |
1143 | : inst->operands[0].reglist.num_regs) | |
1144 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
1145 | else | |
1146 | info->addr.offset.imm = inst->operands[0].reglist.num_regs | |
1147 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier) | |
1148 | * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); | |
1149 | } | |
1150 | else | |
1151 | info->addr.offset.is_reg = 1; | |
1152 | info->addr.writeback = 1; | |
1153 | ||
561a72d4 | 1154 | return TRUE; |
a06ea964 NC |
1155 | } |
1156 | ||
1157 | /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ | |
561a72d4 | 1158 | bfd_boolean |
a06ea964 NC |
1159 | aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1160 | aarch64_opnd_info *info, | |
561a72d4 TC |
1161 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1162 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1163 | { |
1164 | aarch64_insn value; | |
1165 | /* cond */ | |
1166 | value = extract_field (FLD_cond, code, 0); | |
1167 | info->cond = get_cond_from_value (value); | |
561a72d4 | 1168 | return TRUE; |
a06ea964 NC |
1169 | } |
1170 | ||
1171 | /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */ | |
561a72d4 | 1172 | bfd_boolean |
a06ea964 NC |
1173 | aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1174 | aarch64_opnd_info *info, | |
1175 | aarch64_insn code, | |
561a72d4 TC |
1176 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1177 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1178 | { |
1179 | /* op0:op1:CRn:CRm:op2 */ | |
561a72d4 TC |
1180 | info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, |
1181 | FLD_CRm, FLD_op2); | |
f9830ec1 TC |
1182 | info->sysreg.flags = 0; |
1183 | ||
1184 | /* If a system instruction, check which restrictions should be on the register | |
1185 | value during decoding, these will be enforced then. */ | |
1186 | if (inst->opcode->iclass == ic_system) | |
1187 | { | |
1188 | /* Check to see if it's read-only, else check if it's write only. | |
1189 | if it's both or unspecified don't care. */ | |
1190 | if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ) | |
1191 | info->sysreg.flags = F_REG_READ; | |
1192 | else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) | |
1193 | == F_SYS_WRITE) | |
1194 | info->sysreg.flags = F_REG_WRITE; | |
1195 | } | |
1196 | ||
1197 | return TRUE; | |
a06ea964 NC |
1198 | } |
1199 | ||
1200 | /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ | |
561a72d4 | 1201 | bfd_boolean |
a06ea964 NC |
1202 | aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1203 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1204 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1205 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1206 | { |
1207 | int i; | |
1208 | /* op1:op2 */ | |
1209 | info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); | |
1210 | for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) | |
1211 | if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) | |
561a72d4 | 1212 | return TRUE; |
a06ea964 | 1213 | /* Reserved value in <pstatefield>. */ |
561a72d4 | 1214 | return FALSE; |
a06ea964 NC |
1215 | } |
1216 | ||
1217 | /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ | |
561a72d4 | 1218 | bfd_boolean |
a06ea964 NC |
1219 | aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1220 | aarch64_opnd_info *info, | |
1221 | aarch64_insn code, | |
561a72d4 TC |
1222 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1223 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1224 | { |
1225 | int i; | |
1226 | aarch64_insn value; | |
1227 | const aarch64_sys_ins_reg *sysins_ops; | |
1228 | /* op0:op1:CRn:CRm:op2 */ | |
1229 | value = extract_fields (code, 0, 5, | |
1230 | FLD_op0, FLD_op1, FLD_CRn, | |
1231 | FLD_CRm, FLD_op2); | |
1232 | ||
1233 | switch (info->type) | |
1234 | { | |
1235 | case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break; | |
1236 | case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; | |
1237 | case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; | |
1238 | case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; | |
561a72d4 | 1239 | default: assert (0); return FALSE; |
a06ea964 NC |
1240 | } |
1241 | ||
875880c6 | 1242 | for (i = 0; sysins_ops[i].name != NULL; ++i) |
a06ea964 NC |
1243 | if (sysins_ops[i].value == value) |
1244 | { | |
1245 | info->sysins_op = sysins_ops + i; | |
1246 | DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", | |
875880c6 | 1247 | info->sysins_op->name, |
a06ea964 | 1248 | (unsigned)info->sysins_op->value, |
ea2deeec | 1249 | aarch64_sys_ins_reg_has_xt (info->sysins_op), i); |
561a72d4 | 1250 | return TRUE; |
a06ea964 NC |
1251 | } |
1252 | ||
561a72d4 | 1253 | return FALSE; |
a06ea964 NC |
1254 | } |
1255 | ||
1256 | /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ | |
1257 | ||
561a72d4 | 1258 | bfd_boolean |
a06ea964 NC |
1259 | aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1260 | aarch64_opnd_info *info, | |
1261 | aarch64_insn code, | |
561a72d4 TC |
1262 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1263 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1264 | { |
1265 | /* CRm */ | |
1266 | info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0); | |
561a72d4 | 1267 | return TRUE; |
a06ea964 NC |
1268 | } |
1269 | ||
1270 | /* Decode the prefetch operation option operand for e.g. | |
1271 | PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ | |
1272 | ||
561a72d4 | 1273 | bfd_boolean |
a06ea964 NC |
1274 | aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1275 | aarch64_opnd_info *info, | |
561a72d4 TC |
1276 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1277 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1278 | { |
1279 | /* prfop in Rt */ | |
1280 | info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0); | |
561a72d4 | 1281 | return TRUE; |
a06ea964 NC |
1282 | } |
1283 | ||
9ed608f9 MW |
1284 | /* Decode the hint number for an alias taking an operand. Set info->hint_option |
1285 | to the matching name/value pair in aarch64_hint_options. */ | |
1286 | ||
561a72d4 | 1287 | bfd_boolean |
9ed608f9 MW |
1288 | aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1289 | aarch64_opnd_info *info, | |
1290 | aarch64_insn code, | |
561a72d4 TC |
1291 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1292 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
9ed608f9 MW |
1293 | { |
1294 | /* CRm:op2. */ | |
1295 | unsigned hint_number; | |
1296 | int i; | |
1297 | ||
1298 | hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2); | |
1299 | ||
1300 | for (i = 0; aarch64_hint_options[i].name != NULL; i++) | |
1301 | { | |
1302 | if (hint_number == aarch64_hint_options[i].value) | |
1303 | { | |
1304 | info->hint_option = &(aarch64_hint_options[i]); | |
561a72d4 | 1305 | return TRUE; |
9ed608f9 MW |
1306 | } |
1307 | } | |
1308 | ||
561a72d4 | 1309 | return FALSE; |
9ed608f9 MW |
1310 | } |
1311 | ||
a06ea964 NC |
1312 | /* Decode the extended register operand for e.g. |
1313 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1314 | bfd_boolean |
a06ea964 NC |
1315 | aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1316 | aarch64_opnd_info *info, | |
1317 | aarch64_insn code, | |
561a72d4 TC |
1318 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1319 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1320 | { |
1321 | aarch64_insn value; | |
1322 | ||
1323 | /* Rm */ | |
1324 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1325 | /* option */ | |
1326 | value = extract_field (FLD_option, code, 0); | |
1327 | info->shifter.kind = | |
1328 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1329 | /* imm3 */ | |
1330 | info->shifter.amount = extract_field (FLD_imm3, code, 0); | |
1331 | ||
1332 | /* This makes the constraint checking happy. */ | |
1333 | info->shifter.operator_present = 1; | |
1334 | ||
1335 | /* Assume inst->operands[0].qualifier has been resolved. */ | |
1336 | assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL); | |
1337 | info->qualifier = AARCH64_OPND_QLF_W; | |
1338 | if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X | |
1339 | && (info->shifter.kind == AARCH64_MOD_UXTX | |
1340 | || info->shifter.kind == AARCH64_MOD_SXTX)) | |
1341 | info->qualifier = AARCH64_OPND_QLF_X; | |
1342 | ||
561a72d4 | 1343 | return TRUE; |
a06ea964 NC |
1344 | } |
1345 | ||
1346 | /* Decode the shifted register operand for e.g. | |
1347 | SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ | |
561a72d4 | 1348 | bfd_boolean |
a06ea964 NC |
1349 | aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1350 | aarch64_opnd_info *info, | |
1351 | aarch64_insn code, | |
561a72d4 TC |
1352 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1353 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1354 | { |
1355 | aarch64_insn value; | |
1356 | ||
1357 | /* Rm */ | |
1358 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1359 | /* shift */ | |
1360 | value = extract_field (FLD_shift, code, 0); | |
1361 | info->shifter.kind = | |
1362 | aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */); | |
1363 | if (info->shifter.kind == AARCH64_MOD_ROR | |
1364 | && inst->opcode->iclass != log_shift) | |
1365 | /* ROR is not available for the shifted register operand in arithmetic | |
1366 | instructions. */ | |
561a72d4 | 1367 | return FALSE; |
a06ea964 NC |
1368 | /* imm6 */ |
1369 | info->shifter.amount = extract_field (FLD_imm6, code, 0); | |
1370 | ||
1371 | /* This makes the constraint checking happy. */ | |
1372 | info->shifter.operator_present = 1; | |
1373 | ||
561a72d4 | 1374 | return TRUE; |
a06ea964 | 1375 | } |
f11ad6bc | 1376 | |
98907a70 RS |
1377 | /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL], |
1378 | where <offset> is given by the OFFSET parameter and where <factor> is | |
1379 | 1 plus SELF's operand-dependent value. fields[0] specifies the field | |
1380 | that holds <base>. */ | |
561a72d4 | 1381 | static bfd_boolean |
98907a70 RS |
1382 | aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, |
1383 | aarch64_opnd_info *info, aarch64_insn code, | |
1384 | int64_t offset) | |
1385 | { | |
1386 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1387 | info->addr.offset.imm = offset * (1 + get_operand_specific_data (self)); | |
1388 | info->addr.offset.is_reg = FALSE; | |
1389 | info->addr.writeback = FALSE; | |
1390 | info->addr.preind = TRUE; | |
1391 | if (offset != 0) | |
1392 | info->shifter.kind = AARCH64_MOD_MUL_VL; | |
1393 | info->shifter.amount = 1; | |
1394 | info->shifter.operator_present = (info->addr.offset.imm != 0); | |
1395 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1396 | return TRUE; |
98907a70 RS |
1397 | } |
1398 | ||
1399 | /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL], | |
1400 | where <simm4> is a 4-bit signed value and where <factor> is 1 plus | |
1401 | SELF's operand-dependent value. fields[0] specifies the field that | |
1402 | holds <base>. <simm4> is encoded in the SVE_imm4 field. */ | |
561a72d4 | 1403 | bfd_boolean |
98907a70 RS |
1404 | aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, |
1405 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1406 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1407 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1408 | { |
1409 | int offset; | |
1410 | ||
1411 | offset = extract_field (FLD_SVE_imm4, code, 0); | |
1412 | offset = ((offset + 8) & 15) - 8; | |
1413 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1414 | } | |
1415 | ||
1416 | /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL], | |
1417 | where <simm6> is a 6-bit signed value and where <factor> is 1 plus | |
1418 | SELF's operand-dependent value. fields[0] specifies the field that | |
1419 | holds <base>. <simm6> is encoded in the SVE_imm6 field. */ | |
561a72d4 | 1420 | bfd_boolean |
98907a70 RS |
1421 | aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, |
1422 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1423 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1424 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1425 | { |
1426 | int offset; | |
1427 | ||
1428 | offset = extract_field (FLD_SVE_imm6, code, 0); | |
1429 | offset = (((offset + 32) & 63) - 32); | |
1430 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1431 | } | |
1432 | ||
1433 | /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL], | |
1434 | where <simm9> is a 9-bit signed value and where <factor> is 1 plus | |
1435 | SELF's operand-dependent value. fields[0] specifies the field that | |
1436 | holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6 | |
1437 | and imm3 fields, with imm3 being the less-significant part. */ | |
561a72d4 | 1438 | bfd_boolean |
98907a70 RS |
1439 | aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, |
1440 | aarch64_opnd_info *info, | |
1441 | aarch64_insn code, | |
561a72d4 TC |
1442 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1443 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1444 | { |
1445 | int offset; | |
1446 | ||
1447 | offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3); | |
1448 | offset = (((offset + 256) & 511) - 256); | |
1449 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1450 | } | |
1451 | ||
4df068de RS |
1452 | /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset> |
1453 | is given by the OFFSET parameter and where <shift> is SELF's operand- | |
1454 | dependent value. fields[0] specifies the base register field <base>. */ | |
561a72d4 | 1455 | static bfd_boolean |
4df068de RS |
1456 | aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, |
1457 | aarch64_opnd_info *info, aarch64_insn code, | |
1458 | int64_t offset) | |
1459 | { | |
1460 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1461 | info->addr.offset.imm = offset * (1 << get_operand_specific_data (self)); | |
1462 | info->addr.offset.is_reg = FALSE; | |
1463 | info->addr.writeback = FALSE; | |
1464 | info->addr.preind = TRUE; | |
1465 | info->shifter.operator_present = FALSE; | |
1466 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1467 | return TRUE; |
4df068de RS |
1468 | } |
1469 | ||
582e12bf RS |
1470 | /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4> |
1471 | is a 4-bit signed number and where <shift> is SELF's operand-dependent | |
1472 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1473 | bfd_boolean |
582e12bf RS |
1474 | aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, |
1475 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1476 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1477 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1478 | { |
1479 | int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3); | |
1480 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1481 | } | |
1482 | ||
4df068de RS |
1483 | /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6> |
1484 | is a 6-bit unsigned number and where <shift> is SELF's operand-dependent | |
1485 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1486 | bfd_boolean |
4df068de RS |
1487 | aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, |
1488 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1489 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1490 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1491 | { |
1492 | int offset = extract_field (FLD_SVE_imm6, code, 0); | |
1493 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1494 | } | |
1495 | ||
1496 | /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift> | |
1497 | is SELF's operand-dependent value. fields[0] specifies the base | |
1498 | register field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1499 | bfd_boolean |
4df068de RS |
1500 | aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, |
1501 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1502 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1503 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de | 1504 | { |
eaf02703 | 1505 | int index_regno; |
4df068de | 1506 | |
eaf02703 MR |
1507 | index_regno = extract_field (self->fields[1], code, 0); |
1508 | if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0) | |
561a72d4 | 1509 | return FALSE; |
4df068de RS |
1510 | |
1511 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
eaf02703 | 1512 | info->addr.offset.regno = index_regno; |
4df068de RS |
1513 | info->addr.offset.is_reg = TRUE; |
1514 | info->addr.writeback = FALSE; | |
1515 | info->addr.preind = TRUE; | |
1516 | info->shifter.kind = AARCH64_MOD_LSL; | |
1517 | info->shifter.amount = get_operand_specific_data (self); | |
1518 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1519 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1520 | return TRUE; |
4df068de RS |
1521 | } |
1522 | ||
1523 | /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where | |
1524 | <shift> is SELF's operand-dependent value. fields[0] specifies the | |
1525 | base register field, fields[1] specifies the offset register field and | |
1526 | fields[2] is a single-bit field that selects SXTW over UXTW. */ | |
561a72d4 | 1527 | bfd_boolean |
4df068de RS |
1528 | aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, |
1529 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1530 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1531 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1532 | { |
1533 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1534 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1535 | info->addr.offset.is_reg = TRUE; | |
1536 | info->addr.writeback = FALSE; | |
1537 | info->addr.preind = TRUE; | |
1538 | if (extract_field (self->fields[2], code, 0)) | |
1539 | info->shifter.kind = AARCH64_MOD_SXTW; | |
1540 | else | |
1541 | info->shifter.kind = AARCH64_MOD_UXTW; | |
1542 | info->shifter.amount = get_operand_specific_data (self); | |
1543 | info->shifter.operator_present = TRUE; | |
1544 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1545 | return TRUE; |
4df068de RS |
1546 | } |
1547 | ||
1548 | /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a | |
1549 | 5-bit unsigned number and where <shift> is SELF's operand-dependent value. | |
1550 | fields[0] specifies the base register field. */ | |
561a72d4 | 1551 | bfd_boolean |
4df068de RS |
1552 | aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, |
1553 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1554 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1555 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1556 | { |
1557 | int offset = extract_field (FLD_imm5, code, 0); | |
1558 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1559 | } | |
1560 | ||
1561 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}], | |
1562 | where <modifier> is given by KIND and where <msz> is a 2-bit unsigned | |
1563 | number. fields[0] specifies the base register field and fields[1] | |
1564 | specifies the offset register field. */ | |
561a72d4 | 1565 | static bfd_boolean |
4df068de RS |
1566 | aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, |
1567 | aarch64_insn code, enum aarch64_modifier_kind kind) | |
1568 | { | |
1569 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1570 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1571 | info->addr.offset.is_reg = TRUE; | |
1572 | info->addr.writeback = FALSE; | |
1573 | info->addr.preind = TRUE; | |
1574 | info->shifter.kind = kind; | |
1575 | info->shifter.amount = extract_field (FLD_SVE_msz, code, 0); | |
1576 | info->shifter.operator_present = (kind != AARCH64_MOD_LSL | |
1577 | || info->shifter.amount != 0); | |
1578 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1579 | return TRUE; |
4df068de RS |
1580 | } |
1581 | ||
1582 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where | |
1583 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1584 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1585 | bfd_boolean |
4df068de RS |
1586 | aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, |
1587 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1588 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1589 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1590 | { |
1591 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL); | |
1592 | } | |
1593 | ||
1594 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where | |
1595 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1596 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1597 | bfd_boolean |
4df068de RS |
1598 | aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, |
1599 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1600 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1601 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1602 | { |
1603 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW); | |
1604 | } | |
1605 | ||
1606 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where | |
1607 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1608 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1609 | bfd_boolean |
4df068de RS |
1610 | aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self, |
1611 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1612 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1613 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1614 | { |
1615 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW); | |
1616 | } | |
1617 | ||
e950b345 RS |
1618 | /* Finish decoding an SVE arithmetic immediate, given that INFO already |
1619 | has the raw field value and that the low 8 bits decode to VALUE. */ | |
561a72d4 | 1620 | static bfd_boolean |
e950b345 RS |
1621 | decode_sve_aimm (aarch64_opnd_info *info, int64_t value) |
1622 | { | |
1623 | info->shifter.kind = AARCH64_MOD_LSL; | |
1624 | info->shifter.amount = 0; | |
1625 | if (info->imm.value & 0x100) | |
1626 | { | |
1627 | if (value == 0) | |
1628 | /* Decode 0x100 as #0, LSL #8. */ | |
1629 | info->shifter.amount = 8; | |
1630 | else | |
1631 | value *= 256; | |
1632 | } | |
1633 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1634 | info->shifter.amount_present = (info->shifter.amount != 0); | |
1635 | info->imm.value = value; | |
561a72d4 | 1636 | return TRUE; |
e950b345 RS |
1637 | } |
1638 | ||
1639 | /* Decode an SVE ADD/SUB immediate. */ | |
561a72d4 | 1640 | bfd_boolean |
e950b345 RS |
1641 | aarch64_ext_sve_aimm (const aarch64_operand *self, |
1642 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1643 | const aarch64_inst *inst, |
1644 | aarch64_operand_error *errors) | |
e950b345 | 1645 | { |
561a72d4 | 1646 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1647 | && decode_sve_aimm (info, (uint8_t) info->imm.value)); |
1648 | } | |
1649 | ||
1650 | /* Decode an SVE CPY/DUP immediate. */ | |
561a72d4 | 1651 | bfd_boolean |
e950b345 RS |
1652 | aarch64_ext_sve_asimm (const aarch64_operand *self, |
1653 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1654 | const aarch64_inst *inst, |
1655 | aarch64_operand_error *errors) | |
e950b345 | 1656 | { |
561a72d4 | 1657 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1658 | && decode_sve_aimm (info, (int8_t) info->imm.value)); |
1659 | } | |
1660 | ||
165d4950 RS |
1661 | /* Decode a single-bit immediate that selects between #0.5 and #1.0. |
1662 | The fields array specifies which field to use. */ | |
561a72d4 | 1663 | bfd_boolean |
165d4950 RS |
1664 | aarch64_ext_sve_float_half_one (const aarch64_operand *self, |
1665 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1666 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1667 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1668 | { |
1669 | if (extract_field (self->fields[0], code, 0)) | |
1670 | info->imm.value = 0x3f800000; | |
1671 | else | |
1672 | info->imm.value = 0x3f000000; | |
1673 | info->imm.is_fp = TRUE; | |
561a72d4 | 1674 | return TRUE; |
165d4950 RS |
1675 | } |
1676 | ||
1677 | /* Decode a single-bit immediate that selects between #0.5 and #2.0. | |
1678 | The fields array specifies which field to use. */ | |
561a72d4 | 1679 | bfd_boolean |
165d4950 RS |
1680 | aarch64_ext_sve_float_half_two (const aarch64_operand *self, |
1681 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1682 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1683 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1684 | { |
1685 | if (extract_field (self->fields[0], code, 0)) | |
1686 | info->imm.value = 0x40000000; | |
1687 | else | |
1688 | info->imm.value = 0x3f000000; | |
1689 | info->imm.is_fp = TRUE; | |
561a72d4 | 1690 | return TRUE; |
165d4950 RS |
1691 | } |
1692 | ||
1693 | /* Decode a single-bit immediate that selects between #0.0 and #1.0. | |
1694 | The fields array specifies which field to use. */ | |
561a72d4 | 1695 | bfd_boolean |
165d4950 RS |
1696 | aarch64_ext_sve_float_zero_one (const aarch64_operand *self, |
1697 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1698 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1699 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1700 | { |
1701 | if (extract_field (self->fields[0], code, 0)) | |
1702 | info->imm.value = 0x3f800000; | |
1703 | else | |
1704 | info->imm.value = 0x0; | |
1705 | info->imm.is_fp = TRUE; | |
561a72d4 | 1706 | return TRUE; |
165d4950 RS |
1707 | } |
1708 | ||
f11ad6bc RS |
1709 | /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields |
1710 | array specifies which field to use for Zn. MM is encoded in the | |
1711 | concatenation of imm5 and SVE_tszh, with imm5 being the less | |
1712 | significant part. */ | |
561a72d4 | 1713 | bfd_boolean |
f11ad6bc RS |
1714 | aarch64_ext_sve_index (const aarch64_operand *self, |
1715 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1716 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1717 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1718 | { |
1719 | int val; | |
1720 | ||
1721 | info->reglane.regno = extract_field (self->fields[0], code, 0); | |
1722 | val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 1723 | if ((val & 31) == 0) |
f11ad6bc RS |
1724 | return 0; |
1725 | while ((val & 1) == 0) | |
1726 | val /= 2; | |
1727 | info->reglane.index = val / 2; | |
561a72d4 | 1728 | return TRUE; |
f11ad6bc RS |
1729 | } |
1730 | ||
e950b345 | 1731 | /* Decode a logical immediate for the MOV alias of SVE DUPM. */ |
561a72d4 | 1732 | bfd_boolean |
e950b345 RS |
1733 | aarch64_ext_sve_limm_mov (const aarch64_operand *self, |
1734 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1735 | const aarch64_inst *inst, |
1736 | aarch64_operand_error *errors) | |
e950b345 RS |
1737 | { |
1738 | int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
561a72d4 | 1739 | return (aarch64_ext_limm (self, info, code, inst, errors) |
e950b345 RS |
1740 | && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize)); |
1741 | } | |
1742 | ||
582e12bf RS |
1743 | /* Decode Zn[MM], where Zn occupies the least-significant part of the field |
1744 | and where MM occupies the most-significant part. The operand-dependent | |
1745 | value specifies the number of bits in Zn. */ | |
561a72d4 | 1746 | bfd_boolean |
582e12bf RS |
1747 | aarch64_ext_sve_quad_index (const aarch64_operand *self, |
1748 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1749 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1750 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1751 | { |
1752 | unsigned int reg_bits = get_operand_specific_data (self); | |
1753 | unsigned int val = extract_all_fields (self, code); | |
1754 | info->reglane.regno = val & ((1 << reg_bits) - 1); | |
1755 | info->reglane.index = val >> reg_bits; | |
561a72d4 | 1756 | return TRUE; |
582e12bf RS |
1757 | } |
1758 | ||
f11ad6bc RS |
1759 | /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field |
1760 | to use for Zn. The opcode-dependent value specifies the number | |
1761 | of registers in the list. */ | |
561a72d4 | 1762 | bfd_boolean |
f11ad6bc RS |
1763 | aarch64_ext_sve_reglist (const aarch64_operand *self, |
1764 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1765 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1766 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1767 | { |
1768 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
1769 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
561a72d4 | 1770 | return TRUE; |
f11ad6bc | 1771 | } |
2442d846 RS |
1772 | |
1773 | /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which | |
1774 | fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4 | |
1775 | field. */ | |
561a72d4 | 1776 | bfd_boolean |
2442d846 RS |
1777 | aarch64_ext_sve_scale (const aarch64_operand *self, |
1778 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 | 1779 | const aarch64_inst *inst, aarch64_operand_error *errors) |
2442d846 RS |
1780 | { |
1781 | int val; | |
1782 | ||
561a72d4 TC |
1783 | if (!aarch64_ext_imm (self, info, code, inst, errors)) |
1784 | return FALSE; | |
2442d846 RS |
1785 | val = extract_field (FLD_SVE_imm4, code, 0); |
1786 | info->shifter.kind = AARCH64_MOD_MUL; | |
1787 | info->shifter.amount = val + 1; | |
1788 | info->shifter.operator_present = (val != 0); | |
1789 | info->shifter.amount_present = (val != 0); | |
561a72d4 | 1790 | return TRUE; |
2442d846 | 1791 | } |
e950b345 RS |
1792 | |
1793 | /* Return the top set bit in VALUE, which is expected to be relatively | |
1794 | small. */ | |
1795 | static uint64_t | |
1796 | get_top_bit (uint64_t value) | |
1797 | { | |
1798 | while ((value & -value) != value) | |
1799 | value -= value & -value; | |
1800 | return value; | |
1801 | } | |
1802 | ||
1803 | /* Decode an SVE shift-left immediate. */ | |
561a72d4 | 1804 | bfd_boolean |
e950b345 RS |
1805 | aarch64_ext_sve_shlimm (const aarch64_operand *self, |
1806 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 1807 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 1808 | { |
561a72d4 | 1809 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 1810 | || info->imm.value == 0) |
561a72d4 | 1811 | return FALSE; |
e950b345 RS |
1812 | |
1813 | info->imm.value -= get_top_bit (info->imm.value); | |
561a72d4 | 1814 | return TRUE; |
e950b345 RS |
1815 | } |
1816 | ||
1817 | /* Decode an SVE shift-right immediate. */ | |
561a72d4 | 1818 | bfd_boolean |
e950b345 RS |
1819 | aarch64_ext_sve_shrimm (const aarch64_operand *self, |
1820 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 1821 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 1822 | { |
561a72d4 | 1823 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 1824 | || info->imm.value == 0) |
561a72d4 | 1825 | return FALSE; |
e950b345 RS |
1826 | |
1827 | info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value; | |
561a72d4 | 1828 | return TRUE; |
e950b345 | 1829 | } |
a06ea964 NC |
1830 | \f |
1831 | /* Bitfields that are commonly used to encode certain operands' information | |
1832 | may be partially used as part of the base opcode in some instructions. | |
1833 | For example, the bit 1 of the field 'size' in | |
1834 | FCVTXN <Vb><d>, <Va><n> | |
1835 | is actually part of the base opcode, while only size<0> is available | |
1836 | for encoding the register type. Another example is the AdvSIMD | |
1837 | instruction ORR (register), in which the field 'size' is also used for | |
1838 | the base opcode, leaving only the field 'Q' available to encode the | |
1839 | vector register arrangement specifier '8B' or '16B'. | |
1840 | ||
1841 | This function tries to deduce the qualifier from the value of partially | |
1842 | constrained field(s). Given the VALUE of such a field or fields, the | |
1843 | qualifiers CANDIDATES and the MASK (indicating which bits are valid for | |
1844 | operand encoding), the function returns the matching qualifier or | |
1845 | AARCH64_OPND_QLF_NIL if nothing matches. | |
1846 | ||
1847 | N.B. CANDIDATES is a group of possible qualifiers that are valid for | |
1848 | one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and | |
1849 | may end with AARCH64_OPND_QLF_NIL. */ | |
1850 | ||
1851 | static enum aarch64_opnd_qualifier | |
1852 | get_qualifier_from_partial_encoding (aarch64_insn value, | |
1853 | const enum aarch64_opnd_qualifier* \ | |
1854 | candidates, | |
1855 | aarch64_insn mask) | |
1856 | { | |
1857 | int i; | |
1858 | DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask); | |
1859 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1860 | { | |
1861 | aarch64_insn standard_value; | |
1862 | if (candidates[i] == AARCH64_OPND_QLF_NIL) | |
1863 | break; | |
1864 | standard_value = aarch64_get_qualifier_standard_value (candidates[i]); | |
1865 | if ((standard_value & mask) == (value & mask)) | |
1866 | return candidates[i]; | |
1867 | } | |
1868 | return AARCH64_OPND_QLF_NIL; | |
1869 | } | |
1870 | ||
1871 | /* Given a list of qualifier sequences, return all possible valid qualifiers | |
1872 | for operand IDX in QUALIFIERS. | |
1873 | Assume QUALIFIERS is an array whose length is large enough. */ | |
1874 | ||
1875 | static void | |
1876 | get_operand_possible_qualifiers (int idx, | |
1877 | const aarch64_opnd_qualifier_seq_t *list, | |
1878 | enum aarch64_opnd_qualifier *qualifiers) | |
1879 | { | |
1880 | int i; | |
1881 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1882 | if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL) | |
1883 | break; | |
1884 | } | |
1885 | ||
1886 | /* Decode the size Q field for e.g. SHADD. | |
1887 | We tag one operand with the qualifer according to the code; | |
1888 | whether the qualifier is valid for this opcode or not, it is the | |
1889 | duty of the semantic checking. */ | |
1890 | ||
1891 | static int | |
1892 | decode_sizeq (aarch64_inst *inst) | |
1893 | { | |
1894 | int idx; | |
1895 | enum aarch64_opnd_qualifier qualifier; | |
1896 | aarch64_insn code; | |
1897 | aarch64_insn value, mask; | |
1898 | enum aarch64_field_kind fld_sz; | |
1899 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
1900 | ||
1901 | if (inst->opcode->iclass == asisdlse | |
1902 | || inst->opcode->iclass == asisdlsep | |
1903 | || inst->opcode->iclass == asisdlso | |
1904 | || inst->opcode->iclass == asisdlsop) | |
1905 | fld_sz = FLD_vldst_size; | |
1906 | else | |
1907 | fld_sz = FLD_size; | |
1908 | ||
1909 | code = inst->value; | |
1910 | value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q); | |
1911 | /* Obtain the info that which bits of fields Q and size are actually | |
1912 | available for operand encoding. Opcodes like FMAXNM and FMLA have | |
1913 | size[1] unavailable. */ | |
1914 | mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q); | |
1915 | ||
1916 | /* The index of the operand we are going to tag a qualifier and the qualifer | |
1917 | itself are reasoned from the value of the size and Q fields and the | |
1918 | possible valid qualifier lists. */ | |
1919 | idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode); | |
1920 | DEBUG_TRACE ("key idx: %d", idx); | |
1921 | ||
1922 | /* For most related instruciton, size:Q are fully available for operand | |
1923 | encoding. */ | |
1924 | if (mask == 0x7) | |
1925 | { | |
1926 | inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value); | |
1927 | return 1; | |
1928 | } | |
1929 | ||
1930 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
1931 | candidates); | |
1932 | #ifdef DEBUG_AARCH64 | |
1933 | if (debug_dump) | |
1934 | { | |
1935 | int i; | |
1936 | for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL | |
1937 | && i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1938 | DEBUG_TRACE ("qualifier %d: %s", i, | |
1939 | aarch64_get_qualifier_name(candidates[i])); | |
1940 | DEBUG_TRACE ("%d, %d", (int)value, (int)mask); | |
1941 | } | |
1942 | #endif /* DEBUG_AARCH64 */ | |
1943 | ||
1944 | qualifier = get_qualifier_from_partial_encoding (value, candidates, mask); | |
1945 | ||
1946 | if (qualifier == AARCH64_OPND_QLF_NIL) | |
1947 | return 0; | |
1948 | ||
1949 | inst->operands[idx].qualifier = qualifier; | |
1950 | return 1; | |
1951 | } | |
1952 | ||
1953 | /* Decode size[0]:Q, i.e. bit 22 and bit 30, for | |
1954 | e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
1955 | ||
1956 | static int | |
1957 | decode_asimd_fcvt (aarch64_inst *inst) | |
1958 | { | |
1959 | aarch64_field field = {0, 0}; | |
1960 | aarch64_insn value; | |
1961 | enum aarch64_opnd_qualifier qualifier; | |
1962 | ||
1963 | gen_sub_field (FLD_size, 0, 1, &field); | |
1964 | value = extract_field_2 (&field, inst->value, 0); | |
1965 | qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S | |
1966 | : AARCH64_OPND_QLF_V_2D; | |
1967 | switch (inst->opcode->op) | |
1968 | { | |
1969 | case OP_FCVTN: | |
1970 | case OP_FCVTN2: | |
1971 | /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
1972 | inst->operands[1].qualifier = qualifier; | |
1973 | break; | |
1974 | case OP_FCVTL: | |
1975 | case OP_FCVTL2: | |
1976 | /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
1977 | inst->operands[0].qualifier = qualifier; | |
1978 | break; | |
1979 | default: | |
1980 | assert (0); | |
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | return 1; | |
1985 | } | |
1986 | ||
1987 | /* Decode size[0], i.e. bit 22, for | |
1988 | e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
1989 | ||
1990 | static int | |
1991 | decode_asisd_fcvtxn (aarch64_inst *inst) | |
1992 | { | |
1993 | aarch64_field field = {0, 0}; | |
1994 | gen_sub_field (FLD_size, 0, 1, &field); | |
1995 | if (!extract_field_2 (&field, inst->value, 0)) | |
1996 | return 0; | |
1997 | inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; | |
1998 | return 1; | |
1999 | } | |
2000 | ||
2001 | /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */ | |
2002 | static int | |
2003 | decode_fcvt (aarch64_inst *inst) | |
2004 | { | |
2005 | enum aarch64_opnd_qualifier qualifier; | |
2006 | aarch64_insn value; | |
2007 | const aarch64_field field = {15, 2}; | |
2008 | ||
2009 | /* opc dstsize */ | |
2010 | value = extract_field_2 (&field, inst->value, 0); | |
2011 | switch (value) | |
2012 | { | |
2013 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
2014 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
2015 | case 3: qualifier = AARCH64_OPND_QLF_S_H; break; | |
2016 | default: return 0; | |
2017 | } | |
2018 | inst->operands[0].qualifier = qualifier; | |
2019 | ||
2020 | return 1; | |
2021 | } | |
2022 | ||
2023 | /* Do miscellaneous decodings that are not common enough to be driven by | |
2024 | flags. */ | |
2025 | ||
2026 | static int | |
2027 | do_misc_decoding (aarch64_inst *inst) | |
2028 | { | |
c0890d26 | 2029 | unsigned int value; |
a06ea964 NC |
2030 | switch (inst->opcode->op) |
2031 | { | |
2032 | case OP_FCVT: | |
2033 | return decode_fcvt (inst); | |
c0890d26 | 2034 | |
a06ea964 NC |
2035 | case OP_FCVTN: |
2036 | case OP_FCVTN2: | |
2037 | case OP_FCVTL: | |
2038 | case OP_FCVTL2: | |
2039 | return decode_asimd_fcvt (inst); | |
c0890d26 | 2040 | |
a06ea964 NC |
2041 | case OP_FCVTXN_S: |
2042 | return decode_asisd_fcvtxn (inst); | |
c0890d26 RS |
2043 | |
2044 | case OP_MOV_P_P: | |
2045 | case OP_MOVS_P_P: | |
2046 | value = extract_field (FLD_SVE_Pn, inst->value, 0); | |
2047 | return (value == extract_field (FLD_SVE_Pm, inst->value, 0) | |
2048 | && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2049 | ||
2050 | case OP_MOV_Z_P_Z: | |
2051 | return (extract_field (FLD_SVE_Zd, inst->value, 0) | |
2052 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2053 | ||
2054 | case OP_MOV_Z_V: | |
2055 | /* Index must be zero. */ | |
2056 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2057 | return value > 0 && value <= 16 && value == (value & -value); |
c0890d26 RS |
2058 | |
2059 | case OP_MOV_Z_Z: | |
2060 | return (extract_field (FLD_SVE_Zn, inst->value, 0) | |
2061 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2062 | ||
2063 | case OP_MOV_Z_Zi: | |
2064 | /* Index must be nonzero. */ | |
2065 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2066 | return value > 0 && value != (value & -value); |
c0890d26 RS |
2067 | |
2068 | case OP_MOVM_P_P_P: | |
2069 | return (extract_field (FLD_SVE_Pd, inst->value, 0) | |
2070 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2071 | ||
2072 | case OP_MOVZS_P_P_P: | |
2073 | case OP_MOVZ_P_P_P: | |
2074 | return (extract_field (FLD_SVE_Pn, inst->value, 0) | |
2075 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2076 | ||
2077 | case OP_NOTS_P_P_P_Z: | |
2078 | case OP_NOT_P_P_P_Z: | |
2079 | return (extract_field (FLD_SVE_Pm, inst->value, 0) | |
2080 | == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2081 | ||
a06ea964 NC |
2082 | default: |
2083 | return 0; | |
2084 | } | |
2085 | } | |
2086 | ||
2087 | /* Opcodes that have fields shared by multiple operands are usually flagged | |
2088 | with flags. In this function, we detect such flags, decode the related | |
2089 | field(s) and store the information in one of the related operands. The | |
2090 | 'one' operand is not any operand but one of the operands that can | |
2091 | accommadate all the information that has been decoded. */ | |
2092 | ||
2093 | static int | |
2094 | do_special_decoding (aarch64_inst *inst) | |
2095 | { | |
2096 | int idx; | |
2097 | aarch64_insn value; | |
2098 | /* Condition for truly conditional executed instructions, e.g. b.cond. */ | |
2099 | if (inst->opcode->flags & F_COND) | |
2100 | { | |
2101 | value = extract_field (FLD_cond2, inst->value, 0); | |
2102 | inst->cond = get_cond_from_value (value); | |
2103 | } | |
2104 | /* 'sf' field. */ | |
2105 | if (inst->opcode->flags & F_SF) | |
2106 | { | |
2107 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2108 | value = extract_field (FLD_sf, inst->value, 0); | |
2109 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2110 | if ((inst->opcode->flags & F_N) | |
2111 | && extract_field (FLD_N, inst->value, 0) != value) | |
2112 | return 0; | |
2113 | } | |
ee804238 JW |
2114 | /* 'sf' field. */ |
2115 | if (inst->opcode->flags & F_LSE_SZ) | |
2116 | { | |
2117 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2118 | value = extract_field (FLD_lse_sz, inst->value, 0); | |
2119 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2120 | } | |
a06ea964 NC |
2121 | /* size:Q fields. */ |
2122 | if (inst->opcode->flags & F_SIZEQ) | |
2123 | return decode_sizeq (inst); | |
2124 | ||
2125 | if (inst->opcode->flags & F_FPTYPE) | |
2126 | { | |
2127 | idx = select_operand_for_fptype_field_coding (inst->opcode); | |
2128 | value = extract_field (FLD_type, inst->value, 0); | |
2129 | switch (value) | |
2130 | { | |
2131 | case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break; | |
2132 | case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break; | |
2133 | case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break; | |
2134 | default: return 0; | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | if (inst->opcode->flags & F_SSIZE) | |
2139 | { | |
2140 | /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part | |
2141 | of the base opcode. */ | |
2142 | aarch64_insn mask; | |
2143 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
2144 | idx = select_operand_for_scalar_size_field_coding (inst->opcode); | |
2145 | value = extract_field (FLD_size, inst->value, inst->opcode->mask); | |
2146 | mask = extract_field (FLD_size, ~inst->opcode->mask, 0); | |
2147 | /* For most related instruciton, the 'size' field is fully available for | |
2148 | operand encoding. */ | |
2149 | if (mask == 0x3) | |
2150 | inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value); | |
2151 | else | |
2152 | { | |
2153 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
2154 | candidates); | |
2155 | inst->operands[idx].qualifier | |
2156 | = get_qualifier_from_partial_encoding (value, candidates, mask); | |
2157 | } | |
2158 | } | |
2159 | ||
2160 | if (inst->opcode->flags & F_T) | |
2161 | { | |
2162 | /* Num of consecutive '0's on the right side of imm5<3:0>. */ | |
2163 | int num = 0; | |
2164 | unsigned val, Q; | |
2165 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2166 | == AARCH64_OPND_CLASS_SIMD_REG); | |
2167 | /* imm5<3:0> q <t> | |
2168 | 0000 x reserved | |
2169 | xxx1 0 8b | |
2170 | xxx1 1 16b | |
2171 | xx10 0 4h | |
2172 | xx10 1 8h | |
2173 | x100 0 2s | |
2174 | x100 1 4s | |
2175 | 1000 0 reserved | |
2176 | 1000 1 2d */ | |
2177 | val = extract_field (FLD_imm5, inst->value, 0); | |
2178 | while ((val & 0x1) == 0 && ++num <= 3) | |
2179 | val >>= 1; | |
2180 | if (num > 3) | |
2181 | return 0; | |
2182 | Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask); | |
2183 | inst->operands[0].qualifier = | |
2184 | get_vreg_qualifier_from_value ((num << 1) | Q); | |
2185 | } | |
2186 | ||
2187 | if (inst->opcode->flags & F_GPRSIZE_IN_Q) | |
2188 | { | |
2189 | /* Use Rt to encode in the case of e.g. | |
2190 | STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ | |
2191 | idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt); | |
2192 | if (idx == -1) | |
2193 | { | |
2194 | /* Otherwise use the result operand, which has to be a integer | |
2195 | register. */ | |
2196 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2197 | == AARCH64_OPND_CLASS_INT_REG); | |
2198 | idx = 0; | |
2199 | } | |
2200 | assert (idx == 0 || idx == 1); | |
2201 | value = extract_field (FLD_Q, inst->value, 0); | |
2202 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2203 | } | |
2204 | ||
2205 | if (inst->opcode->flags & F_LDS_SIZE) | |
2206 | { | |
2207 | aarch64_field field = {0, 0}; | |
2208 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2209 | == AARCH64_OPND_CLASS_INT_REG); | |
2210 | gen_sub_field (FLD_opc, 0, 1, &field); | |
2211 | value = extract_field_2 (&field, inst->value, 0); | |
2212 | inst->operands[0].qualifier | |
2213 | = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; | |
2214 | } | |
2215 | ||
2216 | /* Miscellaneous decoding; done as the last step. */ | |
2217 | if (inst->opcode->flags & F_MISC) | |
2218 | return do_misc_decoding (inst); | |
2219 | ||
2220 | return 1; | |
2221 | } | |
2222 | ||
2223 | /* Converters converting a real opcode instruction to its alias form. */ | |
2224 | ||
2225 | /* ROR <Wd>, <Ws>, #<shift> | |
2226 | is equivalent to: | |
2227 | EXTR <Wd>, <Ws>, <Ws>, #<shift>. */ | |
2228 | static int | |
2229 | convert_extr_to_ror (aarch64_inst *inst) | |
2230 | { | |
2231 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2232 | { | |
2233 | copy_operand_info (inst, 2, 3); | |
2234 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2235 | return 1; | |
2236 | } | |
2237 | return 0; | |
2238 | } | |
2239 | ||
e30181a5 YZ |
2240 | /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb> |
2241 | is equivalent to: | |
2242 | USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */ | |
2243 | static int | |
2244 | convert_shll_to_xtl (aarch64_inst *inst) | |
2245 | { | |
2246 | if (inst->operands[2].imm.value == 0) | |
2247 | { | |
2248 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2249 | return 1; | |
2250 | } | |
2251 | return 0; | |
2252 | } | |
2253 | ||
a06ea964 NC |
2254 | /* Convert |
2255 | UBFM <Xd>, <Xn>, #<shift>, #63. | |
2256 | to | |
2257 | LSR <Xd>, <Xn>, #<shift>. */ | |
2258 | static int | |
2259 | convert_bfm_to_sr (aarch64_inst *inst) | |
2260 | { | |
2261 | int64_t imms, val; | |
2262 | ||
2263 | imms = inst->operands[3].imm.value; | |
2264 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2265 | if (imms == val) | |
2266 | { | |
2267 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2268 | return 1; | |
2269 | } | |
2270 | ||
2271 | return 0; | |
2272 | } | |
2273 | ||
2274 | /* Convert MOV to ORR. */ | |
2275 | static int | |
2276 | convert_orr_to_mov (aarch64_inst *inst) | |
2277 | { | |
2278 | /* MOV <Vd>.<T>, <Vn>.<T> | |
2279 | is equivalent to: | |
2280 | ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */ | |
2281 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2282 | { | |
2283 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2284 | return 1; | |
2285 | } | |
2286 | return 0; | |
2287 | } | |
2288 | ||
2289 | /* When <imms> >= <immr>, the instruction written: | |
2290 | SBFX <Xd>, <Xn>, #<lsb>, #<width> | |
2291 | is equivalent to: | |
2292 | SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */ | |
2293 | ||
2294 | static int | |
2295 | convert_bfm_to_bfx (aarch64_inst *inst) | |
2296 | { | |
2297 | int64_t immr, imms; | |
2298 | ||
2299 | immr = inst->operands[2].imm.value; | |
2300 | imms = inst->operands[3].imm.value; | |
2301 | if (imms >= immr) | |
2302 | { | |
2303 | int64_t lsb = immr; | |
2304 | inst->operands[2].imm.value = lsb; | |
2305 | inst->operands[3].imm.value = imms + 1 - lsb; | |
2306 | /* The two opcodes have different qualifiers for | |
2307 | the immediate operands; reset to help the checking. */ | |
2308 | reset_operand_qualifier (inst, 2); | |
2309 | reset_operand_qualifier (inst, 3); | |
2310 | return 1; | |
2311 | } | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | ||
2316 | /* When <imms> < <immr>, the instruction written: | |
2317 | SBFIZ <Xd>, <Xn>, #<lsb>, #<width> | |
2318 | is equivalent to: | |
2319 | SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2320 | ||
2321 | static int | |
2322 | convert_bfm_to_bfi (aarch64_inst *inst) | |
2323 | { | |
2324 | int64_t immr, imms, val; | |
2325 | ||
2326 | immr = inst->operands[2].imm.value; | |
2327 | imms = inst->operands[3].imm.value; | |
2328 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2329 | if (imms < immr) | |
2330 | { | |
2331 | inst->operands[2].imm.value = (val - immr) & (val - 1); | |
2332 | inst->operands[3].imm.value = imms + 1; | |
2333 | /* The two opcodes have different qualifiers for | |
2334 | the immediate operands; reset to help the checking. */ | |
2335 | reset_operand_qualifier (inst, 2); | |
2336 | reset_operand_qualifier (inst, 3); | |
2337 | return 1; | |
2338 | } | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | ||
d685192a MW |
2343 | /* The instruction written: |
2344 | BFC <Xd>, #<lsb>, #<width> | |
2345 | is equivalent to: | |
2346 | BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2347 | ||
2348 | static int | |
2349 | convert_bfm_to_bfc (aarch64_inst *inst) | |
2350 | { | |
2351 | int64_t immr, imms, val; | |
2352 | ||
2353 | /* Should have been assured by the base opcode value. */ | |
2354 | assert (inst->operands[1].reg.regno == 0x1f); | |
2355 | ||
2356 | immr = inst->operands[2].imm.value; | |
2357 | imms = inst->operands[3].imm.value; | |
2358 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2359 | if (imms < immr) | |
2360 | { | |
2361 | /* Drop XZR from the second operand. */ | |
2362 | copy_operand_info (inst, 1, 2); | |
2363 | copy_operand_info (inst, 2, 3); | |
2364 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2365 | ||
2366 | /* Recalculate the immediates. */ | |
2367 | inst->operands[1].imm.value = (val - immr) & (val - 1); | |
2368 | inst->operands[2].imm.value = imms + 1; | |
2369 | ||
2370 | /* The two opcodes have different qualifiers for the operands; reset to | |
2371 | help the checking. */ | |
2372 | reset_operand_qualifier (inst, 1); | |
2373 | reset_operand_qualifier (inst, 2); | |
2374 | reset_operand_qualifier (inst, 3); | |
2375 | ||
2376 | return 1; | |
2377 | } | |
2378 | ||
2379 | return 0; | |
2380 | } | |
2381 | ||
a06ea964 NC |
2382 | /* The instruction written: |
2383 | LSL <Xd>, <Xn>, #<shift> | |
2384 | is equivalent to: | |
2385 | UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */ | |
2386 | ||
2387 | static int | |
2388 | convert_ubfm_to_lsl (aarch64_inst *inst) | |
2389 | { | |
2390 | int64_t immr = inst->operands[2].imm.value; | |
2391 | int64_t imms = inst->operands[3].imm.value; | |
2392 | int64_t val | |
2393 | = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2394 | ||
2395 | if ((immr == 0 && imms == val) || immr == imms + 1) | |
2396 | { | |
2397 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2398 | inst->operands[2].imm.value = val - imms; | |
2399 | return 1; | |
2400 | } | |
2401 | ||
2402 | return 0; | |
2403 | } | |
2404 | ||
2405 | /* CINC <Wd>, <Wn>, <cond> | |
2406 | is equivalent to: | |
68a64283 YZ |
2407 | CSINC <Wd>, <Wn>, <Wn>, invert(<cond>) |
2408 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2409 | |
2410 | static int | |
2411 | convert_from_csel (aarch64_inst *inst) | |
2412 | { | |
68a64283 YZ |
2413 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno |
2414 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2415 | { |
2416 | copy_operand_info (inst, 2, 3); | |
2417 | inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond); | |
2418 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2419 | return 1; | |
2420 | } | |
2421 | return 0; | |
2422 | } | |
2423 | ||
2424 | /* CSET <Wd>, <cond> | |
2425 | is equivalent to: | |
68a64283 YZ |
2426 | CSINC <Wd>, WZR, WZR, invert(<cond>) |
2427 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2428 | |
2429 | static int | |
2430 | convert_csinc_to_cset (aarch64_inst *inst) | |
2431 | { | |
2432 | if (inst->operands[1].reg.regno == 0x1f | |
68a64283 YZ |
2433 | && inst->operands[2].reg.regno == 0x1f |
2434 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2435 | { |
2436 | copy_operand_info (inst, 1, 3); | |
2437 | inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond); | |
2438 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2439 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2440 | return 1; | |
2441 | } | |
2442 | return 0; | |
2443 | } | |
2444 | ||
2445 | /* MOV <Wd>, #<imm> | |
2446 | is equivalent to: | |
2447 | MOVZ <Wd>, #<imm16>, LSL #<shift>. | |
2448 | ||
2449 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2450 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2451 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2452 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2453 | machine-instruction mnemonic must be used. */ | |
2454 | ||
2455 | static int | |
2456 | convert_movewide_to_mov (aarch64_inst *inst) | |
2457 | { | |
2458 | uint64_t value = inst->operands[1].imm.value; | |
2459 | /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */ | |
2460 | if (value == 0 && inst->operands[1].shifter.amount != 0) | |
2461 | return 0; | |
2462 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2463 | inst->operands[1].shifter.kind = AARCH64_MOD_NONE; | |
2464 | value <<= inst->operands[1].shifter.amount; | |
2465 | /* As an alias convertor, it has to be clear that the INST->OPCODE | |
2466 | is the opcode of the real instruction. */ | |
2467 | if (inst->opcode->op == OP_MOVN) | |
2468 | { | |
2469 | int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2470 | value = ~value; | |
2471 | /* A MOVN has an immediate that could be encoded by MOVZ. */ | |
535b785f | 2472 | if (aarch64_wide_constant_p (value, is32, NULL)) |
a06ea964 NC |
2473 | return 0; |
2474 | } | |
2475 | inst->operands[1].imm.value = value; | |
2476 | inst->operands[1].shifter.amount = 0; | |
2477 | return 1; | |
2478 | } | |
2479 | ||
2480 | /* MOV <Wd>, #<imm> | |
2481 | is equivalent to: | |
2482 | ORR <Wd>, WZR, #<imm>. | |
2483 | ||
2484 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2485 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2486 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2487 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2488 | machine-instruction mnemonic must be used. */ | |
2489 | ||
2490 | static int | |
2491 | convert_movebitmask_to_mov (aarch64_inst *inst) | |
2492 | { | |
2493 | int is32; | |
2494 | uint64_t value; | |
2495 | ||
2496 | /* Should have been assured by the base opcode value. */ | |
2497 | assert (inst->operands[1].reg.regno == 0x1f); | |
2498 | copy_operand_info (inst, 1, 2); | |
2499 | is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2500 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2501 | value = inst->operands[1].imm.value; | |
2502 | /* ORR has an immediate that could be generated by a MOVZ or MOVN | |
2503 | instruction. */ | |
2504 | if (inst->operands[0].reg.regno != 0x1f | |
535b785f AM |
2505 | && (aarch64_wide_constant_p (value, is32, NULL) |
2506 | || aarch64_wide_constant_p (~value, is32, NULL))) | |
a06ea964 NC |
2507 | return 0; |
2508 | ||
2509 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2510 | return 1; | |
2511 | } | |
2512 | ||
2513 | /* Some alias opcodes are disassembled by being converted from their real-form. | |
2514 | N.B. INST->OPCODE is the real opcode rather than the alias. */ | |
2515 | ||
2516 | static int | |
2517 | convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias) | |
2518 | { | |
2519 | switch (alias->op) | |
2520 | { | |
2521 | case OP_ASR_IMM: | |
2522 | case OP_LSR_IMM: | |
2523 | return convert_bfm_to_sr (inst); | |
2524 | case OP_LSL_IMM: | |
2525 | return convert_ubfm_to_lsl (inst); | |
2526 | case OP_CINC: | |
2527 | case OP_CINV: | |
2528 | case OP_CNEG: | |
2529 | return convert_from_csel (inst); | |
2530 | case OP_CSET: | |
2531 | case OP_CSETM: | |
2532 | return convert_csinc_to_cset (inst); | |
2533 | case OP_UBFX: | |
2534 | case OP_BFXIL: | |
2535 | case OP_SBFX: | |
2536 | return convert_bfm_to_bfx (inst); | |
2537 | case OP_SBFIZ: | |
2538 | case OP_BFI: | |
2539 | case OP_UBFIZ: | |
2540 | return convert_bfm_to_bfi (inst); | |
d685192a MW |
2541 | case OP_BFC: |
2542 | return convert_bfm_to_bfc (inst); | |
a06ea964 NC |
2543 | case OP_MOV_V: |
2544 | return convert_orr_to_mov (inst); | |
2545 | case OP_MOV_IMM_WIDE: | |
2546 | case OP_MOV_IMM_WIDEN: | |
2547 | return convert_movewide_to_mov (inst); | |
2548 | case OP_MOV_IMM_LOG: | |
2549 | return convert_movebitmask_to_mov (inst); | |
2550 | case OP_ROR_IMM: | |
2551 | return convert_extr_to_ror (inst); | |
e30181a5 YZ |
2552 | case OP_SXTL: |
2553 | case OP_SXTL2: | |
2554 | case OP_UXTL: | |
2555 | case OP_UXTL2: | |
2556 | return convert_shll_to_xtl (inst); | |
a06ea964 NC |
2557 | default: |
2558 | return 0; | |
2559 | } | |
2560 | } | |
2561 | ||
561a72d4 TC |
2562 | static bfd_boolean |
2563 | aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, | |
2564 | aarch64_inst *, int, aarch64_operand_error *errors); | |
a06ea964 NC |
2565 | |
2566 | /* Given the instruction information in *INST, check if the instruction has | |
2567 | any alias form that can be used to represent *INST. If the answer is yes, | |
2568 | update *INST to be in the form of the determined alias. */ | |
2569 | ||
2570 | /* In the opcode description table, the following flags are used in opcode | |
2571 | entries to help establish the relations between the real and alias opcodes: | |
2572 | ||
2573 | F_ALIAS: opcode is an alias | |
2574 | F_HAS_ALIAS: opcode has alias(es) | |
2575 | F_P1 | |
2576 | F_P2 | |
2577 | F_P3: Disassembly preference priority 1-3 (the larger the | |
2578 | higher). If nothing is specified, it is the priority | |
2579 | 0 by default, i.e. the lowest priority. | |
2580 | ||
2581 | Although the relation between the machine and the alias instructions are not | |
2582 | explicitly described, it can be easily determined from the base opcode | |
2583 | values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode | |
2584 | description entries: | |
2585 | ||
2586 | The mask of an alias opcode must be equal to or a super-set (i.e. more | |
2587 | constrained) of that of the aliased opcode; so is the base opcode value. | |
2588 | ||
2589 | if (opcode_has_alias (real) && alias_opcode_p (opcode) | |
2590 | && (opcode->mask & real->mask) == real->mask | |
2591 | && (real->mask & opcode->opcode) == (real->mask & real->opcode)) | |
2592 | then OPCODE is an alias of, and only of, the REAL instruction | |
2593 | ||
2594 | The alias relationship is forced flat-structured to keep related algorithm | |
2595 | simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS. | |
2596 | ||
2597 | During the disassembling, the decoding decision tree (in | |
2598 | opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry; | |
2599 | if the decoding of such a machine instruction succeeds (and -Mno-aliases is | |
2600 | not specified), the disassembler will check whether there is any alias | |
2601 | instruction exists for this real instruction. If there is, the disassembler | |
2602 | will try to disassemble the 32-bit binary again using the alias's rule, or | |
2603 | try to convert the IR to the form of the alias. In the case of the multiple | |
2604 | aliases, the aliases are tried one by one from the highest priority | |
2605 | (currently the flag F_P3) to the lowest priority (no priority flag), and the | |
2606 | first succeeds first adopted. | |
2607 | ||
2608 | You may ask why there is a need for the conversion of IR from one form to | |
2609 | another in handling certain aliases. This is because on one hand it avoids | |
2610 | adding more operand code to handle unusual encoding/decoding; on other | |
2611 | hand, during the disassembling, the conversion is an effective approach to | |
2612 | check the condition of an alias (as an alias may be adopted only if certain | |
2613 | conditions are met). | |
2614 | ||
2615 | In order to speed up the alias opcode lookup, aarch64-gen has preprocessed | |
2616 | aarch64_opcode_table and generated aarch64_find_alias_opcode and | |
2617 | aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */ | |
2618 | ||
2619 | static void | |
561a72d4 TC |
2620 | determine_disassembling_preference (struct aarch64_inst *inst, |
2621 | aarch64_operand_error *errors) | |
a06ea964 NC |
2622 | { |
2623 | const aarch64_opcode *opcode; | |
2624 | const aarch64_opcode *alias; | |
2625 | ||
2626 | opcode = inst->opcode; | |
2627 | ||
2628 | /* This opcode does not have an alias, so use itself. */ | |
535b785f | 2629 | if (!opcode_has_alias (opcode)) |
a06ea964 NC |
2630 | return; |
2631 | ||
2632 | alias = aarch64_find_alias_opcode (opcode); | |
2633 | assert (alias); | |
2634 | ||
2635 | #ifdef DEBUG_AARCH64 | |
2636 | if (debug_dump) | |
2637 | { | |
2638 | const aarch64_opcode *tmp = alias; | |
2639 | printf ("#### LIST orderd: "); | |
2640 | while (tmp) | |
2641 | { | |
2642 | printf ("%s, ", tmp->name); | |
2643 | tmp = aarch64_find_next_alias_opcode (tmp); | |
2644 | } | |
2645 | printf ("\n"); | |
2646 | } | |
2647 | #endif /* DEBUG_AARCH64 */ | |
2648 | ||
2649 | for (; alias; alias = aarch64_find_next_alias_opcode (alias)) | |
2650 | { | |
2651 | DEBUG_TRACE ("try %s", alias->name); | |
35822b38 | 2652 | assert (alias_opcode_p (alias) || opcode_has_alias (opcode)); |
a06ea964 NC |
2653 | |
2654 | /* An alias can be a pseudo opcode which will never be used in the | |
2655 | disassembly, e.g. BIC logical immediate is such a pseudo opcode | |
2656 | aliasing AND. */ | |
2657 | if (pseudo_opcode_p (alias)) | |
2658 | { | |
2659 | DEBUG_TRACE ("skip pseudo %s", alias->name); | |
2660 | continue; | |
2661 | } | |
2662 | ||
2663 | if ((inst->value & alias->mask) != alias->opcode) | |
2664 | { | |
2665 | DEBUG_TRACE ("skip %s as base opcode not match", alias->name); | |
2666 | continue; | |
2667 | } | |
2668 | /* No need to do any complicated transformation on operands, if the alias | |
2669 | opcode does not have any operand. */ | |
2670 | if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value) | |
2671 | { | |
2672 | DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name); | |
2673 | aarch64_replace_opcode (inst, alias); | |
2674 | return; | |
2675 | } | |
2676 | if (alias->flags & F_CONV) | |
2677 | { | |
2678 | aarch64_inst copy; | |
2679 | memcpy (©, inst, sizeof (aarch64_inst)); | |
2680 | /* ALIAS is the preference as long as the instruction can be | |
2681 | successfully converted to the form of ALIAS. */ | |
2682 | if (convert_to_alias (©, alias) == 1) | |
2683 | { | |
2684 | aarch64_replace_opcode (©, alias); | |
2685 | assert (aarch64_match_operands_constraint (©, NULL)); | |
2686 | DEBUG_TRACE ("succeed with %s via conversion", alias->name); | |
2687 | memcpy (inst, ©, sizeof (aarch64_inst)); | |
2688 | return; | |
2689 | } | |
2690 | } | |
2691 | else | |
2692 | { | |
2693 | /* Directly decode the alias opcode. */ | |
2694 | aarch64_inst temp; | |
2695 | memset (&temp, '\0', sizeof (aarch64_inst)); | |
561a72d4 | 2696 | if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1) |
a06ea964 NC |
2697 | { |
2698 | DEBUG_TRACE ("succeed with %s via direct decoding", alias->name); | |
2699 | memcpy (inst, &temp, sizeof (aarch64_inst)); | |
2700 | return; | |
2701 | } | |
2702 | } | |
2703 | } | |
2704 | } | |
2705 | ||
116b6019 RS |
2706 | /* Some instructions (including all SVE ones) use the instruction class |
2707 | to describe how a qualifiers_list index is represented in the instruction | |
2708 | encoding. If INST is such an instruction, decode the appropriate fields | |
2709 | and fill in the operand qualifiers accordingly. Return true if no | |
2710 | problems are found. */ | |
2711 | ||
2712 | static bfd_boolean | |
2713 | aarch64_decode_variant_using_iclass (aarch64_inst *inst) | |
2714 | { | |
2715 | int i, variant; | |
2716 | ||
2717 | variant = 0; | |
2718 | switch (inst->opcode->iclass) | |
2719 | { | |
2720 | case sve_cpy: | |
2721 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14); | |
2722 | break; | |
2723 | ||
2724 | case sve_index: | |
582e12bf RS |
2725 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); |
2726 | if ((i & 31) == 0) | |
116b6019 RS |
2727 | return FALSE; |
2728 | while ((i & 1) == 0) | |
2729 | { | |
2730 | i >>= 1; | |
2731 | variant += 1; | |
2732 | } | |
2733 | break; | |
2734 | ||
2735 | case sve_limm: | |
2736 | /* Pick the smallest applicable element size. */ | |
2737 | if ((inst->value & 0x20600) == 0x600) | |
2738 | variant = 0; | |
2739 | else if ((inst->value & 0x20400) == 0x400) | |
2740 | variant = 1; | |
2741 | else if ((inst->value & 0x20000) == 0) | |
2742 | variant = 2; | |
2743 | else | |
2744 | variant = 3; | |
2745 | break; | |
2746 | ||
2747 | case sve_misc: | |
2748 | /* sve_misc instructions have only a single variant. */ | |
2749 | break; | |
2750 | ||
2751 | case sve_movprfx: | |
2752 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16); | |
2753 | break; | |
2754 | ||
2755 | case sve_pred_zm: | |
2756 | variant = extract_field (FLD_SVE_M_4, inst->value, 0); | |
2757 | break; | |
2758 | ||
2759 | case sve_shift_pred: | |
2760 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8); | |
2761 | sve_shift: | |
2762 | if (i == 0) | |
2763 | return FALSE; | |
2764 | while (i != 1) | |
2765 | { | |
2766 | i >>= 1; | |
2767 | variant += 1; | |
2768 | } | |
2769 | break; | |
2770 | ||
2771 | case sve_shift_unpred: | |
2772 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19); | |
2773 | goto sve_shift; | |
2774 | ||
2775 | case sve_size_bhs: | |
2776 | variant = extract_field (FLD_size, inst->value, 0); | |
2777 | if (variant >= 3) | |
2778 | return FALSE; | |
2779 | break; | |
2780 | ||
2781 | case sve_size_bhsd: | |
2782 | variant = extract_field (FLD_size, inst->value, 0); | |
2783 | break; | |
2784 | ||
2785 | case sve_size_hsd: | |
2786 | i = extract_field (FLD_size, inst->value, 0); | |
2787 | if (i < 1) | |
2788 | return FALSE; | |
2789 | variant = i - 1; | |
2790 | break; | |
2791 | ||
2792 | case sve_size_sd: | |
2793 | variant = extract_field (FLD_SVE_sz, inst->value, 0); | |
2794 | break; | |
2795 | ||
2796 | default: | |
2797 | /* No mapping between instruction class and qualifiers. */ | |
2798 | return TRUE; | |
2799 | } | |
2800 | ||
2801 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2802 | inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i]; | |
2803 | return TRUE; | |
2804 | } | |
a06ea964 NC |
2805 | /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding |
2806 | fails, which meanes that CODE is not an instruction of OPCODE; otherwise | |
2807 | return 1. | |
2808 | ||
2809 | If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be | |
2810 | determined and used to disassemble CODE; this is done just before the | |
2811 | return. */ | |
2812 | ||
561a72d4 | 2813 | static bfd_boolean |
a06ea964 | 2814 | aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, |
561a72d4 TC |
2815 | aarch64_inst *inst, int noaliases_p, |
2816 | aarch64_operand_error *errors) | |
a06ea964 NC |
2817 | { |
2818 | int i; | |
2819 | ||
2820 | DEBUG_TRACE ("enter with %s", opcode->name); | |
2821 | ||
2822 | assert (opcode && inst); | |
2823 | ||
b3ac5c6c TC |
2824 | /* Clear inst. */ |
2825 | memset (inst, '\0', sizeof (aarch64_inst)); | |
2826 | ||
a06ea964 NC |
2827 | /* Check the base opcode. */ |
2828 | if ((code & opcode->mask) != (opcode->opcode & opcode->mask)) | |
2829 | { | |
2830 | DEBUG_TRACE ("base opcode match FAIL"); | |
2831 | goto decode_fail; | |
2832 | } | |
2833 | ||
a06ea964 NC |
2834 | inst->opcode = opcode; |
2835 | inst->value = code; | |
2836 | ||
2837 | /* Assign operand codes and indexes. */ | |
2838 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2839 | { | |
2840 | if (opcode->operands[i] == AARCH64_OPND_NIL) | |
2841 | break; | |
2842 | inst->operands[i].type = opcode->operands[i]; | |
2843 | inst->operands[i].idx = i; | |
2844 | } | |
2845 | ||
2846 | /* Call the opcode decoder indicated by flags. */ | |
2847 | if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0) | |
2848 | { | |
2849 | DEBUG_TRACE ("opcode flag-based decoder FAIL"); | |
2850 | goto decode_fail; | |
2851 | } | |
2852 | ||
116b6019 RS |
2853 | /* Possibly use the instruction class to determine the correct |
2854 | qualifier. */ | |
2855 | if (!aarch64_decode_variant_using_iclass (inst)) | |
2856 | { | |
2857 | DEBUG_TRACE ("iclass-based decoder FAIL"); | |
2858 | goto decode_fail; | |
2859 | } | |
2860 | ||
a06ea964 NC |
2861 | /* Call operand decoders. */ |
2862 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2863 | { | |
2864 | const aarch64_operand *opnd; | |
2865 | enum aarch64_opnd type; | |
4bd13cde | 2866 | |
a06ea964 NC |
2867 | type = opcode->operands[i]; |
2868 | if (type == AARCH64_OPND_NIL) | |
2869 | break; | |
2870 | opnd = &aarch64_operands[type]; | |
2871 | if (operand_has_extractor (opnd) | |
561a72d4 TC |
2872 | && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst, |
2873 | errors))) | |
a06ea964 NC |
2874 | { |
2875 | DEBUG_TRACE ("operand decoder FAIL at operand %d", i); | |
2876 | goto decode_fail; | |
2877 | } | |
2878 | } | |
2879 | ||
4bd13cde NC |
2880 | /* If the opcode has a verifier, then check it now. */ |
2881 | if (opcode->verifier && ! opcode->verifier (opcode, code)) | |
2882 | { | |
2883 | DEBUG_TRACE ("operand verifier FAIL"); | |
2884 | goto decode_fail; | |
2885 | } | |
2886 | ||
a06ea964 NC |
2887 | /* Match the qualifiers. */ |
2888 | if (aarch64_match_operands_constraint (inst, NULL) == 1) | |
2889 | { | |
2890 | /* Arriving here, the CODE has been determined as a valid instruction | |
2891 | of OPCODE and *INST has been filled with information of this OPCODE | |
2892 | instruction. Before the return, check if the instruction has any | |
2893 | alias and should be disassembled in the form of its alias instead. | |
2894 | If the answer is yes, *INST will be updated. */ | |
2895 | if (!noaliases_p) | |
561a72d4 | 2896 | determine_disassembling_preference (inst, errors); |
a06ea964 | 2897 | DEBUG_TRACE ("SUCCESS"); |
561a72d4 | 2898 | return TRUE; |
a06ea964 NC |
2899 | } |
2900 | else | |
2901 | { | |
2902 | DEBUG_TRACE ("constraint matching FAIL"); | |
2903 | } | |
2904 | ||
2905 | decode_fail: | |
561a72d4 | 2906 | return FALSE; |
a06ea964 NC |
2907 | } |
2908 | \f | |
2909 | /* This does some user-friendly fix-up to *INST. It is currently focus on | |
2910 | the adjustment of qualifiers to help the printed instruction | |
2911 | recognized/understood more easily. */ | |
2912 | ||
2913 | static void | |
2914 | user_friendly_fixup (aarch64_inst *inst) | |
2915 | { | |
2916 | switch (inst->opcode->iclass) | |
2917 | { | |
2918 | case testbranch: | |
2919 | /* TBNZ Xn|Wn, #uimm6, label | |
2920 | Test and Branch Not Zero: conditionally jumps to label if bit number | |
2921 | uimm6 in register Xn is not zero. The bit number implies the width of | |
2922 | the register, which may be written and should be disassembled as Wn if | |
2923 | uimm is less than 32. Limited to a branch offset range of +/- 32KiB. | |
2924 | */ | |
2925 | if (inst->operands[1].imm.value < 32) | |
2926 | inst->operands[0].qualifier = AARCH64_OPND_QLF_W; | |
2927 | break; | |
2928 | default: break; | |
2929 | } | |
2930 | } | |
2931 | ||
43cdf5ae YQ |
2932 | /* Decode INSN and fill in *INST the instruction information. An alias |
2933 | opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on | |
2934 | success. */ | |
a06ea964 | 2935 | |
36f4aab1 | 2936 | int |
43cdf5ae | 2937 | aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, |
561a72d4 TC |
2938 | bfd_boolean noaliases_p, |
2939 | aarch64_operand_error *errors) | |
a06ea964 NC |
2940 | { |
2941 | const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); | |
2942 | ||
2943 | #ifdef DEBUG_AARCH64 | |
2944 | if (debug_dump) | |
2945 | { | |
2946 | const aarch64_opcode *tmp = opcode; | |
2947 | printf ("\n"); | |
2948 | DEBUG_TRACE ("opcode lookup:"); | |
2949 | while (tmp != NULL) | |
2950 | { | |
2951 | aarch64_verbose (" %s", tmp->name); | |
2952 | tmp = aarch64_find_next_opcode (tmp); | |
2953 | } | |
2954 | } | |
2955 | #endif /* DEBUG_AARCH64 */ | |
2956 | ||
2957 | /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot | |
2958 | distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same | |
2959 | opcode field and value, apart from the difference that one of them has an | |
2960 | extra field as part of the opcode, but such a field is used for operand | |
2961 | encoding in other opcode(s) ('immh' in the case of the example). */ | |
2962 | while (opcode != NULL) | |
2963 | { | |
2964 | /* But only one opcode can be decoded successfully for, as the | |
2965 | decoding routine will check the constraint carefully. */ | |
561a72d4 | 2966 | if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1) |
a06ea964 NC |
2967 | return ERR_OK; |
2968 | opcode = aarch64_find_next_opcode (opcode); | |
2969 | } | |
2970 | ||
2971 | return ERR_UND; | |
2972 | } | |
2973 | ||
2974 | /* Print operands. */ | |
2975 | ||
2976 | static void | |
2977 | print_operands (bfd_vma pc, const aarch64_opcode *opcode, | |
2978 | const aarch64_opnd_info *opnds, struct disassemble_info *info) | |
2979 | { | |
2980 | int i, pcrel_p, num_printed; | |
7d02540a | 2981 | char *notes = NULL; |
a06ea964 NC |
2982 | for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i) |
2983 | { | |
0d2f91fe | 2984 | char str[128]; |
a06ea964 NC |
2985 | /* We regard the opcode operand info more, however we also look into |
2986 | the inst->operands to support the disassembling of the optional | |
2987 | operand. | |
2988 | The two operand code should be the same in all cases, apart from | |
2989 | when the operand can be optional. */ | |
2990 | if (opcode->operands[i] == AARCH64_OPND_NIL | |
2991 | || opnds[i].type == AARCH64_OPND_NIL) | |
2992 | break; | |
2993 | ||
2994 | /* Generate the operand string in STR. */ | |
0d2f91fe | 2995 | aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p, |
7d02540a | 2996 | &info->target, ¬es); |
a06ea964 NC |
2997 | |
2998 | /* Print the delimiter (taking account of omitted operand(s)). */ | |
2999 | if (str[0] != '\0') | |
3000 | (*info->fprintf_func) (info->stream, "%s", | |
3001 | num_printed++ == 0 ? "\t" : ", "); | |
3002 | ||
3003 | /* Print the operand. */ | |
3004 | if (pcrel_p) | |
3005 | (*info->print_address_func) (info->target, info); | |
3006 | else | |
3007 | (*info->fprintf_func) (info->stream, "%s", str); | |
3008 | } | |
7d02540a TC |
3009 | |
3010 | if (notes && !no_notes) | |
3011 | (*info->fprintf_func) (info->stream, "\t; note: %s", notes); | |
a06ea964 NC |
3012 | } |
3013 | ||
bb7eff52 RS |
3014 | /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */ |
3015 | ||
3016 | static void | |
3017 | remove_dot_suffix (char *name, const aarch64_inst *inst) | |
3018 | { | |
3019 | char *ptr; | |
3020 | size_t len; | |
3021 | ||
3022 | ptr = strchr (inst->opcode->name, '.'); | |
3023 | assert (ptr && inst->cond); | |
3024 | len = ptr - inst->opcode->name; | |
3025 | assert (len < 8); | |
3026 | strncpy (name, inst->opcode->name, len); | |
3027 | name[len] = '\0'; | |
3028 | } | |
3029 | ||
a06ea964 NC |
3030 | /* Print the instruction mnemonic name. */ |
3031 | ||
3032 | static void | |
3033 | print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info) | |
3034 | { | |
3035 | if (inst->opcode->flags & F_COND) | |
3036 | { | |
3037 | /* For instructions that are truly conditionally executed, e.g. b.cond, | |
3038 | prepare the full mnemonic name with the corresponding condition | |
3039 | suffix. */ | |
bb7eff52 RS |
3040 | char name[8]; |
3041 | ||
3042 | remove_dot_suffix (name, inst); | |
a06ea964 NC |
3043 | (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]); |
3044 | } | |
3045 | else | |
3046 | (*info->fprintf_func) (info->stream, "%s", inst->opcode->name); | |
3047 | } | |
3048 | ||
bb7eff52 RS |
3049 | /* Decide whether we need to print a comment after the operands of |
3050 | instruction INST. */ | |
3051 | ||
3052 | static void | |
3053 | print_comment (const aarch64_inst *inst, struct disassemble_info *info) | |
3054 | { | |
3055 | if (inst->opcode->flags & F_COND) | |
3056 | { | |
3057 | char name[8]; | |
3058 | unsigned int i, num_conds; | |
3059 | ||
3060 | remove_dot_suffix (name, inst); | |
3061 | num_conds = ARRAY_SIZE (inst->cond->names); | |
3062 | for (i = 1; i < num_conds && inst->cond->names[i]; ++i) | |
3063 | (*info->fprintf_func) (info->stream, "%s %s.%s", | |
3064 | i == 1 ? " //" : ",", | |
3065 | name, inst->cond->names[i]); | |
3066 | } | |
3067 | } | |
3068 | ||
a06ea964 NC |
3069 | /* Print the instruction according to *INST. */ |
3070 | ||
3071 | static void | |
3072 | print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, | |
3073 | struct disassemble_info *info) | |
3074 | { | |
3075 | print_mnemonic_name (inst, info); | |
3076 | print_operands (pc, inst->opcode, inst->operands, info); | |
bb7eff52 | 3077 | print_comment (inst, info); |
a06ea964 NC |
3078 | } |
3079 | ||
3080 | /* Entry-point of the instruction disassembler and printer. */ | |
3081 | ||
3082 | static void | |
3083 | print_insn_aarch64_word (bfd_vma pc, | |
3084 | uint32_t word, | |
561a72d4 TC |
3085 | struct disassemble_info *info, |
3086 | aarch64_operand_error *errors) | |
a06ea964 NC |
3087 | { |
3088 | static const char *err_msg[6] = | |
3089 | { | |
3090 | [ERR_OK] = "_", | |
3091 | [-ERR_UND] = "undefined", | |
3092 | [-ERR_UNP] = "unpredictable", | |
3093 | [-ERR_NYI] = "NYI" | |
3094 | }; | |
3095 | ||
3096 | int ret; | |
3097 | aarch64_inst inst; | |
3098 | ||
3099 | info->insn_info_valid = 1; | |
3100 | info->branch_delay_insns = 0; | |
3101 | info->data_size = 0; | |
3102 | info->target = 0; | |
3103 | info->target2 = 0; | |
3104 | ||
3105 | if (info->flags & INSN_HAS_RELOC) | |
3106 | /* If the instruction has a reloc associated with it, then | |
3107 | the offset field in the instruction will actually be the | |
3108 | addend for the reloc. (If we are using REL type relocs). | |
3109 | In such cases, we can ignore the pc when computing | |
3110 | addresses, since the addend is not currently pc-relative. */ | |
3111 | pc = 0; | |
3112 | ||
561a72d4 | 3113 | ret = aarch64_decode_insn (word, &inst, no_aliases, errors); |
a06ea964 NC |
3114 | |
3115 | if (((word >> 21) & 0x3ff) == 1) | |
3116 | { | |
3117 | /* RESERVED for ALES. */ | |
3118 | assert (ret != ERR_OK); | |
3119 | ret = ERR_NYI; | |
3120 | } | |
3121 | ||
3122 | switch (ret) | |
3123 | { | |
3124 | case ERR_UND: | |
3125 | case ERR_UNP: | |
3126 | case ERR_NYI: | |
3127 | /* Handle undefined instructions. */ | |
3128 | info->insn_type = dis_noninsn; | |
3129 | (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s", | |
3130 | word, err_msg[-ret]); | |
3131 | break; | |
3132 | case ERR_OK: | |
3133 | user_friendly_fixup (&inst); | |
3134 | print_aarch64_insn (pc, &inst, info); | |
3135 | break; | |
3136 | default: | |
3137 | abort (); | |
3138 | } | |
3139 | } | |
3140 | ||
3141 | /* Disallow mapping symbols ($x, $d etc) from | |
3142 | being displayed in symbol relative addresses. */ | |
3143 | ||
3144 | bfd_boolean | |
3145 | aarch64_symbol_is_valid (asymbol * sym, | |
3146 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
3147 | { | |
3148 | const char * name; | |
3149 | ||
3150 | if (sym == NULL) | |
3151 | return FALSE; | |
3152 | ||
3153 | name = bfd_asymbol_name (sym); | |
3154 | ||
3155 | return name | |
3156 | && (name[0] != '$' | |
3157 | || (name[1] != 'x' && name[1] != 'd') | |
3158 | || (name[2] != '\0' && name[2] != '.')); | |
3159 | } | |
3160 | ||
3161 | /* Print data bytes on INFO->STREAM. */ | |
3162 | ||
3163 | static void | |
3164 | print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, | |
3165 | uint32_t word, | |
561a72d4 TC |
3166 | struct disassemble_info *info, |
3167 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
3168 | { |
3169 | switch (info->bytes_per_chunk) | |
3170 | { | |
3171 | case 1: | |
3172 | info->fprintf_func (info->stream, ".byte\t0x%02x", word); | |
3173 | break; | |
3174 | case 2: | |
3175 | info->fprintf_func (info->stream, ".short\t0x%04x", word); | |
3176 | break; | |
3177 | case 4: | |
3178 | info->fprintf_func (info->stream, ".word\t0x%08x", word); | |
3179 | break; | |
3180 | default: | |
3181 | abort (); | |
3182 | } | |
3183 | } | |
3184 | ||
3185 | /* Try to infer the code or data type from a symbol. | |
3186 | Returns nonzero if *MAP_TYPE was set. */ | |
3187 | ||
3188 | static int | |
3189 | get_sym_code_type (struct disassemble_info *info, int n, | |
3190 | enum map_type *map_type) | |
3191 | { | |
3192 | elf_symbol_type *es; | |
3193 | unsigned int type; | |
3194 | const char *name; | |
3195 | ||
4c5ae11b RL |
3196 | /* If the symbol is in a different section, ignore it. */ |
3197 | if (info->section != NULL && info->section != info->symtab[n]->section) | |
3198 | return FALSE; | |
3199 | ||
a06ea964 NC |
3200 | es = *(elf_symbol_type **)(info->symtab + n); |
3201 | type = ELF_ST_TYPE (es->internal_elf_sym.st_info); | |
3202 | ||
3203 | /* If the symbol has function type then use that. */ | |
3204 | if (type == STT_FUNC) | |
3205 | { | |
3206 | *map_type = MAP_INSN; | |
3207 | return TRUE; | |
3208 | } | |
3209 | ||
3210 | /* Check for mapping symbols. */ | |
3211 | name = bfd_asymbol_name(info->symtab[n]); | |
3212 | if (name[0] == '$' | |
3213 | && (name[1] == 'x' || name[1] == 'd') | |
3214 | && (name[2] == '\0' || name[2] == '.')) | |
3215 | { | |
3216 | *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA); | |
3217 | return TRUE; | |
3218 | } | |
3219 | ||
3220 | return FALSE; | |
3221 | } | |
3222 | ||
3223 | /* Entry-point of the AArch64 disassembler. */ | |
3224 | ||
3225 | int | |
3226 | print_insn_aarch64 (bfd_vma pc, | |
3227 | struct disassemble_info *info) | |
3228 | { | |
3229 | bfd_byte buffer[INSNLEN]; | |
3230 | int status; | |
561a72d4 TC |
3231 | void (*printer) (bfd_vma, uint32_t, struct disassemble_info *, |
3232 | aarch64_operand_error *); | |
a06ea964 NC |
3233 | bfd_boolean found = FALSE; |
3234 | unsigned int size = 4; | |
3235 | unsigned long data; | |
561a72d4 | 3236 | aarch64_operand_error errors; |
a06ea964 NC |
3237 | |
3238 | if (info->disassembler_options) | |
3239 | { | |
3240 | set_default_aarch64_dis_options (info); | |
3241 | ||
3242 | parse_aarch64_dis_options (info->disassembler_options); | |
3243 | ||
3244 | /* To avoid repeated parsing of these options, we remove them here. */ | |
3245 | info->disassembler_options = NULL; | |
3246 | } | |
3247 | ||
3248 | /* Aarch64 instructions are always little-endian */ | |
3249 | info->endian_code = BFD_ENDIAN_LITTLE; | |
3250 | ||
3251 | /* First check the full symtab for a mapping symbol, even if there | |
3252 | are no usable non-mapping symbols for this address. */ | |
3253 | if (info->symtab_size != 0 | |
3254 | && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) | |
3255 | { | |
3256 | enum map_type type = MAP_INSN; | |
3257 | int last_sym = -1; | |
3258 | bfd_vma addr; | |
3259 | int n; | |
3260 | ||
3261 | if (pc <= last_mapping_addr) | |
3262 | last_mapping_sym = -1; | |
3263 | ||
3264 | /* Start scanning at the start of the function, or wherever | |
3265 | we finished last time. */ | |
3266 | n = info->symtab_pos + 1; | |
3267 | if (n < last_mapping_sym) | |
3268 | n = last_mapping_sym; | |
3269 | ||
3270 | /* Scan up to the location being disassembled. */ | |
3271 | for (; n < info->symtab_size; n++) | |
3272 | { | |
3273 | addr = bfd_asymbol_value (info->symtab[n]); | |
3274 | if (addr > pc) | |
3275 | break; | |
4c5ae11b | 3276 | if (get_sym_code_type (info, n, &type)) |
a06ea964 NC |
3277 | { |
3278 | last_sym = n; | |
3279 | found = TRUE; | |
3280 | } | |
3281 | } | |
3282 | ||
3283 | if (!found) | |
3284 | { | |
3285 | n = info->symtab_pos; | |
3286 | if (n < last_mapping_sym) | |
3287 | n = last_mapping_sym; | |
3288 | ||
3289 | /* No mapping symbol found at this address. Look backwards | |
3290 | for a preceeding one. */ | |
3291 | for (; n >= 0; n--) | |
3292 | { | |
3293 | if (get_sym_code_type (info, n, &type)) | |
3294 | { | |
3295 | last_sym = n; | |
3296 | found = TRUE; | |
3297 | break; | |
3298 | } | |
3299 | } | |
3300 | } | |
3301 | ||
3302 | last_mapping_sym = last_sym; | |
3303 | last_type = type; | |
3304 | ||
3305 | /* Look a little bit ahead to see if we should print out | |
3306 | less than four bytes of data. If there's a symbol, | |
3307 | mapping or otherwise, after two bytes then don't | |
3308 | print more. */ | |
3309 | if (last_type == MAP_DATA) | |
3310 | { | |
3311 | size = 4 - (pc & 3); | |
3312 | for (n = last_sym + 1; n < info->symtab_size; n++) | |
3313 | { | |
3314 | addr = bfd_asymbol_value (info->symtab[n]); | |
3315 | if (addr > pc) | |
3316 | { | |
3317 | if (addr - pc < size) | |
3318 | size = addr - pc; | |
3319 | break; | |
3320 | } | |
3321 | } | |
3322 | /* If the next symbol is after three bytes, we need to | |
3323 | print only part of the data, so that we can use either | |
3324 | .byte or .short. */ | |
3325 | if (size == 3) | |
3326 | size = (pc & 1) ? 1 : 2; | |
3327 | } | |
3328 | } | |
3329 | ||
3330 | if (last_type == MAP_DATA) | |
3331 | { | |
3332 | /* size was set above. */ | |
3333 | info->bytes_per_chunk = size; | |
3334 | info->display_endian = info->endian; | |
3335 | printer = print_insn_data; | |
3336 | } | |
3337 | else | |
3338 | { | |
3339 | info->bytes_per_chunk = size = INSNLEN; | |
3340 | info->display_endian = info->endian_code; | |
3341 | printer = print_insn_aarch64_word; | |
3342 | } | |
3343 | ||
3344 | status = (*info->read_memory_func) (pc, buffer, size, info); | |
3345 | if (status != 0) | |
3346 | { | |
3347 | (*info->memory_error_func) (status, pc, info); | |
3348 | return -1; | |
3349 | } | |
3350 | ||
3351 | data = bfd_get_bits (buffer, size * 8, | |
3352 | info->display_endian == BFD_ENDIAN_BIG); | |
3353 | ||
561a72d4 | 3354 | (*printer) (pc, data, info, &errors); |
a06ea964 NC |
3355 | |
3356 | return size; | |
3357 | } | |
3358 | \f | |
3359 | void | |
3360 | print_aarch64_disassembler_options (FILE *stream) | |
3361 | { | |
3362 | fprintf (stream, _("\n\ | |
3363 | The following AARCH64 specific disassembler options are supported for use\n\ | |
3364 | with the -M switch (multiple options should be separated by commas):\n")); | |
3365 | ||
3366 | fprintf (stream, _("\n\ | |
3367 | no-aliases Don't print instruction aliases.\n")); | |
3368 | ||
3369 | fprintf (stream, _("\n\ | |
3370 | aliases Do print instruction aliases.\n")); | |
3371 | ||
7d02540a TC |
3372 | fprintf (stream, _("\n\ |
3373 | no-notes Don't print instruction notes.\n")); | |
3374 | ||
3375 | fprintf (stream, _("\n\ | |
3376 | notes Do print instruction notes.\n")); | |
3377 | ||
a06ea964 NC |
3378 | #ifdef DEBUG_AARCH64 |
3379 | fprintf (stream, _("\n\ | |
3380 | debug_dump Temp switch for debug trace.\n")); | |
3381 | #endif /* DEBUG_AARCH64 */ | |
3382 | ||
3383 | fprintf (stream, _("\n")); | |
3384 | } |