[deliverable/binutils-gdb.git] / opcodes / aarch64-opc-2.c

/* This file is automatically generated by aarch64-gen.  Do not edit!  */
/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
   Contributed by ARM Ltd.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#include "sysdep.h"
#include "aarch64-opc.h"


const struct aarch64_operand aarch64_operands[] =
{
  {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"},
  {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
  {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
  {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
  {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
  {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
  {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
  {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
  {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
  {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"},
  {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"},
  {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"},
  {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
  {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
  {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
  {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
  {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
  {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
  {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"},
  {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
  {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
  {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
  {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit unsigned immediate with optional shift"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an 8-bit floating-point constant"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
  {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
  {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
  {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
  {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
  {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"},
  {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
  {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
};

/* Indexed by an enum aarch64_op enumerator, the value is the offset of
   the corresponding aarch64_opcode entry in the aarch64_opcode_table.  */

static const unsigned op_enum_table [] =
{
  0,
  828,
  829,
  830,
  833,
  834,
  835,
  836,
  837,
  831,
  832,
  838,
  839,
  861,
  862,
  863,
  866,
  867,
  868,
  869,
  870,
  864,
  865,
  871,
  872,
  915,
  916,
  917,
  918,
  12,
  627,
  628,
  1110,
  1112,
  1114,
  922,
  1113,
  1111,
  311,
  615,
  626,
  625,
  920,
  622,
  619,
  611,
  610,
  617,
  618,
  621,
  623,
  624,
  930,
  643,
  646,
  649,
  644,
  647,
  772,
  171,
  172,
  173,
  174,
  507,
  713,
  380,
  382,
  404,
  406,
};

/* Given the opcode enumerator OP, return the pointer to the corresponding
   opcode entry.  */

const aarch64_opcode *
aarch64_get_opcode (enum aarch64_op op)
{
  return aarch64_opcode_table + op_enum_table[op];
}
Commit	Line	Data
a06ea964	1	/* This file is automatically generated by aarch64-gen. Do not edit! */
b90efa5b	2	/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
a06ea964 NC	3	Contributed by ARM Ltd.
	4
	5	This file is part of the GNU opcodes library.
	6
	7	This library is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3, or (at your option)
	10	any later version.
	11
	12	It is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; see the file COPYING3. If not,
	19	see <http://www.gnu.org/licenses/>. */
	20
	21	#include "sysdep.h"
	22	#include "aarch64-opc.h"
	23
	24
	25	const struct aarch64_operand aarch64_operands[] =
	26	{
	27	{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"},
	28	{AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"},
	29	{AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
	30	{AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
	31	{AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
	32	{AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
	33	{AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
	34	{AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
	35	{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
	36	{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
	37	{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
ee804238	38	{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
a06ea964 NC	39	{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
	40	{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
	41	{AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
	42	{AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
	43	{AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
	44	{AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"},
	45	{AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"},
	46	{AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"},
	47	{AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"},
	48	{AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
	49	{AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
	50	{AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"},
	51	{AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
	52	{AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
	53	{AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"},
	54	{AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
	55	{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
	56	{AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
	57	{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
	58	{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
	59	{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
	60	{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
	61	{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
	62	{AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"},
	63	{AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"},
	64	{AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"},
	65	{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
	66	{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
	67	{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
	68	{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an 8-bit unsigned immediate with optional shift"},
	69	{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an 8-bit floating-point constant"},
	70	{AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"},
	71	{AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
	72	{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
	73	{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"},
	74	{AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"},
	75	{AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"},
	76	{AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"},
	77	{AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"},
	78	{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
	79	{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
	80	{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
	81	{AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
	82	{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
	83	{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
	84	{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
	85	{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
	86	{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
	87	{AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
	88	{AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
	89	{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
	90	{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
68a64283 YZ	91	{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a condition"},
68a64283 YZ	92	{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
a06ea964 NC	93	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT \| OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
	94	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT \| OPD_F_SHIFT_BY_2 \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
	95	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT \| OPD_F_SHIFT_BY_2 \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
	96	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
	97	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT \| OPD_F_SHIFT_BY_2 \| OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
	98	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
	99	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
	100	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
	101	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
	102	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
	103	{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
	104	{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
	105	{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
	106	{AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a system register"},
	107	{AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
	108	{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
	109	{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
9ed608f9	110	{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
a06ea964 NC	111	{AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
	112	{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
	113	{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
9ed608f9	114	{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
1e6f4800	115	{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER \| OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
a06ea964 NC	116	{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
	117	};
	118
	119	/* Indexed by an enum aarch64_op enumerator, the value is the offset of
	120	the corresponding aarch64_opcode entry in the aarch64_opcode_table. */
	121
	122	static const unsigned op_enum_table [] =
	123	{
	124	0,
4fd0a9fd	125	828,
b195470d	126	829,
b195470d	127	830,
b5b0f34c	128	833,
b5b0f34c MW	129	834,
b5b0f34c MW	130	835,
4fd0a9fd MW	131	836,
	132	837,
	133	831,
	134	832,
	135	838,
	136	839,
	137	861,
b195470d	138	862,
b195470d	139	863,
b5b0f34c	140	866,
b5b0f34c MW	141	867,
b5b0f34c MW	142	868,
4fd0a9fd MW	143	869,
	144	870,
	145	864,
	146	865,
	147	871,
	148	872,
	149	915,
	150	916,
	151	917,
	152	918,
b195470d	153	12,
4fd0a9fd MW	154	627,
4fd0a9fd MW	155	628,
b5b0f34c	156	1110,
4fd0a9fd MW	157	1112,
	158	1114,
	159	922,
	160	1113,
	161	1111,
4b5fc357	162	311,
b195470d	163	615,
4fd0a9fd MW	164	626,
	165	625,
	166	920,
	167	622,
b5b0f34c	168	619,
4fd0a9fd MW	169	611,
	170	610,
	171	617,
	172	618,
	173	621,
	174	623,
	175	624,
	176	930,
b5b0f34c	177	643,
4fd0a9fd MW	178	646,
	179	649,
	180	644,
	181	647,
	182	772,
bb515fea MW	183	171,
	184	172,
	185	173,
4b5fc357	186	174,
b5b0f34c	187	507,
4fd0a9fd	188	713,
4b5fc357 MW	189	380,
4b5fc357 MW	190	382,
4b5fc357	191	404,
b5b0f34c	192	406,
a06ea964 NC	193	};
	194
	195	/* Given the opcode enumerator OP, return the pointer to the corresponding
	196	opcode entry. */
	197
	198	const aarch64_opcode *
	199	aarch64_get_opcode (enum aarch64_op op)
	200	{
	201	return aarch64_opcode_table + op_enum_table[op];
	202	}