[deliverable/binutils-gdb.git] / opcodes / arc-dis.c

/* Instruction printing code for the ARC.
   Copyright (C) 1994, 1995 Free Software Foundation, Inc. 
   Contributed by Doug Evans (dje@cygnus.com).

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */

#include "dis-asm.h"
#include "opcode/arc.h"
#include "libelf.h"
#include "elf/arc.h"

static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_host_little PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_graphics_little PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_audio_little PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_host_big PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_graphics_big PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_arc_audio_big PARAMS ((bfd_vma, disassemble_info *));

static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int));

/* Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (4 or 8 for the ARC). */

static int
print_insn (pc, info, mach, big_p)
     bfd_vma pc;
     disassemble_info *info;
     int mach;
     int big_p;
{
  const struct arc_opcode *opcode,*opcode_end;
  bfd_byte buffer[4];
  void *stream = info->stream;
  fprintf_ftype func = info->fprintf_func;
  int status;
  /* First element is insn, second element is limm (if present).  */
  arc_insn insn[2];
  int got_limm_p = 0;
  static int initialized = 0;
  static int current_mach = 0;

  if (!initialized || mach != current_mach)
    {
      initialized = 1;
      current_mach = arc_get_opcode_mach (mach, big_p);
      arc_opcode_init_tables (current_mach);
    }

  status = (*info->read_memory_func) (pc, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }
  if (big_p)
    insn[0] = bfd_getb32 (buffer);
  else
    insn[0] = bfd_getl32 (buffer);

  (*func) (stream, "%08lx\t", insn[0]);

  opcode_end = arc_opcodes + arc_opcodes_count;
  for (opcode = arc_opcodes; opcode < opcode_end; opcode++)
    {
      char *syn;
      int mods,invalid;
      long value;
      const struct arc_operand *operand;
      const struct arc_operand_value *opval;

      /* Basic bit mask must be correct.  */
      if ((insn[0] & opcode->mask) != opcode->value)
	continue;

      /* Supported by this cpu?  */
      if (! arc_opcode_supported (opcode))
	continue;

      /* Make two passes over the operands.  First see if any of them
	 have extraction functions, and, if they do, make sure the
	 instruction is valid.  */

      arc_opcode_init_extract ();
      invalid = 0;

      /* ??? Granted, this is slower than the `ppc' way.  Maybe when this is
	 done it'll be clear what the right way to do this is.  */
      /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
	 printed first, but we don't know how to print it until we've processed
	 the regs.  Since we're scanning all the args before printing the insn
	 anyways, it's actually quite easy.  */

      for (syn = opcode->syntax; *syn; ++syn)
	{
	  if (*syn != '%' || *++syn == '%')
	    continue;
	  mods = 0;
	  while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
	    {
	      mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
	      ++syn;
	    }
	  operand = arc_operands + arc_operand_map[*syn];
	  if (operand->extract)
	    (*operand->extract) (insn, operand, mods,
				 (const struct arc_operand_value **) NULL,
				 &invalid);
	}
      if (invalid)
	continue;

      /* The instruction is valid.  */

      /* If we have an insn with a limm, fetch it now.  Scanning the insns
	 twice lets us do this.  */
      if (arc_opcode_limm_p (NULL))
	{
	  status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
	  if (status != 0)
	    {
	      (*info->memory_error_func) (status, pc, info);
	      return -1;
	    }
	  if (big_p)
	    insn[1] = bfd_getb32 (buffer);
	  else
	    insn[1] = bfd_getl32 (buffer);
	  got_limm_p = 1;
	}

      for (syn = opcode->syntax; *syn; ++syn)
	{
	  if (*syn != '%' || *++syn == '%')
	    {
	      (*func) (stream, "%c", *syn);
	      continue;
	    }

	  /* We have an operand.  Fetch any special modifiers.  */
	  mods = 0;
	  while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
	    {
	      mods |= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
	      ++syn;
	    }
	  operand = arc_operands + arc_operand_map[*syn];

	  /* Extract the value from the instruction.  */
	  opval = NULL;
	  if (operand->extract)
	    {
	      value = (*operand->extract) (insn, operand, mods,
					   &opval, (int *) NULL);
	    }
	  else
	    {
	      value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
	      if ((operand->flags & ARC_OPERAND_SIGNED)
		  && (value & (1 << (operand->bits - 1))))
		value -= 1 << operand->bits;

	      /* If this is a suffix operand, set `opval'.  */
	      if (operand->flags & ARC_OPERAND_SUFFIX)
		opval = arc_opcode_lookup_suffix (operand, value);
	    }

	  /* Print the operand as directed by the flags.  */
	  if (operand->flags & ARC_OPERAND_FAKE)
	    ; /* nothing to do (??? at least not yet) */
	  else if (operand->flags & ARC_OPERAND_SUFFIX)
	    {
	      /* Default suffixes aren't printed.  Fortunately, they all have
		 zero values.  Also, zero values for boolean suffixes are
		 represented by the absence of text.  */

	      if (value != 0)
		{
		  /* ??? OPVAL should have a value.  If it doesn't just cope
		     as we want disassembly to be reasonably robust.
		     Also remember that several condition code values (16-31)
		     aren't defined yet.  For these cases just print the
		     number suitably decorated.  */
		  if (opval)
		    (*func) (stream, "%s%s",
			     mods & ARC_MOD_DOT ? "." : "",
			     opval->name);
		  else
		    (*func) (stream, "%s%c%d",
			     mods & ARC_MOD_DOT ? "." : "",
			     operand->fmt, value);
		}
	    }
	  else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH)
	    (*info->print_address_func) (pc + 4 + value, info);
	  /* ??? Not all cases of this are currently caught.  */
	  else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if (operand->flags & ARC_OPERAND_ADDRESS)
	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	  else if (opval)
	    /* Note that this case catches both normal and auxiliary regs.  */
	    (*func) (stream, "%s", opval->name);
	  else
	    (*func) (stream, "%ld", value);
	}

      /* We have found and printed an instruction; return.  */
      return got_limm_p ? 8 : 4;
    }

  (*func) (stream, "*unknown*");
  return 4;
}

/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use.
   This does things a non-standard way (the "standard" way would be to copy
   this code into disassemble.c).  Since there are more than a couple of
   variants, hiding all this crud here seems cleaner.  */

disassembler_ftype
arc_get_disassembler (mach, big_p)
     int mach;
     int big_p;
{
  switch (mach)
    {
    case bfd_mach_arc_base:
      return big_p ? print_insn_arc_base_big : print_insn_arc_base_little;
    case bfd_mach_arc_host:
      return big_p ? print_insn_arc_host_big : print_insn_arc_host_little;
    case bfd_mach_arc_graphics:
      return big_p ? print_insn_arc_graphics_big : print_insn_arc_graphics_little;
    case bfd_mach_arc_audio:
      return big_p ? print_insn_arc_audio_big : print_insn_arc_audio_little;
    }
  return print_insn_arc_base_little;
}

static int
print_insn_arc_base_little (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_base, 0);
}

static int
print_insn_arc_host_little (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_host, 0);
}

static int
print_insn_arc_graphics_little (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_graphics, 0);
}

static int
print_insn_arc_audio_little (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_audio, 0);
}

static int
print_insn_arc_base_big (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_base, 1);
}

static int
print_insn_arc_host_big (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_host, 1);
}

static int
print_insn_arc_graphics_big (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_graphics, 1);
}

static int
print_insn_arc_audio_big (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  return print_insn (pc, info, bfd_mach_arc_audio, 1);
}
Commit	Line	Data
edb35c13	1	/* Instruction printing code for the ARC.
98d42df9	2	Copyright (C) 1994, 1995 Free Software Foundation, Inc.
edb35c13 DE	3	Contributed by Doug Evans (dje@cygnus.com).
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
	18
	19	#include "dis-asm.h"
	20	#include "opcode/arc.h"
98d42df9 DE	21	#include "libelf.h"
	22	#include "elf/arc.h"
	23
1a56be5c DE	24	static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *));
	25	static int print_insn_arc_host_little PARAMS ((bfd_vma, disassemble_info *));
	26	static int print_insn_arc_graphics_little PARAMS ((bfd_vma, disassemble_info *));
	27	static int print_insn_arc_audio_little PARAMS ((bfd_vma, disassemble_info *));
	28	static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *));
	29	static int print_insn_arc_host_big PARAMS ((bfd_vma, disassemble_info *));
	30	static int print_insn_arc_graphics_big PARAMS ((bfd_vma, disassemble_info *));
	31	static int print_insn_arc_audio_big PARAMS ((bfd_vma, disassemble_info *));
	32
	33	static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int));
edb35c13 DE	34
	35	/* Print one instruction from PC on INFO->STREAM.
	36	Return the size of the instruction (4 or 8 for the ARC). */
	37
98d42df9	38	static int
1a56be5c	39	print_insn (pc, info, mach, big_p)
edb35c13	40	bfd_vma pc;
98d42df9	41	disassemble_info *info;
1a56be5c DE	42	int mach;
1a56be5c DE	43	int big_p;
edb35c13 DE	44	{
	45	const struct arc_opcode opcode,opcode_end;
	46	bfd_byte buffer[4];
	47	void *stream = info->stream;
	48	fprintf_ftype func = info->fprintf_func;
	49	int status;
	50	/* First element is insn, second element is limm (if present). */
	51	arc_insn insn[2];
	52	int got_limm_p = 0;
	53	static int initialized = 0;
1a56be5c	54	static int current_mach = 0;
edb35c13	55
1a56be5c	56	if (!initialized \|\| mach != current_mach)
edb35c13	57	{
edb35c13	58	initialized = 1;
1a56be5c DE	59	current_mach = arc_get_opcode_mach (mach, big_p);
1a56be5c DE	60	arc_opcode_init_tables (current_mach);
edb35c13 DE	61	}
	62
	63	status = (*info->read_memory_func) (pc, buffer, 4, info);
	64	if (status != 0)
	65	{
	66	(*info->memory_error_func) (status, pc, info);
	67	return -1;
	68	}
1a56be5c	69	if (big_p)
98d42df9 DE	70	insn[0] = bfd_getb32 (buffer);
	71	else
	72	insn[0] = bfd_getl32 (buffer);
edb35c13	73
1a56be5c	74	(*func) (stream, "%08lx\t", insn[0]);
edb35c13 DE	75
	76	opcode_end = arc_opcodes + arc_opcodes_count;
	77	for (opcode = arc_opcodes; opcode < opcode_end; opcode++)
	78	{
	79	char *syn;
	80	int mods,invalid;
	81	long value;
	82	const struct arc_operand *operand;
	83	const struct arc_operand_value *opval;
	84
98d42df9	85	/* Basic bit mask must be correct. */
edb35c13 DE	86	if ((insn[0] & opcode->mask) != opcode->value)
	87	continue;
	88
98d42df9 DE	89	/* Supported by this cpu? */
	90	if (! arc_opcode_supported (opcode))
	91	continue;
	92
edb35c13 DE	93	/* Make two passes over the operands. First see if any of them
	94	have extraction functions, and, if they do, make sure the
	95	instruction is valid. */
	96
	97	arc_opcode_init_extract ();
	98	invalid = 0;
	99
	100	/* ??? Granted, this is slower than the `ppc' way. Maybe when this is
	101	done it'll be clear what the right way to do this is. */
	102	/* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
	103	printed first, but we don't know how to print it until we've processed
	104	the regs. Since we're scanning all the args before printing the insn
98d42df9	105	anyways, it's actually quite easy. */
edb35c13 DE	106
	107	for (syn = opcode->syntax; *syn; ++syn)
	108	{
	109	if (syn != '%' \|\| ++syn == '%')
	110	continue;
	111	mods = 0;
	112	while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
	113	{
	114	mods \|= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
	115	++syn;
	116	}
	117	operand = arc_operands + arc_operand_map[*syn];
	118	if (operand->extract)
	119	(*operand->extract) (insn, operand, mods,
	120	(const struct arc_operand_value **) NULL,
	121	&invalid);
	122	}
	123	if (invalid)
	124	continue;
	125
	126	/* The instruction is valid. */
	127
	128	/* If we have an insn with a limm, fetch it now. Scanning the insns
	129	twice lets us do this. */
	130	if (arc_opcode_limm_p (NULL))
	131	{
	132	status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
	133	if (status != 0)
	134	{
	135	(*info->memory_error_func) (status, pc, info);
	136	return -1;
	137	}
1a56be5c	138	if (big_p)
98d42df9 DE	139	insn[1] = bfd_getb32 (buffer);
	140	else
	141	insn[1] = bfd_getl32 (buffer);
edb35c13 DE	142	got_limm_p = 1;
	143	}
	144
	145	for (syn = opcode->syntax; *syn; ++syn)
	146	{
	147	if (syn != '%' \|\| ++syn == '%')
	148	{
1a56be5c	149	(func) (stream, "%c", syn);
edb35c13 DE	150	continue;
	151	}
	152
	153	/* We have an operand. Fetch any special modifiers. */
	154	mods = 0;
	155	while (ARC_MOD_P (arc_operands[arc_operand_map[*syn]].flags))
	156	{
	157	mods \|= arc_operands[arc_operand_map[*syn]].flags & ARC_MOD_BITS;
	158	++syn;
	159	}
	160	operand = arc_operands + arc_operand_map[*syn];
	161
	162	/* Extract the value from the instruction. */
	163	opval = NULL;
	164	if (operand->extract)
	165	{
	166	value = (*operand->extract) (insn, operand, mods,
	167	&opval, (int *) NULL);
	168	}
	169	else
	170	{
	171	value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
	172	if ((operand->flags & ARC_OPERAND_SIGNED)
	173	&& (value & (1 << (operand->bits - 1))))
	174	value -= 1 << operand->bits;
	175
	176	/* If this is a suffix operand, set `opval'. */
	177	if (operand->flags & ARC_OPERAND_SUFFIX)
	178	opval = arc_opcode_lookup_suffix (operand, value);
	179	}
	180
	181	/* Print the operand as directed by the flags. */
	182	if (operand->flags & ARC_OPERAND_FAKE)
	183	; /* nothing to do (??? at least not yet) */
	184	else if (operand->flags & ARC_OPERAND_SUFFIX)
	185	{
	186	/* Default suffixes aren't printed. Fortunately, they all have
	187	zero values. Also, zero values for boolean suffixes are
	188	represented by the absence of text. */
	189
	190	if (value != 0)
	191	{
	192	/* ??? OPVAL should have a value. If it doesn't just cope
	193	as we want disassembly to be reasonably robust.
	194	Also remember that several condition code values (16-31)
	195	aren't defined yet. For these cases just print the
	196	number suitably decorated. */
	197	if (opval)
1a56be5c DE	198	(*func) (stream, "%s%s",
	199	mods & ARC_MOD_DOT ? "." : "",
	200	opval->name);
edb35c13	201	else
1a56be5c DE	202	(*func) (stream, "%s%c%d",
	203	mods & ARC_MOD_DOT ? "." : "",
	204	operand->fmt, value);
edb35c13 DE	205	}
edb35c13 DE	206	}
1a56be5c	207	else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH)
98d42df9	208	(*info->print_address_func) (pc + 4 + value, info);
edb35c13	209	/* ??? Not all cases of this are currently caught. */
1a56be5c DE	210	else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH)
	211	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	212	else if (operand->flags & ARC_OPERAND_ADDRESS)
edb35c13 DE	213	(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
	214	else if (opval)
	215	/* Note that this case catches both normal and auxiliary regs. */
1a56be5c	216	(*func) (stream, "%s", opval->name);
edb35c13	217	else
1a56be5c	218	(*func) (stream, "%ld", value);
edb35c13 DE	219	}
	220
	221	/* We have found and printed an instruction; return. */
	222	return got_limm_p ? 8 : 4;
	223	}
	224
1a56be5c	225	(func) (stream, "unknown*");
edb35c13 DE	226	return 4;
edb35c13 DE	227	}
98d42df9	228
1a56be5c	229	/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use.
98d42df9 DE	230	This does things a non-standard way (the "standard" way would be to copy
	231	this code into disassemble.c). Since there are more than a couple of
	232	variants, hiding all this crud here seems cleaner. */
	233
	234	disassembler_ftype
1a56be5c DE	235	arc_get_disassembler (mach, big_p)
	236	int mach;
	237	int big_p;
98d42df9	238	{
98d42df9 DE	239	switch (mach)
	240	{
	241	case bfd_mach_arc_base:
1a56be5c	242	return big_p ? print_insn_arc_base_big : print_insn_arc_base_little;
98d42df9	243	case bfd_mach_arc_host:
1a56be5c	244	return big_p ? print_insn_arc_host_big : print_insn_arc_host_little;
98d42df9	245	case bfd_mach_arc_graphics:
1a56be5c	246	return big_p ? print_insn_arc_graphics_big : print_insn_arc_graphics_little;
98d42df9	247	case bfd_mach_arc_audio:
1a56be5c	248	return big_p ? print_insn_arc_audio_big : print_insn_arc_audio_little;
98d42df9	249	}
1a56be5c DE	250	return print_insn_arc_base_little;
	251	}
	252
	253	static int
	254	print_insn_arc_base_little (pc, info)
	255	bfd_vma pc;
	256	disassemble_info *info;
	257	{
	258	return print_insn (pc, info, bfd_mach_arc_base, 0);
98d42df9 DE	259	}
	260
	261	static int
1a56be5c	262	print_insn_arc_host_little (pc, info)
98d42df9 DE	263	bfd_vma pc;
	264	disassemble_info *info;
	265	{
1a56be5c	266	return print_insn (pc, info, bfd_mach_arc_host, 0);
98d42df9 DE	267	}
98d42df9 DE	268
1a56be5c DE	269	static int
	270	print_insn_arc_graphics_little (pc, info)
	271	bfd_vma pc;
	272	disassemble_info *info;
	273	{
	274	return print_insn (pc, info, bfd_mach_arc_graphics, 0);
	275	}
98d42df9 DE	276
98d42df9 DE	277	static int
1a56be5c	278	print_insn_arc_audio_little (pc, info)
98d42df9 DE	279	bfd_vma pc;
	280	disassemble_info *info;
	281	{
1a56be5c	282	return print_insn (pc, info, bfd_mach_arc_audio, 0);
98d42df9 DE	283	}
98d42df9 DE	284
1a56be5c DE	285	static int
	286	print_insn_arc_base_big (pc, info)
	287	bfd_vma pc;
	288	disassemble_info *info;
	289	{
	290	return print_insn (pc, info, bfd_mach_arc_base, 1);
	291	}
98d42df9 DE	292
98d42df9 DE	293	static int
1a56be5c	294	print_insn_arc_host_big (pc, info)
98d42df9 DE	295	bfd_vma pc;
	296	disassemble_info *info;
	297	{
1a56be5c	298	return print_insn (pc, info, bfd_mach_arc_host, 1);
98d42df9 DE	299	}
98d42df9 DE	300
1a56be5c DE	301	static int
	302	print_insn_arc_graphics_big (pc, info)
	303	bfd_vma pc;
	304	disassemble_info *info;
	305	{
	306	return print_insn (pc, info, bfd_mach_arc_graphics, 1);
	307	}
98d42df9 DE	308
98d42df9 DE	309	static int
1a56be5c	310	print_insn_arc_audio_big (pc, info)
98d42df9 DE	311	bfd_vma pc;
	312	disassemble_info *info;
	313	{
1a56be5c	314	return print_insn (pc, info, bfd_mach_arc_audio, 1);
98d42df9	315	}