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edb35c13 | 1 | /* Opcode table for the ARC. |
ecec4df3 | 2 | Copyright 1994, 1995 Free Software Foundation, Inc. |
edb35c13 DE |
3 | Contributed by Doug Evans (dje@cygnus.com). |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2, or (at your option) | |
8 | any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
18 | ||
ecec4df3 DE |
19 | /* The ARC may eventually be bi-endian. |
20 | Keep this file byte order independent. */ | |
21 | ||
edb35c13 DE |
22 | #include "ansidecl.h" |
23 | #include "opcode/arc.h" | |
24 | ||
25 | #define INSERT_FN(fn) \ | |
26 | static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ | |
27 | int, const struct arc_operand_value *, long, \ | |
28 | const char **)) | |
29 | #define EXTRACT_FN(fn) \ | |
30 | static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ | |
31 | int, const struct arc_operand_value **, int *)) | |
32 | ||
33 | INSERT_FN (insert_reg); | |
34 | INSERT_FN (insert_shimmfinish); | |
35 | INSERT_FN (insert_limmfinish); | |
36 | INSERT_FN (insert_shimmoffset); | |
37 | INSERT_FN (insert_shimmzero); | |
38 | INSERT_FN (insert_flag); | |
39 | INSERT_FN (insert_flagfinish); | |
40 | INSERT_FN (insert_cond); | |
41 | INSERT_FN (insert_forcelimm); | |
42 | INSERT_FN (insert_reladdr); | |
43 | INSERT_FN (insert_unopmacro); | |
44 | INSERT_FN (insert_multshift); | |
45 | ||
46 | EXTRACT_FN (extract_reg); | |
47 | EXTRACT_FN (extract_flag); | |
48 | EXTRACT_FN (extract_cond); | |
ecec4df3 | 49 | EXTRACT_FN (extract_reladdr); |
edb35c13 DE |
50 | EXTRACT_FN (extract_unopmacro); |
51 | EXTRACT_FN (extract_multshift); | |
52 | ||
53 | /* Various types of ARC operands, including insn suffixes. */ | |
54 | ||
55 | /* Insn format values: | |
56 | ||
57 | 'a' REGA register A field | |
58 | 'b' REGB register B field | |
59 | 'c' REGC register C field | |
60 | 'S' SHIMMFINISH finish inserting a shimm value | |
61 | 'L' LIMMFINISH finish inserting a limm value | |
62 | 'd' SHIMMOFFSET shimm offset in ld,st insns | |
63 | '0' SHIMMZERO 0 shimm value in ld,st insns | |
64 | 'f' FLAG F flag | |
65 | 'F' FLAGFINISH finish inserting the F flag | |
66 | 'G' FLAGINSN insert F flag in "flag" insn | |
67 | 'n' DELAY N field (nullify field) | |
68 | 'q' COND condition code field | |
69 | 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm | |
70 | 'B' BRANCH branch address | |
71 | 'z' SIZE1 size field in ld a,[b,c] | |
72 | 'Z' SIZE10 size field in ld a,[b,shimm] | |
73 | 'y' SIZE22 size field in st c,[b,shimm] | |
74 | 'x' SIGN0 sign extend field ld a,[b,c] | |
75 | 'X' SIGN9 sign extend field ld a,[b,shimm] | |
ecec4df3 DE |
76 | 'w' ADDRESS3 write-back field in ld a,[b,c] |
77 | 'W' ADDRESS12 write-back field in ld a,[b,shimm] | |
78 | 'v' ADDRESS24 write-back field in st c,[b,shimm] | |
edb35c13 DE |
79 | 'D' CACHEBYPASS5 direct to memory enable (cache bypass) in ld a,[b,c] |
80 | 'e' CACHEBYPASS14 direct to memory enable (cache bypass) in ld a,[b,shimm] | |
81 | 'E' CACHEBYPASS26 direct to memory enable (cache bypass) in st c,[b,shimm] | |
ecec4df3 DE |
82 | 'u' UNSIGNED unsigned multiply |
83 | 's' SATURATION saturation limit in audio arc mac insn | |
edb35c13 | 84 | 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros |
edb35c13 DE |
85 | |
86 | The following modifiers may appear between the % and char (eg: %.f): | |
87 | ||
88 | '.' MODDOT '.' prefix must be present | |
89 | 'r' REG generic register value, for register table | |
90 | 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] | |
91 | ||
92 | Fields are: | |
93 | ||
94 | CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN | |
95 | */ | |
96 | ||
97 | const struct arc_operand arc_operands[] = | |
98 | { | |
99 | /* place holder (??? not sure if needed) */ | |
100 | #define UNUSED 0 | |
101 | { 0 }, | |
102 | ||
103 | /* register A or shimm/limm indicator */ | |
104 | #define REGA (UNUSED + 1) | |
105 | { 'a', 6, ARC_SHIFT_REGA, 0, insert_reg, extract_reg }, | |
106 | ||
107 | /* register B or shimm/limm indicator */ | |
108 | #define REGB (REGA + 1) | |
109 | { 'b', 6, ARC_SHIFT_REGB, 0, insert_reg, extract_reg }, | |
110 | ||
111 | /* register C or shimm/limm indicator */ | |
112 | #define REGC (REGB + 1) | |
113 | { 'c', 6, ARC_SHIFT_REGC, 0, insert_reg, extract_reg }, | |
114 | ||
115 | /* fake operand used to insert shimm value into most instructions */ | |
116 | #define SHIMMFINISH (REGC + 1) | |
117 | { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, | |
118 | ||
119 | /* fake operand used to insert limm value into most instructions */ | |
120 | #define LIMMFINISH (SHIMMFINISH + 1) | |
121 | { 'L', 32, 32, ARC_OPERAND_ABSOLUTE + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, | |
122 | ||
123 | /* shimm operand when there is no reg indicator (ld,st) */ | |
124 | #define SHIMMOFFSET (LIMMFINISH + 1) | |
125 | { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 }, | |
126 | ||
127 | /* 0 shimm operand for ld,st insns */ | |
128 | #define SHIMMZERO (SHIMMOFFSET + 1) | |
129 | { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 }, | |
130 | ||
131 | /* flag update bit (insertion is defered until we know how) */ | |
132 | #define FLAG (SHIMMZERO + 1) | |
133 | { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, | |
134 | ||
135 | /* fake utility operand to finish 'f' suffix handling */ | |
136 | #define FLAGFINISH (FLAG + 1) | |
137 | { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, | |
138 | ||
139 | /* fake utility operand to set the 'f' flag for the "flag" insn */ | |
140 | #define FLAGINSN (FLAGFINISH + 1) | |
141 | { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, | |
142 | ||
143 | /* branch delay types */ | |
144 | #define DELAY (FLAGINSN + 1) | |
145 | { 'n', 2, 5, ARC_OPERAND_SUFFIX }, | |
146 | ||
147 | /* conditions */ | |
148 | #define COND (DELAY + 1) | |
149 | { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, | |
150 | ||
151 | /* set `cond_p' to 1 to ensure a constant is treated as a limm */ | |
152 | #define FORCELIMM (COND + 1) | |
153 | { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm }, | |
154 | ||
155 | /* branch address b, bl, and lp insns */ | |
156 | #define BRANCH (FORCELIMM + 1) | |
ecec4df3 | 157 | { 'B', 20, 7, ARC_OPERAND_RELATIVE + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr }, |
edb35c13 DE |
158 | |
159 | /* size field, stored in bit 1,2 */ | |
160 | #define SIZE1 (BRANCH + 1) | |
161 | { 'z', 2, 1, ARC_OPERAND_SUFFIX }, | |
162 | ||
163 | /* size field, stored in bit 10,11 */ | |
164 | #define SIZE10 (SIZE1 + 1) | |
165 | { 'Z', 2, 10, ARC_OPERAND_SUFFIX, }, | |
166 | ||
167 | /* size field, stored in bit 22,23 */ | |
168 | #define SIZE22 (SIZE10 + 1) | |
169 | { 'y', 2, 22, ARC_OPERAND_SUFFIX, }, | |
170 | ||
171 | /* sign extend field, stored in bit 0 */ | |
172 | #define SIGN0 (SIZE22 + 1) | |
173 | { 'x', 1, 0, ARC_OPERAND_SUFFIX }, | |
174 | ||
175 | /* sign extend field, stored in bit 9 */ | |
176 | #define SIGN9 (SIGN0 + 1) | |
177 | { 'X', 1, 9, ARC_OPERAND_SUFFIX }, | |
178 | ||
179 | /* address write back, stored in bit 3 */ | |
180 | #define ADDRESS3 (SIGN9 + 1) | |
ecec4df3 | 181 | { 'w', 1, 3, ARC_OPERAND_SUFFIX }, |
edb35c13 DE |
182 | |
183 | /* address write back, stored in bit 12 */ | |
184 | #define ADDRESS12 (ADDRESS3 + 1) | |
ecec4df3 | 185 | { 'W', 1, 12, ARC_OPERAND_SUFFIX }, |
edb35c13 DE |
186 | |
187 | /* address write back, stored in bit 24 */ | |
188 | #define ADDRESS24 (ADDRESS12 + 1) | |
ecec4df3 | 189 | { 'v', 1, 24, ARC_OPERAND_SUFFIX }, |
edb35c13 | 190 | |
ecec4df3 | 191 | /* cache bypass, stored in bit 5 */ |
edb35c13 DE |
192 | #define CACHEBYPASS5 (ADDRESS24 + 1) |
193 | { 'D', 1, 5, ARC_OPERAND_SUFFIX }, | |
194 | ||
ecec4df3 | 195 | /* cache bypass, stored in bit 14 */ |
edb35c13 DE |
196 | #define CACHEBYPASS14 (CACHEBYPASS5 + 1) |
197 | { 'e', 1, 14, ARC_OPERAND_SUFFIX }, | |
198 | ||
ecec4df3 | 199 | /* cache bypass, stored in bit 26 */ |
edb35c13 DE |
200 | #define CACHEBYPASS26 (CACHEBYPASS14 + 1) |
201 | { 'E', 1, 26, ARC_OPERAND_SUFFIX }, | |
202 | ||
ecec4df3 DE |
203 | /* unsigned multiply */ |
204 | #define UNSIGNED (CACHEBYPASS26 + 1) | |
205 | { 'u', 1, 27, ARC_OPERAND_SUFFIX }, | |
206 | ||
207 | /* unsigned multiply */ | |
208 | #define SATURATION (UNSIGNED + 1) | |
209 | { 's', 1, 28, ARC_OPERAND_SUFFIX }, | |
210 | ||
edb35c13 | 211 | /* unop macro, used to copy REGB to REGC */ |
ecec4df3 | 212 | #define UNOPMACRO (SATURATION + 1) |
edb35c13 DE |
213 | { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, |
214 | ||
edb35c13 | 215 | /* '.' modifier ('.' required). */ |
ecec4df3 | 216 | #define MODDOT (UNOPMACRO + 1) |
edb35c13 DE |
217 | { '.', 1, 0, ARC_MOD_DOT }, |
218 | ||
219 | /* Dummy 'r' modifier for the register table. | |
220 | It's called a "dummy" because there's no point in inserting an 'r' into all | |
221 | the %a/%b/%c occurrences in the insn table. */ | |
222 | #define REG (MODDOT + 1) | |
223 | { 'r', 6, 0, ARC_MOD_REG }, | |
224 | ||
225 | /* Known auxiliary register modifier (stored in shimm field). */ | |
226 | #define AUXREG (REG + 1) | |
227 | { 'A', 9, 0, ARC_MOD_AUXREG }, | |
228 | ||
229 | /* end of list place holder */ | |
230 | { 0 } | |
231 | }; | |
232 | ||
233 | /* Given a format letter, yields the index into `arc_operands'. | |
234 | eg: arc_operand_map['a'] = REGA. */ | |
235 | unsigned char arc_operand_map[256]; | |
236 | ||
237 | #define I(x) (((x) & 31) << 27) | |
238 | #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) | |
239 | #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) | |
240 | #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) | |
241 | #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ | |
242 | ||
243 | /* ARC instructions (sorted by at least the first letter, and equivalent | |
244 | opcodes kept together). | |
245 | ||
246 | By recording the insns this way, the table is not hashable on the opcode. | |
247 | That's not a real loss though as there are only a few entries for each | |
248 | insn (ld/st being the exception), which are quickly found and since | |
249 | they're stored together (eg: all `ld' variants are together) very little | |
250 | time is spent on the opcode itself. The slow part is parsing the options, | |
251 | but that's always going to be slow. | |
252 | ||
253 | Longer versions of insns must appear before shorter ones (if gas sees | |
254 | "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is | |
255 | junk). */ | |
256 | ||
257 | /* ??? This table also includes macros: asl, lsl, and mov. The ppc port has | |
258 | a more general facility for dealing with macros which could be used if | |
259 | we need to. */ | |
260 | /* ??? As an experiment, the "mov" macro appears at the start so it is | |
261 | prefered to "and" when disassembling. At present, the table needn't be | |
262 | sorted, though all opcodes with the same first letter must be kept | |
263 | together. */ | |
264 | ||
265 | const struct arc_opcode arc_opcodes[] = { | |
ecec4df3 | 266 | { "mac%u%.s%.q%.f %a,%b,%c%F%S%L", I(-4), I(24), ARC_MACH_AUDIO }, |
edb35c13 DE |
267 | /* Note that "mov" is really an "and". */ |
268 | { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) }, | |
ecec4df3 DE |
269 | { "mul%u%.q%.f %a,%b,%c%F%S%L", I(-2), I(28), ARC_MACH_AUDIO }, |
270 | /* ??? This insn allows an optional "0," preceding the args. */ | |
271 | /* We can't use %u here because it's not a suffix (the "64" is in the way). */ | |
272 | { "mul64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(20)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, | |
273 | { "mulu64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(21)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, | |
edb35c13 DE |
274 | |
275 | { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) }, | |
276 | { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) }, | |
277 | { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) }, | |
ecec4df3 | 278 | { "asl%.q%.f %a,%b,%c%F%S%L", I(-1), I(16), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, |
edb35c13 DE |
279 | /* Note that "asl" is really an "add". */ |
280 | { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, | |
ecec4df3 | 281 | { "asr%.q%.f %a,%b,%c%F%S%L", I(-1), I(18), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, |
edb35c13 DE |
282 | { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) }, |
283 | { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) }, | |
284 | { "b%q%.n %B", I(-1), I(4) }, | |
285 | { "bl%q%.n %B", I(-1), I(5) }, | |
286 | { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) }, | |
287 | { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) }, | |
288 | { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) }, | |
289 | /* %Q: force cond_p=1 --> no shimm values */ | |
290 | { "j%q%Q%.n%.f %b%L", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) }, | |
291 | /* Put opcode 1 ld insns first so shimm gets prefered over limm. */ | |
292 | /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ | |
293 | { "ld%Z%.X%.v%.e %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) }, | |
294 | { "ld%Z%.X%.v%.e %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) }, | |
295 | { "ld%z%.x%.u%.D %a,[%b,%c]", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) }, | |
296 | { "lp%q%.n %B", I(-1), I(6), }, | |
297 | { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) }, | |
298 | /* Note that "lsl" is really an "add". */ | |
299 | { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, | |
ecec4df3 | 300 | { "lsr%.q%.f %a,%b,%c%F%S%L", I(-1), I(17), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, |
edb35c13 DE |
301 | { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) }, |
302 | /* Note that "nop" is really an "xor". */ | |
303 | { "nop", 0xffffffff, 0x7fffffff }, | |
304 | { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) }, | |
ecec4df3 DE |
305 | /* ??? The %a here should be %p or something. */ |
306 | { "padc%.q%.f %a,%b,%c%F%S%L", I(-1), I(25), ARC_MACH_GRAPHICS }, | |
307 | { "padd%.q%.f %a,%b,%c%F%S%L", I(-1), I(24), ARC_MACH_GRAPHICS }, | |
308 | /* Note that "pmov" is really a "pand". */ | |
309 | { "pmov%.q%.f %a,%b%F%S%L%U", I(-1), I(28), ARC_MACH_GRAPHICS }, | |
310 | { "pand%.q%.f %a,%b,%c%F%S%L", I(-1), I(28), ARC_MACH_GRAPHICS }, | |
311 | { "psbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(27), ARC_MACH_GRAPHICS }, | |
312 | { "psub%.q%.f %a,%b,%c%F%S%L", I(-1), I(26), ARC_MACH_GRAPHICS }, | |
edb35c13 DE |
313 | /* Note that "rlc" is really an "adc". */ |
314 | { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) }, | |
ecec4df3 | 315 | { "ror%.q%.f %a,%b,%c%F%S%L", I(-1), I(19), ARC_MACH_HOST+ARC_MACH_GRAPHICS }, |
edb35c13 DE |
316 | { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) }, |
317 | { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) }, | |
318 | { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) }, | |
319 | { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) }, | |
320 | { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) }, | |
321 | { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) }, | |
322 | /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ | |
323 | { "st%y%.w%.E %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) }, | |
324 | { "st%y%.w%.E %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) }, | |
325 | { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) }, | |
ecec4df3 | 326 | { "swap%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(9), ARC_MACH_AUDIO }, |
edb35c13 DE |
327 | { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) } |
328 | }; | |
329 | int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); | |
330 | ||
331 | const struct arc_operand_value arc_reg_names[] = | |
332 | { | |
333 | /* Sort this so that the first 61 entries are sequential. | |
334 | IE: For each i (i<61), arc_reg_names[i].value == i. */ | |
335 | ||
336 | { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG }, | |
337 | { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG }, | |
338 | { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG }, | |
339 | { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG }, | |
340 | { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG }, | |
341 | { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG }, | |
342 | { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG }, | |
343 | { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG }, | |
344 | { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG }, | |
345 | { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG }, | |
346 | { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG }, | |
347 | { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG }, | |
348 | { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG }, | |
349 | { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG }, | |
350 | { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG }, | |
351 | { "lp_count", 60, REG }, | |
352 | ||
353 | /* I'd prefer to output these as "fp" and "sp" by default, but we still need | |
354 | to recognize the canonical values. */ | |
355 | { "r27", 27, REG }, { "r28", 28, REG }, | |
356 | ||
357 | /* Standard auxiliary registers. */ | |
ecec4df3 | 358 | { "status", 0, AUXREG }, |
edb35c13 | 359 | { "semaphore", 1, AUXREG }, |
ecec4df3 DE |
360 | { "lp_start", 2, AUXREG }, |
361 | { "lp_end", 3, AUXREG }, | |
362 | { "identity", 4, AUXREG }, | |
363 | { "debug", 5, AUXREG }, | |
364 | ||
365 | /* Host ARC Extensions. */ | |
366 | { "mlo", 57, REG, ARC_MACH_HOST }, | |
367 | { "mmid", 58, REG, ARC_MACH_HOST }, | |
368 | { "mhi", 59, REG, ARC_MACH_HOST }, | |
369 | { "ivic", 0x10, AUXREG, ARC_MACH_HOST }, | |
370 | { "ivdc", 0x11, AUXREG, ARC_MACH_HOST }, | |
371 | { "ivdcn", 0x12, AUXREG, ARC_MACH_HOST }, | |
372 | { "flushd", 0x13, AUXREG, ARC_MACH_HOST }, | |
373 | { "saha", 0x14, AUXREG, ARC_MACH_HOST }, | |
374 | { "gahd", 0x15, AUXREG, ARC_MACH_HOST }, | |
375 | { "aahd", 0x16, AUXREG, ARC_MACH_HOST }, | |
376 | { "rrcr", 0x17, AUXREG, ARC_MACH_HOST }, | |
377 | { "rpcr", 0x18, AUXREG, ARC_MACH_HOST }, | |
378 | { "flushdn", 0x19, AUXREG, ARC_MACH_HOST }, | |
379 | { "dbgad1", 0x1a, AUXREG, ARC_MACH_HOST }, | |
380 | { "dbgad2", 0x1b, AUXREG, ARC_MACH_HOST }, | |
381 | { "dbgmde", 0x1c, AUXREG, ARC_MACH_HOST }, | |
382 | { "dbgstat", 0x1d, AUXREG, ARC_MACH_HOST }, | |
383 | { "wag", 0x1e, AUXREG, ARC_MACH_HOST }, | |
384 | { "mulhi", 0x1f, AUXREG, ARC_MACH_HOST }, | |
385 | { "intwide", 0x20, AUXREG, ARC_MACH_HOST }, | |
386 | { "intgen", 0x21, AUXREG, ARC_MACH_HOST }, | |
387 | { "rfsh_n", 0x22, AUXREG, ARC_MACH_HOST }, | |
388 | ||
389 | /* Graphics ARC Extensions. */ | |
390 | { "mlo", 57, REG, ARC_MACH_GRAPHICS }, | |
391 | { "mmid", 58, REG, ARC_MACH_GRAPHICS }, | |
392 | { "mhi", 59, REG, ARC_MACH_GRAPHICS }, | |
393 | { "ivic", 0x10, AUXREG, ARC_MACH_GRAPHICS }, | |
394 | { "wag", 0x1e, AUXREG, ARC_MACH_GRAPHICS }, | |
395 | { "mulhi", 0x1f, AUXREG, ARC_MACH_GRAPHICS }, | |
396 | { "intwide", 0x20, AUXREG, ARC_MACH_GRAPHICS }, | |
397 | { "intgen", 0x21, AUXREG, ARC_MACH_GRAPHICS }, | |
398 | { "pix", 0x100, AUXREG, ARC_MACH_GRAPHICS }, | |
399 | { "scratch", 0x120, AUXREG, ARC_MACH_GRAPHICS }, | |
400 | ||
401 | /* Audio ARC Extensions. */ | |
402 | { "macmode", 39, REG, ARC_MACH_AUDIO }, | |
403 | { "rs1", 40, REG, ARC_MACH_AUDIO }, | |
404 | { "rs1n", 41, REG, ARC_MACH_AUDIO }, | |
405 | { "rs1start", 42, REG, ARC_MACH_AUDIO }, | |
406 | { "rs1size", 43, REG, ARC_MACH_AUDIO }, | |
407 | { "rs1delta", 44, REG, ARC_MACH_AUDIO }, | |
408 | { "rs1pos", 45, REG, ARC_MACH_AUDIO }, | |
409 | { "rd1", 46, REG, ARC_MACH_AUDIO }, | |
410 | { "rd1n", 47, REG, ARC_MACH_AUDIO }, | |
411 | { "rd1d", 48, REG, ARC_MACH_AUDIO }, | |
412 | { "rd1pos", 49, REG, ARC_MACH_AUDIO }, | |
413 | { "rs2", 50, REG, ARC_MACH_AUDIO }, | |
414 | { "rs2n", 51, REG, ARC_MACH_AUDIO }, | |
415 | { "rs2start", 52, REG, ARC_MACH_AUDIO }, | |
416 | { "rs2size", 53, REG, ARC_MACH_AUDIO }, | |
417 | { "rs2delta", 54, REG, ARC_MACH_AUDIO }, | |
418 | { "rs2pos", 55, REG, ARC_MACH_AUDIO }, | |
419 | { "rd2", 56, REG, ARC_MACH_AUDIO }, | |
420 | { "rd2n", 57, REG, ARC_MACH_AUDIO }, | |
421 | { "rd2d", 58, REG, ARC_MACH_AUDIO }, | |
422 | { "rd2pos", 59, REG, ARC_MACH_AUDIO }, | |
423 | { "ivic", 0x10, AUXREG, ARC_MACH_AUDIO }, | |
424 | { "wag", 0x1e, AUXREG, ARC_MACH_AUDIO }, | |
425 | { "intwide", 0x20, AUXREG, ARC_MACH_AUDIO }, | |
426 | { "intgen", 0x21, AUXREG, ARC_MACH_AUDIO }, | |
427 | { "bm_sstart", 0x30, AUXREG, ARC_MACH_AUDIO }, | |
428 | { "bm_length", 0x31, AUXREG, ARC_MACH_AUDIO }, | |
429 | { "bm_rstart", 0x32, AUXREG, ARC_MACH_AUDIO }, | |
430 | { "bm_go", 0x33, AUXREG, ARC_MACH_AUDIO }, | |
431 | { "xtp_newval", 0x40, AUXREG, ARC_MACH_AUDIO }, | |
432 | { "sram", 0x400, AUXREG, ARC_MACH_AUDIO }, | |
433 | { "reg_file", 0x800, AUXREG, ARC_MACH_AUDIO }, | |
edb35c13 DE |
434 | }; |
435 | int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); | |
436 | ||
437 | /* The suffix table. | |
438 | Operands with the same name must be stored together. */ | |
439 | ||
440 | const struct arc_operand_value arc_suffixes[] = | |
441 | { | |
442 | /* Entry 0 is special, default values aren't printed by the disassembler. */ | |
443 | { "", 0, -1 }, | |
444 | { "al", 0, COND }, | |
445 | { "ra", 0, COND }, | |
446 | { "eq", 1, COND }, | |
447 | { "z", 1, COND }, | |
448 | { "ne", 2, COND }, | |
449 | { "nz", 2, COND }, | |
450 | { "p", 3, COND }, | |
451 | { "pl", 3, COND }, | |
452 | { "n", 4, COND }, | |
453 | { "mi", 4, COND }, | |
454 | { "c", 5, COND }, | |
455 | { "cs", 5, COND }, | |
456 | { "lo", 5, COND }, | |
457 | { "nc", 6, COND }, | |
458 | { "cc", 6, COND }, | |
459 | { "hs", 6, COND }, | |
460 | { "v", 7, COND }, | |
461 | { "vs", 7, COND }, | |
462 | { "nv", 8, COND }, | |
463 | { "vc", 8, COND }, | |
464 | { "gt", 9, COND }, | |
465 | { "ge", 10, COND }, | |
466 | { "lt", 11, COND }, | |
467 | { "le", 12, COND }, | |
468 | { "hi", 13, COND }, | |
469 | { "ls", 14, COND }, | |
470 | { "pnz", 15, COND }, | |
471 | { "f", 1, FLAG }, | |
472 | { "nd", 0, DELAY }, | |
473 | { "d", 1, DELAY }, | |
474 | { "jd", 2, DELAY }, | |
475 | /* { "b", 7, SIZEEXT },*/ | |
476 | /* { "b", 5, SIZESEX },*/ | |
477 | { "b", 1, SIZE1 }, | |
478 | { "b", 1, SIZE10 }, | |
479 | { "b", 1, SIZE22 }, | |
480 | /* { "w", 8, SIZEEXT },*/ | |
481 | /* { "w", 6, SIZESEX },*/ | |
482 | { "w", 2, SIZE1 }, | |
483 | { "w", 2, SIZE10 }, | |
484 | { "w", 2, SIZE22 }, | |
485 | { "x", 1, SIGN0 }, | |
486 | { "x", 1, SIGN9 }, | |
487 | { "a", 1, ADDRESS3 }, | |
488 | { "a", 1, ADDRESS12 }, | |
489 | { "a", 1, ADDRESS24 }, | |
490 | { "di", 1, CACHEBYPASS5 }, | |
491 | { "di", 1, CACHEBYPASS14 }, | |
492 | { "di", 1, CACHEBYPASS26 }, | |
ecec4df3 DE |
493 | |
494 | /* Audio ARC Extensions. */ | |
495 | /* ??? The values here are guesses. */ | |
496 | { "ss", 16, COND, ARC_MACH_AUDIO }, | |
497 | { "sc", 17, COND, ARC_MACH_AUDIO }, | |
498 | { "mh", 18, COND, ARC_MACH_AUDIO }, | |
499 | { "ml", 19, COND, ARC_MACH_AUDIO }, | |
edb35c13 DE |
500 | }; |
501 | int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); | |
502 | ||
503 | /* Configuration flags. */ | |
504 | ||
505 | /* Various ARC_HAVE_XXX bits. */ | |
506 | static int cpu_type; | |
507 | ||
508 | /* Initialize any tables that need it. | |
509 | Must be called once at start up (or when first needed). | |
510 | ||
ecec4df3 | 511 | FLAGS is a set of bits that say what version of the cpu we have. */ |
edb35c13 DE |
512 | |
513 | void | |
ecec4df3 DE |
514 | arc_opcode_init_tables (flags) |
515 | int flags; | |
edb35c13 DE |
516 | { |
517 | register int i,n; | |
518 | ||
ecec4df3 DE |
519 | cpu_type = flags; |
520 | ||
edb35c13 DE |
521 | memset (arc_operand_map, 0, sizeof (arc_operand_map)); |
522 | n = sizeof (arc_operands) / sizeof (arc_operands[0]); | |
523 | for (i = 0; i < n; i++) | |
524 | arc_operand_map[arc_operands[i].fmt] = i; | |
ecec4df3 | 525 | } |
edb35c13 | 526 | |
ecec4df3 DE |
527 | /* Return non-zero if OPCODE is supported on the specified cpu. |
528 | Cpu selection is made when calling `arc_opcode_init_tables'. */ | |
529 | ||
530 | int | |
531 | arc_opcode_supported (opcode) | |
532 | const struct arc_opcode *opcode; | |
533 | { | |
534 | if (ARC_OPCODE_MACH (opcode->flags) == 0) | |
535 | return 1; | |
536 | if (ARC_OPCODE_MACH (opcode->flags) & ARC_HAVE_MACH (cpu_type)) | |
537 | return 1; | |
538 | return 0; | |
539 | } | |
540 | ||
541 | /* Return non-zero if OPVAL is supported on the specified cpu. | |
542 | Cpu selection is made when calling `arc_opcode_init_tables'. */ | |
543 | ||
544 | int | |
545 | arc_opval_supported (opval) | |
546 | const struct arc_operand_value *opval; | |
547 | { | |
548 | if (ARC_OPVAL_MACH (opval->flags) == 0) | |
549 | return 1; | |
550 | if (ARC_OPVAL_MACH (opval->flags) & ARC_HAVE_MACH (cpu_type)) | |
551 | return 1; | |
552 | return 0; | |
edb35c13 DE |
553 | } |
554 | \f | |
555 | /* Nonzero if we've seen an 'f' suffix (in certain insns). */ | |
556 | static int flag_p; | |
557 | ||
558 | /* Nonzero if we've finished processing the 'f' suffix. */ | |
559 | static int flagshimm_handled_p; | |
560 | ||
561 | /* Nonzero if we've seen a 'q' suffix (condition code). */ | |
562 | static int cond_p; | |
563 | ||
564 | /* Nonzero if we've inserted a shimm. */ | |
565 | static int shimm_p; | |
566 | ||
567 | /* The value of the shimm we inserted (each insn only gets one but it can | |
568 | appear multiple times. */ | |
569 | static int shimm; | |
570 | ||
571 | /* Nonzero if we've inserted a limm (during assembly) or seen a limm | |
572 | (during disassembly). */ | |
573 | static int limm_p; | |
574 | ||
575 | /* The value of the limm we inserted. Each insn only gets one but it can | |
576 | appear multiple times. */ | |
577 | static long limm; | |
578 | ||
579 | /* Called by the assembler before parsing an instruction. */ | |
580 | ||
581 | void | |
582 | arc_opcode_init_insert () | |
583 | { | |
584 | flag_p = 0; | |
585 | flagshimm_handled_p = 0; | |
586 | cond_p = 0; | |
587 | shimm_p = 0; | |
588 | limm_p = 0; | |
589 | } | |
590 | ||
591 | /* Called by the assembler to see if the insn has a limm operand. | |
592 | Also called by the disassembler to see if the insn contains a limm. */ | |
593 | ||
594 | int | |
595 | arc_opcode_limm_p (limmp) | |
596 | long *limmp; | |
597 | { | |
598 | if (limmp) | |
599 | *limmp = limm; | |
600 | return limm_p; | |
601 | } | |
602 | ||
603 | /* Insert a value into a register field. | |
604 | If REG is NULL, then this is actually a constant. | |
605 | ||
606 | We must also handle auxiliary registers for lr/sr insns. */ | |
607 | ||
608 | static arc_insn | |
609 | insert_reg (insn, operand, mods, reg, value, errmsg) | |
610 | arc_insn insn; | |
611 | const struct arc_operand *operand; | |
612 | int mods; | |
613 | const struct arc_operand_value *reg; | |
614 | long value; | |
615 | const char **errmsg; | |
616 | { | |
617 | static char buf[100]; | |
618 | ||
619 | if (!reg) | |
620 | { | |
621 | /* We have a constant that also requires a value stored in a register | |
622 | field. Handle these by updating the register field and saving the | |
623 | value for later handling by either %S (shimm) or %L (limm). */ | |
624 | ||
625 | /* Try to use a shimm value before a limm one. */ | |
626 | if (ARC_SHIMM_CONST_P (value) | |
627 | /* If we've seen a conditional suffix we have to use a limm. */ | |
628 | && !cond_p | |
629 | /* If we already have a shimm value that is different than ours | |
630 | we have to use a limm. */ | |
631 | && (!shimm_p || shimm == value)) | |
632 | { | |
633 | int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; | |
634 | flagshimm_handled_p = 1; | |
635 | shimm_p = 1; | |
636 | shimm = value; | |
637 | insn |= marker << operand->shift; | |
638 | /* insn |= value & 511; - done later */ | |
639 | } | |
640 | /* We have to use a limm. If we've already seen one they must match. */ | |
641 | else if (!limm_p || limm == value) | |
642 | { | |
643 | limm_p = 1; | |
644 | limm = value; | |
645 | insn |= ARC_REG_LIMM << operand->shift; | |
646 | /* The constant is stored later. */ | |
647 | } | |
648 | else | |
649 | { | |
650 | *errmsg = "unable to fit different valued constants into instruction"; | |
651 | } | |
652 | } | |
653 | else | |
654 | { | |
655 | /* We have to handle both normal and auxiliary registers. */ | |
656 | ||
657 | if (reg->type == AUXREG) | |
658 | { | |
659 | if (!(mods & ARC_MOD_AUXREG)) | |
660 | *errmsg = "auxiliary register not allowed here"; | |
661 | else | |
662 | { | |
663 | insn |= ARC_REG_SHIMM << operand->shift; | |
664 | insn |= reg->value << arc_operands[reg->type].shift; | |
665 | } | |
666 | } | |
667 | else | |
668 | { | |
669 | /* We should never get an invalid register number here. */ | |
670 | if ((unsigned int) reg->value > 60) | |
671 | { | |
672 | sprintf (buf, "invalid register number `%d'", reg->value); | |
673 | *errmsg = buf; | |
674 | } | |
675 | else | |
676 | insn |= reg->value << operand->shift; | |
677 | } | |
678 | } | |
679 | ||
680 | return insn; | |
681 | } | |
682 | ||
683 | /* Called when we see an 'f' flag. */ | |
684 | ||
685 | static arc_insn | |
686 | insert_flag (insn, operand, mods, reg, value, errmsg) | |
687 | arc_insn insn; | |
688 | const struct arc_operand *operand; | |
689 | int mods; | |
690 | const struct arc_operand_value *reg; | |
691 | long value; | |
692 | const char **errmsg; | |
693 | { | |
694 | /* We can't store anything in the insn until we've parsed the registers. | |
695 | Just record the fact that we've got this flag. `insert_reg' will use it | |
696 | to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ | |
697 | flag_p = 1; | |
698 | ||
699 | return insn; | |
700 | } | |
701 | ||
702 | /* Called after completely building an insn to ensure the 'f' flag gets set | |
703 | properly. This is needed because we don't know how to set this flag until | |
704 | we've parsed the registers. */ | |
705 | ||
706 | static arc_insn | |
707 | insert_flagfinish (insn, operand, mods, reg, value, errmsg) | |
708 | arc_insn insn; | |
709 | const struct arc_operand *operand; | |
710 | int mods; | |
711 | const struct arc_operand_value *reg; | |
712 | long value; | |
713 | const char **errmsg; | |
714 | { | |
715 | if (flag_p && !flagshimm_handled_p) | |
716 | { | |
717 | if (shimm_p) | |
718 | abort (); | |
719 | flagshimm_handled_p = 1; | |
720 | insn |= (1 << operand->shift); | |
721 | } | |
722 | return insn; | |
723 | } | |
724 | ||
725 | /* Called when we see a conditional flag (eg: .eq). */ | |
726 | ||
727 | static arc_insn | |
728 | insert_cond (insn, operand, mods, reg, value, errmsg) | |
729 | arc_insn insn; | |
730 | const struct arc_operand *operand; | |
731 | int mods; | |
732 | const struct arc_operand_value *reg; | |
733 | long value; | |
734 | const char **errmsg; | |
735 | { | |
736 | cond_p = 1; | |
737 | insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; | |
738 | return insn; | |
739 | } | |
740 | ||
741 | /* Used in the "j" instruction to prevent constants from being interpreted as | |
742 | shimm values (which the jump insn doesn't accept). This can also be used | |
743 | to force the use of limm values in other situations (eg: ld r0,[foo] uses | |
744 | this). | |
745 | ??? The mechanism is sound. Access to it is a bit klunky right now. */ | |
746 | ||
747 | static arc_insn | |
748 | insert_forcelimm (insn, operand, mods, reg, value, errmsg) | |
749 | arc_insn insn; | |
750 | const struct arc_operand *operand; | |
751 | int mods; | |
752 | const struct arc_operand_value *reg; | |
753 | long value; | |
754 | const char **errmsg; | |
755 | { | |
756 | cond_p = 1; | |
757 | return insn; | |
758 | } | |
759 | ||
760 | /* Used in ld/st insns to handle the shimm offset field. */ | |
761 | ||
762 | static arc_insn | |
763 | insert_shimmoffset (insn, operand, mods, reg, value, errmsg) | |
764 | arc_insn insn; | |
765 | const struct arc_operand *operand; | |
766 | int mods; | |
767 | const struct arc_operand_value *reg; | |
768 | long value; | |
769 | const char **errmsg; | |
770 | { | |
771 | insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; | |
772 | return insn; | |
773 | } | |
774 | ||
775 | /* Used in ld/st insns when the shimm offset is 0. */ | |
776 | ||
777 | static arc_insn | |
778 | insert_shimmzero (insn, operand, mods, reg, value, errmsg) | |
779 | arc_insn insn; | |
780 | const struct arc_operand *operand; | |
781 | int mods; | |
782 | const struct arc_operand_value *reg; | |
783 | long value; | |
784 | const char **errmsg; | |
785 | { | |
786 | shimm_p = 1; | |
787 | shimm = 0; | |
788 | return insn; | |
789 | } | |
790 | ||
791 | /* Called at the end of processing normal insns (eg: add) to insert a shimm | |
792 | value (if present) into the insn. */ | |
793 | ||
794 | static arc_insn | |
795 | insert_shimmfinish (insn, operand, mods, reg, value, errmsg) | |
796 | arc_insn insn; | |
797 | const struct arc_operand *operand; | |
798 | int mods; | |
799 | const struct arc_operand_value *reg; | |
800 | long value; | |
801 | const char **errmsg; | |
802 | { | |
803 | if (shimm_p) | |
804 | insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; | |
805 | return insn; | |
806 | } | |
807 | ||
808 | /* Called at the end of processing normal insns (eg: add) to insert a limm | |
809 | value (if present) into the insn. Actually, there's nothing for us to do | |
810 | as we can't call frag_more, the caller must do that. */ | |
811 | /* ??? The extract fns take a pointer to two words. The insert insns could be | |
812 | converted and then we could do something useful. Not sure it's worth it. */ | |
813 | ||
814 | static arc_insn | |
815 | insert_limmfinish (insn, operand, mods, reg, value, errmsg) | |
816 | arc_insn insn; | |
817 | const struct arc_operand *operand; | |
818 | int mods; | |
819 | const struct arc_operand_value *reg; | |
820 | long value; | |
821 | const char **errmsg; | |
822 | { | |
823 | if (limm_p) | |
824 | ; /* nothing to do */ | |
825 | return insn; | |
826 | } | |
827 | ||
828 | /* Called at the end of unary operand macros to copy the B field to C. */ | |
829 | ||
830 | static arc_insn | |
831 | insert_unopmacro (insn, operand, mods, reg, value, errmsg) | |
832 | arc_insn insn; | |
833 | const struct arc_operand *operand; | |
834 | int mods; | |
835 | const struct arc_operand_value *reg; | |
836 | long value; | |
837 | const char **errmsg; | |
838 | { | |
839 | insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; | |
840 | return insn; | |
841 | } | |
842 | ||
843 | /* Insert a relative address for a branch insn (b, bl, or lp). */ | |
844 | ||
845 | static arc_insn | |
846 | insert_reladdr (insn, operand, mods, reg, value, errmsg) | |
847 | arc_insn insn; | |
848 | const struct arc_operand *operand; | |
849 | int mods; | |
850 | const struct arc_operand_value *reg; | |
851 | long value; | |
852 | const char **errmsg; | |
853 | { | |
ecec4df3 DE |
854 | if (value & 3) |
855 | *errmsg = "branch address not on 4 byte boundary"; | |
856 | insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; | |
edb35c13 DE |
857 | return insn; |
858 | } | |
859 | \f | |
860 | /* Extraction functions. | |
861 | ||
862 | The suffix extraction functions' return value is redundant since it can be | |
863 | obtained from (*OPVAL)->value. However, the boolean suffixes don't have | |
864 | a suffix table entry for the "false" case, so values of zero must be | |
865 | obtained from the return value (*OPVAL == NULL). */ | |
866 | ||
867 | static const struct arc_operand_value *lookup_register (int type, long regno); | |
868 | ||
869 | /* Called by the disassembler before printing an instruction. */ | |
870 | ||
871 | void | |
872 | arc_opcode_init_extract () | |
873 | { | |
874 | flag_p = 0; | |
875 | flagshimm_handled_p = 0; | |
876 | shimm_p = 0; | |
877 | limm_p = 0; | |
878 | } | |
879 | ||
880 | /* As we're extracting registers, keep an eye out for the 'f' indicator | |
881 | (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, | |
882 | like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. | |
883 | ||
884 | We must also handle auxiliary registers for lr/sr insns. They are just | |
885 | constants with special names. */ | |
886 | ||
887 | static long | |
888 | extract_reg (insn, operand, mods, opval, invalid) | |
889 | arc_insn *insn; | |
890 | const struct arc_operand *operand; | |
891 | int mods; | |
892 | const struct arc_operand_value **opval; | |
893 | int *invalid; | |
894 | { | |
895 | int regno; | |
896 | long value; | |
897 | ||
898 | /* Get the register number. */ | |
899 | regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); | |
900 | ||
901 | /* Is it a constant marker? */ | |
902 | if (regno == ARC_REG_SHIMM) | |
903 | { | |
904 | value = insn[0] & 511; | |
905 | if ((operand->flags & ARC_OPERAND_SIGNED) | |
906 | && (value & 256)) | |
907 | value -= 512; | |
908 | flagshimm_handled_p = 1; | |
909 | } | |
910 | else if (regno == ARC_REG_SHIMM_UPDATE) | |
911 | { | |
912 | value = insn[0] & 511; | |
913 | if ((operand->flags & ARC_OPERAND_SIGNED) | |
914 | && (value & 256)) | |
915 | value -= 512; | |
916 | flag_p = 1; | |
917 | flagshimm_handled_p = 1; | |
918 | } | |
919 | else if (regno == ARC_REG_LIMM) | |
920 | { | |
921 | value = insn[1]; | |
922 | limm_p = 1; | |
923 | } | |
924 | /* It's a register, set OPVAL (that's the only way we distinguish registers | |
925 | from constants here). */ | |
926 | else | |
927 | { | |
928 | const struct arc_operand_value *reg = lookup_register (REG, regno); | |
929 | ||
930 | if (!reg) | |
931 | abort (); | |
932 | if (opval) | |
933 | *opval = reg; | |
934 | value = regno; | |
935 | } | |
936 | ||
937 | /* If this field takes an auxiliary register, see if it's a known one. */ | |
938 | if ((mods & ARC_MOD_AUXREG) | |
939 | && ARC_REG_CONSTANT_P (regno)) | |
940 | { | |
941 | const struct arc_operand_value *reg = lookup_register (AUXREG, value); | |
942 | ||
943 | /* This is really a constant, but tell the caller it has a special | |
944 | name. */ | |
945 | if (reg && opval) | |
946 | *opval = reg; | |
947 | } | |
948 | ||
949 | return value; | |
950 | } | |
951 | ||
952 | /* Return the value of the "flag update" field for shimm insns. | |
953 | This value is actually stored in the register field. */ | |
954 | ||
955 | static long | |
956 | extract_flag (insn, operand, mods, opval, invalid) | |
957 | arc_insn *insn; | |
958 | const struct arc_operand *operand; | |
959 | int mods; | |
960 | const struct arc_operand_value **opval; | |
961 | int *invalid; | |
962 | { | |
963 | int f; | |
964 | const struct arc_operand_value *val; | |
965 | ||
966 | if (flagshimm_handled_p) | |
967 | f = flag_p != 0; | |
968 | else | |
969 | f = (insn[0] & (1 << operand->shift)) != 0; | |
970 | ||
971 | /* There is no text for zero values. */ | |
972 | if (f == 0) | |
973 | return 0; | |
974 | ||
975 | val = arc_opcode_lookup_suffix (operand, 1); | |
976 | if (opval && val) | |
977 | *opval = val; | |
978 | return val->value; | |
979 | } | |
980 | ||
981 | /* Extract the condition code (if it exists). | |
982 | If we've seen a shimm value in this insn (meaning that the insn can't have | |
983 | a condition code field), then we don't store anything in OPVAL and return | |
984 | zero. */ | |
985 | ||
986 | static long | |
987 | extract_cond (insn, operand, mods, opval, invalid) | |
988 | arc_insn *insn; | |
989 | const struct arc_operand *operand; | |
990 | int mods; | |
991 | const struct arc_operand_value **opval; | |
992 | int *invalid; | |
993 | { | |
994 | long cond; | |
995 | const struct arc_operand_value *val; | |
996 | ||
997 | if (flagshimm_handled_p) | |
998 | return 0; | |
999 | ||
1000 | cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); | |
1001 | val = arc_opcode_lookup_suffix (operand, cond); | |
1002 | ||
1003 | /* Ignore NULL values of `val'. Several condition code values aren't | |
1004 | implemented yet. */ | |
1005 | if (opval && val) | |
1006 | *opval = val; | |
1007 | return cond; | |
1008 | } | |
1009 | ||
ecec4df3 DE |
1010 | /* Extract a branch address. |
1011 | We return the value as a real address (not right shifted by 2). */ | |
1012 | ||
1013 | static long | |
1014 | extract_reladdr (insn, operand, mods, opval, invalid) | |
1015 | arc_insn *insn; | |
1016 | const struct arc_operand *operand; | |
1017 | int mods; | |
1018 | const struct arc_operand_value **opval; | |
1019 | int *invalid; | |
1020 | { | |
1021 | long addr; | |
1022 | ||
1023 | addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); | |
1024 | if ((operand->flags & ARC_OPERAND_SIGNED) | |
1025 | && (addr & (1 << (operand->bits - 1)))) | |
1026 | addr -= 1 << operand->bits; | |
1027 | ||
1028 | return addr << 2; | |
1029 | } | |
1030 | ||
edb35c13 DE |
1031 | /* The only thing this does is set the `invalid' flag if B != C. |
1032 | This is needed because the "mov" macro appears before it's real insn "and" | |
1033 | and we don't want the disassembler to confuse them. */ | |
1034 | ||
1035 | static long | |
1036 | extract_unopmacro (insn, operand, mods, opval, invalid) | |
1037 | arc_insn *insn; | |
1038 | const struct arc_operand *operand; | |
1039 | int mods; | |
1040 | const struct arc_operand_value **opval; | |
1041 | int *invalid; | |
1042 | { | |
1043 | /* ??? This misses the case where B == ARC_REG_SHIMM_UPDATE && | |
1044 | C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get | |
1045 | printed as "and"s. */ | |
1046 | if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG) | |
1047 | != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG)) | |
1048 | if (invalid) | |
1049 | *invalid = 1; | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
edb35c13 DE |
1054 | /* Utility for the extraction functions to return the index into |
1055 | `arc_suffixes'. */ | |
1056 | ||
1057 | const struct arc_operand_value * | |
1058 | arc_opcode_lookup_suffix (type, value) | |
1059 | const struct arc_operand *type; | |
1060 | int value; | |
1061 | { | |
1062 | register const struct arc_operand_value *v,*end; | |
1063 | ||
1064 | /* ??? This is a little slow and can be speeded up. */ | |
1065 | ||
1066 | for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) | |
1067 | if (type == &arc_operands[v->type] | |
1068 | && value == v->value) | |
1069 | return v; | |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static const struct arc_operand_value * | |
1074 | lookup_register (type, regno) | |
1075 | int type; | |
1076 | long regno; | |
1077 | { | |
1078 | register const struct arc_operand_value *r,*end; | |
1079 | ||
1080 | if (type == REG) | |
1081 | return &arc_reg_names[regno]; | |
1082 | ||
1083 | /* ??? This is a little slow and can be speeded up. */ | |
1084 | ||
1085 | for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; | |
1086 | r < end; ++r) | |
1087 | if (type == r->type && regno == r->value) | |
1088 | return r; | |
1089 | return 0; | |
1090 | } |