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arc: Change max instruction length to 64-bits
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
886a2506 33/* Insert RB register into a 32-bit opcode. */
bdfe53e3
AB		 34static unsigned long long
35insert_rb (unsigned long long insn,
36 long long int value,
886a2506 37 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 38{
886a2506
NC		 39 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
40}
0d2bcfaf 41
bdfe53e3
AB		 42static long long int
43extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 44 bfd_boolean * invalid ATTRIBUTE_UNUSED)
45{
46 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 47
886a2506
NC		 48 if (value == 0x3e && invalid)
49 *invalid = TRUE; /* A limm operand, it should be extracted in a
50 different way. */
252b5132 51
886a2506
NC		 52 return value;
53}
252b5132 54
bdfe53e3
AB		 55static unsigned long long
56insert_rad (unsigned long long insn,
57 long long int value,
886a2506
NC		 58 const char **errmsg ATTRIBUTE_UNUSED)
59{
60 if (value & 0x01)
61 *errmsg = _("Improper register value.");
0d2bcfaf 62
886a2506
NC		 63 return insn | (value & 0x3F);
64}
0d2bcfaf 65
bdfe53e3
AB		 66static unsigned long long
67insert_rcd (unsigned long long insn,
68 long long int value,
886a2506
NC		 69 const char **errmsg ATTRIBUTE_UNUSED)
70{
71 if (value & 0x01)
72 *errmsg = _("Improper register value.");
0d2bcfaf 73
886a2506
NC		 74 return insn | ((value & 0x3F) << 6);
75}
252b5132 76
886a2506 77/* Dummy insert ZERO operand function. */
252b5132 78
bdfe53e3
AB		 79static unsigned long long
80insert_za (unsigned long long insn,
81 long long int value,
886a2506
NC		 82 const char **errmsg)
83{
84 if (value)
85 *errmsg = _("operand is not zero");
86 return insn;
87}
252b5132 88
886a2506
NC		 89/* Insert Y-bit in bbit/br instructions. This function is called only
90 when solving fixups. */
252b5132 91
bdfe53e3
AB		 92static unsigned long long
93insert_Ybit (unsigned long long insn,
94 long long int value,
886a2506
NC		 95 const char **errmsg ATTRIBUTE_UNUSED)
96{
97 if (value > 0)
98 insn |= 0x08;
252b5132 99
886a2506
NC		 100 return insn;
101}
252b5132 102
886a2506
NC		 103/* Insert Y-bit in bbit/br instructions. This function is called only
104 when solving fixups. */
252b5132 105
bdfe53e3
AB		 106static unsigned long long
107insert_NYbit (unsigned long long insn,
108 long long int value,
886a2506
NC		 109 const char **errmsg ATTRIBUTE_UNUSED)
110{
111 if (value < 0)
112 insn |= 0x08;
0d2bcfaf 113
886a2506
NC		 114 return insn;
115}
252b5132 116
886a2506 117/* Insert H register into a 16-bit opcode. */
252b5132 118
bdfe53e3
AB		 119static unsigned long long
120insert_rhv1 (unsigned long long insn,
121 long long int value,
886a2506
NC		 122 const char **errmsg ATTRIBUTE_UNUSED)
123{
124 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
125}
252b5132 126
bdfe53e3
AB		 127static long long int
128extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 129 bfd_boolean * invalid ATTRIBUTE_UNUSED)
130{
02f3be19 131 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 132
886a2506
NC		 133 return value;
134}
252b5132 135
886a2506 136/* Insert H register into a 16-bit opcode. */
252b5132 137
bdfe53e3
AB		 138static unsigned long long
139insert_rhv2 (unsigned long long insn,
140 long long int value,
886a2506 141 const char **errmsg)
0d2bcfaf 142{
886a2506
NC		 143 if (value == 0x1E)
144 *errmsg =
145 _("Register R30 is a limm indicator for this type of instruction.");
146 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
147}
252b5132 148
bdfe53e3
AB		 149static long long int
150extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 151 bfd_boolean * invalid ATTRIBUTE_UNUSED)
152{
153 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 154
886a2506
NC		 155 return value;
156}
0d2bcfaf 157
bdfe53e3
AB		 158static unsigned long long
159insert_r0 (unsigned long long insn,
160 long long int value,
886a2506
NC		 161 const char **errmsg ATTRIBUTE_UNUSED)
162{
163 if (value != 0)
164 *errmsg = _("Register must be R0.");
47b0e7ad
NC		 165 return insn;
166}
252b5132 167
bdfe53e3
AB		 168static long long int
169extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 170 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 171{
886a2506 172 return 0;
47b0e7ad 173}
252b5132 174
252b5132 175
bdfe53e3
AB		 176static unsigned long long
177insert_r1 (unsigned long long insn,
178 long long int value,
886a2506 179 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 180{
886a2506
NC		 181 if (value != 1)
182 *errmsg = _("Register must be R1.");
47b0e7ad 183 return insn;
252b5132
RH		 184}
185
bdfe53e3
AB		 186static long long int
187extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 188 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 189{
886a2506 190 return 1;
252b5132
RH		 191}
192
bdfe53e3
AB		 193static unsigned long long
194insert_r2 (unsigned long long insn,
195 long long int value,
886a2506 196 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 197{
886a2506
NC		 198 if (value != 2)
199 *errmsg = _("Register must be R2.");
47b0e7ad 200 return insn;
252b5132
RH		 201}
202
bdfe53e3
AB		 203static long long int
204extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 205 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 206{
886a2506 207 return 2;
252b5132
RH		 208}
209
bdfe53e3
AB		 210static unsigned long long
211insert_r3 (unsigned long long insn,
212 long long int value,
886a2506 213 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 214{
886a2506
NC		 215 if (value != 3)
216 *errmsg = _("Register must be R3.");
47b0e7ad 217 return insn;
0d2bcfaf
NC		 218}
219
bdfe53e3
AB		 220static long long int
221extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 222 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 223{
886a2506 224 return 3;
0d2bcfaf
NC		 225}
226
bdfe53e3
AB		 227static unsigned long long
228insert_sp (unsigned long long insn,
229 long long int value,
886a2506 230 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 231{
886a2506
NC		 232 if (value != 28)
233 *errmsg = _("Register must be SP.");
252b5132
RH		 234 return insn;
235}
236
bdfe53e3
AB		 237static long long int
238extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 239 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 240{
886a2506 241 return 28;
0d2bcfaf
NC		 242}
243
bdfe53e3
AB		 244static unsigned long long
245insert_gp (unsigned long long insn,
246 long long int value,
886a2506 247 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 248{
886a2506
NC		 249 if (value != 26)
250 *errmsg = _("Register must be GP.");
251 return insn;
0d2bcfaf
NC		 252}
253
bdfe53e3
AB		 254static long long int
255extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 256 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 257{
886a2506 258 return 26;
0d2bcfaf
NC		 259}
260
bdfe53e3
AB		 261static unsigned long long
262insert_pcl (unsigned long long insn,
263 long long int value,
886a2506 264 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 265{
886a2506
NC		 266 if (value != 63)
267 *errmsg = _("Register must be PCL.");
252b5132
RH		 268 return insn;
269}
270
bdfe53e3
AB		 271static long long int
272extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 273 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 274{
886a2506 275 return 63;
0d2bcfaf
NC		 276}
277
bdfe53e3
AB		 278static unsigned long long
279insert_blink (unsigned long long insn,
280 long long int value,
886a2506 281 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 282{
886a2506
NC		 283 if (value != 31)
284 *errmsg = _("Register must be BLINK.");
252b5132
RH		 285 return insn;
286}
287
bdfe53e3
AB		 288static long long int
289extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 290 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 291{
886a2506 292 return 31;
0d2bcfaf
NC		 293}
294
bdfe53e3
AB		 295static unsigned long long
296insert_ilink1 (unsigned long long insn,
297 long long int value,
886a2506 298 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 299{
886a2506
NC		 300 if (value != 29)
301 *errmsg = _("Register must be ILINK1.");
252b5132
RH		 302 return insn;
303}
304
bdfe53e3
AB		 305static long long int
306extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 307 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 308{
886a2506 309 return 29;
252b5132
RH		 310}
311
bdfe53e3
AB		 312static unsigned long long
313insert_ilink2 (unsigned long long insn,
314 long long int value,
886a2506 315 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 316{
886a2506
NC		 317 if (value != 30)
318 *errmsg = _("Register must be ILINK2.");
252b5132
RH		 319 return insn;
320}
321
bdfe53e3
AB		 322static long long int
323extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 324 bfd_boolean * invalid ATTRIBUTE_UNUSED)
325{
326 return 30;
327}
252b5132 328
bdfe53e3
AB		 329static unsigned long long
330insert_ras (unsigned long long insn,
331 long long int value,
886a2506 332 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 333{
886a2506 334 switch (value)
0d2bcfaf 335 {
886a2506
NC		 336 case 0:
337 case 1:
338 case 2:
339 case 3:
340 insn |= value;
341 break;
342 case 12:
343 case 13:
344 case 14:
345 case 15:
346 insn |= (value - 8);
347 break;
348 default:
349 *errmsg = _("Register must be either r0-r3 or r12-r15.");
350 break;
0d2bcfaf 351 }
252b5132
RH		 352 return insn;
353}
252b5132 354
bdfe53e3
AB		 355static long long int
356extract_ras (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 357 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 358{
886a2506
NC		 359 int value = insn & 0x07;
360 if (value > 3)
361 return (value + 8);
362 else
363 return value;
47b0e7ad
NC		 364}
365
bdfe53e3
AB		 366static unsigned long long
367insert_rbs (unsigned long long insn,
368 long long int value,
886a2506 369 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 370{
886a2506 371 switch (value)
47b0e7ad 372 {
886a2506
NC		 373 case 0:
374 case 1:
375 case 2:
376 case 3:
377 insn |= value << 8;
378 break;
379 case 12:
380 case 13:
381 case 14:
382 case 15:
383 insn |= ((value - 8)) << 8;
384 break;
385 default:
386 *errmsg = _("Register must be either r0-r3 or r12-r15.");
387 break;
47b0e7ad 388 }
886a2506 389 return insn;
252b5132
RH		 390}
391
bdfe53e3
AB		 392static long long int
393extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 394 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 395{
886a2506
NC		 396 int value = (insn >> 8) & 0x07;
397 if (value > 3)
398 return (value + 8);
399 else
400 return value;
401}
252b5132 402
bdfe53e3
AB		 403static unsigned long long
404insert_rcs (unsigned long long insn,
405 long long int value,
886a2506
NC		 406 const char **errmsg ATTRIBUTE_UNUSED)
407{
408 switch (value)
252b5132 409 {
886a2506
NC		 410 case 0:
411 case 1:
412 case 2:
413 case 3:
414 insn |= value << 5;
415 break;
416 case 12:
417 case 13:
418 case 14:
419 case 15:
420 insn |= ((value - 8)) << 5;
421 break;
422 default:
423 *errmsg = _("Register must be either r0-r3 or r12-r15.");
424 break;
252b5132 425 }
886a2506
NC		 426 return insn;
427}
47b0e7ad 428
bdfe53e3
AB		 429static long long int
430extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 431 bfd_boolean * invalid ATTRIBUTE_UNUSED)
432{
433 int value = (insn >> 5) & 0x07;
434 if (value > 3)
435 return (value + 8);
252b5132 436 else
886a2506
NC		 437 return value;
438}
47b0e7ad 439
bdfe53e3
AB		 440static unsigned long long
441insert_simm3s (unsigned long long insn,
442 long long int value,
886a2506
NC		 443 const char **errmsg ATTRIBUTE_UNUSED)
444{
445 int tmp = 0;
446 switch (value)
47b0e7ad 447 {
886a2506
NC		 448 case -1:
449 tmp = 0x07;
47b0e7ad 450 break;
886a2506
NC		 451 case 0:
452 tmp = 0x00;
453 break;
454 case 1:
455 tmp = 0x01;
47b0e7ad 456 break;
886a2506
NC		 457 case 2:
458 tmp = 0x02;
47b0e7ad 459 break;
886a2506
NC		 460 case 3:
461 tmp = 0x03;
462 break;
463 case 4:
464 tmp = 0x04;
465 break;
466 case 5:
467 tmp = 0x05;
468 break;
469 case 6:
470 tmp = 0x06;
471 break;
472 default:
473 *errmsg = _("Accepted values are from -1 to 6.");
47b0e7ad
NC		 474 break;
475 }
476
886a2506
NC		 477 insn |= tmp << 8;
478 return insn;
47b0e7ad
NC		 479}
480
bdfe53e3
AB		 481static long long int
482extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 483 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 484{
886a2506
NC		 485 int value = (insn >> 8) & 0x07;
486 if (value == 7)
487 return -1;
47b0e7ad 488 else
886a2506 489 return value;
47b0e7ad
NC		 490}
491
bdfe53e3
AB		 492static unsigned long long
493insert_rrange (unsigned long long insn,
494 long long int value,
886a2506 495 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 496{
886a2506
NC		 497 int reg1 = (value >> 16) & 0xFFFF;
498 int reg2 = value & 0xFFFF;
499 if (reg1 != 13)
500 {
501 *errmsg = _("First register of the range should be r13.");
502 return insn;
503 }
504 if (reg2 < 13 || reg2 > 26)
505 {
506 *errmsg = _("Last register of the range doesn't fit.");
507 return insn;
508 }
509 insn |= ((reg2 - 12) & 0x0F) << 1;
510 return insn;
47b0e7ad
NC		 511}
512
bdfe53e3
AB		 513static long long int
514extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 515 bfd_boolean * invalid ATTRIBUTE_UNUSED)
516{
517 return (insn >> 1) & 0x0F;
518}
47b0e7ad 519
bdfe53e3
AB		 520static unsigned long long
521insert_fpel (unsigned long long insn,
522 long long int value,
886a2506 523 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 524{
886a2506
NC		 525 if (value != 27)
526 {
527 *errmsg = _("Invalid register number, should be fp.");
528 return insn;
529 }
47b0e7ad 530
886a2506
NC		 531 insn |= 0x0100;
532 return insn;
47b0e7ad
NC		 533}
534
bdfe53e3
AB		 535static long long int
536extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 537 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 538{
886a2506 539 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 540}
541
bdfe53e3
AB		 542static unsigned long long
543insert_blinkel (unsigned long long insn,
544 long long int value,
886a2506 545 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 546{
886a2506 547 if (value != 31)
47b0e7ad 548 {
886a2506
NC		 549 *errmsg = _("Invalid register number, should be blink.");
550 return insn;
47b0e7ad 551 }
47b0e7ad 552
886a2506
NC		 553 insn |= 0x0200;
554 return insn;
47b0e7ad
NC		 555}
556
bdfe53e3
AB		 557static long long int
558extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 559 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 560{
886a2506
NC		 561 return (insn & 0x0200) ? 31 : -1;
562}
47b0e7ad 563
bdfe53e3
AB		 564static unsigned long long
565insert_pclel (unsigned long long insn,
566 long long int value,
886a2506
NC		 567 const char **errmsg ATTRIBUTE_UNUSED)
568{
569 if (value != 63)
47b0e7ad 570 {
886a2506
NC		 571 *errmsg = _("Invalid register number, should be pcl.");
572 return insn;
47b0e7ad 573 }
47b0e7ad 574
886a2506
NC		 575 insn |= 0x0400;
576 return insn;
577}
47b0e7ad 578
bdfe53e3
AB		 579static long long int
580extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 581 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 582{
886a2506 583 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 584}
47b0e7ad 585
886a2506
NC		 586#define INSERT_W6
587/* mask = 00000000000000000000111111000000
588 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
bdfe53e3
AB		 589static unsigned long long
590insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
591 long long int value ATTRIBUTE_UNUSED,
886a2506 592 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 593{
886a2506 594 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 595
886a2506
NC		 596 return insn;
597}
47b0e7ad 598
886a2506
NC		 599#define EXTRACT_W6
600/* mask = 00000000000000000000111111000000. */
bdfe53e3
AB		 601static long long int
602extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 603 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 604{
886a2506 605 unsigned value = 0;
47b0e7ad 606
886a2506 607 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 608
886a2506
NC		 609 return value;
610}
47b0e7ad 611
886a2506
NC		 612#define INSERT_G_S
613/* mask = 0000011100022000
614 insn = 01000ggghhhGG0HH. */
bdfe53e3
AB		 615static unsigned long long
616insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
617 long long int value ATTRIBUTE_UNUSED,
886a2506 618 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 619{
886a2506
NC		 620 insn |= ((value >> 0) & 0x0007) << 8;
621 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 622
886a2506
NC		 623 return insn;
624}
252b5132 625
886a2506
NC		 626#define EXTRACT_G_S
627/* mask = 0000011100022000. */
bdfe53e3
AB		 628static long long int
629extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 630 bfd_boolean * invalid ATTRIBUTE_UNUSED)
631{
632 int value = 0;
252b5132 633
886a2506
NC		 634 value |= ((insn >> 8) & 0x0007) << 0;
635 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 636
886a2506
NC		 637 /* Extend the sign. */
638 int signbit = 1 << (6 - 1);
639 value = (value ^ signbit) - signbit;
252b5132 640
886a2506 641 return value;
252b5132
RH		 642}
643
e23e8ebe 644/* ARC NPS400 Support: See comment near head of file. */
bdfe53e3
AB		 645#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
646static unsigned long long \
647insert_nps_3bit_reg_at_##OFFSET##_##NAME \
648 (unsigned long long insn ATTRIBUTE_UNUSED, \
649 long long int value ATTRIBUTE_UNUSED, \
650 const char **errmsg ATTRIBUTE_UNUSED) \
651{ \
652 switch (value) \
653 { \
654 case 0: \
655 case 1: \
656 case 2: \
657 case 3: \
658 insn |= value << (OFFSET); \
659 break; \
660 case 12: \
661 case 13: \
662 case 14: \
663 case 15: \
664 insn |= (value - 8) << (OFFSET); \
665 break; \
666 default: \
667 *errmsg = _("Register must be either r0-r3 or r12-r15."); \
668 break; \
669 } \
670 return insn; \
671} \
672 \
673static long long int \
674extract_nps_3bit_reg_at_##OFFSET##_##NAME \
675 (unsigned long long insn ATTRIBUTE_UNUSED, \
676 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
677{ \
678 int value = (insn >> (OFFSET)) & 0x07; \
679 if (value > 3) \
680 value += 8; \
681 return value; \
682} \
683
684MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
685MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
686MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
687MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
688
689MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
690MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
691MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
692MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
693
694static unsigned long long
695insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
696 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 697 const char **errmsg ATTRIBUTE_UNUSED)
698{
699 switch (value)
700 {
701 case 1:
702 value = 0;
703 break;
704 case 2:
705 value = 1;
706 break;
707 case 4:
708 value = 2;
709 break;
710 case 8:
711 value = 3;
712 break;
713 default:
714 value = 0;
715 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
716 break;
717 }
718
719 insn |= value << 10;
720 return insn;
721}
722
bdfe53e3
AB		 723static long long int
724extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 725 bfd_boolean * invalid ATTRIBUTE_UNUSED)
726{
727 return 1 << ((insn >> 10) & 0x3);
728}
729
bdfe53e3
AB		 730static unsigned long long
731insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
732 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 733 const char **errmsg ATTRIBUTE_UNUSED)
734{
735 insn |= ((value >> 5) & 7) << 12;
736 insn |= (value & 0x1f);
737 return insn;
738}
739
bdfe53e3
AB		 740static long long int
741extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 742 bfd_boolean * invalid ATTRIBUTE_UNUSED)
743{
744 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
745}
746
bdfe53e3
AB		 747static unsigned long long
748insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
749 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 750 const char **errmsg ATTRIBUTE_UNUSED)
751{
752 switch (value)
753 {
754 case 1:
755 case 2:
756 case 4:
757 break;
758
759 default:
760 *errmsg = _("invalid immediate, must be 1, 2, or 4");
761 value = 0;
762 }
763
764 insn |= (value << 6);
765 return insn;
766}
767
bdfe53e3
AB		 768static long long int
769extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 770 bfd_boolean * invalid ATTRIBUTE_UNUSED)
771{
772 return (insn >> 6) & 0x3f;
773}
774
bdfe53e3
AB		 775static unsigned long long
776insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
777 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 778 const char **errmsg ATTRIBUTE_UNUSED)
779{
780 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
781 return insn;
782}
783
bdfe53e3
AB		 784static long long int
785extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 786 bfd_boolean * invalid ATTRIBUTE_UNUSED)
787{
788 return (insn & 0x1f);
789}
790
bdfe53e3
AB		 791static unsigned long long
792insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
793 long long int value ATTRIBUTE_UNUSED,
4b0c052e
AB		 794 const char **errmsg ATTRIBUTE_UNUSED)
795{
796 int top = (value >> 16) & 0xffff;
797 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
798 *errmsg = _("invalid value for CMEM ld/st immediate");
799 insn |= (value & 0xffff);
800 return insn;
801}
802
bdfe53e3
AB		 803static long long int
804extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
4b0c052e
AB		 805 bfd_boolean * invalid ATTRIBUTE_UNUSED)
806{
807 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
808}
809
537aefaf 810#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
bdfe53e3
AB		 811static unsigned long long \
812insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
813 long long int value ATTRIBUTE_UNUSED, \
537aefaf
AB		 814 const char **errmsg ATTRIBUTE_UNUSED) \
815{ \
816 switch (value) \
817 { \
818 case 0: \
819 case 8: \
820 case 16: \
821 case 24: \
822 value = value / 8; \
823 break; \
824 default: \
825 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
826 value = 0; \
827 } \
828 insn |= (value << SHIFT); \
829 return insn; \
830} \
831 \
bdfe53e3
AB		 832static long long int \
833extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
537aefaf
AB		 834 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
835{ \
836 return ((insn >> SHIFT) & 0x3) * 8; \
837}
838
839MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
840MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
841
9ba75c88 842#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
bdfe53e3
AB		 843static unsigned long long \
844insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
845 long long int value ATTRIBUTE_UNUSED, \
9ba75c88 846 const char **errmsg ATTRIBUTE_UNUSED) \
537aefaf 847 { \
9ba75c88 848 if (value < LOWER || value > UPPER) \
537aefaf
AB		 849 { \
850 *errmsg = _("Invalid size, value must be " \
851 #LOWER " to " #UPPER "."); \
852 return insn; \
853 } \
854 value -= BIAS; \
855 insn |= (value << SHIFT); \
856 return insn; \
857 } \
858 \
bdfe53e3
AB		 859static long long int \
860extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
9ba75c88 861 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 862{ \
863 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
864}
865
db18dbab
GM		 866MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
867MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
868MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
869MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
870MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
871MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
872MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
873MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
874MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
875MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
876MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf 877
bdfe53e3
AB		 878static long long int
879extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 880 bfd_boolean * invalid ATTRIBUTE_UNUSED)
881{
882 int m3 = (insn >> 5) & 0xf;
883 if (m3 == 0xf)
884 *invalid = TRUE;
885 return m3;
886}
887
bdfe53e3
AB		 888static long long int
889extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 890 bfd_boolean * invalid ATTRIBUTE_UNUSED)
891{
892 bfd_boolean tmp_invalid = FALSE;
893 int m2 = (insn >> 15) & 0x1;
894 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
895
896 if (m2 == 0 && m3 == 0xf)
897 *invalid = TRUE;
898 return m2;
899}
900
bdfe53e3
AB		 901static long long int
902extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 903 bfd_boolean * invalid ATTRIBUTE_UNUSED)
904{
905 bfd_boolean tmp_invalid = FALSE;
906 int m1 = (insn >> 14) & 0x1;
907 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
908 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
909
910 if (m1 == 0 && m2 == 0 && m3 == 0xf)
911 *invalid = TRUE;
912 return m1;
913}
914
bdfe53e3
AB		 915static unsigned long long
916insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
917 long long int value ATTRIBUTE_UNUSED,
537aefaf
AB		 918 const char **errmsg ATTRIBUTE_UNUSED)
919{
920 unsigned pwr;
921
922 if (value < 1 || value > 256)
923 {
924 *errmsg = _("value out of range 1 - 256");
925 return 0;
926 }
927
928 for (pwr = 0; (value & 1) == 0; value >>= 1)
929 ++pwr;
930
931 if (value != 1)
932 {
933 *errmsg = _("value must be power of 2");
934 return 0;
935 }
936
937 return insn | (pwr << 8);
938}
939
bdfe53e3
AB		 940static long long int
941extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 942 bfd_boolean * invalid ATTRIBUTE_UNUSED)
943{
944 unsigned entry_size = (insn >> 8) & 0xf;
945 return 1 << entry_size;
946}
947
bdfe53e3
AB		 948static unsigned long long
949insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
950 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 951 const char **errmsg ATTRIBUTE_UNUSED)
952{
bdfe53e3 953 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
4eb6f892
AB		 954}
955
bdfe53e3
AB		 956static long long int
957extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 958 bfd_boolean * invalid ATTRIBUTE_UNUSED)
959{
bdfe53e3 960 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
4eb6f892
AB		 961}
962
bdfe53e3
AB		 963static unsigned long long
964insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
965 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 966 const char **errmsg ATTRIBUTE_UNUSED)
967{
bdfe53e3 968 return insn | (value << 42) | (value << 37);
4eb6f892
AB		 969}
970
bdfe53e3
AB		 971static long long int
972extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 973 bfd_boolean * invalid ATTRIBUTE_UNUSED)
974{
bdfe53e3 975 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
4eb6f892 976 *invalid = TRUE;
bdfe53e3 977 return ((insn >> 37) & 0x1f);
4eb6f892
AB		 978}
979
bdfe53e3
AB		 980static unsigned long long
981insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
982 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 983 const char **errmsg ATTRIBUTE_UNUSED)
984{
985 if (value < 0 || value > 28)
986 *errmsg = _("Value must be in the range 0 to 28");
987 return insn | (value << 20);
988}
989
bdfe53e3
AB		 990static long long int
991extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 992 bfd_boolean * invalid ATTRIBUTE_UNUSED)
993{
994 int value = (insn >> 20) & 0x1f;
995 if (value > 28)
996 *invalid = TRUE;
997 return value;
998}
999
14053c19 1000#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
bdfe53e3
AB		 1001static unsigned long long \
1002insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1003 long long int value ATTRIBUTE_UNUSED, \
14053c19
GM		 1004 const char **errmsg ATTRIBUTE_UNUSED) \
1005{ \
1006 if (value < 1 || value > UPPER) \
1007 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1008 if (value == UPPER) \
1009 value = 0; \
1010 return insn | (value << SHIFT); \
1011} \
1012 \
bdfe53e3
AB		 1013static long long int \
1014extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
14053c19
GM		 1015 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1016{ \
1017 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1018 if (value == 0) \
1019 value = UPPER; \
1020 return value; \
1021}
1022
db18dbab
GM		 1023MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1024MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1025MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1026MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1027MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1028MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
14053c19 1029
bdfe53e3
AB		 1030static unsigned long long
1031insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
1032 long long int value ATTRIBUTE_UNUSED,
14053c19
GM		 1033 const char **errmsg ATTRIBUTE_UNUSED)
1034{
1035 if (value < 0 || value > 240)
1036 *errmsg = _("Value must be in the range 0 to 240");
1037 if ((value % 16) != 0)
1038 *errmsg = _("Value must be a multiple of 16");
1039 value = value / 16;
1040 return insn | (value << 6);
1041}
1042
bdfe53e3
AB		 1043static long long int
1044extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
14053c19
GM		 1045 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1046{
1047 int value = (insn >> 6) & 0xF;
1048 return value * 16;
1049}
1050
db18dbab 1051#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
bdfe53e3
AB		 1052static unsigned long long \
1053insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1054 long long int value ATTRIBUTE_UNUSED, \
db18dbab
GM		 1055 const char **errmsg ATTRIBUTE_UNUSED) \
1056{ \
1057 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1058 *errmsg = _("Invalid address type for operand"); \
1059 return insn; \
1060} \
1061 \
bdfe53e3
AB		 1062static long long int \
1063extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
db18dbab
GM		 1064 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1065{ \
1066 return ARC_NPS400_ADDRTYPE_##VALUE; \
1067}
1068
1069MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1070MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1071MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1072MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1073MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1074MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1075MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1076MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1077MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1078MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1079MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1080MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1081MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1082MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1083MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1084MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1085
886a2506
NC		 1086/* Include the generic extract/insert functions. Order is important
1087 as some of the functions present in the .h may be disabled via
1088 defines. */
1089#include "arc-fxi.h"
252b5132 1090
886a2506 1091/* The flag operands table.
252b5132 1092
886a2506
NC		 1093 The format of the table is
1094 NAME CODE BITS SHIFT FAVAIL. */
1095const struct arc_flag_operand arc_flag_operands[] =
1096{
1097#define F_NULL 0
1098 { 0, 0, 0, 0, 0},
1099#define F_ALWAYS (F_NULL + 1)
1100 { "al", 0, 0, 0, 0 },
1101#define F_RA (F_ALWAYS + 1)
1102 { "ra", 0, 0, 0, 0 },
1103#define F_EQUAL (F_RA + 1)
1104 { "eq", 1, 5, 0, 1 },
1105#define F_ZERO (F_EQUAL + 1)
1106 { "z", 1, 5, 0, 0 },
1107#define F_NOTEQUAL (F_ZERO + 1)
1108 { "ne", 2, 5, 0, 1 },
1109#define F_NOTZERO (F_NOTEQUAL + 1)
1110 { "nz", 2, 5, 0, 0 },
1111#define F_POZITIVE (F_NOTZERO + 1)
1112 { "p", 3, 5, 0, 1 },
1113#define F_PL (F_POZITIVE + 1)
1114 { "pl", 3, 5, 0, 0 },
1115#define F_NEGATIVE (F_PL + 1)
1116 { "n", 4, 5, 0, 1 },
1117#define F_MINUS (F_NEGATIVE + 1)
1118 { "mi", 4, 5, 0, 0 },
1119#define F_CARRY (F_MINUS + 1)
1120 { "c", 5, 5, 0, 1 },
1121#define F_CARRYSET (F_CARRY + 1)
1122 { "cs", 5, 5, 0, 0 },
1123#define F_LOWER (F_CARRYSET + 1)
1124 { "lo", 5, 5, 0, 0 },
1125#define F_CARRYCLR (F_LOWER + 1)
1126 { "cc", 6, 5, 0, 0 },
1127#define F_NOTCARRY (F_CARRYCLR + 1)
1128 { "nc", 6, 5, 0, 1 },
1129#define F_HIGHER (F_NOTCARRY + 1)
1130 { "hs", 6, 5, 0, 0 },
1131#define F_OVERFLOWSET (F_HIGHER + 1)
1132 { "vs", 7, 5, 0, 0 },
1133#define F_OVERFLOW (F_OVERFLOWSET + 1)
1134 { "v", 7, 5, 0, 1 },
1135#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1136 { "nv", 8, 5, 0, 1 },
1137#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1138 { "vc", 8, 5, 0, 0 },
1139#define F_GT (F_OVERFLOWCLR + 1)
1140 { "gt", 9, 5, 0, 1 },
1141#define F_GE (F_GT + 1)
1142 { "ge", 10, 5, 0, 1 },
1143#define F_LT (F_GE + 1)
1144 { "lt", 11, 5, 0, 1 },
1145#define F_LE (F_LT + 1)
1146 { "le", 12, 5, 0, 1 },
1147#define F_HI (F_LE + 1)
1148 { "hi", 13, 5, 0, 1 },
1149#define F_LS (F_HI + 1)
1150 { "ls", 14, 5, 0, 1 },
1151#define F_PNZ (F_LS + 1)
1152 { "pnz", 15, 5, 0, 1 },
1153
1154 /* FLAG. */
1155#define F_FLAG (F_PNZ + 1)
1156 { "f", 1, 1, 15, 1 },
1157#define F_FFAKE (F_FLAG + 1)
1158 { "f", 0, 0, 0, 1 },
1159
1160 /* Delay slot. */
1161#define F_ND (F_FFAKE + 1)
1162 { "nd", 0, 1, 5, 0 },
1163#define F_D (F_ND + 1)
1164 { "d", 1, 1, 5, 1 },
1165#define F_DFAKE (F_D + 1)
1166 { "d", 0, 0, 0, 1 },
2b848ebd
CZ		 1167#define F_DNZ_ND (F_DFAKE + 1)
1168 { "nd", 0, 1, 16, 0 },
1169#define F_DNZ_D (F_DNZ_ND + 1)
1170 { "d", 1, 1, 16, 1 },
886a2506
NC		 1171
1172 /* Data size. */
2b848ebd 1173#define F_SIZEB1 (F_DNZ_D + 1)
886a2506
NC		 1174 { "b", 1, 2, 1, 1 },
1175#define F_SIZEB7 (F_SIZEB1 + 1)
1176 { "b", 1, 2, 7, 1 },
1177#define F_SIZEB17 (F_SIZEB7 + 1)
1178 { "b", 1, 2, 17, 1 },
1179#define F_SIZEW1 (F_SIZEB17 + 1)
1180 { "w", 2, 2, 1, 0 },
1181#define F_SIZEW7 (F_SIZEW1 + 1)
1182 { "w", 2, 2, 7, 0 },
1183#define F_SIZEW17 (F_SIZEW7 + 1)
1184 { "w", 2, 2, 17, 0 },
1185
1186 /* Sign extension. */
1187#define F_SIGN6 (F_SIZEW17 + 1)
1188 { "x", 1, 1, 6, 1 },
1189#define F_SIGN16 (F_SIGN6 + 1)
1190 { "x", 1, 1, 16, 1 },
1191#define F_SIGNX (F_SIGN16 + 1)
1192 { "x", 0, 0, 0, 1 },
1193
1194 /* Address write-back modes. */
1195#define F_A3 (F_SIGNX + 1)
1196 { "a", 1, 2, 3, 0 },
1197#define F_A9 (F_A3 + 1)
1198 { "a", 1, 2, 9, 0 },
1199#define F_A22 (F_A9 + 1)
1200 { "a", 1, 2, 22, 0 },
1201#define F_AW3 (F_A22 + 1)
1202 { "aw", 1, 2, 3, 1 },
1203#define F_AW9 (F_AW3 + 1)
1204 { "aw", 1, 2, 9, 1 },
1205#define F_AW22 (F_AW9 + 1)
1206 { "aw", 1, 2, 22, 1 },
1207#define F_AB3 (F_AW22 + 1)
1208 { "ab", 2, 2, 3, 1 },
1209#define F_AB9 (F_AB3 + 1)
1210 { "ab", 2, 2, 9, 1 },
1211#define F_AB22 (F_AB9 + 1)
1212 { "ab", 2, 2, 22, 1 },
1213#define F_AS3 (F_AB22 + 1)
1214 { "as", 3, 2, 3, 1 },
1215#define F_AS9 (F_AS3 + 1)
1216 { "as", 3, 2, 9, 1 },
1217#define F_AS22 (F_AS9 + 1)
1218 { "as", 3, 2, 22, 1 },
1219#define F_ASFAKE (F_AS22 + 1)
1220 { "as", 0, 0, 0, 1 },
1221
1222 /* Cache bypass. */
1223#define F_DI5 (F_ASFAKE + 1)
1224 { "di", 1, 1, 5, 1 },
1225#define F_DI11 (F_DI5 + 1)
1226 { "di", 1, 1, 11, 1 },
1227#define F_DI15 (F_DI11 + 1)
1228 { "di", 1, 1, 15, 1 },
1229
1230 /* ARCv2 specific. */
1231#define F_NT (F_DI15 + 1)
1232 { "nt", 0, 1, 3, 1},
1233#define F_T (F_NT + 1)
1234 { "t", 1, 1, 3, 1},
1235#define F_H1 (F_T + 1)
1236 { "h", 2, 2, 1, 1 },
1237#define F_H7 (F_H1 + 1)
1238 { "h", 2, 2, 7, 1 },
1239#define F_H17 (F_H7 + 1)
1240 { "h", 2, 2, 17, 1 },
1241
1242 /* Fake Flags. */
1243#define F_NE (F_H17 + 1)
1244 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1245
1246 /* ARC NPS400 Support: See comment near head of file. */
1247#define F_NPS_CL (F_NE + 1)
1248 { "cl", 0, 0, 0, 1 },
1249
1250#define F_NPS_FLAG (F_NPS_CL + 1)
1251 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1252
1253#define F_NPS_R (F_NPS_FLAG + 1)
1254 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1255
1256#define F_NPS_RW (F_NPS_R + 1)
1257 { "rw", 0, 1, 7, 1 },
1258
1259#define F_NPS_RD (F_NPS_RW + 1)
1260 { "rd", 1, 1, 7, 1 },
1261
1262#define F_NPS_WFT (F_NPS_RD + 1)
1263 { "wft", 0, 0, 0, 1 },
1264
1265#define F_NPS_IE1 (F_NPS_WFT + 1)
1266 { "ie1", 1, 2, 8, 1 },
1267
1268#define F_NPS_IE2 (F_NPS_IE1 + 1)
1269 { "ie2", 2, 2, 8, 1 },
1270
1271#define F_NPS_IE12 (F_NPS_IE2 + 1)
1272 { "ie12", 3, 2, 8, 1 },
1273
1274#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1275 { "rd", 0, 1, 6, 1 },
1276
1277#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1278 { "wr", 1, 1, 6, 1 },
1279
1280#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1281 { "off", 0, 0, 0, 1 },
1282
1283#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1284 { "restore", 0, 0, 0, 1 },
1285
537aefaf
AB		 1286#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1287 { "sx", 1, 1, 14, 1 },
1288
1289#define F_NPS_AR (F_NPS_SX + 1)
1290 { "ar", 0, 1, 0, 1 },
1291
1292#define F_NPS_AL (F_NPS_AR + 1)
1293 { "al", 1, 1, 0, 1 },
14053c19
GM		 1294
1295#define F_NPS_S (F_NPS_AL + 1)
1296 { "s", 0, 0, 0, 1 },
1297
1298#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1299 { "rd", 0, 1, 15, 1 },
1300
1301#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1302 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1303
1304#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1305 { "p0", 0, 0, 0, 1 },
1306
1307#define F_NPS_P1 (F_NPS_P0 + 1)
1308 { "p1", 0, 0, 0, 1 },
1309
1310#define F_NPS_P2 (F_NPS_P1 + 1)
1311 { "p2", 0, 0, 0, 1 },
1312
1313#define F_NPS_P3 (F_NPS_P2 + 1)
1314 { "p3", 0, 0, 0, 1 },
28215275
GM		 1315
1316#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1317 { "di", 0, 0, 0, 1 },
1318
1319#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1320 { "cl", 1, 1, 6, 1 },
1321
1322#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1323 { "cl", 1, 1, 16, 1 },
1324
1325#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1326 { "x2", 1, 2, 9, 1 },
1327
1328#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1329 { "x2", 1, 2, 22, 1 },
1330
1331#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1332 { "x4", 2, 2, 9, 1 },
1333
1334#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1335 { "x4", 2, 2, 22, 1 },
886a2506 1336};
252b5132 1337
886a2506 1338const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1339
886a2506 1340/* Table of the flag classes.
252b5132 1341
886a2506
NC		 1342 The format of the table is
1343 CLASS {FLAG_CODE}. */
1344const struct arc_flag_class arc_flag_classes[] =
1345{
1346#define C_EMPTY 0
1ae8ab47 1347 { F_CLASS_NONE, { F_NULL } },
886a2506
NC		 1348
1349#define C_CC (C_EMPTY + 1)
d9eca1df 1350 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1351 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1352 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1353 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1354 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1355 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1356 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1357
1358#define C_AA_ADDR3 (C_CC + 1)
1359#define C_AA27 (C_CC + 1)
1ae8ab47 1360 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1361#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1362#define C_AA21 (C_AA_ADDR3 + 1)
1ae8ab47 1363 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1364#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1365#define C_AA8 (C_AA_ADDR9 + 1)
1ae8ab47 1366 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1367
1368#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1369 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1370#define C_FHARD (C_F + 1)
1ae8ab47 1371 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1372
1373#define C_T (C_FHARD + 1)
1ae8ab47 1374 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1375#define C_D (C_T + 1)
1ae8ab47 1376 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
2b848ebd
CZ		 1377#define C_DNZ_D (C_D + 1)
1378 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
886a2506 1379
2b848ebd 1380#define C_DHARD (C_DNZ_D + 1)
1ae8ab47 1381 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1382
1383#define C_DI20 (C_DHARD + 1)
1ae8ab47 1384 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
886a2506 1385#define C_DI16 (C_DI20 + 1)
1ae8ab47 1386 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1387#define C_DI26 (C_DI16 + 1)
1ae8ab47 1388 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1389
1390#define C_X25 (C_DI26 + 1)
1ae8ab47 1391 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1392#define C_X15 (C_X25 + 1)
1ae8ab47 1393 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1394#define C_XHARD (C_X15 + 1)
1395#define C_X (C_X15 + 1)
1ae8ab47 1396 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1397
1398#define C_ZZ13 (C_X + 1)
1ae8ab47 1399 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1400#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1401 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1402#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1403 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1404
1405#define C_AS (C_ZZ29 + 1)
1ae8ab47 1406 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1407
1408#define C_NE (C_AS + 1)
1ae8ab47 1409 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1410
1411 /* ARC NPS400 Support: See comment near head of file. */
1412#define C_NPS_CL (C_NE + 1)
1413 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1414
1415#define C_NPS_F (C_NPS_CL + 1)
1416 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1417
1418#define C_NPS_R (C_NPS_F + 1)
1419 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1420
1421#define C_NPS_SCHD_RW (C_NPS_R + 1)
1422 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1423
1424#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1425 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1426
1427#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1428 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1429
1430#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1431 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1432
1433#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1434 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1435
1436#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1437 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1438
537aefaf
AB		 1439#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1440 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1441
1442#define C_NPS_AR_AL (C_NPS_SX + 1)
1443 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1444
1445#define C_NPS_S (C_NPS_AR_AL + 1)
1446 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1447
1448#define C_NPS_ZNCV (C_NPS_S + 1)
1449 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1450
1451#define C_NPS_P0 (C_NPS_ZNCV + 1)
1452 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1453
1454#define C_NPS_P1 (C_NPS_P0 + 1)
1455 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1456
1457#define C_NPS_P2 (C_NPS_P1 + 1)
1458 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1459
1460#define C_NPS_P3 (C_NPS_P2 + 1)
1461 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1462
1463#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1464 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1465
1466#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1467 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1468
1469#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1470 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1471
1472#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1473 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1474
1475#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1476 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
886a2506 1477};
252b5132 1478
b99747ae
CZ		 1479const unsigned char flags_none[] = { 0 };
1480const unsigned char flags_f[] = { C_F };
1481const unsigned char flags_cc[] = { C_CC };
1482const unsigned char flags_ccf[] = { C_CC, C_F };
1483
886a2506 1484/* The operands table.
252b5132 1485
886a2506 1486 The format of the operands table is:
47b0e7ad 1487
886a2506
NC		 1488 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1489const struct arc_operand arc_operands[] =
0d2bcfaf 1490{
886a2506
NC		 1491 /* The fields are bits, shift, insert, extract, flags. The zero
1492 index is used to indicate end-of-list. */
1493#define UNUSED 0
1494 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1495
1496#define IGNORED (UNUSED + 1)
1497 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1498
886a2506
NC		 1499 /* The plain integer register fields. Used by 32 bit
1500 instructions. */
4eb6f892 1501#define RA (IGNORED + 1)
886a2506
NC		 1502 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1503#define RB (RA + 1)
1504 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1505#define RC (RB + 1)
1506 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1507#define RBdup (RC + 1)
1508 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1509
1510#define RAD (RBdup + 1)
1511 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1512#define RCD (RAD + 1)
1513 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1514
1515 /* The plain integer register fields. Used by short
1516 instructions. */
1517#define RA16 (RCD + 1)
1518#define RA_S (RCD + 1)
1519 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1520#define RB16 (RA16 + 1)
1521#define RB_S (RA16 + 1)
1522 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1523#define RB16dup (RB16 + 1)
1524#define RB_Sdup (RB16 + 1)
1525 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1526#define RC16 (RB16dup + 1)
1527#define RC_S (RB16dup + 1)
1528 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1529#define R6H (RC16 + 1) /* 6bit register field 'h' used
1530 by V1 cpus. */
1531 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1532#define R5H (R6H + 1) /* 5bit register field 'h' used
1533 by V2 cpus. */
1534#define RH_S (R6H + 1) /* 5bit register field 'h' used
1535 by V2 cpus. */
1536 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1537#define R5Hdup (R5H + 1)
1538#define RH_Sdup (R5H + 1)
1539 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1540 insert_rhv2, extract_rhv2 },
1541
1542#define RG (R5Hdup + 1)
1543#define G_S (R5Hdup + 1)
1544 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1545
1546 /* Fix registers. */
1547#define R0 (RG + 1)
1548#define R0_S (RG + 1)
1549 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1550#define R1 (R0 + 1)
1551#define R1_S (R0 + 1)
1552 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1553#define R2 (R1 + 1)
1554#define R2_S (R1 + 1)
1555 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1556#define R3 (R2 + 1)
1557#define R3_S (R2 + 1)
1558 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1559#define RSP (R3 + 1)
886a2506
NC		 1560#define SP_S (R3 + 1)
1561 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1562#define SPdup (RSP + 1)
1563#define SP_Sdup (RSP + 1)
886a2506
NC		 1564 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1565#define GP (SPdup + 1)
1566#define GP_S (SPdup + 1)
1567 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1568
1569#define PCL_S (GP + 1)
1570 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1571
1572#define BLINK (PCL_S + 1)
1573#define BLINK_S (PCL_S + 1)
1574 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1575
1576#define ILINK1 (BLINK + 1)
1577 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1578#define ILINK2 (ILINK1 + 1)
1579 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1580
1581 /* Long immediate. */
1582#define LIMM (ILINK2 + 1)
1583#define LIMM_S (ILINK2 + 1)
1584 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1585#define LIMMdup (LIMM + 1)
1586 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1587
1588 /* Special operands. */
1589#define ZA (LIMMdup + 1)
1590#define ZB (LIMMdup + 1)
1591#define ZA_S (LIMMdup + 1)
1592#define ZB_S (LIMMdup + 1)
1593#define ZC_S (LIMMdup + 1)
1594 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1595
1596#define RRANGE_EL (ZA + 1)
1597 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1598 insert_rrange, extract_rrange},
1599#define FP_EL (RRANGE_EL + 1)
1600 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1601 insert_fpel, extract_fpel },
1602#define BLINK_EL (FP_EL + 1)
1603 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1604 insert_blinkel, extract_blinkel },
1605#define PCL_EL (BLINK_EL + 1)
1606 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1607 insert_pclel, extract_pclel },
1608
1609 /* Fake operand to handle the T flag. */
1610#define BRAKET (PCL_EL + 1)
1611#define BRAKETdup (PCL_EL + 1)
1612 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1613
1614 /* Fake operand to handle the T flag. */
1615#define FKT_T (BRAKET + 1)
1616 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1617 /* Fake operand to handle the T flag. */
1618#define FKT_NT (FKT_T + 1)
1619 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1620
1621 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1622#define UIMM6_20 (FKT_NT + 1)
1623 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1624
1625 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1626#define SIMM12_20 (UIMM6_20 + 1)
1627 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1628
1629 /* SIMM3_5_S mask = 0000011100000000. */
1630#define SIMM3_5_S (SIMM12_20 + 1)
1631 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1632 insert_simm3s, extract_simm3s},
1633
1634 /* UIMM7_A32_11_S mask = 0000000000011111. */
1635#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1636 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1637 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1638 extract_uimm7_a32_11_s},
1639
1640 /* UIMM7_9_S mask = 0000000001111111. */
1641#define UIMM7_9_S (UIMM7_A32_11_S + 1)
1642 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1643
1644 /* UIMM3_13_S mask = 0000000000000111. */
1645#define UIMM3_13_S (UIMM7_9_S + 1)
1646 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1647
1648 /* SIMM11_A32_7_S mask = 0000000111111111. */
1649#define SIMM11_A32_7_S (UIMM3_13_S + 1)
1650 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1651 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1652
1653 /* UIMM6_13_S mask = 0000000002220111. */
1654#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1655 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1656 /* UIMM5_11_S mask = 0000000000011111. */
1657#define UIMM5_11_S (UIMM6_13_S + 1)
1658 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1659 extract_uimm5_11_s},
1660
1661 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1662#define SIMM9_A16_8 (UIMM5_11_S + 1)
1663 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1664 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1665 extract_simm9_a16_8},
1666
1667 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1668#define UIMM6_8 (SIMM9_A16_8 + 1)
1669 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1670
1671 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1672#define SIMM21_A16_5 (UIMM6_8 + 1)
1673 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1674 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1675 insert_simm21_a16_5, extract_simm21_a16_5},
1676
1677 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1678#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1679 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1680 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1681 insert_simm25_a16_5, extract_simm25_a16_5},
1682
1683 /* SIMM10_A16_7_S mask = 0000000111111111. */
1684#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1685 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1686 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1687 extract_simm10_a16_7_s},
1688
1689#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1690 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1691 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1692
1693 /* SIMM7_A16_10_S mask = 0000000000111111. */
1694#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1695 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1696 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1697 extract_simm7_a16_10_s},
1698
1699 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1700#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1701 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1702 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1703 extract_simm21_a32_5},
1704
1705 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1706#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1707 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1708 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1709 extract_simm25_a32_5},
1710
1711 /* SIMM13_A32_5_S mask = 0000011111111111. */
1712#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1713 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1714 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1715 extract_simm13_a32_5_s},
1716
1717 /* SIMM8_A16_9_S mask = 0000000001111111. */
1718#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1719 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1720 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1721 extract_simm8_a16_9_s},
1722
1723 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1724#define UIMM3_23 (SIMM8_A16_9_S + 1)
1725 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1726
1727 /* UIMM10_6_S mask = 0000001111111111. */
1728#define UIMM10_6_S (UIMM3_23 + 1)
1729 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1730
1731 /* UIMM6_11_S mask = 0000002200011110. */
1732#define UIMM6_11_S (UIMM10_6_S + 1)
1733 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1734
1735 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1736#define SIMM9_8 (UIMM6_11_S + 1)
1737 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1738 insert_simm9_8, extract_simm9_8},
1739
1740 /* UIMM10_A32_8_S mask = 0000000011111111. */
1741#define UIMM10_A32_8_S (SIMM9_8 + 1)
1742 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1743 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1744 extract_uimm10_a32_8_s},
1745
1746 /* SIMM9_7_S mask = 0000000111111111. */
1747#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1748 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1749 extract_simm9_7_s},
1750
1751 /* UIMM6_A16_11_S mask = 0000000000011111. */
1752#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1753 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1754 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1755 extract_uimm6_a16_11_s},
1756
1757 /* UIMM5_A32_11_S mask = 0000020000011000. */
1758#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1759 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1760 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1761 extract_uimm5_a32_11_s},
1762
1763 /* SIMM11_A32_13_S mask = 0000022222200111. */
1764#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1765 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1766 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1767
1768 /* UIMM7_13_S mask = 0000000022220111. */
1769#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1770 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1771
1772 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1773#define UIMM6_A16_21 (UIMM7_13_S + 1)
1774 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1775 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1776
1777 /* UIMM7_11_S mask = 0000022200011110. */
1778#define UIMM7_11_S (UIMM6_A16_21 + 1)
1779 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1780
1781 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1782#define UIMM7_A16_20 (UIMM7_11_S + 1)
1783 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1784 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1785 extract_uimm7_a16_20},
1786
1787 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1788#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1789 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1790 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1791 extract_simm13_a16_20},
1792
1793 /* UIMM8_8_S mask = 0000000011111111. */
1794#define UIMM8_8_S (SIMM13_A16_20 + 1)
1795 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1796
1797 /* W6 mask = 00000000000000000000111111000000. */
1798#define W6 (UIMM8_8_S + 1)
1799 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1800
1801 /* UIMM6_5_S mask = 0000011111100000. */
1802#define UIMM6_5_S (W6 + 1)
1803 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 1804
1805 /* ARC NPS400 Support: See comment near head of file. */
1806#define NPS_R_DST_3B (UIMM6_5_S + 1)
bdfe53e3 1807 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 1808
1809#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
bdfe53e3 1810 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 1811
1812#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
bdfe53e3 1813 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
e23e8ebe
AB		 1814
1815#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 1816 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 1817
1818#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 1819 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 1820
1821#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1822 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1823
1824#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1825 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1826
1827#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 1828 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 1829
820f03ff
AB		 1830#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1831 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1832
1833#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1834 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1835
1836#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1837 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1838
1839#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 1840 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 1841
14053c19
GM		 1842#define NPS_SIMM16 (NPS_UIMM16 + 1)
1843 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
1844
1845#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
820f03ff 1846 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 1847
1848#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1849 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 1850
1851#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1852 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1853
1854#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1855 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1856
1857#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1858 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1859
1860#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1861 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1862
1863#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1864 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1865
1866#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1867 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1868
1869#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1870 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1871
1872#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1873 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1874
1875#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1876 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1877
1878#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1879 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1880
1881#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1882 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1883
1884#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1885 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1886
1887#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1888 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 1889
1890#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
bdfe53e3 1891 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 1892
1893#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
bdfe53e3 1894 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 1895
1896#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
bdfe53e3 1897 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
4eb6f892
AB		 1898
1899#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
1900 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
1901
1902#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
1903 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
1904
1905#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
1906 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
1907
1908#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
bdfe53e3 1909 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1910
1911#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
bdfe53e3 1912 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1913
1914#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
1915 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1916
1917#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
1918 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1919
1920#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
bdfe53e3 1921 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 1922
1923#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
1924 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1925
1926#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
1927 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1928
1929#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
1930 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1931
bdfe53e3
AB		 1932#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
1933 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
4eb6f892 1934
bdfe53e3 1935#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
4eb6f892
AB		 1936 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1937
1938#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
1939 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1940
1941#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
1942 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1943
1944#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
1945 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 1946
1947#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
1948 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1949
1950#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
1951 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
1952
1953#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
1954 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
1955
1956#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
1957 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
1958
1959#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
1960 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1961
1962#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
1963 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
1964
1965#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
1966 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
1967
1968#define NPS_PSBC (NPS_MIN_HOFS + 1)
1969 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 1970
1971#define NPS_DPI_DST (NPS_PSBC + 1)
1972 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
1973
1974 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
1975#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
bdfe53e3 1976 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
9ba75c88
GM		 1977
1978#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
1979 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
1980
1981#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
1982 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1983
1984#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
1985 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1986
1987#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
1988 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1989
1990#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
1991 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
1992
1993#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
1994 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1995
1996#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
1997 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1998
1999#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2000 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2001
2002#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2003 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2004
2005#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2006 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2007
2008#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2009 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2010
2011#define COLON (NPS_E4BY_INDEX3 + 1)
2012 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2013
2014#define NPS_BD (COLON + 1)
2015 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
2016
2017#define NPS_JID (NPS_BD + 1)
2018 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
2019
2020#define NPS_LBD (NPS_JID + 1)
2021 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
2022
2023#define NPS_MBD (NPS_LBD + 1)
2024 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
2025
2026#define NPS_SD (NPS_MBD + 1)
2027 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
2028
2029#define NPS_SM (NPS_SD + 1)
2030 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
2031
2032#define NPS_XA (NPS_SM + 1)
2033 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
2034
2035#define NPS_XD (NPS_XA + 1)
2036 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
2037
2038#define NPS_CD (NPS_XD + 1)
2039 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
2040
2041#define NPS_CBD (NPS_CD + 1)
2042 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
2043
2044#define NPS_CJID (NPS_CBD + 1)
2045 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
2046
2047#define NPS_CLBD (NPS_CJID + 1)
2048 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
2049
2050#define NPS_CM (NPS_CLBD + 1)
2051 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
2052
2053#define NPS_CSD (NPS_CM + 1)
2054 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
2055
2056#define NPS_CXA (NPS_CSD + 1)
2057 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
2058
2059#define NPS_CXD (NPS_CXA + 1)
2060 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
2061
2062#define NPS_BD_TYPE (NPS_CXD + 1)
2063 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2064
2065#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2066 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2067
2068#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2069 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2070
2071#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2072 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
bdfe53e3
AB		 2073
2074#define NPS_R_DST_3B_48 (NPS_PMU_NUM_JOB + 1)
2075 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2076
2077#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2078 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2079
2080#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2081 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2082
2083#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2084 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2085
2086#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2087 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2088
2089#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2090 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
886a2506 2091};
0d2bcfaf 2092
886a2506 2093const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2094
886a2506
NC		 2095const unsigned arc_Toperand = FKT_T;
2096const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2097
b99747ae
CZ		 2098const unsigned char arg_none[] = { 0 };
2099const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2100const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2101const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2102const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2103const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2104const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2105const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2106const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2107const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2108const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2109const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2110
2111const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2112const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2113const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2114
2115const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2116const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2117const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2118
2119const unsigned char arg_32bit_rbrc[] = { RB, RC };
2120const unsigned char arg_32bit_zarc[] = { ZA, RC };
2121const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2122const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2123const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2124const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2125
2126const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2127const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2128const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2129const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2130
945e0f82
CZ		 2131const unsigned char arg_32bit_rc[] = { RC };
2132const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2133const unsigned char arg_32bit_limm[] = { LIMM };
2134
886a2506 2135/* The opcode table.
0d2bcfaf 2136
886a2506 2137 The format of the opcode table is:
0d2bcfaf 2138
1328504b
AB		 2139 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2140
2141 The table is organised such that, where possible, all instructions with
2142 the same mnemonic are together in a block. When the assembler searches
2143 for a suitable instruction the entries are checked in table order, so
2144 more specific, or specialised cases should appear earlier in the table.
2145
2146 As an example, consider two instructions 'add a,b,u6' and 'add
2147 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2148 32-bit instruction, while the second takes a 32-bit immediate that is
2149 encoded in a follow-on 32-bit, making the total instruction length
2150 64-bits. In this case the u6 variant must appear first in the table, as
2151 all u6 immediates could also be encoded using the 'limm' extension,
2152 however, we want to use the shorter instruction wherever possible.
2153
2154 It is possible though to split instructions with the same mnemonic into
2155 multiple groups. However, the instructions are still checked in table
2156 order, even across groups. The only time that instructions with the
2157 same mnemonic should be split into different groups is when different
2158 variants of the instruction appear in different architectures, in which
2159 case, grouping all instructions from a particular architecture together
2160 might be preferable to merging the instruction into the main instruction
2161 table.
2162
2163 An example of this split instruction groups can be found with the 'sync'
2164 instruction. The core arc architecture provides a 'sync' instruction,
2165 while the nps instruction set extension provides 'sync.rd' and
2166 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2167 mnemonic, so we end up with two groups for the sync instruction, the
2168 first within the core arc instruction table, and the second within the
2169 nps extension instructions. */
886a2506 2170const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2171{
886a2506 2172#include "arc-tbl.h"
e23e8ebe 2173#include "arc-nps400-tbl.h"
f2dd8838 2174#include "arc-ext-tbl.h"
0d2bcfaf 2175
b99747ae
CZ		 2176 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2177};
252b5132 2178
886a2506
NC		 2179/* List with special cases instructions and the applicable flags. */
2180const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2181{
886a2506
NC		 2182 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2183 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2184 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2185 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2186 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2187 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2188 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2189 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2190 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2191 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2192 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2193 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2194 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2195 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2196 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2197 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2198 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2199 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2200 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2201 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2202 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2203 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2204 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2205 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2206 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2207 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2208 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2209 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2210 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2211 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2212};
252b5132 2213
886a2506 2214const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2215
886a2506 2216/* Relocations. */
886a2506
NC		 2217const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2218{
24b368f8
CZ		 2219 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2220 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2221 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2222 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2223 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2224 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2225 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2226 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2227
2228 /* Next two entries will cover the undefined behavior ldb/stb with
2229 address scaling. */
2230 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2231 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2232 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2233 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2234
2235 { "sda", "ld", { F_ASFAKE, F_NULL },
2236 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2237 { "sda", "st", { F_ASFAKE, F_NULL },
2238 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2239 { "sda", "ldd", { F_ASFAKE, F_NULL },
2240 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2241 { "sda", "std", { F_ASFAKE, F_NULL },
2242 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2243
2244 /* Short instructions. */
24b368f8
CZ		 2245 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2246 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2247 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2248 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2249
2250 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2251 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2252
2253 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2254 BFD_RELOC_ARC_S25H_PCREL_PLT },
2255 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2256 BFD_RELOC_ARC_S21H_PCREL_PLT },
2257 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2258 BFD_RELOC_ARC_S25W_PCREL_PLT },
2259 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2260 BFD_RELOC_ARC_S21W_PCREL_PLT },
2261
2262 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2263};
252b5132 2264
886a2506 2265const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2266
886a2506 2267const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2268{
886a2506
NC		 2269 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2270 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2271 { BRAKETdup, 1, 0, 4} } },
2272 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2273 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2274 { BRAKETdup, 1, 0, 4} } },
2275
2276 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2277 { SIMM9_A16_8, 0, 0, 2 } } },
2278 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2279 { SIMM9_A16_8, 0, 0, 2 } } },
2280 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2281 { SIMM9_A16_8, 0, 0, 2 } } },
2282 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2283 { SIMM9_A16_8, 0, 0, 2 } } },
2284 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2285 { SIMM9_A16_8, 0, 0, 2 } } },
2286
2287 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2288 { SIMM9_A16_8, 0, 0, 2 } } },
2289 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2290 { SIMM9_A16_8, 0, 0, 2 } } },
2291 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2292 { SIMM9_A16_8, 0, 0, 2 } } },
2293 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2294 { SIMM9_A16_8, 0, 0, 2 } } },
2295 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2296 { SIMM9_A16_8, 0, 0, 2 } } },
2297
2298 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2299 { SIMM9_A16_8, 0, 0, 2 } } },
2300 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2301 { SIMM9_A16_8, 0, 0, 2 } } },
2302 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2303 { SIMM9_A16_8, 0, 0, 2 } } },
2304 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2305 { SIMM9_A16_8, 0, 0, 2 } } },
2306 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2307 { SIMM9_A16_8, 0, 0, 2 } } },
2308
2309 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2310 { SIMM9_A16_8, 0, 0, 2 } } },
2311 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2312 { SIMM9_A16_8, 0, 0, 2 } } },
2313 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2314 { SIMM9_A16_8, 0, 0, 2 } } },
2315 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2316 { SIMM9_A16_8, 0, 0, 2 } } },
2317 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2318 { SIMM9_A16_8, 0, 0, 2 } } },
2319};
0d2bcfaf 2320
886a2506
NC		 2321const unsigned arc_num_pseudo_insn =
2322 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2323
886a2506 2324const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2325{
886a2506 2326#undef DEF
f36e33da
CZ		 2327#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2328 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2329
886a2506 2330#include "arc-regs.h"
0d2bcfaf 2331
886a2506
NC		 2332#undef DEF
2333};
0d2bcfaf 2334
886a2506 2335const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2336
2337/* NOTE: The order of this array MUST be consistent with 'enum
2338 arc_rlx_types' located in tc-arc.h! */
2339const struct arc_opcode arc_relax_opcodes[] =
2340{
2341 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2342
2343 /* bl_s s13 11111sssssssssss. */
2344 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2345 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2346 { SIMM13_A32_5_S }, { 0 }},
2347
2348 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2349 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2350 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2351 { SIMM25_A32_5 }, { C_D }},
2352
2353 /* b_s s10 1111000sssssssss. */
2354 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2355 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2356 { SIMM10_A16_7_S }, { 0 }},
2357
2358 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2359 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2360 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2361 { SIMM25_A16_5 }, { C_D }},
2362
2363 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2364 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2365 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2366 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2367
2368 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2369 UIMM6_20_PCREL. */
2370 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2371 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2372 { RA, RB, UIMM6_20 }, { C_F }},
2373
2374 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2375 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2376 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2377 { RA, RB, LIMM }, { C_F }},
2378
2379 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2380 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2381 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2382 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
2383
2384 /* ld<.di><.aa><.x><zz> a,b,s9
2385 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2386 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2387 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2388 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2389 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2390
2391 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2392 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2393 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2394 { RA, BRAKET, RB, LIMM, BRAKETdup },
2395 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2396
2397 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2398 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2399 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2400 { RB_S, UIMM8_8_S }, { 0 }},
2401
2402 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2403 SIMM12_20_PCREL. */
2404 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2405 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2406 { RB, SIMM12_20 }, { C_F }},
2407
2408 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2409 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2410 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2411 { RB, LIMM }, { C_F }},
2412
2413 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2414 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2415 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2416 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2417
2418 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2419 UIMM6_20_PCREL. */
2420 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2421 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2422 { RA, RB, UIMM6_20 }, { C_F }},
2423
2424 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2425 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2426 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2427 { RA, RB, LIMM }, { C_F }},
2428
2429 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2430 UIMM6_20_PCREL. */
2431 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2432 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2433
2434 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2435 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2436 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2437
2438 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2439 UIMM6_20_PCREL. */
2440 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2441 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2442 { RB, UIMM6_20 }, { C_F, C_CC }},
2443
2444 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2445 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2446 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2447 { RB, LIMM }, { C_F, C_CC }},
2448
2449 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2450 UIMM6_20_PCREL. */
2451 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2452 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2453 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2454
2455 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2456 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2457 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2458 { RB, RBdup, LIMM }, { C_F, C_CC }}
2459};
2460
2461const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892 2462
bdfe53e3 2463/* Return length of an opcode in bytes. */
06fe285f
GM		 2464
2465int
2466arc_opcode_len (const struct arc_opcode *opcode)
2467{
2468 if (opcode->mask < 0x10000ull)
2469 return 2;
bdfe53e3
AB		 2470
2471 if (opcode->mask < 0x100000000ull)
2472 return 4;
2473
2474 if (opcode->mask < 0x1000000000000ull)
2475 return 6;
2476
2477 return 8;
06fe285f 2478}
GDB Binutils - Deliverables
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