Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Opcode table for the ARC. |
b90efa5b | 2 | Copyright (C) 1994-2015 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) | |
bcee8eb8 | 5 | |
9b201bb5 NC |
6 | This file is part of libopcodes. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
252b5132 | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
252b5132 RH |
17 | |
18 | You should have received a copy of the GNU General Public License | |
0d2bcfaf | 19 | along with this program; if not, write to the Free Software Foundation, |
f4321104 | 20 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
5bd67f35 | 22 | #include "sysdep.h" |
252b5132 | 23 | #include <stdio.h> |
d943fe33 | 24 | #include "bfd.h" |
252b5132 | 25 | #include "opcode/arc.h" |
47b0e7ad | 26 | #include "opintl.h" |
886a2506 | 27 | #include "libiberty.h" |
252b5132 | 28 | |
886a2506 NC |
29 | /* Insert RB register into a 32-bit opcode. */ |
30 | static unsigned | |
31 | insert_rb (unsigned insn, | |
32 | int value, | |
33 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 34 | { |
886a2506 NC |
35 | return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); |
36 | } | |
0d2bcfaf | 37 | |
886a2506 NC |
38 | static int |
39 | extract_rb (unsigned insn ATTRIBUTE_UNUSED, | |
40 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
41 | { | |
42 | int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); | |
0d2bcfaf | 43 | |
886a2506 NC |
44 | if (value == 0x3e && invalid) |
45 | *invalid = TRUE; /* A limm operand, it should be extracted in a | |
46 | different way. */ | |
252b5132 | 47 | |
886a2506 NC |
48 | return value; |
49 | } | |
252b5132 | 50 | |
886a2506 NC |
51 | static unsigned |
52 | insert_rad (unsigned insn, | |
53 | int value, | |
54 | const char **errmsg ATTRIBUTE_UNUSED) | |
55 | { | |
56 | if (value & 0x01) | |
57 | *errmsg = _("Improper register value."); | |
0d2bcfaf | 58 | |
886a2506 NC |
59 | return insn | (value & 0x3F); |
60 | } | |
0d2bcfaf | 61 | |
886a2506 NC |
62 | static unsigned |
63 | insert_rcd (unsigned insn, | |
64 | int value, | |
65 | const char **errmsg ATTRIBUTE_UNUSED) | |
66 | { | |
67 | if (value & 0x01) | |
68 | *errmsg = _("Improper register value."); | |
0d2bcfaf | 69 | |
886a2506 NC |
70 | return insn | ((value & 0x3F) << 6); |
71 | } | |
252b5132 | 72 | |
886a2506 | 73 | /* Dummy insert ZERO operand function. */ |
252b5132 | 74 | |
886a2506 NC |
75 | static unsigned |
76 | insert_za (unsigned insn, | |
77 | int value, | |
78 | const char **errmsg) | |
79 | { | |
80 | if (value) | |
81 | *errmsg = _("operand is not zero"); | |
82 | return insn; | |
83 | } | |
252b5132 | 84 | |
886a2506 NC |
85 | /* Insert Y-bit in bbit/br instructions. This function is called only |
86 | when solving fixups. */ | |
252b5132 | 87 | |
886a2506 NC |
88 | static unsigned |
89 | insert_Ybit (unsigned insn, | |
90 | int value, | |
91 | const char **errmsg ATTRIBUTE_UNUSED) | |
92 | { | |
93 | if (value > 0) | |
94 | insn |= 0x08; | |
252b5132 | 95 | |
886a2506 NC |
96 | return insn; |
97 | } | |
252b5132 | 98 | |
886a2506 NC |
99 | /* Insert Y-bit in bbit/br instructions. This function is called only |
100 | when solving fixups. */ | |
252b5132 | 101 | |
886a2506 NC |
102 | static unsigned |
103 | insert_NYbit (unsigned insn, | |
104 | int value, | |
105 | const char **errmsg ATTRIBUTE_UNUSED) | |
106 | { | |
107 | if (value < 0) | |
108 | insn |= 0x08; | |
0d2bcfaf | 109 | |
886a2506 NC |
110 | return insn; |
111 | } | |
252b5132 | 112 | |
886a2506 | 113 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 114 | |
886a2506 NC |
115 | static unsigned |
116 | insert_rhv1 (unsigned insn, | |
117 | int value, | |
118 | const char **errmsg ATTRIBUTE_UNUSED) | |
119 | { | |
120 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); | |
121 | } | |
252b5132 | 122 | |
886a2506 NC |
123 | static int |
124 | extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED, | |
125 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
126 | { | |
127 | int value = 0; | |
252b5132 | 128 | |
886a2506 NC |
129 | return value; |
130 | } | |
252b5132 | 131 | |
886a2506 | 132 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 133 | |
886a2506 NC |
134 | static unsigned |
135 | insert_rhv2 (unsigned insn, | |
136 | int value, | |
137 | const char **errmsg) | |
0d2bcfaf | 138 | { |
886a2506 NC |
139 | if (value == 0x1E) |
140 | *errmsg = | |
141 | _("Register R30 is a limm indicator for this type of instruction."); | |
142 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); | |
143 | } | |
252b5132 | 144 | |
886a2506 NC |
145 | static int |
146 | extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, | |
147 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
148 | { | |
149 | int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); | |
0d2bcfaf | 150 | |
886a2506 NC |
151 | return value; |
152 | } | |
0d2bcfaf | 153 | |
886a2506 NC |
154 | static unsigned |
155 | insert_r0 (unsigned insn, | |
156 | int value, | |
157 | const char **errmsg ATTRIBUTE_UNUSED) | |
158 | { | |
159 | if (value != 0) | |
160 | *errmsg = _("Register must be R0."); | |
47b0e7ad NC |
161 | return insn; |
162 | } | |
252b5132 | 163 | |
886a2506 NC |
164 | static int |
165 | extract_r0 (unsigned insn ATTRIBUTE_UNUSED, | |
166 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 167 | { |
886a2506 | 168 | return 0; |
47b0e7ad | 169 | } |
252b5132 | 170 | |
252b5132 | 171 | |
886a2506 NC |
172 | static unsigned |
173 | insert_r1 (unsigned insn, | |
174 | int value, | |
175 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 176 | { |
886a2506 NC |
177 | if (value != 1) |
178 | *errmsg = _("Register must be R1."); | |
47b0e7ad | 179 | return insn; |
252b5132 RH |
180 | } |
181 | ||
886a2506 NC |
182 | static int |
183 | extract_r1 (unsigned insn ATTRIBUTE_UNUSED, | |
184 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 185 | { |
886a2506 | 186 | return 1; |
252b5132 RH |
187 | } |
188 | ||
886a2506 NC |
189 | static unsigned |
190 | insert_r2 (unsigned insn, | |
191 | int value, | |
192 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 193 | { |
886a2506 NC |
194 | if (value != 2) |
195 | *errmsg = _("Register must be R2."); | |
47b0e7ad | 196 | return insn; |
252b5132 RH |
197 | } |
198 | ||
886a2506 NC |
199 | static int |
200 | extract_r2 (unsigned insn ATTRIBUTE_UNUSED, | |
201 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 202 | { |
886a2506 | 203 | return 2; |
252b5132 RH |
204 | } |
205 | ||
886a2506 NC |
206 | static unsigned |
207 | insert_r3 (unsigned insn, | |
208 | int value, | |
209 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 210 | { |
886a2506 NC |
211 | if (value != 3) |
212 | *errmsg = _("Register must be R3."); | |
47b0e7ad | 213 | return insn; |
0d2bcfaf NC |
214 | } |
215 | ||
886a2506 NC |
216 | static int |
217 | extract_r3 (unsigned insn ATTRIBUTE_UNUSED, | |
218 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 219 | { |
886a2506 | 220 | return 3; |
0d2bcfaf NC |
221 | } |
222 | ||
886a2506 NC |
223 | static unsigned |
224 | insert_sp (unsigned insn, | |
225 | int value, | |
226 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 227 | { |
886a2506 NC |
228 | if (value != 28) |
229 | *errmsg = _("Register must be SP."); | |
252b5132 RH |
230 | return insn; |
231 | } | |
232 | ||
886a2506 NC |
233 | static int |
234 | extract_sp (unsigned insn ATTRIBUTE_UNUSED, | |
235 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 236 | { |
886a2506 | 237 | return 28; |
0d2bcfaf NC |
238 | } |
239 | ||
886a2506 NC |
240 | static unsigned |
241 | insert_gp (unsigned insn, | |
242 | int value, | |
243 | const char **errmsg ATTRIBUTE_UNUSED) | |
0d2bcfaf | 244 | { |
886a2506 NC |
245 | if (value != 26) |
246 | *errmsg = _("Register must be GP."); | |
247 | return insn; | |
0d2bcfaf NC |
248 | } |
249 | ||
886a2506 NC |
250 | static int |
251 | extract_gp (unsigned insn ATTRIBUTE_UNUSED, | |
252 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 253 | { |
886a2506 | 254 | return 26; |
0d2bcfaf NC |
255 | } |
256 | ||
886a2506 NC |
257 | static unsigned |
258 | insert_pcl (unsigned insn, | |
259 | int value, | |
260 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 261 | { |
886a2506 NC |
262 | if (value != 63) |
263 | *errmsg = _("Register must be PCL."); | |
252b5132 RH |
264 | return insn; |
265 | } | |
266 | ||
886a2506 NC |
267 | static int |
268 | extract_pcl (unsigned insn ATTRIBUTE_UNUSED, | |
269 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 270 | { |
886a2506 | 271 | return 63; |
0d2bcfaf NC |
272 | } |
273 | ||
886a2506 NC |
274 | static unsigned |
275 | insert_blink (unsigned insn, | |
276 | int value, | |
277 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 278 | { |
886a2506 NC |
279 | if (value != 31) |
280 | *errmsg = _("Register must be BLINK."); | |
252b5132 RH |
281 | return insn; |
282 | } | |
283 | ||
886a2506 NC |
284 | static int |
285 | extract_blink (unsigned insn ATTRIBUTE_UNUSED, | |
286 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 287 | { |
886a2506 | 288 | return 31; |
0d2bcfaf NC |
289 | } |
290 | ||
886a2506 NC |
291 | static unsigned |
292 | insert_ilink1 (unsigned insn, | |
293 | int value, | |
294 | const char **errmsg ATTRIBUTE_UNUSED) | |
0d2bcfaf | 295 | { |
886a2506 NC |
296 | if (value != 29) |
297 | *errmsg = _("Register must be ILINK1."); | |
252b5132 RH |
298 | return insn; |
299 | } | |
300 | ||
886a2506 NC |
301 | static int |
302 | extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED, | |
303 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 304 | { |
886a2506 | 305 | return 29; |
252b5132 RH |
306 | } |
307 | ||
886a2506 NC |
308 | static unsigned |
309 | insert_ilink2 (unsigned insn, | |
310 | int value, | |
311 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 312 | { |
886a2506 NC |
313 | if (value != 30) |
314 | *errmsg = _("Register must be ILINK2."); | |
252b5132 RH |
315 | return insn; |
316 | } | |
317 | ||
886a2506 NC |
318 | static int |
319 | extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED, | |
320 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
321 | { | |
322 | return 30; | |
323 | } | |
252b5132 | 324 | |
886a2506 NC |
325 | static unsigned |
326 | insert_ras (unsigned insn, | |
327 | int value, | |
328 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 329 | { |
886a2506 | 330 | switch (value) |
0d2bcfaf | 331 | { |
886a2506 NC |
332 | case 0: |
333 | case 1: | |
334 | case 2: | |
335 | case 3: | |
336 | insn |= value; | |
337 | break; | |
338 | case 12: | |
339 | case 13: | |
340 | case 14: | |
341 | case 15: | |
342 | insn |= (value - 8); | |
343 | break; | |
344 | default: | |
345 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
346 | break; | |
0d2bcfaf | 347 | } |
252b5132 RH |
348 | return insn; |
349 | } | |
252b5132 | 350 | |
886a2506 NC |
351 | static int |
352 | extract_ras (unsigned insn ATTRIBUTE_UNUSED, | |
353 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 354 | { |
886a2506 NC |
355 | int value = insn & 0x07; |
356 | if (value > 3) | |
357 | return (value + 8); | |
358 | else | |
359 | return value; | |
47b0e7ad NC |
360 | } |
361 | ||
886a2506 NC |
362 | static unsigned |
363 | insert_rbs (unsigned insn, | |
364 | int value, | |
365 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 366 | { |
886a2506 | 367 | switch (value) |
47b0e7ad | 368 | { |
886a2506 NC |
369 | case 0: |
370 | case 1: | |
371 | case 2: | |
372 | case 3: | |
373 | insn |= value << 8; | |
374 | break; | |
375 | case 12: | |
376 | case 13: | |
377 | case 14: | |
378 | case 15: | |
379 | insn |= ((value - 8)) << 8; | |
380 | break; | |
381 | default: | |
382 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
383 | break; | |
47b0e7ad | 384 | } |
886a2506 | 385 | return insn; |
252b5132 RH |
386 | } |
387 | ||
886a2506 NC |
388 | static int |
389 | extract_rbs (unsigned insn ATTRIBUTE_UNUSED, | |
390 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 391 | { |
886a2506 NC |
392 | int value = (insn >> 8) & 0x07; |
393 | if (value > 3) | |
394 | return (value + 8); | |
395 | else | |
396 | return value; | |
397 | } | |
252b5132 | 398 | |
886a2506 NC |
399 | static unsigned |
400 | insert_rcs (unsigned insn, | |
401 | int value, | |
402 | const char **errmsg ATTRIBUTE_UNUSED) | |
403 | { | |
404 | switch (value) | |
252b5132 | 405 | { |
886a2506 NC |
406 | case 0: |
407 | case 1: | |
408 | case 2: | |
409 | case 3: | |
410 | insn |= value << 5; | |
411 | break; | |
412 | case 12: | |
413 | case 13: | |
414 | case 14: | |
415 | case 15: | |
416 | insn |= ((value - 8)) << 5; | |
417 | break; | |
418 | default: | |
419 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
420 | break; | |
252b5132 | 421 | } |
886a2506 NC |
422 | return insn; |
423 | } | |
47b0e7ad | 424 | |
886a2506 NC |
425 | static int |
426 | extract_rcs (unsigned insn ATTRIBUTE_UNUSED, | |
427 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
428 | { | |
429 | int value = (insn >> 5) & 0x07; | |
430 | if (value > 3) | |
431 | return (value + 8); | |
252b5132 | 432 | else |
886a2506 NC |
433 | return value; |
434 | } | |
47b0e7ad | 435 | |
886a2506 NC |
436 | static unsigned |
437 | insert_simm3s (unsigned insn, | |
438 | int value, | |
439 | const char **errmsg ATTRIBUTE_UNUSED) | |
440 | { | |
441 | int tmp = 0; | |
442 | switch (value) | |
47b0e7ad | 443 | { |
886a2506 NC |
444 | case -1: |
445 | tmp = 0x07; | |
47b0e7ad | 446 | break; |
886a2506 NC |
447 | case 0: |
448 | tmp = 0x00; | |
449 | break; | |
450 | case 1: | |
451 | tmp = 0x01; | |
47b0e7ad | 452 | break; |
886a2506 NC |
453 | case 2: |
454 | tmp = 0x02; | |
47b0e7ad | 455 | break; |
886a2506 NC |
456 | case 3: |
457 | tmp = 0x03; | |
458 | break; | |
459 | case 4: | |
460 | tmp = 0x04; | |
461 | break; | |
462 | case 5: | |
463 | tmp = 0x05; | |
464 | break; | |
465 | case 6: | |
466 | tmp = 0x06; | |
467 | break; | |
468 | default: | |
469 | *errmsg = _("Accepted values are from -1 to 6."); | |
47b0e7ad NC |
470 | break; |
471 | } | |
472 | ||
886a2506 NC |
473 | insn |= tmp << 8; |
474 | return insn; | |
47b0e7ad NC |
475 | } |
476 | ||
886a2506 NC |
477 | static int |
478 | extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, | |
479 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 480 | { |
886a2506 NC |
481 | int value = (insn >> 8) & 0x07; |
482 | if (value == 7) | |
483 | return -1; | |
47b0e7ad | 484 | else |
886a2506 | 485 | return value; |
47b0e7ad NC |
486 | } |
487 | ||
886a2506 NC |
488 | static unsigned |
489 | insert_rrange (unsigned insn, | |
490 | int value, | |
491 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 492 | { |
886a2506 NC |
493 | int reg1 = (value >> 16) & 0xFFFF; |
494 | int reg2 = value & 0xFFFF; | |
495 | if (reg1 != 13) | |
496 | { | |
497 | *errmsg = _("First register of the range should be r13."); | |
498 | return insn; | |
499 | } | |
500 | if (reg2 < 13 || reg2 > 26) | |
501 | { | |
502 | *errmsg = _("Last register of the range doesn't fit."); | |
503 | return insn; | |
504 | } | |
505 | insn |= ((reg2 - 12) & 0x0F) << 1; | |
506 | return insn; | |
47b0e7ad NC |
507 | } |
508 | ||
886a2506 NC |
509 | static int |
510 | extract_rrange (unsigned insn ATTRIBUTE_UNUSED, | |
511 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
512 | { | |
513 | return (insn >> 1) & 0x0F; | |
514 | } | |
47b0e7ad | 515 | |
886a2506 NC |
516 | static unsigned |
517 | insert_fpel (unsigned insn, | |
518 | int value, | |
519 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 520 | { |
886a2506 NC |
521 | if (value != 27) |
522 | { | |
523 | *errmsg = _("Invalid register number, should be fp."); | |
524 | return insn; | |
525 | } | |
47b0e7ad | 526 | |
886a2506 NC |
527 | insn |= 0x0100; |
528 | return insn; | |
47b0e7ad NC |
529 | } |
530 | ||
886a2506 NC |
531 | static int |
532 | extract_fpel (unsigned insn ATTRIBUTE_UNUSED, | |
533 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 534 | { |
886a2506 | 535 | return (insn & 0x0100) ? 27 : -1; |
47b0e7ad NC |
536 | } |
537 | ||
886a2506 NC |
538 | static unsigned |
539 | insert_blinkel (unsigned insn, | |
540 | int value, | |
541 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 542 | { |
886a2506 | 543 | if (value != 31) |
47b0e7ad | 544 | { |
886a2506 NC |
545 | *errmsg = _("Invalid register number, should be blink."); |
546 | return insn; | |
47b0e7ad | 547 | } |
47b0e7ad | 548 | |
886a2506 NC |
549 | insn |= 0x0200; |
550 | return insn; | |
47b0e7ad NC |
551 | } |
552 | ||
886a2506 NC |
553 | static int |
554 | extract_blinkel (unsigned insn ATTRIBUTE_UNUSED, | |
555 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 556 | { |
886a2506 NC |
557 | return (insn & 0x0200) ? 31 : -1; |
558 | } | |
47b0e7ad | 559 | |
886a2506 NC |
560 | static unsigned |
561 | insert_pclel (unsigned insn, | |
562 | int value, | |
563 | const char **errmsg ATTRIBUTE_UNUSED) | |
564 | { | |
565 | if (value != 63) | |
47b0e7ad | 566 | { |
886a2506 NC |
567 | *errmsg = _("Invalid register number, should be pcl."); |
568 | return insn; | |
47b0e7ad | 569 | } |
47b0e7ad | 570 | |
886a2506 NC |
571 | insn |= 0x0400; |
572 | return insn; | |
573 | } | |
47b0e7ad | 574 | |
886a2506 NC |
575 | static int |
576 | extract_pclel (unsigned insn ATTRIBUTE_UNUSED, | |
577 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 578 | { |
886a2506 | 579 | return (insn & 0x0400) ? 63 : -1; |
47b0e7ad | 580 | } |
47b0e7ad | 581 | |
886a2506 NC |
582 | #define INSERT_W6 |
583 | /* mask = 00000000000000000000111111000000 | |
584 | insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ | |
585 | static unsigned | |
586 | insert_w6 (unsigned insn ATTRIBUTE_UNUSED, | |
587 | int value ATTRIBUTE_UNUSED, | |
588 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 589 | { |
886a2506 | 590 | insn |= ((value >> 0) & 0x003f) << 6; |
47b0e7ad | 591 | |
886a2506 NC |
592 | return insn; |
593 | } | |
47b0e7ad | 594 | |
886a2506 NC |
595 | #define EXTRACT_W6 |
596 | /* mask = 00000000000000000000111111000000. */ | |
597 | static int | |
598 | extract_w6 (unsigned insn ATTRIBUTE_UNUSED, | |
599 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 600 | { |
886a2506 | 601 | unsigned value = 0; |
47b0e7ad | 602 | |
886a2506 | 603 | value |= ((insn >> 6) & 0x003f) << 0; |
47b0e7ad | 604 | |
886a2506 NC |
605 | return value; |
606 | } | |
47b0e7ad | 607 | |
886a2506 NC |
608 | #define INSERT_G_S |
609 | /* mask = 0000011100022000 | |
610 | insn = 01000ggghhhGG0HH. */ | |
611 | static unsigned | |
612 | insert_g_s (unsigned insn ATTRIBUTE_UNUSED, | |
613 | int value ATTRIBUTE_UNUSED, | |
614 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 615 | { |
886a2506 NC |
616 | insn |= ((value >> 0) & 0x0007) << 8; |
617 | insn |= ((value >> 3) & 0x0003) << 3; | |
252b5132 | 618 | |
886a2506 NC |
619 | return insn; |
620 | } | |
252b5132 | 621 | |
886a2506 NC |
622 | #define EXTRACT_G_S |
623 | /* mask = 0000011100022000. */ | |
624 | static int | |
625 | extract_g_s (unsigned insn ATTRIBUTE_UNUSED, | |
626 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
627 | { | |
628 | int value = 0; | |
252b5132 | 629 | |
886a2506 NC |
630 | value |= ((insn >> 8) & 0x0007) << 0; |
631 | value |= ((insn >> 3) & 0x0003) << 3; | |
252b5132 | 632 | |
886a2506 NC |
633 | /* Extend the sign. */ |
634 | int signbit = 1 << (6 - 1); | |
635 | value = (value ^ signbit) - signbit; | |
252b5132 | 636 | |
886a2506 | 637 | return value; |
252b5132 RH |
638 | } |
639 | ||
886a2506 NC |
640 | /* Include the generic extract/insert functions. Order is important |
641 | as some of the functions present in the .h may be disabled via | |
642 | defines. */ | |
643 | #include "arc-fxi.h" | |
252b5132 | 644 | |
886a2506 NC |
645 | /* Abbreviations for instruction subsets. */ |
646 | #define BASE ARC_OPCODE_BASE | |
47b0e7ad | 647 | |
886a2506 | 648 | /* The flag operands table. |
252b5132 | 649 | |
886a2506 NC |
650 | The format of the table is |
651 | NAME CODE BITS SHIFT FAVAIL. */ | |
652 | const struct arc_flag_operand arc_flag_operands[] = | |
653 | { | |
654 | #define F_NULL 0 | |
655 | { 0, 0, 0, 0, 0}, | |
656 | #define F_ALWAYS (F_NULL + 1) | |
657 | { "al", 0, 0, 0, 0 }, | |
658 | #define F_RA (F_ALWAYS + 1) | |
659 | { "ra", 0, 0, 0, 0 }, | |
660 | #define F_EQUAL (F_RA + 1) | |
661 | { "eq", 1, 5, 0, 1 }, | |
662 | #define F_ZERO (F_EQUAL + 1) | |
663 | { "z", 1, 5, 0, 0 }, | |
664 | #define F_NOTEQUAL (F_ZERO + 1) | |
665 | { "ne", 2, 5, 0, 1 }, | |
666 | #define F_NOTZERO (F_NOTEQUAL + 1) | |
667 | { "nz", 2, 5, 0, 0 }, | |
668 | #define F_POZITIVE (F_NOTZERO + 1) | |
669 | { "p", 3, 5, 0, 1 }, | |
670 | #define F_PL (F_POZITIVE + 1) | |
671 | { "pl", 3, 5, 0, 0 }, | |
672 | #define F_NEGATIVE (F_PL + 1) | |
673 | { "n", 4, 5, 0, 1 }, | |
674 | #define F_MINUS (F_NEGATIVE + 1) | |
675 | { "mi", 4, 5, 0, 0 }, | |
676 | #define F_CARRY (F_MINUS + 1) | |
677 | { "c", 5, 5, 0, 1 }, | |
678 | #define F_CARRYSET (F_CARRY + 1) | |
679 | { "cs", 5, 5, 0, 0 }, | |
680 | #define F_LOWER (F_CARRYSET + 1) | |
681 | { "lo", 5, 5, 0, 0 }, | |
682 | #define F_CARRYCLR (F_LOWER + 1) | |
683 | { "cc", 6, 5, 0, 0 }, | |
684 | #define F_NOTCARRY (F_CARRYCLR + 1) | |
685 | { "nc", 6, 5, 0, 1 }, | |
686 | #define F_HIGHER (F_NOTCARRY + 1) | |
687 | { "hs", 6, 5, 0, 0 }, | |
688 | #define F_OVERFLOWSET (F_HIGHER + 1) | |
689 | { "vs", 7, 5, 0, 0 }, | |
690 | #define F_OVERFLOW (F_OVERFLOWSET + 1) | |
691 | { "v", 7, 5, 0, 1 }, | |
692 | #define F_NOTOVERFLOW (F_OVERFLOW + 1) | |
693 | { "nv", 8, 5, 0, 1 }, | |
694 | #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) | |
695 | { "vc", 8, 5, 0, 0 }, | |
696 | #define F_GT (F_OVERFLOWCLR + 1) | |
697 | { "gt", 9, 5, 0, 1 }, | |
698 | #define F_GE (F_GT + 1) | |
699 | { "ge", 10, 5, 0, 1 }, | |
700 | #define F_LT (F_GE + 1) | |
701 | { "lt", 11, 5, 0, 1 }, | |
702 | #define F_LE (F_LT + 1) | |
703 | { "le", 12, 5, 0, 1 }, | |
704 | #define F_HI (F_LE + 1) | |
705 | { "hi", 13, 5, 0, 1 }, | |
706 | #define F_LS (F_HI + 1) | |
707 | { "ls", 14, 5, 0, 1 }, | |
708 | #define F_PNZ (F_LS + 1) | |
709 | { "pnz", 15, 5, 0, 1 }, | |
710 | ||
711 | /* FLAG. */ | |
712 | #define F_FLAG (F_PNZ + 1) | |
713 | { "f", 1, 1, 15, 1 }, | |
714 | #define F_FFAKE (F_FLAG + 1) | |
715 | { "f", 0, 0, 0, 1 }, | |
716 | ||
717 | /* Delay slot. */ | |
718 | #define F_ND (F_FFAKE + 1) | |
719 | { "nd", 0, 1, 5, 0 }, | |
720 | #define F_D (F_ND + 1) | |
721 | { "d", 1, 1, 5, 1 }, | |
722 | #define F_DFAKE (F_D + 1) | |
723 | { "d", 0, 0, 0, 1 }, | |
724 | ||
725 | /* Data size. */ | |
726 | #define F_SIZEB1 (F_DFAKE + 1) | |
727 | { "b", 1, 2, 1, 1 }, | |
728 | #define F_SIZEB7 (F_SIZEB1 + 1) | |
729 | { "b", 1, 2, 7, 1 }, | |
730 | #define F_SIZEB17 (F_SIZEB7 + 1) | |
731 | { "b", 1, 2, 17, 1 }, | |
732 | #define F_SIZEW1 (F_SIZEB17 + 1) | |
733 | { "w", 2, 2, 1, 0 }, | |
734 | #define F_SIZEW7 (F_SIZEW1 + 1) | |
735 | { "w", 2, 2, 7, 0 }, | |
736 | #define F_SIZEW17 (F_SIZEW7 + 1) | |
737 | { "w", 2, 2, 17, 0 }, | |
738 | ||
739 | /* Sign extension. */ | |
740 | #define F_SIGN6 (F_SIZEW17 + 1) | |
741 | { "x", 1, 1, 6, 1 }, | |
742 | #define F_SIGN16 (F_SIGN6 + 1) | |
743 | { "x", 1, 1, 16, 1 }, | |
744 | #define F_SIGNX (F_SIGN16 + 1) | |
745 | { "x", 0, 0, 0, 1 }, | |
746 | ||
747 | /* Address write-back modes. */ | |
748 | #define F_A3 (F_SIGNX + 1) | |
749 | { "a", 1, 2, 3, 0 }, | |
750 | #define F_A9 (F_A3 + 1) | |
751 | { "a", 1, 2, 9, 0 }, | |
752 | #define F_A22 (F_A9 + 1) | |
753 | { "a", 1, 2, 22, 0 }, | |
754 | #define F_AW3 (F_A22 + 1) | |
755 | { "aw", 1, 2, 3, 1 }, | |
756 | #define F_AW9 (F_AW3 + 1) | |
757 | { "aw", 1, 2, 9, 1 }, | |
758 | #define F_AW22 (F_AW9 + 1) | |
759 | { "aw", 1, 2, 22, 1 }, | |
760 | #define F_AB3 (F_AW22 + 1) | |
761 | { "ab", 2, 2, 3, 1 }, | |
762 | #define F_AB9 (F_AB3 + 1) | |
763 | { "ab", 2, 2, 9, 1 }, | |
764 | #define F_AB22 (F_AB9 + 1) | |
765 | { "ab", 2, 2, 22, 1 }, | |
766 | #define F_AS3 (F_AB22 + 1) | |
767 | { "as", 3, 2, 3, 1 }, | |
768 | #define F_AS9 (F_AS3 + 1) | |
769 | { "as", 3, 2, 9, 1 }, | |
770 | #define F_AS22 (F_AS9 + 1) | |
771 | { "as", 3, 2, 22, 1 }, | |
772 | #define F_ASFAKE (F_AS22 + 1) | |
773 | { "as", 0, 0, 0, 1 }, | |
774 | ||
775 | /* Cache bypass. */ | |
776 | #define F_DI5 (F_ASFAKE + 1) | |
777 | { "di", 1, 1, 5, 1 }, | |
778 | #define F_DI11 (F_DI5 + 1) | |
779 | { "di", 1, 1, 11, 1 }, | |
780 | #define F_DI15 (F_DI11 + 1) | |
781 | { "di", 1, 1, 15, 1 }, | |
782 | ||
783 | /* ARCv2 specific. */ | |
784 | #define F_NT (F_DI15 + 1) | |
785 | { "nt", 0, 1, 3, 1}, | |
786 | #define F_T (F_NT + 1) | |
787 | { "t", 1, 1, 3, 1}, | |
788 | #define F_H1 (F_T + 1) | |
789 | { "h", 2, 2, 1, 1 }, | |
790 | #define F_H7 (F_H1 + 1) | |
791 | { "h", 2, 2, 7, 1 }, | |
792 | #define F_H17 (F_H7 + 1) | |
793 | { "h", 2, 2, 17, 1 }, | |
794 | ||
795 | /* Fake Flags. */ | |
796 | #define F_NE (F_H17 + 1) | |
797 | { "ne", 0, 0, 0, 1 }, | |
798 | }; | |
252b5132 | 799 | |
886a2506 | 800 | const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); |
252b5132 | 801 | |
886a2506 | 802 | /* Table of the flag classes. |
252b5132 | 803 | |
886a2506 NC |
804 | The format of the table is |
805 | CLASS {FLAG_CODE}. */ | |
806 | const struct arc_flag_class arc_flag_classes[] = | |
807 | { | |
808 | #define C_EMPTY 0 | |
809 | { FNONE, { F_NULL } }, | |
810 | ||
811 | #define C_CC (C_EMPTY + 1) | |
812 | { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, | |
813 | F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, | |
814 | F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, | |
815 | F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, | |
816 | F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
817 | ||
818 | #define C_AA_ADDR3 (C_CC + 1) | |
819 | #define C_AA27 (C_CC + 1) | |
820 | { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, | |
821 | #define C_AA_ADDR9 (C_AA_ADDR3 + 1) | |
822 | #define C_AA21 (C_AA_ADDR3 + 1) | |
823 | { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, | |
824 | #define C_AA_ADDR22 (C_AA_ADDR9 + 1) | |
825 | #define C_AA8 (C_AA_ADDR9 + 1) | |
826 | { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, | |
827 | ||
828 | #define C_F (C_AA_ADDR22 + 1) | |
829 | { FLG, { F_FLAG, F_NULL } }, | |
830 | #define C_FHARD (C_F + 1) | |
831 | { FLG, { F_FFAKE, F_NULL } }, | |
832 | ||
833 | #define C_T (C_FHARD + 1) | |
834 | { SBP, { F_NT, F_T, F_NULL } }, | |
835 | #define C_D (C_T + 1) | |
836 | { DLY, { F_ND, F_D, F_NULL } }, | |
837 | ||
838 | #define C_DHARD (C_D + 1) | |
839 | { DLY, { F_DFAKE, F_NULL } }, | |
840 | ||
841 | #define C_DI20 (C_DHARD + 1) | |
842 | { DIF, { F_DI11, F_NULL }}, | |
843 | #define C_DI16 (C_DI20 + 1) | |
844 | { DIF, { F_DI15, F_NULL }}, | |
845 | #define C_DI26 (C_DI16 + 1) | |
846 | { DIF, { F_DI5, F_NULL }}, | |
847 | ||
848 | #define C_X25 (C_DI26 + 1) | |
849 | { SGX, { F_SIGN6, F_NULL }}, | |
850 | #define C_X15 (C_X25 + 1) | |
851 | { SGX, { F_SIGN16, F_NULL }}, | |
852 | #define C_XHARD (C_X15 + 1) | |
853 | #define C_X (C_X15 + 1) | |
854 | { SGX, { F_SIGNX, F_NULL }}, | |
855 | ||
856 | #define C_ZZ13 (C_X + 1) | |
857 | { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, | |
858 | #define C_ZZ23 (C_ZZ13 + 1) | |
859 | { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, | |
860 | #define C_ZZ29 (C_ZZ23 + 1) | |
861 | { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, | |
862 | ||
863 | #define C_AS (C_ZZ29 + 1) | |
864 | { SZM, { F_ASFAKE, F_NULL}}, | |
865 | ||
866 | #define C_NE (C_AS + 1) | |
867 | { CND, { F_NE, F_NULL}}, | |
868 | }; | |
252b5132 | 869 | |
886a2506 | 870 | /* The operands table. |
252b5132 | 871 | |
886a2506 | 872 | The format of the operands table is: |
47b0e7ad | 873 | |
886a2506 NC |
874 | BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ |
875 | const struct arc_operand arc_operands[] = | |
0d2bcfaf | 876 | { |
886a2506 NC |
877 | /* The fields are bits, shift, insert, extract, flags. The zero |
878 | index is used to indicate end-of-list. */ | |
879 | #define UNUSED 0 | |
880 | { 0, 0, 0, 0, 0, 0 }, | |
881 | /* The plain integer register fields. Used by 32 bit | |
882 | instructions. */ | |
883 | #define RA (UNUSED + 1) | |
884 | { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, | |
885 | #define RB (RA + 1) | |
886 | { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, | |
887 | #define RC (RB + 1) | |
888 | { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, | |
889 | #define RBdup (RC + 1) | |
890 | { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, | |
891 | ||
892 | #define RAD (RBdup + 1) | |
893 | { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, | |
894 | #define RCD (RAD + 1) | |
895 | { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, | |
896 | ||
897 | /* The plain integer register fields. Used by short | |
898 | instructions. */ | |
899 | #define RA16 (RCD + 1) | |
900 | #define RA_S (RCD + 1) | |
901 | { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, | |
902 | #define RB16 (RA16 + 1) | |
903 | #define RB_S (RA16 + 1) | |
904 | { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, | |
905 | #define RB16dup (RB16 + 1) | |
906 | #define RB_Sdup (RB16 + 1) | |
907 | { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, | |
908 | #define RC16 (RB16dup + 1) | |
909 | #define RC_S (RB16dup + 1) | |
910 | { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, | |
911 | #define R6H (RC16 + 1) /* 6bit register field 'h' used | |
912 | by V1 cpus. */ | |
913 | { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, | |
914 | #define R5H (R6H + 1) /* 5bit register field 'h' used | |
915 | by V2 cpus. */ | |
916 | #define RH_S (R6H + 1) /* 5bit register field 'h' used | |
917 | by V2 cpus. */ | |
918 | { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, | |
919 | #define R5Hdup (R5H + 1) | |
920 | #define RH_Sdup (R5H + 1) | |
921 | { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, | |
922 | insert_rhv2, extract_rhv2 }, | |
923 | ||
924 | #define RG (R5Hdup + 1) | |
925 | #define G_S (R5Hdup + 1) | |
926 | { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, | |
927 | ||
928 | /* Fix registers. */ | |
929 | #define R0 (RG + 1) | |
930 | #define R0_S (RG + 1) | |
931 | { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, | |
932 | #define R1 (R0 + 1) | |
933 | #define R1_S (R0 + 1) | |
934 | { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, | |
935 | #define R2 (R1 + 1) | |
936 | #define R2_S (R1 + 1) | |
937 | { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, | |
938 | #define R3 (R2 + 1) | |
939 | #define R3_S (R2 + 1) | |
940 | { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, | |
941 | #define SP (R3 + 1) | |
942 | #define SP_S (R3 + 1) | |
943 | { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, | |
944 | #define SPdup (SP + 1) | |
945 | #define SP_Sdup (SP + 1) | |
946 | { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, | |
947 | #define GP (SPdup + 1) | |
948 | #define GP_S (SPdup + 1) | |
949 | { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, | |
950 | ||
951 | #define PCL_S (GP + 1) | |
952 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, | |
953 | ||
954 | #define BLINK (PCL_S + 1) | |
955 | #define BLINK_S (PCL_S + 1) | |
956 | { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, | |
957 | ||
958 | #define ILINK1 (BLINK + 1) | |
959 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, | |
960 | #define ILINK2 (ILINK1 + 1) | |
961 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, | |
962 | ||
963 | /* Long immediate. */ | |
964 | #define LIMM (ILINK2 + 1) | |
965 | #define LIMM_S (ILINK2 + 1) | |
966 | { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, | |
967 | #define LIMMdup (LIMM + 1) | |
968 | { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, | |
969 | ||
970 | /* Special operands. */ | |
971 | #define ZA (LIMMdup + 1) | |
972 | #define ZB (LIMMdup + 1) | |
973 | #define ZA_S (LIMMdup + 1) | |
974 | #define ZB_S (LIMMdup + 1) | |
975 | #define ZC_S (LIMMdup + 1) | |
976 | { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, | |
977 | ||
978 | #define RRANGE_EL (ZA + 1) | |
979 | { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, | |
980 | insert_rrange, extract_rrange}, | |
981 | #define FP_EL (RRANGE_EL + 1) | |
982 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
983 | insert_fpel, extract_fpel }, | |
984 | #define BLINK_EL (FP_EL + 1) | |
985 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
986 | insert_blinkel, extract_blinkel }, | |
987 | #define PCL_EL (BLINK_EL + 1) | |
988 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
989 | insert_pclel, extract_pclel }, | |
990 | ||
991 | /* Fake operand to handle the T flag. */ | |
992 | #define BRAKET (PCL_EL + 1) | |
993 | #define BRAKETdup (PCL_EL + 1) | |
994 | { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, | |
995 | ||
996 | /* Fake operand to handle the T flag. */ | |
997 | #define FKT_T (BRAKET + 1) | |
998 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, | |
999 | /* Fake operand to handle the T flag. */ | |
1000 | #define FKT_NT (FKT_T + 1) | |
1001 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, | |
1002 | ||
1003 | /* UIMM6_20 mask = 00000000000000000000111111000000. */ | |
1004 | #define UIMM6_20 (FKT_NT + 1) | |
1005 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, | |
1006 | ||
1007 | /* SIMM12_20 mask = 00000000000000000000111111222222. */ | |
1008 | #define SIMM12_20 (UIMM6_20 + 1) | |
1009 | {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, | |
1010 | ||
1011 | /* SIMM3_5_S mask = 0000011100000000. */ | |
1012 | #define SIMM3_5_S (SIMM12_20 + 1) | |
1013 | {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, | |
1014 | insert_simm3s, extract_simm3s}, | |
1015 | ||
1016 | /* UIMM7_A32_11_S mask = 0000000000011111. */ | |
1017 | #define UIMM7_A32_11_S (SIMM3_5_S + 1) | |
1018 | {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1019 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, | |
1020 | extract_uimm7_a32_11_s}, | |
1021 | ||
1022 | /* UIMM7_9_S mask = 0000000001111111. */ | |
1023 | #define UIMM7_9_S (UIMM7_A32_11_S + 1) | |
1024 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, | |
1025 | ||
1026 | /* UIMM3_13_S mask = 0000000000000111. */ | |
1027 | #define UIMM3_13_S (UIMM7_9_S + 1) | |
1028 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, | |
1029 | ||
1030 | /* SIMM11_A32_7_S mask = 0000000111111111. */ | |
1031 | #define SIMM11_A32_7_S (UIMM3_13_S + 1) | |
1032 | {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1033 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, | |
1034 | ||
1035 | /* UIMM6_13_S mask = 0000000002220111. */ | |
1036 | #define UIMM6_13_S (SIMM11_A32_7_S + 1) | |
1037 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, | |
1038 | /* UIMM5_11_S mask = 0000000000011111. */ | |
1039 | #define UIMM5_11_S (UIMM6_13_S + 1) | |
1040 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, | |
1041 | extract_uimm5_11_s}, | |
1042 | ||
1043 | /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ | |
1044 | #define SIMM9_A16_8 (UIMM5_11_S + 1) | |
1045 | {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1046 | | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, | |
1047 | extract_simm9_a16_8}, | |
1048 | ||
1049 | /* UIMM6_8 mask = 00000000000000000000111111000000. */ | |
1050 | #define UIMM6_8 (SIMM9_A16_8 + 1) | |
1051 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, | |
1052 | ||
1053 | /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ | |
1054 | #define SIMM21_A16_5 (UIMM6_8 + 1) | |
1055 | {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | |
1056 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, | |
1057 | insert_simm21_a16_5, extract_simm21_a16_5}, | |
1058 | ||
1059 | /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ | |
1060 | #define SIMM25_A16_5 (SIMM21_A16_5 + 1) | |
1061 | {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | |
1062 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, | |
1063 | insert_simm25_a16_5, extract_simm25_a16_5}, | |
1064 | ||
1065 | /* SIMM10_A16_7_S mask = 0000000111111111. */ | |
1066 | #define SIMM10_A16_7_S (SIMM25_A16_5 + 1) | |
1067 | {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1068 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, | |
1069 | extract_simm10_a16_7_s}, | |
1070 | ||
1071 | #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) | |
1072 | {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1073 | | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, | |
1074 | ||
1075 | /* SIMM7_A16_10_S mask = 0000000000111111. */ | |
1076 | #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) | |
1077 | {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1078 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, | |
1079 | extract_simm7_a16_10_s}, | |
1080 | ||
1081 | /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ | |
1082 | #define SIMM21_A32_5 (SIMM7_A16_10_S + 1) | |
1083 | {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1084 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, | |
1085 | extract_simm21_a32_5}, | |
1086 | ||
1087 | /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ | |
1088 | #define SIMM25_A32_5 (SIMM21_A32_5 + 1) | |
1089 | {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1090 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, | |
1091 | extract_simm25_a32_5}, | |
1092 | ||
1093 | /* SIMM13_A32_5_S mask = 0000011111111111. */ | |
1094 | #define SIMM13_A32_5_S (SIMM25_A32_5 + 1) | |
1095 | {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1096 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, | |
1097 | extract_simm13_a32_5_s}, | |
1098 | ||
1099 | /* SIMM8_A16_9_S mask = 0000000001111111. */ | |
1100 | #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) | |
1101 | {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1102 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, | |
1103 | extract_simm8_a16_9_s}, | |
1104 | ||
1105 | /* UIMM3_23 mask = 00000000000000000000000111000000. */ | |
1106 | #define UIMM3_23 (SIMM8_A16_9_S + 1) | |
1107 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, | |
1108 | ||
1109 | /* UIMM10_6_S mask = 0000001111111111. */ | |
1110 | #define UIMM10_6_S (UIMM3_23 + 1) | |
1111 | {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, | |
1112 | ||
1113 | /* UIMM6_11_S mask = 0000002200011110. */ | |
1114 | #define UIMM6_11_S (UIMM10_6_S + 1) | |
1115 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, | |
1116 | ||
1117 | /* SIMM9_8 mask = 00000000111111112000000000000000. */ | |
1118 | #define SIMM9_8 (UIMM6_11_S + 1) | |
1119 | {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, | |
1120 | insert_simm9_8, extract_simm9_8}, | |
1121 | ||
1122 | /* UIMM10_A32_8_S mask = 0000000011111111. */ | |
1123 | #define UIMM10_A32_8_S (SIMM9_8 + 1) | |
1124 | {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1125 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, | |
1126 | extract_uimm10_a32_8_s}, | |
1127 | ||
1128 | /* SIMM9_7_S mask = 0000000111111111. */ | |
1129 | #define SIMM9_7_S (UIMM10_A32_8_S + 1) | |
1130 | {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, | |
1131 | extract_simm9_7_s}, | |
1132 | ||
1133 | /* UIMM6_A16_11_S mask = 0000000000011111. */ | |
1134 | #define UIMM6_A16_11_S (SIMM9_7_S + 1) | |
1135 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1136 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, | |
1137 | extract_uimm6_a16_11_s}, | |
1138 | ||
1139 | /* UIMM5_A32_11_S mask = 0000020000011000. */ | |
1140 | #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) | |
1141 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1142 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, | |
1143 | extract_uimm5_a32_11_s}, | |
1144 | ||
1145 | /* SIMM11_A32_13_S mask = 0000022222200111. */ | |
1146 | #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) | |
1147 | {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1148 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, | |
1149 | ||
1150 | /* UIMM7_13_S mask = 0000000022220111. */ | |
1151 | #define UIMM7_13_S (SIMM11_A32_13_S + 1) | |
1152 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, | |
1153 | ||
1154 | /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ | |
1155 | #define UIMM6_A16_21 (UIMM7_13_S + 1) | |
1156 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1157 | | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, | |
1158 | ||
1159 | /* UIMM7_11_S mask = 0000022200011110. */ | |
1160 | #define UIMM7_11_S (UIMM6_A16_21 + 1) | |
1161 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, | |
1162 | ||
1163 | /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ | |
1164 | #define UIMM7_A16_20 (UIMM7_11_S + 1) | |
1165 | {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1166 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, | |
1167 | extract_uimm7_a16_20}, | |
1168 | ||
1169 | /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ | |
1170 | #define SIMM13_A16_20 (UIMM7_A16_20 + 1) | |
1171 | {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1172 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, | |
1173 | extract_simm13_a16_20}, | |
1174 | ||
1175 | /* UIMM8_8_S mask = 0000000011111111. */ | |
1176 | #define UIMM8_8_S (SIMM13_A16_20 + 1) | |
1177 | {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, | |
1178 | ||
1179 | /* W6 mask = 00000000000000000000111111000000. */ | |
1180 | #define W6 (UIMM8_8_S + 1) | |
1181 | {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, | |
1182 | ||
1183 | /* UIMM6_5_S mask = 0000011111100000. */ | |
1184 | #define UIMM6_5_S (W6 + 1) | |
1185 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, | |
1186 | }; | |
0d2bcfaf | 1187 | |
886a2506 | 1188 | const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); |
0d2bcfaf | 1189 | |
886a2506 NC |
1190 | const unsigned arc_Toperand = FKT_T; |
1191 | const unsigned arc_NToperand = FKT_NT; | |
47b0e7ad | 1192 | |
886a2506 | 1193 | /* The opcode table. |
0d2bcfaf | 1194 | |
886a2506 | 1195 | The format of the opcode table is: |
0d2bcfaf | 1196 | |
886a2506 NC |
1197 | NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */ |
1198 | const struct arc_opcode arc_opcodes[] = | |
0d2bcfaf | 1199 | { |
886a2506 NC |
1200 | #include "arc-tbl.h" |
1201 | }; | |
0d2bcfaf | 1202 | |
886a2506 | 1203 | const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes); |
252b5132 | 1204 | |
886a2506 NC |
1205 | /* List with special cases instructions and the applicable flags. */ |
1206 | const struct arc_flag_special arc_flag_special_cases[] = | |
252b5132 | 1207 | { |
886a2506 NC |
1208 | { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, |
1209 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1210 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1211 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1212 | { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1213 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1214 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1215 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1216 | { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1217 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1218 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1219 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1220 | { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1221 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1222 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1223 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1224 | { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1225 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1226 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1227 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1228 | { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1229 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1230 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1231 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1232 | { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
1233 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1234 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
1235 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
1236 | { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, | |
1237 | { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } | |
1238 | }; | |
252b5132 | 1239 | |
886a2506 | 1240 | const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); |
252b5132 | 1241 | |
886a2506 | 1242 | /* Relocations. */ |
886a2506 NC |
1243 | const struct arc_reloc_equiv_tab arc_reloc_equiv[] = |
1244 | { | |
24b368f8 CZ |
1245 | { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, |
1246 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
1247 | { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, | |
1248 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
1249 | { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
1250 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
1251 | { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
1252 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
1253 | ||
1254 | /* Next two entries will cover the undefined behavior ldb/stb with | |
1255 | address scaling. */ | |
1256 | { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
1257 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
1258 | { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
1259 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, | |
1260 | ||
1261 | { "sda", "ld", { F_ASFAKE, F_NULL }, | |
1262 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
1263 | { "sda", "st", { F_ASFAKE, F_NULL }, | |
1264 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
1265 | { "sda", "ldd", { F_ASFAKE, F_NULL }, | |
1266 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
1267 | { "sda", "std", { F_ASFAKE, F_NULL }, | |
1268 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
886a2506 NC |
1269 | |
1270 | /* Short instructions. */ | |
24b368f8 CZ |
1271 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, |
1272 | { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, | |
1273 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, | |
1274 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, | |
1275 | ||
1276 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, | |
1277 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
1278 | ||
1279 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, | |
1280 | BFD_RELOC_ARC_S25H_PCREL_PLT }, | |
1281 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, | |
1282 | BFD_RELOC_ARC_S21H_PCREL_PLT }, | |
1283 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, | |
1284 | BFD_RELOC_ARC_S25W_PCREL_PLT }, | |
1285 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, | |
1286 | BFD_RELOC_ARC_S21W_PCREL_PLT }, | |
1287 | ||
1288 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } | |
886a2506 | 1289 | }; |
252b5132 | 1290 | |
886a2506 | 1291 | const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); |
252b5132 | 1292 | |
886a2506 | 1293 | const struct arc_pseudo_insn arc_pseudo_insns[] = |
0d2bcfaf | 1294 | { |
886a2506 NC |
1295 | { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, |
1296 | { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, | |
1297 | { BRAKETdup, 1, 0, 4} } }, | |
1298 | { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, | |
1299 | { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, | |
1300 | { BRAKETdup, 1, 0, 4} } }, | |
1301 | ||
1302 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1303 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1304 | { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1305 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1306 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
1307 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1308 | { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1309 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1310 | { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1311 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1312 | ||
1313 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1314 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1315 | { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1316 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1317 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
1318 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1319 | { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1320 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1321 | { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1322 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1323 | ||
1324 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1325 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1326 | { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1327 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1328 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
1329 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1330 | { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1331 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1332 | { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1333 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1334 | ||
1335 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1336 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1337 | { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1338 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1339 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
1340 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1341 | { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
1342 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1343 | { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
1344 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
1345 | }; | |
0d2bcfaf | 1346 | |
886a2506 NC |
1347 | const unsigned arc_num_pseudo_insn = |
1348 | sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); | |
0d2bcfaf | 1349 | |
886a2506 | 1350 | const struct arc_aux_reg arc_aux_regs[] = |
0d2bcfaf | 1351 | { |
886a2506 NC |
1352 | #undef DEF |
1353 | #define DEF(ADDR, NAME) \ | |
1354 | { ADDR, #NAME, sizeof (#NAME)-1 }, | |
0d2bcfaf | 1355 | |
886a2506 | 1356 | #include "arc-regs.h" |
0d2bcfaf | 1357 | |
886a2506 NC |
1358 | #undef DEF |
1359 | }; | |
0d2bcfaf | 1360 | |
886a2506 | 1361 | const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); |