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[ARC] Allow non-instruction relocations within .text sections
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
e49d43ff 37#include "mach-o.h"
252b5132 38
6b5d3a4d 39/* FIXME: Belongs in global header. */
01c7f630 40#ifndef strneq
58efb6c0
NC		 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42#endif
43
44#ifndef NUM_ELEM
45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 46#endif
47
1fbaefec
PB		 48/* Cached mapping symbol state. */
49enum map_type
50{
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54};
55
b0e28b39
DJ		 56struct arm_private_data
57{
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
1fbaefec
PB		 64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
b0e28b39
DJ		 71};
72
6b5d3a4d
ZW		 73struct opcode32
74{
823d2571
TG		 75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 78 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 79};
80
81struct opcode16
82{
823d2571 83 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 85 const char *assembler; /* How to disassemble this insn. */
86};
b7693d02 87
8f06b2d8 88/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 89
2fbad815 90 %% %
4a5329c6 91
c22aaad1 92 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 93 %q print shifter argument
e2efe87d
MGD		 94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
4a5329c6 96 %A print address for ldc/stc/ldf/stf instruction
16980d0b 97 %B print vstm/vldm register list
4a5329c6 98 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
33399f07 104 %<bitfield>c print as a condition code (for vsel)
4a5329c6 105 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 108 %<bitfield>d print the bitfield in decimal
16980d0b 109 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
4a5329c6
ZW		 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
6f1c2142 119 %<bitfield>E print a quarter-float immediate value
4a5329c6 120
16980d0b 121 %y<code> print a single precision VFP reg.
2fbad815 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 123 %z<code> print a double precision VFP reg
2fbad815 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 125
16980d0b
JB		 126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
43e65147 129
2fbad815 130 %L print as an iWMMXt N/M width field.
4a5329c6 131 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 132 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
fe56b6ce 136 %r print register offset address for wldt/wstr instruction. */
2fbad815 137
21d799b5 138enum opcode_sentinel_enum
05413229
NC		 139{
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143} opcode_sentinels;
144
aefd8a40 145#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
fe56b6ce 411 /* Register load/store. */
823d2571
TG		 412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 453
fe56b6ce 454 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 483 /* Half-precision conversion instructions. */
823d2571
TG		 484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 492
fe56b6ce 493 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 628
629 /* Cirrus coprocessor instructions. */
823d2571
TG		 630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 802
62f3b8c8 803 /* VFP Fused multiply add instructions. */
823d2571
TG		 804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 820
33399f07 821 /* FP v5. */
823d2571 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 823 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 825 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 827 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 829 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 843 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 845 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 846
05413229 847 /* Generic coprocessor instructions. */
823d2571
TG		 848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 870
05413229 871 /* V6 coprocessor instructions. */
823d2571
TG		 872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 878
05413229 879 /* V5 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
b0c11777
RL		 894 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
895 cp_num: bit <11:8> == 0b1001.
896 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
898 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
900 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
902 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
904 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
906 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
908 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
910 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
912 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
914 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
916 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
918 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
920 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
922 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
924 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
926 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
928 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
930 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
932 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
967
823d2571 968 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 969};
970
16980d0b
JB		 971/* Neon opcode table: This does not encode the top byte -- that is
972 checked by the print_insn_neon routine, as it depends on whether we are
973 doing thumb32 or arm32 disassembly. */
974
975/* print_insn_neon recognizes the following format control codes:
976
977 %% %
978
c22aaad1 979 %c print condition code
e2efe87d
MGD		 980 %u print condition code (unconditional in ARM mode,
981 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 982 %A print v{st,ld}[1234] operands
983 %B print v{st,ld}[1234] any one operands
984 %C print v{st,ld}[1234] single->all operands
985 %D print scalar
986 %E print vmov, vmvn, vorr, vbic encoded constant
987 %F print vtbl,vtbx register list
988
989 %<bitfield>r print as an ARM register
990 %<bitfield>d print the bitfield in decimal
991 %<bitfield>e print the 2^N - bitfield in decimal
992 %<bitfield>D print as a NEON D register
993 %<bitfield>Q print as a NEON Q register
994 %<bitfield>R print as a NEON D or Q register
995 %<bitfield>Sn print byte scaled width limited by n
996 %<bitfield>Tn print short scaled width limited by n
997 %<bitfield>Un print long scaled width limited by n
43e65147 998
16980d0b
JB		 999 %<bitfield>'c print specified char iff bitfield is all ones
1000 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1001 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1002
1003static const struct opcode32 neon_opcodes[] =
1004{
fe56b6ce 1005 /* Extract. */
823d2571
TG		 1006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1007 0xf2b00840, 0xffb00850,
1008 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf2b00000, 0xffb00810,
1011 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1012
fe56b6ce 1013 /* Move data element to all lanes. */
823d2571
TG		 1014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1015 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1017 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1019 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1020
fe56b6ce 1021 /* Table lookup. */
823d2571
TG		 1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1026
8e79c3df 1027 /* Half-precision conversions. */
823d2571
TG		 1028 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1029 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1030 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1031 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1032
1033 /* NEON fused multiply add instructions. */
823d2571
TG		 1034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1035 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1037 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1038
fe56b6ce 1039 /* Two registers, miscellaneous. */
823d2571
TG		 1040 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1041 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1043 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1044 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1045 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1046 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1047 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1048 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1049 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1050 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1051 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1052 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1059 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1060 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1061 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1063 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1069 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b20300, 0xffb30fd0,
1080 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1082 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1084 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1086 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1087 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1088 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1090 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1092 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1096 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1098 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf3b30600, 0xffb30e10,
1125 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1126
fe56b6ce 1127 /* Three registers of the same length. */
823d2571
TG		 1128 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1129 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1130 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1131 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1132 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1133 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1134 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1135 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1136 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1137 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1138 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1139 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1141 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1143 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1145 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1151 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1187 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1193 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1198 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1199 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1200 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1201 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1203 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1205 0xf2000b00, 0xff800f10,
1206 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2000b10, 0xff800f10,
1209 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1211 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1213 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1217 0xf3000b00, 0xff800f10,
1218 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2000000, 0xfe800f10,
1221 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223 0xf2000010, 0xfe800f10,
1224 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2000100, 0xfe800f10,
1227 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229 0xf2000200, 0xfe800f10,
1230 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2000210, 0xfe800f10,
1233 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235 0xf2000300, 0xfe800f10,
1236 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2000310, 0xfe800f10,
1239 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241 0xf2000400, 0xfe800f10,
1242 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2000410, 0xfe800f10,
1245 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2000500, 0xfe800f10,
1248 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0xf2000510, 0xfe800f10,
1251 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2000600, 0xfe800f10,
1254 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256 0xf2000610, 0xfe800f10,
1257 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf2000700, 0xfe800f10,
1260 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf2000710, 0xfe800f10,
1263 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2000910, 0xfe800f10,
1266 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf2000a00, 0xfe800f10,
1269 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1271 0xf2000a10, 0xfe800f10,
1272 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1274 0xf3000b10, 0xff800f10,
1275 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1277 0xf3000c10, 0xff800f10,
1278 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1279
fe56b6ce 1280 /* One register and an immediate value. */
823d2571
TG		 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1307
fe56b6ce 1308 /* Two registers and a shift amount. */
823d2571
TG		 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2880950, 0xfeb80fd0,
1321 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2900950, 0xfeb00fd0,
1344 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2a00950, 0xfea00fd0,
1389 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2a00e10, 0xfea00e90,
1428 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1429
fe56b6ce 1430 /* Three registers of different lengths. */
823d2571
TG		 1431 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1432 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2800400, 0xff800f50,
1437 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2800600, 0xff800f50,
1440 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2800900, 0xff800f50,
1443 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2800b00, 0xff800f50,
1446 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2800d00, 0xff800f50,
1449 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3800400, 0xff800f50,
1452 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3800600, 0xff800f50,
1455 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2800000, 0xfe800f50,
1458 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2800100, 0xfe800f50,
1461 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2800200, 0xfe800f50,
1464 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf2800300, 0xfe800f50,
1467 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2800500, 0xfe800f50,
1470 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2800700, 0xfe800f50,
1473 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2800800, 0xfe800f50,
1476 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2800a00, 0xfe800f50,
1479 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf2800c00, 0xfe800f50,
1482 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1483
fe56b6ce 1484 /* Two registers and a scalar. */
823d2571
TG		 1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800240, 0xfe800f50,
1525 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800640, 0xfe800f50,
1528 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800a40, 0xfe800f50,
1531 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1533 0xf2800e40, 0xff800f50,
1534 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1536 0xf2800f40, 0xff800f50,
1537 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1539 0xf3800e40, 0xff800f50,
1540 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1542 0xf3800f40, 0xff800f50,
1543 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1544 },
16980d0b 1545
fe56b6ce 1546 /* Element and structure load/store. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1585
1586 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1587};
1588
8f06b2d8
PB		 1589/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1590 ordered: they must be searched linearly from the top to obtain a correct
1591 match. */
1592
1593/* print_insn_arm recognizes the following format control codes:
1594
1595 %% %
1596
1597 %a print address for ldr/str instruction
1598 %s print address for ldr/str halfword/signextend instruction
c1e26897 1599 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1600 %b print branch destination
1601 %c print condition code (always bits 28-31)
1602 %m print register mask for ldm/stm instruction
1603 %o print operand2 (immediate or register + shift)
1604 %p print 'p' iff bits 12-15 are 15
1605 %t print 't' iff bit 21 set and bit 24 clear
1606 %B print arm BLX(1) destination
1607 %C print the PSR sub type.
62b3e311
PB		 1608 %U print barrier type.
1609 %P print address for pli instruction.
8f06b2d8
PB		 1610
1611 %<bitfield>r print as an ARM register
9eb6c0f1 1612 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1613 %<bitfield>R as %r but r15 is UNPREDICTABLE
1614 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1615 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1616 %<bitfield>d print the bitfield in decimal
43e65147 1617 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1618 %<bitfield>x print the bitfield in hex
1619 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1620
16980d0b
JB		 1621 %<bitfield>'c print specified char iff bitfield is all ones
1622 %<bitfield>`c print specified char iff bitfield is all zeroes
1623 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1624
8f06b2d8
PB		 1625 %e print arm SMI operand (bits 0..7,8..19).
1626 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1627 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1628 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1629
8f06b2d8
PB		 1630static const struct opcode32 arm_opcodes[] =
1631{
1632 /* ARM instructions. */
823d2571
TG		 1633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1634 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1636 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1637
1638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1639 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1641 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1643 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1645 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1647 0x00800090, 0x0fa000f0,
1648 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1650 0x00a00090, 0x0fa000f0,
1651 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1652
105bde57
MW		 1653 /* V8.2 RAS extension instructions. */
1654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
1655 0xe320f010, 0xffffffff, "esb"},
1656
53c4b28b 1657 /* V8 instructions. */
823d2571
TG		 1658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1659 0x0320f005, 0x0fffffff, "sevl"},
1660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1661 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1663 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1664 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1665 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1667 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1669 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1670 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1671 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1672 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1673 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1674 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1675 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1676 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1677 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1678 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1679 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1680 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1681 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1682 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1683 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1684 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1685 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1686 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1687 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1688 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1689 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1690 /* CRC32 instructions. */
823d2571
TG		 1691 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1692 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1693 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1694 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1695 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1696 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1697 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1698 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1699 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1700 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1701 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1702 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1703
ddfded2f
MW		 1704 /* Privileged Access Never extension instructions. */
1705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1706 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1707
90ec0d68 1708 /* Virtualization Extension instructions. */
823d2571
TG		 1709 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1710 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1711
eea54501 1712 /* Integer Divide Extension instructions. */
823d2571
TG		 1713 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1714 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1716 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1717
60e5ef9f 1718 /* MP Extension instructions. */
823d2571 1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1720
62b3e311 1721 /* V7 instructions. */
823d2571
TG		 1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1730 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1731
c19d1205 1732 /* ARM V6T2 instructions. */
823d2571
TG		 1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1734 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1736 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1738 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1740 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1741
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1743 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1745 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1746
ff8646ee 1747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1748 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1750 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1752 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1754 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1755
f4c65163 1756 /* ARM Security extension instructions. */
823d2571
TG		 1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1758 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1759
8f06b2d8 1760 /* ARM V6K instructions. */
823d2571
TG		 1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1762 0xf57ff01f, 0xffffffff, "clrex"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1764 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1766 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1768 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1770 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1772 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1774 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1775
8f06b2d8 1776 /* ARM V6K NOP hints. */
823d2571
TG		 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1778 0x0320f001, 0x0fffffff, "yield%c"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1780 0x0320f002, 0x0fffffff, "wfe%c"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1782 0x0320f003, 0x0fffffff, "wfi%c"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1784 0x0320f004, 0x0fffffff, "sev%c"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1786 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1787
fe56b6ce 1788 /* ARM V6 instructions. */
823d2571
TG		 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2033
8f06b2d8 2034 /* V5J instruction. */
823d2571
TG		 2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2036 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2037
8f06b2d8 2038 /* V5 Instructions. */
823d2571
TG		 2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2040 0xe1200070, 0xfff000f0,
2041 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2043 0xfa000000, 0xfe000000, "blx\t%B"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2045 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2047 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2048
2049 /* V5E "El Segundo" Instructions. */
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2051 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2053 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2055 0xf450f000, 0xfc70f000, "pld\t%a"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2057 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2059 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2061 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2063 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2064
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2066 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2068 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2069
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2071 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2073 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2075 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2077 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2078
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2080 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2082 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2084 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2086 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2087
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2089 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2091 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2092
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2094 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2096 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2098 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2100 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2101
8f06b2d8 2102 /* ARM Instructions. */
823d2571
TG		 2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2104 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2105
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2107 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2109 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2111 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2115 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2117 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2118
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2120 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2122 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2124 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2126 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2127
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2129 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2133 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2135 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2136
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2138 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2140 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2142 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2143
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2145 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2147 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2149 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2150
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2152 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2154 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2156 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2157
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2159 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2161 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2163 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2164
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2171
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2173 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2178
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2180 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2182 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2185
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2194 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2196 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2198 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2199
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2206
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2208 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2210 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a
AV		 2212 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2214 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
823d2571
TG		 2215
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2222
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2229
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2236
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2251
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2258
2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2265
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2270
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2273
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2310 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x092d0000, 0x0fff0000, "push%c\t%m"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2317
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2335 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2337 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2349 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2356
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2361
2362 /* The rest. */
4ab90a7a
AV		 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2364 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2367 {ARM_FEATURE_CORE_LOW (0),
2368 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2369};
2370
2371/* print_insn_thumb16 recognizes the following format control codes:
2372
2373 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2374 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2375 %<bitfield>I print bitfield as a signed decimal
2376 (top bit of range being the sign bit)
2377 %N print Thumb register mask (with LR)
2378 %O print Thumb register mask (with PC)
2379 %M print Thumb register mask
2380 %b print CZB's 6-bit unsigned branch destination
2381 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2382 %c print the condition code
2383 %C print the condition code, or "s" if not conditional
2384 %x print warning if conditional an not at end of IT block"
2385 %X print "\t; unpredictable <IT:code>" if conditional
2386 %I print IT instruction suffix and operands
4547cb56 2387 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2388 %<bitfield>r print bitfield as an ARM register
2389 %<bitfield>d print bitfield as a decimal
2390 %<bitfield>H print (bitfield * 2) as a decimal
2391 %<bitfield>W print (bitfield * 4) as a decimal
2392 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2393 %<bitfield>B print Thumb branch destination (signed displacement)
2394 %<bitfield>c print bitfield as a condition code
2395 %<bitnum>'c print specified char iff bit is one
2396 %<bitnum>?ab print a if bit is one else print b. */
2397
2398static const struct opcode16 thumb_opcodes[] =
2399{
2400 /* Thumb instructions. */
2401
53c4b28b 2402 /* ARM V8 instructions. */
823d2571
TG		 2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2406
8f06b2d8 2407 /* ARM V6K no-argument instructions. */
823d2571
TG		 2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2414
2415 /* ARM V6T2 instructions. */
ff8646ee
TP		 2416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2417 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2418 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2419 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2421
2422 /* ARM V6. */
823d2571
TG		 2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2434
2435 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2437 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2438 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2440 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2441 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2443 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2444 /* Format 4. */
823d2571
TG		 2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2461 /* format 13 */
823d2571
TG		 2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2464 /* format 5 */
823d2571
TG		 2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2469 /* format 14 */
823d2571
TG		 2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2472 /* format 2 */
823d2571
TG		 2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2474 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2476 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2478 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2480 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2481 /* format 8 */
823d2571
TG		 2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2483 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2485 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2487 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2488 /* format 7 */
823d2571
TG		 2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2490 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2492 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2493 /* format 1 */
823d2571
TG		 2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2496 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2499 /* format 3 */
823d2571
TG		 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2504 /* format 6 */
823d2571
TG		 2505 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2507 0x4800, 0xF800,
2508 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2509 /* format 9 */
823d2571
TG		 2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2511 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2513 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2515 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2517 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2518 /* format 10 */
823d2571
TG		 2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2520 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2522 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2523 /* format 11 */
823d2571
TG		 2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2525 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2527 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2528 /* format 12 */
823d2571
TG		 2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2530 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2532 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2533 /* format 15 */
823d2571
TG		 2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2536 /* format 17 */
823d2571 2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2538 /* format 16 */
823d2571
TG		 2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2542 /* format 18 */
823d2571 2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2544
2545 /* The E800 .. FFFF range is unconditionally redirected to the
2546 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2547 are processed via that table. Thus, we can never encounter a
2548 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2550 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2551};
2552
2553/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2554 We adopt the convention that hw1 is the high 16 bits of .value and
2555 .mask, hw2 the low 16 bits.
2556
2557 print_insn_thumb32 recognizes the following format control codes:
2558
2559 %% %
2560
2561 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2562 %M print a modified 12-bit immediate (same location)
2563 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2564 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2565 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2566 %S print a possibly-shifted Rm
2567
32a94698 2568 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2569 %a print the address of a plain load/store
2570 %w print the width and signedness of a core load/store
2571 %m print register mask for ldm/stm
2572
2573 %E print the lsb and width fields of a bfc/bfi instruction
2574 %F print the lsb and width fields of a sbfx/ubfx instruction
2575 %b print a conditional branch offset
2576 %B print an unconditional branch offset
2577 %s print the shift field of an SSAT instruction
2578 %R print the rotation field of an SXT instruction
62b3e311
PB		 2579 %U print barrier type.
2580 %P print address for pli instruction.
c22aaad1
PB		 2581 %c print the condition code
2582 %x print warning if conditional an not at end of IT block"
2583 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2584
2585 %<bitfield>d print bitfield in decimal
f0fba320 2586 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2587 %<bitfield>W print bitfield*4 in decimal
2588 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2589 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2590 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2591 %<bitfield>c print bitfield as a condition code
2592
16980d0b
JB		 2593 %<bitfield>'c print specified char iff bitfield is all ones
2594 %<bitfield>`c print specified char iff bitfield is all zeroes
2595 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2596
2597 With one exception at the bottom (done because BL and BLX(1) need
2598 to come dead last), this table was machine-sorted first in
2599 decreasing order of number of bits set in the mask, then in
2600 increasing numeric order of mask, then in increasing numeric order
2601 of opcode. This order is not the clearest for a human reader, but
2602 is guaranteed never to catch a special-case bit pattern with a more
2603 general mask, which is important, because this instruction encoding
2604 makes heavy use of special-case bit patterns. */
2605static const struct opcode32 thumb32_opcodes[] =
2606{
4ed7ed8d
TP		 2607 /* V8-M instructions. */
2608 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2609 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2611 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2612
105bde57
MW		 2613 /* ARM V8.2 RAS extension instructions. */
2614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
2615 0xf3af8010, 0xffffffff, "esb"},
2616
53c4b28b 2617 /* V8 instructions. */
823d2571
TG		 2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2619 0xf3af8005, 0xffffffff, "sevl%c.w"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2621 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2623 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2625 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2627 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2629 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2631 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2633 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2635 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2637 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2639 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2641 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2643 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2645 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2647 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2649 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2650
dd5181d5 2651 /* CRC32 instructions. */
823d2571
TG		 2652 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2653 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2654 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2655 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2656 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2657 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2658 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2659 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2660 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2661 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2662 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2663 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2664
62b3e311 2665 /* V7 instructions. */
823d2571
TG		 2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2674 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2676 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2677
90ec0d68 2678 /* Virtualization Extension instructions. */
823d2571 2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2680 /* We skip ERET as that is SUBS pc, lr, #0. */
2681
60e5ef9f 2682 /* MP Extension instructions. */
823d2571 2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2684
f4c65163 2685 /* Security extension instructions. */
823d2571 2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2687
8f06b2d8 2688 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2697
ff8646ee 2698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2699 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2727 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2729 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2747 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2854 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2855 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2857 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 2922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2923 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf810f000, 0xff70f000, "pld%c\t%a"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfb100000, 0xfff000c0,
2956 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfbc00080, 0xfff000c0,
2959 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2965 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 2970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2971 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 2974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2975 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2997 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xe9400000, 0xff500000,
3032 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xe9500000, 0xff500000,
3035 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xe8600000, 0xff700000,
3038 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xe8700000, 0xff700000,
3041 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3046
3047 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3056
8f06b2d8 3057 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3059 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3061 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3062
3063 /* Fallback. */
823d2571
TG		 3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3065 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3066 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3067};
ff4a8d2b 3068
8f06b2d8
PB		 3069static const char *const arm_conditional[] =
3070{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3071 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3072
3073static const char *const arm_fp_const[] =
3074{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3075
3076static const char *const arm_shift[] =
3077{"lsl", "lsr", "asr", "ror"};
3078
3079typedef struct
3080{
3081 const char *name;
3082 const char *description;
3083 const char *reg_names[16];
3084}
3085arm_regname;
3086
3087static const arm_regname regnames[] =
3088{
3089 { "raw" , "Select raw register names",
3090 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3091 { "gcc", "Select register names used by GCC",
3092 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3093 { "std", "Select register names used in ARM's ISA documentation",
3094 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3095 { "apcs", "Select register names used in the APCS",
3096 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3097 { "atpcs", "Select register names used in the ATPCS",
3098 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3099 { "special-atpcs", "Select special register names used in the ATPCS",
3100 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3101};
3102
3103static const char *const iwmmxt_wwnames[] =
3104{"b", "h", "w", "d"};
3105
3106static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3107{"b", "bus", "bc", "bss",
3108 "h", "hus", "hc", "hss",
3109 "w", "wus", "wc", "wss",
3110 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3111};
3112
3113static const char *const iwmmxt_regnames[] =
3114{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3115 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3116};
3117
3118static const char *const iwmmxt_cregnames[] =
3119{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3120 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3121};
3122
3123/* Default to GCC register name set. */
3124static unsigned int regname_selected = 1;
3125
3126#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3127#define arm_regnames regnames[regname_selected].reg_names
3128
3129static bfd_boolean force_thumb = FALSE;
3130
c22aaad1
PB		 3131/* Current IT instruction state. This contains the same state as the IT
3132 bits in the CPSR. */
3133static unsigned int ifthen_state;
3134/* IT state for the next instruction. */
3135static unsigned int ifthen_next_state;
3136/* The address of the insn for which the IT state is valid. */
3137static bfd_vma ifthen_address;
3138#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3139/* Indicates that the current Conditional state is unconditional or outside
3140 an IT block. */
3141#define COND_UNCOND 16
c22aaad1 3142
8f06b2d8
PB		 3143\f
3144/* Functions. */
3145int
3146get_arm_regname_num_options (void)
3147{
3148 return NUM_ARM_REGNAMES;
3149}
3150
3151int
3152set_arm_regname_option (int option)
3153{
3154 int old = regname_selected;
3155 regname_selected = option;
3156 return old;
3157}
3158
3159int
fe56b6ce
NC		 3160get_arm_regnames (int option,
3161 const char **setname,
3162 const char **setdescription,
8f06b2d8
PB		 3163 const char *const **register_names)
3164{
3165 *setname = regnames[option].name;
3166 *setdescription = regnames[option].description;
3167 *register_names = regnames[option].reg_names;
3168 return 16;
3169}
3170
16980d0b
JB		 3171/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3172 Returns pointer to following character of the format string and
3173 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3174 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3175
3176static const char *
fe56b6ce
NC		 3177arm_decode_bitfield (const char *ptr,
3178 unsigned long insn,
3179 unsigned long *valuep,
3180 int *widthp)
16980d0b
JB		 3181{
3182 unsigned long value = 0;
3183 int width = 0;
43e65147
L		 3184
3185 do
16980d0b
JB		 3186 {
3187 int start, end;
3188 int bits;
3189
3190 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3191 start = start * 10 + *ptr - '0';
3192 if (*ptr == '-')
3193 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3194 end = end * 10 + *ptr - '0';
3195 else
3196 end = start;
3197 bits = end - start;
3198 if (bits < 0)
3199 abort ();
3200 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3201 width += bits + 1;
3202 }
3203 while (*ptr++ == ',');
3204 *valuep = value;
3205 if (widthp)
3206 *widthp = width;
3207 return ptr - 1;
3208}
3209
8f06b2d8 3210static void
37b37b2d 3211arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3212 bfd_boolean print_shift)
8f06b2d8
PB		 3213{
3214 func (stream, "%s", arm_regnames[given & 0xf]);
3215
3216 if ((given & 0xff0) != 0)
3217 {
3218 if ((given & 0x10) == 0)
3219 {
3220 int amount = (given & 0xf80) >> 7;
3221 int shift = (given & 0x60) >> 5;
3222
3223 if (amount == 0)
3224 {
3225 if (shift == 3)
3226 {
3227 func (stream, ", rrx");
3228 return;
3229 }
3230
3231 amount = 32;
3232 }
3233
37b37b2d
RE		 3234 if (print_shift)
3235 func (stream, ", %s #%d", arm_shift[shift], amount);
3236 else
3237 func (stream, ", #%d", amount);
8f06b2d8 3238 }
74bdfecf 3239 else if ((given & 0x80) == 0x80)
aefd8a40 3240 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3241 else if (print_shift)
8f06b2d8
PB		 3242 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3243 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3244 else
3245 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3246 }
3247}
3248
c1e26897
NC		 3249#define W_BIT 21
3250#define I_BIT 22
3251#define U_BIT 23
3252#define P_BIT 24
3253
3254#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3255#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3256#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3257#define PRE_BIT_SET (given & (1 << P_BIT))
3258
8f06b2d8
PB		 3259/* Print one coprocessor instruction on INFO->STREAM.
3260 Return TRUE if the instuction matched, FALSE if this is not a
3261 recognised coprocessor instruction. */
3262
3263static bfd_boolean
fe56b6ce
NC		 3264print_insn_coprocessor (bfd_vma pc,
3265 struct disassemble_info *info,
3266 long given,
8f06b2d8
PB		 3267 bfd_boolean thumb)
3268{
3269 const struct opcode32 *insn;
3270 void *stream = info->stream;
3271 fprintf_ftype func = info->fprintf_func;
3272 unsigned long mask;
2edcd244 3273 unsigned long value = 0;
c22aaad1 3274 int cond;
8afc7bea 3275 int cp_num;
823d2571
TG		 3276 struct arm_private_data *private_data = info->private_data;
3277 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3278
3279 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3280
3281 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3282 {
ff4a8d2b
NC		 3283 unsigned long u_reg = 16;
3284 bfd_boolean is_unpredictable = FALSE;
05413229 3285 signed long value_in_comment = 0;
0313a2b8
NC		 3286 const char *c;
3287
823d2571 3288 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3289 switch (insn->value)
3290 {
3291 case SENTINEL_IWMMXT_START:
3292 if (info->mach != bfd_mach_arm_XScale
3293 && info->mach != bfd_mach_arm_iWMMXt
3294 && info->mach != bfd_mach_arm_iWMMXt2)
3295 do
3296 insn++;
823d2571
TG		 3297 while ((! ARM_FEATURE_ZERO (insn->arch))
3298 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3299 continue;
3300
3301 case SENTINEL_IWMMXT_END:
3302 continue;
3303
3304 case SENTINEL_GENERIC_START:
823d2571 3305 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3306 continue;
3307
3308 default:
3309 abort ();
3310 }
8f06b2d8
PB		 3311
3312 mask = insn->mask;
3313 value = insn->value;
8afc7bea
RL		 3314 cp_num = (given >> 8) & 0xf;
3315
8f06b2d8
PB		 3316 if (thumb)
3317 {
3318 /* The high 4 bits are 0xe for Arm conditional instructions, and
3319 0xe for arm unconditional instructions. The rest of the
3320 encoding is the same. */
3321 mask |= 0xf0000000;
3322 value |= 0xe0000000;
c22aaad1
PB		 3323 if (ifthen_state)
3324 cond = IFTHEN_COND;
3325 else
e2efe87d 3326 cond = COND_UNCOND;
8f06b2d8
PB		 3327 }
3328 else
3329 {
3330 /* Only match unconditional instuctions against unconditional
3331 patterns. */
3332 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3333 {
3334 mask |= 0xf0000000;
e2efe87d 3335 cond = COND_UNCOND;
c22aaad1
PB		 3336 }
3337 else
3338 {
3339 cond = (given >> 28) & 0xf;
3340 if (cond == 0xe)
e2efe87d 3341 cond = COND_UNCOND;
c22aaad1 3342 }
8f06b2d8 3343 }
823d2571 3344
0313a2b8
NC		 3345 if ((given & mask) != value)
3346 continue;
8f06b2d8 3347
823d2571 3348 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3349 continue;
3350
8afc7bea
RL		 3351 if (insn->value == 0xfe000010 /* mcr2 */
3352 || insn->value == 0xfe100010 /* mrc2 */
3353 || insn->value == 0xfc100000 /* ldc2 */
3354 || insn->value == 0xfc000000) /* stc2 */
3355 {
b0c11777 3356 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3357 is_unpredictable = TRUE;
3358 }
3359 else if (insn->value == 0x0e000000 /* cdp */
3360 || insn->value == 0xfe000000 /* cdp2 */
3361 || insn->value == 0x0e000010 /* mcr */
3362 || insn->value == 0x0e100010 /* mrc */
3363 || insn->value == 0x0c100000 /* ldc */
3364 || insn->value == 0x0c000000) /* stc */
3365 {
3366 /* Floating-point instructions. */
b0c11777 3367 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3368 continue;
3369 }
3370
0313a2b8
NC		 3371 for (c = insn->assembler; *c; c++)
3372 {
3373 if (*c == '%')
8f06b2d8 3374 {
0313a2b8 3375 switch (*++c)
8f06b2d8 3376 {
0313a2b8
NC		 3377 case '%':
3378 func (stream, "%%");
3379 break;
3380
3381 case 'A':
05413229 3382 {
79862e45 3383 int rn = (given >> 16) & 0xf;
b0c11777 3384 bfd_vma offset = given & 0xff;
0313a2b8 3385
05413229 3386 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3387
79862e45
DJ		 3388 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3389 {
3390 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3391 if (cp_num == 9)
3392 /* vldr.16/vstr.16 will shift the address
3393 left by 1 bit only. */
3394 offset = offset * 2;
3395 else
3396 offset = offset * 4;
3397
79862e45
DJ		 3398 if (NEGATIVE_BIT_SET)
3399 offset = - offset;
3400 if (rn != 15)
3401 value_in_comment = offset;
3402 }
3403
c1e26897 3404 if (PRE_BIT_SET)
05413229
NC		 3405 {
3406 if (offset)
fe56b6ce 3407 func (stream, ", #%d]%s",
d908c8af 3408 (int) offset,
c1e26897 3409 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3410 else if (NEGATIVE_BIT_SET)
3411 func (stream, ", #-0]");
05413229
NC		 3412 else
3413 func (stream, "]");
3414 }
3415 else
3416 {
0313a2b8 3417 func (stream, "]");
8f06b2d8 3418
c1e26897 3419 if (WRITEBACK_BIT_SET)
05413229
NC		 3420 {
3421 if (offset)
d908c8af 3422 func (stream, ", #%d", (int) offset);
26d97720
NS		 3423 else if (NEGATIVE_BIT_SET)
3424 func (stream, ", #-0");
05413229
NC		 3425 }
3426 else
fe56b6ce 3427 {
26d97720
NS		 3428 func (stream, ", {%s%d}",
3429 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3430 (int) offset);
fe56b6ce
NC		 3431 value_in_comment = offset;
3432 }
05413229 3433 }
79862e45
DJ		 3434 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3435 {
3436 func (stream, "\t; ");
6844b2c2
MGD		 3437 /* For unaligned PCs, apply off-by-alignment
3438 correction. */
43e65147 3439 info->print_address_func (offset + pc
6844b2c2
MGD		 3440 + info->bytes_per_chunk * 2
3441 - (pc & 3),
3442 info);
79862e45 3443 }
05413229 3444 }
0313a2b8 3445 break;
8f06b2d8 3446
0313a2b8
NC		 3447 case 'B':
3448 {
3449 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3450 int offset = (given >> 1) & 0x3f;
3451
3452 if (offset == 1)
3453 func (stream, "{d%d}", regno);
3454 else if (regno + offset > 32)
3455 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3456 else
3457 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3458 }
3459 break;
8f06b2d8 3460
e2efe87d
MGD		 3461 case 'u':
3462 if (cond != COND_UNCOND)
3463 is_unpredictable = TRUE;
3464
3465 /* Fall through. */
0313a2b8 3466 case 'c':
b0c11777
RL		 3467 if (cond != COND_UNCOND && cp_num == 9)
3468 is_unpredictable = TRUE;
3469
0313a2b8
NC		 3470 func (stream, "%s", arm_conditional[cond]);
3471 break;
8f06b2d8 3472
0313a2b8
NC		 3473 case 'I':
3474 /* Print a Cirrus/DSP shift immediate. */
3475 /* Immediates are 7bit signed ints with bits 0..3 in
3476 bits 0..3 of opcode and bits 4..6 in bits 5..7
3477 of opcode. */
3478 {
3479 int imm;
8f06b2d8 3480
0313a2b8 3481 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3482
0313a2b8
NC		 3483 /* Is ``imm'' a negative number? */
3484 if (imm & 0x40)
24b4cf66 3485 imm -= 0x80;
8f06b2d8 3486
0313a2b8
NC		 3487 func (stream, "%d", imm);
3488 }
3489
3490 break;
8f06b2d8 3491
0313a2b8
NC		 3492 case 'F':
3493 switch (given & 0x00408000)
3494 {
3495 case 0:
3496 func (stream, "4");
3497 break;
3498 case 0x8000:
3499 func (stream, "1");
3500 break;
3501 case 0x00400000:
3502 func (stream, "2");
8f06b2d8 3503 break;
0313a2b8
NC		 3504 default:
3505 func (stream, "3");
3506 }
3507 break;
8f06b2d8 3508
0313a2b8
NC		 3509 case 'P':
3510 switch (given & 0x00080080)
3511 {
3512 case 0:
3513 func (stream, "s");
3514 break;
3515 case 0x80:
3516 func (stream, "d");
3517 break;
3518 case 0x00080000:
3519 func (stream, "e");
3520 break;
3521 default:
3522 func (stream, _("<illegal precision>"));
8f06b2d8 3523 break;
0313a2b8
NC		 3524 }
3525 break;
8f06b2d8 3526
0313a2b8
NC		 3527 case 'Q':
3528 switch (given & 0x00408000)
3529 {
3530 case 0:
3531 func (stream, "s");
8f06b2d8 3532 break;
0313a2b8
NC		 3533 case 0x8000:
3534 func (stream, "d");
8f06b2d8 3535 break;
0313a2b8
NC		 3536 case 0x00400000:
3537 func (stream, "e");
3538 break;
3539 default:
3540 func (stream, "p");
8f06b2d8 3541 break;
0313a2b8
NC		 3542 }
3543 break;
8f06b2d8 3544
0313a2b8
NC		 3545 case 'R':
3546 switch (given & 0x60)
3547 {
3548 case 0:
3549 break;
3550 case 0x20:
3551 func (stream, "p");
3552 break;
3553 case 0x40:
3554 func (stream, "m");
3555 break;
3556 default:
3557 func (stream, "z");
3558 break;
3559 }
3560 break;
16980d0b 3561
0313a2b8
NC		 3562 case '0': case '1': case '2': case '3': case '4':
3563 case '5': case '6': case '7': case '8': case '9':
3564 {
3565 int width;
8f06b2d8 3566
0313a2b8 3567 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3568
0313a2b8
NC		 3569 switch (*c)
3570 {
ff4a8d2b
NC		 3571 case 'R':
3572 if (value == 15)
3573 is_unpredictable = TRUE;
3574 /* Fall through. */
0313a2b8 3575 case 'r':
ff4a8d2b
NC		 3576 if (c[1] == 'u')
3577 {
3578 /* Eat the 'u' character. */
3579 ++ c;
3580
3581 if (u_reg == value)
3582 is_unpredictable = TRUE;
3583 u_reg = value;
3584 }
0313a2b8
NC		 3585 func (stream, "%s", arm_regnames[value]);
3586 break;
3587 case 'D':
3588 func (stream, "d%ld", value);
3589 break;
3590 case 'Q':
3591 if (value & 1)
3592 func (stream, "<illegal reg q%ld.5>", value >> 1);
3593 else
3594 func (stream, "q%ld", value >> 1);
3595 break;
3596 case 'd':
3597 func (stream, "%ld", value);
05413229 3598 value_in_comment = value;
0313a2b8 3599 break;
6f1c2142
AM		 3600 case 'E':
3601 {
3602 /* Converts immediate 8 bit back to float value. */
3603 unsigned floatVal = (value & 0x80) << 24
3604 | (value & 0x3F) << 19
3605 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3606
3607 /* Quarter float have a maximum value of 31.0.
3608 Get floating point value multiplied by 1e7.
3609 The maximum value stays in limit of a 32-bit int. */
3610 unsigned decVal =
3611 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3612 (16 + (value & 0xF));
3613
3614 if (!(decVal % 1000000))
3615 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3616 floatVal, value & 0x80 ? '-' : ' ',
3617 decVal / 10000000,
3618 decVal % 10000000 / 1000000);
3619 else if (!(decVal % 10000))
3620 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3621 floatVal, value & 0x80 ? '-' : ' ',
3622 decVal / 10000000,
3623 decVal % 10000000 / 10000);
3624 else
3625 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3626 floatVal, value & 0x80 ? '-' : ' ',
3627 decVal / 10000000, decVal % 10000000);
3628 break;
3629 }
0313a2b8
NC		 3630 case 'k':
3631 {
3632 int from = (given & (1 << 7)) ? 32 : 16;
3633 func (stream, "%ld", from - value);
3634 }
3635 break;
8f06b2d8 3636
0313a2b8
NC		 3637 case 'f':
3638 if (value > 7)
3639 func (stream, "#%s", arm_fp_const[value & 7]);
3640 else
3641 func (stream, "f%ld", value);
3642 break;
4146fd53 3643
0313a2b8
NC		 3644 case 'w':
3645 if (width == 2)
3646 func (stream, "%s", iwmmxt_wwnames[value]);
3647 else
3648 func (stream, "%s", iwmmxt_wwssnames[value]);
3649 break;
4146fd53 3650
0313a2b8
NC		 3651 case 'g':
3652 func (stream, "%s", iwmmxt_regnames[value]);
3653 break;
3654 case 'G':
3655 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3656 break;
8f06b2d8 3657
0313a2b8 3658 case 'x':
d1aaab3c 3659 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3660 break;
8f06b2d8 3661
33399f07
MGD		 3662 case 'c':
3663 switch (value)
3664 {
3665 case 0:
3666 func (stream, "eq");
3667 break;
3668
3669 case 1:
3670 func (stream, "vs");
3671 break;
3672
3673 case 2:
3674 func (stream, "ge");
3675 break;
3676
3677 case 3:
3678 func (stream, "gt");
3679 break;
3680
3681 default:
3682 func (stream, "??");
3683 break;
3684 }
3685 break;
3686
0313a2b8
NC		 3687 case '`':
3688 c++;
3689 if (value == 0)
3690 func (stream, "%c", *c);
3691 break;
3692 case '\'':
3693 c++;
3694 if (value == ((1ul << width) - 1))
3695 func (stream, "%c", *c);
3696 break;
3697 case '?':
fe56b6ce 3698 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3699 c += 1 << width;
3700 break;
3701 default:
3702 abort ();
3703 }
3704 break;
8f06b2d8 3705
0313a2b8
NC		 3706 case 'y':
3707 case 'z':
3708 {
3709 int single = *c++ == 'y';
3710 int regno;
3711
3712 switch (*c)
3713 {
3714 case '4': /* Sm pair */
3715 case '0': /* Sm, Dm */
3716 regno = given & 0x0000000f;
3717 if (single)
3718 {
3719 regno <<= 1;
3720 regno += (given >> 5) & 1;
16980d0b 3721 }
0313a2b8
NC		 3722 else
3723 regno += ((given >> 5) & 1) << 4;
3724 break;
8f06b2d8 3725
0313a2b8
NC		 3726 case '1': /* Sd, Dd */
3727 regno = (given >> 12) & 0x0000000f;
3728 if (single)
3729 {
3730 regno <<= 1;
3731 regno += (given >> 22) & 1;
3732 }
3733 else
3734 regno += ((given >> 22) & 1) << 4;
3735 break;
8f06b2d8 3736
0313a2b8
NC		 3737 case '2': /* Sn, Dn */
3738 regno = (given >> 16) & 0x0000000f;
3739 if (single)
8f06b2d8 3740 {
0313a2b8
NC		 3741 regno <<= 1;
3742 regno += (given >> 7) & 1;
8f06b2d8 3743 }
0313a2b8
NC		 3744 else
3745 regno += ((given >> 7) & 1) << 4;
3746 break;
7df76b80 3747
0313a2b8
NC		 3748 case '3': /* List */
3749 func (stream, "{");
3750 regno = (given >> 12) & 0x0000000f;
3751 if (single)
3752 {
3753 regno <<= 1;
3754 regno += (given >> 22) & 1;
3755 }
3756 else
3757 regno += ((given >> 22) & 1) << 4;
3758 break;
a7f8487e 3759
0313a2b8
NC		 3760 default:
3761 abort ();
8f06b2d8 3762 }
a7f8487e 3763
0313a2b8
NC		 3764 func (stream, "%c%d", single ? 's' : 'd', regno);
3765
3766 if (*c == '3')
8f06b2d8 3767 {
0313a2b8 3768 int count = given & 0xff;
a7f8487e 3769
0313a2b8
NC		 3770 if (single == 0)
3771 count >>= 1;
b34976b6 3772
0313a2b8 3773 if (--count)
8f06b2d8 3774 {
0313a2b8
NC		 3775 func (stream, "-%c%d",
3776 single ? 's' : 'd',
3777 regno + count);
8f06b2d8 3778 }
0313a2b8
NC		 3779
3780 func (stream, "}");
8f06b2d8 3781 }
0313a2b8
NC		 3782 else if (*c == '4')
3783 func (stream, ", %c%d", single ? 's' : 'd',
3784 regno + 1);
3785 }
3786 break;
3787
3788 case 'L':
3789 switch (given & 0x00400100)
3790 {
3791 case 0x00000000: func (stream, "b"); break;
3792 case 0x00400000: func (stream, "h"); break;
3793 case 0x00000100: func (stream, "w"); break;
3794 case 0x00400100: func (stream, "d"); break;
3795 default:
8f06b2d8 3796 break;
0313a2b8
NC		 3797 }
3798 break;
b34976b6 3799
0313a2b8
NC		 3800 case 'Z':
3801 {
0313a2b8
NC		 3802 /* given (20, 23) | given (0, 3) */
3803 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3804 func (stream, "%d", (int) value);
0313a2b8
NC		 3805 }
3806 break;
2d447fca 3807
0313a2b8
NC		 3808 case 'l':
3809 /* This is like the 'A' operator, except that if
3810 the width field "M" is zero, then the offset is
3811 *not* multiplied by four. */
3812 {
3813 int offset = given & 0xff;
3814 int multiplier = (given & 0x00000100) ? 4 : 1;
3815
3816 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3817
05413229
NC		 3818 if (multiplier > 1)
3819 {
3820 value_in_comment = offset * multiplier;
c1e26897 3821 if (NEGATIVE_BIT_SET)
05413229
NC		 3822 value_in_comment = - value_in_comment;
3823 }
3824
0313a2b8
NC		 3825 if (offset)
3826 {
c1e26897 3827 if (PRE_BIT_SET)
0313a2b8 3828 func (stream, ", #%s%d]%s",
c1e26897 3829 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3830 offset * multiplier,
c1e26897 3831 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3832 else
3833 func (stream, "], #%s%d",
c1e26897 3834 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3835 offset * multiplier);
2d447fca 3836 }
0313a2b8
NC		 3837 else
3838 func (stream, "]");
3839 }
3840 break;
3841
3842 case 'r':
3843 {
3844 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3845 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3846 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3847 const char *rm = arm_regnames [given & 0xf];
3848 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3849
0313a2b8 3850 switch (puw_bits)
2d447fca 3851 {
0313a2b8
NC		 3852 case 1:
3853 case 3:
3854 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3855 if (imm4)
3856 func (stream, ", lsl #%d", imm4);
3857 break;
3858
3859 case 4:
3860 case 5:
3861 case 6:
3862 case 7:
3863 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3864 if (imm4 > 0)
3865 func (stream, ", lsl #%d", imm4);
3866 func (stream, "]");
3867 if (puw_bits == 5 || puw_bits == 7)
3868 func (stream, "!");
3869 break;
3870
3871 default:
3872 func (stream, "INVALID");
2d447fca 3873 }
0313a2b8
NC		 3874 }
3875 break;
2d447fca 3876
0313a2b8
NC		 3877 case 'i':
3878 {
3879 long imm5;
3880 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3881 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3882 }
0313a2b8
NC		 3883 break;
3884
3885 default:
3886 abort ();
3887 }
252b5132 3888 }
252b5132 3889 }
0313a2b8
NC		 3890 else
3891 func (stream, "%c", *c);
252b5132 3892 }
05413229
NC		 3893
3894 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3895 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3896
ff4a8d2b
NC		 3897 if (is_unpredictable)
3898 func (stream, UNPREDICTABLE_INSTRUCTION);
3899
0313a2b8 3900 return TRUE;
252b5132 3901 }
8f06b2d8 3902 return FALSE;
252b5132
RH		 3903}
3904
05413229
NC		 3905/* Decodes and prints ARM addressing modes. Returns the offset
3906 used in the address, if any, if it is worthwhile printing the
3907 offset as a hexadecimal value in a comment at the end of the
3908 line of disassembly. */
3909
3910static signed long
62b3e311
PB		 3911print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3912{
3913 void *stream = info->stream;
3914 fprintf_ftype func = info->fprintf_func;
f8b960bc 3915 bfd_vma offset = 0;
62b3e311
PB		 3916
3917 if (((given & 0x000f0000) == 0x000f0000)
3918 && ((given & 0x02000000) == 0))
3919 {
05413229 3920 offset = given & 0xfff;
62b3e311
PB		 3921
3922 func (stream, "[pc");
3923
c1e26897 3924 if (PRE_BIT_SET)
62b3e311 3925 {
26d97720
NS		 3926 /* Pre-indexed. Elide offset of positive zero when
3927 non-writeback. */
3928 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3929 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3930
3931 if (NEGATIVE_BIT_SET)
3932 offset = -offset;
62b3e311
PB		 3933
3934 offset += pc + 8;
3935
3936 /* Cope with the possibility of write-back
3937 being used. Probably a very dangerous thing
3938 for the programmer to do, but who are we to
3939 argue ? */
26d97720 3940 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3941 }
c1e26897 3942 else /* Post indexed. */
62b3e311 3943 {
d908c8af 3944 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3945
c1e26897 3946 /* Ie ignore the offset. */
62b3e311
PB		 3947 offset = pc + 8;
3948 }
3949
3950 func (stream, "\t; ");
3951 info->print_address_func (offset, info);
05413229 3952 offset = 0;
62b3e311
PB		 3953 }
3954 else
3955 {
3956 func (stream, "[%s",
3957 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3958
3959 if (PRE_BIT_SET)
62b3e311
PB		 3960 {
3961 if ((given & 0x02000000) == 0)
3962 {
26d97720 3963 /* Elide offset of positive zero when non-writeback. */
05413229 3964 offset = given & 0xfff;
26d97720 3965 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3966 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3967 }
3968 else
3969 {
26d97720 3970 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3971 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3972 }
3973
3974 func (stream, "]%s",
c1e26897 3975 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3976 }
3977 else
3978 {
3979 if ((given & 0x02000000) == 0)
3980 {
26d97720 3981 /* Always show offset. */
05413229 3982 offset = given & 0xfff;
26d97720 3983 func (stream, "], #%s%d",
d908c8af 3984 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3985 }
3986 else
3987 {
3988 func (stream, "], %s",
c1e26897 3989 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3990 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3991 }
3992 }
84919466
MR		 3993 if (NEGATIVE_BIT_SET)
3994 offset = -offset;
62b3e311 3995 }
05413229
NC		 3996
3997 return (signed long) offset;
62b3e311
PB		 3998}
3999
16980d0b
JB		 4000/* Print one neon instruction on INFO->STREAM.
4001 Return TRUE if the instuction matched, FALSE if this is not a
4002 recognised neon instruction. */
4003
4004static bfd_boolean
4005print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4006{
4007 const struct opcode32 *insn;
4008 void *stream = info->stream;
4009 fprintf_ftype func = info->fprintf_func;
4010
4011 if (thumb)
4012 {
4013 if ((given & 0xef000000) == 0xef000000)
4014 {
0313a2b8 4015 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4016 unsigned long bit28 = given & (1 << 28);
4017
4018 given &= 0x00ffffff;
4019 if (bit28)
4020 given |= 0xf3000000;
4021 else
4022 given |= 0xf2000000;
4023 }
4024 else if ((given & 0xff000000) == 0xf9000000)
4025 given ^= 0xf9000000 ^ 0xf4000000;
4026 else
4027 return FALSE;
4028 }
43e65147 4029
16980d0b
JB		 4030 for (insn = neon_opcodes; insn->assembler; insn++)
4031 {
4032 if ((given & insn->mask) == insn->value)
4033 {
05413229 4034 signed long value_in_comment = 0;
e2efe87d 4035 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4036 const char *c;
4037
4038 for (c = insn->assembler; *c; c++)
4039 {
4040 if (*c == '%')
4041 {
4042 switch (*++c)
4043 {
4044 case '%':
4045 func (stream, "%%");
4046 break;
4047
e2efe87d
MGD		 4048 case 'u':
4049 if (thumb && ifthen_state)
4050 is_unpredictable = TRUE;
4051
4052 /* Fall through. */
c22aaad1
PB		 4053 case 'c':
4054 if (thumb && ifthen_state)
4055 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4056 break;
4057
16980d0b
JB		 4058 case 'A':
4059 {
43e65147 4060 static const unsigned char enc[16] =
16980d0b
JB		 4061 {
4062 0x4, 0x14, /* st4 0,1 */
4063 0x4, /* st1 2 */
4064 0x4, /* st2 3 */
4065 0x3, /* st3 4 */
4066 0x13, /* st3 5 */
4067 0x3, /* st1 6 */
4068 0x1, /* st1 7 */
4069 0x2, /* st2 8 */
4070 0x12, /* st2 9 */
4071 0x2, /* st1 10 */
4072 0, 0, 0, 0, 0
4073 };
4074 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4075 int rn = ((given >> 16) & 0xf);
4076 int rm = ((given >> 0) & 0xf);
4077 int align = ((given >> 4) & 0x3);
4078 int type = ((given >> 8) & 0xf);
4079 int n = enc[type] & 0xf;
4080 int stride = (enc[type] >> 4) + 1;
4081 int ix;
43e65147 4082
16980d0b
JB		 4083 func (stream, "{");
4084 if (stride > 1)
4085 for (ix = 0; ix != n; ix++)
4086 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4087 else if (n == 1)
4088 func (stream, "d%d", rd);
4089 else
4090 func (stream, "d%d-d%d", rd, rd + n - 1);
4091 func (stream, "}, [%s", arm_regnames[rn]);
4092 if (align)
8e560766 4093 func (stream, " :%d", 32 << align);
16980d0b
JB		 4094 func (stream, "]");
4095 if (rm == 0xd)
4096 func (stream, "!");
4097 else if (rm != 0xf)
4098 func (stream, ", %s", arm_regnames[rm]);
4099 }
4100 break;
43e65147 4101
16980d0b
JB		 4102 case 'B':
4103 {
4104 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4105 int rn = ((given >> 16) & 0xf);
4106 int rm = ((given >> 0) & 0xf);
4107 int idx_align = ((given >> 4) & 0xf);
4108 int align = 0;
4109 int size = ((given >> 10) & 0x3);
4110 int idx = idx_align >> (size + 1);
4111 int length = ((given >> 8) & 3) + 1;
4112 int stride = 1;
4113 int i;
4114
4115 if (length > 1 && size > 0)
4116 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4117
16980d0b
JB		 4118 switch (length)
4119 {
4120 case 1:
4121 {
4122 int amask = (1 << size) - 1;
4123 if ((idx_align & (1 << size)) != 0)
4124 return FALSE;
4125 if (size > 0)
4126 {
4127 if ((idx_align & amask) == amask)
4128 align = 8 << size;
4129 else if ((idx_align & amask) != 0)
4130 return FALSE;
4131 }
4132 }
4133 break;
43e65147 4134
16980d0b
JB		 4135 case 2:
4136 if (size == 2 && (idx_align & 2) != 0)
4137 return FALSE;
4138 align = (idx_align & 1) ? 16 << size : 0;
4139 break;
43e65147 4140
16980d0b
JB		 4141 case 3:
4142 if ((size == 2 && (idx_align & 3) != 0)
4143 || (idx_align & 1) != 0)
4144 return FALSE;
4145 break;
43e65147 4146
16980d0b
JB		 4147 case 4:
4148 if (size == 2)
4149 {
4150 if ((idx_align & 3) == 3)
4151 return FALSE;
4152 align = (idx_align & 3) * 64;
4153 }
4154 else
4155 align = (idx_align & 1) ? 32 << size : 0;
4156 break;
43e65147 4157
16980d0b
JB		 4158 default:
4159 abort ();
4160 }
43e65147 4161
16980d0b
JB		 4162 func (stream, "{");
4163 for (i = 0; i < length; i++)
4164 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4165 rd + i * stride, idx);
4166 func (stream, "}, [%s", arm_regnames[rn]);
4167 if (align)
8e560766 4168 func (stream, " :%d", align);
16980d0b
JB		 4169 func (stream, "]");
4170 if (rm == 0xd)
4171 func (stream, "!");
4172 else if (rm != 0xf)
4173 func (stream, ", %s", arm_regnames[rm]);
4174 }
4175 break;
43e65147 4176
16980d0b
JB		 4177 case 'C':
4178 {
4179 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4180 int rn = ((given >> 16) & 0xf);
4181 int rm = ((given >> 0) & 0xf);
4182 int align = ((given >> 4) & 0x1);
4183 int size = ((given >> 6) & 0x3);
4184 int type = ((given >> 8) & 0x3);
4185 int n = type + 1;
4186 int stride = ((given >> 5) & 0x1);
4187 int ix;
43e65147 4188
16980d0b
JB		 4189 if (stride && (n == 1))
4190 n++;
4191 else
4192 stride++;
43e65147 4193
16980d0b
JB		 4194 func (stream, "{");
4195 if (stride > 1)
4196 for (ix = 0; ix != n; ix++)
4197 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4198 else if (n == 1)
4199 func (stream, "d%d[]", rd);
4200 else
4201 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4202 func (stream, "}, [%s", arm_regnames[rn]);
4203 if (align)
4204 {
91d6fa6a 4205 align = (8 * (type + 1)) << size;
16980d0b
JB		 4206 if (type == 3)
4207 align = (size > 1) ? align >> 1 : align;
4208 if (type == 2 || (type == 0 && !size))
8e560766 4209 func (stream, " :<bad align %d>", align);
16980d0b 4210 else
8e560766 4211 func (stream, " :%d", align);
16980d0b
JB		 4212 }
4213 func (stream, "]");
4214 if (rm == 0xd)
4215 func (stream, "!");
4216 else if (rm != 0xf)
4217 func (stream, ", %s", arm_regnames[rm]);
4218 }
4219 break;
43e65147 4220
16980d0b
JB		 4221 case 'D':
4222 {
4223 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4224 int size = (given >> 20) & 3;
4225 int reg = raw_reg & ((4 << size) - 1);
4226 int ix = raw_reg >> size >> 2;
43e65147 4227
16980d0b
JB		 4228 func (stream, "d%d[%d]", reg, ix);
4229 }
4230 break;
43e65147 4231
16980d0b 4232 case 'E':
fe56b6ce 4233 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4234 {
4235 int bits = 0;
4236 int cmode = (given >> 8) & 0xf;
4237 int op = (given >> 5) & 0x1;
4238 unsigned long value = 0, hival = 0;
4239 unsigned shift;
4240 int size = 0;
0dbde4cf 4241 int isfloat = 0;
43e65147 4242
16980d0b
JB		 4243 bits |= ((given >> 24) & 1) << 7;
4244 bits |= ((given >> 16) & 7) << 4;
4245 bits |= ((given >> 0) & 15) << 0;
43e65147 4246
16980d0b
JB		 4247 if (cmode < 8)
4248 {
4249 shift = (cmode >> 1) & 3;
fe56b6ce 4250 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4251 size = 32;
4252 }
4253 else if (cmode < 12)
4254 {
4255 shift = (cmode >> 1) & 1;
fe56b6ce 4256 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4257 size = 16;
4258 }
4259 else if (cmode < 14)
4260 {
4261 shift = (cmode & 1) + 1;
fe56b6ce 4262 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4263 value |= (1ul << (8 * shift)) - 1;
4264 size = 32;
4265 }
4266 else if (cmode == 14)
4267 {
4268 if (op)
4269 {
fe56b6ce 4270 /* Bit replication into bytes. */
16980d0b
JB		 4271 int ix;
4272 unsigned long mask;
43e65147 4273
16980d0b
JB		 4274 value = 0;
4275 hival = 0;
4276 for (ix = 7; ix >= 0; ix--)
4277 {
4278 mask = ((bits >> ix) & 1) ? 0xff : 0;
4279 if (ix <= 3)
4280 value = (value << 8) | mask;
4281 else
4282 hival = (hival << 8) | mask;
4283 }
4284 size = 64;
4285 }
4286 else
4287 {
fe56b6ce
NC		 4288 /* Byte replication. */
4289 value = (unsigned long) bits;
16980d0b
JB		 4290 size = 8;
4291 }
4292 }
4293 else if (!op)
4294 {
fe56b6ce 4295 /* Floating point encoding. */
16980d0b 4296 int tmp;
43e65147 4297
fe56b6ce
NC		 4298 value = (unsigned long) (bits & 0x7f) << 19;
4299 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4300 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4301 value |= (unsigned long) tmp << 24;
16980d0b 4302 size = 32;
0dbde4cf 4303 isfloat = 1;
16980d0b
JB		 4304 }
4305 else
4306 {
4307 func (stream, "<illegal constant %.8x:%x:%x>",
4308 bits, cmode, op);
4309 size = 32;
4310 break;
4311 }
4312 switch (size)
4313 {
4314 case 8:
4315 func (stream, "#%ld\t; 0x%.2lx", value, value);
4316 break;
43e65147 4317
16980d0b
JB		 4318 case 16:
4319 func (stream, "#%ld\t; 0x%.4lx", value, value);
4320 break;
4321
4322 case 32:
0dbde4cf
JB		 4323 if (isfloat)
4324 {
4325 unsigned char valbytes[4];
4326 double fvalue;
43e65147 4327
0dbde4cf
JB		 4328 /* Do this a byte at a time so we don't have to
4329 worry about the host's endianness. */
4330 valbytes[0] = value & 0xff;
4331 valbytes[1] = (value >> 8) & 0xff;
4332 valbytes[2] = (value >> 16) & 0xff;
4333 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4334
4335 floatformat_to_double
c1e26897
NC		 4336 (& floatformat_ieee_single_little, valbytes,
4337 & fvalue);
43e65147 4338
0dbde4cf
JB		 4339 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4340 value);
4341 }
4342 else
4e9d3b81 4343 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4344 (long) (((value & 0x80000000L) != 0)
9d82ec38 4345 ? value | ~0xffffffffL : value),
c1e26897 4346 value);
16980d0b
JB		 4347 break;
4348
4349 case 64:
4350 func (stream, "#0x%.8lx%.8lx", hival, value);
4351 break;
43e65147 4352
16980d0b
JB		 4353 default:
4354 abort ();
4355 }
4356 }
4357 break;
43e65147 4358
16980d0b
JB		 4359 case 'F':
4360 {
4361 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4362 int num = (given >> 8) & 0x3;
43e65147 4363
16980d0b
JB		 4364 if (!num)
4365 func (stream, "{d%d}", regno);
4366 else if (num + regno >= 32)
4367 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4368 else
4369 func (stream, "{d%d-d%d}", regno, regno + num);
4370 }
4371 break;
7e8e6784 4372
16980d0b
JB		 4373
4374 case '0': case '1': case '2': case '3': case '4':
4375 case '5': case '6': case '7': case '8': case '9':
4376 {
4377 int width;
4378 unsigned long value;
4379
4380 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4381
16980d0b
JB		 4382 switch (*c)
4383 {
4384 case 'r':
4385 func (stream, "%s", arm_regnames[value]);
4386 break;
4387 case 'd':
4388 func (stream, "%ld", value);
05413229 4389 value_in_comment = value;
16980d0b
JB		 4390 break;
4391 case 'e':
4392 func (stream, "%ld", (1ul << width) - value);
4393 break;
43e65147 4394
16980d0b
JB		 4395 case 'S':
4396 case 'T':
4397 case 'U':
05413229 4398 /* Various width encodings. */
16980d0b
JB		 4399 {
4400 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4401 int limit;
4402 unsigned low, high;
4403
4404 c++;
4405 if (*c >= '0' && *c <= '9')
4406 limit = *c - '0';
4407 else if (*c >= 'a' && *c <= 'f')
4408 limit = *c - 'a' + 10;
4409 else
4410 abort ();
4411 low = limit >> 2;
4412 high = limit & 3;
4413
4414 if (value < low || value > high)
4415 func (stream, "<illegal width %d>", base << value);
4416 else
4417 func (stream, "%d", base << value);
4418 }
4419 break;
4420 case 'R':
4421 if (given & (1 << 6))
4422 goto Q;
4423 /* FALLTHROUGH */
4424 case 'D':
4425 func (stream, "d%ld", value);
4426 break;
4427 case 'Q':
4428 Q:
4429 if (value & 1)
4430 func (stream, "<illegal reg q%ld.5>", value >> 1);
4431 else
4432 func (stream, "q%ld", value >> 1);
4433 break;
43e65147 4434
16980d0b
JB		 4435 case '`':
4436 c++;
4437 if (value == 0)
4438 func (stream, "%c", *c);
4439 break;
4440 case '\'':
4441 c++;
4442 if (value == ((1ul << width) - 1))
4443 func (stream, "%c", *c);
4444 break;
4445 case '?':
fe56b6ce 4446 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4447 c += 1 << width;
4448 break;
4449 default:
4450 abort ();
4451 }
4452 break;
4453
4454 default:
4455 abort ();
4456 }
4457 }
4458 }
4459 else
4460 func (stream, "%c", *c);
4461 }
05413229
NC		 4462
4463 if (value_in_comment > 32 || value_in_comment < -16)
4464 func (stream, "\t; 0x%lx", value_in_comment);
4465
e2efe87d
MGD		 4466 if (is_unpredictable)
4467 func (stream, UNPREDICTABLE_INSTRUCTION);
4468
16980d0b
JB		 4469 return TRUE;
4470 }
4471 }
4472 return FALSE;
4473}
4474
90ec0d68
MGD		 4475/* Return the name of a v7A special register. */
4476
43e65147 4477static const char *
90ec0d68
MGD		 4478banked_regname (unsigned reg)
4479{
4480 switch (reg)
4481 {
4482 case 15: return "CPSR";
43e65147 4483 case 32: return "R8_usr";
90ec0d68
MGD		 4484 case 33: return "R9_usr";
4485 case 34: return "R10_usr";
4486 case 35: return "R11_usr";
4487 case 36: return "R12_usr";
4488 case 37: return "SP_usr";
4489 case 38: return "LR_usr";
43e65147 4490 case 40: return "R8_fiq";
90ec0d68
MGD		 4491 case 41: return "R9_fiq";
4492 case 42: return "R10_fiq";
4493 case 43: return "R11_fiq";
4494 case 44: return "R12_fiq";
4495 case 45: return "SP_fiq";
4496 case 46: return "LR_fiq";
4497 case 48: return "LR_irq";
4498 case 49: return "SP_irq";
4499 case 50: return "LR_svc";
4500 case 51: return "SP_svc";
4501 case 52: return "LR_abt";
4502 case 53: return "SP_abt";
4503 case 54: return "LR_und";
4504 case 55: return "SP_und";
4505 case 60: return "LR_mon";
4506 case 61: return "SP_mon";
4507 case 62: return "ELR_hyp";
4508 case 63: return "SP_hyp";
4509 case 79: return "SPSR";
4510 case 110: return "SPSR_fiq";
4511 case 112: return "SPSR_irq";
4512 case 114: return "SPSR_svc";
4513 case 116: return "SPSR_abt";
4514 case 118: return "SPSR_und";
4515 case 124: return "SPSR_mon";
4516 case 126: return "SPSR_hyp";
4517 default: return NULL;
4518 }
4519}
4520
e797f7e0
MGD		 4521/* Return the name of the DMB/DSB option. */
4522static const char *
4523data_barrier_option (unsigned option)
4524{
4525 switch (option & 0xf)
4526 {
4527 case 0xf: return "sy";
4528 case 0xe: return "st";
4529 case 0xd: return "ld";
4530 case 0xb: return "ish";
4531 case 0xa: return "ishst";
4532 case 0x9: return "ishld";
4533 case 0x7: return "un";
4534 case 0x6: return "unst";
4535 case 0x5: return "nshld";
4536 case 0x3: return "osh";
4537 case 0x2: return "oshst";
4538 case 0x1: return "oshld";
4539 default: return NULL;
4540 }
4541}
4542
4a5329c6
ZW		 4543/* Print one ARM instruction from PC on INFO->STREAM. */
4544
4545static void
4546print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4547{
6b5d3a4d 4548 const struct opcode32 *insn;
6a51a8a8 4549 void *stream = info->stream;
6b5d3a4d 4550 fprintf_ftype func = info->fprintf_func;
b0e28b39 4551 struct arm_private_data *private_data = info->private_data;
252b5132 4552
16980d0b
JB		 4553 if (print_insn_coprocessor (pc, info, given, FALSE))
4554 return;
4555
4556 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4557 return;
4558
252b5132
RH		 4559 for (insn = arm_opcodes; insn->assembler; insn++)
4560 {
0313a2b8
NC		 4561 if ((given & insn->mask) != insn->value)
4562 continue;
823d2571
TG		 4563
4564 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4565 continue;
4566
4567 /* Special case: an instruction with all bits set in the condition field
4568 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4569 or by the catchall at the end of the table. */
4570 if ((given & 0xF0000000) != 0xF0000000
4571 || (insn->mask & 0xF0000000) == 0xF0000000
4572 || (insn->mask == 0 && insn->value == 0))
252b5132 4573 {
ff4a8d2b
NC		 4574 unsigned long u_reg = 16;
4575 unsigned long U_reg = 16;
ab8e2090 4576 bfd_boolean is_unpredictable = FALSE;
05413229 4577 signed long value_in_comment = 0;
6b5d3a4d 4578 const char *c;
b34976b6 4579
252b5132
RH		 4580 for (c = insn->assembler; *c; c++)
4581 {
4582 if (*c == '%')
4583 {
c1e26897
NC		 4584 bfd_boolean allow_unpredictable = FALSE;
4585
252b5132
RH		 4586 switch (*++c)
4587 {
4588 case '%':
4589 func (stream, "%%");
4590 break;
4591
4592 case 'a':
05413229 4593 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4594 break;
252b5132 4595
62b3e311
PB		 4596 case 'P':
4597 /* Set P address bit and use normal address
4598 printing routine. */
c1e26897 4599 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4600 break;
4601
c1e26897
NC		 4602 case 'S':
4603 allow_unpredictable = TRUE;
252b5132
RH		 4604 case 's':
4605 if ((given & 0x004f0000) == 0x004f0000)
4606 {
58efb6c0 4607 /* PC relative with immediate offset. */
f8b960bc 4608 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4609
aefd8a40
NC		 4610 if (PRE_BIT_SET)
4611 {
26d97720
NS		 4612 /* Elide positive zero offset. */
4613 if (offset || NEGATIVE_BIT_SET)
4614 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4615 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4616 else
26d97720
NS		 4617 func (stream, "[pc]\t; ");
4618 if (NEGATIVE_BIT_SET)
4619 offset = -offset;
aefd8a40
NC		 4620 info->print_address_func (offset + pc + 8, info);
4621 }
4622 else
4623 {
26d97720
NS		 4624 /* Always show the offset. */
4625 func (stream, "[pc], #%s%d",
d908c8af 4626 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4627 if (! allow_unpredictable)
4628 is_unpredictable = TRUE;
aefd8a40 4629 }
252b5132
RH		 4630 }
4631 else
4632 {
fe56b6ce
NC		 4633 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4634
b34976b6 4635 func (stream, "[%s",
252b5132 4636 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4637
c1e26897 4638 if (PRE_BIT_SET)
252b5132 4639 {
c1e26897 4640 if (IMMEDIATE_BIT_SET)
252b5132 4641 {
26d97720
NS		 4642 /* Elide offset for non-writeback
4643 positive zero. */
4644 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4645 || offset)
4646 func (stream, ", #%s%d",
4647 NEGATIVE_BIT_SET ? "-" : "", offset);
4648
4649 if (NEGATIVE_BIT_SET)
4650 offset = -offset;
945ee430 4651
fe56b6ce 4652 value_in_comment = offset;
252b5132 4653 }
945ee430 4654 else
ff4a8d2b
NC		 4655 {
4656 /* Register Offset or Register Pre-Indexed. */
4657 func (stream, ", %s%s",
4658 NEGATIVE_BIT_SET ? "-" : "",
4659 arm_regnames[given & 0xf]);
4660
4661 /* Writing back to the register that is the source/
4662 destination of the load/store is unpredictable. */
4663 if (! allow_unpredictable
4664 && WRITEBACK_BIT_SET
4665 && ((given & 0xf) == ((given >> 12) & 0xf)))
4666 is_unpredictable = TRUE;
4667 }
252b5132 4668
b34976b6 4669 func (stream, "]%s",
c1e26897 4670 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4671 }
945ee430 4672 else
252b5132 4673 {
c1e26897 4674 if (IMMEDIATE_BIT_SET)
252b5132 4675 {
945ee430 4676 /* Immediate Post-indexed. */
aefd8a40 4677 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4678 func (stream, "], #%s%d",
4679 NEGATIVE_BIT_SET ? "-" : "", offset);
4680 if (NEGATIVE_BIT_SET)
4681 offset = -offset;
fe56b6ce 4682 value_in_comment = offset;
252b5132 4683 }
945ee430 4684 else
ff4a8d2b
NC		 4685 {
4686 /* Register Post-indexed. */
4687 func (stream, "], %s%s",
4688 NEGATIVE_BIT_SET ? "-" : "",
4689 arm_regnames[given & 0xf]);
4690
4691 /* Writing back to the register that is the source/
4692 destination of the load/store is unpredictable. */
4693 if (! allow_unpredictable
4694 && (given & 0xf) == ((given >> 12) & 0xf))
4695 is_unpredictable = TRUE;
4696 }
c1e26897 4697
07a28fab
NC		 4698 if (! allow_unpredictable)
4699 {
4700 /* Writeback is automatically implied by post- addressing.
4701 Setting the W bit is unnecessary and ARM specify it as
4702 being unpredictable. */
4703 if (WRITEBACK_BIT_SET
4704 /* Specifying the PC register as the post-indexed
4705 registers is also unpredictable. */
ab8e2090
NC		 4706 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4707 is_unpredictable = TRUE;
07a28fab 4708 }
252b5132
RH		 4709 }
4710 }
4711 break;
b34976b6 4712
252b5132 4713 case 'b':
6b5d3a4d 4714 {
f8b960bc 4715 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4716 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4717 }
252b5132
RH		 4718 break;
4719
4720 case 'c':
c22aaad1
PB		 4721 if (((given >> 28) & 0xf) != 0xe)
4722 func (stream, "%s",
4723 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4724 break;
4725
4726 case 'm':
4727 {
4728 int started = 0;
4729 int reg;
4730
4731 func (stream, "{");
4732 for (reg = 0; reg < 16; reg++)
4733 if ((given & (1 << reg)) != 0)
4734 {
4735 if (started)
4736 func (stream, ", ");
4737 started = 1;
4738 func (stream, "%s", arm_regnames[reg]);
4739 }
4740 func (stream, "}");
ab8e2090
NC		 4741 if (! started)
4742 is_unpredictable = TRUE;
252b5132
RH		 4743 }
4744 break;
4745
37b37b2d 4746 case 'q':
78c66db8 4747 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4748 break;
4749
252b5132
RH		 4750 case 'o':
4751 if ((given & 0x02000000) != 0)
4752 {
a415b1cd
JB		 4753 unsigned int rotate = (given & 0xf00) >> 7;
4754 unsigned int immed = (given & 0xff);
4755 unsigned int a, i;
4756
4757 a = (((immed << (32 - rotate))
4758 | (immed >> rotate)) & 0xffffffff);
4759 /* If there is another encoding with smaller rotate,
4760 the rotate should be specified directly. */
4761 for (i = 0; i < 32; i += 2)
4762 if ((a << i | a >> (32 - i)) <= 0xff)
4763 break;
4764
4765 if (i != rotate)
4766 func (stream, "#%d, %d", immed, rotate);
4767 else
4768 func (stream, "#%d", a);
4769 value_in_comment = a;
252b5132
RH		 4770 }
4771 else
78c66db8 4772 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4773 break;
4774
4775 case 'p':
4776 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4777 {
823d2571
TG		 4778 arm_feature_set arm_ext_v6 =
4779 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4780
aefd8a40
NC		 4781 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4782 mechanism for setting PSR flag bits. They are
4783 obsolete in V6 onwards. */
823d2571
TG		 4784 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4785 arm_ext_v6))
aefd8a40 4786 func (stream, "p");
4ab90a7a
AV		 4787 else
4788 is_unpredictable = TRUE;
aefd8a40 4789 }
252b5132
RH		 4790 break;
4791
4792 case 't':
4793 if ((given & 0x01200000) == 0x00200000)
4794 func (stream, "t");
4795 break;
4796
252b5132 4797 case 'A':
05413229
NC		 4798 {
4799 int offset = given & 0xff;
f02232aa 4800
05413229 4801 value_in_comment = offset * 4;
c1e26897 4802 if (NEGATIVE_BIT_SET)
05413229 4803 value_in_comment = - value_in_comment;
f02232aa 4804
05413229 4805 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4806
c1e26897 4807 if (PRE_BIT_SET)
05413229
NC		 4808 {
4809 if (offset)
fe56b6ce 4810 func (stream, ", #%d]%s",
d908c8af 4811 (int) value_in_comment,
c1e26897 4812 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4813 else
4814 func (stream, "]");
4815 }
4816 else
4817 {
4818 func (stream, "]");
f02232aa 4819
c1e26897 4820 if (WRITEBACK_BIT_SET)
05413229
NC		 4821 {
4822 if (offset)
d908c8af 4823 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4824 }
4825 else
fe56b6ce 4826 {
d908c8af 4827 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4828 value_in_comment = offset;
4829 }
05413229
NC		 4830 }
4831 }
252b5132
RH		 4832 break;
4833
077b8428
NC		 4834 case 'B':
4835 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4836 {
4837 bfd_vma address;
4838 bfd_vma offset = 0;
b34976b6 4839
c1e26897 4840 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4841 /* Is signed, hi bits should be ones. */
4842 offset = (-1) ^ 0x00ffffff;
4843
4844 /* Offset is (SignExtend(offset field)<<2). */
4845 offset += given & 0x00ffffff;
4846 offset <<= 2;
4847 address = offset + pc + 8;
b34976b6 4848
8f06b2d8
PB		 4849 if (given & 0x01000000)
4850 /* H bit allows addressing to 2-byte boundaries. */
4851 address += 2;
b1ee46c5 4852
8f06b2d8 4853 info->print_address_func (address, info);
b1ee46c5 4854 }
b1ee46c5
AH		 4855 break;
4856
252b5132 4857 case 'C':
90ec0d68
MGD		 4858 if ((given & 0x02000200) == 0x200)
4859 {
4860 const char * name;
4861 unsigned sysm = (given & 0x004f0000) >> 16;
4862
4863 sysm |= (given & 0x300) >> 4;
4864 name = banked_regname (sysm);
4865
4866 if (name != NULL)
4867 func (stream, "%s", name);
4868 else
d908c8af 4869 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4870 }
4871 else
4872 {
43e65147 4873 func (stream, "%cPSR_",
90ec0d68
MGD		 4874 (given & 0x00400000) ? 'S' : 'C');
4875 if (given & 0x80000)
4876 func (stream, "f");
4877 if (given & 0x40000)
4878 func (stream, "s");
4879 if (given & 0x20000)
4880 func (stream, "x");
4881 if (given & 0x10000)
4882 func (stream, "c");
4883 }
252b5132
RH		 4884 break;
4885
62b3e311 4886 case 'U':
43e65147 4887 if ((given & 0xf0) == 0x60)
62b3e311 4888 {
52e7f43d
RE		 4889 switch (given & 0xf)
4890 {
4891 case 0xf: func (stream, "sy"); break;
4892 default:
4893 func (stream, "#%d", (int) given & 0xf);
4894 break;
4895 }
43e65147
L		 4896 }
4897 else
52e7f43d 4898 {
e797f7e0
MGD		 4899 const char * opt = data_barrier_option (given & 0xf);
4900 if (opt != NULL)
4901 func (stream, "%s", opt);
4902 else
52e7f43d 4903 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4904 }
4905 break;
4906
b34976b6 4907 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4908 case '5': case '6': case '7': case '8': case '9':
4909 {
16980d0b
JB		 4910 int width;
4911 unsigned long value;
252b5132 4912
16980d0b 4913 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4914
252b5132
RH		 4915 switch (*c)
4916 {
ab8e2090
NC		 4917 case 'R':
4918 if (value == 15)
4919 is_unpredictable = TRUE;
4920 /* Fall through. */
16980d0b 4921 case 'r':
9eb6c0f1
MGD		 4922 case 'T':
4923 /* We want register + 1 when decoding T. */
4924 if (*c == 'T')
4925 ++value;
4926
ff4a8d2b
NC		 4927 if (c[1] == 'u')
4928 {
4929 /* Eat the 'u' character. */
4930 ++ c;
4931
4932 if (u_reg == value)
4933 is_unpredictable = TRUE;
4934 u_reg = value;
4935 }
4936 if (c[1] == 'U')
4937 {
4938 /* Eat the 'U' character. */
4939 ++ c;
4940
4941 if (U_reg == value)
4942 is_unpredictable = TRUE;
4943 U_reg = value;
4944 }
16980d0b
JB		 4945 func (stream, "%s", arm_regnames[value]);
4946 break;
4947 case 'd':
4948 func (stream, "%ld", value);
05413229 4949 value_in_comment = value;
16980d0b
JB		 4950 break;
4951 case 'b':
4952 func (stream, "%ld", value * 8);
05413229 4953 value_in_comment = value * 8;
16980d0b
JB		 4954 break;
4955 case 'W':
4956 func (stream, "%ld", value + 1);
05413229 4957 value_in_comment = value + 1;
16980d0b
JB		 4958 break;
4959 case 'x':
4960 func (stream, "0x%08lx", value);
4961
4962 /* Some SWI instructions have special
4963 meanings. */
4964 if ((given & 0x0fffffff) == 0x0FF00000)
4965 func (stream, "\t; IMB");
4966 else if ((given & 0x0fffffff) == 0x0FF00001)
4967 func (stream, "\t; IMBRange");
4968 break;
4969 case 'X':
4970 func (stream, "%01lx", value & 0xf);
05413229 4971 value_in_comment = value;
252b5132
RH		 4972 break;
4973 case '`':
4974 c++;
16980d0b 4975 if (value == 0)
252b5132
RH		 4976 func (stream, "%c", *c);
4977 break;
4978 case '\'':
4979 c++;
16980d0b 4980 if (value == ((1ul << width) - 1))
252b5132
RH		 4981 func (stream, "%c", *c);
4982 break;
4983 case '?':
fe56b6ce 4984 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4985 c += 1 << width;
252b5132
RH		 4986 break;
4987 default:
4988 abort ();
4989 }
4990 break;
4991
0dd132b6
NC		 4992 case 'e':
4993 {
4994 int imm;
4995
4996 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4997 func (stream, "%d", imm);
fe56b6ce 4998 value_in_comment = imm;
0dd132b6
NC		 4999 }
5000 break;
5001
0a003adc
ZW		 5002 case 'E':
5003 /* LSB and WIDTH fields of BFI or BFC. The machine-
5004 language instruction encodes LSB and MSB. */
5005 {
5006 long msb = (given & 0x001f0000) >> 16;
5007 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5008 long w = msb - lsb + 1;
fe56b6ce 5009
91d6fa6a
NC		 5010 if (w > 0)
5011 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5012 else
5013 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5014 }
5015 break;
5016
90ec0d68
MGD		 5017 case 'R':
5018 /* Get the PSR/banked register name. */
5019 {
5020 const char * name;
5021 unsigned sysm = (given & 0x004f0000) >> 16;
5022
5023 sysm |= (given & 0x300) >> 4;
5024 name = banked_regname (sysm);
5025
5026 if (name != NULL)
5027 func (stream, "%s", name);
5028 else
d908c8af 5029 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5030 }
5031 break;
5032
0a003adc
ZW		 5033 case 'V':
5034 /* 16-bit unsigned immediate from a MOVT or MOVW
5035 instruction, encoded in bits 0:11 and 15:19. */
5036 {
5037 long hi = (given & 0x000f0000) >> 4;
5038 long lo = (given & 0x00000fff);
5039 long imm16 = hi | lo;
fe56b6ce
NC		 5040
5041 func (stream, "#%lu", imm16);
5042 value_in_comment = imm16;
0a003adc
ZW		 5043 }
5044 break;
5045
252b5132
RH		 5046 default:
5047 abort ();
5048 }
5049 }
5050 }
5051 else
5052 func (stream, "%c", *c);
5053 }
05413229
NC		 5054
5055 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5056 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5057
5058 if (is_unpredictable)
5059 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5060
4a5329c6 5061 return;
252b5132
RH		 5062 }
5063 }
5064 abort ();
5065}
5066
4a5329c6 5067/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5068
4a5329c6
ZW		 5069static void
5070print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5071{
6b5d3a4d 5072 const struct opcode16 *insn;
6a51a8a8
AM		 5073 void *stream = info->stream;
5074 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5075
5076 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5077 if ((given & insn->mask) == insn->value)
5078 {
05413229 5079 signed long value_in_comment = 0;
6b5d3a4d 5080 const char *c = insn->assembler;
05413229 5081
c19d1205
ZW		 5082 for (; *c; c++)
5083 {
5084 int domaskpc = 0;
5085 int domasklr = 0;
5086
5087 if (*c != '%')
5088 {
5089 func (stream, "%c", *c);
5090 continue;
5091 }
252b5132 5092
c19d1205
ZW		 5093 switch (*++c)
5094 {
5095 case '%':
5096 func (stream, "%%");
5097 break;
b34976b6 5098
c22aaad1
PB		 5099 case 'c':
5100 if (ifthen_state)
5101 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5102 break;
5103
5104 case 'C':
5105 if (ifthen_state)
5106 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5107 else
5108 func (stream, "s");
5109 break;
5110
5111 case 'I':
5112 {
5113 unsigned int tmp;
5114
5115 ifthen_next_state = given & 0xff;
5116 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5117 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5118 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5119 }
5120 break;
5121
5122 case 'x':
5123 if (ifthen_next_state)
5124 func (stream, "\t; unpredictable branch in IT block\n");
5125 break;
5126
5127 case 'X':
5128 if (ifthen_state)
5129 func (stream, "\t; unpredictable <IT:%s>",
5130 arm_conditional[IFTHEN_COND]);
5131 break;
5132
c19d1205
ZW		 5133 case 'S':
5134 {
5135 long reg;
5136
5137 reg = (given >> 3) & 0x7;
5138 if (given & (1 << 6))
5139 reg += 8;
4f3c3dbb 5140
c19d1205
ZW		 5141 func (stream, "%s", arm_regnames[reg]);
5142 }
5143 break;
baf0cc5e 5144
c19d1205 5145 case 'D':
4f3c3dbb 5146 {
c19d1205
ZW		 5147 long reg;
5148
5149 reg = given & 0x7;
5150 if (given & (1 << 7))
5151 reg += 8;
5152
5153 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5154 }
c19d1205
ZW		 5155 break;
5156
5157 case 'N':
5158 if (given & (1 << 8))
5159 domasklr = 1;
5160 /* Fall through. */
5161 case 'O':
5162 if (*c == 'O' && (given & (1 << 8)))
5163 domaskpc = 1;
5164 /* Fall through. */
5165 case 'M':
5166 {
5167 int started = 0;
5168 int reg;
5169
5170 func (stream, "{");
5171
5172 /* It would be nice if we could spot
5173 ranges, and generate the rS-rE format: */
5174 for (reg = 0; (reg < 8); reg++)
5175 if ((given & (1 << reg)) != 0)
5176 {
5177 if (started)
5178 func (stream, ", ");
5179 started = 1;
5180 func (stream, "%s", arm_regnames[reg]);
5181 }
5182
5183 if (domasklr)
5184 {
5185 if (started)
5186 func (stream, ", ");
5187 started = 1;
d908c8af 5188 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5189 }
5190
5191 if (domaskpc)
5192 {
5193 if (started)
5194 func (stream, ", ");
d908c8af 5195 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5196 }
5197
5198 func (stream, "}");
5199 }
5200 break;
5201
4547cb56
NC		 5202 case 'W':
5203 /* Print writeback indicator for a LDMIA. We are doing a
5204 writeback if the base register is not in the register
5205 mask. */
5206 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5207 func (stream, "!");
5208 break;
5209
c19d1205
ZW		 5210 case 'b':
5211 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5212 {
5213 bfd_vma address = (pc + 4
5214 + ((given & 0x00f8) >> 2)
5215 + ((given & 0x0200) >> 3));
5216 info->print_address_func (address, info);
5217 }
5218 break;
5219
5220 case 's':
5221 /* Right shift immediate -- bits 6..10; 1-31 print
5222 as themselves, 0 prints as 32. */
5223 {
5224 long imm = (given & 0x07c0) >> 6;
5225 if (imm == 0)
5226 imm = 32;
0fd3a477 5227 func (stream, "#%ld", imm);
c19d1205
ZW		 5228 }
5229 break;
5230
5231 case '0': case '1': case '2': case '3': case '4':
5232 case '5': case '6': case '7': case '8': case '9':
5233 {
5234 int bitstart = *c++ - '0';
5235 int bitend = 0;
5236
5237 while (*c >= '0' && *c <= '9')
5238 bitstart = (bitstart * 10) + *c++ - '0';
5239
5240 switch (*c)
5241 {
5242 case '-':
5243 {
f8b960bc 5244 bfd_vma reg;
c19d1205
ZW		 5245
5246 c++;
5247 while (*c >= '0' && *c <= '9')
5248 bitend = (bitend * 10) + *c++ - '0';
5249 if (!bitend)
5250 abort ();
5251 reg = given >> bitstart;
5252 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5253
c19d1205
ZW		 5254 switch (*c)
5255 {
5256 case 'r':
5257 func (stream, "%s", arm_regnames[reg]);
5258 break;
5259
5260 case 'd':
d908c8af 5261 func (stream, "%ld", (long) reg);
05413229 5262 value_in_comment = reg;
c19d1205
ZW		 5263 break;
5264
5265 case 'H':
d908c8af 5266 func (stream, "%ld", (long) (reg << 1));
05413229 5267 value_in_comment = reg << 1;
c19d1205
ZW		 5268 break;
5269
5270 case 'W':
d908c8af 5271 func (stream, "%ld", (long) (reg << 2));
05413229 5272 value_in_comment = reg << 2;
c19d1205
ZW		 5273 break;
5274
5275 case 'a':
5276 /* PC-relative address -- the bottom two
5277 bits of the address are dropped
5278 before the calculation. */
5279 info->print_address_func
5280 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5281 value_in_comment = 0;
c19d1205
ZW		 5282 break;
5283
5284 case 'x':
d908c8af 5285 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5286 break;
5287
c19d1205
ZW		 5288 case 'B':
5289 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5290 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5291 value_in_comment = 0;
c19d1205
ZW		 5292 break;
5293
5294 case 'c':
c22aaad1 5295 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5296 break;
5297
5298 default:
5299 abort ();
5300 }
5301 }
5302 break;
5303
5304 case '\'':
5305 c++;
5306 if ((given & (1 << bitstart)) != 0)
5307 func (stream, "%c", *c);
5308 break;
5309
5310 case '?':
5311 ++c;
5312 if ((given & (1 << bitstart)) != 0)
5313 func (stream, "%c", *c++);
5314 else
5315 func (stream, "%c", *++c);
5316 break;
5317
5318 default:
5319 abort ();
5320 }
5321 }
5322 break;
5323
5324 default:
5325 abort ();
5326 }
5327 }
05413229
NC		 5328
5329 if (value_in_comment > 32 || value_in_comment < -16)
5330 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5331 return;
c19d1205
ZW		 5332 }
5333
5334 /* No match. */
5335 abort ();
5336}
5337
62b3e311 5338/* Return the name of an V7M special register. */
fe56b6ce 5339
62b3e311
PB		 5340static const char *
5341psr_name (int regno)
5342{
5343 switch (regno)
5344 {
5345 case 0: return "APSR";
5346 case 1: return "IAPSR";
5347 case 2: return "EAPSR";
5348 case 3: return "PSR";
5349 case 5: return "IPSR";
5350 case 6: return "EPSR";
5351 case 7: return "IEPSR";
5352 case 8: return "MSP";
5353 case 9: return "PSP";
5354 case 16: return "PRIMASK";
5355 case 17: return "BASEPRI";
00bbc0bd 5356 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5357 case 19: return "FAULTMASK";
5358 case 20: return "CONTROL";
5359 default: return "<unknown>";
5360 }
5361}
5362
4a5329c6
ZW		 5363/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5364
5365static void
5366print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5367{
6b5d3a4d 5368 const struct opcode32 *insn;
c19d1205
ZW		 5369 void *stream = info->stream;
5370 fprintf_ftype func = info->fprintf_func;
5371
16980d0b
JB		 5372 if (print_insn_coprocessor (pc, info, given, TRUE))
5373 return;
5374
5375 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5376 return;
5377
c19d1205
ZW		 5378 for (insn = thumb32_opcodes; insn->assembler; insn++)
5379 if ((given & insn->mask) == insn->value)
5380 {
ff4a8d2b 5381 bfd_boolean is_unpredictable = FALSE;
05413229 5382 signed long value_in_comment = 0;
6b5d3a4d 5383 const char *c = insn->assembler;
05413229 5384
c19d1205
ZW		 5385 for (; *c; c++)
5386 {
5387 if (*c != '%')
5388 {
5389 func (stream, "%c", *c);
5390 continue;
5391 }
5392
5393 switch (*++c)
5394 {
5395 case '%':
5396 func (stream, "%%");
5397 break;
5398
c22aaad1
PB		 5399 case 'c':
5400 if (ifthen_state)
5401 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5402 break;
5403
5404 case 'x':
5405 if (ifthen_next_state)
5406 func (stream, "\t; unpredictable branch in IT block\n");
5407 break;
5408
5409 case 'X':
5410 if (ifthen_state)
5411 func (stream, "\t; unpredictable <IT:%s>",
5412 arm_conditional[IFTHEN_COND]);
5413 break;
5414
c19d1205
ZW		 5415 case 'I':
5416 {
5417 unsigned int imm12 = 0;
fe56b6ce 5418
c19d1205
ZW		 5419 imm12 |= (given & 0x000000ffu);
5420 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5421 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5422 func (stream, "#%u", imm12);
5423 value_in_comment = imm12;
c19d1205
ZW		 5424 }
5425 break;
5426
5427 case 'M':
5428 {
5429 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5430
c19d1205
ZW		 5431 bits |= (given & 0x000000ffu);
5432 bits |= (given & 0x00007000u) >> 4;
5433 bits |= (given & 0x04000000u) >> 15;
5434 imm8 = (bits & 0x0ff);
5435 mod = (bits & 0xf00) >> 8;
5436 switch (mod)
5437 {
5438 case 0: imm = imm8; break;
c1e26897
NC		 5439 case 1: imm = ((imm8 << 16) | imm8); break;
5440 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5441 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5442 default:
5443 mod = (bits & 0xf80) >> 7;
5444 imm8 = (bits & 0x07f) | 0x80;
5445 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5446 }
fe56b6ce
NC		 5447 func (stream, "#%u", imm);
5448 value_in_comment = imm;
c19d1205
ZW		 5449 }
5450 break;
43e65147 5451
c19d1205
ZW		 5452 case 'J':
5453 {
5454 unsigned int imm = 0;
fe56b6ce 5455
c19d1205
ZW		 5456 imm |= (given & 0x000000ffu);
5457 imm |= (given & 0x00007000u) >> 4;
5458 imm |= (given & 0x04000000u) >> 15;
5459 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5460 func (stream, "#%u", imm);
5461 value_in_comment = imm;
c19d1205
ZW		 5462 }
5463 break;
5464
5465 case 'K':
5466 {
5467 unsigned int imm = 0;
fe56b6ce 5468
c19d1205
ZW		 5469 imm |= (given & 0x000f0000u) >> 16;
5470 imm |= (given & 0x00000ff0u) >> 0;
5471 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5472 func (stream, "#%u", imm);
5473 value_in_comment = imm;
c19d1205
ZW		 5474 }
5475 break;
5476
74db7efb
NC		 5477 case 'H':
5478 {
5479 unsigned int imm = 0;
5480
5481 imm |= (given & 0x000f0000u) >> 4;
5482 imm |= (given & 0x00000fffu) >> 0;
5483 func (stream, "#%u", imm);
5484 value_in_comment = imm;
5485 }
5486 break;
5487
90ec0d68
MGD		 5488 case 'V':
5489 {
5490 unsigned int imm = 0;
5491
5492 imm |= (given & 0x00000fffu);
5493 imm |= (given & 0x000f0000u) >> 4;
5494 func (stream, "#%u", imm);
5495 value_in_comment = imm;
5496 }
5497 break;
5498
c19d1205
ZW		 5499 case 'S':
5500 {
5501 unsigned int reg = (given & 0x0000000fu);
5502 unsigned int stp = (given & 0x00000030u) >> 4;
5503 unsigned int imm = 0;
5504 imm |= (given & 0x000000c0u) >> 6;
5505 imm |= (given & 0x00007000u) >> 10;
5506
5507 func (stream, "%s", arm_regnames[reg]);
5508 switch (stp)
5509 {
5510 case 0:
5511 if (imm > 0)
5512 func (stream, ", lsl #%u", imm);
5513 break;
5514
5515 case 1:
5516 if (imm == 0)
5517 imm = 32;
5518 func (stream, ", lsr #%u", imm);
5519 break;
5520
5521 case 2:
5522 if (imm == 0)
5523 imm = 32;
5524 func (stream, ", asr #%u", imm);
5525 break;
5526
5527 case 3:
5528 if (imm == 0)
5529 func (stream, ", rrx");
5530 else
5531 func (stream, ", ror #%u", imm);
5532 }
5533 }
5534 break;
5535
5536 case 'a':
5537 {
5538 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5539 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5540 unsigned int op = (given & 0x00000f00) >> 8;
5541 unsigned int i12 = (given & 0x00000fff);
5542 unsigned int i8 = (given & 0x000000ff);
5543 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5544 bfd_vma offset = 0;
c19d1205
ZW		 5545
5546 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5547 if (U) /* 12-bit positive immediate offset. */
5548 {
5549 offset = i12;
5550 if (Rn != 15)
5551 value_in_comment = offset;
5552 }
5553 else if (Rn == 15) /* 12-bit negative immediate offset. */
5554 offset = - (int) i12;
5555 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5556 {
5557 unsigned int Rm = (i8 & 0x0f);
5558 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5559
c19d1205
ZW		 5560 func (stream, ", %s", arm_regnames[Rm]);
5561 if (sh)
5562 func (stream, ", lsl #%u", sh);
5563 func (stream, "]");
5564 break;
5565 }
5566 else switch (op)
5567 {
05413229 5568 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5569 offset = i8;
5570 break;
5571
05413229 5572 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5573 offset = -i8;
5574 break;
5575
05413229 5576 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5577 offset = i8;
5578 writeback = TRUE;
5579 break;
5580
05413229 5581 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5582 offset = -i8;
5583 writeback = TRUE;
5584 break;
5585
05413229 5586 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5587 offset = i8;
5588 postind = TRUE;
5589 break;
5590
05413229 5591 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5592 offset = -i8;
5593 postind = TRUE;
5594 break;
5595
5596 default:
5597 func (stream, ", <undefined>]");
5598 goto skip;
5599 }
5600
5601 if (postind)
d908c8af 5602 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5603 else
5604 {
5605 if (offset)
d908c8af 5606 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5607 func (stream, writeback ? "]!" : "]");
5608 }
5609
5610 if (Rn == 15)
5611 {
5612 func (stream, "\t; ");
5613 info->print_address_func (((pc + 4) & ~3) + offset, info);
5614 }
5615 }
5616 skip:
5617 break;
5618
5619 case 'A':
5620 {
c1e26897
NC		 5621 unsigned int U = ! NEGATIVE_BIT_SET;
5622 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5623 unsigned int Rn = (given & 0x000f0000) >> 16;
5624 unsigned int off = (given & 0x000000ff);
5625
5626 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5627
5628 if (PRE_BIT_SET)
c19d1205
ZW		 5629 {
5630 if (off || !U)
05413229
NC		 5631 {
5632 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5633 value_in_comment = off * 4 * U ? 1 : -1;
5634 }
c19d1205
ZW		 5635 func (stream, "]");
5636 if (W)
5637 func (stream, "!");
5638 }
5639 else
5640 {
5641 func (stream, "], ");
5642 if (W)
05413229
NC		 5643 {
5644 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5645 value_in_comment = off * 4 * U ? 1 : -1;
5646 }
c19d1205 5647 else
fe56b6ce
NC		 5648 {
5649 func (stream, "{%u}", off);
5650 value_in_comment = off;
5651 }
c19d1205
ZW		 5652 }
5653 }
5654 break;
5655
5656 case 'w':
5657 {
5658 unsigned int Sbit = (given & 0x01000000) >> 24;
5659 unsigned int type = (given & 0x00600000) >> 21;
05413229 5660
c19d1205
ZW		 5661 switch (type)
5662 {
5663 case 0: func (stream, Sbit ? "sb" : "b"); break;
5664 case 1: func (stream, Sbit ? "sh" : "h"); break;
5665 case 2:
5666 if (Sbit)
5667 func (stream, "??");
5668 break;
5669 case 3:
5670 func (stream, "??");
5671 break;
5672 }
5673 }
5674 break;
5675
5676 case 'm':
5677 {
5678 int started = 0;
5679 int reg;
5680
5681 func (stream, "{");
5682 for (reg = 0; reg < 16; reg++)
5683 if ((given & (1 << reg)) != 0)
5684 {
5685 if (started)
5686 func (stream, ", ");
5687 started = 1;
5688 func (stream, "%s", arm_regnames[reg]);
5689 }
5690 func (stream, "}");
5691 }
5692 break;
5693
5694 case 'E':
5695 {
5696 unsigned int msb = (given & 0x0000001f);
5697 unsigned int lsb = 0;
fe56b6ce 5698
c19d1205
ZW		 5699 lsb |= (given & 0x000000c0u) >> 6;
5700 lsb |= (given & 0x00007000u) >> 10;
5701 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5702 }
5703 break;
5704
5705 case 'F':
5706 {
5707 unsigned int width = (given & 0x0000001f) + 1;
5708 unsigned int lsb = 0;
fe56b6ce 5709
c19d1205
ZW		 5710 lsb |= (given & 0x000000c0u) >> 6;
5711 lsb |= (given & 0x00007000u) >> 10;
5712 func (stream, "#%u, #%u", lsb, width);
5713 }
5714 break;
5715
5716 case 'b':
5717 {
5718 unsigned int S = (given & 0x04000000u) >> 26;
5719 unsigned int J1 = (given & 0x00002000u) >> 13;
5720 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5721 bfd_vma offset = 0;
c19d1205
ZW		 5722
5723 offset |= !S << 20;
5724 offset |= J2 << 19;
5725 offset |= J1 << 18;
5726 offset |= (given & 0x003f0000) >> 4;
5727 offset |= (given & 0x000007ff) << 1;
5728 offset -= (1 << 20);
5729
5730 info->print_address_func (pc + 4 + offset, info);
5731 }
5732 break;
5733
5734 case 'B':
5735 {
5736 unsigned int S = (given & 0x04000000u) >> 26;
5737 unsigned int I1 = (given & 0x00002000u) >> 13;
5738 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5739 bfd_vma offset = 0;
c19d1205
ZW		 5740
5741 offset |= !S << 24;
5742 offset |= !(I1 ^ S) << 23;
5743 offset |= !(I2 ^ S) << 22;
5744 offset |= (given & 0x03ff0000u) >> 4;
5745 offset |= (given & 0x000007ffu) << 1;
5746 offset -= (1 << 24);
36b0c57d 5747 offset += pc + 4;
c19d1205 5748
36b0c57d
PB		 5749 /* BLX target addresses are always word aligned. */
5750 if ((given & 0x00001000u) == 0)
5751 offset &= ~2u;
5752
5753 info->print_address_func (offset, info);
c19d1205
ZW		 5754 }
5755 break;
5756
5757 case 's':
5758 {
5759 unsigned int shift = 0;
fe56b6ce 5760
c19d1205
ZW		 5761 shift |= (given & 0x000000c0u) >> 6;
5762 shift |= (given & 0x00007000u) >> 10;
c1e26897 5763 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5764 func (stream, ", asr #%u", shift);
5765 else if (shift)
5766 func (stream, ", lsl #%u", shift);
5767 /* else print nothing - lsl #0 */
5768 }
5769 break;
5770
5771 case 'R':
5772 {
5773 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5774
c19d1205
ZW		 5775 if (rot)
5776 func (stream, ", ror #%u", rot * 8);
5777 }
5778 break;
5779
62b3e311 5780 case 'U':
43e65147 5781 if ((given & 0xf0) == 0x60)
62b3e311 5782 {
52e7f43d
RE		 5783 switch (given & 0xf)
5784 {
5785 case 0xf: func (stream, "sy"); break;
5786 default:
5787 func (stream, "#%d", (int) given & 0xf);
5788 break;
5789 }
62b3e311 5790 }
43e65147 5791 else
52e7f43d 5792 {
e797f7e0
MGD		 5793 const char * opt = data_barrier_option (given & 0xf);
5794 if (opt != NULL)
5795 func (stream, "%s", opt);
5796 else
5797 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5798 }
62b3e311
PB		 5799 break;
5800
5801 case 'C':
5802 if ((given & 0xff) == 0)
5803 {
5804 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5805 if (given & 0x800)
5806 func (stream, "f");
5807 if (given & 0x400)
5808 func (stream, "s");
5809 if (given & 0x200)
5810 func (stream, "x");
5811 if (given & 0x100)
5812 func (stream, "c");
5813 }
90ec0d68
MGD		 5814 else if ((given & 0x20) == 0x20)
5815 {
5816 char const* name;
5817 unsigned sysm = (given & 0xf00) >> 8;
5818
5819 sysm |= (given & 0x30);
5820 sysm |= (given & 0x00100000) >> 14;
5821 name = banked_regname (sysm);
43e65147 5822
90ec0d68
MGD		 5823 if (name != NULL)
5824 func (stream, "%s", name);
5825 else
d908c8af 5826 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5827 }
62b3e311
PB		 5828 else
5829 {
d908c8af 5830 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5831 }
5832 break;
5833
5834 case 'D':
90ec0d68
MGD		 5835 if (((given & 0xff) == 0)
5836 || ((given & 0x20) == 0x20))
5837 {
5838 char const* name;
5839 unsigned sm = (given & 0xf0000) >> 16;
5840
5841 sm |= (given & 0x30);
5842 sm |= (given & 0x00100000) >> 14;
5843 name = banked_regname (sm);
5844
5845 if (name != NULL)
5846 func (stream, "%s", name);
5847 else
d908c8af 5848 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5849 }
62b3e311 5850 else
d908c8af 5851 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5852 break;
5853
c19d1205
ZW		 5854 case '0': case '1': case '2': case '3': case '4':
5855 case '5': case '6': case '7': case '8': case '9':
5856 {
16980d0b
JB		 5857 int width;
5858 unsigned long val;
c19d1205 5859
16980d0b 5860 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5861
c19d1205
ZW		 5862 switch (*c)
5863 {
05413229
NC		 5864 case 'd':
5865 func (stream, "%lu", val);
5866 value_in_comment = val;
5867 break;
ff4a8d2b 5868
f0fba320
RL		 5869 case 'D':
5870 func (stream, "%lu", val + 1);
5871 value_in_comment = val + 1;
5872 break;
5873
05413229
NC		 5874 case 'W':
5875 func (stream, "%lu", val * 4);
5876 value_in_comment = val * 4;
5877 break;
ff4a8d2b 5878
dd5181d5
KT		 5879 case 'S':
5880 if (val == 13)
5881 is_unpredictable = TRUE;
5882 /* Fall through. */
ff4a8d2b
NC		 5883 case 'R':
5884 if (val == 15)
5885 is_unpredictable = TRUE;
5886 /* Fall through. */
5887 case 'r':
5888 func (stream, "%s", arm_regnames[val]);
5889 break;
c19d1205
ZW		 5890
5891 case 'c':
c22aaad1 5892 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5893 break;
5894
5895 case '\'':
c19d1205 5896 c++;
16980d0b
JB		 5897 if (val == ((1ul << width) - 1))
5898 func (stream, "%c", *c);
c19d1205 5899 break;
43e65147 5900
c19d1205 5901 case '`':
c19d1205 5902 c++;
16980d0b
JB		 5903 if (val == 0)
5904 func (stream, "%c", *c);
c19d1205
ZW		 5905 break;
5906
5907 case '?':
fe56b6ce 5908 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5909 c += 1 << width;
c19d1205 5910 break;
43e65147 5911
0bb027fd
RR		 5912 case 'x':
5913 func (stream, "0x%lx", val & 0xffffffffUL);
5914 break;
c19d1205
ZW		 5915
5916 default:
5917 abort ();
5918 }
5919 }
5920 break;
5921
32a94698
NC		 5922 case 'L':
5923 /* PR binutils/12534
5924 If we have a PC relative offset in an LDRD or STRD
5925 instructions then display the decoded address. */
5926 if (((given >> 16) & 0xf) == 0xf)
5927 {
5928 bfd_vma offset = (given & 0xff) * 4;
5929
5930 if ((given & (1 << 23)) == 0)
5931 offset = - offset;
5932 func (stream, "\t; ");
5933 info->print_address_func ((pc & ~3) + 4 + offset, info);
5934 }
5935 break;
5936
c19d1205
ZW		 5937 default:
5938 abort ();
5939 }
5940 }
05413229
NC		 5941
5942 if (value_in_comment > 32 || value_in_comment < -16)
5943 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5944
5945 if (is_unpredictable)
5946 func (stream, UNPREDICTABLE_INSTRUCTION);
5947
4a5329c6 5948 return;
c19d1205 5949 }
252b5132 5950
58efb6c0 5951 /* No match. */
252b5132
RH		 5952 abort ();
5953}
5954
e821645d
DJ		 5955/* Print data bytes on INFO->STREAM. */
5956
5957static void
fe56b6ce
NC		 5958print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5959 struct disassemble_info *info,
e821645d
DJ		 5960 long given)
5961{
5962 switch (info->bytes_per_chunk)
5963 {
5964 case 1:
5965 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5966 break;
5967 case 2:
5968 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5969 break;
5970 case 4:
5971 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5972 break;
5973 default:
5974 abort ();
5975 }
5976}
5977
22a398e1 5978/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5979 being displayed in symbol relative addresses.
5980
5981 Also disallow private symbol, with __tagsym$$ prefix,
5982 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5983
5984bfd_boolean
5985arm_symbol_is_valid (asymbol * sym,
5986 struct disassemble_info * info ATTRIBUTE_UNUSED)
5987{
5988 const char * name;
43e65147 5989
22a398e1
NC		 5990 if (sym == NULL)
5991 return FALSE;
5992
5993 name = bfd_asymbol_name (sym);
5994
d8282f0e 5995 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5996}
5997
58efb6c0 5998/* Parse an individual disassembler option. */
baf0cc5e 5999
a3d9c82d 6000void
4a5329c6 6001parse_arm_disassembler_option (char *option)
dd92f639 6002{
01c7f630 6003 if (option == NULL)
dd92f639 6004 return;
b34976b6 6005
0112cd26 6006 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 6007 {
58efb6c0 6008 int i;
b34976b6 6009
01c7f630 6010 option += 10;
58efb6c0
NC		 6011
6012 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 6013 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 6014 {
6015 regname_selected = i;
6016 break;
6017 }
b34976b6 6018
58efb6c0 6019 if (i < 0)
31e0f3cd 6020 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6021 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 6022 }
0112cd26 6023 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 6024 force_thumb = 1;
0112cd26 6025 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 6026 force_thumb = 0;
dd92f639 6027 else
31e0f3cd 6028 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6029 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 6030
dd92f639
NC		 6031 return;
6032}
6033
31e0f3cd
NC		 6034/* Parse the string of disassembler options, spliting it at whitespaces
6035 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 6036
01c7f630 6037static void
4a5329c6 6038parse_disassembler_options (char *options)
01c7f630 6039{
01c7f630
NC		 6040 if (options == NULL)
6041 return;
6042
31e0f3cd 6043 while (*options)
01c7f630 6044 {
31e0f3cd
NC		 6045 parse_arm_disassembler_option (options);
6046
6047 /* Skip forward to next seperator. */
6048 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
6049 ++ options;
6050 /* Skip forward past seperators. */
6051 while (ISSPACE (*options) || (*options == ','))
43e65147 6052 ++ options;
01c7f630 6053 }
01c7f630
NC		 6054}
6055
5bc5ae88
RL		 6056static bfd_boolean
6057mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6058 enum map_type *map_symbol);
6059
c22aaad1
PB		 6060/* Search back through the insn stream to determine if this instruction is
6061 conditionally executed. */
fe56b6ce 6062
c22aaad1 6063static void
fe56b6ce
NC		 6064find_ifthen_state (bfd_vma pc,
6065 struct disassemble_info *info,
c22aaad1
PB		 6066 bfd_boolean little)
6067{
6068 unsigned char b[2];
6069 unsigned int insn;
6070 int status;
6071 /* COUNT is twice the number of instructions seen. It will be odd if we
6072 just crossed an instruction boundary. */
6073 int count;
6074 int it_count;
6075 unsigned int seen_it;
6076 bfd_vma addr;
6077
6078 ifthen_address = pc;
6079 ifthen_state = 0;
6080
6081 addr = pc;
6082 count = 1;
6083 it_count = 0;
6084 seen_it = 0;
6085 /* Scan backwards looking for IT instructions, keeping track of where
6086 instruction boundaries are. We don't know if something is actually an
6087 IT instruction until we find a definite instruction boundary. */
6088 for (;;)
6089 {
fe56b6ce 6090 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6091 {
6092 /* A symbol must be on an instruction boundary, and will not
6093 be within an IT block. */
6094 if (seen_it && (count & 1))
6095 break;
6096
6097 return;
6098 }
6099 addr -= 2;
fe56b6ce 6100 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6101 if (status)
6102 return;
6103
6104 if (little)
6105 insn = (b[0]) | (b[1] << 8);
6106 else
6107 insn = (b[1]) | (b[0] << 8);
6108 if (seen_it)
6109 {
6110 if ((insn & 0xf800) < 0xe800)
6111 {
6112 /* Addr + 2 is an instruction boundary. See if this matches
6113 the expected boundary based on the position of the last
6114 IT candidate. */
6115 if (count & 1)
6116 break;
6117 seen_it = 0;
6118 }
6119 }
6120 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6121 {
5bc5ae88
RL		 6122 enum map_type type = MAP_ARM;
6123 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6124
6125 if (!found || (found && type == MAP_THUMB))
6126 {
6127 /* This could be an IT instruction. */
6128 seen_it = insn;
6129 it_count = count >> 1;
6130 }
c22aaad1
PB		 6131 }
6132 if ((insn & 0xf800) >= 0xe800)
6133 count++;
6134 else
6135 count = (count + 2) | 1;
6136 /* IT blocks contain at most 4 instructions. */
6137 if (count >= 8 && !seen_it)
6138 return;
6139 }
6140 /* We found an IT instruction. */
6141 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6142 if ((ifthen_state & 0xf) == 0)
6143 ifthen_state = 0;
6144}
6145
b0e28b39
DJ		 6146/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6147 mapping symbol. */
6148
6149static int
6150is_mapping_symbol (struct disassemble_info *info, int n,
6151 enum map_type *map_type)
6152{
6153 const char *name;
6154
6155 name = bfd_asymbol_name (info->symtab[n]);
6156 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6157 && (name[2] == 0 || name[2] == '.'))
6158 {
6159 *map_type = ((name[1] == 'a') ? MAP_ARM
6160 : (name[1] == 't') ? MAP_THUMB
6161 : MAP_DATA);
6162 return TRUE;
6163 }
6164
6165 return FALSE;
6166}
6167
6168/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6169 Returns nonzero if *MAP_TYPE was set. */
6170
6171static int
6172get_map_sym_type (struct disassemble_info *info,
6173 int n,
6174 enum map_type *map_type)
6175{
6176 /* If the symbol is in a different section, ignore it. */
6177 if (info->section != NULL && info->section != info->symtab[n]->section)
6178 return FALSE;
6179
6180 return is_mapping_symbol (info, n, map_type);
6181}
6182
6183/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6184 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6185
6186static int
fe56b6ce
NC		 6187get_sym_code_type (struct disassemble_info *info,
6188 int n,
e821645d 6189 enum map_type *map_type)
2087ad84
PB		 6190{
6191 elf_symbol_type *es;
6192 unsigned int type;
b0e28b39
DJ		 6193
6194 /* If the symbol is in a different section, ignore it. */
6195 if (info->section != NULL && info->section != info->symtab[n]->section)
6196 return FALSE;
2087ad84 6197
e821645d 6198 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6199 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6200
6201 /* If the symbol has function type then use that. */
34e77a92 6202 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6203 {
35fc36a8
RS		 6204 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6205 *map_type = MAP_THUMB;
6206 else
6207 *map_type = MAP_ARM;
2087ad84
PB		 6208 return TRUE;
6209 }
6210
2087ad84
PB		 6211 return FALSE;
6212}
6213
5bc5ae88
RL		 6214/* Search the mapping symbol state for instruction at pc. This is only
6215 applicable for elf target.
6216
6217 There is an assumption Here, info->private_data contains the correct AND
6218 up-to-date information about current scan process. The information will be
6219 used to speed this search process.
6220
6221 Return TRUE if the mapping state can be determined, and map_symbol
6222 will be updated accordingly. Otherwise, return FALSE. */
6223
6224static bfd_boolean
6225mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6226 enum map_type *map_symbol)
6227{
6228 bfd_vma addr;
6229 int n, start = 0;
6230 bfd_boolean found = FALSE;
6231 enum map_type type = MAP_ARM;
6232 struct arm_private_data *private_data;
6233
6234 if (info->private_data == NULL || info->symtab_size == 0
6235 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6236 return FALSE;
6237
6238 private_data = info->private_data;
6239 if (pc == 0)
6240 start = 0;
6241 else
6242 start = private_data->last_mapping_sym;
6243
6244 start = (start == -1)? 0 : start;
6245 addr = bfd_asymbol_value (info->symtab[start]);
6246
6247 if (pc >= addr)
6248 {
6249 if (get_map_sym_type (info, start, &type))
6250 found = TRUE;
6251 }
6252 else
6253 {
6254 for (n = start - 1; n >= 0; n--)
6255 {
6256 if (get_map_sym_type (info, n, &type))
6257 {
6258 found = TRUE;
6259 break;
6260 }
6261 }
6262 }
6263
6264 /* No mapping symbols were found. A leading $d may be
6265 omitted for sections which start with data; but for
6266 compatibility with legacy and stripped binaries, only
6267 assume the leading $d if there is at least one mapping
6268 symbol in the file. */
6269 if (!found && private_data->has_mapping_symbols == 1)
6270 {
6271 type = MAP_DATA;
6272 found = TRUE;
6273 }
6274
6275 *map_symbol = type;
6276 return found;
6277}
6278
0313a2b8
NC		 6279/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6280 of the supplied arm_feature_set structure with bitmasks indicating
6281 the support base architectures and coprocessor extensions.
6282
6283 FIXME: This could more efficiently implemented as a constant array,
6284 although it would also be less robust. */
6285
6286static void
6287select_arm_features (unsigned long mach,
6288 arm_feature_set * features)
6289{
1af1dd51
MW		 6290#undef ARM_SET_FEATURES
6291#define ARM_SET_FEATURES(FSET) \
6292 { \
6293 const arm_feature_set fset = FSET; \
6294 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6295 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6296 }
823d2571 6297
0313a2b8
NC		 6298 switch (mach)
6299 {
1af1dd51
MW		 6300 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6301 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6302 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6303 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6304 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6305 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6306 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6307 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6308 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6309 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6310 case bfd_mach_arm_ep9312:
6311 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6312 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6313 break;
6314 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6315 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6316 /* If the machine type is unknown allow all
6317 architecture types and all extensions. */
1af1dd51 6318 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6319 default:
6320 abort ();
6321 }
1af1dd51
MW		 6322
6323#undef ARM_SET_FEATURES
0313a2b8
NC		 6324}
6325
6326
58efb6c0
NC		 6327/* NOTE: There are no checks in these routines that
6328 the relevant number of data bytes exist. */
baf0cc5e 6329
58efb6c0 6330static int
4a5329c6 6331print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6332{
c19d1205
ZW		 6333 unsigned char b[4];
6334 long given;
6335 int status;
e821645d 6336 int is_thumb = FALSE;
b0e28b39 6337 int is_data = FALSE;
bd2e2557 6338 int little_code;
e821645d 6339 unsigned int size = 4;
4a5329c6 6340 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6341 bfd_boolean found = FALSE;
b0e28b39 6342 struct arm_private_data *private_data;
58efb6c0 6343
dd92f639
NC		 6344 if (info->disassembler_options)
6345 {
6346 parse_disassembler_options (info->disassembler_options);
b34976b6 6347
58efb6c0 6348 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6349 info->disassembler_options = NULL;
6350 }
b34976b6 6351
0313a2b8
NC		 6352 /* PR 10288: Control which instructions will be disassembled. */
6353 if (info->private_data == NULL)
6354 {
b0e28b39 6355 static struct arm_private_data private;
0313a2b8
NC		 6356
6357 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6358 /* If the user did not use the -m command line switch then default to
6359 disassembling all types of ARM instruction.
43e65147 6360
0313a2b8
NC		 6361 The info->mach value has to be ignored as this will be based on
6362 the default archictecture for the target and/or hints in the notes
6363 section, but it will never be greater than the current largest arm
6364 machine value (iWMMXt2), which is only equivalent to the V5TE
6365 architecture. ARM architectures have advanced beyond the machine
6366 value encoding, and these newer architectures would be ignored if
6367 the machine value was used.
6368
6369 Ie the -m switch is used to restrict which instructions will be
6370 disassembled. If it is necessary to use the -m switch to tell
6371 objdump that an ARM binary is being disassembled, eg because the
6372 input is a raw binary file, but it is also desired to disassemble
6373 all ARM instructions then use "-marm". This will select the
6374 "unknown" arm architecture which is compatible with any ARM
6375 instruction. */
6376 info->mach = bfd_mach_arm_unknown;
6377
6378 /* Compute the architecture bitmask from the machine number.
6379 Note: This assumes that the machine number will not change
6380 during disassembly.... */
b0e28b39 6381 select_arm_features (info->mach, & private.features);
0313a2b8 6382
b0e28b39 6383 private.has_mapping_symbols = -1;
1fbaefec
PB		 6384 private.last_mapping_sym = -1;
6385 private.last_mapping_addr = 0;
b0e28b39
DJ		 6386
6387 info->private_data = & private;
0313a2b8 6388 }
b0e28b39
DJ		 6389
6390 private_data = info->private_data;
6391
bd2e2557
SS		 6392 /* Decide if our code is going to be little-endian, despite what the
6393 function argument might say. */
6394 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6395
b0e28b39
DJ		 6396 /* For ELF, consult the symbol table to determine what kind of code
6397 or data we have. */
8977d4b2 6398 if (info->symtab_size != 0
e821645d
DJ		 6399 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6400 {
6401 bfd_vma addr;
b0e28b39 6402 int n, start;
e821645d 6403 int last_sym = -1;
b0e28b39 6404 enum map_type type = MAP_ARM;
e821645d 6405
e821645d
DJ		 6406 /* Start scanning at the start of the function, or wherever
6407 we finished last time. */
6750a3a7
NC		 6408 /* PR 14006. When the address is 0 we are either at the start of the
6409 very first function, or else the first function in a new, unlinked
6410 executable section (eg because uf -ffunction-sections). Either way
6411 start scanning from the beginning of the symbol table, not where we
6412 left off last time. */
6413 if (pc == 0)
6414 start = 0;
6415 else
6416 {
6417 start = info->symtab_pos + 1;
6418 if (start < private_data->last_mapping_sym)
6419 start = private_data->last_mapping_sym;
6420 }
b0e28b39 6421 found = FALSE;
e821645d 6422
b0e28b39
DJ		 6423 /* First, look for mapping symbols. */
6424 if (private_data->has_mapping_symbols != 0)
e821645d 6425 {
b0e28b39
DJ		 6426 /* Scan up to the location being disassembled. */
6427 for (n = start; n < info->symtab_size; n++)
6428 {
6429 addr = bfd_asymbol_value (info->symtab[n]);
6430 if (addr > pc)
6431 break;
6432 if (get_map_sym_type (info, n, &type))
6433 {
6434 last_sym = n;
6435 found = TRUE;
6436 }
6437 }
6438
6439 if (!found)
6440 {
6441 /* No mapping symbol found at this address. Look backwards
cc643b88 6442 for a preceding one. */
b0e28b39
DJ		 6443 for (n = start - 1; n >= 0; n--)
6444 {
6445 if (get_map_sym_type (info, n, &type))
6446 {
6447 last_sym = n;
6448 found = TRUE;
6449 break;
6450 }
6451 }
6452 }
6453
6454 if (found)
6455 private_data->has_mapping_symbols = 1;
6456
6457 /* No mapping symbols were found. A leading $d may be
6458 omitted for sections which start with data; but for
6459 compatibility with legacy and stripped binaries, only
6460 assume the leading $d if there is at least one mapping
6461 symbol in the file. */
6462 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6463 {
b0e28b39
DJ		 6464 /* Look for mapping symbols, in any section. */
6465 for (n = 0; n < info->symtab_size; n++)
6466 if (is_mapping_symbol (info, n, &type))
6467 {
6468 private_data->has_mapping_symbols = 1;
6469 break;
6470 }
6471 if (private_data->has_mapping_symbols == -1)
6472 private_data->has_mapping_symbols = 0;
6473 }
6474
6475 if (!found && private_data->has_mapping_symbols == 1)
6476 {
6477 type = MAP_DATA;
e821645d
DJ		 6478 found = TRUE;
6479 }
6480 }
6481
b0e28b39
DJ		 6482 /* Next search for function symbols to separate ARM from Thumb
6483 in binaries without mapping symbols. */
e821645d
DJ		 6484 if (!found)
6485 {
b0e28b39
DJ		 6486 /* Scan up to the location being disassembled. */
6487 for (n = start; n < info->symtab_size; n++)
e821645d 6488 {
b0e28b39
DJ		 6489 addr = bfd_asymbol_value (info->symtab[n]);
6490 if (addr > pc)
6491 break;
6492 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6493 {
6494 last_sym = n;
6495 found = TRUE;
b0e28b39
DJ		 6496 }
6497 }
6498
6499 if (!found)
6500 {
6501 /* No mapping symbol found at this address. Look backwards
cc643b88 6502 for a preceding one. */
b0e28b39
DJ		 6503 for (n = start - 1; n >= 0; n--)
6504 {
6505 if (get_sym_code_type (info, n, &type))
6506 {
6507 last_sym = n;
6508 found = TRUE;
6509 break;
6510 }
e821645d
DJ		 6511 }
6512 }
6513 }
6514
1fbaefec
PB		 6515 private_data->last_mapping_sym = last_sym;
6516 private_data->last_type = type;
6517 is_thumb = (private_data->last_type == MAP_THUMB);
6518 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6519
e821645d
DJ		 6520 /* Look a little bit ahead to see if we should print out
6521 two or four bytes of data. If there's a symbol,
6522 mapping or otherwise, after two bytes then don't
6523 print more. */
6524 if (is_data)
6525 {
6526 size = 4 - (pc & 3);
6527 for (n = last_sym + 1; n < info->symtab_size; n++)
6528 {
6529 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6530 if (addr > pc
6531 && (info->section == NULL
6532 || info->section == info->symtab[n]->section))
e821645d
DJ		 6533 {
6534 if (addr - pc < size)
6535 size = addr - pc;
6536 break;
6537 }
6538 }
6539 /* If the next symbol is after three bytes, we need to
6540 print only part of the data, so that we can use either
6541 .byte or .short. */
6542 if (size == 3)
6543 size = (pc & 1) ? 1 : 2;
6544 }
6545 }
6546
6547 if (info->symbols != NULL)
252b5132 6548 {
5876e06d
NC		 6549 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6550 {
2f0ca46a 6551 coff_symbol_type * cs;
b34976b6 6552
5876e06d
NC		 6553 cs = coffsymbol (*info->symbols);
6554 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6555 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6556 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6557 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6558 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6559 }
e821645d
DJ		 6560 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6561 && !found)
5876e06d 6562 {
2087ad84
PB		 6563 /* If no mapping symbol has been found then fall back to the type
6564 of the function symbol. */
e821645d
DJ		 6565 elf_symbol_type * es;
6566 unsigned int type;
2087ad84 6567
e821645d
DJ		 6568 es = *(elf_symbol_type **)(info->symbols);
6569 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6570
35fc36a8
RS		 6571 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6572 == ST_BRANCH_TO_THUMB)
6573 || type == STT_ARM_16BIT);
5876e06d 6574 }
e49d43ff
TG		 6575 else if (bfd_asymbol_flavour (*info->symbols)
6576 == bfd_target_mach_o_flavour)
6577 {
6578 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6579
6580 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6581 }
5876e06d 6582 }
b34976b6 6583
e821645d
DJ		 6584 if (force_thumb)
6585 is_thumb = TRUE;
6586
b8f9ee44
CL		 6587 if (is_data)
6588 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6589 else
6590 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6591
c19d1205 6592 info->bytes_per_line = 4;
252b5132 6593
1316c8b3
NC		 6594 /* PR 10263: Disassemble data if requested to do so by the user. */
6595 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6596 {
6597 int i;
6598
1316c8b3 6599 /* Size was already set above. */
e821645d
DJ		 6600 info->bytes_per_chunk = size;
6601 printer = print_insn_data;
6602
fe56b6ce 6603 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6604 given = 0;
6605 if (little)
6606 for (i = size - 1; i >= 0; i--)
6607 given = b[i] | (given << 8);
6608 else
6609 for (i = 0; i < (int) size; i++)
6610 given = b[i] | (given << 8);
6611 }
6612 else if (!is_thumb)
252b5132 6613 {
c19d1205
ZW		 6614 /* In ARM mode endianness is a straightforward issue: the instruction
6615 is four bytes long and is either ordered 0123 or 3210. */
6616 printer = print_insn_arm;
6617 info->bytes_per_chunk = 4;
4a5329c6 6618 size = 4;
c19d1205 6619
0313a2b8 6620 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6621 if (little_code)
c19d1205
ZW		 6622 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6623 else
6624 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6625 }
58efb6c0 6626 else
252b5132 6627 {
c19d1205
ZW		 6628 /* In Thumb mode we have the additional wrinkle of two
6629 instruction lengths. Fortunately, the bits that determine
6630 the length of the current instruction are always to be found
6631 in the first two bytes. */
4a5329c6 6632 printer = print_insn_thumb16;
c19d1205 6633 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6634 size = 2;
6635
fe56b6ce 6636 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6637 if (little_code)
9a2ff3f5
AM		 6638 given = (b[0]) | (b[1] << 8);
6639 else
6640 given = (b[1]) | (b[0] << 8);
6641
c19d1205 6642 if (!status)
252b5132 6643 {
c19d1205
ZW		 6644 /* These bit patterns signal a four-byte Thumb
6645 instruction. */
6646 if ((given & 0xF800) == 0xF800
6647 || (given & 0xF800) == 0xF000
6648 || (given & 0xF800) == 0xE800)
252b5132 6649 {
0313a2b8 6650 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6651 if (little_code)
c19d1205 6652 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6653 else
c19d1205
ZW		 6654 given = (b[1]) | (b[0] << 8) | (given << 16);
6655
6656 printer = print_insn_thumb32;
4a5329c6 6657 size = 4;
252b5132 6658 }
252b5132 6659 }
c22aaad1
PB		 6660
6661 if (ifthen_address != pc)
0313a2b8 6662 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6663
6664 if (ifthen_state)
6665 {
6666 if ((ifthen_state & 0xf) == 0x8)
6667 ifthen_next_state = 0;
6668 else
6669 ifthen_next_state = (ifthen_state & 0xe0)
6670 | ((ifthen_state & 0xf) << 1);
6671 }
252b5132 6672 }
b34976b6 6673
c19d1205
ZW		 6674 if (status)
6675 {
6676 info->memory_error_func (status, pc, info);
6677 return -1;
6678 }
6a56ec7e
NC		 6679 if (info->flags & INSN_HAS_RELOC)
6680 /* If the instruction has a reloc associated with it, then
6681 the offset field in the instruction will actually be the
6682 addend for the reloc. (We are using REL type relocs).
6683 In such cases, we can ignore the pc when computing
6684 addresses, since the addend is not currently pc-relative. */
6685 pc = 0;
b34976b6 6686
4a5329c6 6687 printer (pc, info, given);
c22aaad1
PB		 6688
6689 if (is_thumb)
6690 {
6691 ifthen_state = ifthen_next_state;
6692 ifthen_address += size;
6693 }
4a5329c6 6694 return size;
252b5132
RH		 6695}
6696
6697int
4a5329c6 6698print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6699{
bd2e2557
SS		 6700 /* Detect BE8-ness and record it in the disassembler info. */
6701 if (info->flavour == bfd_target_elf_flavour
6702 && info->section != NULL
6703 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6704 info->endian_code = BFD_ENDIAN_LITTLE;
6705
b34976b6 6706 return print_insn (pc, info, FALSE);
58efb6c0 6707}
01c7f630 6708
58efb6c0 6709int
4a5329c6 6710print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6711{
b34976b6 6712 return print_insn (pc, info, TRUE);
58efb6c0 6713}
252b5132 6714
58efb6c0 6715void
4a5329c6 6716print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6717{
6718 int i;
252b5132 6719
58efb6c0
NC		 6720 fprintf (stream, _("\n\
6721The following ARM specific disassembler options are supported for use with\n\
6722the -M switch:\n"));
b34976b6 6723
58efb6c0
NC		 6724 for (i = NUM_ARM_REGNAMES; i--;)
6725 fprintf (stream, " reg-names-%s %*c%s\n",
6726 regnames[i].name,
d5b2f4d6 6727 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6728 regnames[i].description);
6729
6730 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6731 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6732}
GDB Binutils - Deliverables
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