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C99 binutils configury
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
250d07de 2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
4a5329c6 408 %A print address for ldc/stc/ldf/stf instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
4a5329c6 411 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
4a5329c6
ZW		 414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
418
33399f07 419 %<bitfield>c print as a condition code (for vsel)
4a5329c6 420 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 423 %<bitfield>d print the bitfield in decimal
16980d0b 424 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
4a5329c6
ZW		 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
c28eeff2 434 %<bitfield>V print as a NEON D or Q register
6f1c2142 435 %<bitfield>E print a quarter-float immediate value
4a5329c6 436
16980d0b 437 %y<code> print a single precision VFP reg.
2fbad815 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 439 %z<code> print a double precision VFP reg
2fbad815 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 441
16980d0b
JB		 442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
43e65147 445
2fbad815 446 %L print as an iWMMXt N/M width field.
4a5329c6 447 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 448 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 449 versions.
450 %i print 5-bit immediate in bits 8,3..0
451 (print "32" when 0)
fe56b6ce 452 %r print register offset address for wldt/wstr instruction. */
2fbad815 453
21d799b5 454enum opcode_sentinel_enum
05413229
NC		 455{
456 SENTINEL_IWMMXT_START = 1,
457 SENTINEL_IWMMXT_END,
458 SENTINEL_GENERIC_START
459} opcode_sentinels;
460
aefd8a40 461#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 462#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
463#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 464#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 465
8f06b2d8 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 467
4934a27c
MM		 468/* print_insn_cde recognizes the following format control codes:
469
470 %% %
471
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
483
484/* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488static const struct cdeopcode32 cde_opcodes[] =
489{
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee000000, 0xefc00840,
493 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee000040, 0xefc00840,
496 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee400000, 0xefc00840,
500 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee400040, 0xefc00840,
503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
504
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xee800000, 0xef800840,
507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xee800040, 0xef800840,
510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
511
5aae9ae9
MM		 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec200000, 0xeeb00840,
514 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec200040, 0xeeb00840,
517 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec300000, 0xeeb00840,
521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec300040, 0xeeb00840,
524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
525
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527 0xec800000, 0xee800840,
528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530 0xec800040, 0xee800840,
531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
532
4934a27c
MM		 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535};
536
6b0dd094 537static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 538{
2fbad815 539 /* XScale instructions. */
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 541 0x0e200010, 0x0fff0ff0,
542 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 544 0x0e280010, 0x0fff0ff0,
545 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 552
2fbad815 553 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 707 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 708 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 709
fe56b6ce 710 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 797
efd6b359
AV		 798 /* Armv8.1-M Mainline instructions. */
799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
16a1fa25 804 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
fe56b6ce 810 /* Register load/store. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 847
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 856
fe56b6ce 857 /* Data transfer between ARM and NEON registers. */
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 874 /* Half-precision conversion instructions. */
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 883
fe56b6ce 884 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
2da2eaf4 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
890 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
2da2eaf4 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
2da2eaf4 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
908 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
910 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
2da2eaf4 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
2da2eaf4 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
2da2eaf4 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1043
1044 /* Cirrus coprocessor instructions. */
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1048 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1050 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1052 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1054 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1056 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1058 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1060 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1062 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1064 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1066 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1068 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1070 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1072 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1074 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1076 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1098 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1122 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1150 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1152 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1162 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1164 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1166 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1168 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1170 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1182 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1184 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1186 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1188 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1206 0x0e000600, 0x0ff00f10,
1207 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1209 0x0e100600, 0x0ff00f10,
1210 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1212 0x0e200600, 0x0ff00f10,
1213 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1215 0x0e300600, 0x0ff00f10,
1216 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1217
62f3b8c8 1218 /* VFP Fused multiply add instructions. */
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1235
33399f07 1236 /* FP v5. */
6b0dd094 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1245 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1247 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1249 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1251 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1253 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1255 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1257 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1259 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1261
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1284
aab2c27d
MM		 1285 /* BFloat16 instructions. */
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
c604a79a 1289 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1290 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1292 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1294
dec41383 1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1312
b0c11777
RL		 1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1370 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1374 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1376 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1378 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1380 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1382 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1384 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
49e8a725 1387 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1388 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
6b0dd094 1391 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1392};
1393
33593eaf
MM		 1394/* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1396
1397static const struct sopcode32 generic_coprocessor_opcodes[] =
1398{
1399 /* Generic coprocessor instructions. */
1400 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403 0x0c500000, 0x0ff00000,
1404 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406 0x0e000000, 0x0f000010,
1407 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409 0x0e10f010, 0x0f10f010,
1410 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412 0x0e100010, 0x0f100010,
1413 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415 0x0e000010, 0x0f100010,
1416 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1421
1422 /* V6 coprocessor instructions. */
1423 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424 0xfc500000, 0xfff00000,
1425 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427 0xfc400000, 0xfff00000,
1428 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1429
1430 /* V5 coprocessor instructions. */
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436 0xfe000000, 0xff000010,
1437 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfe000010, 0xff100010,
1440 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442 0xfe100010, 0xff100010,
1443 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1444
1445 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446};
1447
16980d0b
JB		 1448/* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1451
1452/* print_insn_neon recognizes the following format control codes:
1453
1454 %% %
1455
c22aaad1 1456 %c print condition code
e2efe87d
MGD		 1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1462 %D print scalar
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1465
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
43e65147 1475
16980d0b
JB		 1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1478 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1479
1480static const struct opcode32 neon_opcodes[] =
1481{
fe56b6ce 1482 /* Extract. */
823d2571
TG		 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2b00840, 0xffb00850,
1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2b00000, 0xffb00810,
1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1489
9743db03
AV		 1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1503
fe56b6ce 1504 /* Move data element to all lanes. */
823d2571
TG		 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1511
fe56b6ce 1512 /* Table lookup. */
823d2571
TG		 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
8e79c3df 1518 /* Half-precision conversions. */
823d2571
TG		 1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1523
1524 /* NEON fused multiply add instructions. */
823d2571 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1533
aab2c27d
MM		 1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1547
616ce08e
MM		 1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1561
fe56b6ce 1562 /* Two registers, miscellaneous. */
823d2571
TG		 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3b20300, 0xffb30fd0,
1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1655 0xf3bb0600, 0xffbf0e10,
823d2571 1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1660
fe56b6ce 1661 /* Three registers of the same length. */
823d2571
TG		 1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1853
fe56b6ce 1854 /* One register and an immediate value. */
823d2571
TG		 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1881
fe56b6ce 1882 /* Two registers and a shift amount. */
823d2571
TG		 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2880950, 0xfeb80fd0,
1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2900950, 0xfeb00fd0,
1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2a00950, 0xfea00fd0,
1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2a00e10, 0xfea00e90,
2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004 0xf2a00c10, 0xfea00e90,
2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 2006
fe56b6ce 2007 /* Three registers of different lengths. */
823d2571
TG		 2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2060
fe56b6ce 2061 /* Two registers and a scalar. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133 },
16980d0b 2134
fe56b6ce 2135 /* Element and structure load/store. */
823d2571
TG		 2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2176};
2177
73cd51e5
AV		 2178/* mve opcode table. */
2179
2180/* print_insn_mve recognizes the following format control codes:
2181
2182 %% %
2183
ef1576a1
AV		 2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2185 vstr[bhwd]
9743db03 2186 %c print condition code
aef6d006
AV		 2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2189 %i print MVE predicate(s) for vpt and vpst
23d00a41 2190 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2191 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2192 %m print rounding mode for vcvt and vrint
143275ea 2193 %n print vector comparison code for predicated instruction
bf0b396d 2194 %s print size for various vcvt instructions
143275ea
AV		 2195 %v print vector predicate for instruction in predicated
2196 block
ef1576a1 2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
14925797 2202 %T print bottom ('b') or top ('t') of source register
d3b63143 2203 %X print exchange field in vmla* instructions
04d54ace 2204
9743db03 2205 %<bitfield>r print as an ARM register
04d54ace 2206 %<bitfield>d print the bitfield in decimal
d3b63143 2207 %<bitfield>A print accumulate or not
e39c1607
SD		 2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
143275ea 2210 %<bitfield>Q print as a MVE Q register
c507f10b 2211 %<bitfield>F print as a MVE S register
143275ea
AV		 2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2213 UNPREDICTABLE
23d00a41
SD		 2214
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2216 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2217 %<bitfield>I print carry flag or not
ef1576a1 2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2219 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2220 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2221 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2222 %<bitfield>o print rotate value for vcmul
1c8f2df8 2223 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2224 %<bitfield>x print the bitfield in hex.
1c8f2df8 2225 */
73cd51e5
AV		 2226
2227static const struct mopcode32 mve_opcodes[] =
2228{
143275ea
AV		 2229 /* MVE. */
2230
2da2eaf4 2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2232 MVE_VPST,
2233 0xfe310f4d, 0xffbf1fff,
2234 "vpst%i"
2235 },
2236
2237 /* Floating point VPT T1. */
2da2eaf4 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2239 MVE_VPT_FP_T1,
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T2,
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248 /* Vector VPT T1. */
2da2eaf4 2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2250 MVE_VPT_VEC_T1,
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T2,
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T3,
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T4,
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T5,
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T6,
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
c507f10b 2279 /* Vector VBIC immediate. */
2da2eaf4 2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2281 MVE_VBIC_IMM,
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285 /* Vector VBIC register. */
2da2eaf4 2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2287 MVE_VBIC_REG,
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
66dcaa5d 2291 /* Vector VABAV. */
2da2eaf4 2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2293 MVE_VABAV,
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297 /* Vector VABD floating point. */
2da2eaf4 2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2299 MVE_VABD_FP,
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303 /* Vector VABD. */
2da2eaf4 2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2305 MVE_VABD_VEC,
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309 /* Vector VABS floating point. */
2da2eaf4 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2311 MVE_VABS_FP,
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314 /* Vector VABS. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2316 MVE_VABS_VEC,
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320 /* Vector VADD floating point T1. */
2da2eaf4 2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2322 MVE_VADD_FP_T1,
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T2,
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2332 MVE_VADD_VEC_T1,
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T2,
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
d3b63143 2341 /* Vector VADDLV. */
2da2eaf4 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2343 MVE_VADDLV,
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347 /* Vector VADDV. */
2da2eaf4 2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2349 MVE_VADDV,
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
66dcaa5d 2353 /* Vector VADC. */
2da2eaf4 2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2355 MVE_VADC,
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
e523f101 2359 /* Vector VAND. */
2da2eaf4 2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2361 MVE_VAND,
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365 /* Vector VBRSR register. */
2da2eaf4 2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2367 MVE_VBRSR,
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
897b9bbc 2371 /* Vector VCADD floating point. */
2da2eaf4 2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2373 MVE_VCADD_FP,
2374 0xfc800840, 0xfea11f51,
2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2376
2377 /* Vector VCADD. */
2da2eaf4 2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2379 MVE_VCADD_VEC,
2380 0xfe000f00, 0xff810f51,
2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2382
e523f101 2383 /* Vector VCLS. */
2da2eaf4 2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2385 MVE_VCLS,
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389 /* Vector VCLZ. */
2da2eaf4 2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2391 MVE_VCLZ,
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
897b9bbc 2395 /* Vector VCMLA. */
2da2eaf4 2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2397 MVE_VCMLA_FP,
2398 0xfc200840, 0xfe211f51,
2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2400
143275ea 2401 /* Vector VCMP floating point T1. */
2da2eaf4 2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2403 MVE_VCMP_FP_T1,
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407 /* Vector VCMP floating point T2. */
2da2eaf4 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2409 MVE_VCMP_FP_T2,
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413 /* Vector VCMP T1. */
2da2eaf4 2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2415 MVE_VCMP_VEC_T1,
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T2,
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T3,
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T4,
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T5,
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T6,
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
9743db03 2444 /* Vector VDUP. */
2da2eaf4 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2446 MVE_VDUP,
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450 /* Vector VEOR. */
2da2eaf4 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2452 MVE_VEOR,
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456 /* Vector VFMA, vector * scalar. */
2da2eaf4 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2458 MVE_VFMA_FP_SCALAR,
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462 /* Vector VFMA floating point. */
2da2eaf4 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2464 MVE_VFMA_FP,
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468 /* Vector VFMS floating point. */
2da2eaf4 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2470 MVE_VFMS_FP,
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2476 MVE_VFMAS_FP_SCALAR,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480 /* Vector VHADD T1. */
2da2eaf4 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2482 MVE_VHADD_T1,
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486 /* Vector VHADD T2. */
2da2eaf4 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2488 MVE_VHADD_T2,
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492 /* Vector VHSUB T1. */
2da2eaf4 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2494 MVE_VHSUB_T1,
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498 /* Vector VHSUB T2. */
2da2eaf4 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2500 MVE_VHSUB_T2,
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
897b9bbc 2504 /* Vector VCMUL. */
2da2eaf4 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2506 MVE_VCMUL_FP,
2507 0xee300e00, 0xefb10f50,
2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2509
e523f101 2510 /* Vector VCTP. */
2da2eaf4 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2512 MVE_VCTP,
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2515
9743db03 2516 /* Vector VDUP. */
2da2eaf4 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2518 MVE_VDUP,
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522 /* Vector VRHADD. */
2da2eaf4 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2524 MVE_VRHADD,
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
bf0b396d 2528 /* Vector VCVT. */
2da2eaf4 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2530 MVE_VCVT_FP_FIX_VEC,
2531 0xef800c50, 0xef801cd1,
2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2533
2534 /* Vector VCVT. */
2da2eaf4 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2536 MVE_VCVT_BETWEEN_FP_INT,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2542 MVE_VCVT_FP_HALF_FP,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2548 MVE_VCVT_FP_HALF_FP,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552 /* Vector VCVT. */
2da2eaf4 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2554 MVE_VCVT_FROM_FP_TO_INT,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
1c8f2df8 2558 /* Vector VDDUP. */
2da2eaf4 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2560 MVE_VDDUP,
2561 0xee011f6e, 0xff811f7e,
2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2563
2564 /* Vector VDWDUP. */
2da2eaf4 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2566 MVE_VDWDUP,
2567 0xee011f60, 0xff811f70,
2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2569
897b9bbc 2570 /* Vector VHCADD. */
2da2eaf4 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2572 MVE_VHCADD,
2573 0xee000f00, 0xff810f51,
2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2575
1c8f2df8 2576 /* Vector VIWDUP. */
2da2eaf4 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2578 MVE_VIWDUP,
2579 0xee010f60, 0xff811f70,
2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2581
2582 /* Vector VIDUP. */
2da2eaf4 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2584 MVE_VIDUP,
2585 0xee010f6e, 0xff811f7e,
2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2587
04d54ace 2588 /* Vector VLD2. */
2da2eaf4 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2590 MVE_VLD2,
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594 /* Vector VLD4. */
2da2eaf4 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2596 MVE_VLD4,
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
ef1576a1 2600 /* Vector VLDRB gather load. */
2da2eaf4 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2602 MVE_VLDRB_GATHER_T1,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606 /* Vector VLDRH gather load. */
2da2eaf4 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2608 MVE_VLDRH_GATHER_T2,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612 /* Vector VLDRW gather load. */
2da2eaf4 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2614 MVE_VLDRW_GATHER_T3,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618 /* Vector VLDRD gather load. */
2da2eaf4 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2620 MVE_VLDRD_GATHER_T4,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624 /* Vector VLDRW gather load. */
2da2eaf4 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2626 MVE_VLDRW_GATHER_T5,
2627 0xfd101e00, 0xff111f00,
2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2629
2630 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2632 MVE_VLDRD_GATHER_T6,
2633 0xfd101f00, 0xff111f00,
2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2635
aef6d006 2636 /* Vector VLDRB. */
2da2eaf4 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2638 MVE_VLDRB_T1,
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642 /* Vector VLDRH. */
2da2eaf4 2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2644 MVE_VLDRH_T2,
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2650 MVE_VLDRB_T5,
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2656 MVE_VLDRH_T6,
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2662 MVE_VLDRW_T7,
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2665
56858bea 2666 /* Vector VMAX. */
2da2eaf4 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2668 MVE_VMAX,
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672 /* Vector VMAXA. */
2da2eaf4 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2674 MVE_VMAXA,
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678 /* Vector VMAXNM floating point. */
2da2eaf4 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2680 MVE_VMAXNM_FP,
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684 /* Vector VMAXNMA floating point. */
2da2eaf4 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2686 MVE_VMAXNMA_FP,
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690 /* Vector VMAXNMV floating point. */
2da2eaf4 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2692 MVE_VMAXNMV_FP,
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696 /* Vector VMAXNMAV floating point. */
2da2eaf4 2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2698 MVE_VMAXNMAV_FP,
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702 /* Vector VMAXV. */
2da2eaf4 2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2704 MVE_VMAXV,
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708 /* Vector VMAXAV. */
2da2eaf4 2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2710 MVE_VMAXAV,
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714 /* Vector VMIN. */
2da2eaf4 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2716 MVE_VMIN,
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720 /* Vector VMINA. */
2da2eaf4 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2722 MVE_VMINA,
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726 /* Vector VMINNM floating point. */
2da2eaf4 2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2728 MVE_VMINNM_FP,
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732 /* Vector VMINNMA floating point. */
2da2eaf4 2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2734 MVE_VMINNMA_FP,
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738 /* Vector VMINNMV floating point. */
2da2eaf4 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2740 MVE_VMINNMV_FP,
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744 /* Vector VMINNMAV floating point. */
2da2eaf4 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2746 MVE_VMINNMAV_FP,
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750 /* Vector VMINV. */
2da2eaf4 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2752 MVE_VMINV,
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756 /* Vector VMINAV. */
2da2eaf4 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2758 MVE_VMINAV,
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762 /* Vector VMLA. */
2da2eaf4 2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2764 MVE_VMLA,
2765 0xee010e40, 0xef811f70,
2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
d3b63143
AV		 2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2769 opcode aliasing. */
2da2eaf4 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2771 MVE_VMLALDAV,
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2782 MVE_VMLADAV_T1,
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2788 MVE_VMLADAV_T2,
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792 /* Vector VMLADAV T1 variant. */
2da2eaf4 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2794 MVE_VMLADAV_T1,
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798 /* Vector VMLADAV T2 variant. */
2da2eaf4 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2800 MVE_VMLADAV_T2,
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804 /* Vector VMLAS. */
2da2eaf4 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2806 MVE_VMLAS,
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2811 opcode aliasing. */
2da2eaf4 2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2813 MVE_VRMLSLDAVH,
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2818 opcdoe aliasing. */
2da2eaf4 2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2820 MVE_VMLSLDAV,
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2826 MVE_VMLSDAV_T1,
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2832 MVE_VMLSDAV_T2,
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
c507f10b 2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2838 MVE_VMOV_HFP_TO_GP,
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2844 MVE_VMOV_HFP_TO_GP,
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2847
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_GP_TO_VEC_LANE,
2850 0xee000b10, 0xff900f1f,
2851 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2852
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2857 MVE_VORR_IMM,
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
ed63aa17
AV		 2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2865 MVE_VQSHL_T2,
2866 0xef800750, 0xef801fd1,
2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2868
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2872
2da2eaf4 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2874 MVE_VQSHLU_T3,
2875 0xff800650, 0xff801fd1,
2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2877
2878 /* Vector VRSHR
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2882 MVE_VRSHR,
2883 0xef800250, 0xef801fd1,
2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2885
2886 /* Vector VSHL.
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2890 MVE_VSHL_T1,
2891 0xef800550, 0xff801fd1,
2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893
2894 /* Vector VSHR
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2898 MVE_VSHR,
2899 0xef800050, 0xef801fd1,
2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2901
2902 /* Vector VSLI
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2906 MVE_VSLI,
2907 0xff800550, 0xff801fd1,
2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2909
2910 /* Vector VSRI
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2914 MVE_VSRI,
2915 0xff800450, 0xff801fd1,
2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2917
c507f10b 2918 /* Vector VMOV immediate to vector,
ce760a76 2919 undefinded for cmode == 1111 */
2da2eaf4 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2921 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923 /* Vector VMOV immediate to vector,
2924 cmode == 1101 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2928
2929 /* Vector VMOV immediate to vector. */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2931 MVE_VMOV_IMM_TO_VEC,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2937 MVE_VMOV2_VEC_LANE_TO_GP,
2938 0xec000f00, 0xffb01ff0,
2939 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2940
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2943 MVE_VMOV2_VEC_LANE_TO_GP,
2944 0xec000f10, 0xffb01ff0,
2945 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2946
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2949 MVE_VMOV2_GP_TO_VEC_LANE,
2950 0xec100f00, 0xffb01ff0,
2951 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2952
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2955 MVE_VMOV2_GP_TO_VEC_LANE,
2956 0xec100f10, 0xffb01ff0,
2957 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2958
2959 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2961 MVE_VMOV_VEC_LANE_TO_GP,
2962 0xee100b10, 0xff100f1f,
2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2964
ed63aa17
AV		 2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2da2eaf4 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2968 MVE_VSHLL_T1,
2969 0xeea00f40, 0xefa00fd1,
2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2971
14925797 2972 /* Vector VMOVL long. */
2da2eaf4 2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2974 MVE_VMOVL,
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978 /* Vector VMOV and narrow. */
2da2eaf4 2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2980 MVE_VMOVN,
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
c507f10b 2984 /* Floating point move extract. */
2da2eaf4 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2986 MVE_VMOVX,
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
f49bb598 2990 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2992 MVE_VMUL_FP_T1,
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2998 MVE_VMUL_FP_T2,
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002 /* Vector VMUL T1 variant. */
2da2eaf4 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3004 MVE_VMUL_VEC_T1,
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008 /* Vector VMUL T2 variant. */
2da2eaf4 3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3010 MVE_VMUL_VEC_T2,
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014 /* Vector VMULH. */
2da2eaf4 3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3016 MVE_VMULH,
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VRMULH. */
2da2eaf4 3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3022 MVE_VRMULH,
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
14925797 3026 /* Vector VMULL integer. */
2da2eaf4 3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3028 MVE_VMULL_INT,
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032 /* Vector VMULL polynomial. */
2da2eaf4 3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3034 MVE_VMULL_POLY,
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
c507f10b 3038 /* Vector VMVN immediate to vector. */
2da2eaf4 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3040 MVE_VMVN_IMM,
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044 /* Vector VMVN register. */
2da2eaf4 3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3046 MVE_VMVN_REG,
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
f49bb598 3050 /* Vector VNEG floating point. */
2da2eaf4 3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3052 MVE_VNEG_FP,
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056 /* Vector VNEG. */
2da2eaf4 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3058 MVE_VNEG_VEC,
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
c507f10b 3062 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3064 MVE_VORN,
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VORR register. */
2da2eaf4 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3070 MVE_VORR_REG,
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
c4a23bf8
SP		 3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077 array. */
3078
2da2eaf4 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3080 MVE_VMOV_VEC_TO_VEC,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
14925797 3084 /* Vector VQDMULL T1 variant. */
2da2eaf4 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3086 MVE_VQDMULL_T1,
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
14b456f2 3090 /* Vector VPNOT. */
2da2eaf4 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3092 MVE_VPNOT,
3093 0xfe310f4d, 0xffffffff,
3094 "vpnot%v"},
3095
3096 /* Vector VPSEL. */
2da2eaf4 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3098 MVE_VPSEL,
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102 /* Vector VQABS. */
2da2eaf4 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3104 MVE_VQABS,
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108 /* Vector VQADD T1 variant. */
2da2eaf4 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3110 MVE_VQADD_T1,
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114 /* Vector VQADD T2 variant. */
2da2eaf4 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3116 MVE_VQADD_T2,
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
14925797 3120 /* Vector VQDMULL T2 variant. */
2da2eaf4 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3122 MVE_VQDMULL_T2,
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126 /* Vector VQMOVN. */
2da2eaf4 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3128 MVE_VQMOVN,
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132 /* Vector VQMOVUN. */
2da2eaf4 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3134 MVE_VQMOVUN,
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
d3b63143 3138 /* Vector VQDMLADH. */
2da2eaf4 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3140 MVE_VQDMLADH,
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144 /* Vector VQRDMLADH. */
2da2eaf4 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3146 MVE_VQRDMLADH,
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150 /* Vector VQDMLAH. */
2da2eaf4 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3152 MVE_VQDMLAH,
23d188c7 3153 0xee000e60, 0xff811f70,
d3b63143
AV		 3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156 /* Vector VQRDMLAH. */
2da2eaf4 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3158 MVE_VQRDMLAH,
23d188c7 3159 0xee000e40, 0xff811f70,
d3b63143
AV		 3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162 /* Vector VQDMLASH. */
2da2eaf4 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3164 MVE_VQDMLASH,
23d188c7 3165 0xee001e60, 0xff811f70,
d3b63143
AV		 3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168 /* Vector VQRDMLASH. */
2da2eaf4 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3170 MVE_VQRDMLASH,
23d188c7 3171 0xee001e40, 0xff811f70,
d3b63143
AV		 3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174 /* Vector VQDMLSDH. */
2da2eaf4 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3176 MVE_VQDMLSDH,
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180 /* Vector VQRDMLSDH. */
2da2eaf4 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3182 MVE_VQRDMLSDH,
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186 /* Vector VQDMULH T1 variant. */
2da2eaf4 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3188 MVE_VQDMULH_T1,
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3194 MVE_VQRDMULH_T2,
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198 /* Vector VQDMULH T3 variant. */
2da2eaf4 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3200 MVE_VQDMULH_T3,
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3206 MVE_VQRDMULH_T4,
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
14b456f2 3210 /* Vector VQNEG. */
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3212 MVE_VQNEG,
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
ed63aa17 3216 /* Vector VQRSHL T1 variant. */
2da2eaf4 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3218 MVE_VQRSHL_T1,
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222 /* Vector VQRSHL T2 variant. */
2da2eaf4 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3224 MVE_VQRSHL_T2,
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228 /* Vector VQRSHRN. */
2da2eaf4 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3230 MVE_VQRSHRN,
3231 0xee800f41, 0xefa00fd1,
3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3233
3234 /* Vector VQRSHRUN. */
2da2eaf4 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3236 MVE_VQRSHRUN,
3237 0xfe800fc0, 0xffa00fd1,
3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3239
3240 /* Vector VQSHL T1 Variant. */
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3242 MVE_VQSHL_T1,
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246 /* Vector VQSHL T4 Variant. */
2da2eaf4 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3248 MVE_VQSHL_T4,
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252 /* Vector VQSHRN. */
2da2eaf4 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3254 MVE_VQSHRN,
3255 0xee800f40, 0xefa00fd1,
3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3257
3258 /* Vector VQSHRUN. */
2da2eaf4 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3260 MVE_VQSHRUN,
3261 0xee800fc0, 0xffa00fd1,
3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3263
14b456f2 3264 /* Vector VQSUB T1 Variant. */
2da2eaf4 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3266 MVE_VQSUB_T1,
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270 /* Vector VQSUB T2 Variant. */
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3272 MVE_VQSUB_T2,
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276 /* Vector VREV16. */
2da2eaf4 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3278 MVE_VREV16,
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282 /* Vector VREV32. */
2da2eaf4 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3284 MVE_VREV32,
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288 /* Vector VREV64. */
2da2eaf4 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3290 MVE_VREV64,
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
bf0b396d 3294 /* Vector VRINT floating point. */
2da2eaf4 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3296 MVE_VRINT_FP,
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
d3b63143 3300 /* Vector VRMLALDAVH. */
2da2eaf4 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3302 MVE_VRMLALDAVH,
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306 /* Vector VRMLALDAVH. */
2da2eaf4 3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3308 MVE_VRMLALDAVH,
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
ed63aa17 3312 /* Vector VRSHL T1 Variant. */
2da2eaf4 3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3314 MVE_VRSHL_T1,
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318 /* Vector VRSHL T2 Variant. */
2da2eaf4 3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3320 MVE_VRSHL_T2,
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324 /* Vector VRSHRN. */
2da2eaf4 3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3326 MVE_VRSHRN,
3327 0xfe800fc1, 0xffa00fd1,
3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3329
66dcaa5d 3330 /* Vector VSBC. */
2da2eaf4 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3332 MVE_VSBC,
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
ed63aa17 3336 /* Vector VSHL T2 Variant. */
2da2eaf4 3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3338 MVE_VSHL_T2,
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342 /* Vector VSHL T3 Variant. */
2da2eaf4 3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3344 MVE_VSHL_T3,
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348 /* Vector VSHLC. */
2da2eaf4 3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3350 MVE_VSHLC,
3351 0xeea00fc0, 0xffa01ff0,
3352 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3353
3354 /* Vector VSHLL T2 Variant. */
2da2eaf4 3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3356 MVE_VSHLL_T2,
3357 0xee310e01, 0xefb30fd1,
3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3359
3360 /* Vector VSHRN. */
2da2eaf4 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3362 MVE_VSHRN,
3363 0xee800fc1, 0xffa00fd1,
3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3365
04d54ace 3366 /* Vector VST2 no writeback. */
2da2eaf4 3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3368 MVE_VST2,
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372 /* Vector VST2 writeback. */
2da2eaf4 3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3374 MVE_VST2,
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378 /* Vector VST4 no writeback. */
2da2eaf4 3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3380 MVE_VST4,
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384 /* Vector VST4 writeback. */
2da2eaf4 3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3386 MVE_VST4,
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
ef1576a1 3390 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3392 MVE_VSTRB_SCATTER_T1,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3398 MVE_VSTRH_SCATTER_T2,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3404 MVE_VSTRW_SCATTER_T3,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3410 MVE_VSTRD_SCATTER_T4,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3416 MVE_VSTRW_SCATTER_T5,
3417 0xfd001e00, 0xff111f00,
3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3419
3420 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3422 MVE_VSTRD_SCATTER_T6,
3423 0xfd001f00, 0xff111f00,
3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3425
aef6d006 3426 /* Vector VSTRB. */
2da2eaf4 3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3428 MVE_VSTRB_T1,
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432 /* Vector VSTRH. */
2da2eaf4 3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3434 MVE_VSTRH_T2,
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438 /* Vector VSTRB variant T5. */
2da2eaf4 3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3440 MVE_VSTRB_T5,
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444 /* Vector VSTRH variant T6. */
2da2eaf4 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3446 MVE_VSTRH_T6,
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450 /* Vector VSTRW variant T7. */
2da2eaf4 3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3452 MVE_VSTRW_T7,
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3455
66dcaa5d 3456 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3458 MVE_VSUB_FP_T1,
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3464 MVE_VSUB_FP_T2,
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468 /* Vector VSUB T1 variant. */
2da2eaf4 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3470 MVE_VSUB_VEC_T1,
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474 /* Vector VSUB T2 variant. */
2da2eaf4 3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3476 MVE_VSUB_VEC_T2,
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3481 MVE_ASRLI,
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRL,
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_LSLLI,
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLL,
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSRL,
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3506 MVE_SQRSHRL,
08132bdd
SP		 3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3511 MVE_SQRSHR,
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQSHLL,
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHL,
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SRSHRL,
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHR,
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3536 MVE_UQRSHLL,
08132bdd
SP		 3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3541 MVE_UQRSHL,
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQSHLL,
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHL,
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_URSHRL,
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHR,
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3564
e39c1607
SD		 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566 MVE_CSINC,
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINV,
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSET,
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSETM,
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSEL,
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSNEG,
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CINC,
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINV,
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CNEG,
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
143275ea
AV		 3610 {ARM_FEATURE_CORE_LOW (0),
3611 MVE_NONE,
3612 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3613};
3614
8f06b2d8
PB		 3615/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3617 match. */
3618
3619/* print_insn_arm recognizes the following format control codes:
3620
3621 %% %
3622
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
c1e26897 3625 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
62b3e311
PB		 3634 %U print barrier type.
3635 %P print address for pli instruction.
8f06b2d8
PB		 3636
3637 %<bitfield>r print as an ARM register
9eb6c0f1 3638 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3642 %<bitfield>d print the bitfield in decimal
43e65147 3643 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3646
16980d0b
JB		 3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3650
8f06b2d8
PB		 3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3655
8f06b2d8
PB		 3656static const struct opcode32 arm_opcodes[] =
3657{
3658 /* ARM instructions. */
823d2571
TG		 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3663
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3678
105bde57 3679 /* V8.2 RAS extension instructions. */
4d1464f2 3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3681 0xe320f010, 0xffffffff, "esb"},
3682
26417f19
AC		 3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3686
53c4b28b 3687 /* V8 instructions. */
823d2571
TG		 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3692 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3721 /* CRC32 instructions. */
8b301fbb 3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3734
ddfded2f
MW		 3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3738
90ec0d68 3739 /* Virtualization Extension instructions. */
823d2571
TG		 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3742
eea54501 3743 /* Integer Divide Extension instructions. */
823d2571
TG		 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3748
60e5ef9f 3749 /* MP Extension instructions. */
823d2571 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3751
c597cc3d
SD		 3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
62b3e311 3757 /* V7 instructions. */
823d2571
TG		 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3767
c19d1205 3768 /* ARM V6T2 instructions. */
823d2571
TG		 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
ff8646ee 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3791
f4c65163 3792 /* ARM Security extension instructions. */
823d2571
TG		 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3795
8f06b2d8 3796 /* ARM V6K instructions. */
823d2571
TG		 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3811
7fadb25d
SD		 3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
8f06b2d8 3815 /* ARM V6K NOP hints. */
823d2571
TG		 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3826
fe56b6ce 3827 /* ARM V6 instructions. */
823d2571
TG		 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 4072
8f06b2d8 4073 /* V5J instruction. */
823d2571
TG		 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4076
8f06b2d8 4077 /* V5 Instructions. */
823d2571
TG		 4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079 0xe1200070, 0xfff000f0,
4080 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4140
8f06b2d8 4141 /* ARM Instructions. */
823d2571
TG		 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4144
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4252
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4307
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4398
4399 /* The rest. */
4ab90a7a
AV		 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4406};
4407
4408/* print_insn_thumb16 recognizes the following format control codes:
4409
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
4422 %X print "\t; unpredictable <IT:code>" if conditional
4423 %I print IT instruction suffix and operands
4547cb56 4424 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4434
4435static const struct opcode16 thumb_opcodes[] =
4436{
4437 /* Thumb instructions. */
4438
16a1fa25
TP		 4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4442
53c4b28b 4443 /* ARM V8 instructions. */
823d2571
TG		 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4447
8f06b2d8 4448 /* ARM V6K no-argument instructions. */
823d2571
TG		 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4455
4456 /* ARM V6T2 instructions. */
ff8646ee
TP		 4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4462
4463 /* ARM V6. */
823d2571
TG		 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4475
4476 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4482 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4485 /* Format 4. */
823d2571
TG		 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4502 /* format 13 */
823d2571
TG		 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4505 /* format 5 */
823d2571
TG		 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4510 /* format 14 */
823d2571
TG		 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4513 /* format 2 */
823d2571
TG		 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4522 /* format 8 */
823d2571
TG		 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4529 /* format 7 */
823d2571
TG		 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4534 /* format 1 */
823d2571
TG		 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4540 /* format 3 */
823d2571
TG		 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4545 /* format 6 */
823d2571
TG		 4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548 0x4800, 0xF800,
4549 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4550 /* format 9 */
823d2571
TG		 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4559 /* format 10 */
823d2571
TG		 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4564 /* format 11 */
823d2571
TG		 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4569 /* format 12 */
823d2571
TG		 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4574 /* format 15 */
823d2571
TG		 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4577 /* format 17 */
823d2571 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4579 /* format 16 */
823d2571
TG		 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4583 /* format 18 */
823d2571 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4585
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4592};
4593
4594/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4597
4598 print_insn_thumb32 recognizes the following format control codes:
4599
4600 %% %
4601
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4607 %S print a possibly-shifted Rm
4608
32a94698 4609 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4b5a202f 4613 %n print register mask for clrm
8f06b2d8
PB		 4614
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4617 %G print a fallback offset for Branch Future instructions
e5d6e09e 4618 %W print an offset for BF instruction
1caf72a5 4619 %Y print an offset for BFL instruction
1889da70 4620 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
62b3e311
PB		 4627 %U print barrier type.
4628 %P print address for pli instruction.
c22aaad1
PB		 4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
4631 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4632
4633 %<bitfield>d print bitfield in decimal
f0fba320 4634 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
dd5181d5 4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4639 %<bitfield>c print bitfield as a condition code
4640
16980d0b
JB		 4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4644
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653static const struct opcode32 thumb32_opcodes[] =
4654{
4b5a202f
AV		 4655 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4656 instructions. */
60f993ce 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4658 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4660 0xf02fc001, 0xfffff001, "le\t%P"},
4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4664 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4668 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4670 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4671 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4672 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4673
4389b29a
AV		 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4681 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4683 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4684
4b5a202f
AV		 4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4686 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4687
16a1fa25
TP		 4688 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4691 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4693 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4695 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4697 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4698
105bde57 4699 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4701 0xf3af8010, 0xffffffff, "esb"},
4702
53c4b28b 4703 /* V8 instructions. */
823d2571
TG		 4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4705 0xf3af8005, 0xffffffff, "sevl%c.w"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4707 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4709 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4711 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4713 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4715 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4717 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4719 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4721 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4723 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4725 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4727 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4729 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4731 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4733 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4735 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4736
26417f19
AC		 4737 /* V8-R instructions. */
4738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4739 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4740
dd5181d5 4741 /* CRC32 instructions. */
8b301fbb 4742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4743 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4745 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4747 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4749 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4751 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4753 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4754
c597cc3d
SD		 4755 /* Speculation Barriers. */
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4759
62b3e311 4760 /* V7 instructions. */
823d2571
TG		 4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4769 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4771 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4772
90ec0d68 4773 /* Virtualization Extension instructions. */
823d2571 4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4775 /* We skip ERET as that is SUBS pc, lr, #0. */
4776
60e5ef9f 4777 /* MP Extension instructions. */
823d2571 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4779
f4c65163 4780 /* Security extension instructions. */
823d2571 4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4782
7fadb25d
SD		 4783 /* ARMv8.5-A instructions. */
4784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4785
8f06b2d8 4786 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4795
ff8646ee 4796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4797 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4825 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4826 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4827 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4845 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4929 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4931 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4935 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4953 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4955 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5011 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5013 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5017 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5019 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5021 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5025 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5027 0xf810f000, 0xff70f000, "pld%c\t%a"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5029 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5031 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5033 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5035 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5037 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5039 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5041 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5043 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5045 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5047 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5049 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5051 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5053 0xfb100000, 0xfff000c0,
5054 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xfbc00080, 0xfff000c0,
5057 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5059 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5061 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 5063 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5065 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5067 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5069 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5071 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5073 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5075 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5077 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5079 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5081 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5083 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5085 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5087 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5089 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5091 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5093 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5095 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5097 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5099 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5101 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5103 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5105 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5107 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5109 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5111 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5113 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5115 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5117 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5119 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5121 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5123 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5125 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5127 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5129 0xe9400000, 0xff500000,
5130 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xe9500000, 0xff500000,
5133 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5135 0xe8600000, 0xff700000,
5136 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138 0xe8700000, 0xff700000,
5139 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5141 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5143 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5144
5145 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5147 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5151 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5153 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5154
8f06b2d8 5155 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5157 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5159 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5160
5161 /* Fallback. */
823d2571
TG		 5162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5163 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5164 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5165};
ff4a8d2b 5166
8f06b2d8
PB		 5167static const char *const arm_conditional[] =
5168{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5169 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5170
5171static const char *const arm_fp_const[] =
5172{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5173
5174static const char *const arm_shift[] =
5175{"lsl", "lsr", "asr", "ror"};
5176
5177typedef struct
5178{
5179 const char *name;
5180 const char *description;
5181 const char *reg_names[16];
5182}
5183arm_regname;
5184
5185static const arm_regname regnames[] =
5186{
65b48a81 5187 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5188 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5189 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5190 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5191 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5192 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5193 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5194 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5195 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5196 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5197 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5198 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5199 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5200 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5201 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5202};
5203
5204static const char *const iwmmxt_wwnames[] =
5205{"b", "h", "w", "d"};
5206
5207static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5208{"b", "bus", "bc", "bss",
5209 "h", "hus", "hc", "hss",
5210 "w", "wus", "wc", "wss",
5211 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5212};
5213
5214static const char *const iwmmxt_regnames[] =
5215{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5216 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5217};
5218
5219static const char *const iwmmxt_cregnames[] =
5220{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5221 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5222};
5223
143275ea
AV		 5224static const char *const vec_condnames[] =
5225{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5226};
5227
5228static const char *const mve_predicatenames[] =
5229{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5230 "eee", "ee", "eet", "e", "ett", "et", "ete"
5231};
5232
5233/* Names for 2-bit size field for mve vector isntructions. */
5234static const char *const mve_vec_sizename[] =
5235 { "8", "16", "32", "64"};
5236
5237/* Indicates whether we are processing a then predicate,
5238 else predicate or none at all. */
5239enum vpt_pred_state
5240{
5241 PRED_NONE,
5242 PRED_THEN,
5243 PRED_ELSE
5244};
5245
5246/* Information used to process a vpt block and subsequent instructions. */
5247struct vpt_block
5248{
5249 /* Are we in a vpt block. */
78933a4a 5250 bool in_vpt_block;
143275ea
AV		 5251
5252 /* Next predicate state if in vpt block. */
5253 enum vpt_pred_state next_pred_state;
5254
5255 /* Mask from vpt/vpst instruction. */
5256 long predicate_mask;
5257
5258 /* Instruction number in vpt block. */
5259 long current_insn_num;
5260
5261 /* Number of instructions in vpt block.. */
5262 long num_pred_insn;
5263};
5264
5265static struct vpt_block vpt_block_state =
5266{
78933a4a 5267 false,
143275ea
AV		 5268 PRED_NONE,
5269 0,
5270 0,
5271 0
5272};
5273
8f06b2d8
PB		 5274/* Default to GCC register name set. */
5275static unsigned int regname_selected = 1;
5276
65b48a81 5277#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5278#define arm_regnames regnames[regname_selected].reg_names
5279
78933a4a 5280static bool force_thumb = false;
4934a27c 5281static uint16_t cde_coprocs = 0;
8f06b2d8 5282
c22aaad1
PB		 5283/* Current IT instruction state. This contains the same state as the IT
5284 bits in the CPSR. */
5285static unsigned int ifthen_state;
5286/* IT state for the next instruction. */
5287static unsigned int ifthen_next_state;
5288/* The address of the insn for which the IT state is valid. */
5289static bfd_vma ifthen_address;
5290#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5291/* Indicates that the current Conditional state is unconditional or outside
5292 an IT block. */
5293#define COND_UNCOND 16
c22aaad1 5294
8f06b2d8
PB		 5295\f
5296/* Functions. */
143275ea
AV		 5297/* Extract the predicate mask for a VPT or VPST instruction.
5298 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5299
5300static long
5301mve_extract_pred_mask (long given)
5302{
5303 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5304}
5305
5306/* Return the number of instructions in a MVE predicate block. */
5307static long
5308num_instructions_vpt_block (long given)
5309{
5310 long mask = mve_extract_pred_mask (given);
5311 if (mask == 0)
5312 return 0;
5313
5314 if (mask == 8)
5315 return 1;
5316
5317 if ((mask & 7) == 4)
5318 return 2;
5319
5320 if ((mask & 3) == 2)
5321 return 3;
5322
5323 if ((mask & 1) == 1)
5324 return 4;
5325
5326 return 0;
5327}
5328
5329static void
5330mark_outside_vpt_block (void)
5331{
78933a4a 5332 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5333 vpt_block_state.next_pred_state = PRED_NONE;
5334 vpt_block_state.predicate_mask = 0;
5335 vpt_block_state.current_insn_num = 0;
5336 vpt_block_state.num_pred_insn = 0;
5337}
5338
5339static void
5340mark_inside_vpt_block (long given)
5341{
78933a4a 5342 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5343 vpt_block_state.next_pred_state = PRED_THEN;
5344 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5345 vpt_block_state.current_insn_num = 0;
5346 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5347 assert (vpt_block_state.num_pred_insn >= 1);
5348}
5349
5350static enum vpt_pred_state
5351invert_next_predicate_state (enum vpt_pred_state astate)
5352{
5353 if (astate == PRED_THEN)
5354 return PRED_ELSE;
5355 else if (astate == PRED_ELSE)
5356 return PRED_THEN;
5357 else
5358 return PRED_NONE;
5359}
5360
5361static enum vpt_pred_state
5362update_next_predicate_state (void)
5363{
5364 long pred_mask = vpt_block_state.predicate_mask;
5365 long mask_for_insn = 0;
5366
5367 switch (vpt_block_state.current_insn_num)
5368 {
5369 case 1:
5370 mask_for_insn = 8;
5371 break;
5372
5373 case 2:
5374 mask_for_insn = 4;
5375 break;
5376
5377 case 3:
5378 mask_for_insn = 2;
5379 break;
5380
5381 case 4:
5382 return PRED_NONE;
5383 }
5384
5385 if (pred_mask & mask_for_insn)
5386 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5387 else
5388 return vpt_block_state.next_pred_state;
5389}
5390
5391static void
5392update_vpt_block_state (void)
5393{
5394 vpt_block_state.current_insn_num++;
5395 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5396 {
5397 /* No more instructions to process in vpt block. */
5398 mark_outside_vpt_block ();
5399 return;
5400 }
5401
5402 vpt_block_state.next_pred_state = update_next_predicate_state ();
5403}
8f06b2d8 5404
16980d0b
JB		 5405/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5406 Returns pointer to following character of the format string and
5407 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5408 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5409
5410static const char *
fe56b6ce
NC		 5411arm_decode_bitfield (const char *ptr,
5412 unsigned long insn,
5413 unsigned long *valuep,
5414 int *widthp)
16980d0b
JB		 5415{
5416 unsigned long value = 0;
5417 int width = 0;
43e65147
L		 5418
5419 do
16980d0b
JB		 5420 {
5421 int start, end;
5422 int bits;
5423
5424 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5425 start = start * 10 + *ptr - '0';
5426 if (*ptr == '-')
5427 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5428 end = end * 10 + *ptr - '0';
5429 else
5430 end = start;
5431 bits = end - start;
5432 if (bits < 0)
5433 abort ();
5434 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5435 width += bits + 1;
5436 }
5437 while (*ptr++ == ',');
5438 *valuep = value;
5439 if (widthp)
5440 *widthp = width;
5441 return ptr - 1;
5442}
5443
8f06b2d8 5444static void
37b37b2d 5445arm_decode_shift (long given, fprintf_ftype func, void *stream,
78933a4a 5446 bool print_shift)
8f06b2d8
PB		 5447{
5448 func (stream, "%s", arm_regnames[given & 0xf]);
5449
5450 if ((given & 0xff0) != 0)
5451 {
5452 if ((given & 0x10) == 0)
5453 {
5454 int amount = (given & 0xf80) >> 7;
5455 int shift = (given & 0x60) >> 5;
5456
5457 if (amount == 0)
5458 {
5459 if (shift == 3)
5460 {
5461 func (stream, ", rrx");
5462 return;
5463 }
5464
5465 amount = 32;
5466 }
5467
37b37b2d
RE		 5468 if (print_shift)
5469 func (stream, ", %s #%d", arm_shift[shift], amount);
5470 else
5471 func (stream, ", #%d", amount);
8f06b2d8 5472 }
74bdfecf 5473 else if ((given & 0x80) == 0x80)
aefd8a40 5474 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5475 else if (print_shift)
8f06b2d8
PB		 5476 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5477 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5478 else
5479 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5480 }
5481}
5482
73cd51e5
AV		 5483/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5484
78933a4a 5485static bool
73cd51e5
AV		 5486is_mve_okay_in_it (enum mve_instructions matched_insn)
5487{
c507f10b
AV		 5488 switch (matched_insn)
5489 {
5490 case MVE_VMOV_GP_TO_VEC_LANE:
5491 case MVE_VMOV2_VEC_LANE_TO_GP:
5492 case MVE_VMOV2_GP_TO_VEC_LANE:
5493 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5494 case MVE_LSLL:
5495 case MVE_LSLLI:
5496 case MVE_LSRL:
5497 case MVE_ASRL:
5498 case MVE_ASRLI:
5499 case MVE_SQRSHRL:
5500 case MVE_SQRSHR:
5501 case MVE_UQRSHL:
5502 case MVE_UQRSHLL:
5503 case MVE_UQSHL:
5504 case MVE_UQSHLL:
5505 case MVE_URSHRL:
5506 case MVE_URSHR:
5507 case MVE_SRSHRL:
5508 case MVE_SRSHR:
5509 case MVE_SQSHLL:
5510 case MVE_SQSHL:
78933a4a 5511 return true;
c507f10b 5512 default:
78933a4a 5513 return false;
c507f10b 5514 }
73cd51e5
AV		 5515}
5516
78933a4a 5517static bool
73cd51e5
AV		 5518is_mve_architecture (struct disassemble_info *info)
5519{
5520 struct arm_private_data *private_data = info->private_data;
5521 arm_feature_set allowed_arches = private_data->features;
5522
5523 arm_feature_set arm_ext_v8_1m_main
5524 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5525
5526 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5527 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5528 return true;
73cd51e5 5529 else
78933a4a 5530 return false;
73cd51e5
AV		 5531}
5532
78933a4a 5533static bool
143275ea
AV		 5534is_vpt_instruction (long given)
5535{
5536
5537 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5538 if ((given & 0x0040e000) == 0)
78933a4a 5539 return false;
143275ea
AV		 5540
5541 /* VPT floating point T1 variant. */
5542 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5543 /* VPT floating point T2 variant. */
5544 || ((given & 0xefb10f50) == 0xee310f40)
5545 /* VPT vector T1 variant. */
5546 || ((given & 0xff811f51) == 0xfe010f00)
5547 /* VPT vector T2 variant. */
5548 || ((given & 0xff811f51) == 0xfe010f01
5549 && ((given & 0x300000) != 0x300000))
5550 /* VPT vector T3 variant. */
5551 || ((given & 0xff811f50) == 0xfe011f00)
5552 /* VPT vector T4 variant. */
5553 || ((given & 0xff811f70) == 0xfe010f40)
5554 /* VPT vector T5 variant. */
5555 || ((given & 0xff811f70) == 0xfe010f60)
5556 /* VPT vector T6 variant. */
5557 || ((given & 0xff811f50) == 0xfe011f40)
5558 /* VPST vector T variant. */
5559 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5560 return true;
143275ea 5561 else
78933a4a 5562 return false;
143275ea
AV		 5563}
5564
73cd51e5
AV		 5565/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5566 and ending bitfield = END. END must be greater than START. */
5567
5568static unsigned long
5569arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5570{
5571 int bits = end - start;
5572
5573 if (bits < 0)
5574 abort ();
5575
5576 return ((given >> start) & ((2ul << bits) - 1));
5577}
5578
5579/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5580 START:END and START2:END2. END/END2 must be greater than
5581 START/START2. */
5582
5583static unsigned long
5584arm_decode_field_multiple (unsigned long given, unsigned int start,
5585 unsigned int end, unsigned int start2,
5586 unsigned int end2)
5587{
5588 int bits = end - start;
5589 int bits2 = end2 - start2;
5590 unsigned long value = 0;
5591 int width = 0;
5592
5593 if (bits2 < 0)
5594 abort ();
5595
5596 value = arm_decode_field (given, start, end);
5597 width += bits + 1;
5598
5599 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5600 return value;
5601}
5602
5603/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5604 This helps us decode instructions that change mnemonic depending on specific
5605 operand values/encodings. */
5606
78933a4a 5607static bool
73cd51e5
AV		 5608is_mve_encoding_conflict (unsigned long given,
5609 enum mve_instructions matched_insn)
5610{
143275ea
AV		 5611 switch (matched_insn)
5612 {
5613 case MVE_VPST:
5614 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5615 return true;
143275ea 5616 else
78933a4a 5617 return false;
143275ea
AV		 5618
5619 case MVE_VPT_FP_T1:
5620 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5621 return true;
143275ea
AV		 5622 if ((arm_decode_field (given, 12, 12) == 0)
5623 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5624 return true;
5625 return false;
143275ea
AV		 5626
5627 case MVE_VPT_FP_T2:
5628 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5629 return true;
143275ea 5630 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5631 return true;
5632 return false;
143275ea
AV		 5633
5634 case MVE_VPT_VEC_T1:
5635 case MVE_VPT_VEC_T2:
5636 case MVE_VPT_VEC_T3:
5637 case MVE_VPT_VEC_T4:
5638 case MVE_VPT_VEC_T5:
5639 case MVE_VPT_VEC_T6:
5640 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5641 return true;
143275ea 5642 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5643 return true;
5644 return false;
143275ea
AV		 5645
5646 case MVE_VCMP_FP_T1:
5647 if ((arm_decode_field (given, 12, 12) == 0)
5648 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5649 return true;
143275ea 5650 else
78933a4a 5651 return false;
143275ea
AV		 5652
5653 case MVE_VCMP_FP_T2:
5654 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5655 return true;
143275ea 5656 else
78933a4a 5657 return false;
143275ea 5658
14b456f2
AV		 5659 case MVE_VQADD_T2:
5660 case MVE_VQSUB_T2:
f49bb598
AV		 5661 case MVE_VMUL_VEC_T2:
5662 case MVE_VMULH:
5663 case MVE_VRMULH:
56858bea
AV		 5664 case MVE_VMLA:
5665 case MVE_VMAX:
5666 case MVE_VMIN:
e523f101 5667 case MVE_VBRSR:
66dcaa5d
AV		 5668 case MVE_VADD_VEC_T2:
5669 case MVE_VSUB_VEC_T2:
5670 case MVE_VABAV:
ed63aa17
AV		 5671 case MVE_VQRSHL_T1:
5672 case MVE_VQSHL_T4:
5673 case MVE_VRSHL_T1:
5674 case MVE_VSHL_T3:
897b9bbc
AV		 5675 case MVE_VCADD_VEC:
5676 case MVE_VHCADD:
1c8f2df8
AV		 5677 case MVE_VDDUP:
5678 case MVE_VIDUP:
d3b63143
AV		 5679 case MVE_VQRDMLADH:
5680 case MVE_VQDMLAH:
5681 case MVE_VQRDMLAH:
5682 case MVE_VQDMLASH:
5683 case MVE_VQRDMLASH:
5684 case MVE_VQDMLSDH:
5685 case MVE_VQRDMLSDH:
5686 case MVE_VQDMULH_T3:
5687 case MVE_VQRDMULH_T4:
5688 case MVE_VQDMLADH:
5689 case MVE_VMLAS:
14925797 5690 case MVE_VMULL_INT:
9743db03
AV		 5691 case MVE_VHADD_T2:
5692 case MVE_VHSUB_T2:
143275ea
AV		 5693 case MVE_VCMP_VEC_T1:
5694 case MVE_VCMP_VEC_T2:
5695 case MVE_VCMP_VEC_T3:
5696 case MVE_VCMP_VEC_T4:
5697 case MVE_VCMP_VEC_T5:
5698 case MVE_VCMP_VEC_T6:
5699 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5700 return true;
143275ea 5701 else
78933a4a 5702 return false;
143275ea 5703
04d54ace
AV		 5704 case MVE_VLD2:
5705 case MVE_VLD4:
5706 case MVE_VST2:
5707 case MVE_VST4:
5708 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5709 return true;
04d54ace 5710 else
78933a4a 5711 return false;
04d54ace 5712
aef6d006
AV		 5713 case MVE_VSTRB_T1:
5714 case MVE_VSTRH_T2:
5715 if ((arm_decode_field (given, 24, 24) == 0)
5716 && (arm_decode_field (given, 21, 21) == 0))
5717 {
78933a4a 5718 return true;
aef6d006
AV		 5719 }
5720 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5721 return true;
aef6d006 5722 else
78933a4a 5723 return false;
aef6d006
AV		 5724
5725 case MVE_VSTRB_T5:
5726 case MVE_VSTRH_T6:
5727 case MVE_VSTRW_T7:
5728 if ((arm_decode_field (given, 24, 24) == 0)
5729 && (arm_decode_field (given, 21, 21) == 0))
5730 {
78933a4a 5731 return true;
aef6d006
AV		 5732 }
5733 else
78933a4a 5734 return false;
aef6d006 5735
bf0b396d
AV		 5736 case MVE_VCVT_FP_FIX_VEC:
5737 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5738
c507f10b
AV		 5739 case MVE_VBIC_IMM:
5740 case MVE_VORR_IMM:
5741 {
5742 unsigned long cmode = arm_decode_field (given, 8, 11);
5743
5744 if ((cmode & 1) == 0)
78933a4a 5745 return true;
c507f10b 5746 else if ((cmode & 0xc) == 0xc)
78933a4a 5747 return true;
c507f10b 5748 else
78933a4a 5749 return false;
c507f10b
AV		 5750 }
5751
5752 case MVE_VMVN_IMM:
5753 {
5754 unsigned long cmode = arm_decode_field (given, 8, 11);
5755
ce760a76 5756 if (cmode == 0xe)
78933a4a 5757 return true;
ce760a76 5758 else if ((cmode & 0x9) == 1)
78933a4a 5759 return true;
ce760a76 5760 else if ((cmode & 0xd) == 9)
78933a4a 5761 return true;
c507f10b 5762 else
78933a4a 5763 return false;
c507f10b
AV		 5764 }
5765
5766 case MVE_VMOV_IMM_TO_VEC:
5767 if ((arm_decode_field (given, 5, 5) == 1)
5768 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5769 return true;
c507f10b 5770 else
78933a4a 5771 return false;
c507f10b 5772
14925797
AV		 5773 case MVE_VMOVL:
5774 {
5775 unsigned long size = arm_decode_field (given, 19, 20);
5776 if ((size == 0) || (size == 3))
78933a4a 5777 return true;
14925797 5778 else
78933a4a 5779 return false;
14925797
AV		 5780 }
5781
56858bea
AV		 5782 case MVE_VMAXA:
5783 case MVE_VMINA:
5784 case MVE_VMAXV:
5785 case MVE_VMAXAV:
5786 case MVE_VMINV:
5787 case MVE_VMINAV:
ed63aa17
AV		 5788 case MVE_VQRSHL_T2:
5789 case MVE_VQSHL_T1:
5790 case MVE_VRSHL_T2:
5791 case MVE_VSHL_T2:
5792 case MVE_VSHLL_T2:
d3b63143 5793 case MVE_VADDV:
14925797
AV		 5794 case MVE_VMOVN:
5795 case MVE_VQMOVUN:
5796 case MVE_VQMOVN:
5797 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5798 return true;
14925797 5799 else
78933a4a 5800 return false;
14925797 5801
d3b63143
AV		 5802 case MVE_VMLSLDAV:
5803 case MVE_VRMLSLDAVH:
5804 case MVE_VMLALDAV:
5805 case MVE_VADDLV:
5806 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5807 return true;
d3b63143 5808 else
78933a4a 5809 return false;
d3b63143
AV		 5810
5811 case MVE_VRMLALDAVH:
5812 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5813 return true;
d3b63143 5814 else
78933a4a 5815 return false;
d3b63143 5816
1c8f2df8
AV		 5817 case MVE_VDWDUP:
5818 case MVE_VIWDUP:
5819 if ((arm_decode_field (given, 20, 21) == 3)
5820 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5821 return true;
1c8f2df8 5822 else
78933a4a 5823 return false;
1c8f2df8 5824
ed63aa17
AV		 5825
5826 case MVE_VSHLL_T1:
5827 if (arm_decode_field (given, 16, 18) == 0)
5828 {
5829 unsigned long sz = arm_decode_field (given, 19, 20);
5830
5831 if ((sz == 1) || (sz == 2))
78933a4a 5832 return true;
ed63aa17 5833 else
78933a4a 5834 return false;
ed63aa17
AV		 5835 }
5836 else
78933a4a 5837 return false;
ed63aa17
AV		 5838
5839 case MVE_VQSHL_T2:
5840 case MVE_VQSHLU_T3:
5841 case MVE_VRSHR:
5842 case MVE_VSHL_T1:
5843 case MVE_VSHR:
5844 case MVE_VSLI:
5845 case MVE_VSRI:
5846 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5847 return true;
ed63aa17 5848 else
78933a4a 5849 return false;
ed63aa17 5850
e523f101
AV		 5851 case MVE_VCTP:
5852 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5853 return true;
e523f101 5854 else
78933a4a 5855 return false;
e523f101 5856
23d00a41
SD		 5857 case MVE_ASRLI:
5858 case MVE_ASRL:
5859 case MVE_LSLLI:
5860 case MVE_LSLL:
5861 case MVE_LSRL:
5862 case MVE_SQRSHRL:
5863 case MVE_SQSHLL:
5864 case MVE_SRSHRL:
5865 case MVE_UQRSHLL:
5866 case MVE_UQSHLL:
5867 case MVE_URSHRL:
5868 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5869 return true;
23d00a41 5870 else
78933a4a 5871 return false;
23d00a41 5872
e39c1607
SD		 5873 case MVE_CSINC:
5874 case MVE_CSINV:
5875 {
5876 unsigned long rm, rn;
5877 rm = arm_decode_field (given, 0, 3);
5878 rn = arm_decode_field (given, 16, 19);
5879 /* CSET/CSETM. */
5880 if (rm == 0xf && rn == 0xf)
78933a4a 5881 return true;
e39c1607
SD		 5882 /* CINC/CINV. */
5883 else if (rn == rm && rn != 0xf)
78933a4a 5884 return true;
e39c1607
SD		 5885 }
5886 /* Fall through. */
5887 case MVE_CSEL:
5888 case MVE_CSNEG:
5889 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5890 return true;
e39c1607
SD		 5891 /* CNEG. */
5892 else if (matched_insn == MVE_CSNEG)
5893 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5894 return true;
5895 return false;
e39c1607 5896
143275ea 5897 default:
66dcaa5d
AV		 5898 case MVE_VADD_FP_T1:
5899 case MVE_VADD_FP_T2:
5900 case MVE_VADD_VEC_T1:
78933a4a 5901 return false;
143275ea
AV		 5902
5903 }
73cd51e5
AV		 5904}
5905
aef6d006
AV		 5906static void
5907print_mve_vld_str_addr (struct disassemble_info *info,
5908 unsigned long given,
5909 enum mve_instructions matched_insn)
5910{
5911 void *stream = info->stream;
5912 fprintf_ftype func = info->fprintf_func;
5913
5914 unsigned long p, w, gpr, imm, add, mod_imm;
5915
5916 imm = arm_decode_field (given, 0, 6);
5917 mod_imm = imm;
5918
5919 switch (matched_insn)
5920 {
5921 case MVE_VLDRB_T1:
5922 case MVE_VSTRB_T1:
5923 gpr = arm_decode_field (given, 16, 18);
5924 break;
5925
5926 case MVE_VLDRH_T2:
5927 case MVE_VSTRH_T2:
5928 gpr = arm_decode_field (given, 16, 18);
5929 mod_imm = imm << 1;
5930 break;
5931
5932 case MVE_VLDRH_T6:
5933 case MVE_VSTRH_T6:
5934 gpr = arm_decode_field (given, 16, 19);
5935 mod_imm = imm << 1;
5936 break;
5937
5938 case MVE_VLDRW_T7:
5939 case MVE_VSTRW_T7:
5940 gpr = arm_decode_field (given, 16, 19);
5941 mod_imm = imm << 2;
5942 break;
5943
5944 case MVE_VLDRB_T5:
5945 case MVE_VSTRB_T5:
5946 gpr = arm_decode_field (given, 16, 19);
5947 break;
5948
5949 default:
5950 return;
5951 }
5952
5953 p = arm_decode_field (given, 24, 24);
5954 w = arm_decode_field (given, 21, 21);
5955
5956 add = arm_decode_field (given, 23, 23);
5957
5958 char * add_sub;
5959
5960 /* Don't print anything for '+' as it is implied. */
5961 if (add == 1)
5962 add_sub = "";
5963 else
5964 add_sub = "-";
5965
5966 if (p == 1)
5967 {
5968 /* Offset mode. */
5969 if (w == 0)
5970 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5971 /* Pre-indexed mode. */
5972 else
5973 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5974 }
5975 else if ((p == 0) && (w == 1))
5976 /* Post-index mode. */
5977 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5978}
5979
73cd51e5
AV		 5980/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5981 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5982 this encoding is undefined. */
5983
78933a4a 5984static bool
73cd51e5
AV		 5985is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5986 enum mve_undefined *undefined_code)
5987{
5988 *undefined_code = UNDEF_NONE;
5989
9743db03
AV		 5990 switch (matched_insn)
5991 {
5992 case MVE_VDUP:
5993 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5994 {
5995 *undefined_code = UNDEF_SIZE_3;
78933a4a 5996 return true;
9743db03
AV		 5997 }
5998 else
78933a4a 5999 return false;
9743db03 6000
14b456f2
AV		 6001 case MVE_VQADD_T1:
6002 case MVE_VQSUB_T1:
f49bb598 6003 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6004 case MVE_VABD_VEC:
6005 case MVE_VADD_VEC_T1:
6006 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6007 case MVE_VQDMULH_T1:
6008 case MVE_VQRDMULH_T2:
9743db03
AV		 6009 case MVE_VRHADD:
6010 case MVE_VHADD_T1:
6011 case MVE_VHSUB_T1:
6012 if (arm_decode_field (given, 20, 21) == 3)
6013 {
6014 *undefined_code = UNDEF_SIZE_3;
78933a4a 6015 return true;
9743db03
AV		 6016 }
6017 else
78933a4a 6018 return false;
9743db03 6019
aef6d006
AV		 6020 case MVE_VLDRB_T1:
6021 if (arm_decode_field (given, 7, 8) == 3)
6022 {
6023 *undefined_code = UNDEF_SIZE_3;
78933a4a 6024 return true;
aef6d006
AV		 6025 }
6026 else
78933a4a 6027 return false;
aef6d006
AV		 6028
6029 case MVE_VLDRH_T2:
6030 if (arm_decode_field (given, 7, 8) <= 1)
6031 {
6032 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6033 return true;
aef6d006
AV		 6034 }
6035 else
78933a4a 6036 return false;
aef6d006
AV		 6037
6038 case MVE_VSTRB_T1:
6039 if ((arm_decode_field (given, 7, 8) == 0))
6040 {
6041 *undefined_code = UNDEF_SIZE_0;
78933a4a 6042 return true;
aef6d006
AV		 6043 }
6044 else
78933a4a 6045 return false;
aef6d006
AV		 6046
6047 case MVE_VSTRH_T2:
6048 if ((arm_decode_field (given, 7, 8) <= 1))
6049 {
6050 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6051 return true;
aef6d006
AV		 6052 }
6053 else
78933a4a 6054 return false;
aef6d006 6055
ef1576a1
AV		 6056 case MVE_VLDRB_GATHER_T1:
6057 if (arm_decode_field (given, 7, 8) == 3)
6058 {
6059 *undefined_code = UNDEF_SIZE_3;
78933a4a 6060 return true;
ef1576a1
AV		 6061 }
6062 else if ((arm_decode_field (given, 28, 28) == 0)
6063 && (arm_decode_field (given, 7, 8) == 0))
6064 {
6065 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 6066 return true;
ef1576a1
AV		 6067 }
6068 else
78933a4a 6069 return false;
ef1576a1
AV		 6070
6071 case MVE_VLDRH_GATHER_T2:
6072 if (arm_decode_field (given, 7, 8) == 3)
6073 {
6074 *undefined_code = UNDEF_SIZE_3;
78933a4a 6075 return true;
ef1576a1
AV		 6076 }
6077 else if ((arm_decode_field (given, 28, 28) == 0)
6078 && (arm_decode_field (given, 7, 8) == 1))
6079 {
6080 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 6081 return true;
ef1576a1
AV		 6082 }
6083 else if (arm_decode_field (given, 7, 8) == 0)
6084 {
6085 *undefined_code = UNDEF_SIZE_0;
78933a4a 6086 return true;
ef1576a1
AV		 6087 }
6088 else
78933a4a 6089 return false;
ef1576a1
AV		 6090
6091 case MVE_VLDRW_GATHER_T3:
6092 if (arm_decode_field (given, 7, 8) != 2)
6093 {
6094 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6095 return true;
ef1576a1
AV		 6096 }
6097 else if (arm_decode_field (given, 28, 28) == 0)
6098 {
6099 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6100 return true;
ef1576a1
AV		 6101 }
6102 else
78933a4a 6103 return false;
ef1576a1
AV		 6104
6105 case MVE_VLDRD_GATHER_T4:
6106 if (arm_decode_field (given, 7, 8) != 3)
6107 {
6108 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6109 return true;
ef1576a1
AV		 6110 }
6111 else if (arm_decode_field (given, 28, 28) == 0)
6112 {
6113 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6114 return true;
ef1576a1
AV		 6115 }
6116 else
78933a4a 6117 return false;
ef1576a1
AV		 6118
6119 case MVE_VSTRB_SCATTER_T1:
6120 if (arm_decode_field (given, 7, 8) == 3)
6121 {
6122 *undefined_code = UNDEF_SIZE_3;
78933a4a 6123 return true;
ef1576a1
AV		 6124 }
6125 else
78933a4a 6126 return false;
ef1576a1
AV		 6127
6128 case MVE_VSTRH_SCATTER_T2:
6129 {
6130 unsigned long size = arm_decode_field (given, 7, 8);
6131 if (size == 3)
6132 {
6133 *undefined_code = UNDEF_SIZE_3;
78933a4a 6134 return true;
ef1576a1
AV		 6135 }
6136 else if (size == 0)
6137 {
6138 *undefined_code = UNDEF_SIZE_0;
78933a4a 6139 return true;
ef1576a1
AV		 6140 }
6141 else
78933a4a 6142 return false;
ef1576a1
AV		 6143 }
6144
6145 case MVE_VSTRW_SCATTER_T3:
6146 if (arm_decode_field (given, 7, 8) != 2)
6147 {
6148 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6149 return true;
ef1576a1
AV		 6150 }
6151 else
78933a4a 6152 return false;
ef1576a1
AV		 6153
6154 case MVE_VSTRD_SCATTER_T4:
6155 if (arm_decode_field (given, 7, 8) != 3)
6156 {
6157 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6158 return true;
ef1576a1
AV		 6159 }
6160 else
78933a4a 6161 return false;
ef1576a1 6162
bf0b396d
AV		 6163 case MVE_VCVT_FP_FIX_VEC:
6164 {
6165 unsigned long imm6 = arm_decode_field (given, 16, 21);
6166 if ((imm6 & 0x20) == 0)
6167 {
6168 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 6169 return true;
bf0b396d
AV		 6170 }
6171
6172 if ((arm_decode_field (given, 9, 9) == 0)
6173 && ((imm6 & 0x30) == 0x20))
6174 {
6175 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 6176 return true;
bf0b396d
AV		 6177 }
6178
78933a4a 6179 return false;
bf0b396d
AV		 6180 }
6181
f49bb598 6182 case MVE_VNEG_FP:
66dcaa5d 6183 case MVE_VABS_FP:
bf0b396d
AV		 6184 case MVE_VCVT_BETWEEN_FP_INT:
6185 case MVE_VCVT_FROM_FP_TO_INT:
6186 {
6187 unsigned long size = arm_decode_field (given, 18, 19);
6188 if (size == 0)
6189 {
6190 *undefined_code = UNDEF_SIZE_0;
78933a4a 6191 return true;
bf0b396d
AV		 6192 }
6193 else if (size == 3)
6194 {
6195 *undefined_code = UNDEF_SIZE_3;
78933a4a 6196 return true;
bf0b396d
AV		 6197 }
6198 else
78933a4a 6199 return false;
bf0b396d
AV		 6200 }
6201
c507f10b
AV		 6202 case MVE_VMOV_VEC_LANE_TO_GP:
6203 {
6204 unsigned long op1 = arm_decode_field (given, 21, 22);
6205 unsigned long op2 = arm_decode_field (given, 5, 6);
6206 unsigned long u = arm_decode_field (given, 23, 23);
6207
6208 if ((op2 == 0) && (u == 1))
6209 {
6210 if ((op1 == 0) || (op1 == 1))
6211 {
6212 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 6213 return true;
c507f10b
AV		 6214 }
6215 else
78933a4a 6216 return false;
c507f10b
AV		 6217 }
6218 else if (op2 == 2)
6219 {
6220 if ((op1 == 0) || (op1 == 1))
6221 {
6222 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6223 return true;
c507f10b
AV		 6224 }
6225 else
78933a4a 6226 return false;
c507f10b
AV		 6227 }
6228
78933a4a 6229 return false;
c507f10b
AV		 6230 }
6231
6232 case MVE_VMOV_GP_TO_VEC_LANE:
6233 if (arm_decode_field (given, 5, 6) == 2)
6234 {
6235 unsigned long op1 = arm_decode_field (given, 21, 22);
6236 if ((op1 == 0) || (op1 == 1))
6237 {
6238 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6239 return true;
c507f10b
AV		 6240 }
6241 else
78933a4a 6242 return false;
c507f10b
AV		 6243 }
6244 else
78933a4a 6245 return false;
c507f10b 6246
c4a23bf8
SP		 6247 case MVE_VMOV_VEC_TO_VEC:
6248 if ((arm_decode_field (given, 5, 5) == 1)
6249 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6250 return true;
6251 return false;
c4a23bf8 6252
c507f10b
AV		 6253 case MVE_VMOV_IMM_TO_VEC:
6254 if (arm_decode_field (given, 5, 5) == 0)
6255 {
6256 unsigned long cmode = arm_decode_field (given, 8, 11);
6257
6258 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6259 {
6260 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6261 return true;
c507f10b
AV		 6262 }
6263 else
78933a4a 6264 return false;
c507f10b
AV		 6265 }
6266 else
78933a4a 6267 return false;
c507f10b 6268
ed63aa17 6269 case MVE_VSHLL_T2:
14925797
AV		 6270 case MVE_VMOVN:
6271 if (arm_decode_field (given, 18, 19) == 2)
6272 {
6273 *undefined_code = UNDEF_SIZE_2;
78933a4a 6274 return true;
14925797
AV		 6275 }
6276 else
78933a4a 6277 return false;
14925797 6278
d3b63143
AV		 6279 case MVE_VRMLALDAVH:
6280 case MVE_VMLADAV_T1:
6281 case MVE_VMLADAV_T2:
6282 case MVE_VMLALDAV:
6283 if ((arm_decode_field (given, 28, 28) == 1)
6284 && (arm_decode_field (given, 12, 12) == 1))
6285 {
6286 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6287 return true;
d3b63143
AV		 6288 }
6289 else
78933a4a 6290 return false;
d3b63143 6291
ed63aa17
AV		 6292 case MVE_VQSHRN:
6293 case MVE_VQSHRUN:
6294 case MVE_VSHLL_T1:
6295 case MVE_VSHRN:
6296 {
6297 unsigned long sz = arm_decode_field (given, 19, 20);
6298 if (sz == 1)
78933a4a 6299 return false;
ed63aa17 6300 else if ((sz & 2) == 2)
78933a4a 6301 return false;
ed63aa17
AV		 6302 else
6303 {
6304 *undefined_code = UNDEF_SIZE;
78933a4a 6305 return true;
ed63aa17
AV		 6306 }
6307 }
6308 break;
6309
6310 case MVE_VQSHL_T2:
6311 case MVE_VQSHLU_T3:
6312 case MVE_VRSHR:
6313 case MVE_VSHL_T1:
6314 case MVE_VSHR:
6315 case MVE_VSLI:
6316 case MVE_VSRI:
6317 {
6318 unsigned long sz = arm_decode_field (given, 19, 21);
6319 if ((sz & 7) == 1)
78933a4a 6320 return false;
ed63aa17 6321 else if ((sz & 6) == 2)
78933a4a 6322 return false;
ed63aa17 6323 else if ((sz & 4) == 4)
78933a4a 6324 return false;
ed63aa17
AV		 6325 else
6326 {
6327 *undefined_code = UNDEF_SIZE;
78933a4a 6328 return true;
ed63aa17
AV		 6329 }
6330 }
6331
6332 case MVE_VQRSHRN:
6333 case MVE_VQRSHRUN:
6334 if (arm_decode_field (given, 19, 20) == 0)
6335 {
6336 *undefined_code = UNDEF_SIZE_0;
78933a4a 6337 return true;
ed63aa17
AV		 6338 }
6339 else
78933a4a 6340 return false;
ed63aa17 6341
66dcaa5d
AV		 6342 case MVE_VABS_VEC:
6343 if (arm_decode_field (given, 18, 19) == 3)
6344 {
6345 *undefined_code = UNDEF_SIZE_3;
78933a4a 6346 return true;
66dcaa5d
AV		 6347 }
6348 else
78933a4a 6349 return false;
66dcaa5d 6350
14b456f2
AV		 6351 case MVE_VQNEG:
6352 case MVE_VQABS:
f49bb598 6353 case MVE_VNEG_VEC:
e523f101
AV		 6354 case MVE_VCLS:
6355 case MVE_VCLZ:
6356 if (arm_decode_field (given, 18, 19) == 3)
6357 {
6358 *undefined_code = UNDEF_SIZE_3;
78933a4a 6359 return true;
e523f101
AV		 6360 }
6361 else
78933a4a 6362 return false;
e523f101 6363
14b456f2
AV		 6364 case MVE_VREV16:
6365 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6366 return false;
14b456f2
AV		 6367 else
6368 {
6369 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6370 return true;
14b456f2
AV		 6371 }
6372
6373 case MVE_VREV32:
6374 {
6375 unsigned long size = arm_decode_field (given, 18, 19);
6376 if ((size & 2) == 2)
6377 {
6378 *undefined_code = UNDEF_SIZE_2;
78933a4a 6379 return true;
14b456f2
AV		 6380 }
6381 else
78933a4a 6382 return false;
14b456f2
AV		 6383 }
6384
6385 case MVE_VREV64:
6386 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6387 return false;
14b456f2
AV		 6388 else
6389 {
6390 *undefined_code = UNDEF_SIZE_3;
78933a4a 6391 return true;
14b456f2
AV		 6392 }
6393
9743db03 6394 default:
78933a4a 6395 return false;
9743db03 6396 }
73cd51e5
AV		 6397}
6398
6399/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6400 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6401 why this encoding is unpredictable. */
6402
78933a4a 6403static bool
73cd51e5
AV		 6404is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6405 enum mve_unpredictable *unpredictable_code)
6406{
6407 *unpredictable_code = UNPRED_NONE;
6408
143275ea
AV		 6409 switch (matched_insn)
6410 {
6411 case MVE_VCMP_FP_T2:
6412 case MVE_VPT_FP_T2:
6413 if ((arm_decode_field (given, 12, 12) == 0)
6414 && (arm_decode_field (given, 5, 5) == 1))
6415 {
6416 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6417 return true;
143275ea
AV		 6418 }
6419 else
78933a4a 6420 return false;
73cd51e5 6421
143275ea
AV		 6422 case MVE_VPT_VEC_T4:
6423 case MVE_VPT_VEC_T5:
6424 case MVE_VPT_VEC_T6:
6425 case MVE_VCMP_VEC_T4:
6426 case MVE_VCMP_VEC_T5:
6427 case MVE_VCMP_VEC_T6:
6428 if (arm_decode_field (given, 0, 3) == 0xd)
6429 {
6430 *unpredictable_code = UNPRED_R13;
78933a4a 6431 return true;
143275ea
AV		 6432 }
6433 else
78933a4a 6434 return false;
c1e26897 6435
9743db03
AV		 6436 case MVE_VDUP:
6437 {
6438 unsigned long gpr = arm_decode_field (given, 12, 15);
6439 if (gpr == 0xd)
6440 {
6441 *unpredictable_code = UNPRED_R13;
78933a4a 6442 return true;
9743db03
AV		 6443 }
6444 else if (gpr == 0xf)
6445 {
6446 *unpredictable_code = UNPRED_R15;
78933a4a 6447 return true;
9743db03
AV		 6448 }
6449
78933a4a 6450 return false;
9743db03
AV		 6451 }
6452
14b456f2
AV		 6453 case MVE_VQADD_T2:
6454 case MVE_VQSUB_T2:
f49bb598
AV		 6455 case MVE_VMUL_FP_T2:
6456 case MVE_VMUL_VEC_T2:
56858bea 6457 case MVE_VMLA:
e523f101 6458 case MVE_VBRSR:
66dcaa5d
AV		 6459 case MVE_VADD_FP_T2:
6460 case MVE_VSUB_FP_T2:
6461 case MVE_VADD_VEC_T2:
6462 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6463 case MVE_VQRSHL_T2:
6464 case MVE_VQSHL_T1:
6465 case MVE_VRSHL_T2:
6466 case MVE_VSHL_T2:
6467 case MVE_VSHLC:
d3b63143
AV		 6468 case MVE_VQDMLAH:
6469 case MVE_VQRDMLAH:
6470 case MVE_VQDMLASH:
6471 case MVE_VQRDMLASH:
6472 case MVE_VQDMULH_T3:
6473 case MVE_VQRDMULH_T4:
6474 case MVE_VMLAS:
9743db03
AV		 6475 case MVE_VFMA_FP_SCALAR:
6476 case MVE_VFMAS_FP_SCALAR:
6477 case MVE_VHADD_T2:
6478 case MVE_VHSUB_T2:
6479 {
6480 unsigned long gpr = arm_decode_field (given, 0, 3);
6481 if (gpr == 0xd)
6482 {
6483 *unpredictable_code = UNPRED_R13;
78933a4a 6484 return true;
9743db03
AV		 6485 }
6486 else if (gpr == 0xf)
6487 {
6488 *unpredictable_code = UNPRED_R15;
78933a4a 6489 return true;
9743db03
AV		 6490 }
6491
78933a4a 6492 return false;
9743db03
AV		 6493 }
6494
04d54ace
AV		 6495 case MVE_VLD2:
6496 case MVE_VST2:
6497 {
6498 unsigned long rn = arm_decode_field (given, 16, 19);
6499
6500 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6501 {
6502 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6503 return true;
04d54ace
AV		 6504 }
6505
6506 if (rn == 0xf)
6507 {
6508 *unpredictable_code = UNPRED_R15;
78933a4a 6509 return true;
04d54ace
AV		 6510 }
6511
6512 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6513 {
6514 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6515 return true;
04d54ace
AV		 6516 }
6517 else
78933a4a 6518 return false;
04d54ace
AV		 6519 }
6520
6521 case MVE_VLD4:
6522 case MVE_VST4:
6523 {
6524 unsigned long rn = arm_decode_field (given, 16, 19);
6525
6526 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6527 {
6528 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6529 return true;
04d54ace
AV		 6530 }
6531
6532 if (rn == 0xf)
6533 {
6534 *unpredictable_code = UNPRED_R15;
78933a4a 6535 return true;
04d54ace
AV		 6536 }
6537
6538 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6539 {
6540 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6541 return true;
04d54ace
AV		 6542 }
6543 else
78933a4a 6544 return false;
04d54ace
AV		 6545 }
6546
aef6d006
AV		 6547 case MVE_VLDRB_T5:
6548 case MVE_VLDRH_T6:
6549 case MVE_VLDRW_T7:
6550 case MVE_VSTRB_T5:
6551 case MVE_VSTRH_T6:
6552 case MVE_VSTRW_T7:
6553 {
6554 unsigned long rn = arm_decode_field (given, 16, 19);
6555
6556 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6557 {
6558 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6559 return true;
aef6d006
AV		 6560 }
6561 else if (rn == 0xf)
6562 {
6563 *unpredictable_code = UNPRED_R15;
78933a4a 6564 return true;
aef6d006
AV		 6565 }
6566 else
78933a4a 6567 return false;
aef6d006
AV		 6568 }
6569
ef1576a1
AV		 6570 case MVE_VLDRB_GATHER_T1:
6571 if (arm_decode_field (given, 0, 0) == 1)
6572 {
6573 *unpredictable_code = UNPRED_OS;
78933a4a 6574 return true;
ef1576a1
AV		 6575 }
6576
6577 /* fall through. */
6578 /* To handle common code with T2-T4 variants. */
6579 case MVE_VLDRH_GATHER_T2:
6580 case MVE_VLDRW_GATHER_T3:
6581 case MVE_VLDRD_GATHER_T4:
6582 {
6583 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6584 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6585
6586 if (qd == qm)
6587 {
6588 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6589 return true;
ef1576a1
AV		 6590 }
6591
6592 if (arm_decode_field (given, 16, 19) == 0xf)
6593 {
6594 *unpredictable_code = UNPRED_R15;
78933a4a 6595 return true;
ef1576a1
AV		 6596 }
6597
78933a4a 6598 return false;
ef1576a1
AV		 6599 }
6600
6601 case MVE_VLDRW_GATHER_T5:
6602 case MVE_VLDRD_GATHER_T6:
6603 {
6604 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6605 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6606
6607 if (qd == qm)
6608 {
6609 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6610 return true;
ef1576a1
AV		 6611 }
6612 else
78933a4a 6613 return false;
ef1576a1
AV		 6614 }
6615
6616 case MVE_VSTRB_SCATTER_T1:
6617 if (arm_decode_field (given, 16, 19) == 0xf)
6618 {
6619 *unpredictable_code = UNPRED_R15;
78933a4a 6620 return true;
ef1576a1
AV		 6621 }
6622 else if (arm_decode_field (given, 0, 0) == 1)
6623 {
6624 *unpredictable_code = UNPRED_OS;
78933a4a 6625 return true;
ef1576a1
AV		 6626 }
6627 else
78933a4a 6628 return false;
ef1576a1
AV		 6629
6630 case MVE_VSTRH_SCATTER_T2:
6631 case MVE_VSTRW_SCATTER_T3:
6632 case MVE_VSTRD_SCATTER_T4:
6633 if (arm_decode_field (given, 16, 19) == 0xf)
6634 {
6635 *unpredictable_code = UNPRED_R15;
78933a4a 6636 return true;
ef1576a1
AV		 6637 }
6638 else
78933a4a 6639 return false;
ef1576a1 6640
c507f10b
AV		 6641 case MVE_VMOV2_VEC_LANE_TO_GP:
6642 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6643 case MVE_VCVT_BETWEEN_FP_INT:
6644 case MVE_VCVT_FROM_FP_TO_INT:
6645 {
6646 unsigned long rt = arm_decode_field (given, 0, 3);
6647 unsigned long rt2 = arm_decode_field (given, 16, 19);
6648
6649 if ((rt == 0xd) || (rt2 == 0xd))
6650 {
6651 *unpredictable_code = UNPRED_R13;
78933a4a 6652 return true;
bf0b396d
AV		 6653 }
6654 else if ((rt == 0xf) || (rt2 == 0xf))
6655 {
6656 *unpredictable_code = UNPRED_R15;
78933a4a 6657 return true;
bf0b396d
AV		 6658 }
6659 else if (rt == rt2)
6660 {
6661 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6662 return true;
bf0b396d
AV		 6663 }
6664
78933a4a 6665 return false;
bf0b396d
AV		 6666 }
6667
56858bea
AV		 6668 case MVE_VMAXV:
6669 case MVE_VMAXAV:
6670 case MVE_VMAXNMV_FP:
6671 case MVE_VMAXNMAV_FP:
6672 case MVE_VMINNMV_FP:
6673 case MVE_VMINNMAV_FP:
6674 case MVE_VMINV:
6675 case MVE_VMINAV:
66dcaa5d 6676 case MVE_VABAV:
c507f10b
AV		 6677 case MVE_VMOV_HFP_TO_GP:
6678 case MVE_VMOV_GP_TO_VEC_LANE:
6679 case MVE_VMOV_VEC_LANE_TO_GP:
6680 {
6681 unsigned long rda = arm_decode_field (given, 12, 15);
6682 if (rda == 0xd)
6683 {
6684 *unpredictable_code = UNPRED_R13;
78933a4a 6685 return true;
c507f10b
AV		 6686 }
6687 else if (rda == 0xf)
6688 {
6689 *unpredictable_code = UNPRED_R15;
78933a4a 6690 return true;
c507f10b
AV		 6691 }
6692
78933a4a 6693 return false;
c507f10b
AV		 6694 }
6695
14925797
AV		 6696 case MVE_VMULL_INT:
6697 {
6698 unsigned long Qd;
6699 unsigned long Qm;
6700 unsigned long Qn;
6701
6702 if (arm_decode_field (given, 20, 21) == 2)
6703 {
6704 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6705 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6706 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6707
6708 if ((Qd == Qn) || (Qd == Qm))
6709 {
6710 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6711 return true;
14925797
AV		 6712 }
6713 else
78933a4a 6714 return false;
14925797
AV		 6715 }
6716 else
78933a4a 6717 return false;
14925797
AV		 6718 }
6719
897b9bbc 6720 case MVE_VCMUL_FP:
14925797
AV		 6721 case MVE_VQDMULL_T1:
6722 {
6723 unsigned long Qd;
6724 unsigned long Qm;
6725 unsigned long Qn;
6726
6727 if (arm_decode_field (given, 28, 28) == 1)
6728 {
6729 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6730 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6731 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6732
6733 if ((Qd == Qn) || (Qd == Qm))
6734 {
6735 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6736 return true;
14925797
AV		 6737 }
6738 else
78933a4a 6739 return false;
14925797
AV		 6740 }
6741 else
78933a4a 6742 return false;
14925797
AV		 6743 }
6744
6745 case MVE_VQDMULL_T2:
6746 {
6747 unsigned long gpr = arm_decode_field (given, 0, 3);
6748 if (gpr == 0xd)
6749 {
6750 *unpredictable_code = UNPRED_R13;
78933a4a 6751 return true;
14925797
AV		 6752 }
6753 else if (gpr == 0xf)
6754 {
6755 *unpredictable_code = UNPRED_R15;
78933a4a 6756 return true;
14925797
AV		 6757 }
6758
6759 if (arm_decode_field (given, 28, 28) == 1)
6760 {
6761 unsigned long Qd
6762 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6763 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6764
a9d96ab9 6765 if (Qd == Qn)
14925797
AV		 6766 {
6767 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6768 return true;
14925797
AV		 6769 }
6770 else
78933a4a 6771 return false;
14925797
AV		 6772 }
6773
78933a4a 6774 return false;
14925797
AV		 6775 }
6776
d3b63143
AV		 6777 case MVE_VMLSLDAV:
6778 case MVE_VRMLSLDAVH:
6779 case MVE_VMLALDAV:
6780 case MVE_VADDLV:
6781 if (arm_decode_field (given, 20, 22) == 6)
6782 {
6783 *unpredictable_code = UNPRED_R13;
78933a4a 6784 return true;
d3b63143
AV		 6785 }
6786 else
78933a4a 6787 return false;
d3b63143 6788
1c8f2df8
AV		 6789 case MVE_VDWDUP:
6790 case MVE_VIWDUP:
6791 if (arm_decode_field (given, 1, 3) == 6)
6792 {
6793 *unpredictable_code = UNPRED_R13;
78933a4a 6794 return true;
1c8f2df8
AV		 6795 }
6796 else
78933a4a 6797 return false;
1c8f2df8 6798
897b9bbc
AV		 6799 case MVE_VCADD_VEC:
6800 case MVE_VHCADD:
6801 {
6802 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6803 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6804 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6805 {
6806 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6807 return true;
897b9bbc
AV		 6808 }
6809 else
78933a4a 6810 return false;
897b9bbc
AV		 6811 }
6812
6813 case MVE_VCADD_FP:
6814 {
6815 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6816 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6817 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6818 {
6819 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6820 return true;
897b9bbc
AV		 6821 }
6822 else
78933a4a 6823 return false;
897b9bbc
AV		 6824 }
6825
6826 case MVE_VCMLA_FP:
6827 {
6828 unsigned long Qda;
6829 unsigned long Qm;
6830 unsigned long Qn;
6831
6832 if (arm_decode_field (given, 20, 20) == 1)
6833 {
6834 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6835 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6836 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6837
6838 if ((Qda == Qn) || (Qda == Qm))
6839 {
6840 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6841 return true;
897b9bbc
AV		 6842 }
6843 else
78933a4a 6844 return false;
897b9bbc
AV		 6845 }
6846 else
78933a4a 6847 return false;
897b9bbc
AV		 6848
6849 }
6850
e523f101
AV		 6851 case MVE_VCTP:
6852 if (arm_decode_field (given, 16, 19) == 0xd)
6853 {
6854 *unpredictable_code = UNPRED_R13;
78933a4a 6855 return true;
e523f101
AV		 6856 }
6857 else
78933a4a 6858 return false;
e523f101 6859
14b456f2
AV		 6860 case MVE_VREV64:
6861 {
6862 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6863 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6864
6865 if (qd == qm)
6866 {
6867 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6868 return true;
14b456f2
AV		 6869 }
6870 else
78933a4a 6871 return false;
14b456f2
AV		 6872 }
6873
23d00a41
SD		 6874 case MVE_LSLL:
6875 case MVE_LSLLI:
6876 case MVE_LSRL:
6877 case MVE_ASRL:
6878 case MVE_ASRLI:
6879 case MVE_UQSHLL:
6880 case MVE_UQRSHLL:
6881 case MVE_URSHRL:
6882 case MVE_SRSHRL:
6883 case MVE_SQSHLL:
6884 case MVE_SQRSHRL:
6885 {
6886 unsigned long gpr = arm_decode_field (given, 9, 11);
6887 gpr = ((gpr << 1) | 1);
6888 if (gpr == 0xd)
6889 {
6890 *unpredictable_code = UNPRED_R13;
78933a4a 6891 return true;
23d00a41
SD		 6892 }
6893 else if (gpr == 0xf)
6894 {
6895 *unpredictable_code = UNPRED_R15;
78933a4a 6896 return true;
23d00a41
SD		 6897 }
6898
78933a4a 6899 return false;
23d00a41
SD		 6900 }
6901
143275ea 6902 default:
78933a4a 6903 return false;
143275ea
AV		 6904 }
6905}
c1e26897 6906
c507f10b
AV		 6907static void
6908print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6909{
6910 unsigned long op1 = arm_decode_field (given, 21, 22);
6911 unsigned long op2 = arm_decode_field (given, 5, 6);
6912 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6913 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6914 void *stream = info->stream;
6915 fprintf_ftype func = info->fprintf_func;
6916
6917 if ((op1 & 0x2) == 0x2)
6918 {
43dd7626 6919 index_operand = op2;
c507f10b
AV		 6920 esize = 8;
6921 }
6922 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6923 {
43dd7626 6924 index_operand = op2 >> 1;
c507f10b
AV		 6925 esize = 16;
6926 }
6927 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6928 {
43dd7626 6929 index_operand = 0;
c507f10b
AV		 6930 esize = 32;
6931 }
6932 else
6933 {
6934 func (stream, "<undefined index>");
6935 return;
6936 }
6937
6938 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6939 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6940
6941 func (stream, "%lu", idx);
6942}
6943
6944/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6945 in length and integer of floating-point type. */
6946static void
6947print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6948 unsigned int ibit_loc, const struct mopcode32 *insn)
6949{
6950 int bits = 0;
6951 int cmode = (given >> 8) & 0xf;
6952 int op = (given >> 5) & 0x1;
6953 unsigned long value = 0, hival = 0;
6954 unsigned shift;
6955 int size = 0;
6956 int isfloat = 0;
6957 void *stream = info->stream;
6958 fprintf_ftype func = info->fprintf_func;
6959
6960 /* On Neon the 'i' bit is at bit 24, on mve it is
6961 at bit 28. */
6962 bits |= ((given >> ibit_loc) & 1) << 7;
6963 bits |= ((given >> 16) & 7) << 4;
6964 bits |= ((given >> 0) & 15) << 0;
6965
6966 if (cmode < 8)
6967 {
6968 shift = (cmode >> 1) & 3;
6969 value = (unsigned long) bits << (8 * shift);
6970 size = 32;
6971 }
6972 else if (cmode < 12)
6973 {
6974 shift = (cmode >> 1) & 1;
6975 value = (unsigned long) bits << (8 * shift);
6976 size = 16;
6977 }
6978 else if (cmode < 14)
6979 {
6980 shift = (cmode & 1) + 1;
6981 value = (unsigned long) bits << (8 * shift);
6982 value |= (1ul << (8 * shift)) - 1;
6983 size = 32;
6984 }
6985 else if (cmode == 14)
6986 {
6987 if (op)
6988 {
6989 /* Bit replication into bytes. */
6990 int ix;
6991 unsigned long mask;
6992
6993 value = 0;
6994 hival = 0;
6995 for (ix = 7; ix >= 0; ix--)
6996 {
6997 mask = ((bits >> ix) & 1) ? 0xff : 0;
6998 if (ix <= 3)
6999 value = (value << 8) | mask;
7000 else
7001 hival = (hival << 8) | mask;
7002 }
7003 size = 64;
7004 }
7005 else
7006 {
7007 /* Byte replication. */
7008 value = (unsigned long) bits;
7009 size = 8;
7010 }
7011 }
7012 else if (!op)
7013 {
7014 /* Floating point encoding. */
7015 int tmp;
7016
7017 value = (unsigned long) (bits & 0x7f) << 19;
7018 value |= (unsigned long) (bits & 0x80) << 24;
7019 tmp = bits & 0x40 ? 0x3c : 0x40;
7020 value |= (unsigned long) tmp << 24;
7021 size = 32;
7022 isfloat = 1;
7023 }
7024 else
7025 {
7026 func (stream, "<illegal constant %.8x:%x:%x>",
7027 bits, cmode, op);
7028 size = 32;
7029 return;
7030 }
7031
279edac5
AM		 7032 /* printU determines whether the immediate value should be printed as
7033 unsigned. */
c507f10b
AV		 7034 unsigned printU = 0;
7035 switch (insn->mve_op)
7036 {
7037 default:
7038 break;
279edac5 7039 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 7040 case MVE_VBIC_IMM:
7041 case MVE_VORR_IMM:
7042 case MVE_VMVN_IMM:
7043 case MVE_VMOV_IMM_TO_VEC:
7044 printU = 1;
7045 break;
7046 }
7047 switch (size)
7048 {
7049 case 8:
7050 func (stream, "#%ld\t; 0x%.2lx", value, value);
7051 break;
7052
7053 case 16:
7054 func (stream,
7055 printU
7056 ? "#%lu\t; 0x%.4lx"
7057 : "#%ld\t; 0x%.4lx", value, value);
7058 break;
7059
7060 case 32:
7061 if (isfloat)
7062 {
7063 unsigned char valbytes[4];
7064 double fvalue;
7065
7066 /* Do this a byte at a time so we don't have to
7067 worry about the host's endianness. */
7068 valbytes[0] = value & 0xff;
7069 valbytes[1] = (value >> 8) & 0xff;
7070 valbytes[2] = (value >> 16) & 0xff;
7071 valbytes[3] = (value >> 24) & 0xff;
7072
7073 floatformat_to_double
7074 (& floatformat_ieee_single_little, valbytes,
7075 & fvalue);
7076
7077 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7078 value);
7079 }
7080 else
7081 func (stream,
7082 printU
7083 ? "#%lu\t; 0x%.8lx"
7084 : "#%ld\t; 0x%.8lx",
7085 (long) (((value & 0x80000000L) != 0)
7086 && !printU
7087 ? value | ~0xffffffffL : value),
7088 value);
7089 break;
7090
7091 case 64:
7092 func (stream, "#0x%.8lx%.8lx", hival, value);
7093 break;
7094
7095 default:
7096 abort ();
7097 }
7098
7099}
7100
73cd51e5
AV		 7101static void
7102print_mve_undefined (struct disassemble_info *info,
7103 enum mve_undefined undefined_code)
7104{
7105 void *stream = info->stream;
7106 fprintf_ftype func = info->fprintf_func;
7107
7108 func (stream, "\t\tundefined instruction: ");
7109
7110 switch (undefined_code)
7111 {
ed63aa17
AV		 7112 case UNDEF_SIZE:
7113 func (stream, "illegal size");
7114 break;
7115
aef6d006
AV		 7116 case UNDEF_SIZE_0:
7117 func (stream, "size equals zero");
7118 break;
7119
c507f10b
AV		 7120 case UNDEF_SIZE_2:
7121 func (stream, "size equals two");
7122 break;
7123
9743db03
AV		 7124 case UNDEF_SIZE_3:
7125 func (stream, "size equals three");
7126 break;
7127
aef6d006
AV		 7128 case UNDEF_SIZE_LE_1:
7129 func (stream, "size <= 1");
7130 break;
7131
14b456f2
AV		 7132 case UNDEF_SIZE_NOT_0:
7133 func (stream, "size not equal to 0");
7134 break;
7135
ef1576a1
AV		 7136 case UNDEF_SIZE_NOT_2:
7137 func (stream, "size not equal to 2");
7138 break;
7139
7140 case UNDEF_SIZE_NOT_3:
7141 func (stream, "size not equal to 3");
7142 break;
7143
7144 case UNDEF_NOT_UNS_SIZE_0:
7145 func (stream, "not unsigned and size = zero");
7146 break;
7147
7148 case UNDEF_NOT_UNS_SIZE_1:
7149 func (stream, "not unsigned and size = one");
7150 break;
7151
7152 case UNDEF_NOT_UNSIGNED:
7153 func (stream, "not unsigned");
7154 break;
7155
bf0b396d
AV		 7156 case UNDEF_VCVT_IMM6:
7157 func (stream, "invalid imm6");
7158 break;
7159
7160 case UNDEF_VCVT_FSI_IMM6:
7161 func (stream, "fsi = 0 and invalid imm6");
7162 break;
7163
c507f10b
AV		 7164 case UNDEF_BAD_OP1_OP2:
7165 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7166 break;
7167
7168 case UNDEF_BAD_U_OP1_OP2:
7169 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7170 break;
7171
7172 case UNDEF_OP_0_BAD_CMODE:
7173 func (stream, "op field equal 0 and bad cmode");
7174 break;
7175
d3b63143
AV		 7176 case UNDEF_XCHG_UNS:
7177 func (stream, "exchange and unsigned together");
7178 break;
7179
73cd51e5
AV		 7180 case UNDEF_NONE:
7181 break;
7182 }
7183
7184}
7185
7186static void
7187print_mve_unpredictable (struct disassemble_info *info,
7188 enum mve_unpredictable unpredict_code)
7189{
7190 void *stream = info->stream;
7191 fprintf_ftype func = info->fprintf_func;
7192
7193 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7194
7195 switch (unpredict_code)
7196 {
7197 case UNPRED_IT_BLOCK:
7198 func (stream, "mve instruction in it block");
7199 break;
7200
143275ea
AV		 7201 case UNPRED_FCA_0_FCB_1:
7202 func (stream, "condition bits, fca = 0 and fcb = 1");
7203 break;
7204
7205 case UNPRED_R13:
7206 func (stream, "use of r13 (sp)");
7207 break;
7208
9743db03
AV		 7209 case UNPRED_R15:
7210 func (stream, "use of r15 (pc)");
7211 break;
7212
04d54ace
AV		 7213 case UNPRED_Q_GT_4:
7214 func (stream, "start register block > r4");
7215 break;
7216
7217 case UNPRED_Q_GT_6:
7218 func (stream, "start register block > r6");
7219 break;
7220
7221 case UNPRED_R13_AND_WB:
7222 func (stream, "use of r13 and write back");
7223 break;
7224
ef1576a1
AV		 7225 case UNPRED_Q_REGS_EQUAL:
7226 func (stream,
7227 "same vector register used for destination and other operand");
7228 break;
7229
7230 case UNPRED_OS:
7231 func (stream, "use of offset scaled");
7232 break;
7233
bf0b396d
AV		 7234 case UNPRED_GP_REGS_EQUAL:
7235 func (stream, "same general-purpose register used for both operands");
7236 break;
7237
c507f10b
AV		 7238 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7239 func (stream, "use of identical q registers and size = 1");
7240 break;
7241
7242 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7243 func (stream, "use of identical q registers and size = 1");
7244 break;
7245
73cd51e5
AV		 7246 case UNPRED_NONE:
7247 break;
7248 }
7249}
7250
04d54ace
AV		 7251/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7252
7253static void
7254print_mve_register_blocks (struct disassemble_info *info,
7255 unsigned long given,
7256 enum mve_instructions matched_insn)
7257{
7258 void *stream = info->stream;
7259 fprintf_ftype func = info->fprintf_func;
7260
7261 unsigned long q_reg_start = arm_decode_field_multiple (given,
7262 13, 15,
7263 22, 22);
7264 switch (matched_insn)
7265 {
7266 case MVE_VLD2:
7267 case MVE_VST2:
7268 if (q_reg_start <= 6)
7269 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7270 else
7271 func (stream, "<illegal reg q%ld>", q_reg_start);
7272 break;
7273
7274 case MVE_VLD4:
7275 case MVE_VST4:
7276 if (q_reg_start <= 4)
7277 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7278 q_reg_start + 1, q_reg_start + 2,
7279 q_reg_start + 3);
7280 else
7281 func (stream, "<illegal reg q%ld>", q_reg_start);
7282 break;
7283
7284 default:
7285 break;
7286 }
7287}
7288
bf0b396d
AV		 7289static void
7290print_mve_rounding_mode (struct disassemble_info *info,
7291 unsigned long given,
7292 enum mve_instructions matched_insn)
7293{
7294 void *stream = info->stream;
7295 fprintf_ftype func = info->fprintf_func;
7296
7297 switch (matched_insn)
7298 {
7299 case MVE_VCVT_FROM_FP_TO_INT:
7300 {
7301 switch (arm_decode_field (given, 8, 9))
7302 {
7303 case 0:
7304 func (stream, "a");
7305 break;
7306
7307 case 1:
7308 func (stream, "n");
7309 break;
7310
7311 case 2:
7312 func (stream, "p");
7313 break;
7314
7315 case 3:
7316 func (stream, "m");
7317 break;
7318
7319 default:
7320 break;
7321 }
7322 }
7323 break;
7324
7325 case MVE_VRINT_FP:
7326 {
7327 switch (arm_decode_field (given, 7, 9))
7328 {
7329 case 0:
7330 func (stream, "n");
7331 break;
7332
7333 case 1:
7334 func (stream, "x");
7335 break;
7336
7337 case 2:
7338 func (stream, "a");
7339 break;
7340
7341 case 3:
7342 func (stream, "z");
7343 break;
7344
7345 case 5:
7346 func (stream, "m");
7347 break;
7348
7349 case 7:
7350 func (stream, "p");
7351
7352 case 4:
7353 case 6:
7354 default:
7355 break;
7356 }
7357 }
7358 break;
7359
7360 default:
7361 break;
7362 }
7363}
7364
7365static void
7366print_mve_vcvt_size (struct disassemble_info *info,
7367 unsigned long given,
7368 enum mve_instructions matched_insn)
7369{
7370 unsigned long mode = 0;
7371 void *stream = info->stream;
7372 fprintf_ftype func = info->fprintf_func;
7373
7374 switch (matched_insn)
7375 {
7376 case MVE_VCVT_FP_FIX_VEC:
7377 {
7378 mode = (((given & 0x200) >> 7)
7379 | ((given & 0x10000000) >> 27)
7380 | ((given & 0x100) >> 8));
7381
7382 switch (mode)
7383 {
7384 case 0:
7385 func (stream, "f16.s16");
7386 break;
7387
7388 case 1:
7389 func (stream, "s16.f16");
7390 break;
7391
7392 case 2:
7393 func (stream, "f16.u16");
7394 break;
7395
7396 case 3:
7397 func (stream, "u16.f16");
7398 break;
7399
7400 case 4:
7401 func (stream, "f32.s32");
7402 break;
7403
7404 case 5:
7405 func (stream, "s32.f32");
7406 break;
7407
7408 case 6:
7409 func (stream, "f32.u32");
7410 break;
7411
7412 case 7:
7413 func (stream, "u32.f32");
7414 break;
7415
7416 default:
7417 break;
7418 }
7419 break;
7420 }
7421 case MVE_VCVT_BETWEEN_FP_INT:
7422 {
7423 unsigned long size = arm_decode_field (given, 18, 19);
7424 unsigned long op = arm_decode_field (given, 7, 8);
7425
7426 if (size == 1)
7427 {
7428 switch (op)
7429 {
7430 case 0:
7431 func (stream, "f16.s16");
7432 break;
7433
7434 case 1:
7435 func (stream, "f16.u16");
7436 break;
7437
7438 case 2:
7439 func (stream, "s16.f16");
7440 break;
7441
7442 case 3:
7443 func (stream, "u16.f16");
7444 break;
7445
7446 default:
7447 break;
7448 }
7449 }
7450 else if (size == 2)
7451 {
7452 switch (op)
7453 {
7454 case 0:
7455 func (stream, "f32.s32");
7456 break;
7457
7458 case 1:
7459 func (stream, "f32.u32");
7460 break;
7461
7462 case 2:
7463 func (stream, "s32.f32");
7464 break;
7465
7466 case 3:
7467 func (stream, "u32.f32");
7468 break;
7469 }
7470 }
7471 }
7472 break;
7473
7474 case MVE_VCVT_FP_HALF_FP:
7475 {
7476 unsigned long op = arm_decode_field (given, 28, 28);
7477 if (op == 0)
7478 func (stream, "f16.f32");
7479 else if (op == 1)
7480 func (stream, "f32.f16");
7481 }
7482 break;
7483
7484 case MVE_VCVT_FROM_FP_TO_INT:
7485 {
7486 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7487
7488 switch (size)
7489 {
7490 case 2:
7491 func (stream, "s16.f16");
7492 break;
7493
7494 case 3:
7495 func (stream, "u16.f16");
7496 break;
7497
7498 case 4:
7499 func (stream, "s32.f32");
7500 break;
7501
7502 case 5:
7503 func (stream, "u32.f32");
7504 break;
7505
7506 default:
7507 break;
7508 }
7509 }
7510 break;
7511
7512 default:
7513 break;
7514 }
7515}
7516
897b9bbc
AV		 7517static void
7518print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7519 unsigned long rot_width)
7520{
7521 void *stream = info->stream;
7522 fprintf_ftype func = info->fprintf_func;
7523
7524 if (rot_width == 1)
7525 {
7526 switch (rot)
7527 {
7528 case 0:
7529 func (stream, "90");
7530 break;
7531 case 1:
7532 func (stream, "270");
7533 break;
7534 default:
7535 break;
7536 }
7537 }
7538 else if (rot_width == 2)
7539 {
7540 switch (rot)
7541 {
7542 case 0:
7543 func (stream, "0");
7544 break;
7545 case 1:
7546 func (stream, "90");
7547 break;
7548 case 2:
7549 func (stream, "180");
7550 break;
7551 case 3:
7552 func (stream, "270");
7553 break;
7554 default:
7555 break;
7556 }
7557 }
7558}
7559
143275ea
AV		 7560static void
7561print_instruction_predicate (struct disassemble_info *info)
7562{
7563 void *stream = info->stream;
7564 fprintf_ftype func = info->fprintf_func;
7565
7566 if (vpt_block_state.next_pred_state == PRED_THEN)
7567 func (stream, "t");
7568 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7569 func (stream, "e");
7570}
7571
7572static void
7573print_mve_size (struct disassemble_info *info,
7574 unsigned long size,
7575 enum mve_instructions matched_insn)
7576{
7577 void *stream = info->stream;
7578 fprintf_ftype func = info->fprintf_func;
7579
7580 switch (matched_insn)
7581 {
66dcaa5d
AV		 7582 case MVE_VABAV:
7583 case MVE_VABD_VEC:
7584 case MVE_VABS_FP:
7585 case MVE_VABS_VEC:
7586 case MVE_VADD_VEC_T1:
7587 case MVE_VADD_VEC_T2:
d3b63143 7588 case MVE_VADDV:
e523f101 7589 case MVE_VBRSR:
897b9bbc 7590 case MVE_VCADD_VEC:
e523f101
AV		 7591 case MVE_VCLS:
7592 case MVE_VCLZ:
143275ea
AV		 7593 case MVE_VCMP_VEC_T1:
7594 case MVE_VCMP_VEC_T2:
7595 case MVE_VCMP_VEC_T3:
7596 case MVE_VCMP_VEC_T4:
7597 case MVE_VCMP_VEC_T5:
7598 case MVE_VCMP_VEC_T6:
e523f101 7599 case MVE_VCTP:
1c8f2df8
AV		 7600 case MVE_VDDUP:
7601 case MVE_VDWDUP:
9743db03
AV		 7602 case MVE_VHADD_T1:
7603 case MVE_VHADD_T2:
897b9bbc 7604 case MVE_VHCADD:
9743db03
AV		 7605 case MVE_VHSUB_T1:
7606 case MVE_VHSUB_T2:
1c8f2df8
AV		 7607 case MVE_VIDUP:
7608 case MVE_VIWDUP:
04d54ace
AV		 7609 case MVE_VLD2:
7610 case MVE_VLD4:
ef1576a1
AV		 7611 case MVE_VLDRB_GATHER_T1:
7612 case MVE_VLDRH_GATHER_T2:
7613 case MVE_VLDRW_GATHER_T3:
7614 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7615 case MVE_VLDRB_T1:
7616 case MVE_VLDRH_T2:
56858bea
AV		 7617 case MVE_VMAX:
7618 case MVE_VMAXA:
7619 case MVE_VMAXV:
7620 case MVE_VMAXAV:
7621 case MVE_VMIN:
7622 case MVE_VMINA:
7623 case MVE_VMINV:
7624 case MVE_VMINAV:
7625 case MVE_VMLA:
d3b63143 7626 case MVE_VMLAS:
f49bb598
AV		 7627 case MVE_VMUL_VEC_T1:
7628 case MVE_VMUL_VEC_T2:
7629 case MVE_VMULH:
7630 case MVE_VRMULH:
7631 case MVE_VMULL_INT:
7632 case MVE_VNEG_FP:
7633 case MVE_VNEG_VEC:
143275ea
AV		 7634 case MVE_VPT_VEC_T1:
7635 case MVE_VPT_VEC_T2:
7636 case MVE_VPT_VEC_T3:
7637 case MVE_VPT_VEC_T4:
7638 case MVE_VPT_VEC_T5:
7639 case MVE_VPT_VEC_T6:
14b456f2
AV		 7640 case MVE_VQABS:
7641 case MVE_VQADD_T1:
7642 case MVE_VQADD_T2:
d3b63143
AV		 7643 case MVE_VQDMLADH:
7644 case MVE_VQRDMLADH:
7645 case MVE_VQDMLAH:
7646 case MVE_VQRDMLAH:
7647 case MVE_VQDMLASH:
7648 case MVE_VQRDMLASH:
7649 case MVE_VQDMLSDH:
7650 case MVE_VQRDMLSDH:
7651 case MVE_VQDMULH_T1:
7652 case MVE_VQRDMULH_T2:
7653 case MVE_VQDMULH_T3:
7654 case MVE_VQRDMULH_T4:
14b456f2 7655 case MVE_VQNEG:
ed63aa17
AV		 7656 case MVE_VQRSHL_T1:
7657 case MVE_VQRSHL_T2:
7658 case MVE_VQSHL_T1:
7659 case MVE_VQSHL_T4:
14b456f2
AV		 7660 case MVE_VQSUB_T1:
7661 case MVE_VQSUB_T2:
7662 case MVE_VREV32:
7663 case MVE_VREV64:
9743db03 7664 case MVE_VRHADD:
bf0b396d 7665 case MVE_VRINT_FP:
ed63aa17
AV		 7666 case MVE_VRSHL_T1:
7667 case MVE_VRSHL_T2:
7668 case MVE_VSHL_T2:
7669 case MVE_VSHL_T3:
7670 case MVE_VSHLL_T2:
04d54ace
AV		 7671 case MVE_VST2:
7672 case MVE_VST4:
ef1576a1
AV		 7673 case MVE_VSTRB_SCATTER_T1:
7674 case MVE_VSTRH_SCATTER_T2:
7675 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7676 case MVE_VSTRB_T1:
7677 case MVE_VSTRH_T2:
66dcaa5d
AV		 7678 case MVE_VSUB_VEC_T1:
7679 case MVE_VSUB_VEC_T2:
143275ea
AV		 7680 if (size <= 3)
7681 func (stream, "%s", mve_vec_sizename[size]);
7682 else
7683 func (stream, "<undef size>");
7684 break;
7685
66dcaa5d
AV		 7686 case MVE_VABD_FP:
7687 case MVE_VADD_FP_T1:
7688 case MVE_VADD_FP_T2:
7689 case MVE_VSUB_FP_T1:
7690 case MVE_VSUB_FP_T2:
143275ea
AV		 7691 case MVE_VCMP_FP_T1:
7692 case MVE_VCMP_FP_T2:
9743db03
AV		 7693 case MVE_VFMA_FP_SCALAR:
7694 case MVE_VFMA_FP:
7695 case MVE_VFMS_FP:
7696 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7697 case MVE_VMAXNM_FP:
7698 case MVE_VMAXNMA_FP:
7699 case MVE_VMAXNMV_FP:
7700 case MVE_VMAXNMAV_FP:
7701 case MVE_VMINNM_FP:
7702 case MVE_VMINNMA_FP:
7703 case MVE_VMINNMV_FP:
7704 case MVE_VMINNMAV_FP:
f49bb598
AV		 7705 case MVE_VMUL_FP_T1:
7706 case MVE_VMUL_FP_T2:
143275ea
AV		 7707 case MVE_VPT_FP_T1:
7708 case MVE_VPT_FP_T2:
7709 if (size == 0)
7710 func (stream, "32");
7711 else if (size == 1)
7712 func (stream, "16");
7713 break;
7714
897b9bbc
AV		 7715 case MVE_VCADD_FP:
7716 case MVE_VCMLA_FP:
7717 case MVE_VCMUL_FP:
d3b63143
AV		 7718 case MVE_VMLADAV_T1:
7719 case MVE_VMLALDAV:
7720 case MVE_VMLSDAV_T1:
7721 case MVE_VMLSLDAV:
14925797
AV		 7722 case MVE_VMOVN:
7723 case MVE_VQDMULL_T1:
7724 case MVE_VQDMULL_T2:
7725 case MVE_VQMOVN:
7726 case MVE_VQMOVUN:
7727 if (size == 0)
7728 func (stream, "16");
7729 else if (size == 1)
7730 func (stream, "32");
7731 break;
7732
7733 case MVE_VMOVL:
7734 if (size == 1)
7735 func (stream, "8");
7736 else if (size == 2)
7737 func (stream, "16");
7738 break;
7739
9743db03
AV		 7740 case MVE_VDUP:
7741 switch (size)
7742 {
7743 case 0:
7744 func (stream, "32");
7745 break;
7746 case 1:
7747 func (stream, "16");
7748 break;
7749 case 2:
7750 func (stream, "8");
7751 break;
7752 default:
7753 break;
7754 }
7755 break;
7756
c507f10b
AV		 7757 case MVE_VMOV_GP_TO_VEC_LANE:
7758 case MVE_VMOV_VEC_LANE_TO_GP:
7759 switch (size)
7760 {
7761 case 0: case 4:
7762 func (stream, "32");
7763 break;
7764
7765 case 1: case 3:
7766 case 5: case 7:
7767 func (stream, "16");
7768 break;
7769
7770 case 8: case 9: case 10: case 11:
7771 case 12: case 13: case 14: case 15:
7772 func (stream, "8");
7773 break;
7774
7775 default:
7776 break;
7777 }
7778 break;
7779
7780 case MVE_VMOV_IMM_TO_VEC:
7781 switch (size)
7782 {
7783 case 0: case 4: case 8:
7784 case 12: case 24: case 26:
7785 func (stream, "i32");
7786 break;
7787 case 16: case 20:
7788 func (stream, "i16");
7789 break;
7790 case 28:
7791 func (stream, "i8");
7792 break;
7793 case 29:
7794 func (stream, "i64");
7795 break;
7796 case 30:
7797 func (stream, "f32");
7798 break;
7799 default:
7800 break;
7801 }
7802 break;
7803
14925797
AV		 7804 case MVE_VMULL_POLY:
7805 if (size == 0)
7806 func (stream, "p8");
7807 else if (size == 1)
7808 func (stream, "p16");
7809 break;
7810
c507f10b
AV		 7811 case MVE_VMVN_IMM:
7812 switch (size)
7813 {
7814 case 0: case 2: case 4:
7815 case 6: case 12: case 13:
7816 func (stream, "32");
7817 break;
7818
7819 case 8: case 10:
7820 func (stream, "16");
7821 break;
7822
7823 default:
7824 break;
7825 }
7826 break;
7827
7828 case MVE_VBIC_IMM:
7829 case MVE_VORR_IMM:
7830 switch (size)
7831 {
7832 case 1: case 3:
7833 case 5: case 7:
7834 func (stream, "32");
7835 break;
7836
7837 case 9: case 11:
7838 func (stream, "16");
7839 break;
7840
7841 default:
7842 break;
7843 }
7844 break;
7845
ed63aa17
AV		 7846 case MVE_VQSHRN:
7847 case MVE_VQSHRUN:
7848 case MVE_VQRSHRN:
7849 case MVE_VQRSHRUN:
7850 case MVE_VRSHRN:
7851 case MVE_VSHRN:
7852 {
7853 switch (size)
7854 {
7855 case 1:
7856 func (stream, "16");
7857 break;
7858
7859 case 2: case 3:
7860 func (stream, "32");
7861 break;
7862
7863 default:
7864 break;
7865 }
7866 }
7867 break;
7868
7869 case MVE_VQSHL_T2:
7870 case MVE_VQSHLU_T3:
7871 case MVE_VRSHR:
7872 case MVE_VSHL_T1:
7873 case MVE_VSHLL_T1:
7874 case MVE_VSHR:
7875 case MVE_VSLI:
7876 case MVE_VSRI:
7877 {
7878 switch (size)
7879 {
7880 case 1:
7881 func (stream, "8");
7882 break;
7883
7884 case 2: case 3:
7885 func (stream, "16");
7886 break;
7887
7888 case 4: case 5: case 6: case 7:
7889 func (stream, "32");
7890 break;
7891
7892 default:
7893 break;
7894 }
7895 }
7896 break;
7897
143275ea
AV		 7898 default:
7899 break;
7900 }
7901}
7902
ed63aa17
AV		 7903static void
7904print_mve_shift_n (struct disassemble_info *info, long given,
7905 enum mve_instructions matched_insn)
7906{
7907 void *stream = info->stream;
7908 fprintf_ftype func = info->fprintf_func;
7909
7910 int startAt0
7911 = matched_insn == MVE_VQSHL_T2
7912 || matched_insn == MVE_VQSHLU_T3
7913 || matched_insn == MVE_VSHL_T1
7914 || matched_insn == MVE_VSHLL_T1
7915 || matched_insn == MVE_VSLI;
7916
7917 unsigned imm6 = (given & 0x3f0000) >> 16;
7918
7919 if (matched_insn == MVE_VSHLL_T1)
7920 imm6 &= 0x1f;
7921
7922 unsigned shiftAmount = 0;
7923 if ((imm6 & 0x20) != 0)
7924 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7925 else if ((imm6 & 0x10) != 0)
7926 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7927 else if ((imm6 & 0x08) != 0)
7928 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7929 else
7930 print_mve_undefined (info, UNDEF_SIZE_0);
7931
7932 func (stream, "%u", shiftAmount);
7933}
7934
143275ea
AV		 7935static void
7936print_vec_condition (struct disassemble_info *info, long given,
7937 enum mve_instructions matched_insn)
7938{
7939 void *stream = info->stream;
7940 fprintf_ftype func = info->fprintf_func;
7941 long vec_cond = 0;
7942
7943 switch (matched_insn)
7944 {
7945 case MVE_VPT_FP_T1:
7946 case MVE_VCMP_FP_T1:
7947 vec_cond = (((given & 0x1000) >> 10)
7948 | ((given & 1) << 1)
7949 | ((given & 0x0080) >> 7));
7950 func (stream, "%s",vec_condnames[vec_cond]);
7951 break;
7952
7953 case MVE_VPT_FP_T2:
7954 case MVE_VCMP_FP_T2:
7955 vec_cond = (((given & 0x1000) >> 10)
7956 | ((given & 0x0020) >> 4)
7957 | ((given & 0x0080) >> 7));
7958 func (stream, "%s",vec_condnames[vec_cond]);
7959 break;
7960
7961 case MVE_VPT_VEC_T1:
7962 case MVE_VCMP_VEC_T1:
7963 vec_cond = (given & 0x0080) >> 7;
7964 func (stream, "%s",vec_condnames[vec_cond]);
7965 break;
7966
7967 case MVE_VPT_VEC_T2:
7968 case MVE_VCMP_VEC_T2:
7969 vec_cond = 2 | ((given & 0x0080) >> 7);
7970 func (stream, "%s",vec_condnames[vec_cond]);
7971 break;
7972
7973 case MVE_VPT_VEC_T3:
7974 case MVE_VCMP_VEC_T3:
7975 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7976 func (stream, "%s",vec_condnames[vec_cond]);
7977 break;
7978
7979 case MVE_VPT_VEC_T4:
7980 case MVE_VCMP_VEC_T4:
7981 vec_cond = (given & 0x0080) >> 7;
7982 func (stream, "%s",vec_condnames[vec_cond]);
7983 break;
7984
7985 case MVE_VPT_VEC_T5:
7986 case MVE_VCMP_VEC_T5:
7987 vec_cond = 2 | ((given & 0x0080) >> 7);
7988 func (stream, "%s",vec_condnames[vec_cond]);
7989 break;
7990
7991 case MVE_VPT_VEC_T6:
7992 case MVE_VCMP_VEC_T6:
7993 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7994 func (stream, "%s",vec_condnames[vec_cond]);
7995 break;
7996
7997 case MVE_NONE:
7998 case MVE_VPST:
7999 default:
8000 break;
8001 }
8002}
8003
8004#define W_BIT 21
8005#define I_BIT 22
8006#define U_BIT 23
8007#define P_BIT 24
8008
8009#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8010#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8011#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8012#define PRE_BIT_SET (given & (1 << P_BIT))
8013
8014
8f06b2d8
PB		 8015/* Print one coprocessor instruction on INFO->STREAM.
8016 Return TRUE if the instuction matched, FALSE if this is not a
8017 recognised coprocessor instruction. */
8018
78933a4a 8019static bool
33593eaf
MM		 8020print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8021 bfd_vma pc,
8022 struct disassemble_info *info,
8023 long given,
78933a4a 8024 bool thumb)
8f06b2d8 8025{
6b0dd094 8026 const struct sopcode32 *insn;
8f06b2d8
PB		 8027 void *stream = info->stream;
8028 fprintf_ftype func = info->fprintf_func;
8029 unsigned long mask;
2edcd244 8030 unsigned long value = 0;
c22aaad1 8031 int cond;
8afc7bea 8032 int cp_num;
823d2571
TG		 8033 struct arm_private_data *private_data = info->private_data;
8034 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8035 arm_feature_set arm_ext_v8_1m_main =
8036 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 8037
5b616bef 8038 allowed_arches = private_data->features;
8f06b2d8 8039
33593eaf 8040 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8041 {
ff4a8d2b 8042 unsigned long u_reg = 16;
78933a4a 8043 bool is_unpredictable = false;
05413229 8044 signed long value_in_comment = 0;
0313a2b8
NC		 8045 const char *c;
8046
823d2571 8047 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8048 switch (insn->value)
8049 {
8050 case SENTINEL_IWMMXT_START:
8051 if (info->mach != bfd_mach_arm_XScale
8052 && info->mach != bfd_mach_arm_iWMMXt
8053 && info->mach != bfd_mach_arm_iWMMXt2)
8054 do
8055 insn++;
823d2571
TG		 8056 while ((! ARM_FEATURE_ZERO (insn->arch))
8057 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8058 continue;
8059
8060 case SENTINEL_IWMMXT_END:
8061 continue;
8062
8063 case SENTINEL_GENERIC_START:
5b616bef 8064 allowed_arches = private_data->features;
05413229
NC		 8065 continue;
8066
8067 default:
8068 abort ();
8069 }
8f06b2d8
PB		 8070
8071 mask = insn->mask;
8072 value = insn->value;
8afc7bea
RL		 8073 cp_num = (given >> 8) & 0xf;
8074
8f06b2d8
PB		 8075 if (thumb)
8076 {
8077 /* The high 4 bits are 0xe for Arm conditional instructions, and
8078 0xe for arm unconditional instructions. The rest of the
8079 encoding is the same. */
8080 mask |= 0xf0000000;
8081 value |= 0xe0000000;
c22aaad1
PB		 8082 if (ifthen_state)
8083 cond = IFTHEN_COND;
8084 else
e2efe87d 8085 cond = COND_UNCOND;
8f06b2d8
PB		 8086 }
8087 else
8088 {
8089 /* Only match unconditional instuctions against unconditional
8090 patterns. */
8091 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8092 {
8093 mask |= 0xf0000000;
e2efe87d 8094 cond = COND_UNCOND;
c22aaad1
PB		 8095 }
8096 else
8097 {
8098 cond = (given >> 28) & 0xf;
8099 if (cond == 0xe)
e2efe87d 8100 cond = COND_UNCOND;
c22aaad1 8101 }
8f06b2d8 8102 }
823d2571 8103
6b0dd094
AV		 8104 if ((insn->isa == T32 && !thumb)
8105 || (insn->isa == ARM && thumb))
8106 continue;
8107
0313a2b8
NC		 8108 if ((given & mask) != value)
8109 continue;
8f06b2d8 8110
823d2571 8111 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8112 continue;
8113
8afc7bea
RL		 8114 if (insn->value == 0xfe000010 /* mcr2 */
8115 || insn->value == 0xfe100010 /* mrc2 */
8116 || insn->value == 0xfc100000 /* ldc2 */
8117 || insn->value == 0xfc000000) /* stc2 */
8118 {
b0c11777 8119 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 8120 is_unpredictable = true;
f08d8ce3
AV		 8121
8122 /* Armv8.1-M Mainline FP & MVE instructions. */
8123 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8124 && !ARM_CPU_IS_ANY (allowed_arches)
8125 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8126 continue;
8127
8afc7bea
RL		 8128 }
8129 else if (insn->value == 0x0e000000 /* cdp */
8130 || insn->value == 0xfe000000 /* cdp2 */
8131 || insn->value == 0x0e000010 /* mcr */
8132 || insn->value == 0x0e100010 /* mrc */
8133 || insn->value == 0x0c100000 /* ldc */
8134 || insn->value == 0x0c000000) /* stc */
8135 {
8136 /* Floating-point instructions. */
b0c11777 8137 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8138 continue;
32c36c3c
AV		 8139
8140 /* Armv8.1-M Mainline FP & MVE instructions. */
8141 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8142 && !ARM_CPU_IS_ANY (allowed_arches)
8143 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8144 continue;
8afc7bea 8145 }
aef6d006
AV		 8146 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8147 || insn->value == 0xec000f80) /* vstr (system register) */
8148 && arm_decode_field (given, 24, 24) == 0
8149 && arm_decode_field (given, 21, 21) == 0)
8150 /* If the P and W bits are both 0 then these encodings match the MVE
8151 VLDR and VSTR instructions, these are in a different table, so we
8152 don't let it match here. */
8153 continue;
8154
0313a2b8
NC		 8155 for (c = insn->assembler; *c; c++)
8156 {
8157 if (*c == '%')
8f06b2d8 8158 {
32c36c3c
AV		 8159 const char mod = *++c;
8160 switch (mod)
8f06b2d8 8161 {
0313a2b8
NC		 8162 case '%':
8163 func (stream, "%%");
8164 break;
8165
8166 case 'A':
32c36c3c 8167 case 'K':
05413229 8168 {
79862e45 8169 int rn = (given >> 16) & 0xf;
b0c11777 8170 bfd_vma offset = given & 0xff;
0313a2b8 8171
32c36c3c
AV		 8172 if (mod == 'K')
8173 offset = given & 0x7f;
8174
05413229 8175 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8176
79862e45
DJ		 8177 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8178 {
8179 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8180 if (cp_num == 9)
8181 /* vldr.16/vstr.16 will shift the address
8182 left by 1 bit only. */
8183 offset = offset * 2;
8184 else
8185 offset = offset * 4;
8186
79862e45
DJ		 8187 if (NEGATIVE_BIT_SET)
8188 offset = - offset;
8189 if (rn != 15)
8190 value_in_comment = offset;
8191 }
8192
c1e26897 8193 if (PRE_BIT_SET)
05413229
NC		 8194 {
8195 if (offset)
fe56b6ce 8196 func (stream, ", #%d]%s",
d908c8af 8197 (int) offset,
c1e26897 8198 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8199 else if (NEGATIVE_BIT_SET)
8200 func (stream, ", #-0]");
05413229
NC		 8201 else
8202 func (stream, "]");
8203 }
8204 else
8205 {
0313a2b8 8206 func (stream, "]");
8f06b2d8 8207
c1e26897 8208 if (WRITEBACK_BIT_SET)
05413229
NC		 8209 {
8210 if (offset)
d908c8af 8211 func (stream, ", #%d", (int) offset);
26d97720
NS		 8212 else if (NEGATIVE_BIT_SET)
8213 func (stream, ", #-0");
05413229
NC		 8214 }
8215 else
fe56b6ce 8216 {
26d97720
NS		 8217 func (stream, ", {%s%d}",
8218 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8219 (int) offset);
fe56b6ce
NC		 8220 value_in_comment = offset;
8221 }
05413229 8222 }
79862e45
DJ		 8223 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8224 {
8225 func (stream, "\t; ");
6844b2c2
MGD		 8226 /* For unaligned PCs, apply off-by-alignment
8227 correction. */
43e65147 8228 info->print_address_func (offset + pc
6844b2c2
MGD		 8229 + info->bytes_per_chunk * 2
8230 - (pc & 3),
dffaa15c 8231 info);
79862e45 8232 }
05413229 8233 }
0313a2b8 8234 break;
8f06b2d8 8235
0313a2b8
NC		 8236 case 'B':
8237 {
8238 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8239 int offset = (given >> 1) & 0x3f;
8240
8241 if (offset == 1)
8242 func (stream, "{d%d}", regno);
8243 else if (regno + offset > 32)
8244 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8245 else
8246 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8247 }
8248 break;
8f06b2d8 8249
efd6b359
AV		 8250 case 'C':
8251 {
78933a4a 8252 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8253 char reg_prefix = single ? 's' : 'd';
8254 int Dreg = (given >> 22) & 0x1;
8255 int Vdreg = (given >> 12) & 0xf;
8256 int reg = single ? ((Vdreg << 1) | Dreg)
8257 : ((Dreg << 4) | Vdreg);
8258 int num = (given >> (single ? 0 : 1)) & 0x7f;
8259 int maxreg = single ? 31 : 15;
8260 int topreg = reg + num - 1;
8261
8262 if (!num)
8263 func (stream, "{VPR}");
8264 else if (num == 1)
8265 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8266 else if (topreg > maxreg)
8267 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8268 reg_prefix, reg, single ? topreg >> 1 : topreg);
8269 else
8270 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8271 reg_prefix, topreg);
8272 }
8273 break;
8274
e2efe87d
MGD		 8275 case 'u':
8276 if (cond != COND_UNCOND)
78933a4a 8277 is_unpredictable = true;
e2efe87d
MGD		 8278
8279 /* Fall through. */
0313a2b8 8280 case 'c':
b0c11777 8281 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8282 is_unpredictable = true;
b0c11777 8283
aab2c27d
MM		 8284 /* Fall through. */
8285 case 'b':
0313a2b8
NC		 8286 func (stream, "%s", arm_conditional[cond]);
8287 break;
8f06b2d8 8288
0313a2b8
NC		 8289 case 'I':
8290 /* Print a Cirrus/DSP shift immediate. */
8291 /* Immediates are 7bit signed ints with bits 0..3 in
8292 bits 0..3 of opcode and bits 4..6 in bits 5..7
8293 of opcode. */
8294 {
8295 int imm;
8f06b2d8 8296
0313a2b8 8297 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8298
0313a2b8
NC		 8299 /* Is ``imm'' a negative number? */
8300 if (imm & 0x40)
24b4cf66 8301 imm -= 0x80;
8f06b2d8 8302
0313a2b8
NC		 8303 func (stream, "%d", imm);
8304 }
8305
8306 break;
8f06b2d8 8307
32c36c3c
AV		 8308 case 'J':
8309 {
73cd51e5
AV		 8310 unsigned long regno
8311 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8312
8313 switch (regno)
8314 {
8315 case 0x1:
8316 func (stream, "FPSCR");
8317 break;
8318 case 0x2:
8319 func (stream, "FPSCR_nzcvqc");
8320 break;
8321 case 0xc:
8322 func (stream, "VPR");
8323 break;
8324 case 0xd:
8325 func (stream, "P0");
8326 break;
8327 case 0xe:
8328 func (stream, "FPCXTNS");
8329 break;
8330 case 0xf:
8331 func (stream, "FPCXTS");
8332 break;
8333 default:
73cd51e5 8334 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8335 break;
8336 }
8337 }
8338 break;
8339
0313a2b8
NC		 8340 case 'F':
8341 switch (given & 0x00408000)
8342 {
8343 case 0:
8344 func (stream, "4");
8345 break;
8346 case 0x8000:
8347 func (stream, "1");
8348 break;
8349 case 0x00400000:
8350 func (stream, "2");
8f06b2d8 8351 break;
0313a2b8
NC		 8352 default:
8353 func (stream, "3");
8354 }
8355 break;
8f06b2d8 8356
0313a2b8
NC		 8357 case 'P':
8358 switch (given & 0x00080080)
8359 {
8360 case 0:
8361 func (stream, "s");
8362 break;
8363 case 0x80:
8364 func (stream, "d");
8365 break;
8366 case 0x00080000:
8367 func (stream, "e");
8368 break;
8369 default:
8370 func (stream, _("<illegal precision>"));
8f06b2d8 8371 break;
0313a2b8
NC		 8372 }
8373 break;
8f06b2d8 8374
0313a2b8
NC		 8375 case 'Q':
8376 switch (given & 0x00408000)
8377 {
8378 case 0:
8379 func (stream, "s");
8f06b2d8 8380 break;
0313a2b8
NC		 8381 case 0x8000:
8382 func (stream, "d");
8f06b2d8 8383 break;
0313a2b8
NC		 8384 case 0x00400000:
8385 func (stream, "e");
8386 break;
8387 default:
8388 func (stream, "p");
8f06b2d8 8389 break;
0313a2b8
NC		 8390 }
8391 break;
8f06b2d8 8392
0313a2b8
NC		 8393 case 'R':
8394 switch (given & 0x60)
8395 {
8396 case 0:
8397 break;
8398 case 0x20:
8399 func (stream, "p");
8400 break;
8401 case 0x40:
8402 func (stream, "m");
8403 break;
8404 default:
8405 func (stream, "z");
8406 break;
8407 }
8408 break;
16980d0b 8409
0313a2b8
NC		 8410 case '0': case '1': case '2': case '3': case '4':
8411 case '5': case '6': case '7': case '8': case '9':
8412 {
8413 int width;
8f06b2d8 8414
0313a2b8 8415 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8416
0313a2b8
NC		 8417 switch (*c)
8418 {
ff4a8d2b
NC		 8419 case 'R':
8420 if (value == 15)
78933a4a 8421 is_unpredictable = true;
ff4a8d2b 8422 /* Fall through. */
0313a2b8 8423 case 'r':
ff4a8d2b
NC		 8424 if (c[1] == 'u')
8425 {
8426 /* Eat the 'u' character. */
8427 ++ c;
8428
8429 if (u_reg == value)
78933a4a 8430 is_unpredictable = true;
ff4a8d2b
NC		 8431 u_reg = value;
8432 }
0313a2b8
NC		 8433 func (stream, "%s", arm_regnames[value]);
8434 break;
c28eeff2
SN		 8435 case 'V':
8436 if (given & (1 << 6))
8437 goto Q;
8438 /* FALLTHROUGH */
0313a2b8
NC		 8439 case 'D':
8440 func (stream, "d%ld", value);
8441 break;
8442 case 'Q':
c28eeff2 8443 Q:
0313a2b8
NC		 8444 if (value & 1)
8445 func (stream, "<illegal reg q%ld.5>", value >> 1);
8446 else
8447 func (stream, "q%ld", value >> 1);
8448 break;
8449 case 'd':
8450 func (stream, "%ld", value);
05413229 8451 value_in_comment = value;
0313a2b8 8452 break;
6f1c2142
AM		 8453 case 'E':
8454 {
8455 /* Converts immediate 8 bit back to float value. */
8456 unsigned floatVal = (value & 0x80) << 24
8457 | (value & 0x3F) << 19
8458 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8459
8460 /* Quarter float have a maximum value of 31.0.
8461 Get floating point value multiplied by 1e7.
8462 The maximum value stays in limit of a 32-bit int. */
8463 unsigned decVal =
8464 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8465 (16 + (value & 0xF));
8466
8467 if (!(decVal % 1000000))
8468 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8469 floatVal, value & 0x80 ? '-' : ' ',
8470 decVal / 10000000,
8471 decVal % 10000000 / 1000000);
8472 else if (!(decVal % 10000))
8473 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8474 floatVal, value & 0x80 ? '-' : ' ',
8475 decVal / 10000000,
8476 decVal % 10000000 / 10000);
8477 else
8478 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8479 floatVal, value & 0x80 ? '-' : ' ',
8480 decVal / 10000000, decVal % 10000000);
8481 break;
8482 }
0313a2b8
NC		 8483 case 'k':
8484 {
8485 int from = (given & (1 << 7)) ? 32 : 16;
8486 func (stream, "%ld", from - value);
8487 }
8488 break;
8f06b2d8 8489
0313a2b8
NC		 8490 case 'f':
8491 if (value > 7)
8492 func (stream, "#%s", arm_fp_const[value & 7]);
8493 else
8494 func (stream, "f%ld", value);
8495 break;
4146fd53 8496
0313a2b8
NC		 8497 case 'w':
8498 if (width == 2)
8499 func (stream, "%s", iwmmxt_wwnames[value]);
8500 else
8501 func (stream, "%s", iwmmxt_wwssnames[value]);
8502 break;
4146fd53 8503
0313a2b8
NC		 8504 case 'g':
8505 func (stream, "%s", iwmmxt_regnames[value]);
8506 break;
8507 case 'G':
8508 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8509 break;
8f06b2d8 8510
0313a2b8 8511 case 'x':
d1aaab3c 8512 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8513 break;
8f06b2d8 8514
33399f07
MGD		 8515 case 'c':
8516 switch (value)
8517 {
8518 case 0:
8519 func (stream, "eq");
8520 break;
8521
8522 case 1:
8523 func (stream, "vs");
8524 break;
8525
8526 case 2:
8527 func (stream, "ge");
8528 break;
8529
8530 case 3:
8531 func (stream, "gt");
8532 break;
8533
8534 default:
8535 func (stream, "??");
8536 break;
8537 }
8538 break;
8539
0313a2b8
NC		 8540 case '`':
8541 c++;
8542 if (value == 0)
8543 func (stream, "%c", *c);
8544 break;
8545 case '\'':
8546 c++;
8547 if (value == ((1ul << width) - 1))
8548 func (stream, "%c", *c);
8549 break;
8550 case '?':
fe56b6ce 8551 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8552 c += 1 << width;
8553 break;
8554 default:
8555 abort ();
8556 }
dffaa15c
AM		 8557 }
8558 break;
0313a2b8 8559
dffaa15c
AM		 8560 case 'y':
8561 case 'z':
8562 {
8563 int single = *c++ == 'y';
8564 int regno;
8f06b2d8 8565
dffaa15c
AM		 8566 switch (*c)
8567 {
8568 case '4': /* Sm pair */
8569 case '0': /* Sm, Dm */
8570 regno = given & 0x0000000f;
8571 if (single)
8572 {
8573 regno <<= 1;
8574 regno += (given >> 5) & 1;
8575 }
8576 else
8577 regno += ((given >> 5) & 1) << 4;
8578 break;
8f06b2d8 8579
dffaa15c
AM		 8580 case '1': /* Sd, Dd */
8581 regno = (given >> 12) & 0x0000000f;
8582 if (single)
8583 {
8584 regno <<= 1;
8585 regno += (given >> 22) & 1;
8586 }
8587 else
8588 regno += ((given >> 22) & 1) << 4;
8589 break;
7df76b80 8590
dffaa15c
AM		 8591 case '2': /* Sn, Dn */
8592 regno = (given >> 16) & 0x0000000f;
8593 if (single)
8594 {
8595 regno <<= 1;
8596 regno += (given >> 7) & 1;
8597 }
8598 else
8599 regno += ((given >> 7) & 1) << 4;
8600 break;
a7f8487e 8601
dffaa15c
AM		 8602 case '3': /* List */
8603 func (stream, "{");
8604 regno = (given >> 12) & 0x0000000f;
8605 if (single)
8606 {
8607 regno <<= 1;
8608 regno += (given >> 22) & 1;
8609 }
8610 else
8611 regno += ((given >> 22) & 1) << 4;
8612 break;
a7f8487e 8613
dffaa15c
AM		 8614 default:
8615 abort ();
8616 }
0313a2b8 8617
dffaa15c 8618 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8619
dffaa15c
AM		 8620 if (*c == '3')
8621 {
8622 int count = given & 0xff;
b34976b6 8623
dffaa15c
AM		 8624 if (single == 0)
8625 count >>= 1;
0313a2b8 8626
dffaa15c
AM		 8627 if (--count)
8628 {
8629 func (stream, "-%c%d",
8630 single ? 's' : 'd',
8631 regno + count);
8632 }
0313a2b8 8633
dffaa15c 8634 func (stream, "}");
0313a2b8 8635 }
dffaa15c
AM		 8636 else if (*c == '4')
8637 func (stream, ", %c%d", single ? 's' : 'd',
8638 regno + 1);
8639 }
8640 break;
b34976b6 8641
dffaa15c
AM		 8642 case 'L':
8643 switch (given & 0x00400100)
0313a2b8 8644 {
dffaa15c
AM		 8645 case 0x00000000: func (stream, "b"); break;
8646 case 0x00400000: func (stream, "h"); break;
8647 case 0x00000100: func (stream, "w"); break;
8648 case 0x00400100: func (stream, "d"); break;
8649 default:
8650 break;
0313a2b8 8651 }
dffaa15c 8652 break;
2d447fca 8653
dffaa15c
AM		 8654 case 'Z':
8655 {
8656 /* given (20, 23) | given (0, 3) */
8657 value = ((given >> 16) & 0xf0) | (given & 0xf);
8658 func (stream, "%d", (int) value);
8659 }
8660 break;
0313a2b8 8661
dffaa15c
AM		 8662 case 'l':
8663 /* This is like the 'A' operator, except that if
8664 the width field "M" is zero, then the offset is
8665 *not* multiplied by four. */
8666 {
8667 int offset = given & 0xff;
8668 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8669
dffaa15c 8670 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8671
dffaa15c
AM		 8672 if (multiplier > 1)
8673 {
8674 value_in_comment = offset * multiplier;
8675 if (NEGATIVE_BIT_SET)
8676 value_in_comment = - value_in_comment;
8677 }
0313a2b8 8678
dffaa15c
AM		 8679 if (offset)
8680 {
8681 if (PRE_BIT_SET)
8682 func (stream, ", #%s%d]%s",
8683 NEGATIVE_BIT_SET ? "-" : "",
8684 offset * multiplier,
8685 WRITEBACK_BIT_SET ? "!" : "");
8686 else
8687 func (stream, "], #%s%d",
8688 NEGATIVE_BIT_SET ? "-" : "",
8689 offset * multiplier);
8690 }
8691 else
8692 func (stream, "]");
8693 }
8694 break;
2d447fca 8695
dffaa15c
AM		 8696 case 'r':
8697 {
8698 int imm4 = (given >> 4) & 0xf;
8699 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8700 int ubit = ! NEGATIVE_BIT_SET;
8701 const char *rm = arm_regnames [given & 0xf];
8702 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8703
dffaa15c
AM		 8704 switch (puw_bits)
8705 {
8706 case 1:
8707 case 3:
8708 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8709 if (imm4)
8710 func (stream, ", lsl #%d", imm4);
8711 break;
0313a2b8 8712
dffaa15c
AM		 8713 case 4:
8714 case 5:
8715 case 6:
8716 case 7:
8717 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8718 if (imm4 > 0)
8719 func (stream, ", lsl #%d", imm4);
8720 func (stream, "]");
8721 if (puw_bits == 5 || puw_bits == 7)
8722 func (stream, "!");
8723 break;
2d447fca 8724
dffaa15c
AM		 8725 default:
8726 func (stream, "INVALID");
8727 }
8728 }
8729 break;
0313a2b8 8730
dffaa15c
AM		 8731 case 'i':
8732 {
8733 long imm5;
8734 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8735 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8736 }
dffaa15c
AM		 8737 break;
8738
8739 default:
8740 abort ();
252b5132 8741 }
252b5132 8742 }
0313a2b8
NC		 8743 else
8744 func (stream, "%c", *c);
252b5132 8745 }
05413229
NC		 8746
8747 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8748 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8749
ff4a8d2b
NC		 8750 if (is_unpredictable)
8751 func (stream, UNPREDICTABLE_INSTRUCTION);
8752
78933a4a 8753 return true;
252b5132 8754 }
78933a4a 8755 return false;
252b5132
RH		 8756}
8757
78933a4a 8758static bool
33593eaf
MM		 8759print_insn_coprocessor (bfd_vma pc,
8760 struct disassemble_info *info,
8761 long given,
78933a4a 8762 bool thumb)
33593eaf
MM		 8763{
8764 return print_insn_coprocessor_1 (coprocessor_opcodes,
8765 pc, info, given, thumb);
8766}
8767
78933a4a 8768static bool
33593eaf
MM		 8769print_insn_generic_coprocessor (bfd_vma pc,
8770 struct disassemble_info *info,
8771 long given,
78933a4a 8772 bool thumb)
33593eaf
MM		 8773{
8774 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8775 pc, info, given, thumb);
8776}
8777
05413229
NC		 8778/* Decodes and prints ARM addressing modes. Returns the offset
8779 used in the address, if any, if it is worthwhile printing the
8780 offset as a hexadecimal value in a comment at the end of the
8781 line of disassembly. */
8782
8783static signed long
62b3e311
PB		 8784print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8785{
8786 void *stream = info->stream;
8787 fprintf_ftype func = info->fprintf_func;
f8b960bc 8788 bfd_vma offset = 0;
62b3e311
PB		 8789
8790 if (((given & 0x000f0000) == 0x000f0000)
8791 && ((given & 0x02000000) == 0))
8792 {
05413229 8793 offset = given & 0xfff;
62b3e311
PB		 8794
8795 func (stream, "[pc");
8796
c1e26897 8797 if (PRE_BIT_SET)
62b3e311 8798 {
26d97720
NS		 8799 /* Pre-indexed. Elide offset of positive zero when
8800 non-writeback. */
8801 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8802 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8803
8804 if (NEGATIVE_BIT_SET)
8805 offset = -offset;
62b3e311
PB		 8806
8807 offset += pc + 8;
8808
8809 /* Cope with the possibility of write-back
8810 being used. Probably a very dangerous thing
8811 for the programmer to do, but who are we to
8812 argue ? */
26d97720 8813 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8814 }
c1e26897 8815 else /* Post indexed. */
62b3e311 8816 {
d908c8af 8817 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8818
c1e26897 8819 /* Ie ignore the offset. */
62b3e311
PB		 8820 offset = pc + 8;
8821 }
8822
8823 func (stream, "\t; ");
8824 info->print_address_func (offset, info);
05413229 8825 offset = 0;
62b3e311
PB		 8826 }
8827 else
8828 {
8829 func (stream, "[%s",
8830 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8831
8832 if (PRE_BIT_SET)
62b3e311
PB		 8833 {
8834 if ((given & 0x02000000) == 0)
8835 {
26d97720 8836 /* Elide offset of positive zero when non-writeback. */
05413229 8837 offset = given & 0xfff;
26d97720 8838 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8839 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8840 }
8841 else
8842 {
26d97720 8843 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8844 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8845 }
8846
8847 func (stream, "]%s",
c1e26897 8848 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8849 }
8850 else
8851 {
8852 if ((given & 0x02000000) == 0)
8853 {
26d97720 8854 /* Always show offset. */
05413229 8855 offset = given & 0xfff;
26d97720 8856 func (stream, "], #%s%d",
d908c8af 8857 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8858 }
8859 else
8860 {
8861 func (stream, "], %s",
c1e26897 8862 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8863 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8864 }
8865 }
84919466
MR		 8866 if (NEGATIVE_BIT_SET)
8867 offset = -offset;
62b3e311 8868 }
05413229
NC		 8869
8870 return (signed long) offset;
62b3e311
PB		 8871}
8872
4934a27c
MM		 8873
8874/* Print one cde instruction on INFO->STREAM.
8875 Return TRUE if the instuction matched, FALSE if this is not a
8876 recognised cde instruction. */
78933a4a
AM		 8877static bool
8878print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 8879{
8880 const struct cdeopcode32 *insn;
8881 void *stream = info->stream;
8882 fprintf_ftype func = info->fprintf_func;
8883
8884 if (thumb)
8885 {
8886 /* Manually extract the coprocessor code from a known point.
8887 This position is the same across all CDE instructions. */
8888 for (insn = cde_opcodes; insn->assembler; insn++)
8889 {
8890 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8891 uint16_t coproc_mask = 1 << coproc;
8892 if (! (coproc_mask & cde_coprocs))
8893 continue;
8894
8895 if ((given & insn->mask) == insn->value)
8896 {
78933a4a 8897 bool is_unpredictable = false;
4934a27c
MM		 8898 const char *c;
8899
8900 for (c = insn->assembler; *c; c++)
8901 {
8902 if (*c == '%')
8903 {
8904 switch (*++c)
8905 {
8906 case '%':
8907 func (stream, "%%");
8908 break;
8909
8910 case '0': case '1': case '2': case '3': case '4':
8911 case '5': case '6': case '7': case '8': case '9':
8912 {
8913 int width;
8914 unsigned long value;
8915
8916 c = arm_decode_bitfield (c, given, &value, &width);
8917
8918 switch (*c)
8919 {
8920 case 'S':
8921 if (value > 10)
78933a4a 8922 is_unpredictable = true;
4934a27c
MM		 8923 /* Fall through. */
8924 case 'R':
8925 if (value == 13)
78933a4a 8926 is_unpredictable = true;
4934a27c
MM		 8927 /* Fall through. */
8928 case 'r':
8929 func (stream, "%s", arm_regnames[value]);
8930 break;
8931
8932 case 'n':
8933 if (value == 15)
8934 func (stream, "%s", "APSR_nzcv");
8935 else
8936 func (stream, "%s", arm_regnames[value]);
8937 break;
8938
8939 case 'T':
8940 func (stream, "%s", arm_regnames[value + 1]);
8941 break;
8942
8943 case 'd':
8944 func (stream, "%ld", value);
8945 break;
8946
5aae9ae9
MM		 8947 case 'V':
8948 if (given & (1 << 6))
8949 func (stream, "q%ld", value >> 1);
8950 else if (given & (1 << 24))
8951 func (stream, "d%ld", value);
8952 else
8953 {
8954 /* Encoding for S register is different than for D and
8955 Q registers. S registers are encoded using the top
8956 single bit in position 22 as the lowest bit of the
8957 register number, while for Q and D it represents the
8958 highest bit of the register number. */
8959 uint8_t top_bit = (value >> 4) & 1;
8960 uint8_t tmp = (value << 1) & 0x1e;
8961 uint8_t res = tmp | top_bit;
8962 func (stream, "s%u", res);
8963 }
8964 break;
8965
4934a27c
MM		 8966 default:
8967 abort ();
8968 }
8969 }
8970 break;
8971
8972 case 'p':
8973 {
8974 uint8_t proc_number = (given >> 8) & 0x7;
8975 func (stream, "p%u", proc_number);
8976 break;
8977 }
8978
8979 case 'a':
8980 {
8981 uint8_t a_offset = 28;
8982 if (given & (1 << a_offset))
8983 func (stream, "a");
8984 break;
8985 }
8986 default:
8987 abort ();
8988 }
8989 }
8990 else
8991 func (stream, "%c", *c);
8992 }
8993
8994 if (is_unpredictable)
8995 func (stream, UNPREDICTABLE_INSTRUCTION);
8996
78933a4a 8997 return true;
4934a27c
MM		 8998 }
8999 }
78933a4a 9000 return false;
4934a27c
MM		 9001 }
9002 else
78933a4a 9003 return false;
4934a27c
MM		 9004}
9005
9006
16980d0b
JB		 9007/* Print one neon instruction on INFO->STREAM.
9008 Return TRUE if the instuction matched, FALSE if this is not a
9009 recognised neon instruction. */
9010
78933a4a
AM		 9011static bool
9012print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 9013{
9014 const struct opcode32 *insn;
9015 void *stream = info->stream;
9016 fprintf_ftype func = info->fprintf_func;
9017
9018 if (thumb)
9019 {
9020 if ((given & 0xef000000) == 0xef000000)
9021 {
0313a2b8 9022 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9023 unsigned long bit28 = given & (1 << 28);
9024
9025 given &= 0x00ffffff;
9026 if (bit28)
9027 given |= 0xf3000000;
9028 else
9029 given |= 0xf2000000;
9030 }
9031 else if ((given & 0xff000000) == 0xf9000000)
9032 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9033 /* BFloat16 neon instructions without special top byte handling. */
9034 else if ((given & 0xff000000) == 0xfe000000
9035 || (given & 0xff000000) == 0xfc000000)
9036 ;
9743db03 9037 /* vdup is also a valid neon instruction. */
e409955d 9038 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 9039 return false;
16980d0b 9040 }
43e65147 9041
16980d0b
JB		 9042 for (insn = neon_opcodes; insn->assembler; insn++)
9043 {
e409955d
FS		 9044 unsigned long cond_mask = insn->mask;
9045 unsigned long cond_value = insn->value;
9046 int cond;
9047
9048 if (thumb)
9049 {
9050 if ((cond_mask & 0xf0000000) == 0) {
9051 /* For the entries in neon_opcodes, an opcode mask/value with
9052 the high 4 bits equal to 0 indicates a conditional
9053 instruction. For thumb however, we need to include those
9054 bits in the instruction matching. */
9055 cond_mask |= 0xf0000000;
9056 /* Furthermore, the thumb encoding of a conditional instruction
9057 will have the high 4 bits equal to 0xe. */
9058 cond_value |= 0xe0000000;
9059 }
9060 if (ifthen_state)
9061 cond = IFTHEN_COND;
9062 else
9063 cond = COND_UNCOND;
9064 }
9065 else
9066 {
9067 if ((given & 0xf0000000) == 0xf0000000)
9068 {
9069 /* If the instruction is unconditional, update the mask to only
9070 match against unconditional opcode values. */
9071 cond_mask |= 0xf0000000;
9072 cond = COND_UNCOND;
9073 }
9074 else
9075 {
9076 cond = (given >> 28) & 0xf;
9077 if (cond == 0xe)
9078 cond = COND_UNCOND;
9079 }
9080 }
9081
9082 if ((given & cond_mask) == cond_value)
16980d0b 9083 {
05413229 9084 signed long value_in_comment = 0;
78933a4a 9085 bool is_unpredictable = false;
16980d0b
JB		 9086 const char *c;
9087
9088 for (c = insn->assembler; *c; c++)
9089 {
9090 if (*c == '%')
9091 {
9092 switch (*++c)
9093 {
9094 case '%':
9095 func (stream, "%%");
9096 break;
9097
e2efe87d
MGD		 9098 case 'u':
9099 if (thumb && ifthen_state)
78933a4a 9100 is_unpredictable = true;
e2efe87d
MGD		 9101
9102 /* Fall through. */
c22aaad1 9103 case 'c':
e409955d 9104 func (stream, "%s", arm_conditional[cond]);
c22aaad1
PB		 9105 break;
9106
16980d0b
JB		 9107 case 'A':
9108 {
43e65147 9109 static const unsigned char enc[16] =
16980d0b
JB		 9110 {
9111 0x4, 0x14, /* st4 0,1 */
9112 0x4, /* st1 2 */
9113 0x4, /* st2 3 */
9114 0x3, /* st3 4 */
9115 0x13, /* st3 5 */
9116 0x3, /* st1 6 */
9117 0x1, /* st1 7 */
9118 0x2, /* st2 8 */
9119 0x12, /* st2 9 */
9120 0x2, /* st1 10 */
9121 0, 0, 0, 0, 0
9122 };
9123 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9124 int rn = ((given >> 16) & 0xf);
9125 int rm = ((given >> 0) & 0xf);
9126 int align = ((given >> 4) & 0x3);
9127 int type = ((given >> 8) & 0xf);
9128 int n = enc[type] & 0xf;
9129 int stride = (enc[type] >> 4) + 1;
9130 int ix;
43e65147 9131
16980d0b
JB		 9132 func (stream, "{");
9133 if (stride > 1)
9134 for (ix = 0; ix != n; ix++)
9135 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9136 else if (n == 1)
9137 func (stream, "d%d", rd);
9138 else
9139 func (stream, "d%d-d%d", rd, rd + n - 1);
9140 func (stream, "}, [%s", arm_regnames[rn]);
9141 if (align)
8e560766 9142 func (stream, " :%d", 32 << align);
16980d0b
JB		 9143 func (stream, "]");
9144 if (rm == 0xd)
9145 func (stream, "!");
9146 else if (rm != 0xf)
9147 func (stream, ", %s", arm_regnames[rm]);
9148 }
9149 break;
43e65147 9150
16980d0b
JB		 9151 case 'B':
9152 {
9153 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9154 int rn = ((given >> 16) & 0xf);
9155 int rm = ((given >> 0) & 0xf);
9156 int idx_align = ((given >> 4) & 0xf);
9157 int align = 0;
9158 int size = ((given >> 10) & 0x3);
9159 int idx = idx_align >> (size + 1);
9160 int length = ((given >> 8) & 3) + 1;
9161 int stride = 1;
9162 int i;
9163
9164 if (length > 1 && size > 0)
9165 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9166
16980d0b
JB		 9167 switch (length)
9168 {
9169 case 1:
9170 {
9171 int amask = (1 << size) - 1;
9172 if ((idx_align & (1 << size)) != 0)
78933a4a 9173 return false;
16980d0b
JB		 9174 if (size > 0)
9175 {
9176 if ((idx_align & amask) == amask)
9177 align = 8 << size;
9178 else if ((idx_align & amask) != 0)
78933a4a 9179 return false;
16980d0b
JB		 9180 }
9181 }
9182 break;
43e65147 9183
16980d0b
JB		 9184 case 2:
9185 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9186 return false;
16980d0b
JB		 9187 align = (idx_align & 1) ? 16 << size : 0;
9188 break;
43e65147 9189
16980d0b
JB		 9190 case 3:
9191 if ((size == 2 && (idx_align & 3) != 0)
9192 || (idx_align & 1) != 0)
78933a4a 9193 return false;
16980d0b 9194 break;
43e65147 9195
16980d0b
JB		 9196 case 4:
9197 if (size == 2)
9198 {
9199 if ((idx_align & 3) == 3)
78933a4a 9200 return false;
16980d0b
JB		 9201 align = (idx_align & 3) * 64;
9202 }
9203 else
9204 align = (idx_align & 1) ? 32 << size : 0;
9205 break;
43e65147 9206
16980d0b
JB		 9207 default:
9208 abort ();
9209 }
43e65147 9210
16980d0b
JB		 9211 func (stream, "{");
9212 for (i = 0; i < length; i++)
9213 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9214 rd + i * stride, idx);
9215 func (stream, "}, [%s", arm_regnames[rn]);
9216 if (align)
8e560766 9217 func (stream, " :%d", align);
16980d0b
JB		 9218 func (stream, "]");
9219 if (rm == 0xd)
9220 func (stream, "!");
9221 else if (rm != 0xf)
9222 func (stream, ", %s", arm_regnames[rm]);
9223 }
9224 break;
43e65147 9225
16980d0b
JB		 9226 case 'C':
9227 {
9228 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9229 int rn = ((given >> 16) & 0xf);
9230 int rm = ((given >> 0) & 0xf);
9231 int align = ((given >> 4) & 0x1);
9232 int size = ((given >> 6) & 0x3);
9233 int type = ((given >> 8) & 0x3);
9234 int n = type + 1;
9235 int stride = ((given >> 5) & 0x1);
9236 int ix;
43e65147 9237
16980d0b
JB		 9238 if (stride && (n == 1))
9239 n++;
9240 else
9241 stride++;
43e65147 9242
16980d0b
JB		 9243 func (stream, "{");
9244 if (stride > 1)
9245 for (ix = 0; ix != n; ix++)
9246 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9247 else if (n == 1)
9248 func (stream, "d%d[]", rd);
9249 else
9250 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9251 func (stream, "}, [%s", arm_regnames[rn]);
9252 if (align)
9253 {
91d6fa6a 9254 align = (8 * (type + 1)) << size;
16980d0b
JB		 9255 if (type == 3)
9256 align = (size > 1) ? align >> 1 : align;
9257 if (type == 2 || (type == 0 && !size))
8e560766 9258 func (stream, " :<bad align %d>", align);
16980d0b 9259 else
8e560766 9260 func (stream, " :%d", align);
16980d0b
JB		 9261 }
9262 func (stream, "]");
9263 if (rm == 0xd)
9264 func (stream, "!");
9265 else if (rm != 0xf)
9266 func (stream, ", %s", arm_regnames[rm]);
9267 }
9268 break;
43e65147 9269
16980d0b
JB		 9270 case 'D':
9271 {
9272 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9273 int size = (given >> 20) & 3;
9274 int reg = raw_reg & ((4 << size) - 1);
9275 int ix = raw_reg >> size >> 2;
43e65147 9276
16980d0b
JB		 9277 func (stream, "d%d[%d]", reg, ix);
9278 }
9279 break;
43e65147 9280
16980d0b 9281 case 'E':
fe56b6ce 9282 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9283 {
9284 int bits = 0;
9285 int cmode = (given >> 8) & 0xf;
9286 int op = (given >> 5) & 0x1;
9287 unsigned long value = 0, hival = 0;
9288 unsigned shift;
9289 int size = 0;
0dbde4cf 9290 int isfloat = 0;
43e65147 9291
16980d0b
JB		 9292 bits |= ((given >> 24) & 1) << 7;
9293 bits |= ((given >> 16) & 7) << 4;
9294 bits |= ((given >> 0) & 15) << 0;
43e65147 9295
16980d0b
JB		 9296 if (cmode < 8)
9297 {
9298 shift = (cmode >> 1) & 3;
fe56b6ce 9299 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9300 size = 32;
9301 }
9302 else if (cmode < 12)
9303 {
9304 shift = (cmode >> 1) & 1;
fe56b6ce 9305 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9306 size = 16;
9307 }
9308 else if (cmode < 14)
9309 {
9310 shift = (cmode & 1) + 1;
fe56b6ce 9311 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9312 value |= (1ul << (8 * shift)) - 1;
9313 size = 32;
9314 }
9315 else if (cmode == 14)
9316 {
9317 if (op)
9318 {
fe56b6ce 9319 /* Bit replication into bytes. */
16980d0b
JB		 9320 int ix;
9321 unsigned long mask;
43e65147 9322
16980d0b
JB		 9323 value = 0;
9324 hival = 0;
9325 for (ix = 7; ix >= 0; ix--)
9326 {
9327 mask = ((bits >> ix) & 1) ? 0xff : 0;
9328 if (ix <= 3)
9329 value = (value << 8) | mask;
9330 else
9331 hival = (hival << 8) | mask;
9332 }
9333 size = 64;
9334 }
9335 else
9336 {
fe56b6ce
NC		 9337 /* Byte replication. */
9338 value = (unsigned long) bits;
16980d0b
JB		 9339 size = 8;
9340 }
9341 }
9342 else if (!op)
9343 {
fe56b6ce 9344 /* Floating point encoding. */
16980d0b 9345 int tmp;
43e65147 9346
fe56b6ce
NC		 9347 value = (unsigned long) (bits & 0x7f) << 19;
9348 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9349 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9350 value |= (unsigned long) tmp << 24;
16980d0b 9351 size = 32;
0dbde4cf 9352 isfloat = 1;
16980d0b
JB		 9353 }
9354 else
9355 {
9356 func (stream, "<illegal constant %.8x:%x:%x>",
9357 bits, cmode, op);
9358 size = 32;
9359 break;
9360 }
9361 switch (size)
9362 {
9363 case 8:
9364 func (stream, "#%ld\t; 0x%.2lx", value, value);
9365 break;
43e65147 9366
16980d0b
JB		 9367 case 16:
9368 func (stream, "#%ld\t; 0x%.4lx", value, value);
9369 break;
9370
9371 case 32:
0dbde4cf
JB		 9372 if (isfloat)
9373 {
9374 unsigned char valbytes[4];
9375 double fvalue;
43e65147 9376
0dbde4cf
JB		 9377 /* Do this a byte at a time so we don't have to
9378 worry about the host's endianness. */
9379 valbytes[0] = value & 0xff;
9380 valbytes[1] = (value >> 8) & 0xff;
9381 valbytes[2] = (value >> 16) & 0xff;
9382 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9383
9384 floatformat_to_double
c1e26897
NC		 9385 (& floatformat_ieee_single_little, valbytes,
9386 & fvalue);
43e65147 9387
0dbde4cf
JB		 9388 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9389 value);
9390 }
9391 else
4e9d3b81 9392 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9393 (long) (((value & 0x80000000L) != 0)
9d82ec38 9394 ? value | ~0xffffffffL : value),
c1e26897 9395 value);
16980d0b
JB		 9396 break;
9397
9398 case 64:
9399 func (stream, "#0x%.8lx%.8lx", hival, value);
9400 break;
43e65147 9401
16980d0b
JB		 9402 default:
9403 abort ();
9404 }
9405 }
9406 break;
43e65147 9407
16980d0b
JB		 9408 case 'F':
9409 {
9410 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9411 int num = (given >> 8) & 0x3;
43e65147 9412
16980d0b
JB		 9413 if (!num)
9414 func (stream, "{d%d}", regno);
9415 else if (num + regno >= 32)
9416 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9417 else
9418 func (stream, "{d%d-d%d}", regno, regno + num);
9419 }
9420 break;
7e8e6784 9421
16980d0b
JB		 9422
9423 case '0': case '1': case '2': case '3': case '4':
9424 case '5': case '6': case '7': case '8': case '9':
9425 {
9426 int width;
9427 unsigned long value;
9428
9429 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9430
16980d0b
JB		 9431 switch (*c)
9432 {
9433 case 'r':
9434 func (stream, "%s", arm_regnames[value]);
9435 break;
9436 case 'd':
9437 func (stream, "%ld", value);
05413229 9438 value_in_comment = value;
16980d0b
JB		 9439 break;
9440 case 'e':
9441 func (stream, "%ld", (1ul << width) - value);
9442 break;
43e65147 9443
16980d0b
JB		 9444 case 'S':
9445 case 'T':
9446 case 'U':
05413229 9447 /* Various width encodings. */
16980d0b
JB		 9448 {
9449 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9450 int limit;
9451 unsigned low, high;
9452
9453 c++;
9454 if (*c >= '0' && *c <= '9')
9455 limit = *c - '0';
9456 else if (*c >= 'a' && *c <= 'f')
9457 limit = *c - 'a' + 10;
9458 else
9459 abort ();
9460 low = limit >> 2;
9461 high = limit & 3;
9462
9463 if (value < low || value > high)
9464 func (stream, "<illegal width %d>", base << value);
9465 else
9466 func (stream, "%d", base << value);
9467 }
9468 break;
9469 case 'R':
9470 if (given & (1 << 6))
9471 goto Q;
9472 /* FALLTHROUGH */
9473 case 'D':
9474 func (stream, "d%ld", value);
9475 break;
9476 case 'Q':
9477 Q:
9478 if (value & 1)
9479 func (stream, "<illegal reg q%ld.5>", value >> 1);
9480 else
9481 func (stream, "q%ld", value >> 1);
9482 break;
43e65147 9483
16980d0b
JB		 9484 case '`':
9485 c++;
9486 if (value == 0)
9487 func (stream, "%c", *c);
9488 break;
9489 case '\'':
9490 c++;
9491 if (value == ((1ul << width) - 1))
9492 func (stream, "%c", *c);
9493 break;
9494 case '?':
fe56b6ce 9495 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9496 c += 1 << width;
9497 break;
9498 default:
9499 abort ();
9500 }
16980d0b 9501 }
dffaa15c
AM		 9502 break;
9503
9504 default:
9505 abort ();
16980d0b
JB		 9506 }
9507 }
9508 else
9509 func (stream, "%c", *c);
9510 }
05413229
NC		 9511
9512 if (value_in_comment > 32 || value_in_comment < -16)
9513 func (stream, "\t; 0x%lx", value_in_comment);
9514
e2efe87d
MGD		 9515 if (is_unpredictable)
9516 func (stream, UNPREDICTABLE_INSTRUCTION);
9517
78933a4a 9518 return true;
16980d0b
JB		 9519 }
9520 }
78933a4a 9521 return false;
16980d0b
JB		 9522}
9523
73cd51e5
AV		 9524/* Print one mve instruction on INFO->STREAM.
9525 Return TRUE if the instuction matched, FALSE if this is not a
9526 recognised mve instruction. */
9527
78933a4a 9528static bool
73cd51e5
AV		 9529print_insn_mve (struct disassemble_info *info, long given)
9530{
9531 const struct mopcode32 *insn;
9532 void *stream = info->stream;
9533 fprintf_ftype func = info->fprintf_func;
9534
9535 for (insn = mve_opcodes; insn->assembler; insn++)
9536 {
9537 if (((given & insn->mask) == insn->value)
9538 && !is_mve_encoding_conflict (given, insn->mve_op))
9539 {
9540 signed long value_in_comment = 0;
78933a4a
AM		 9541 bool is_unpredictable = false;
9542 bool is_undefined = false;
73cd51e5
AV		 9543 const char *c;
9544 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9545 enum mve_undefined undefined_cond = UNDEF_NONE;
9546
9547 /* Most vector mve instruction are illegal in a it block.
9548 There are a few exceptions; check for them. */
9549 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9550 {
78933a4a 9551 is_unpredictable = true;
73cd51e5
AV		 9552 unpredictable_cond = UNPRED_IT_BLOCK;
9553 }
9554 else if (is_mve_unpredictable (given, insn->mve_op,
9555 &unpredictable_cond))
78933a4a 9556 is_unpredictable = true;
73cd51e5
AV		 9557
9558 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9559 is_undefined = true;
73cd51e5 9560
c4a23bf8
SP		 9561 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9562 i.e "VMOV Qd, Qm". */
9563 if ((insn->mve_op == MVE_VORR_REG)
9564 && (arm_decode_field (given, 1, 3)
9565 == arm_decode_field (given, 17, 19)))
9566 continue;
9567
73cd51e5
AV		 9568 for (c = insn->assembler; *c; c++)
9569 {
9570 if (*c == '%')
9571 {
9572 switch (*++c)
9573 {
9574 case '%':
9575 func (stream, "%%");
9576 break;
9577
ef1576a1
AV		 9578 case 'a':
9579 /* Don't print anything for '+' as it is implied. */
9580 if (arm_decode_field (given, 23, 23) == 0)
9581 func (stream, "-");
9582 break;
9583
143275ea
AV		 9584 case 'c':
9585 if (ifthen_state)
9586 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9587 break;
9588
aef6d006
AV		 9589 case 'd':
9590 print_mve_vld_str_addr (info, given, insn->mve_op);
9591 break;
9592
143275ea
AV		 9593 case 'i':
9594 {
9595 long mve_mask = mve_extract_pred_mask (given);
9596 func (stream, "%s", mve_predicatenames[mve_mask]);
9597 }
9598 break;
9599
23d00a41
SD		 9600 case 'j':
9601 {
9602 unsigned int imm5 = 0;
9603 imm5 |= arm_decode_field (given, 6, 7);
9604 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9605 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9606 }
9607 break;
9608
08132bdd
SP		 9609 case 'k':
9610 func (stream, "#%u",
9611 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9612 break;
9613
143275ea
AV		 9614 case 'n':
9615 print_vec_condition (info, given, insn->mve_op);
9616 break;
9617
ef1576a1
AV		 9618 case 'o':
9619 if (arm_decode_field (given, 0, 0) == 1)
9620 {
9621 unsigned long size
9622 = arm_decode_field (given, 4, 4)
9623 | (arm_decode_field (given, 6, 6) << 1);
9624
9625 func (stream, ", uxtw #%lu", size);
9626 }
9627 break;
9628
bf0b396d
AV		 9629 case 'm':
9630 print_mve_rounding_mode (info, given, insn->mve_op);
9631 break;
9632
9633 case 's':
9634 print_mve_vcvt_size (info, given, insn->mve_op);
9635 break;
9636
aef6d006
AV		 9637 case 'u':
9638 {
c507f10b
AV		 9639 unsigned long op1 = arm_decode_field (given, 21, 22);
9640
9641 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9642 {
9643 /* Check for signed. */
9644 if (arm_decode_field (given, 23, 23) == 0)
9645 {
9646 /* We don't print 's' for S32. */
9647 if ((arm_decode_field (given, 5, 6) == 0)
9648 && ((op1 == 0) || (op1 == 1)))
9649 ;
9650 else
9651 func (stream, "s");
9652 }
9653 else
9654 func (stream, "u");
9655 }
aef6d006 9656 else
c507f10b
AV		 9657 {
9658 if (arm_decode_field (given, 28, 28) == 0)
9659 func (stream, "s");
9660 else
9661 func (stream, "u");
9662 }
aef6d006 9663 }
ef1576a1 9664 break;
aef6d006 9665
143275ea
AV		 9666 case 'v':
9667 print_instruction_predicate (info);
9668 break;
9669
04d54ace
AV		 9670 case 'w':
9671 if (arm_decode_field (given, 21, 21) == 1)
9672 func (stream, "!");
9673 break;
9674
9675 case 'B':
9676 print_mve_register_blocks (info, given, insn->mve_op);
9677 break;
9678
c507f10b
AV		 9679 case 'E':
9680 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9681
9682 print_simd_imm8 (info, given, 28, insn);
9683 break;
9684
9685 case 'N':
9686 print_mve_vmov_index (info, given);
9687 break;
9688
14925797
AV		 9689 case 'T':
9690 if (arm_decode_field (given, 12, 12) == 0)
9691 func (stream, "b");
9692 else
9693 func (stream, "t");
9694 break;
9695
d3b63143
AV		 9696 case 'X':
9697 if (arm_decode_field (given, 12, 12) == 1)
9698 func (stream, "x");
9699 break;
9700
143275ea
AV		 9701 case '0': case '1': case '2': case '3': case '4':
9702 case '5': case '6': case '7': case '8': case '9':
9703 {
9704 int width;
9705 unsigned long value;
9706
9707 c = arm_decode_bitfield (c, given, &value, &width);
9708
9709 switch (*c)
9710 {
9711 case 'Z':
9712 if (value == 13)
78933a4a 9713 is_unpredictable = true;
143275ea
AV		 9714 else if (value == 15)
9715 func (stream, "zr");
9716 else
9717 func (stream, "%s", arm_regnames[value]);
9718 break;
23d00a41 9719
e39c1607
SD		 9720 case 'c':
9721 func (stream, "%s", arm_conditional[value]);
9722 break;
9723
9724 case 'C':
9725 value ^= 1;
9726 func (stream, "%s", arm_conditional[value]);
9727 break;
9728
23d00a41
SD		 9729 case 'S':
9730 if (value == 13 || value == 15)
78933a4a 9731 is_unpredictable = true;
23d00a41
SD		 9732 else
9733 func (stream, "%s", arm_regnames[value]);
9734 break;
9735
143275ea
AV		 9736 case 's':
9737 print_mve_size (info,
9738 value,
9739 insn->mve_op);
9740 break;
66dcaa5d
AV		 9741 case 'I':
9742 if (value == 1)
9743 func (stream, "i");
9744 break;
d3b63143
AV		 9745 case 'A':
9746 if (value == 1)
9747 func (stream, "a");
9748 break;
1c8f2df8
AV		 9749 case 'h':
9750 {
9751 unsigned int odd_reg = (value << 1) | 1;
9752 func (stream, "%s", arm_regnames[odd_reg]);
9753 }
9754 break;
ef1576a1
AV		 9755 case 'i':
9756 {
9757 unsigned long imm
9758 = arm_decode_field (given, 0, 6);
9759 unsigned long mod_imm = imm;
9760
9761 switch (insn->mve_op)
9762 {
9763 case MVE_VLDRW_GATHER_T5:
9764 case MVE_VSTRW_SCATTER_T5:
9765 mod_imm = mod_imm << 2;
9766 break;
9767 case MVE_VSTRD_SCATTER_T6:
9768 case MVE_VLDRD_GATHER_T6:
9769 mod_imm = mod_imm << 3;
9770 break;
9771
9772 default:
9773 break;
9774 }
9775
9776 func (stream, "%lu", mod_imm);
9777 }
9778 break;
bf0b396d
AV		 9779 case 'k':
9780 func (stream, "%lu", 64 - value);
9781 break;
1c8f2df8
AV		 9782 case 'l':
9783 {
9784 unsigned int even_reg = value << 1;
9785 func (stream, "%s", arm_regnames[even_reg]);
9786 }
9787 break;
9788 case 'u':
9789 switch (value)
9790 {
9791 case 0:
9792 func (stream, "1");
9793 break;
9794 case 1:
9795 func (stream, "2");
9796 break;
9797 case 2:
9798 func (stream, "4");
9799 break;
9800 case 3:
9801 func (stream, "8");
9802 break;
9803 default:
9804 break;
9805 }
9806 break;
897b9bbc
AV		 9807 case 'o':
9808 print_mve_rotate (info, value, width);
9809 break;
9743db03
AV		 9810 case 'r':
9811 func (stream, "%s", arm_regnames[value]);
9812 break;
04d54ace 9813 case 'd':
ed63aa17
AV		 9814 if (insn->mve_op == MVE_VQSHL_T2
9815 || insn->mve_op == MVE_VQSHLU_T3
9816 || insn->mve_op == MVE_VRSHR
9817 || insn->mve_op == MVE_VRSHRN
9818 || insn->mve_op == MVE_VSHL_T1
9819 || insn->mve_op == MVE_VSHLL_T1
9820 || insn->mve_op == MVE_VSHR
9821 || insn->mve_op == MVE_VSHRN
9822 || insn->mve_op == MVE_VSLI
9823 || insn->mve_op == MVE_VSRI)
9824 print_mve_shift_n (info, given, insn->mve_op);
9825 else if (insn->mve_op == MVE_VSHLL_T2)
9826 {
9827 switch (value)
9828 {
9829 case 0x00:
9830 func (stream, "8");
9831 break;
9832 case 0x01:
9833 func (stream, "16");
9834 break;
9835 case 0x10:
9836 print_mve_undefined (info, UNDEF_SIZE_0);
9837 break;
9838 default:
9839 assert (0);
9840 break;
9841 }
9842 }
9843 else
9844 {
9845 if (insn->mve_op == MVE_VSHLC && value == 0)
9846 value = 32;
9847 func (stream, "%ld", value);
9848 value_in_comment = value;
9849 }
04d54ace 9850 break;
c507f10b
AV		 9851 case 'F':
9852 func (stream, "s%ld", value);
9853 break;
143275ea
AV		 9854 case 'Q':
9855 if (value & 0x8)
9856 func (stream, "<illegal reg q%ld.5>", value);
9857 else
9858 func (stream, "q%ld", value);
9859 break;
c507f10b
AV		 9860 case 'x':
9861 func (stream, "0x%08lx", value);
9862 break;
143275ea
AV		 9863 default:
9864 abort ();
9865 }
9866 break;
9867 default:
9868 abort ();
9869 }
73cd51e5
AV		 9870 }
9871 }
9872 else
9873 func (stream, "%c", *c);
9874 }
9875
9876 if (value_in_comment > 32 || value_in_comment < -16)
9877 func (stream, "\t; 0x%lx", value_in_comment);
9878
9879 if (is_unpredictable)
9880 print_mve_unpredictable (info, unpredictable_cond);
9881
9882 if (is_undefined)
9883 print_mve_undefined (info, undefined_cond);
9884
63b4cc53 9885 if (!vpt_block_state.in_vpt_block
143275ea 9886 && !ifthen_state
63b4cc53 9887 && is_vpt_instruction (given))
143275ea 9888 mark_inside_vpt_block (given);
63b4cc53 9889 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 9890 update_vpt_block_state ();
9891
78933a4a 9892 return true;
73cd51e5
AV		 9893 }
9894 }
78933a4a 9895 return false;
73cd51e5
AV		 9896}
9897
9898
90ec0d68
MGD		 9899/* Return the name of a v7A special register. */
9900
43e65147 9901static const char *
90ec0d68
MGD		 9902banked_regname (unsigned reg)
9903{
9904 switch (reg)
9905 {
9906 case 15: return "CPSR";
43e65147 9907 case 32: return "R8_usr";
90ec0d68
MGD		 9908 case 33: return "R9_usr";
9909 case 34: return "R10_usr";
9910 case 35: return "R11_usr";
9911 case 36: return "R12_usr";
9912 case 37: return "SP_usr";
9913 case 38: return "LR_usr";
43e65147 9914 case 40: return "R8_fiq";
90ec0d68
MGD		 9915 case 41: return "R9_fiq";
9916 case 42: return "R10_fiq";
9917 case 43: return "R11_fiq";
9918 case 44: return "R12_fiq";
9919 case 45: return "SP_fiq";
9920 case 46: return "LR_fiq";
9921 case 48: return "LR_irq";
9922 case 49: return "SP_irq";
9923 case 50: return "LR_svc";
9924 case 51: return "SP_svc";
9925 case 52: return "LR_abt";
9926 case 53: return "SP_abt";
9927 case 54: return "LR_und";
9928 case 55: return "SP_und";
9929 case 60: return "LR_mon";
9930 case 61: return "SP_mon";
9931 case 62: return "ELR_hyp";
9932 case 63: return "SP_hyp";
9933 case 79: return "SPSR";
9934 case 110: return "SPSR_fiq";
9935 case 112: return "SPSR_irq";
9936 case 114: return "SPSR_svc";
9937 case 116: return "SPSR_abt";
9938 case 118: return "SPSR_und";
9939 case 124: return "SPSR_mon";
9940 case 126: return "SPSR_hyp";
9941 default: return NULL;
9942 }
9943}
9944
e797f7e0
MGD		 9945/* Return the name of the DMB/DSB option. */
9946static const char *
9947data_barrier_option (unsigned option)
9948{
9949 switch (option & 0xf)
9950 {
9951 case 0xf: return "sy";
9952 case 0xe: return "st";
9953 case 0xd: return "ld";
9954 case 0xb: return "ish";
9955 case 0xa: return "ishst";
9956 case 0x9: return "ishld";
9957 case 0x7: return "un";
9958 case 0x6: return "unst";
9959 case 0x5: return "nshld";
9960 case 0x3: return "osh";
9961 case 0x2: return "oshst";
9962 case 0x1: return "oshld";
9963 default: return NULL;
9964 }
9965}
9966
4a5329c6
ZW		 9967/* Print one ARM instruction from PC on INFO->STREAM. */
9968
9969static void
9970print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9971{
6b5d3a4d 9972 const struct opcode32 *insn;
6a51a8a8 9973 void *stream = info->stream;
6b5d3a4d 9974 fprintf_ftype func = info->fprintf_func;
b0e28b39 9975 struct arm_private_data *private_data = info->private_data;
252b5132 9976
78933a4a 9977 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 9978 return;
9979
78933a4a 9980 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 9981 return;
9982
78933a4a 9983 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 9984 return;
9985
252b5132
RH		 9986 for (insn = arm_opcodes; insn->assembler; insn++)
9987 {
0313a2b8
NC		 9988 if ((given & insn->mask) != insn->value)
9989 continue;
823d2571
TG		 9990
9991 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9992 continue;
9993
9994 /* Special case: an instruction with all bits set in the condition field
9995 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9996 or by the catchall at the end of the table. */
9997 if ((given & 0xF0000000) != 0xF0000000
9998 || (insn->mask & 0xF0000000) == 0xF0000000
9999 || (insn->mask == 0 && insn->value == 0))
252b5132 10000 {
ff4a8d2b
NC		 10001 unsigned long u_reg = 16;
10002 unsigned long U_reg = 16;
78933a4a 10003 bool is_unpredictable = false;
05413229 10004 signed long value_in_comment = 0;
6b5d3a4d 10005 const char *c;
b34976b6 10006
252b5132
RH		 10007 for (c = insn->assembler; *c; c++)
10008 {
10009 if (*c == '%')
10010 {
78933a4a 10011 bool allow_unpredictable = false;
c1e26897 10012
252b5132
RH		 10013 switch (*++c)
10014 {
10015 case '%':
10016 func (stream, "%%");
10017 break;
10018
10019 case 'a':
05413229 10020 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10021 break;
252b5132 10022
62b3e311
PB		 10023 case 'P':
10024 /* Set P address bit and use normal address
10025 printing routine. */
c1e26897 10026 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10027 break;
10028
c1e26897 10029 case 'S':
78933a4a 10030 allow_unpredictable = true;
1a0670f3 10031 /* Fall through. */
252b5132
RH		 10032 case 's':
10033 if ((given & 0x004f0000) == 0x004f0000)
10034 {
58efb6c0 10035 /* PC relative with immediate offset. */
f8b960bc 10036 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10037
aefd8a40
NC		 10038 if (PRE_BIT_SET)
10039 {
26d97720
NS		 10040 /* Elide positive zero offset. */
10041 if (offset || NEGATIVE_BIT_SET)
10042 func (stream, "[pc, #%s%d]\t; ",
d908c8af 10043 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 10044 else
26d97720
NS		 10045 func (stream, "[pc]\t; ");
10046 if (NEGATIVE_BIT_SET)
10047 offset = -offset;
aefd8a40
NC		 10048 info->print_address_func (offset + pc + 8, info);
10049 }
10050 else
10051 {
26d97720
NS		 10052 /* Always show the offset. */
10053 func (stream, "[pc], #%s%d",
d908c8af 10054 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10055 if (! allow_unpredictable)
78933a4a 10056 is_unpredictable = true;
aefd8a40 10057 }
252b5132
RH		 10058 }
10059 else
10060 {
fe56b6ce
NC		 10061 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10062
b34976b6 10063 func (stream, "[%s",
252b5132 10064 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10065
c1e26897 10066 if (PRE_BIT_SET)
252b5132 10067 {
c1e26897 10068 if (IMMEDIATE_BIT_SET)
252b5132 10069 {
26d97720
NS		 10070 /* Elide offset for non-writeback
10071 positive zero. */
10072 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10073 || offset)
10074 func (stream, ", #%s%d",
10075 NEGATIVE_BIT_SET ? "-" : "", offset);
10076
10077 if (NEGATIVE_BIT_SET)
10078 offset = -offset;
945ee430 10079
fe56b6ce 10080 value_in_comment = offset;
252b5132 10081 }
945ee430 10082 else
ff4a8d2b
NC		 10083 {
10084 /* Register Offset or Register Pre-Indexed. */
10085 func (stream, ", %s%s",
10086 NEGATIVE_BIT_SET ? "-" : "",
10087 arm_regnames[given & 0xf]);
10088
10089 /* Writing back to the register that is the source/
10090 destination of the load/store is unpredictable. */
10091 if (! allow_unpredictable
10092 && WRITEBACK_BIT_SET
10093 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10094 is_unpredictable = true;
ff4a8d2b 10095 }
252b5132 10096
b34976b6 10097 func (stream, "]%s",
c1e26897 10098 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10099 }
945ee430 10100 else
252b5132 10101 {
c1e26897 10102 if (IMMEDIATE_BIT_SET)
252b5132 10103 {
945ee430 10104 /* Immediate Post-indexed. */
aefd8a40 10105 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 10106 func (stream, "], #%s%d",
10107 NEGATIVE_BIT_SET ? "-" : "", offset);
10108 if (NEGATIVE_BIT_SET)
10109 offset = -offset;
fe56b6ce 10110 value_in_comment = offset;
252b5132 10111 }
945ee430 10112 else
ff4a8d2b
NC		 10113 {
10114 /* Register Post-indexed. */
10115 func (stream, "], %s%s",
10116 NEGATIVE_BIT_SET ? "-" : "",
10117 arm_regnames[given & 0xf]);
10118
10119 /* Writing back to the register that is the source/
10120 destination of the load/store is unpredictable. */
10121 if (! allow_unpredictable
10122 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10123 is_unpredictable = true;
ff4a8d2b 10124 }
c1e26897 10125
07a28fab
NC		 10126 if (! allow_unpredictable)
10127 {
10128 /* Writeback is automatically implied by post- addressing.
10129 Setting the W bit is unnecessary and ARM specify it as
10130 being unpredictable. */
10131 if (WRITEBACK_BIT_SET
10132 /* Specifying the PC register as the post-indexed
10133 registers is also unpredictable. */
ab8e2090 10134 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10135 is_unpredictable = true;
07a28fab 10136 }
252b5132
RH		 10137 }
10138 }
10139 break;
b34976b6 10140
252b5132 10141 case 'b':
6b5d3a4d 10142 {
f8b960bc 10143 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10144 bfd_vma target = disp * 4 + pc + 8;
10145 info->print_address_func (target, info);
10146
10147 /* Fill in instruction information. */
10148 info->insn_info_valid = 1;
10149 info->insn_type = dis_branch;
10150 info->target = target;
6b5d3a4d 10151 }
252b5132
RH		 10152 break;
10153
10154 case 'c':
c22aaad1
PB		 10155 if (((given >> 28) & 0xf) != 0xe)
10156 func (stream, "%s",
10157 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10158 break;
10159
10160 case 'm':
10161 {
10162 int started = 0;
10163 int reg;
10164
10165 func (stream, "{");
10166 for (reg = 0; reg < 16; reg++)
10167 if ((given & (1 << reg)) != 0)
10168 {
10169 if (started)
10170 func (stream, ", ");
10171 started = 1;
10172 func (stream, "%s", arm_regnames[reg]);
10173 }
10174 func (stream, "}");
ab8e2090 10175 if (! started)
78933a4a 10176 is_unpredictable = true;
252b5132
RH		 10177 }
10178 break;
10179
37b37b2d 10180 case 'q':
78933a4a 10181 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10182 break;
10183
252b5132
RH		 10184 case 'o':
10185 if ((given & 0x02000000) != 0)
10186 {
a415b1cd
JB		 10187 unsigned int rotate = (given & 0xf00) >> 7;
10188 unsigned int immed = (given & 0xff);
10189 unsigned int a, i;
10190
ebd1c6d1
AM		 10191 a = (immed << ((32 - rotate) & 31)
10192 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10193 /* If there is another encoding with smaller rotate,
10194 the rotate should be specified directly. */
10195 for (i = 0; i < 32; i += 2)
ebd1c6d1 10196 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10197 break;
10198
10199 if (i != rotate)
10200 func (stream, "#%d, %d", immed, rotate);
10201 else
10202 func (stream, "#%d", a);
10203 value_in_comment = a;
252b5132
RH		 10204 }
10205 else
78933a4a 10206 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10207 break;
10208
10209 case 'p':
10210 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10211 {
823d2571
TG		 10212 arm_feature_set arm_ext_v6 =
10213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10214
aefd8a40
NC		 10215 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10216 mechanism for setting PSR flag bits. They are
10217 obsolete in V6 onwards. */
823d2571
TG		 10218 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10219 arm_ext_v6))
aefd8a40 10220 func (stream, "p");
4ab90a7a 10221 else
78933a4a 10222 is_unpredictable = true;
aefd8a40 10223 }
252b5132
RH		 10224 break;
10225
10226 case 't':
10227 if ((given & 0x01200000) == 0x00200000)
10228 func (stream, "t");
10229 break;
10230
252b5132 10231 case 'A':
05413229
NC		 10232 {
10233 int offset = given & 0xff;
f02232aa 10234
05413229 10235 value_in_comment = offset * 4;
c1e26897 10236 if (NEGATIVE_BIT_SET)
05413229 10237 value_in_comment = - value_in_comment;
f02232aa 10238
05413229 10239 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 10240
c1e26897 10241 if (PRE_BIT_SET)
05413229
NC		 10242 {
10243 if (offset)
fe56b6ce 10244 func (stream, ", #%d]%s",
d908c8af 10245 (int) value_in_comment,
c1e26897 10246 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 10247 else
10248 func (stream, "]");
10249 }
10250 else
10251 {
10252 func (stream, "]");
f02232aa 10253
c1e26897 10254 if (WRITEBACK_BIT_SET)
05413229
NC		 10255 {
10256 if (offset)
d908c8af 10257 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 10258 }
10259 else
fe56b6ce 10260 {
d908c8af 10261 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10262 value_in_comment = offset;
10263 }
05413229
NC		 10264 }
10265 }
252b5132
RH		 10266 break;
10267
077b8428
NC		 10268 case 'B':
10269 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10270 {
10271 bfd_vma address;
10272 bfd_vma offset = 0;
b34976b6 10273
c1e26897 10274 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10275 /* Is signed, hi bits should be ones. */
10276 offset = (-1) ^ 0x00ffffff;
10277
10278 /* Offset is (SignExtend(offset field)<<2). */
10279 offset += given & 0x00ffffff;
10280 offset <<= 2;
10281 address = offset + pc + 8;
b34976b6 10282
8f06b2d8
PB		 10283 if (given & 0x01000000)
10284 /* H bit allows addressing to 2-byte boundaries. */
10285 address += 2;
b1ee46c5 10286
8f06b2d8 10287 info->print_address_func (address, info);
1d67fe3b
TT		 10288
10289 /* Fill in instruction information. */
10290 info->insn_info_valid = 1;
10291 info->insn_type = dis_branch;
10292 info->target = address;
b1ee46c5 10293 }
b1ee46c5
AH		 10294 break;
10295
252b5132 10296 case 'C':
90ec0d68
MGD		 10297 if ((given & 0x02000200) == 0x200)
10298 {
10299 const char * name;
10300 unsigned sysm = (given & 0x004f0000) >> 16;
10301
10302 sysm |= (given & 0x300) >> 4;
10303 name = banked_regname (sysm);
10304
10305 if (name != NULL)
10306 func (stream, "%s", name);
10307 else
d908c8af 10308 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10309 }
10310 else
10311 {
43e65147 10312 func (stream, "%cPSR_",
90ec0d68
MGD		 10313 (given & 0x00400000) ? 'S' : 'C');
10314 if (given & 0x80000)
10315 func (stream, "f");
10316 if (given & 0x40000)
10317 func (stream, "s");
10318 if (given & 0x20000)
10319 func (stream, "x");
10320 if (given & 0x10000)
10321 func (stream, "c");
10322 }
252b5132
RH		 10323 break;
10324
62b3e311 10325 case 'U':
43e65147 10326 if ((given & 0xf0) == 0x60)
62b3e311 10327 {
52e7f43d
RE		 10328 switch (given & 0xf)
10329 {
10330 case 0xf: func (stream, "sy"); break;
10331 default:
10332 func (stream, "#%d", (int) given & 0xf);
10333 break;
10334 }
43e65147
L		 10335 }
10336 else
52e7f43d 10337 {
e797f7e0
MGD		 10338 const char * opt = data_barrier_option (given & 0xf);
10339 if (opt != NULL)
10340 func (stream, "%s", opt);
10341 else
52e7f43d 10342 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10343 }
10344 break;
10345
b34976b6 10346 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10347 case '5': case '6': case '7': case '8': case '9':
10348 {
16980d0b
JB		 10349 int width;
10350 unsigned long value;
252b5132 10351
16980d0b 10352 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10353
252b5132
RH		 10354 switch (*c)
10355 {
ab8e2090
NC		 10356 case 'R':
10357 if (value == 15)
78933a4a 10358 is_unpredictable = true;
ab8e2090 10359 /* Fall through. */
16980d0b 10360 case 'r':
9eb6c0f1
MGD		 10361 case 'T':
10362 /* We want register + 1 when decoding T. */
10363 if (*c == 'T')
2bddb71a 10364 value = (value + 1) & 0xf;
9eb6c0f1 10365
ff4a8d2b
NC		 10366 if (c[1] == 'u')
10367 {
10368 /* Eat the 'u' character. */
10369 ++ c;
10370
10371 if (u_reg == value)
78933a4a 10372 is_unpredictable = true;
ff4a8d2b
NC		 10373 u_reg = value;
10374 }
10375 if (c[1] == 'U')
10376 {
10377 /* Eat the 'U' character. */
10378 ++ c;
10379
10380 if (U_reg == value)
78933a4a 10381 is_unpredictable = true;
ff4a8d2b
NC		 10382 U_reg = value;
10383 }
16980d0b
JB		 10384 func (stream, "%s", arm_regnames[value]);
10385 break;
10386 case 'd':
10387 func (stream, "%ld", value);
05413229 10388 value_in_comment = value;
16980d0b
JB		 10389 break;
10390 case 'b':
10391 func (stream, "%ld", value * 8);
05413229 10392 value_in_comment = value * 8;
16980d0b
JB		 10393 break;
10394 case 'W':
10395 func (stream, "%ld", value + 1);
05413229 10396 value_in_comment = value + 1;
16980d0b
JB		 10397 break;
10398 case 'x':
10399 func (stream, "0x%08lx", value);
10400
10401 /* Some SWI instructions have special
10402 meanings. */
10403 if ((given & 0x0fffffff) == 0x0FF00000)
10404 func (stream, "\t; IMB");
10405 else if ((given & 0x0fffffff) == 0x0FF00001)
10406 func (stream, "\t; IMBRange");
10407 break;
10408 case 'X':
10409 func (stream, "%01lx", value & 0xf);
05413229 10410 value_in_comment = value;
252b5132
RH		 10411 break;
10412 case '`':
10413 c++;
16980d0b 10414 if (value == 0)
252b5132
RH		 10415 func (stream, "%c", *c);
10416 break;
10417 case '\'':
10418 c++;
16980d0b 10419 if (value == ((1ul << width) - 1))
252b5132
RH		 10420 func (stream, "%c", *c);
10421 break;
10422 case '?':
fe56b6ce 10423 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10424 c += 1 << width;
252b5132
RH		 10425 break;
10426 default:
10427 abort ();
10428 }
dffaa15c
AM		 10429 }
10430 break;
0dd132b6 10431
dffaa15c
AM		 10432 case 'e':
10433 {
10434 int imm;
0dd132b6 10435
dffaa15c
AM		 10436 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10437 func (stream, "%d", imm);
10438 value_in_comment = imm;
10439 }
10440 break;
fe56b6ce 10441
dffaa15c
AM		 10442 case 'E':
10443 /* LSB and WIDTH fields of BFI or BFC. The machine-
10444 language instruction encodes LSB and MSB. */
10445 {
10446 long msb = (given & 0x001f0000) >> 16;
10447 long lsb = (given & 0x00000f80) >> 7;
10448 long w = msb - lsb + 1;
0a003adc 10449
dffaa15c
AM		 10450 if (w > 0)
10451 func (stream, "#%lu, #%lu", lsb, w);
10452 else
10453 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10454 }
10455 break;
90ec0d68 10456
dffaa15c
AM		 10457 case 'R':
10458 /* Get the PSR/banked register name. */
10459 {
10460 const char * name;
10461 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10462
dffaa15c
AM		 10463 sysm |= (given & 0x300) >> 4;
10464 name = banked_regname (sysm);
90ec0d68 10465
dffaa15c
AM		 10466 if (name != NULL)
10467 func (stream, "%s", name);
10468 else
10469 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10470 }
10471 break;
fe56b6ce 10472
dffaa15c
AM		 10473 case 'V':
10474 /* 16-bit unsigned immediate from a MOVT or MOVW
10475 instruction, encoded in bits 0:11 and 15:19. */
10476 {
10477 long hi = (given & 0x000f0000) >> 4;
10478 long lo = (given & 0x00000fff);
10479 long imm16 = hi | lo;
0a003adc 10480
dffaa15c
AM		 10481 func (stream, "#%lu", imm16);
10482 value_in_comment = imm16;
252b5132 10483 }
dffaa15c
AM		 10484 break;
10485
10486 default:
10487 abort ();
252b5132
RH		 10488 }
10489 }
10490 else
10491 func (stream, "%c", *c);
10492 }
05413229
NC		 10493
10494 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10495 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10496
10497 if (is_unpredictable)
10498 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10499
4a5329c6 10500 return;
252b5132
RH		 10501 }
10502 }
0b347048
TC		 10503 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10504 return;
252b5132
RH		 10505}
10506
4a5329c6 10507/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10508
4a5329c6
ZW		 10509static void
10510print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10511{
6b5d3a4d 10512 const struct opcode16 *insn;
6a51a8a8
AM		 10513 void *stream = info->stream;
10514 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10515
10516 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10517 if ((given & insn->mask) == insn->value)
10518 {
05413229 10519 signed long value_in_comment = 0;
6b5d3a4d 10520 const char *c = insn->assembler;
05413229 10521
c19d1205
ZW		 10522 for (; *c; c++)
10523 {
10524 int domaskpc = 0;
10525 int domasklr = 0;
10526
10527 if (*c != '%')
10528 {
10529 func (stream, "%c", *c);
10530 continue;
10531 }
252b5132 10532
c19d1205
ZW		 10533 switch (*++c)
10534 {
10535 case '%':
10536 func (stream, "%%");
10537 break;
b34976b6 10538
c22aaad1
PB		 10539 case 'c':
10540 if (ifthen_state)
10541 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10542 break;
10543
10544 case 'C':
10545 if (ifthen_state)
10546 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10547 else
10548 func (stream, "s");
10549 break;
10550
10551 case 'I':
10552 {
10553 unsigned int tmp;
10554
10555 ifthen_next_state = given & 0xff;
10556 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10557 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10558 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10559 }
10560 break;
10561
10562 case 'x':
10563 if (ifthen_next_state)
10564 func (stream, "\t; unpredictable branch in IT block\n");
10565 break;
10566
10567 case 'X':
10568 if (ifthen_state)
10569 func (stream, "\t; unpredictable <IT:%s>",
10570 arm_conditional[IFTHEN_COND]);
10571 break;
10572
c19d1205
ZW		 10573 case 'S':
10574 {
10575 long reg;
10576
10577 reg = (given >> 3) & 0x7;
10578 if (given & (1 << 6))
10579 reg += 8;
4f3c3dbb 10580
c19d1205
ZW		 10581 func (stream, "%s", arm_regnames[reg]);
10582 }
10583 break;
baf0cc5e 10584
c19d1205 10585 case 'D':
4f3c3dbb 10586 {
c19d1205
ZW		 10587 long reg;
10588
10589 reg = given & 0x7;
10590 if (given & (1 << 7))
10591 reg += 8;
10592
10593 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10594 }
c19d1205
ZW		 10595 break;
10596
10597 case 'N':
10598 if (given & (1 << 8))
10599 domasklr = 1;
10600 /* Fall through. */
10601 case 'O':
10602 if (*c == 'O' && (given & (1 << 8)))
10603 domaskpc = 1;
10604 /* Fall through. */
10605 case 'M':
10606 {
10607 int started = 0;
10608 int reg;
10609
10610 func (stream, "{");
10611
10612 /* It would be nice if we could spot
10613 ranges, and generate the rS-rE format: */
10614 for (reg = 0; (reg < 8); reg++)
10615 if ((given & (1 << reg)) != 0)
10616 {
10617 if (started)
10618 func (stream, ", ");
10619 started = 1;
10620 func (stream, "%s", arm_regnames[reg]);
10621 }
10622
10623 if (domasklr)
10624 {
10625 if (started)
10626 func (stream, ", ");
10627 started = 1;
d908c8af 10628 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10629 }
10630
10631 if (domaskpc)
10632 {
10633 if (started)
10634 func (stream, ", ");
d908c8af 10635 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10636 }
10637
10638 func (stream, "}");
10639 }
10640 break;
10641
4547cb56
NC		 10642 case 'W':
10643 /* Print writeback indicator for a LDMIA. We are doing a
10644 writeback if the base register is not in the register
10645 mask. */
10646 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10647 func (stream, "!");
dffaa15c 10648 break;
4547cb56 10649
c19d1205
ZW		 10650 case 'b':
10651 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10652 {
10653 bfd_vma address = (pc + 4
10654 + ((given & 0x00f8) >> 2)
10655 + ((given & 0x0200) >> 3));
10656 info->print_address_func (address, info);
1d67fe3b
TT		 10657
10658 /* Fill in instruction information. */
10659 info->insn_info_valid = 1;
10660 info->insn_type = dis_branch;
10661 info->target = address;
c19d1205
ZW		 10662 }
10663 break;
10664
10665 case 's':
10666 /* Right shift immediate -- bits 6..10; 1-31 print
10667 as themselves, 0 prints as 32. */
10668 {
10669 long imm = (given & 0x07c0) >> 6;
10670 if (imm == 0)
10671 imm = 32;
0fd3a477 10672 func (stream, "#%ld", imm);
c19d1205
ZW		 10673 }
10674 break;
10675
10676 case '0': case '1': case '2': case '3': case '4':
10677 case '5': case '6': case '7': case '8': case '9':
10678 {
10679 int bitstart = *c++ - '0';
10680 int bitend = 0;
10681
10682 while (*c >= '0' && *c <= '9')
10683 bitstart = (bitstart * 10) + *c++ - '0';
10684
10685 switch (*c)
10686 {
10687 case '-':
10688 {
f8b960bc 10689 bfd_vma reg;
c19d1205
ZW		 10690
10691 c++;
10692 while (*c >= '0' && *c <= '9')
10693 bitend = (bitend * 10) + *c++ - '0';
10694 if (!bitend)
10695 abort ();
10696 reg = given >> bitstart;
10697 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10698
c19d1205
ZW		 10699 switch (*c)
10700 {
10701 case 'r':
10702 func (stream, "%s", arm_regnames[reg]);
10703 break;
10704
10705 case 'd':
d908c8af 10706 func (stream, "%ld", (long) reg);
05413229 10707 value_in_comment = reg;
c19d1205
ZW		 10708 break;
10709
10710 case 'H':
d908c8af 10711 func (stream, "%ld", (long) (reg << 1));
05413229 10712 value_in_comment = reg << 1;
c19d1205
ZW		 10713 break;
10714
10715 case 'W':
d908c8af 10716 func (stream, "%ld", (long) (reg << 2));
05413229 10717 value_in_comment = reg << 2;
c19d1205
ZW		 10718 break;
10719
10720 case 'a':
10721 /* PC-relative address -- the bottom two
10722 bits of the address are dropped
10723 before the calculation. */
10724 info->print_address_func
10725 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10726 value_in_comment = 0;
c19d1205
ZW		 10727 break;
10728
10729 case 'x':
d908c8af 10730 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10731 break;
10732
c19d1205
ZW		 10733 case 'B':
10734 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10735 bfd_vma target = reg * 2 + pc + 4;
10736 info->print_address_func (target, info);
05413229 10737 value_in_comment = 0;
1d67fe3b
TT		 10738
10739 /* Fill in instruction information. */
10740 info->insn_info_valid = 1;
10741 info->insn_type = dis_branch;
10742 info->target = target;
c19d1205
ZW		 10743 break;
10744
10745 case 'c':
c22aaad1 10746 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10747 break;
10748
10749 default:
10750 abort ();
10751 }
10752 }
10753 break;
10754
10755 case '\'':
10756 c++;
10757 if ((given & (1 << bitstart)) != 0)
10758 func (stream, "%c", *c);
10759 break;
10760
10761 case '?':
10762 ++c;
10763 if ((given & (1 << bitstart)) != 0)
10764 func (stream, "%c", *c++);
10765 else
10766 func (stream, "%c", *++c);
10767 break;
10768
10769 default:
10770 abort ();
10771 }
10772 }
10773 break;
10774
10775 default:
10776 abort ();
10777 }
10778 }
05413229
NC		 10779
10780 if (value_in_comment > 32 || value_in_comment < -16)
10781 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10782 return;
c19d1205
ZW		 10783 }
10784
10785 /* No match. */
0b347048
TC		 10786 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10787 return;
c19d1205
ZW		 10788}
10789
62b3e311 10790/* Return the name of an V7M special register. */
fe56b6ce 10791
62b3e311
PB		 10792static const char *
10793psr_name (int regno)
10794{
10795 switch (regno)
10796 {
1a336194
TP		 10797 case 0x0: return "APSR";
10798 case 0x1: return "IAPSR";
10799 case 0x2: return "EAPSR";
10800 case 0x3: return "PSR";
10801 case 0x5: return "IPSR";
10802 case 0x6: return "EPSR";
10803 case 0x7: return "IEPSR";
10804 case 0x8: return "MSP";
10805 case 0x9: return "PSP";
10806 case 0xa: return "MSPLIM";
10807 case 0xb: return "PSPLIM";
10808 case 0x10: return "PRIMASK";
10809 case 0x11: return "BASEPRI";
10810 case 0x12: return "BASEPRI_MAX";
10811 case 0x13: return "FAULTMASK";
10812 case 0x14: return "CONTROL";
16a1fa25
TP		 10813 case 0x88: return "MSP_NS";
10814 case 0x89: return "PSP_NS";
1a336194
TP		 10815 case 0x8a: return "MSPLIM_NS";
10816 case 0x8b: return "PSPLIM_NS";
10817 case 0x90: return "PRIMASK_NS";
10818 case 0x91: return "BASEPRI_NS";
10819 case 0x93: return "FAULTMASK_NS";
10820 case 0x94: return "CONTROL_NS";
10821 case 0x98: return "SP_NS";
62b3e311
PB		 10822 default: return "<unknown>";
10823 }
10824}
10825
4a5329c6
ZW		 10826/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10827
10828static void
10829print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10830{
6b5d3a4d 10831 const struct opcode32 *insn;
c19d1205
ZW		 10832 void *stream = info->stream;
10833 fprintf_ftype func = info->fprintf_func;
78933a4a 10834 bool is_mve = is_mve_architecture (info);
c19d1205 10835
78933a4a 10836 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 10837 return;
10838
78933a4a 10839 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 10840 return;
10841
10842 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10843 return;
10844
78933a4a 10845 if (print_insn_cde (info, given, true))
4934a27c
MM		 10846 return;
10847
78933a4a 10848 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 10849 return;
10850
c19d1205
ZW		 10851 for (insn = thumb32_opcodes; insn->assembler; insn++)
10852 if ((given & insn->mask) == insn->value)
10853 {
78933a4a
AM		 10854 bool is_clrm = false;
10855 bool is_unpredictable = false;
05413229 10856 signed long value_in_comment = 0;
6b5d3a4d 10857 const char *c = insn->assembler;
05413229 10858
c19d1205
ZW		 10859 for (; *c; c++)
10860 {
10861 if (*c != '%')
10862 {
10863 func (stream, "%c", *c);
10864 continue;
10865 }
10866
10867 switch (*++c)
10868 {
10869 case '%':
10870 func (stream, "%%");
10871 break;
10872
c22aaad1
PB		 10873 case 'c':
10874 if (ifthen_state)
10875 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10876 break;
10877
10878 case 'x':
10879 if (ifthen_next_state)
10880 func (stream, "\t; unpredictable branch in IT block\n");
10881 break;
10882
10883 case 'X':
10884 if (ifthen_state)
10885 func (stream, "\t; unpredictable <IT:%s>",
10886 arm_conditional[IFTHEN_COND]);
10887 break;
10888
c19d1205
ZW		 10889 case 'I':
10890 {
10891 unsigned int imm12 = 0;
fe56b6ce 10892
c19d1205
ZW		 10893 imm12 |= (given & 0x000000ffu);
10894 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10895 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10896 func (stream, "#%u", imm12);
10897 value_in_comment = imm12;
c19d1205
ZW		 10898 }
10899 break;
10900
10901 case 'M':
10902 {
10903 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10904
c19d1205
ZW		 10905 bits |= (given & 0x000000ffu);
10906 bits |= (given & 0x00007000u) >> 4;
10907 bits |= (given & 0x04000000u) >> 15;
10908 imm8 = (bits & 0x0ff);
10909 mod = (bits & 0xf00) >> 8;
10910 switch (mod)
10911 {
10912 case 0: imm = imm8; break;
c1e26897
NC		 10913 case 1: imm = ((imm8 << 16) | imm8); break;
10914 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10915 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10916 default:
10917 mod = (bits & 0xf80) >> 7;
10918 imm8 = (bits & 0x07f) | 0x80;
10919 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10920 }
fe56b6ce
NC		 10921 func (stream, "#%u", imm);
10922 value_in_comment = imm;
c19d1205
ZW		 10923 }
10924 break;
43e65147 10925
c19d1205
ZW		 10926 case 'J':
10927 {
10928 unsigned int imm = 0;
fe56b6ce 10929
c19d1205
ZW		 10930 imm |= (given & 0x000000ffu);
10931 imm |= (given & 0x00007000u) >> 4;
10932 imm |= (given & 0x04000000u) >> 15;
10933 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10934 func (stream, "#%u", imm);
10935 value_in_comment = imm;
c19d1205
ZW		 10936 }
10937 break;
10938
10939 case 'K':
10940 {
10941 unsigned int imm = 0;
fe56b6ce 10942
c19d1205
ZW		 10943 imm |= (given & 0x000f0000u) >> 16;
10944 imm |= (given & 0x00000ff0u) >> 0;
10945 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10946 func (stream, "#%u", imm);
10947 value_in_comment = imm;
c19d1205
ZW		 10948 }
10949 break;
10950
74db7efb
NC		 10951 case 'H':
10952 {
10953 unsigned int imm = 0;
10954
10955 imm |= (given & 0x000f0000u) >> 4;
10956 imm |= (given & 0x00000fffu) >> 0;
10957 func (stream, "#%u", imm);
10958 value_in_comment = imm;
10959 }
10960 break;
10961
90ec0d68
MGD		 10962 case 'V':
10963 {
10964 unsigned int imm = 0;
10965
10966 imm |= (given & 0x00000fffu);
10967 imm |= (given & 0x000f0000u) >> 4;
10968 func (stream, "#%u", imm);
10969 value_in_comment = imm;
10970 }
10971 break;
10972
c19d1205
ZW		 10973 case 'S':
10974 {
10975 unsigned int reg = (given & 0x0000000fu);
10976 unsigned int stp = (given & 0x00000030u) >> 4;
10977 unsigned int imm = 0;
10978 imm |= (given & 0x000000c0u) >> 6;
10979 imm |= (given & 0x00007000u) >> 10;
10980
10981 func (stream, "%s", arm_regnames[reg]);
10982 switch (stp)
10983 {
10984 case 0:
10985 if (imm > 0)
10986 func (stream, ", lsl #%u", imm);
10987 break;
10988
10989 case 1:
10990 if (imm == 0)
10991 imm = 32;
10992 func (stream, ", lsr #%u", imm);
10993 break;
10994
10995 case 2:
10996 if (imm == 0)
10997 imm = 32;
10998 func (stream, ", asr #%u", imm);
10999 break;
11000
11001 case 3:
11002 if (imm == 0)
11003 func (stream, ", rrx");
11004 else
11005 func (stream, ", ror #%u", imm);
11006 }
11007 }
11008 break;
11009
11010 case 'a':
11011 {
11012 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11013 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11014 unsigned int op = (given & 0x00000f00) >> 8;
11015 unsigned int i12 = (given & 0x00000fff);
11016 unsigned int i8 = (given & 0x000000ff);
78933a4a 11017 bool writeback = false, postind = false;
f8b960bc 11018 bfd_vma offset = 0;
c19d1205
ZW		 11019
11020 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 11021 if (U) /* 12-bit positive immediate offset. */
11022 {
11023 offset = i12;
11024 if (Rn != 15)
11025 value_in_comment = offset;
11026 }
11027 else if (Rn == 15) /* 12-bit negative immediate offset. */
11028 offset = - (int) i12;
11029 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11030 {
11031 unsigned int Rm = (i8 & 0x0f);
11032 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11033
c19d1205
ZW		 11034 func (stream, ", %s", arm_regnames[Rm]);
11035 if (sh)
11036 func (stream, ", lsl #%u", sh);
11037 func (stream, "]");
11038 break;
11039 }
11040 else switch (op)
11041 {
05413229 11042 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11043 offset = i8;
11044 break;
11045
05413229 11046 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11047 offset = -i8;
11048 break;
11049
05413229 11050 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11051 offset = i8;
78933a4a 11052 writeback = true;
c19d1205
ZW		 11053 break;
11054
05413229 11055 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11056 offset = -i8;
78933a4a 11057 writeback = true;
c19d1205
ZW		 11058 break;
11059
05413229 11060 case 0xB: /* 8-bit + postindex. */
c19d1205 11061 offset = i8;
78933a4a 11062 postind = true;
c19d1205
ZW		 11063 break;
11064
05413229 11065 case 0x9: /* 8-bit - postindex. */
c19d1205 11066 offset = -i8;
78933a4a 11067 postind = true;
c19d1205
ZW		 11068 break;
11069
11070 default:
11071 func (stream, ", <undefined>]");
11072 goto skip;
11073 }
11074
11075 if (postind)
d908c8af 11076 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 11077 else
11078 {
11079 if (offset)
d908c8af 11080 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 11081 func (stream, writeback ? "]!" : "]");
11082 }
11083
11084 if (Rn == 15)
11085 {
11086 func (stream, "\t; ");
11087 info->print_address_func (((pc + 4) & ~3) + offset, info);
11088 }
11089 }
11090 skip:
11091 break;
11092
11093 case 'A':
11094 {
c1e26897
NC		 11095 unsigned int U = ! NEGATIVE_BIT_SET;
11096 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11097 unsigned int Rn = (given & 0x000f0000) >> 16;
11098 unsigned int off = (given & 0x000000ff);
11099
11100 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 11101
11102 if (PRE_BIT_SET)
c19d1205
ZW		 11103 {
11104 if (off || !U)
05413229
NC		 11105 {
11106 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 11107 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11108 }
c19d1205
ZW		 11109 func (stream, "]");
11110 if (W)
11111 func (stream, "!");
11112 }
11113 else
11114 {
11115 func (stream, "], ");
11116 if (W)
05413229
NC		 11117 {
11118 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 11119 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11120 }
c19d1205 11121 else
fe56b6ce
NC		 11122 {
11123 func (stream, "{%u}", off);
11124 value_in_comment = off;
11125 }
c19d1205
ZW		 11126 }
11127 }
11128 break;
11129
11130 case 'w':
11131 {
11132 unsigned int Sbit = (given & 0x01000000) >> 24;
11133 unsigned int type = (given & 0x00600000) >> 21;
05413229 11134
c19d1205
ZW		 11135 switch (type)
11136 {
11137 case 0: func (stream, Sbit ? "sb" : "b"); break;
11138 case 1: func (stream, Sbit ? "sh" : "h"); break;
11139 case 2:
11140 if (Sbit)
11141 func (stream, "??");
11142 break;
11143 case 3:
11144 func (stream, "??");
11145 break;
11146 }
11147 }
11148 break;
11149
4b5a202f 11150 case 'n':
78933a4a 11151 is_clrm = true;
4b5a202f 11152 /* Fall through. */
c19d1205
ZW		 11153 case 'm':
11154 {
11155 int started = 0;
11156 int reg;
11157
11158 func (stream, "{");
11159 for (reg = 0; reg < 16; reg++)
11160 if ((given & (1 << reg)) != 0)
11161 {
11162 if (started)
11163 func (stream, ", ");
11164 started = 1;
4b5a202f
AV		 11165 if (is_clrm && reg == 13)
11166 func (stream, "(invalid: %s)", arm_regnames[reg]);
11167 else if (is_clrm && reg == 15)
11168 func (stream, "%s", "APSR");
11169 else
11170 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 11171 }
11172 func (stream, "}");
11173 }
11174 break;
11175
11176 case 'E':
11177 {
11178 unsigned int msb = (given & 0x0000001f);
11179 unsigned int lsb = 0;
fe56b6ce 11180
c19d1205
ZW		 11181 lsb |= (given & 0x000000c0u) >> 6;
11182 lsb |= (given & 0x00007000u) >> 10;
11183 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11184 }
11185 break;
11186
11187 case 'F':
11188 {
11189 unsigned int width = (given & 0x0000001f) + 1;
11190 unsigned int lsb = 0;
fe56b6ce 11191
c19d1205
ZW		 11192 lsb |= (given & 0x000000c0u) >> 6;
11193 lsb |= (given & 0x00007000u) >> 10;
11194 func (stream, "#%u, #%u", lsb, width);
11195 }
11196 break;
11197
e12437dc
AV		 11198 case 'G':
11199 {
11200 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11201 func (stream, "%x", boff);
11202 }
11203 break;
11204
e5d6e09e
AV		 11205 case 'W':
11206 {
11207 unsigned int immA = (given & 0x001f0000u) >> 16;
11208 unsigned int immB = (given & 0x000007feu) >> 1;
11209 unsigned int immC = (given & 0x00000800u) >> 11;
11210 bfd_vma offset = 0;
11211
11212 offset |= immA << 12;
11213 offset |= immB << 2;
11214 offset |= immC << 1;
11215 /* Sign extend. */
11216 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11217
11218 info->print_address_func (pc + 4 + offset, info);
11219 }
11220 break;
11221
1caf72a5
AV		 11222 case 'Y':
11223 {
11224 unsigned int immA = (given & 0x007f0000u) >> 16;
11225 unsigned int immB = (given & 0x000007feu) >> 1;
11226 unsigned int immC = (given & 0x00000800u) >> 11;
11227 bfd_vma offset = 0;
11228
11229 offset |= immA << 12;
11230 offset |= immB << 2;
11231 offset |= immC << 1;
11232 /* Sign extend. */
11233 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11234
11235 info->print_address_func (pc + 4 + offset, info);
11236 }
11237 break;
11238
1889da70
AV		 11239 case 'Z':
11240 {
11241 unsigned int immA = (given & 0x00010000u) >> 16;
11242 unsigned int immB = (given & 0x000007feu) >> 1;
11243 unsigned int immC = (given & 0x00000800u) >> 11;
11244 bfd_vma offset = 0;
11245
11246 offset |= immA << 12;
11247 offset |= immB << 2;
11248 offset |= immC << 1;
11249 /* Sign extend. */
11250 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11251
11252 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11253
11254 unsigned int T = (given & 0x00020000u) >> 17;
11255 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11256 unsigned int boffset = (T == 1) ? 4 : 2;
11257 func (stream, ", ");
11258 func (stream, "%x", endoffset + boffset);
1889da70
AV		 11259 }
11260 break;
11261
60f993ce
AV		 11262 case 'Q':
11263 {
11264 unsigned int immh = (given & 0x000007feu) >> 1;
11265 unsigned int imml = (given & 0x00000800u) >> 11;
11266 bfd_vma imm32 = 0;
11267
11268 imm32 |= immh << 2;
11269 imm32 |= imml << 1;
11270
11271 info->print_address_func (pc + 4 + imm32, info);
11272 }
11273 break;
11274
11275 case 'P':
11276 {
11277 unsigned int immh = (given & 0x000007feu) >> 1;
11278 unsigned int imml = (given & 0x00000800u) >> 11;
11279 bfd_vma imm32 = 0;
11280
11281 imm32 |= immh << 2;
11282 imm32 |= imml << 1;
11283
11284 info->print_address_func (pc + 4 - imm32, info);
11285 }
11286 break;
11287
c19d1205
ZW		 11288 case 'b':
11289 {
11290 unsigned int S = (given & 0x04000000u) >> 26;
11291 unsigned int J1 = (given & 0x00002000u) >> 13;
11292 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11293 bfd_vma offset = 0;
c19d1205
ZW		 11294
11295 offset |= !S << 20;
11296 offset |= J2 << 19;
11297 offset |= J1 << 18;
11298 offset |= (given & 0x003f0000) >> 4;
11299 offset |= (given & 0x000007ff) << 1;
11300 offset -= (1 << 20);
11301
1d67fe3b
TT		 11302 bfd_vma target = pc + 4 + offset;
11303 info->print_address_func (target, info);
11304
11305 /* Fill in instruction information. */
11306 info->insn_info_valid = 1;
11307 info->insn_type = dis_branch;
11308 info->target = target;
c19d1205
ZW		 11309 }
11310 break;
11311
11312 case 'B':
11313 {
11314 unsigned int S = (given & 0x04000000u) >> 26;
11315 unsigned int I1 = (given & 0x00002000u) >> 13;
11316 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11317 bfd_vma offset = 0;
c19d1205
ZW		 11318
11319 offset |= !S << 24;
11320 offset |= !(I1 ^ S) << 23;
11321 offset |= !(I2 ^ S) << 22;
11322 offset |= (given & 0x03ff0000u) >> 4;
11323 offset |= (given & 0x000007ffu) << 1;
11324 offset -= (1 << 24);
36b0c57d 11325 offset += pc + 4;
c19d1205 11326
36b0c57d
PB		 11327 /* BLX target addresses are always word aligned. */
11328 if ((given & 0x00001000u) == 0)
11329 offset &= ~2u;
11330
11331 info->print_address_func (offset, info);
1d67fe3b
TT		 11332
11333 /* Fill in instruction information. */
11334 info->insn_info_valid = 1;
11335 info->insn_type = dis_branch;
11336 info->target = offset;
c19d1205
ZW		 11337 }
11338 break;
11339
11340 case 's':
11341 {
11342 unsigned int shift = 0;
fe56b6ce 11343
c19d1205
ZW		 11344 shift |= (given & 0x000000c0u) >> 6;
11345 shift |= (given & 0x00007000u) >> 10;
c1e26897 11346 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11347 func (stream, ", asr #%u", shift);
11348 else if (shift)
11349 func (stream, ", lsl #%u", shift);
11350 /* else print nothing - lsl #0 */
11351 }
11352 break;
11353
11354 case 'R':
11355 {
11356 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11357
c19d1205
ZW		 11358 if (rot)
11359 func (stream, ", ror #%u", rot * 8);
11360 }
11361 break;
11362
62b3e311 11363 case 'U':
43e65147 11364 if ((given & 0xf0) == 0x60)
62b3e311 11365 {
52e7f43d
RE		 11366 switch (given & 0xf)
11367 {
11368 case 0xf: func (stream, "sy"); break;
11369 default:
11370 func (stream, "#%d", (int) given & 0xf);
11371 break;
11372 }
62b3e311 11373 }
43e65147 11374 else
52e7f43d 11375 {
e797f7e0
MGD		 11376 const char * opt = data_barrier_option (given & 0xf);
11377 if (opt != NULL)
11378 func (stream, "%s", opt);
11379 else
11380 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11381 }
62b3e311
PB		 11382 break;
11383
11384 case 'C':
11385 if ((given & 0xff) == 0)
11386 {
11387 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11388 if (given & 0x800)
11389 func (stream, "f");
11390 if (given & 0x400)
11391 func (stream, "s");
11392 if (given & 0x200)
11393 func (stream, "x");
11394 if (given & 0x100)
11395 func (stream, "c");
11396 }
90ec0d68
MGD		 11397 else if ((given & 0x20) == 0x20)
11398 {
11399 char const* name;
11400 unsigned sysm = (given & 0xf00) >> 8;
11401
11402 sysm |= (given & 0x30);
11403 sysm |= (given & 0x00100000) >> 14;
11404 name = banked_regname (sysm);
43e65147 11405
90ec0d68
MGD		 11406 if (name != NULL)
11407 func (stream, "%s", name);
11408 else
d908c8af 11409 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11410 }
62b3e311
PB		 11411 else
11412 {
d908c8af 11413 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11414 }
11415 break;
11416
11417 case 'D':
90ec0d68
MGD		 11418 if (((given & 0xff) == 0)
11419 || ((given & 0x20) == 0x20))
11420 {
11421 char const* name;
11422 unsigned sm = (given & 0xf0000) >> 16;
11423
11424 sm |= (given & 0x30);
11425 sm |= (given & 0x00100000) >> 14;
11426 name = banked_regname (sm);
11427
11428 if (name != NULL)
11429 func (stream, "%s", name);
11430 else
d908c8af 11431 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11432 }
62b3e311 11433 else
d908c8af 11434 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11435 break;
11436
c19d1205
ZW		 11437 case '0': case '1': case '2': case '3': case '4':
11438 case '5': case '6': case '7': case '8': case '9':
11439 {
16980d0b
JB		 11440 int width;
11441 unsigned long val;
c19d1205 11442
16980d0b 11443 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11444
c19d1205
ZW		 11445 switch (*c)
11446 {
d052b9b7
AV		 11447 case 's':
11448 if (val <= 3)
11449 func (stream, "%s", mve_vec_sizename[val]);
11450 else
11451 func (stream, "<undef size>");
11452 break;
11453
05413229
NC		 11454 case 'd':
11455 func (stream, "%lu", val);
11456 value_in_comment = val;
11457 break;
ff4a8d2b 11458
f0fba320
RL		 11459 case 'D':
11460 func (stream, "%lu", val + 1);
11461 value_in_comment = val + 1;
11462 break;
11463
05413229
NC		 11464 case 'W':
11465 func (stream, "%lu", val * 4);
11466 value_in_comment = val * 4;
11467 break;
ff4a8d2b 11468
f1c7f421
AV		 11469 case 'S':
11470 if (val == 13)
78933a4a 11471 is_unpredictable = true;
f1c7f421 11472 /* Fall through. */
ff4a8d2b
NC		 11473 case 'R':
11474 if (val == 15)
78933a4a 11475 is_unpredictable = true;
ff4a8d2b
NC		 11476 /* Fall through. */
11477 case 'r':
11478 func (stream, "%s", arm_regnames[val]);
11479 break;
c19d1205
ZW		 11480
11481 case 'c':
c22aaad1 11482 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11483 break;
11484
11485 case '\'':
c19d1205 11486 c++;
16980d0b
JB		 11487 if (val == ((1ul << width) - 1))
11488 func (stream, "%c", *c);
c19d1205 11489 break;
43e65147 11490
c19d1205 11491 case '`':
c19d1205 11492 c++;
16980d0b
JB		 11493 if (val == 0)
11494 func (stream, "%c", *c);
c19d1205
ZW		 11495 break;
11496
11497 case '?':
fe56b6ce 11498 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11499 c += 1 << width;
c19d1205 11500 break;
43e65147 11501
0bb027fd
RR		 11502 case 'x':
11503 func (stream, "0x%lx", val & 0xffffffffUL);
11504 break;
c19d1205
ZW		 11505
11506 default:
11507 abort ();
11508 }
11509 }
11510 break;
11511
32a94698
NC		 11512 case 'L':
11513 /* PR binutils/12534
11514 If we have a PC relative offset in an LDRD or STRD
11515 instructions then display the decoded address. */
11516 if (((given >> 16) & 0xf) == 0xf)
11517 {
11518 bfd_vma offset = (given & 0xff) * 4;
11519
11520 if ((given & (1 << 23)) == 0)
11521 offset = - offset;
11522 func (stream, "\t; ");
11523 info->print_address_func ((pc & ~3) + 4 + offset, info);
11524 }
11525 break;
11526
c19d1205
ZW		 11527 default:
11528 abort ();
11529 }
11530 }
05413229
NC		 11531
11532 if (value_in_comment > 32 || value_in_comment < -16)
11533 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11534
11535 if (is_unpredictable)
11536 func (stream, UNPREDICTABLE_INSTRUCTION);
11537
4a5329c6 11538 return;
c19d1205 11539 }
252b5132 11540
58efb6c0 11541 /* No match. */
0b347048
TC		 11542 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11543 return;
252b5132
RH		 11544}
11545
e821645d
DJ		 11546/* Print data bytes on INFO->STREAM. */
11547
11548static void
fe56b6ce
NC		 11549print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11550 struct disassemble_info *info,
e821645d
DJ		 11551 long given)
11552{
11553 switch (info->bytes_per_chunk)
11554 {
11555 case 1:
11556 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11557 break;
11558 case 2:
11559 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11560 break;
11561 case 4:
11562 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11563 break;
11564 default:
11565 abort ();
11566 }
11567}
11568
22a398e1 11569/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11570 being displayed in symbol relative addresses.
11571
11572 Also disallow private symbol, with __tagsym$$ prefix,
11573 from ARM RVCT toolchain being displayed. */
22a398e1 11574
78933a4a 11575bool
22a398e1
NC		 11576arm_symbol_is_valid (asymbol * sym,
11577 struct disassemble_info * info ATTRIBUTE_UNUSED)
11578{
11579 const char * name;
43e65147 11580
22a398e1 11581 if (sym == NULL)
78933a4a 11582 return false;
22a398e1
NC		 11583
11584 name = bfd_asymbol_name (sym);
11585
d8282f0e 11586 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11587}
11588
65b48a81 11589/* Parse the string of disassembler options. */
baf0cc5e 11590
65b48a81 11591static void
f995bbe8 11592parse_arm_disassembler_options (const char *options)
dd92f639 11593{
f995bbe8 11594 const char *opt;
b34976b6 11595
65b48a81 11596 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11597 {
08dedd66 11598 if (startswith (opt, "reg-names-"))
65b48a81
PB		 11599 {
11600 unsigned int i;
11601 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11602 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11603 {
11604 regname_selected = i;
11605 break;
11606 }
b34976b6 11607
65b48a81 11608 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11609 /* xgettext: c-format */
11610 opcodes_error_handler (_("unrecognised register name set: %s"),
11611 opt);
65b48a81 11612 }
08dedd66 11613 else if (startswith (opt, "force-thumb"))
65b48a81 11614 force_thumb = 1;
08dedd66 11615 else if (startswith (opt, "no-force-thumb"))
65b48a81 11616 force_thumb = 0;
08dedd66 11617 else if (startswith (opt, "coproc"))
4934a27c
MM		 11618 {
11619 const char *procptr = opt + sizeof ("coproc") - 1;
11620 char *endptr;
11621 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11622 if (endptr != procptr + 1 || coproc_number > 7)
11623 {
11624 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11625 opt);
11626 continue;
11627 }
11628 if (*endptr != '=')
11629 {
11630 opcodes_error_handler (_("coproc must have an argument: %s"),
11631 opt);
11632 continue;
11633 }
11634 endptr += 1;
08dedd66 11635 if (startswith (endptr, "generic"))
4934a27c 11636 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 11637 else if (startswith (endptr, "cde")
11638 || startswith (endptr, "CDE"))
4934a27c
MM		 11639 cde_coprocs |= (1 << coproc_number);
11640 else
11641 {
11642 opcodes_error_handler (
11643 _("coprocN argument takes options \"generic\","
11644 " \"cde\", or \"CDE\": %s"), opt);
11645 }
11646 }
65b48a81 11647 else
a6743a54
AM		 11648 /* xgettext: c-format */
11649 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11650 }
b34976b6 11651
dd92f639
NC		 11652 return;
11653}
11654
78933a4a 11655static bool
5bc5ae88
RL		 11656mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11657 enum map_type *map_symbol);
11658
c22aaad1
PB		 11659/* Search back through the insn stream to determine if this instruction is
11660 conditionally executed. */
fe56b6ce 11661
c22aaad1 11662static void
fe56b6ce
NC		 11663find_ifthen_state (bfd_vma pc,
11664 struct disassemble_info *info,
78933a4a 11665 bool little)
c22aaad1
PB		 11666{
11667 unsigned char b[2];
11668 unsigned int insn;
11669 int status;
11670 /* COUNT is twice the number of instructions seen. It will be odd if we
11671 just crossed an instruction boundary. */
11672 int count;
11673 int it_count;
11674 unsigned int seen_it;
11675 bfd_vma addr;
11676
11677 ifthen_address = pc;
11678 ifthen_state = 0;
11679
11680 addr = pc;
11681 count = 1;
11682 it_count = 0;
11683 seen_it = 0;
11684 /* Scan backwards looking for IT instructions, keeping track of where
11685 instruction boundaries are. We don't know if something is actually an
11686 IT instruction until we find a definite instruction boundary. */
11687 for (;;)
11688 {
fe56b6ce 11689 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11690 {
11691 /* A symbol must be on an instruction boundary, and will not
11692 be within an IT block. */
11693 if (seen_it && (count & 1))
11694 break;
11695
11696 return;
11697 }
11698 addr -= 2;
fe56b6ce 11699 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11700 if (status)
11701 return;
11702
11703 if (little)
11704 insn = (b[0]) | (b[1] << 8);
11705 else
11706 insn = (b[1]) | (b[0] << 8);
11707 if (seen_it)
11708 {
11709 if ((insn & 0xf800) < 0xe800)
11710 {
11711 /* Addr + 2 is an instruction boundary. See if this matches
11712 the expected boundary based on the position of the last
11713 IT candidate. */
11714 if (count & 1)
11715 break;
11716 seen_it = 0;
11717 }
11718 }
11719 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11720 {
5bc5ae88 11721 enum map_type type = MAP_ARM;
78933a4a 11722 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 11723
11724 if (!found || (found && type == MAP_THUMB))
11725 {
11726 /* This could be an IT instruction. */
11727 seen_it = insn;
11728 it_count = count >> 1;
11729 }
c22aaad1
PB		 11730 }
11731 if ((insn & 0xf800) >= 0xe800)
11732 count++;
11733 else
11734 count = (count + 2) | 1;
11735 /* IT blocks contain at most 4 instructions. */
11736 if (count >= 8 && !seen_it)
11737 return;
11738 }
11739 /* We found an IT instruction. */
11740 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11741 if ((ifthen_state & 0xf) == 0)
11742 ifthen_state = 0;
11743}
11744
b0e28b39
DJ		 11745/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11746 mapping symbol. */
11747
11748static int
11749is_mapping_symbol (struct disassemble_info *info, int n,
11750 enum map_type *map_type)
11751{
11752 const char *name;
11753
11754 name = bfd_asymbol_name (info->symtab[n]);
11755 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11756 && (name[2] == 0 || name[2] == '.'))
11757 {
11758 *map_type = ((name[1] == 'a') ? MAP_ARM
11759 : (name[1] == 't') ? MAP_THUMB
11760 : MAP_DATA);
78933a4a 11761 return true;
b0e28b39
DJ		 11762 }
11763
78933a4a 11764 return false;
b0e28b39
DJ		 11765}
11766
11767/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11768 Returns nonzero if *MAP_TYPE was set. */
11769
11770static int
11771get_map_sym_type (struct disassemble_info *info,
11772 int n,
11773 enum map_type *map_type)
11774{
11775 /* If the symbol is in a different section, ignore it. */
11776 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 11777 return false;
b0e28b39
DJ		 11778
11779 return is_mapping_symbol (info, n, map_type);
11780}
11781
11782/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11783 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11784
11785static int
fe56b6ce
NC		 11786get_sym_code_type (struct disassemble_info *info,
11787 int n,
e821645d 11788 enum map_type *map_type)
2087ad84
PB		 11789{
11790 elf_symbol_type *es;
11791 unsigned int type;
b0e28b39
DJ		 11792
11793 /* If the symbol is in a different section, ignore it. */
11794 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 11795 return false;
2087ad84 11796
e821645d 11797 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11798 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11799
11800 /* If the symbol has function type then use that. */
34e77a92 11801 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11802 {
39d911fc
TP		 11803 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11804 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11805 *map_type = MAP_THUMB;
11806 else
11807 *map_type = MAP_ARM;
78933a4a 11808 return true;
2087ad84
PB		 11809 }
11810
78933a4a 11811 return false;
2087ad84
PB		 11812}
11813
5bc5ae88
RL		 11814/* Search the mapping symbol state for instruction at pc. This is only
11815 applicable for elf target.
11816
11817 There is an assumption Here, info->private_data contains the correct AND
11818 up-to-date information about current scan process. The information will be
11819 used to speed this search process.
11820
11821 Return TRUE if the mapping state can be determined, and map_symbol
11822 will be updated accordingly. Otherwise, return FALSE. */
11823
78933a4a 11824static bool
5bc5ae88
RL		 11825mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11826 enum map_type *map_symbol)
11827{
796d6298
TC		 11828 bfd_vma addr, section_vma = 0;
11829 int n, last_sym = -1;
78933a4a
AM		 11830 bool found = false;
11831 bool can_use_search_opt_p = false;
796d6298
TC		 11832
11833 /* Default to DATA. A text section is required by the ABI to contain an
11834 INSN mapping symbol at the start. A data section has no such
11835 requirement, hence if no mapping symbol is found the section must
11836 contain only data. This however isn't very useful if the user has
11837 fully stripped the binaries. If this is the case use the section
11838 attributes to determine the default. If we have no section default to
11839 INSN as well, as we may be disassembling some raw bytes on a baremetal
11840 HEX file or similar. */
11841 enum map_type type = MAP_DATA;
11842 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11843 type = MAP_ARM;
5bc5ae88
RL		 11844 struct arm_private_data *private_data;
11845
796d6298 11846 if (info->private_data == NULL
5bc5ae88 11847 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 11848 return false;
5bc5ae88
RL		 11849
11850 private_data = info->private_data;
5bc5ae88 11851
796d6298
TC		 11852 /* First, look for mapping symbols. */
11853 if (info->symtab_size != 0)
11854 {
11855 if (pc <= private_data->last_mapping_addr)
11856 private_data->last_mapping_sym = -1;
11857
11858 /* Start scanning at the start of the function, or wherever
11859 we finished last time. */
11860 n = info->symtab_pos + 1;
11861
11862 /* If the last stop offset is different from the current one it means we
11863 are disassembling a different glob of bytes. As such the optimization
11864 would not be safe and we should start over. */
11865 can_use_search_opt_p
11866 = private_data->last_mapping_sym >= 0
11867 && info->stop_offset == private_data->last_stop_offset;
11868
11869 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11870 n = private_data->last_mapping_sym;
11871
11872 /* Look down while we haven't passed the location being disassembled.
11873 The reason for this is that there's no defined order between a symbol
11874 and an mapping symbol that may be at the same address. We may have to
11875 look at least one position ahead. */
11876 for (; n < info->symtab_size; n++)
11877 {
11878 addr = bfd_asymbol_value (info->symtab[n]);
11879 if (addr > pc)
11880 break;
11881 if (get_map_sym_type (info, n, &type))
11882 {
11883 last_sym = n;
78933a4a 11884 found = true;
796d6298
TC		 11885 }
11886 }
5bc5ae88 11887
796d6298
TC		 11888 if (!found)
11889 {
11890 n = info->symtab_pos;
11891 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11892 n = private_data->last_mapping_sym;
11893
11894 /* No mapping symbol found at this address. Look backwards
11895 for a preceeding one, but don't go pass the section start
11896 otherwise a data section with no mapping symbol can pick up
11897 a text mapping symbol of a preceeding section. The documentation
11898 says section can be NULL, in which case we will seek up all the
11899 way to the top. */
11900 if (info->section)
11901 section_vma = info->section->vma;
11902
11903 for (; n >= 0; n--)
11904 {
11905 addr = bfd_asymbol_value (info->symtab[n]);
11906 if (addr < section_vma)
11907 break;
11908
11909 if (get_map_sym_type (info, n, &type))
11910 {
11911 last_sym = n;
78933a4a 11912 found = true;
796d6298
TC		 11913 break;
11914 }
11915 }
11916 }
11917 }
11918
11919 /* If no mapping symbol was found, try looking up without a mapping
11920 symbol. This is done by walking up from the current PC to the nearest
11921 symbol. We don't actually have to loop here since symtab_pos will
11922 contain the nearest symbol already. */
11923 if (!found)
5bc5ae88 11924 {
796d6298
TC		 11925 n = info->symtab_pos;
11926 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11927 {
796d6298 11928 last_sym = n;
78933a4a 11929 found = true;
5bc5ae88
RL		 11930 }
11931 }
11932
796d6298
TC		 11933 private_data->last_mapping_sym = last_sym;
11934 private_data->last_type = type;
11935 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11936
11937 *map_symbol = type;
11938 return found;
11939}
11940
0313a2b8
NC		 11941/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11942 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11943 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11944
11945 FIXME: This could more efficiently implemented as a constant array,
11946 although it would also be less robust. */
11947
11948static void
11949select_arm_features (unsigned long mach,
11950 arm_feature_set * features)
11951{
c0c468d5
TP		 11952 arm_feature_set arch_fset;
11953 const arm_feature_set fpu_any = FPU_ANY;
11954
1af1dd51
MW		 11955#undef ARM_SET_FEATURES
11956#define ARM_SET_FEATURES(FSET) \
11957 { \
11958 const arm_feature_set fset = FSET; \
c0c468d5 11959 arch_fset = fset; \
1af1dd51 11960 }
823d2571 11961
c0c468d5
TP		 11962 /* When several architecture versions share the same bfd_mach_arm_XXX value
11963 the most featureful is chosen. */
0313a2b8
NC		 11964 switch (mach)
11965 {
c0c468d5
TP		 11966 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11967 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11968 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11969 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11970 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11971 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11972 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11973 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11974 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11975 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11976 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11977 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11978 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11979 break;
c0c468d5
TP		 11980 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11981 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11982 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11983 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11984 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11985 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11986 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11987 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11988 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11989 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11990 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11991 case bfd_mach_arm_8:
11992 {
aab2c27d
MM		 11993 /* Add bits for extensions that Armv8.6-A recognizes. */
11994 arm_feature_set armv8_6_ext_fset
0632eeea 11995 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11996 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11997 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 11998 break;
11999 }
12000 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12001 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12002 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12003 case bfd_mach_arm_8_1M_MAIN:
12004 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12005 arm_feature_set mve_all
12006 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12007 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12008 force_thumb = 1;
12009 break;
c0c468d5 12010 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12011 extensions, with the exception of MVE as that clashes with NEON. */
12012 case bfd_mach_arm_unknown:
12013 ARM_SET_FEATURES (ARM_FEATURE (-1,
12014 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12015 -1));
12016 break;
0313a2b8
NC		 12017 default:
12018 abort ();
12019 }
1af1dd51 12020#undef ARM_SET_FEATURES
c0c468d5
TP		 12021
12022 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12023 and thus on bfd_mach_arm_XXX value. Therefore for a given
12024 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12025 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12026}
12027
12028
58efb6c0
NC		 12029/* NOTE: There are no checks in these routines that
12030 the relevant number of data bytes exist. */
baf0cc5e 12031
58efb6c0 12032static int
78933a4a 12033print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12034{
c19d1205 12035 unsigned char b[4];
2480b6fa 12036 unsigned long given;
78933a4a
AM		 12037 int status;
12038 int is_thumb = false;
12039 int is_data = false;
12040 int little_code;
e821645d 12041 unsigned int size = 4;
78933a4a
AM		 12042 void (*printer) (bfd_vma, struct disassemble_info *, long);
12043 bool found = false;
b0e28b39 12044 struct arm_private_data *private_data;
58efb6c0 12045
1d67fe3b
TT		 12046 /* Clear instruction information field. */
12047 info->insn_info_valid = 0;
12048 info->branch_delay_insns = 0;
12049 info->data_size = 0;
12050 info->insn_type = dis_noninsn;
12051 info->target = 0;
12052 info->target2 = 0;
12053
dd92f639
NC		 12054 if (info->disassembler_options)
12055 {
65b48a81 12056 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12057
58efb6c0 12058 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12059 info->disassembler_options = NULL;
12060 }
b34976b6 12061
0313a2b8
NC		 12062 /* PR 10288: Control which instructions will be disassembled. */
12063 if (info->private_data == NULL)
12064 {
b0e28b39 12065 static struct arm_private_data private;
0313a2b8
NC		 12066
12067 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12068 /* If the user did not use the -m command line switch then default to
12069 disassembling all types of ARM instruction.
43e65147 12070
0313a2b8
NC		 12071 The info->mach value has to be ignored as this will be based on
12072 the default archictecture for the target and/or hints in the notes
12073 section, but it will never be greater than the current largest arm
12074 machine value (iWMMXt2), which is only equivalent to the V5TE
12075 architecture. ARM architectures have advanced beyond the machine
12076 value encoding, and these newer architectures would be ignored if
12077 the machine value was used.
12078
12079 Ie the -m switch is used to restrict which instructions will be
12080 disassembled. If it is necessary to use the -m switch to tell
12081 objdump that an ARM binary is being disassembled, eg because the
12082 input is a raw binary file, but it is also desired to disassemble
12083 all ARM instructions then use "-marm". This will select the
12084 "unknown" arm architecture which is compatible with any ARM
12085 instruction. */
12086 info->mach = bfd_mach_arm_unknown;
12087
12088 /* Compute the architecture bitmask from the machine number.
12089 Note: This assumes that the machine number will not change
12090 during disassembly.... */
b0e28b39 12091 select_arm_features (info->mach, & private.features);
0313a2b8 12092
1fbaefec
PB		 12093 private.last_mapping_sym = -1;
12094 private.last_mapping_addr = 0;
796d6298 12095 private.last_stop_offset = 0;
b0e28b39
DJ		 12096
12097 info->private_data = & private;
0313a2b8 12098 }
b0e28b39
DJ		 12099
12100 private_data = info->private_data;
12101
bd2e2557
SS		 12102 /* Decide if our code is going to be little-endian, despite what the
12103 function argument might say. */
12104 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12105
b0e28b39
DJ		 12106 /* For ELF, consult the symbol table to determine what kind of code
12107 or data we have. */
8977d4b2 12108 if (info->symtab_size != 0
e821645d
DJ		 12109 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12110 {
12111 bfd_vma addr;
796d6298 12112 int n;
e821645d 12113 int last_sym = -1;
b0e28b39 12114 enum map_type type = MAP_ARM;
e821645d 12115
796d6298
TC		 12116 found = mapping_symbol_for_insn (pc, info, &type);
12117 last_sym = private_data->last_mapping_sym;
e821645d 12118
1fbaefec
PB		 12119 is_thumb = (private_data->last_type == MAP_THUMB);
12120 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12121
e821645d
DJ		 12122 /* Look a little bit ahead to see if we should print out
12123 two or four bytes of data. If there's a symbol,
12124 mapping or otherwise, after two bytes then don't
12125 print more. */
12126 if (is_data)
12127 {
12128 size = 4 - (pc & 3);
12129 for (n = last_sym + 1; n < info->symtab_size; n++)
12130 {
12131 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12132 if (addr > pc
12133 && (info->section == NULL
12134 || info->section == info->symtab[n]->section))
e821645d
DJ		 12135 {
12136 if (addr - pc < size)
12137 size = addr - pc;
12138 break;
12139 }
12140 }
12141 /* If the next symbol is after three bytes, we need to
12142 print only part of the data, so that we can use either
12143 .byte or .short. */
12144 if (size == 3)
12145 size = (pc & 1) ? 1 : 2;
12146 }
12147 }
12148
12149 if (info->symbols != NULL)
252b5132 12150 {
5876e06d
NC		 12151 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12152 {
2f0ca46a 12153 coff_symbol_type * cs;
b34976b6 12154
5876e06d
NC		 12155 cs = coffsymbol (*info->symbols);
12156 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12157 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12158 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12159 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12160 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12161 }
e821645d
DJ		 12162 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12163 && !found)
5876e06d 12164 {
2087ad84
PB		 12165 /* If no mapping symbol has been found then fall back to the type
12166 of the function symbol. */
e821645d
DJ		 12167 elf_symbol_type * es;
12168 unsigned int type;
2087ad84 12169
e821645d
DJ		 12170 es = *(elf_symbol_type **)(info->symbols);
12171 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12172
39d911fc
TP		 12173 is_thumb =
12174 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12175 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12176 }
e49d43ff
TG		 12177 else if (bfd_asymbol_flavour (*info->symbols)
12178 == bfd_target_mach_o_flavour)
12179 {
12180 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12181
12182 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12183 }
5876e06d 12184 }
b34976b6 12185
e821645d 12186 if (force_thumb)
78933a4a 12187 is_thumb = true;
e821645d 12188
b8f9ee44
CL		 12189 if (is_data)
12190 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12191 else
12192 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12193
c19d1205 12194 info->bytes_per_line = 4;
252b5132 12195
1316c8b3
NC		 12196 /* PR 10263: Disassemble data if requested to do so by the user. */
12197 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12198 {
12199 int i;
12200
1316c8b3 12201 /* Size was already set above. */
e821645d
DJ		 12202 info->bytes_per_chunk = size;
12203 printer = print_insn_data;
12204
fe56b6ce 12205 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12206 given = 0;
12207 if (little)
12208 for (i = size - 1; i >= 0; i--)
12209 given = b[i] | (given << 8);
12210 else
12211 for (i = 0; i < (int) size; i++)
12212 given = b[i] | (given << 8);
12213 }
12214 else if (!is_thumb)
252b5132 12215 {
c19d1205
ZW		 12216 /* In ARM mode endianness is a straightforward issue: the instruction
12217 is four bytes long and is either ordered 0123 or 3210. */
12218 printer = print_insn_arm;
12219 info->bytes_per_chunk = 4;
4a5329c6 12220 size = 4;
c19d1205 12221
0313a2b8 12222 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12223 if (little_code)
2480b6fa 12224 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12225 else
2480b6fa 12226 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12227 }
58efb6c0 12228 else
252b5132 12229 {
c19d1205
ZW		 12230 /* In Thumb mode we have the additional wrinkle of two
12231 instruction lengths. Fortunately, the bits that determine
12232 the length of the current instruction are always to be found
12233 in the first two bytes. */
4a5329c6 12234 printer = print_insn_thumb16;
c19d1205 12235 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12236 size = 2;
12237
fe56b6ce 12238 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12239 if (little_code)
9a2ff3f5
AM		 12240 given = (b[0]) | (b[1] << 8);
12241 else
12242 given = (b[1]) | (b[0] << 8);
12243
c19d1205 12244 if (!status)
252b5132 12245 {
c19d1205
ZW		 12246 /* These bit patterns signal a four-byte Thumb
12247 instruction. */
12248 if ((given & 0xF800) == 0xF800
12249 || (given & 0xF800) == 0xF000
12250 || (given & 0xF800) == 0xE800)
252b5132 12251 {
0313a2b8 12252 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12253 if (little_code)
c19d1205 12254 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12255 else
c19d1205
ZW		 12256 given = (b[1]) | (b[0] << 8) | (given << 16);
12257
12258 printer = print_insn_thumb32;
4a5329c6 12259 size = 4;
252b5132 12260 }
252b5132 12261 }
c22aaad1
PB		 12262
12263 if (ifthen_address != pc)
0313a2b8 12264 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12265
12266 if (ifthen_state)
12267 {
12268 if ((ifthen_state & 0xf) == 0x8)
12269 ifthen_next_state = 0;
12270 else
12271 ifthen_next_state = (ifthen_state & 0xe0)
12272 | ((ifthen_state & 0xf) << 1);
12273 }
252b5132 12274 }
b34976b6 12275
c19d1205
ZW		 12276 if (status)
12277 {
12278 info->memory_error_func (status, pc, info);
12279 return -1;
12280 }
6a56ec7e
NC		 12281 if (info->flags & INSN_HAS_RELOC)
12282 /* If the instruction has a reloc associated with it, then
12283 the offset field in the instruction will actually be the
12284 addend for the reloc. (We are using REL type relocs).
12285 In such cases, we can ignore the pc when computing
12286 addresses, since the addend is not currently pc-relative. */
12287 pc = 0;
b34976b6 12288
4a5329c6 12289 printer (pc, info, given);
c22aaad1
PB		 12290
12291 if (is_thumb)
12292 {
12293 ifthen_state = ifthen_next_state;
12294 ifthen_address += size;
12295 }
4a5329c6 12296 return size;
252b5132
RH		 12297}
12298
12299int
4a5329c6 12300print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12301{
bd2e2557
SS		 12302 /* Detect BE8-ness and record it in the disassembler info. */
12303 if (info->flavour == bfd_target_elf_flavour
12304 && info->section != NULL
12305 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12306 info->endian_code = BFD_ENDIAN_LITTLE;
12307
78933a4a 12308 return print_insn (pc, info, false);
58efb6c0 12309}
01c7f630 12310
58efb6c0 12311int
4a5329c6 12312print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12313{
78933a4a 12314 return print_insn (pc, info, true);
58efb6c0 12315}
252b5132 12316
471b9d15 12317const disasm_options_and_args_t *
65b48a81
PB		 12318disassembler_options_arm (void)
12319{
471b9d15 12320 static disasm_options_and_args_t *opts_and_args;
65b48a81 12321
471b9d15 12322 if (opts_and_args == NULL)
65b48a81 12323 {
471b9d15 12324 disasm_options_t *opts;
65b48a81 12325 unsigned int i;
471b9d15
MR		 12326
12327 opts_and_args = XNEW (disasm_options_and_args_t);
12328 opts_and_args->args = NULL;
12329
12330 opts = &opts_and_args->options;
65b48a81
PB		 12331 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12332 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12333 opts->arg = NULL;
65b48a81
PB		 12334 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12335 {
12336 opts->name[i] = regnames[i].name;
12337 if (regnames[i].description != NULL)
12338 opts->description[i] = _(regnames[i].description);
12339 else
12340 opts->description[i] = NULL;
12341 }
12342 /* The array we return must be NULL terminated. */
12343 opts->name[i] = NULL;
12344 opts->description[i] = NULL;
12345 }
12346
471b9d15 12347 return opts_and_args;
65b48a81
PB		 12348}
12349
58efb6c0 12350void
4a5329c6 12351print_arm_disassembler_options (FILE *stream)
58efb6c0 12352{
65b48a81 12353 unsigned int i, max_len = 0;
58efb6c0
NC		 12354 fprintf (stream, _("\n\
12355The following ARM specific disassembler options are supported for use with\n\
12356the -M switch:\n"));
b34976b6 12357
65b48a81
PB		 12358 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12359 {
12360 unsigned int len = strlen (regnames[i].name);
12361 if (max_len < len)
12362 max_len = len;
12363 }
58efb6c0 12364
65b48a81
PB		 12365 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12366 fprintf (stream, " %s%*c %s\n",
12367 regnames[i].name,
12368 (int)(max_len - strlen (regnames[i].name)), ' ',
12369 _(regnames[i].description));
252b5132 12370}
GDB Binutils - Deliverables
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