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Arm: Fix Arm disassembler mapping symbol search.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
2d5d5a8f 35#include "bfd.h"
252b5132
RH		 36#include "elf-bfd.h"
37#include "elf/internal.h"
38#include "elf/arm.h"
e49d43ff 39#include "mach-o.h"
252b5132 40
6b5d3a4d 41/* FIXME: Belongs in global header. */
01c7f630 42#ifndef strneq
58efb6c0
NC		 43#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44#endif
45
1fbaefec
PB		 46/* Cached mapping symbol state. */
47enum map_type
48{
49 MAP_ARM,
50 MAP_THUMB,
51 MAP_DATA
52};
53
b0e28b39
DJ		 54struct arm_private_data
55{
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features;
58
1fbaefec
PB		 59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type;
61
62 /* Tracking symbol table information */
63 int last_mapping_sym;
796d6298
TC		 64
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset;
1fbaefec 67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 144#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
145#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
16a1fa25
TP		 411 /* ARMv8-M Mainline Security Extensions instructions. */
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
415 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
416
fe56b6ce 417 /* Register load/store. */
823d2571
TG		 418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
433 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
449 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
450
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
457 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
458 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 459
fe56b6ce 460 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
488 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 489 /* Half-precision conversion instructions. */
823d2571
TG		 490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
493 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
497 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 498
fe56b6ce 499 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
40c7d507
RR		 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
509 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823d2571
TG		 510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
40c7d507
RR		 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
523 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
823d2571
TG		 524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
535 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
537 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
549 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
553 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
569 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
571 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
575 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
577 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
579 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
581 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
583 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
585 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
587 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
589 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
591 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 593 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 595 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
599 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
601 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
605 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
609 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
613 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
617 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
621 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
625 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
627 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
629 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
633 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
635 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
636 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
637 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 638
639 /* Cirrus coprocessor instructions. */
823d2571
TG		 640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
800 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
801 0x0e000600, 0x0ff00f10,
802 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
803 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
804 0x0e100600, 0x0ff00f10,
805 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
806 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
807 0x0e200600, 0x0ff00f10,
808 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
809 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
810 0x0e300600, 0x0ff00f10,
811 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 812
62f3b8c8 813 /* VFP Fused multiply add instructions. */
823d2571
TG		 814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
829 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 830
33399f07 831 /* FP v5. */
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 841 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 843 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
851 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 853 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 854 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 855 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 856
05413229 857 /* Generic coprocessor instructions. */
823d2571
TG		 858 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
860 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
862 0x0c500000, 0x0ff00000,
863 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0e000000, 0x0f000010,
866 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
868 0x0e10f010, 0x0f10f010,
869 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
871 0x0e100010, 0x0f100010,
872 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
874 0x0e000010, 0x0f100010,
875 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
877 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
879 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 880
05413229 881 /* V6 coprocessor instructions. */
823d2571
TG		 882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
883 0xfc500000, 0xfff00000,
884 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
886 0xfc400000, 0xfff00000,
887 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 888
c28eeff2
SN		 889 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
901 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 905 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 907 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 908 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 909 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 910
c604a79a
JW		 911 /* Dot Product instructions in the space of coprocessor 13. */
912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
913 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
915 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
916
dec41383
JW		 917 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
919 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
921 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
923 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
925 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
927 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
929 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
931 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
933 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
934
05413229 935 /* V5 coprocessor instructions. */
823d2571
TG		 936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
937 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
939 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
941 0xfe000000, 0xff000010,
942 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
944 0xfe000010, 0xff100010,
945 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
947 0xfe100010, 0xff100010,
948 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
949
b0c11777
RL		 950 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
951 cp_num: bit <11:8> == 0b1001.
952 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1023
49e8a725
SN		 1024 /* ARMv8.3 javascript conversion instruction. */
1025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1027
823d2571 1028 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1029};
1030
16980d0b
JB		 1031/* Neon opcode table: This does not encode the top byte -- that is
1032 checked by the print_insn_neon routine, as it depends on whether we are
1033 doing thumb32 or arm32 disassembly. */
1034
1035/* print_insn_neon recognizes the following format control codes:
1036
1037 %% %
1038
c22aaad1 1039 %c print condition code
e2efe87d
MGD		 1040 %u print condition code (unconditional in ARM mode,
1041 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1042 %A print v{st,ld}[1234] operands
1043 %B print v{st,ld}[1234] any one operands
1044 %C print v{st,ld}[1234] single->all operands
1045 %D print scalar
1046 %E print vmov, vmvn, vorr, vbic encoded constant
1047 %F print vtbl,vtbx register list
1048
1049 %<bitfield>r print as an ARM register
1050 %<bitfield>d print the bitfield in decimal
1051 %<bitfield>e print the 2^N - bitfield in decimal
1052 %<bitfield>D print as a NEON D register
1053 %<bitfield>Q print as a NEON Q register
1054 %<bitfield>R print as a NEON D or Q register
1055 %<bitfield>Sn print byte scaled width limited by n
1056 %<bitfield>Tn print short scaled width limited by n
1057 %<bitfield>Un print long scaled width limited by n
43e65147 1058
16980d0b
JB		 1059 %<bitfield>'c print specified char iff bitfield is all ones
1060 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1061 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1062
1063static const struct opcode32 neon_opcodes[] =
1064{
fe56b6ce 1065 /* Extract. */
823d2571
TG		 1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067 0xf2b00840, 0xffb00850,
1068 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1070 0xf2b00000, 0xffb00810,
1071 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1072
fe56b6ce 1073 /* Move data element to all lanes. */
823d2571
TG		 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1080
fe56b6ce 1081 /* Table lookup. */
823d2571
TG		 1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1086
8e79c3df 1087 /* Half-precision conversions. */
823d2571
TG		 1088 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1090 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1091 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1092
1093 /* NEON fused multiply add instructions. */
823d2571 1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1095 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1099 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1102
fe56b6ce 1103 /* Two registers, miscellaneous. */
823d2571
TG		 1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1105 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1109 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1110 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1112 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1116 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1118 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1125 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf3b20300, 0xffb30fd0,
1148 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1152 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1196 0xf3bb0600, 0xffbf0e10,
823d2571 1197 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199 0xf3b70600, 0xffbf0e10,
1200 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1201
fe56b6ce 1202 /* Three registers of the same length. */
823d2571
TG		 1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1216 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1218 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1222 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1242 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1246 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1250 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1254 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1258 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1262 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1266 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1270 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1274 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1278 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1282 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1286 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1290 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1294 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1298 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1302 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1306 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1310 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000b00, 0xff800f10,
1321 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000b10, 0xff800f10,
1324 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf3000b00, 0xff800f10,
1333 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2000000, 0xfe800f10,
1336 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2000010, 0xfe800f10,
1339 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2000100, 0xfe800f10,
1342 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000200, 0xfe800f10,
1345 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2000210, 0xfe800f10,
1348 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2000300, 0xfe800f10,
1351 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2000310, 0xfe800f10,
1354 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf2000400, 0xfe800f10,
1357 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2000410, 0xfe800f10,
1360 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2000500, 0xfe800f10,
1363 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2000510, 0xfe800f10,
1366 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2000600, 0xfe800f10,
1369 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2000610, 0xfe800f10,
1372 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2000700, 0xfe800f10,
1375 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2000710, 0xfe800f10,
1378 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2000910, 0xfe800f10,
1381 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2000a00, 0xfe800f10,
1384 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2000a10, 0xfe800f10,
1387 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1389 0xf3000b10, 0xff800f10,
1390 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1392 0xf3000c10, 0xff800f10,
1393 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1394
fe56b6ce 1395 /* One register and an immediate value. */
823d2571
TG		 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1422
fe56b6ce 1423 /* Two registers and a shift amount. */
823d2571
TG		 1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2880950, 0xfeb80fd0,
1436 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2900950, 0xfeb00fd0,
1459 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2a00950, 0xfea00fd0,
1504 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2a00e10, 0xfea00e90,
1543 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf2a00c10, 0xfea00e90,
1546 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1547
fe56b6ce 1548 /* Three registers of different lengths. */
823d2571
TG		 1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800400, 0xff800f50,
1555 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2800600, 0xff800f50,
1558 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800900, 0xff800f50,
1561 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2800b00, 0xff800f50,
1564 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800d00, 0xff800f50,
1567 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3800400, 0xff800f50,
1570 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf3800600, 0xff800f50,
1573 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2800000, 0xfe800f50,
1576 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2800100, 0xfe800f50,
1579 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2800200, 0xfe800f50,
1582 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800300, 0xfe800f50,
1585 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2800500, 0xfe800f50,
1588 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800700, 0xfe800f50,
1591 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2800800, 0xfe800f50,
1594 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2800a00, 0xfe800f50,
1597 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800c00, 0xfe800f50,
1600 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1601
fe56b6ce 1602 /* Two registers and a scalar. */
823d2571
TG		 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1606 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1607 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1608 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1614 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1615 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1622 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1623 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1634 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1635 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1636 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1640 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1641 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1642 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1646 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1647 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800240, 0xfe800f50,
1655 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf2800640, 0xfe800f50,
1658 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2800a40, 0xfe800f50,
1661 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1663 0xf2800e40, 0xff800f50,
1664 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1666 0xf2800f40, 0xff800f50,
1667 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1669 0xf3800e40, 0xff800f50,
1670 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1672 0xf3800f40, 0xff800f50,
1673 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1674 },
16980d0b 1675
fe56b6ce 1676 /* Element and structure load/store. */
823d2571
TG		 1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1715
1716 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1717};
1718
8f06b2d8
PB		 1719/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1720 ordered: they must be searched linearly from the top to obtain a correct
1721 match. */
1722
1723/* print_insn_arm recognizes the following format control codes:
1724
1725 %% %
1726
1727 %a print address for ldr/str instruction
1728 %s print address for ldr/str halfword/signextend instruction
c1e26897 1729 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1730 %b print branch destination
1731 %c print condition code (always bits 28-31)
1732 %m print register mask for ldm/stm instruction
1733 %o print operand2 (immediate or register + shift)
1734 %p print 'p' iff bits 12-15 are 15
1735 %t print 't' iff bit 21 set and bit 24 clear
1736 %B print arm BLX(1) destination
1737 %C print the PSR sub type.
62b3e311
PB		 1738 %U print barrier type.
1739 %P print address for pli instruction.
8f06b2d8
PB		 1740
1741 %<bitfield>r print as an ARM register
9eb6c0f1 1742 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1743 %<bitfield>R as %r but r15 is UNPREDICTABLE
1744 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1745 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1746 %<bitfield>d print the bitfield in decimal
43e65147 1747 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1748 %<bitfield>x print the bitfield in hex
1749 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1750
16980d0b
JB		 1751 %<bitfield>'c print specified char iff bitfield is all ones
1752 %<bitfield>`c print specified char iff bitfield is all zeroes
1753 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1754
8f06b2d8
PB		 1755 %e print arm SMI operand (bits 0..7,8..19).
1756 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1757 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1758 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1759
8f06b2d8
PB		 1760static const struct opcode32 arm_opcodes[] =
1761{
1762 /* ARM instructions. */
823d2571
TG		 1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1766 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1767
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1769 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1773 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1775 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1777 0x00800090, 0x0fa000f0,
1778 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1780 0x00a00090, 0x0fa000f0,
1781 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1782
105bde57 1783 /* V8.2 RAS extension instructions. */
4d1464f2 1784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1785 0xe320f010, 0xffffffff, "esb"},
1786
53c4b28b 1787 /* V8 instructions. */
823d2571
TG		 1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 1790 /* Defined in V8 but is in NOP space so available to all arch. */
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 1792 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1794 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1795 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1796 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1798 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1800 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1801 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1802 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1803 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1804 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1805 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1806 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1807 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1808 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1809 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1810 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1811 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1812 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1813 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1814 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1815 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1816 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1817 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1818 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1820 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1821 /* CRC32 instructions. */
823d2571
TG		 1822 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1823 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1824 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1825 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1826 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1827 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1828 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1829 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1830 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1831 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1832 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1833 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1834
ddfded2f
MW		 1835 /* Privileged Access Never extension instructions. */
1836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1837 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1838
90ec0d68 1839 /* Virtualization Extension instructions. */
823d2571
TG		 1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1842
eea54501 1843 /* Integer Divide Extension instructions. */
823d2571
TG		 1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1845 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1847 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1848
60e5ef9f 1849 /* MP Extension instructions. */
823d2571 1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1851
c597cc3d
SD		 1852 /* Speculation Barriers. */
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1856
62b3e311 1857 /* V7 instructions. */
823d2571
TG		 1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1866 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1867
c19d1205 1868 /* ARM V6T2 instructions. */
823d2571
TG		 1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1870 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1872 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1874 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1876 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1877
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1879 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1881 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1882
ff8646ee 1883 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1884 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1885 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1886 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1888 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1890 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1891
f4c65163 1892 /* ARM Security extension instructions. */
823d2571
TG		 1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1894 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1895
8f06b2d8 1896 /* ARM V6K instructions. */
823d2571
TG		 1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898 0xf57ff01f, 0xffffffff, "clrex"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1904 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1906 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1908 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1910 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1911
7fadb25d
SD		 1912 /* ARMv8.5-A instructions. */
1913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1914
8f06b2d8 1915 /* ARM V6K NOP hints. */
823d2571
TG		 1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917 0x0320f001, 0x0fffffff, "yield%c"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1919 0x0320f002, 0x0fffffff, "wfe%c"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1921 0x0320f003, 0x0fffffff, "wfi%c"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1923 0x0320f004, 0x0fffffff, "sev%c"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1925 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1926
fe56b6ce 1927 /* ARM V6 instructions. */
823d2571
TG		 1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2172
8f06b2d8 2173 /* V5J instruction. */
823d2571
TG		 2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2175 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2176
8f06b2d8 2177 /* V5 Instructions. */
823d2571
TG		 2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2179 0xe1200070, 0xfff000f0,
2180 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2182 0xfa000000, 0xfe000000, "blx\t%B"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2184 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2186 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2187
2188 /* V5E "El Segundo" Instructions. */
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2190 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2192 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2194 0xf450f000, 0xfc70f000, "pld\t%a"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2198 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2203
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2205 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2207 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2208
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2212 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2214 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2216 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2217
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2221 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2223 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2226
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2231
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2233 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2235 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2237 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2239 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2240
8f06b2d8 2241 /* ARM Instructions. */
823d2571
TG		 2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2244
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2257
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2266
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2275
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2282
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2289
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2296
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2303
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2310
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2317
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2324
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2331
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2333 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2335 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2337 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2338
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2345
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2347 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2349 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2351 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2352
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2359
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2366
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2373
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2388
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2395
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2402
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2407
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2410
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2415
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x092d0000, 0x0fff0000, "push%c\t%m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2454
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2478 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2493
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2497 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2498
2499 /* The rest. */
4ab90a7a
AV		 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2501 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2503 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2504 {ARM_FEATURE_CORE_LOW (0),
2505 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2506};
2507
2508/* print_insn_thumb16 recognizes the following format control codes:
2509
2510 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2511 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2512 %<bitfield>I print bitfield as a signed decimal
2513 (top bit of range being the sign bit)
2514 %N print Thumb register mask (with LR)
2515 %O print Thumb register mask (with PC)
2516 %M print Thumb register mask
2517 %b print CZB's 6-bit unsigned branch destination
2518 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2519 %c print the condition code
2520 %C print the condition code, or "s" if not conditional
2521 %x print warning if conditional an not at end of IT block"
2522 %X print "\t; unpredictable <IT:code>" if conditional
2523 %I print IT instruction suffix and operands
4547cb56 2524 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2525 %<bitfield>r print bitfield as an ARM register
2526 %<bitfield>d print bitfield as a decimal
2527 %<bitfield>H print (bitfield * 2) as a decimal
2528 %<bitfield>W print (bitfield * 4) as a decimal
2529 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2530 %<bitfield>B print Thumb branch destination (signed displacement)
2531 %<bitfield>c print bitfield as a condition code
2532 %<bitnum>'c print specified char iff bit is one
2533 %<bitnum>?ab print a if bit is one else print b. */
2534
2535static const struct opcode16 thumb_opcodes[] =
2536{
2537 /* Thumb instructions. */
2538
16a1fa25
TP		 2539 /* ARMv8-M Security Extensions instructions. */
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2542
53c4b28b 2543 /* ARM V8 instructions. */
823d2571
TG		 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2547
8f06b2d8 2548 /* ARM V6K no-argument instructions. */
823d2571
TG		 2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2555
2556 /* ARM V6T2 instructions. */
ff8646ee
TP		 2557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2558 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2560 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2562
2563 /* ARM V6. */
823d2571
TG		 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2575
2576 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2578 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2579 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2581 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2582 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2584 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2585 /* Format 4. */
823d2571
TG		 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2602 /* format 13 */
823d2571
TG		 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2605 /* format 5 */
823d2571
TG		 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2610 /* format 14 */
823d2571
TG		 2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2613 /* format 2 */
823d2571
TG		 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2622 /* format 8 */
823d2571
TG		 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2626 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2629 /* format 7 */
823d2571
TG		 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2631 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2633 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2634 /* format 1 */
823d2571
TG		 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2640 /* format 3 */
823d2571
TG		 2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2645 /* format 6 */
823d2571
TG		 2646 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648 0x4800, 0xF800,
2649 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2650 /* format 9 */
823d2571
TG		 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2656 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2659 /* format 10 */
823d2571
TG		 2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2664 /* format 11 */
823d2571
TG		 2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2666 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2668 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2669 /* format 12 */
823d2571
TG		 2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2671 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2673 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2674 /* format 15 */
823d2571
TG		 2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2677 /* format 17 */
823d2571 2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2679 /* format 16 */
823d2571
TG		 2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2683 /* format 18 */
823d2571 2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2685
2686 /* The E800 .. FFFF range is unconditionally redirected to the
2687 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2688 are processed via that table. Thus, we can never encounter a
2689 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2691 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2692};
2693
2694/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2695 We adopt the convention that hw1 is the high 16 bits of .value and
2696 .mask, hw2 the low 16 bits.
2697
2698 print_insn_thumb32 recognizes the following format control codes:
2699
2700 %% %
2701
2702 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2703 %M print a modified 12-bit immediate (same location)
2704 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2705 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2706 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2707 %S print a possibly-shifted Rm
2708
32a94698 2709 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2710 %a print the address of a plain load/store
2711 %w print the width and signedness of a core load/store
2712 %m print register mask for ldm/stm
2713
2714 %E print the lsb and width fields of a bfc/bfi instruction
2715 %F print the lsb and width fields of a sbfx/ubfx instruction
2716 %b print a conditional branch offset
2717 %B print an unconditional branch offset
2718 %s print the shift field of an SSAT instruction
2719 %R print the rotation field of an SXT instruction
62b3e311
PB		 2720 %U print barrier type.
2721 %P print address for pli instruction.
c22aaad1
PB		 2722 %c print the condition code
2723 %x print warning if conditional an not at end of IT block"
2724 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2725
2726 %<bitfield>d print bitfield in decimal
f0fba320 2727 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2728 %<bitfield>W print bitfield*4 in decimal
2729 %<bitfield>r print bitfield as an ARM register
dd5181d5 2730 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
8f06b2d8
PB		 2731 %<bitfield>c print bitfield as a condition code
2732
16980d0b
JB		 2733 %<bitfield>'c print specified char iff bitfield is all ones
2734 %<bitfield>`c print specified char iff bitfield is all zeroes
2735 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2736
2737 With one exception at the bottom (done because BL and BLX(1) need
2738 to come dead last), this table was machine-sorted first in
2739 decreasing order of number of bits set in the mask, then in
2740 increasing numeric order of mask, then in increasing numeric order
2741 of opcode. This order is not the clearest for a human reader, but
2742 is guaranteed never to catch a special-case bit pattern with a more
2743 general mask, which is important, because this instruction encoding
2744 makes heavy use of special-case bit patterns. */
2745static const struct opcode32 thumb32_opcodes[] =
2746{
16a1fa25
TP		 2747 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2750 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2752 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2754 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2756 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2757
105bde57 2758 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2760 0xf3af8010, 0xffffffff, "esb"},
2761
53c4b28b 2762 /* V8 instructions. */
823d2571
TG		 2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2764 0xf3af8005, 0xffffffff, "sevl%c.w"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2766 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2768 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2770 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2772 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2774 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2776 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2778 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2780 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2782 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2784 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2786 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2788 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2790 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2792 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2794 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2795
dd5181d5 2796 /* CRC32 instructions. */
823d2571 2797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2798 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2800 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2802 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2804 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2806 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2808 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2809
c597cc3d
SD		 2810 /* Speculation Barriers. */
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2814
62b3e311 2815 /* V7 instructions. */
823d2571
TG		 2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2824 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2826 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2827
90ec0d68 2828 /* Virtualization Extension instructions. */
823d2571 2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2830 /* We skip ERET as that is SUBS pc, lr, #0. */
2831
60e5ef9f 2832 /* MP Extension instructions. */
823d2571 2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2834
f4c65163 2835 /* Security extension instructions. */
823d2571 2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2837
7fadb25d
SD		 2838 /* ARMv8.5-A instructions. */
2839 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2840
8f06b2d8 2841 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2850
ff8646ee 2851 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2852 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2879 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2880 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2882 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2900 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3008 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3010 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3076 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0xf810f000, 0xff70f000, "pld%c\t%a"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xfb100000, 0xfff000c0,
3109 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xfbc00080, 0xfff000c0,
3112 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3118 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3124 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3128 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3148 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3149 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3150 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3152 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3154 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3158 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3160 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3164 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3176 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3178 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3180 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3182 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3184 0xe9400000, 0xff500000,
3185 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187 0xe9500000, 0xff500000,
3188 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3190 0xe8600000, 0xff700000,
3191 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193 0xe8700000, 0xff700000,
3194 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3196 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3198 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3199
3200 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3202 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3204 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3206 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3208 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3209
8f06b2d8 3210 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3212 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3214 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3215
3216 /* Fallback. */
823d2571
TG		 3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3218 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3219 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3220};
ff4a8d2b 3221
8f06b2d8
PB		 3222static const char *const arm_conditional[] =
3223{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3224 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3225
3226static const char *const arm_fp_const[] =
3227{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3228
3229static const char *const arm_shift[] =
3230{"lsl", "lsr", "asr", "ror"};
3231
3232typedef struct
3233{
3234 const char *name;
3235 const char *description;
3236 const char *reg_names[16];
3237}
3238arm_regname;
3239
3240static const arm_regname regnames[] =
3241{
65b48a81 3242 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3243 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3244 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3245 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3246 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3247 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3248 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3249 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3250 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3251 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3252 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3253 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3254 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3255 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3256};
3257
3258static const char *const iwmmxt_wwnames[] =
3259{"b", "h", "w", "d"};
3260
3261static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3262{"b", "bus", "bc", "bss",
3263 "h", "hus", "hc", "hss",
3264 "w", "wus", "wc", "wss",
3265 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3266};
3267
3268static const char *const iwmmxt_regnames[] =
3269{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3270 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3271};
3272
3273static const char *const iwmmxt_cregnames[] =
3274{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3275 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3276};
3277
3278/* Default to GCC register name set. */
3279static unsigned int regname_selected = 1;
3280
65b48a81 3281#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3282#define arm_regnames regnames[regname_selected].reg_names
3283
3284static bfd_boolean force_thumb = FALSE;
3285
c22aaad1
PB		 3286/* Current IT instruction state. This contains the same state as the IT
3287 bits in the CPSR. */
3288static unsigned int ifthen_state;
3289/* IT state for the next instruction. */
3290static unsigned int ifthen_next_state;
3291/* The address of the insn for which the IT state is valid. */
3292static bfd_vma ifthen_address;
3293#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3294/* Indicates that the current Conditional state is unconditional or outside
3295 an IT block. */
3296#define COND_UNCOND 16
c22aaad1 3297
8f06b2d8
PB		 3298\f
3299/* Functions. */
8f06b2d8 3300
16980d0b
JB		 3301/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3302 Returns pointer to following character of the format string and
3303 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3304 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3305
3306static const char *
fe56b6ce
NC		 3307arm_decode_bitfield (const char *ptr,
3308 unsigned long insn,
3309 unsigned long *valuep,
3310 int *widthp)
16980d0b
JB		 3311{
3312 unsigned long value = 0;
3313 int width = 0;
43e65147
L		 3314
3315 do
16980d0b
JB		 3316 {
3317 int start, end;
3318 int bits;
3319
3320 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3321 start = start * 10 + *ptr - '0';
3322 if (*ptr == '-')
3323 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3324 end = end * 10 + *ptr - '0';
3325 else
3326 end = start;
3327 bits = end - start;
3328 if (bits < 0)
3329 abort ();
3330 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3331 width += bits + 1;
3332 }
3333 while (*ptr++ == ',');
3334 *valuep = value;
3335 if (widthp)
3336 *widthp = width;
3337 return ptr - 1;
3338}
3339
8f06b2d8 3340static void
37b37b2d 3341arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3342 bfd_boolean print_shift)
8f06b2d8
PB		 3343{
3344 func (stream, "%s", arm_regnames[given & 0xf]);
3345
3346 if ((given & 0xff0) != 0)
3347 {
3348 if ((given & 0x10) == 0)
3349 {
3350 int amount = (given & 0xf80) >> 7;
3351 int shift = (given & 0x60) >> 5;
3352
3353 if (amount == 0)
3354 {
3355 if (shift == 3)
3356 {
3357 func (stream, ", rrx");
3358 return;
3359 }
3360
3361 amount = 32;
3362 }
3363
37b37b2d
RE		 3364 if (print_shift)
3365 func (stream, ", %s #%d", arm_shift[shift], amount);
3366 else
3367 func (stream, ", #%d", amount);
8f06b2d8 3368 }
74bdfecf 3369 else if ((given & 0x80) == 0x80)
aefd8a40 3370 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3371 else if (print_shift)
8f06b2d8
PB		 3372 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3373 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3374 else
3375 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3376 }
3377}
3378
c1e26897
NC		 3379#define W_BIT 21
3380#define I_BIT 22
3381#define U_BIT 23
3382#define P_BIT 24
3383
3384#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3385#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3386#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3387#define PRE_BIT_SET (given & (1 << P_BIT))
3388
8f06b2d8
PB		 3389/* Print one coprocessor instruction on INFO->STREAM.
3390 Return TRUE if the instuction matched, FALSE if this is not a
3391 recognised coprocessor instruction. */
3392
3393static bfd_boolean
fe56b6ce
NC		 3394print_insn_coprocessor (bfd_vma pc,
3395 struct disassemble_info *info,
3396 long given,
8f06b2d8
PB		 3397 bfd_boolean thumb)
3398{
3399 const struct opcode32 *insn;
3400 void *stream = info->stream;
3401 fprintf_ftype func = info->fprintf_func;
3402 unsigned long mask;
2edcd244 3403 unsigned long value = 0;
c22aaad1 3404 int cond;
8afc7bea 3405 int cp_num;
823d2571
TG		 3406 struct arm_private_data *private_data = info->private_data;
3407 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3408
5b616bef 3409 allowed_arches = private_data->features;
8f06b2d8
PB		 3410
3411 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3412 {
ff4a8d2b
NC		 3413 unsigned long u_reg = 16;
3414 bfd_boolean is_unpredictable = FALSE;
05413229 3415 signed long value_in_comment = 0;
0313a2b8
NC		 3416 const char *c;
3417
823d2571 3418 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3419 switch (insn->value)
3420 {
3421 case SENTINEL_IWMMXT_START:
3422 if (info->mach != bfd_mach_arm_XScale
3423 && info->mach != bfd_mach_arm_iWMMXt
3424 && info->mach != bfd_mach_arm_iWMMXt2)
3425 do
3426 insn++;
823d2571
TG		 3427 while ((! ARM_FEATURE_ZERO (insn->arch))
3428 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3429 continue;
3430
3431 case SENTINEL_IWMMXT_END:
3432 continue;
3433
3434 case SENTINEL_GENERIC_START:
5b616bef 3435 allowed_arches = private_data->features;
05413229
NC		 3436 continue;
3437
3438 default:
3439 abort ();
3440 }
8f06b2d8
PB		 3441
3442 mask = insn->mask;
3443 value = insn->value;
8afc7bea
RL		 3444 cp_num = (given >> 8) & 0xf;
3445
8f06b2d8
PB		 3446 if (thumb)
3447 {
3448 /* The high 4 bits are 0xe for Arm conditional instructions, and
3449 0xe for arm unconditional instructions. The rest of the
3450 encoding is the same. */
3451 mask |= 0xf0000000;
3452 value |= 0xe0000000;
c22aaad1
PB		 3453 if (ifthen_state)
3454 cond = IFTHEN_COND;
3455 else
e2efe87d 3456 cond = COND_UNCOND;
8f06b2d8
PB		 3457 }
3458 else
3459 {
3460 /* Only match unconditional instuctions against unconditional
3461 patterns. */
3462 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3463 {
3464 mask |= 0xf0000000;
e2efe87d 3465 cond = COND_UNCOND;
c22aaad1
PB		 3466 }
3467 else
3468 {
3469 cond = (given >> 28) & 0xf;
3470 if (cond == 0xe)
e2efe87d 3471 cond = COND_UNCOND;
c22aaad1 3472 }
8f06b2d8 3473 }
823d2571 3474
0313a2b8
NC		 3475 if ((given & mask) != value)
3476 continue;
8f06b2d8 3477
823d2571 3478 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3479 continue;
3480
8afc7bea
RL		 3481 if (insn->value == 0xfe000010 /* mcr2 */
3482 || insn->value == 0xfe100010 /* mrc2 */
3483 || insn->value == 0xfc100000 /* ldc2 */
3484 || insn->value == 0xfc000000) /* stc2 */
3485 {
b0c11777 3486 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3487 is_unpredictable = TRUE;
3488 }
3489 else if (insn->value == 0x0e000000 /* cdp */
3490 || insn->value == 0xfe000000 /* cdp2 */
3491 || insn->value == 0x0e000010 /* mcr */
3492 || insn->value == 0x0e100010 /* mrc */
3493 || insn->value == 0x0c100000 /* ldc */
3494 || insn->value == 0x0c000000) /* stc */
3495 {
3496 /* Floating-point instructions. */
b0c11777 3497 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3498 continue;
3499 }
3500
0313a2b8
NC		 3501 for (c = insn->assembler; *c; c++)
3502 {
3503 if (*c == '%')
8f06b2d8 3504 {
0313a2b8 3505 switch (*++c)
8f06b2d8 3506 {
0313a2b8
NC		 3507 case '%':
3508 func (stream, "%%");
3509 break;
3510
3511 case 'A':
05413229 3512 {
79862e45 3513 int rn = (given >> 16) & 0xf;
b0c11777 3514 bfd_vma offset = given & 0xff;
0313a2b8 3515
05413229 3516 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3517
79862e45
DJ		 3518 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3519 {
3520 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3521 if (cp_num == 9)
3522 /* vldr.16/vstr.16 will shift the address
3523 left by 1 bit only. */
3524 offset = offset * 2;
3525 else
3526 offset = offset * 4;
3527
79862e45
DJ		 3528 if (NEGATIVE_BIT_SET)
3529 offset = - offset;
3530 if (rn != 15)
3531 value_in_comment = offset;
3532 }
3533
c1e26897 3534 if (PRE_BIT_SET)
05413229
NC		 3535 {
3536 if (offset)
fe56b6ce 3537 func (stream, ", #%d]%s",
d908c8af 3538 (int) offset,
c1e26897 3539 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3540 else if (NEGATIVE_BIT_SET)
3541 func (stream, ", #-0]");
05413229
NC		 3542 else
3543 func (stream, "]");
3544 }
3545 else
3546 {
0313a2b8 3547 func (stream, "]");
8f06b2d8 3548
c1e26897 3549 if (WRITEBACK_BIT_SET)
05413229
NC		 3550 {
3551 if (offset)
d908c8af 3552 func (stream, ", #%d", (int) offset);
26d97720
NS		 3553 else if (NEGATIVE_BIT_SET)
3554 func (stream, ", #-0");
05413229
NC		 3555 }
3556 else
fe56b6ce 3557 {
26d97720
NS		 3558 func (stream, ", {%s%d}",
3559 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3560 (int) offset);
fe56b6ce
NC		 3561 value_in_comment = offset;
3562 }
05413229 3563 }
79862e45
DJ		 3564 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3565 {
3566 func (stream, "\t; ");
6844b2c2
MGD		 3567 /* For unaligned PCs, apply off-by-alignment
3568 correction. */
43e65147 3569 info->print_address_func (offset + pc
6844b2c2
MGD		 3570 + info->bytes_per_chunk * 2
3571 - (pc & 3),
3572 info);
79862e45 3573 }
05413229 3574 }
0313a2b8 3575 break;
8f06b2d8 3576
0313a2b8
NC		 3577 case 'B':
3578 {
3579 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3580 int offset = (given >> 1) & 0x3f;
3581
3582 if (offset == 1)
3583 func (stream, "{d%d}", regno);
3584 else if (regno + offset > 32)
3585 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3586 else
3587 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3588 }
3589 break;
8f06b2d8 3590
e2efe87d
MGD		 3591 case 'u':
3592 if (cond != COND_UNCOND)
3593 is_unpredictable = TRUE;
3594
3595 /* Fall through. */
0313a2b8 3596 case 'c':
b0c11777
RL		 3597 if (cond != COND_UNCOND && cp_num == 9)
3598 is_unpredictable = TRUE;
3599
0313a2b8
NC		 3600 func (stream, "%s", arm_conditional[cond]);
3601 break;
8f06b2d8 3602
0313a2b8
NC		 3603 case 'I':
3604 /* Print a Cirrus/DSP shift immediate. */
3605 /* Immediates are 7bit signed ints with bits 0..3 in
3606 bits 0..3 of opcode and bits 4..6 in bits 5..7
3607 of opcode. */
3608 {
3609 int imm;
8f06b2d8 3610
0313a2b8 3611 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3612
0313a2b8
NC		 3613 /* Is ``imm'' a negative number? */
3614 if (imm & 0x40)
24b4cf66 3615 imm -= 0x80;
8f06b2d8 3616
0313a2b8
NC		 3617 func (stream, "%d", imm);
3618 }
3619
3620 break;
8f06b2d8 3621
0313a2b8
NC		 3622 case 'F':
3623 switch (given & 0x00408000)
3624 {
3625 case 0:
3626 func (stream, "4");
3627 break;
3628 case 0x8000:
3629 func (stream, "1");
3630 break;
3631 case 0x00400000:
3632 func (stream, "2");
8f06b2d8 3633 break;
0313a2b8
NC		 3634 default:
3635 func (stream, "3");
3636 }
3637 break;
8f06b2d8 3638
0313a2b8
NC		 3639 case 'P':
3640 switch (given & 0x00080080)
3641 {
3642 case 0:
3643 func (stream, "s");
3644 break;
3645 case 0x80:
3646 func (stream, "d");
3647 break;
3648 case 0x00080000:
3649 func (stream, "e");
3650 break;
3651 default:
3652 func (stream, _("<illegal precision>"));
8f06b2d8 3653 break;
0313a2b8
NC		 3654 }
3655 break;
8f06b2d8 3656
0313a2b8
NC		 3657 case 'Q':
3658 switch (given & 0x00408000)
3659 {
3660 case 0:
3661 func (stream, "s");
8f06b2d8 3662 break;
0313a2b8
NC		 3663 case 0x8000:
3664 func (stream, "d");
8f06b2d8 3665 break;
0313a2b8
NC		 3666 case 0x00400000:
3667 func (stream, "e");
3668 break;
3669 default:
3670 func (stream, "p");
8f06b2d8 3671 break;
0313a2b8
NC		 3672 }
3673 break;
8f06b2d8 3674
0313a2b8
NC		 3675 case 'R':
3676 switch (given & 0x60)
3677 {
3678 case 0:
3679 break;
3680 case 0x20:
3681 func (stream, "p");
3682 break;
3683 case 0x40:
3684 func (stream, "m");
3685 break;
3686 default:
3687 func (stream, "z");
3688 break;
3689 }
3690 break;
16980d0b 3691
0313a2b8
NC		 3692 case '0': case '1': case '2': case '3': case '4':
3693 case '5': case '6': case '7': case '8': case '9':
3694 {
3695 int width;
8f06b2d8 3696
0313a2b8 3697 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3698
0313a2b8
NC		 3699 switch (*c)
3700 {
ff4a8d2b
NC		 3701 case 'R':
3702 if (value == 15)
3703 is_unpredictable = TRUE;
3704 /* Fall through. */
0313a2b8 3705 case 'r':
ff4a8d2b
NC		 3706 if (c[1] == 'u')
3707 {
3708 /* Eat the 'u' character. */
3709 ++ c;
3710
3711 if (u_reg == value)
3712 is_unpredictable = TRUE;
3713 u_reg = value;
3714 }
0313a2b8
NC		 3715 func (stream, "%s", arm_regnames[value]);
3716 break;
c28eeff2
SN		 3717 case 'V':
3718 if (given & (1 << 6))
3719 goto Q;
3720 /* FALLTHROUGH */
0313a2b8
NC		 3721 case 'D':
3722 func (stream, "d%ld", value);
3723 break;
3724 case 'Q':
c28eeff2 3725 Q:
0313a2b8
NC		 3726 if (value & 1)
3727 func (stream, "<illegal reg q%ld.5>", value >> 1);
3728 else
3729 func (stream, "q%ld", value >> 1);
3730 break;
3731 case 'd':
3732 func (stream, "%ld", value);
05413229 3733 value_in_comment = value;
0313a2b8 3734 break;
6f1c2142
AM		 3735 case 'E':
3736 {
3737 /* Converts immediate 8 bit back to float value. */
3738 unsigned floatVal = (value & 0x80) << 24
3739 | (value & 0x3F) << 19
3740 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3741
3742 /* Quarter float have a maximum value of 31.0.
3743 Get floating point value multiplied by 1e7.
3744 The maximum value stays in limit of a 32-bit int. */
3745 unsigned decVal =
3746 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3747 (16 + (value & 0xF));
3748
3749 if (!(decVal % 1000000))
3750 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3751 floatVal, value & 0x80 ? '-' : ' ',
3752 decVal / 10000000,
3753 decVal % 10000000 / 1000000);
3754 else if (!(decVal % 10000))
3755 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3756 floatVal, value & 0x80 ? '-' : ' ',
3757 decVal / 10000000,
3758 decVal % 10000000 / 10000);
3759 else
3760 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3761 floatVal, value & 0x80 ? '-' : ' ',
3762 decVal / 10000000, decVal % 10000000);
3763 break;
3764 }
0313a2b8
NC		 3765 case 'k':
3766 {
3767 int from = (given & (1 << 7)) ? 32 : 16;
3768 func (stream, "%ld", from - value);
3769 }
3770 break;
8f06b2d8 3771
0313a2b8
NC		 3772 case 'f':
3773 if (value > 7)
3774 func (stream, "#%s", arm_fp_const[value & 7]);
3775 else
3776 func (stream, "f%ld", value);
3777 break;
4146fd53 3778
0313a2b8
NC		 3779 case 'w':
3780 if (width == 2)
3781 func (stream, "%s", iwmmxt_wwnames[value]);
3782 else
3783 func (stream, "%s", iwmmxt_wwssnames[value]);
3784 break;
4146fd53 3785
0313a2b8
NC		 3786 case 'g':
3787 func (stream, "%s", iwmmxt_regnames[value]);
3788 break;
3789 case 'G':
3790 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3791 break;
8f06b2d8 3792
0313a2b8 3793 case 'x':
d1aaab3c 3794 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3795 break;
8f06b2d8 3796
33399f07
MGD		 3797 case 'c':
3798 switch (value)
3799 {
3800 case 0:
3801 func (stream, "eq");
3802 break;
3803
3804 case 1:
3805 func (stream, "vs");
3806 break;
3807
3808 case 2:
3809 func (stream, "ge");
3810 break;
3811
3812 case 3:
3813 func (stream, "gt");
3814 break;
3815
3816 default:
3817 func (stream, "??");
3818 break;
3819 }
3820 break;
3821
0313a2b8
NC		 3822 case '`':
3823 c++;
3824 if (value == 0)
3825 func (stream, "%c", *c);
3826 break;
3827 case '\'':
3828 c++;
3829 if (value == ((1ul << width) - 1))
3830 func (stream, "%c", *c);
3831 break;
3832 case '?':
fe56b6ce 3833 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3834 c += 1 << width;
3835 break;
3836 default:
3837 abort ();
3838 }
3839 break;
8f06b2d8 3840
0313a2b8
NC		 3841 case 'y':
3842 case 'z':
3843 {
3844 int single = *c++ == 'y';
3845 int regno;
3846
3847 switch (*c)
3848 {
3849 case '4': /* Sm pair */
3850 case '0': /* Sm, Dm */
3851 regno = given & 0x0000000f;
3852 if (single)
3853 {
3854 regno <<= 1;
3855 regno += (given >> 5) & 1;
16980d0b 3856 }
0313a2b8
NC		 3857 else
3858 regno += ((given >> 5) & 1) << 4;
3859 break;
8f06b2d8 3860
0313a2b8
NC		 3861 case '1': /* Sd, Dd */
3862 regno = (given >> 12) & 0x0000000f;
3863 if (single)
3864 {
3865 regno <<= 1;
3866 regno += (given >> 22) & 1;
3867 }
3868 else
3869 regno += ((given >> 22) & 1) << 4;
3870 break;
8f06b2d8 3871
0313a2b8
NC		 3872 case '2': /* Sn, Dn */
3873 regno = (given >> 16) & 0x0000000f;
3874 if (single)
8f06b2d8 3875 {
0313a2b8
NC		 3876 regno <<= 1;
3877 regno += (given >> 7) & 1;
8f06b2d8 3878 }
0313a2b8
NC		 3879 else
3880 regno += ((given >> 7) & 1) << 4;
3881 break;
7df76b80 3882
0313a2b8
NC		 3883 case '3': /* List */
3884 func (stream, "{");
3885 regno = (given >> 12) & 0x0000000f;
3886 if (single)
3887 {
3888 regno <<= 1;
3889 regno += (given >> 22) & 1;
3890 }
3891 else
3892 regno += ((given >> 22) & 1) << 4;
3893 break;
a7f8487e 3894
0313a2b8
NC		 3895 default:
3896 abort ();
8f06b2d8 3897 }
a7f8487e 3898
0313a2b8
NC		 3899 func (stream, "%c%d", single ? 's' : 'd', regno);
3900
3901 if (*c == '3')
8f06b2d8 3902 {
0313a2b8 3903 int count = given & 0xff;
a7f8487e 3904
0313a2b8
NC		 3905 if (single == 0)
3906 count >>= 1;
b34976b6 3907
0313a2b8 3908 if (--count)
8f06b2d8 3909 {
0313a2b8
NC		 3910 func (stream, "-%c%d",
3911 single ? 's' : 'd',
3912 regno + count);
8f06b2d8 3913 }
0313a2b8
NC		 3914
3915 func (stream, "}");
8f06b2d8 3916 }
0313a2b8
NC		 3917 else if (*c == '4')
3918 func (stream, ", %c%d", single ? 's' : 'd',
3919 regno + 1);
3920 }
3921 break;
3922
3923 case 'L':
3924 switch (given & 0x00400100)
3925 {
3926 case 0x00000000: func (stream, "b"); break;
3927 case 0x00400000: func (stream, "h"); break;
3928 case 0x00000100: func (stream, "w"); break;
3929 case 0x00400100: func (stream, "d"); break;
3930 default:
8f06b2d8 3931 break;
0313a2b8
NC		 3932 }
3933 break;
b34976b6 3934
0313a2b8
NC		 3935 case 'Z':
3936 {
0313a2b8
NC		 3937 /* given (20, 23) | given (0, 3) */
3938 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3939 func (stream, "%d", (int) value);
0313a2b8
NC		 3940 }
3941 break;
2d447fca 3942
0313a2b8
NC		 3943 case 'l':
3944 /* This is like the 'A' operator, except that if
3945 the width field "M" is zero, then the offset is
3946 *not* multiplied by four. */
3947 {
3948 int offset = given & 0xff;
3949 int multiplier = (given & 0x00000100) ? 4 : 1;
3950
3951 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3952
05413229
NC		 3953 if (multiplier > 1)
3954 {
3955 value_in_comment = offset * multiplier;
c1e26897 3956 if (NEGATIVE_BIT_SET)
05413229
NC		 3957 value_in_comment = - value_in_comment;
3958 }
3959
0313a2b8
NC		 3960 if (offset)
3961 {
c1e26897 3962 if (PRE_BIT_SET)
0313a2b8 3963 func (stream, ", #%s%d]%s",
c1e26897 3964 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3965 offset * multiplier,
c1e26897 3966 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3967 else
3968 func (stream, "], #%s%d",
c1e26897 3969 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3970 offset * multiplier);
2d447fca 3971 }
0313a2b8
NC		 3972 else
3973 func (stream, "]");
3974 }
3975 break;
3976
3977 case 'r':
3978 {
3979 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3980 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3981 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3982 const char *rm = arm_regnames [given & 0xf];
3983 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3984
0313a2b8 3985 switch (puw_bits)
2d447fca 3986 {
0313a2b8
NC		 3987 case 1:
3988 case 3:
3989 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3990 if (imm4)
3991 func (stream, ", lsl #%d", imm4);
3992 break;
3993
3994 case 4:
3995 case 5:
3996 case 6:
3997 case 7:
3998 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3999 if (imm4 > 0)
4000 func (stream, ", lsl #%d", imm4);
4001 func (stream, "]");
4002 if (puw_bits == 5 || puw_bits == 7)
4003 func (stream, "!");
4004 break;
4005
4006 default:
4007 func (stream, "INVALID");
2d447fca 4008 }
0313a2b8
NC		 4009 }
4010 break;
2d447fca 4011
0313a2b8
NC		 4012 case 'i':
4013 {
4014 long imm5;
4015 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4016 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 4017 }
0313a2b8
NC		 4018 break;
4019
4020 default:
4021 abort ();
4022 }
252b5132 4023 }
252b5132 4024 }
0313a2b8
NC		 4025 else
4026 func (stream, "%c", *c);
252b5132 4027 }
05413229
NC		 4028
4029 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4030 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4031
ff4a8d2b
NC		 4032 if (is_unpredictable)
4033 func (stream, UNPREDICTABLE_INSTRUCTION);
4034
0313a2b8 4035 return TRUE;
252b5132 4036 }
8f06b2d8 4037 return FALSE;
252b5132
RH		 4038}
4039
05413229
NC		 4040/* Decodes and prints ARM addressing modes. Returns the offset
4041 used in the address, if any, if it is worthwhile printing the
4042 offset as a hexadecimal value in a comment at the end of the
4043 line of disassembly. */
4044
4045static signed long
62b3e311
PB		 4046print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4047{
4048 void *stream = info->stream;
4049 fprintf_ftype func = info->fprintf_func;
f8b960bc 4050 bfd_vma offset = 0;
62b3e311
PB		 4051
4052 if (((given & 0x000f0000) == 0x000f0000)
4053 && ((given & 0x02000000) == 0))
4054 {
05413229 4055 offset = given & 0xfff;
62b3e311
PB		 4056
4057 func (stream, "[pc");
4058
c1e26897 4059 if (PRE_BIT_SET)
62b3e311 4060 {
26d97720
NS		 4061 /* Pre-indexed. Elide offset of positive zero when
4062 non-writeback. */
4063 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4064 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4065
4066 if (NEGATIVE_BIT_SET)
4067 offset = -offset;
62b3e311
PB		 4068
4069 offset += pc + 8;
4070
4071 /* Cope with the possibility of write-back
4072 being used. Probably a very dangerous thing
4073 for the programmer to do, but who are we to
4074 argue ? */
26d97720 4075 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4076 }
c1e26897 4077 else /* Post indexed. */
62b3e311 4078 {
d908c8af 4079 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4080
c1e26897 4081 /* Ie ignore the offset. */
62b3e311
PB		 4082 offset = pc + 8;
4083 }
4084
4085 func (stream, "\t; ");
4086 info->print_address_func (offset, info);
05413229 4087 offset = 0;
62b3e311
PB		 4088 }
4089 else
4090 {
4091 func (stream, "[%s",
4092 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4093
4094 if (PRE_BIT_SET)
62b3e311
PB		 4095 {
4096 if ((given & 0x02000000) == 0)
4097 {
26d97720 4098 /* Elide offset of positive zero when non-writeback. */
05413229 4099 offset = given & 0xfff;
26d97720 4100 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4101 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4102 }
4103 else
4104 {
26d97720 4105 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4106 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4107 }
4108
4109 func (stream, "]%s",
c1e26897 4110 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4111 }
4112 else
4113 {
4114 if ((given & 0x02000000) == 0)
4115 {
26d97720 4116 /* Always show offset. */
05413229 4117 offset = given & 0xfff;
26d97720 4118 func (stream, "], #%s%d",
d908c8af 4119 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4120 }
4121 else
4122 {
4123 func (stream, "], %s",
c1e26897 4124 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4125 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4126 }
4127 }
84919466
MR		 4128 if (NEGATIVE_BIT_SET)
4129 offset = -offset;
62b3e311 4130 }
05413229
NC		 4131
4132 return (signed long) offset;
62b3e311
PB		 4133}
4134
16980d0b
JB		 4135/* Print one neon instruction on INFO->STREAM.
4136 Return TRUE if the instuction matched, FALSE if this is not a
4137 recognised neon instruction. */
4138
4139static bfd_boolean
4140print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4141{
4142 const struct opcode32 *insn;
4143 void *stream = info->stream;
4144 fprintf_ftype func = info->fprintf_func;
4145
4146 if (thumb)
4147 {
4148 if ((given & 0xef000000) == 0xef000000)
4149 {
0313a2b8 4150 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4151 unsigned long bit28 = given & (1 << 28);
4152
4153 given &= 0x00ffffff;
4154 if (bit28)
4155 given |= 0xf3000000;
4156 else
4157 given |= 0xf2000000;
4158 }
4159 else if ((given & 0xff000000) == 0xf9000000)
4160 given ^= 0xf9000000 ^ 0xf4000000;
4161 else
4162 return FALSE;
4163 }
43e65147 4164
16980d0b
JB		 4165 for (insn = neon_opcodes; insn->assembler; insn++)
4166 {
4167 if ((given & insn->mask) == insn->value)
4168 {
05413229 4169 signed long value_in_comment = 0;
e2efe87d 4170 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4171 const char *c;
4172
4173 for (c = insn->assembler; *c; c++)
4174 {
4175 if (*c == '%')
4176 {
4177 switch (*++c)
4178 {
4179 case '%':
4180 func (stream, "%%");
4181 break;
4182
e2efe87d
MGD		 4183 case 'u':
4184 if (thumb && ifthen_state)
4185 is_unpredictable = TRUE;
4186
4187 /* Fall through. */
c22aaad1
PB		 4188 case 'c':
4189 if (thumb && ifthen_state)
4190 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4191 break;
4192
16980d0b
JB		 4193 case 'A':
4194 {
43e65147 4195 static const unsigned char enc[16] =
16980d0b
JB		 4196 {
4197 0x4, 0x14, /* st4 0,1 */
4198 0x4, /* st1 2 */
4199 0x4, /* st2 3 */
4200 0x3, /* st3 4 */
4201 0x13, /* st3 5 */
4202 0x3, /* st1 6 */
4203 0x1, /* st1 7 */
4204 0x2, /* st2 8 */
4205 0x12, /* st2 9 */
4206 0x2, /* st1 10 */
4207 0, 0, 0, 0, 0
4208 };
4209 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4210 int rn = ((given >> 16) & 0xf);
4211 int rm = ((given >> 0) & 0xf);
4212 int align = ((given >> 4) & 0x3);
4213 int type = ((given >> 8) & 0xf);
4214 int n = enc[type] & 0xf;
4215 int stride = (enc[type] >> 4) + 1;
4216 int ix;
43e65147 4217
16980d0b
JB		 4218 func (stream, "{");
4219 if (stride > 1)
4220 for (ix = 0; ix != n; ix++)
4221 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4222 else if (n == 1)
4223 func (stream, "d%d", rd);
4224 else
4225 func (stream, "d%d-d%d", rd, rd + n - 1);
4226 func (stream, "}, [%s", arm_regnames[rn]);
4227 if (align)
8e560766 4228 func (stream, " :%d", 32 << align);
16980d0b
JB		 4229 func (stream, "]");
4230 if (rm == 0xd)
4231 func (stream, "!");
4232 else if (rm != 0xf)
4233 func (stream, ", %s", arm_regnames[rm]);
4234 }
4235 break;
43e65147 4236
16980d0b
JB		 4237 case 'B':
4238 {
4239 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4240 int rn = ((given >> 16) & 0xf);
4241 int rm = ((given >> 0) & 0xf);
4242 int idx_align = ((given >> 4) & 0xf);
4243 int align = 0;
4244 int size = ((given >> 10) & 0x3);
4245 int idx = idx_align >> (size + 1);
4246 int length = ((given >> 8) & 3) + 1;
4247 int stride = 1;
4248 int i;
4249
4250 if (length > 1 && size > 0)
4251 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4252
16980d0b
JB		 4253 switch (length)
4254 {
4255 case 1:
4256 {
4257 int amask = (1 << size) - 1;
4258 if ((idx_align & (1 << size)) != 0)
4259 return FALSE;
4260 if (size > 0)
4261 {
4262 if ((idx_align & amask) == amask)
4263 align = 8 << size;
4264 else if ((idx_align & amask) != 0)
4265 return FALSE;
4266 }
4267 }
4268 break;
43e65147 4269
16980d0b
JB		 4270 case 2:
4271 if (size == 2 && (idx_align & 2) != 0)
4272 return FALSE;
4273 align = (idx_align & 1) ? 16 << size : 0;
4274 break;
43e65147 4275
16980d0b
JB		 4276 case 3:
4277 if ((size == 2 && (idx_align & 3) != 0)
4278 || (idx_align & 1) != 0)
4279 return FALSE;
4280 break;
43e65147 4281
16980d0b
JB		 4282 case 4:
4283 if (size == 2)
4284 {
4285 if ((idx_align & 3) == 3)
4286 return FALSE;
4287 align = (idx_align & 3) * 64;
4288 }
4289 else
4290 align = (idx_align & 1) ? 32 << size : 0;
4291 break;
43e65147 4292
16980d0b
JB		 4293 default:
4294 abort ();
4295 }
43e65147 4296
16980d0b
JB		 4297 func (stream, "{");
4298 for (i = 0; i < length; i++)
4299 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4300 rd + i * stride, idx);
4301 func (stream, "}, [%s", arm_regnames[rn]);
4302 if (align)
8e560766 4303 func (stream, " :%d", align);
16980d0b
JB		 4304 func (stream, "]");
4305 if (rm == 0xd)
4306 func (stream, "!");
4307 else if (rm != 0xf)
4308 func (stream, ", %s", arm_regnames[rm]);
4309 }
4310 break;
43e65147 4311
16980d0b
JB		 4312 case 'C':
4313 {
4314 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4315 int rn = ((given >> 16) & 0xf);
4316 int rm = ((given >> 0) & 0xf);
4317 int align = ((given >> 4) & 0x1);
4318 int size = ((given >> 6) & 0x3);
4319 int type = ((given >> 8) & 0x3);
4320 int n = type + 1;
4321 int stride = ((given >> 5) & 0x1);
4322 int ix;
43e65147 4323
16980d0b
JB		 4324 if (stride && (n == 1))
4325 n++;
4326 else
4327 stride++;
43e65147 4328
16980d0b
JB		 4329 func (stream, "{");
4330 if (stride > 1)
4331 for (ix = 0; ix != n; ix++)
4332 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4333 else if (n == 1)
4334 func (stream, "d%d[]", rd);
4335 else
4336 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4337 func (stream, "}, [%s", arm_regnames[rn]);
4338 if (align)
4339 {
91d6fa6a 4340 align = (8 * (type + 1)) << size;
16980d0b
JB		 4341 if (type == 3)
4342 align = (size > 1) ? align >> 1 : align;
4343 if (type == 2 || (type == 0 && !size))
8e560766 4344 func (stream, " :<bad align %d>", align);
16980d0b 4345 else
8e560766 4346 func (stream, " :%d", align);
16980d0b
JB		 4347 }
4348 func (stream, "]");
4349 if (rm == 0xd)
4350 func (stream, "!");
4351 else if (rm != 0xf)
4352 func (stream, ", %s", arm_regnames[rm]);
4353 }
4354 break;
43e65147 4355
16980d0b
JB		 4356 case 'D':
4357 {
4358 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4359 int size = (given >> 20) & 3;
4360 int reg = raw_reg & ((4 << size) - 1);
4361 int ix = raw_reg >> size >> 2;
43e65147 4362
16980d0b
JB		 4363 func (stream, "d%d[%d]", reg, ix);
4364 }
4365 break;
43e65147 4366
16980d0b 4367 case 'E':
fe56b6ce 4368 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4369 {
4370 int bits = 0;
4371 int cmode = (given >> 8) & 0xf;
4372 int op = (given >> 5) & 0x1;
4373 unsigned long value = 0, hival = 0;
4374 unsigned shift;
4375 int size = 0;
0dbde4cf 4376 int isfloat = 0;
43e65147 4377
16980d0b
JB		 4378 bits |= ((given >> 24) & 1) << 7;
4379 bits |= ((given >> 16) & 7) << 4;
4380 bits |= ((given >> 0) & 15) << 0;
43e65147 4381
16980d0b
JB		 4382 if (cmode < 8)
4383 {
4384 shift = (cmode >> 1) & 3;
fe56b6ce 4385 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4386 size = 32;
4387 }
4388 else if (cmode < 12)
4389 {
4390 shift = (cmode >> 1) & 1;
fe56b6ce 4391 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4392 size = 16;
4393 }
4394 else if (cmode < 14)
4395 {
4396 shift = (cmode & 1) + 1;
fe56b6ce 4397 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4398 value |= (1ul << (8 * shift)) - 1;
4399 size = 32;
4400 }
4401 else if (cmode == 14)
4402 {
4403 if (op)
4404 {
fe56b6ce 4405 /* Bit replication into bytes. */
16980d0b
JB		 4406 int ix;
4407 unsigned long mask;
43e65147 4408
16980d0b
JB		 4409 value = 0;
4410 hival = 0;
4411 for (ix = 7; ix >= 0; ix--)
4412 {
4413 mask = ((bits >> ix) & 1) ? 0xff : 0;
4414 if (ix <= 3)
4415 value = (value << 8) | mask;
4416 else
4417 hival = (hival << 8) | mask;
4418 }
4419 size = 64;
4420 }
4421 else
4422 {
fe56b6ce
NC		 4423 /* Byte replication. */
4424 value = (unsigned long) bits;
16980d0b
JB		 4425 size = 8;
4426 }
4427 }
4428 else if (!op)
4429 {
fe56b6ce 4430 /* Floating point encoding. */
16980d0b 4431 int tmp;
43e65147 4432
fe56b6ce
NC		 4433 value = (unsigned long) (bits & 0x7f) << 19;
4434 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4435 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4436 value |= (unsigned long) tmp << 24;
16980d0b 4437 size = 32;
0dbde4cf 4438 isfloat = 1;
16980d0b
JB		 4439 }
4440 else
4441 {
4442 func (stream, "<illegal constant %.8x:%x:%x>",
4443 bits, cmode, op);
4444 size = 32;
4445 break;
4446 }
4447 switch (size)
4448 {
4449 case 8:
4450 func (stream, "#%ld\t; 0x%.2lx", value, value);
4451 break;
43e65147 4452
16980d0b
JB		 4453 case 16:
4454 func (stream, "#%ld\t; 0x%.4lx", value, value);
4455 break;
4456
4457 case 32:
0dbde4cf
JB		 4458 if (isfloat)
4459 {
4460 unsigned char valbytes[4];
4461 double fvalue;
43e65147 4462
0dbde4cf
JB		 4463 /* Do this a byte at a time so we don't have to
4464 worry about the host's endianness. */
4465 valbytes[0] = value & 0xff;
4466 valbytes[1] = (value >> 8) & 0xff;
4467 valbytes[2] = (value >> 16) & 0xff;
4468 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4469
4470 floatformat_to_double
c1e26897
NC		 4471 (& floatformat_ieee_single_little, valbytes,
4472 & fvalue);
43e65147 4473
0dbde4cf
JB		 4474 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4475 value);
4476 }
4477 else
4e9d3b81 4478 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4479 (long) (((value & 0x80000000L) != 0)
9d82ec38 4480 ? value | ~0xffffffffL : value),
c1e26897 4481 value);
16980d0b
JB		 4482 break;
4483
4484 case 64:
4485 func (stream, "#0x%.8lx%.8lx", hival, value);
4486 break;
43e65147 4487
16980d0b
JB		 4488 default:
4489 abort ();
4490 }
4491 }
4492 break;
43e65147 4493
16980d0b
JB		 4494 case 'F':
4495 {
4496 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4497 int num = (given >> 8) & 0x3;
43e65147 4498
16980d0b
JB		 4499 if (!num)
4500 func (stream, "{d%d}", regno);
4501 else if (num + regno >= 32)
4502 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4503 else
4504 func (stream, "{d%d-d%d}", regno, regno + num);
4505 }
4506 break;
7e8e6784 4507
16980d0b
JB		 4508
4509 case '0': case '1': case '2': case '3': case '4':
4510 case '5': case '6': case '7': case '8': case '9':
4511 {
4512 int width;
4513 unsigned long value;
4514
4515 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4516
16980d0b
JB		 4517 switch (*c)
4518 {
4519 case 'r':
4520 func (stream, "%s", arm_regnames[value]);
4521 break;
4522 case 'd':
4523 func (stream, "%ld", value);
05413229 4524 value_in_comment = value;
16980d0b
JB		 4525 break;
4526 case 'e':
4527 func (stream, "%ld", (1ul << width) - value);
4528 break;
43e65147 4529
16980d0b
JB		 4530 case 'S':
4531 case 'T':
4532 case 'U':
05413229 4533 /* Various width encodings. */
16980d0b
JB		 4534 {
4535 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4536 int limit;
4537 unsigned low, high;
4538
4539 c++;
4540 if (*c >= '0' && *c <= '9')
4541 limit = *c - '0';
4542 else if (*c >= 'a' && *c <= 'f')
4543 limit = *c - 'a' + 10;
4544 else
4545 abort ();
4546 low = limit >> 2;
4547 high = limit & 3;
4548
4549 if (value < low || value > high)
4550 func (stream, "<illegal width %d>", base << value);
4551 else
4552 func (stream, "%d", base << value);
4553 }
4554 break;
4555 case 'R':
4556 if (given & (1 << 6))
4557 goto Q;
4558 /* FALLTHROUGH */
4559 case 'D':
4560 func (stream, "d%ld", value);
4561 break;
4562 case 'Q':
4563 Q:
4564 if (value & 1)
4565 func (stream, "<illegal reg q%ld.5>", value >> 1);
4566 else
4567 func (stream, "q%ld", value >> 1);
4568 break;
43e65147 4569
16980d0b
JB		 4570 case '`':
4571 c++;
4572 if (value == 0)
4573 func (stream, "%c", *c);
4574 break;
4575 case '\'':
4576 c++;
4577 if (value == ((1ul << width) - 1))
4578 func (stream, "%c", *c);
4579 break;
4580 case '?':
fe56b6ce 4581 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4582 c += 1 << width;
4583 break;
4584 default:
4585 abort ();
4586 }
4587 break;
4588
4589 default:
4590 abort ();
4591 }
4592 }
4593 }
4594 else
4595 func (stream, "%c", *c);
4596 }
05413229
NC		 4597
4598 if (value_in_comment > 32 || value_in_comment < -16)
4599 func (stream, "\t; 0x%lx", value_in_comment);
4600
e2efe87d
MGD		 4601 if (is_unpredictable)
4602 func (stream, UNPREDICTABLE_INSTRUCTION);
4603
16980d0b
JB		 4604 return TRUE;
4605 }
4606 }
4607 return FALSE;
4608}
4609
90ec0d68
MGD		 4610/* Return the name of a v7A special register. */
4611
43e65147 4612static const char *
90ec0d68
MGD		 4613banked_regname (unsigned reg)
4614{
4615 switch (reg)
4616 {
4617 case 15: return "CPSR";
43e65147 4618 case 32: return "R8_usr";
90ec0d68
MGD		 4619 case 33: return "R9_usr";
4620 case 34: return "R10_usr";
4621 case 35: return "R11_usr";
4622 case 36: return "R12_usr";
4623 case 37: return "SP_usr";
4624 case 38: return "LR_usr";
43e65147 4625 case 40: return "R8_fiq";
90ec0d68
MGD		 4626 case 41: return "R9_fiq";
4627 case 42: return "R10_fiq";
4628 case 43: return "R11_fiq";
4629 case 44: return "R12_fiq";
4630 case 45: return "SP_fiq";
4631 case 46: return "LR_fiq";
4632 case 48: return "LR_irq";
4633 case 49: return "SP_irq";
4634 case 50: return "LR_svc";
4635 case 51: return "SP_svc";
4636 case 52: return "LR_abt";
4637 case 53: return "SP_abt";
4638 case 54: return "LR_und";
4639 case 55: return "SP_und";
4640 case 60: return "LR_mon";
4641 case 61: return "SP_mon";
4642 case 62: return "ELR_hyp";
4643 case 63: return "SP_hyp";
4644 case 79: return "SPSR";
4645 case 110: return "SPSR_fiq";
4646 case 112: return "SPSR_irq";
4647 case 114: return "SPSR_svc";
4648 case 116: return "SPSR_abt";
4649 case 118: return "SPSR_und";
4650 case 124: return "SPSR_mon";
4651 case 126: return "SPSR_hyp";
4652 default: return NULL;
4653 }
4654}
4655
e797f7e0
MGD		 4656/* Return the name of the DMB/DSB option. */
4657static const char *
4658data_barrier_option (unsigned option)
4659{
4660 switch (option & 0xf)
4661 {
4662 case 0xf: return "sy";
4663 case 0xe: return "st";
4664 case 0xd: return "ld";
4665 case 0xb: return "ish";
4666 case 0xa: return "ishst";
4667 case 0x9: return "ishld";
4668 case 0x7: return "un";
4669 case 0x6: return "unst";
4670 case 0x5: return "nshld";
4671 case 0x3: return "osh";
4672 case 0x2: return "oshst";
4673 case 0x1: return "oshld";
4674 default: return NULL;
4675 }
4676}
4677
4a5329c6
ZW		 4678/* Print one ARM instruction from PC on INFO->STREAM. */
4679
4680static void
4681print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4682{
6b5d3a4d 4683 const struct opcode32 *insn;
6a51a8a8 4684 void *stream = info->stream;
6b5d3a4d 4685 fprintf_ftype func = info->fprintf_func;
b0e28b39 4686 struct arm_private_data *private_data = info->private_data;
252b5132 4687
16980d0b
JB		 4688 if (print_insn_coprocessor (pc, info, given, FALSE))
4689 return;
4690
4691 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4692 return;
4693
252b5132
RH		 4694 for (insn = arm_opcodes; insn->assembler; insn++)
4695 {
0313a2b8
NC		 4696 if ((given & insn->mask) != insn->value)
4697 continue;
823d2571
TG		 4698
4699 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4700 continue;
4701
4702 /* Special case: an instruction with all bits set in the condition field
4703 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4704 or by the catchall at the end of the table. */
4705 if ((given & 0xF0000000) != 0xF0000000
4706 || (insn->mask & 0xF0000000) == 0xF0000000
4707 || (insn->mask == 0 && insn->value == 0))
252b5132 4708 {
ff4a8d2b
NC		 4709 unsigned long u_reg = 16;
4710 unsigned long U_reg = 16;
ab8e2090 4711 bfd_boolean is_unpredictable = FALSE;
05413229 4712 signed long value_in_comment = 0;
6b5d3a4d 4713 const char *c;
b34976b6 4714
252b5132
RH		 4715 for (c = insn->assembler; *c; c++)
4716 {
4717 if (*c == '%')
4718 {
c1e26897
NC		 4719 bfd_boolean allow_unpredictable = FALSE;
4720
252b5132
RH		 4721 switch (*++c)
4722 {
4723 case '%':
4724 func (stream, "%%");
4725 break;
4726
4727 case 'a':
05413229 4728 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4729 break;
252b5132 4730
62b3e311
PB		 4731 case 'P':
4732 /* Set P address bit and use normal address
4733 printing routine. */
c1e26897 4734 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4735 break;
4736
c1e26897
NC		 4737 case 'S':
4738 allow_unpredictable = TRUE;
1a0670f3 4739 /* Fall through. */
252b5132
RH		 4740 case 's':
4741 if ((given & 0x004f0000) == 0x004f0000)
4742 {
58efb6c0 4743 /* PC relative with immediate offset. */
f8b960bc 4744 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4745
aefd8a40
NC		 4746 if (PRE_BIT_SET)
4747 {
26d97720
NS		 4748 /* Elide positive zero offset. */
4749 if (offset || NEGATIVE_BIT_SET)
4750 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4751 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4752 else
26d97720
NS		 4753 func (stream, "[pc]\t; ");
4754 if (NEGATIVE_BIT_SET)
4755 offset = -offset;
aefd8a40
NC		 4756 info->print_address_func (offset + pc + 8, info);
4757 }
4758 else
4759 {
26d97720
NS		 4760 /* Always show the offset. */
4761 func (stream, "[pc], #%s%d",
d908c8af 4762 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4763 if (! allow_unpredictable)
4764 is_unpredictable = TRUE;
aefd8a40 4765 }
252b5132
RH		 4766 }
4767 else
4768 {
fe56b6ce
NC		 4769 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4770
b34976b6 4771 func (stream, "[%s",
252b5132 4772 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4773
c1e26897 4774 if (PRE_BIT_SET)
252b5132 4775 {
c1e26897 4776 if (IMMEDIATE_BIT_SET)
252b5132 4777 {
26d97720
NS		 4778 /* Elide offset for non-writeback
4779 positive zero. */
4780 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4781 || offset)
4782 func (stream, ", #%s%d",
4783 NEGATIVE_BIT_SET ? "-" : "", offset);
4784
4785 if (NEGATIVE_BIT_SET)
4786 offset = -offset;
945ee430 4787
fe56b6ce 4788 value_in_comment = offset;
252b5132 4789 }
945ee430 4790 else
ff4a8d2b
NC		 4791 {
4792 /* Register Offset or Register Pre-Indexed. */
4793 func (stream, ", %s%s",
4794 NEGATIVE_BIT_SET ? "-" : "",
4795 arm_regnames[given & 0xf]);
4796
4797 /* Writing back to the register that is the source/
4798 destination of the load/store is unpredictable. */
4799 if (! allow_unpredictable
4800 && WRITEBACK_BIT_SET
4801 && ((given & 0xf) == ((given >> 12) & 0xf)))
4802 is_unpredictable = TRUE;
4803 }
252b5132 4804
b34976b6 4805 func (stream, "]%s",
c1e26897 4806 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4807 }
945ee430 4808 else
252b5132 4809 {
c1e26897 4810 if (IMMEDIATE_BIT_SET)
252b5132 4811 {
945ee430 4812 /* Immediate Post-indexed. */
aefd8a40 4813 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4814 func (stream, "], #%s%d",
4815 NEGATIVE_BIT_SET ? "-" : "", offset);
4816 if (NEGATIVE_BIT_SET)
4817 offset = -offset;
fe56b6ce 4818 value_in_comment = offset;
252b5132 4819 }
945ee430 4820 else
ff4a8d2b
NC		 4821 {
4822 /* Register Post-indexed. */
4823 func (stream, "], %s%s",
4824 NEGATIVE_BIT_SET ? "-" : "",
4825 arm_regnames[given & 0xf]);
4826
4827 /* Writing back to the register that is the source/
4828 destination of the load/store is unpredictable. */
4829 if (! allow_unpredictable
4830 && (given & 0xf) == ((given >> 12) & 0xf))
4831 is_unpredictable = TRUE;
4832 }
c1e26897 4833
07a28fab
NC		 4834 if (! allow_unpredictable)
4835 {
4836 /* Writeback is automatically implied by post- addressing.
4837 Setting the W bit is unnecessary and ARM specify it as
4838 being unpredictable. */
4839 if (WRITEBACK_BIT_SET
4840 /* Specifying the PC register as the post-indexed
4841 registers is also unpredictable. */
ab8e2090
NC		 4842 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4843 is_unpredictable = TRUE;
07a28fab 4844 }
252b5132
RH		 4845 }
4846 }
4847 break;
b34976b6 4848
252b5132 4849 case 'b':
6b5d3a4d 4850 {
f8b960bc 4851 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4852 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4853 }
252b5132
RH		 4854 break;
4855
4856 case 'c':
c22aaad1
PB		 4857 if (((given >> 28) & 0xf) != 0xe)
4858 func (stream, "%s",
4859 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4860 break;
4861
4862 case 'm':
4863 {
4864 int started = 0;
4865 int reg;
4866
4867 func (stream, "{");
4868 for (reg = 0; reg < 16; reg++)
4869 if ((given & (1 << reg)) != 0)
4870 {
4871 if (started)
4872 func (stream, ", ");
4873 started = 1;
4874 func (stream, "%s", arm_regnames[reg]);
4875 }
4876 func (stream, "}");
ab8e2090
NC		 4877 if (! started)
4878 is_unpredictable = TRUE;
252b5132
RH		 4879 }
4880 break;
4881
37b37b2d 4882 case 'q':
78c66db8 4883 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4884 break;
4885
252b5132
RH		 4886 case 'o':
4887 if ((given & 0x02000000) != 0)
4888 {
a415b1cd
JB		 4889 unsigned int rotate = (given & 0xf00) >> 7;
4890 unsigned int immed = (given & 0xff);
4891 unsigned int a, i;
4892
4893 a = (((immed << (32 - rotate))
4894 | (immed >> rotate)) & 0xffffffff);
4895 /* If there is another encoding with smaller rotate,
4896 the rotate should be specified directly. */
4897 for (i = 0; i < 32; i += 2)
4898 if ((a << i | a >> (32 - i)) <= 0xff)
4899 break;
4900
4901 if (i != rotate)
4902 func (stream, "#%d, %d", immed, rotate);
4903 else
4904 func (stream, "#%d", a);
4905 value_in_comment = a;
252b5132
RH		 4906 }
4907 else
78c66db8 4908 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4909 break;
4910
4911 case 'p':
4912 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4913 {
823d2571
TG		 4914 arm_feature_set arm_ext_v6 =
4915 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4916
aefd8a40
NC		 4917 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4918 mechanism for setting PSR flag bits. They are
4919 obsolete in V6 onwards. */
823d2571
TG		 4920 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4921 arm_ext_v6))
aefd8a40 4922 func (stream, "p");
4ab90a7a
AV		 4923 else
4924 is_unpredictable = TRUE;
aefd8a40 4925 }
252b5132
RH		 4926 break;
4927
4928 case 't':
4929 if ((given & 0x01200000) == 0x00200000)
4930 func (stream, "t");
4931 break;
4932
252b5132 4933 case 'A':
05413229
NC		 4934 {
4935 int offset = given & 0xff;
f02232aa 4936
05413229 4937 value_in_comment = offset * 4;
c1e26897 4938 if (NEGATIVE_BIT_SET)
05413229 4939 value_in_comment = - value_in_comment;
f02232aa 4940
05413229 4941 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4942
c1e26897 4943 if (PRE_BIT_SET)
05413229
NC		 4944 {
4945 if (offset)
fe56b6ce 4946 func (stream, ", #%d]%s",
d908c8af 4947 (int) value_in_comment,
c1e26897 4948 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4949 else
4950 func (stream, "]");
4951 }
4952 else
4953 {
4954 func (stream, "]");
f02232aa 4955
c1e26897 4956 if (WRITEBACK_BIT_SET)
05413229
NC		 4957 {
4958 if (offset)
d908c8af 4959 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4960 }
4961 else
fe56b6ce 4962 {
d908c8af 4963 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4964 value_in_comment = offset;
4965 }
05413229
NC		 4966 }
4967 }
252b5132
RH		 4968 break;
4969
077b8428
NC		 4970 case 'B':
4971 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4972 {
4973 bfd_vma address;
4974 bfd_vma offset = 0;
b34976b6 4975
c1e26897 4976 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4977 /* Is signed, hi bits should be ones. */
4978 offset = (-1) ^ 0x00ffffff;
4979
4980 /* Offset is (SignExtend(offset field)<<2). */
4981 offset += given & 0x00ffffff;
4982 offset <<= 2;
4983 address = offset + pc + 8;
b34976b6 4984
8f06b2d8
PB		 4985 if (given & 0x01000000)
4986 /* H bit allows addressing to 2-byte boundaries. */
4987 address += 2;
b1ee46c5 4988
8f06b2d8 4989 info->print_address_func (address, info);
b1ee46c5 4990 }
b1ee46c5
AH		 4991 break;
4992
252b5132 4993 case 'C':
90ec0d68
MGD		 4994 if ((given & 0x02000200) == 0x200)
4995 {
4996 const char * name;
4997 unsigned sysm = (given & 0x004f0000) >> 16;
4998
4999 sysm |= (given & 0x300) >> 4;
5000 name = banked_regname (sysm);
5001
5002 if (name != NULL)
5003 func (stream, "%s", name);
5004 else
d908c8af 5005 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5006 }
5007 else
5008 {
43e65147 5009 func (stream, "%cPSR_",
90ec0d68
MGD		 5010 (given & 0x00400000) ? 'S' : 'C');
5011 if (given & 0x80000)
5012 func (stream, "f");
5013 if (given & 0x40000)
5014 func (stream, "s");
5015 if (given & 0x20000)
5016 func (stream, "x");
5017 if (given & 0x10000)
5018 func (stream, "c");
5019 }
252b5132
RH		 5020 break;
5021
62b3e311 5022 case 'U':
43e65147 5023 if ((given & 0xf0) == 0x60)
62b3e311 5024 {
52e7f43d
RE		 5025 switch (given & 0xf)
5026 {
5027 case 0xf: func (stream, "sy"); break;
5028 default:
5029 func (stream, "#%d", (int) given & 0xf);
5030 break;
5031 }
43e65147
L		 5032 }
5033 else
52e7f43d 5034 {
e797f7e0
MGD		 5035 const char * opt = data_barrier_option (given & 0xf);
5036 if (opt != NULL)
5037 func (stream, "%s", opt);
5038 else
52e7f43d 5039 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5040 }
5041 break;
5042
b34976b6 5043 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5044 case '5': case '6': case '7': case '8': case '9':
5045 {
16980d0b
JB		 5046 int width;
5047 unsigned long value;
252b5132 5048
16980d0b 5049 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5050
252b5132
RH		 5051 switch (*c)
5052 {
ab8e2090
NC		 5053 case 'R':
5054 if (value == 15)
5055 is_unpredictable = TRUE;
5056 /* Fall through. */
16980d0b 5057 case 'r':
9eb6c0f1
MGD		 5058 case 'T':
5059 /* We want register + 1 when decoding T. */
5060 if (*c == 'T')
5061 ++value;
5062
ff4a8d2b
NC		 5063 if (c[1] == 'u')
5064 {
5065 /* Eat the 'u' character. */
5066 ++ c;
5067
5068 if (u_reg == value)
5069 is_unpredictable = TRUE;
5070 u_reg = value;
5071 }
5072 if (c[1] == 'U')
5073 {
5074 /* Eat the 'U' character. */
5075 ++ c;
5076
5077 if (U_reg == value)
5078 is_unpredictable = TRUE;
5079 U_reg = value;
5080 }
16980d0b
JB		 5081 func (stream, "%s", arm_regnames[value]);
5082 break;
5083 case 'd':
5084 func (stream, "%ld", value);
05413229 5085 value_in_comment = value;
16980d0b
JB		 5086 break;
5087 case 'b':
5088 func (stream, "%ld", value * 8);
05413229 5089 value_in_comment = value * 8;
16980d0b
JB		 5090 break;
5091 case 'W':
5092 func (stream, "%ld", value + 1);
05413229 5093 value_in_comment = value + 1;
16980d0b
JB		 5094 break;
5095 case 'x':
5096 func (stream, "0x%08lx", value);
5097
5098 /* Some SWI instructions have special
5099 meanings. */
5100 if ((given & 0x0fffffff) == 0x0FF00000)
5101 func (stream, "\t; IMB");
5102 else if ((given & 0x0fffffff) == 0x0FF00001)
5103 func (stream, "\t; IMBRange");
5104 break;
5105 case 'X':
5106 func (stream, "%01lx", value & 0xf);
05413229 5107 value_in_comment = value;
252b5132
RH		 5108 break;
5109 case '`':
5110 c++;
16980d0b 5111 if (value == 0)
252b5132
RH		 5112 func (stream, "%c", *c);
5113 break;
5114 case '\'':
5115 c++;
16980d0b 5116 if (value == ((1ul << width) - 1))
252b5132
RH		 5117 func (stream, "%c", *c);
5118 break;
5119 case '?':
fe56b6ce 5120 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5121 c += 1 << width;
252b5132
RH		 5122 break;
5123 default:
5124 abort ();
5125 }
5126 break;
5127
0dd132b6
NC		 5128 case 'e':
5129 {
5130 int imm;
5131
5132 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5133 func (stream, "%d", imm);
fe56b6ce 5134 value_in_comment = imm;
0dd132b6
NC		 5135 }
5136 break;
5137
0a003adc
ZW		 5138 case 'E':
5139 /* LSB and WIDTH fields of BFI or BFC. The machine-
5140 language instruction encodes LSB and MSB. */
5141 {
5142 long msb = (given & 0x001f0000) >> 16;
5143 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5144 long w = msb - lsb + 1;
fe56b6ce 5145
91d6fa6a
NC		 5146 if (w > 0)
5147 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5148 else
5149 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5150 }
5151 break;
5152
90ec0d68
MGD		 5153 case 'R':
5154 /* Get the PSR/banked register name. */
5155 {
5156 const char * name;
5157 unsigned sysm = (given & 0x004f0000) >> 16;
5158
5159 sysm |= (given & 0x300) >> 4;
5160 name = banked_regname (sysm);
5161
5162 if (name != NULL)
5163 func (stream, "%s", name);
5164 else
d908c8af 5165 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5166 }
5167 break;
5168
0a003adc
ZW		 5169 case 'V':
5170 /* 16-bit unsigned immediate from a MOVT or MOVW
5171 instruction, encoded in bits 0:11 and 15:19. */
5172 {
5173 long hi = (given & 0x000f0000) >> 4;
5174 long lo = (given & 0x00000fff);
5175 long imm16 = hi | lo;
fe56b6ce
NC		 5176
5177 func (stream, "#%lu", imm16);
5178 value_in_comment = imm16;
0a003adc
ZW		 5179 }
5180 break;
5181
252b5132
RH		 5182 default:
5183 abort ();
5184 }
5185 }
5186 }
5187 else
5188 func (stream, "%c", *c);
5189 }
05413229
NC		 5190
5191 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5192 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5193
5194 if (is_unpredictable)
5195 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5196
4a5329c6 5197 return;
252b5132
RH		 5198 }
5199 }
0b347048
TC		 5200 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5201 return;
252b5132
RH		 5202}
5203
4a5329c6 5204/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5205
4a5329c6
ZW		 5206static void
5207print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5208{
6b5d3a4d 5209 const struct opcode16 *insn;
6a51a8a8
AM		 5210 void *stream = info->stream;
5211 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5212
5213 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5214 if ((given & insn->mask) == insn->value)
5215 {
05413229 5216 signed long value_in_comment = 0;
6b5d3a4d 5217 const char *c = insn->assembler;
05413229 5218
c19d1205
ZW		 5219 for (; *c; c++)
5220 {
5221 int domaskpc = 0;
5222 int domasklr = 0;
5223
5224 if (*c != '%')
5225 {
5226 func (stream, "%c", *c);
5227 continue;
5228 }
252b5132 5229
c19d1205
ZW		 5230 switch (*++c)
5231 {
5232 case '%':
5233 func (stream, "%%");
5234 break;
b34976b6 5235
c22aaad1
PB		 5236 case 'c':
5237 if (ifthen_state)
5238 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5239 break;
5240
5241 case 'C':
5242 if (ifthen_state)
5243 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5244 else
5245 func (stream, "s");
5246 break;
5247
5248 case 'I':
5249 {
5250 unsigned int tmp;
5251
5252 ifthen_next_state = given & 0xff;
5253 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5254 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5255 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5256 }
5257 break;
5258
5259 case 'x':
5260 if (ifthen_next_state)
5261 func (stream, "\t; unpredictable branch in IT block\n");
5262 break;
5263
5264 case 'X':
5265 if (ifthen_state)
5266 func (stream, "\t; unpredictable <IT:%s>",
5267 arm_conditional[IFTHEN_COND]);
5268 break;
5269
c19d1205
ZW		 5270 case 'S':
5271 {
5272 long reg;
5273
5274 reg = (given >> 3) & 0x7;
5275 if (given & (1 << 6))
5276 reg += 8;
4f3c3dbb 5277
c19d1205
ZW		 5278 func (stream, "%s", arm_regnames[reg]);
5279 }
5280 break;
baf0cc5e 5281
c19d1205 5282 case 'D':
4f3c3dbb 5283 {
c19d1205
ZW		 5284 long reg;
5285
5286 reg = given & 0x7;
5287 if (given & (1 << 7))
5288 reg += 8;
5289
5290 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5291 }
c19d1205
ZW		 5292 break;
5293
5294 case 'N':
5295 if (given & (1 << 8))
5296 domasklr = 1;
5297 /* Fall through. */
5298 case 'O':
5299 if (*c == 'O' && (given & (1 << 8)))
5300 domaskpc = 1;
5301 /* Fall through. */
5302 case 'M':
5303 {
5304 int started = 0;
5305 int reg;
5306
5307 func (stream, "{");
5308
5309 /* It would be nice if we could spot
5310 ranges, and generate the rS-rE format: */
5311 for (reg = 0; (reg < 8); reg++)
5312 if ((given & (1 << reg)) != 0)
5313 {
5314 if (started)
5315 func (stream, ", ");
5316 started = 1;
5317 func (stream, "%s", arm_regnames[reg]);
5318 }
5319
5320 if (domasklr)
5321 {
5322 if (started)
5323 func (stream, ", ");
5324 started = 1;
d908c8af 5325 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5326 }
5327
5328 if (domaskpc)
5329 {
5330 if (started)
5331 func (stream, ", ");
d908c8af 5332 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5333 }
5334
5335 func (stream, "}");
5336 }
5337 break;
5338
4547cb56
NC		 5339 case 'W':
5340 /* Print writeback indicator for a LDMIA. We are doing a
5341 writeback if the base register is not in the register
5342 mask. */
5343 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5344 func (stream, "!");
5345 break;
5346
c19d1205
ZW		 5347 case 'b':
5348 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5349 {
5350 bfd_vma address = (pc + 4
5351 + ((given & 0x00f8) >> 2)
5352 + ((given & 0x0200) >> 3));
5353 info->print_address_func (address, info);
5354 }
5355 break;
5356
5357 case 's':
5358 /* Right shift immediate -- bits 6..10; 1-31 print
5359 as themselves, 0 prints as 32. */
5360 {
5361 long imm = (given & 0x07c0) >> 6;
5362 if (imm == 0)
5363 imm = 32;
0fd3a477 5364 func (stream, "#%ld", imm);
c19d1205
ZW		 5365 }
5366 break;
5367
5368 case '0': case '1': case '2': case '3': case '4':
5369 case '5': case '6': case '7': case '8': case '9':
5370 {
5371 int bitstart = *c++ - '0';
5372 int bitend = 0;
5373
5374 while (*c >= '0' && *c <= '9')
5375 bitstart = (bitstart * 10) + *c++ - '0';
5376
5377 switch (*c)
5378 {
5379 case '-':
5380 {
f8b960bc 5381 bfd_vma reg;
c19d1205
ZW		 5382
5383 c++;
5384 while (*c >= '0' && *c <= '9')
5385 bitend = (bitend * 10) + *c++ - '0';
5386 if (!bitend)
5387 abort ();
5388 reg = given >> bitstart;
5389 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5390
c19d1205
ZW		 5391 switch (*c)
5392 {
5393 case 'r':
5394 func (stream, "%s", arm_regnames[reg]);
5395 break;
5396
5397 case 'd':
d908c8af 5398 func (stream, "%ld", (long) reg);
05413229 5399 value_in_comment = reg;
c19d1205
ZW		 5400 break;
5401
5402 case 'H':
d908c8af 5403 func (stream, "%ld", (long) (reg << 1));
05413229 5404 value_in_comment = reg << 1;
c19d1205
ZW		 5405 break;
5406
5407 case 'W':
d908c8af 5408 func (stream, "%ld", (long) (reg << 2));
05413229 5409 value_in_comment = reg << 2;
c19d1205
ZW		 5410 break;
5411
5412 case 'a':
5413 /* PC-relative address -- the bottom two
5414 bits of the address are dropped
5415 before the calculation. */
5416 info->print_address_func
5417 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5418 value_in_comment = 0;
c19d1205
ZW		 5419 break;
5420
5421 case 'x':
d908c8af 5422 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5423 break;
5424
c19d1205
ZW		 5425 case 'B':
5426 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5427 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5428 value_in_comment = 0;
c19d1205
ZW		 5429 break;
5430
5431 case 'c':
c22aaad1 5432 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5433 break;
5434
5435 default:
5436 abort ();
5437 }
5438 }
5439 break;
5440
5441 case '\'':
5442 c++;
5443 if ((given & (1 << bitstart)) != 0)
5444 func (stream, "%c", *c);
5445 break;
5446
5447 case '?':
5448 ++c;
5449 if ((given & (1 << bitstart)) != 0)
5450 func (stream, "%c", *c++);
5451 else
5452 func (stream, "%c", *++c);
5453 break;
5454
5455 default:
5456 abort ();
5457 }
5458 }
5459 break;
5460
5461 default:
5462 abort ();
5463 }
5464 }
05413229
NC		 5465
5466 if (value_in_comment > 32 || value_in_comment < -16)
5467 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5468 return;
c19d1205
ZW		 5469 }
5470
5471 /* No match. */
0b347048
TC		 5472 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5473 return;
c19d1205
ZW		 5474}
5475
62b3e311 5476/* Return the name of an V7M special register. */
fe56b6ce 5477
62b3e311
PB		 5478static const char *
5479psr_name (int regno)
5480{
5481 switch (regno)
5482 {
1a336194
TP		 5483 case 0x0: return "APSR";
5484 case 0x1: return "IAPSR";
5485 case 0x2: return "EAPSR";
5486 case 0x3: return "PSR";
5487 case 0x5: return "IPSR";
5488 case 0x6: return "EPSR";
5489 case 0x7: return "IEPSR";
5490 case 0x8: return "MSP";
5491 case 0x9: return "PSP";
5492 case 0xa: return "MSPLIM";
5493 case 0xb: return "PSPLIM";
5494 case 0x10: return "PRIMASK";
5495 case 0x11: return "BASEPRI";
5496 case 0x12: return "BASEPRI_MAX";
5497 case 0x13: return "FAULTMASK";
5498 case 0x14: return "CONTROL";
16a1fa25
TP		 5499 case 0x88: return "MSP_NS";
5500 case 0x89: return "PSP_NS";
1a336194
TP		 5501 case 0x8a: return "MSPLIM_NS";
5502 case 0x8b: return "PSPLIM_NS";
5503 case 0x90: return "PRIMASK_NS";
5504 case 0x91: return "BASEPRI_NS";
5505 case 0x93: return "FAULTMASK_NS";
5506 case 0x94: return "CONTROL_NS";
5507 case 0x98: return "SP_NS";
62b3e311
PB		 5508 default: return "<unknown>";
5509 }
5510}
5511
4a5329c6
ZW		 5512/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5513
5514static void
5515print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5516{
6b5d3a4d 5517 const struct opcode32 *insn;
c19d1205
ZW		 5518 void *stream = info->stream;
5519 fprintf_ftype func = info->fprintf_func;
5520
16980d0b
JB		 5521 if (print_insn_coprocessor (pc, info, given, TRUE))
5522 return;
5523
5524 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5525 return;
5526
c19d1205
ZW		 5527 for (insn = thumb32_opcodes; insn->assembler; insn++)
5528 if ((given & insn->mask) == insn->value)
5529 {
ff4a8d2b 5530 bfd_boolean is_unpredictable = FALSE;
05413229 5531 signed long value_in_comment = 0;
6b5d3a4d 5532 const char *c = insn->assembler;
05413229 5533
c19d1205
ZW		 5534 for (; *c; c++)
5535 {
5536 if (*c != '%')
5537 {
5538 func (stream, "%c", *c);
5539 continue;
5540 }
5541
5542 switch (*++c)
5543 {
5544 case '%':
5545 func (stream, "%%");
5546 break;
5547
c22aaad1
PB		 5548 case 'c':
5549 if (ifthen_state)
5550 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5551 break;
5552
5553 case 'x':
5554 if (ifthen_next_state)
5555 func (stream, "\t; unpredictable branch in IT block\n");
5556 break;
5557
5558 case 'X':
5559 if (ifthen_state)
5560 func (stream, "\t; unpredictable <IT:%s>",
5561 arm_conditional[IFTHEN_COND]);
5562 break;
5563
c19d1205
ZW		 5564 case 'I':
5565 {
5566 unsigned int imm12 = 0;
fe56b6ce 5567
c19d1205
ZW		 5568 imm12 |= (given & 0x000000ffu);
5569 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5570 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5571 func (stream, "#%u", imm12);
5572 value_in_comment = imm12;
c19d1205
ZW		 5573 }
5574 break;
5575
5576 case 'M':
5577 {
5578 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5579
c19d1205
ZW		 5580 bits |= (given & 0x000000ffu);
5581 bits |= (given & 0x00007000u) >> 4;
5582 bits |= (given & 0x04000000u) >> 15;
5583 imm8 = (bits & 0x0ff);
5584 mod = (bits & 0xf00) >> 8;
5585 switch (mod)
5586 {
5587 case 0: imm = imm8; break;
c1e26897
NC		 5588 case 1: imm = ((imm8 << 16) | imm8); break;
5589 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5590 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5591 default:
5592 mod = (bits & 0xf80) >> 7;
5593 imm8 = (bits & 0x07f) | 0x80;
5594 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5595 }
fe56b6ce
NC		 5596 func (stream, "#%u", imm);
5597 value_in_comment = imm;
c19d1205
ZW		 5598 }
5599 break;
43e65147 5600
c19d1205
ZW		 5601 case 'J':
5602 {
5603 unsigned int imm = 0;
fe56b6ce 5604
c19d1205
ZW		 5605 imm |= (given & 0x000000ffu);
5606 imm |= (given & 0x00007000u) >> 4;
5607 imm |= (given & 0x04000000u) >> 15;
5608 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5609 func (stream, "#%u", imm);
5610 value_in_comment = imm;
c19d1205
ZW		 5611 }
5612 break;
5613
5614 case 'K':
5615 {
5616 unsigned int imm = 0;
fe56b6ce 5617
c19d1205
ZW		 5618 imm |= (given & 0x000f0000u) >> 16;
5619 imm |= (given & 0x00000ff0u) >> 0;
5620 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5621 func (stream, "#%u", imm);
5622 value_in_comment = imm;
c19d1205
ZW		 5623 }
5624 break;
5625
74db7efb
NC		 5626 case 'H':
5627 {
5628 unsigned int imm = 0;
5629
5630 imm |= (given & 0x000f0000u) >> 4;
5631 imm |= (given & 0x00000fffu) >> 0;
5632 func (stream, "#%u", imm);
5633 value_in_comment = imm;
5634 }
5635 break;
5636
90ec0d68
MGD		 5637 case 'V':
5638 {
5639 unsigned int imm = 0;
5640
5641 imm |= (given & 0x00000fffu);
5642 imm |= (given & 0x000f0000u) >> 4;
5643 func (stream, "#%u", imm);
5644 value_in_comment = imm;
5645 }
5646 break;
5647
c19d1205
ZW		 5648 case 'S':
5649 {
5650 unsigned int reg = (given & 0x0000000fu);
5651 unsigned int stp = (given & 0x00000030u) >> 4;
5652 unsigned int imm = 0;
5653 imm |= (given & 0x000000c0u) >> 6;
5654 imm |= (given & 0x00007000u) >> 10;
5655
5656 func (stream, "%s", arm_regnames[reg]);
5657 switch (stp)
5658 {
5659 case 0:
5660 if (imm > 0)
5661 func (stream, ", lsl #%u", imm);
5662 break;
5663
5664 case 1:
5665 if (imm == 0)
5666 imm = 32;
5667 func (stream, ", lsr #%u", imm);
5668 break;
5669
5670 case 2:
5671 if (imm == 0)
5672 imm = 32;
5673 func (stream, ", asr #%u", imm);
5674 break;
5675
5676 case 3:
5677 if (imm == 0)
5678 func (stream, ", rrx");
5679 else
5680 func (stream, ", ror #%u", imm);
5681 }
5682 }
5683 break;
5684
5685 case 'a':
5686 {
5687 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5688 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5689 unsigned int op = (given & 0x00000f00) >> 8;
5690 unsigned int i12 = (given & 0x00000fff);
5691 unsigned int i8 = (given & 0x000000ff);
5692 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5693 bfd_vma offset = 0;
c19d1205
ZW		 5694
5695 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5696 if (U) /* 12-bit positive immediate offset. */
5697 {
5698 offset = i12;
5699 if (Rn != 15)
5700 value_in_comment = offset;
5701 }
5702 else if (Rn == 15) /* 12-bit negative immediate offset. */
5703 offset = - (int) i12;
5704 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5705 {
5706 unsigned int Rm = (i8 & 0x0f);
5707 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5708
c19d1205
ZW		 5709 func (stream, ", %s", arm_regnames[Rm]);
5710 if (sh)
5711 func (stream, ", lsl #%u", sh);
5712 func (stream, "]");
5713 break;
5714 }
5715 else switch (op)
5716 {
05413229 5717 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5718 offset = i8;
5719 break;
5720
05413229 5721 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5722 offset = -i8;
5723 break;
5724
05413229 5725 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5726 offset = i8;
5727 writeback = TRUE;
5728 break;
5729
05413229 5730 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5731 offset = -i8;
5732 writeback = TRUE;
5733 break;
5734
05413229 5735 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5736 offset = i8;
5737 postind = TRUE;
5738 break;
5739
05413229 5740 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5741 offset = -i8;
5742 postind = TRUE;
5743 break;
5744
5745 default:
5746 func (stream, ", <undefined>]");
5747 goto skip;
5748 }
5749
5750 if (postind)
d908c8af 5751 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5752 else
5753 {
5754 if (offset)
d908c8af 5755 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5756 func (stream, writeback ? "]!" : "]");
5757 }
5758
5759 if (Rn == 15)
5760 {
5761 func (stream, "\t; ");
5762 info->print_address_func (((pc + 4) & ~3) + offset, info);
5763 }
5764 }
5765 skip:
5766 break;
5767
5768 case 'A':
5769 {
c1e26897
NC		 5770 unsigned int U = ! NEGATIVE_BIT_SET;
5771 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5772 unsigned int Rn = (given & 0x000f0000) >> 16;
5773 unsigned int off = (given & 0x000000ff);
5774
5775 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5776
5777 if (PRE_BIT_SET)
c19d1205
ZW		 5778 {
5779 if (off || !U)
05413229
NC		 5780 {
5781 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5782 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5783 }
c19d1205
ZW		 5784 func (stream, "]");
5785 if (W)
5786 func (stream, "!");
5787 }
5788 else
5789 {
5790 func (stream, "], ");
5791 if (W)
05413229
NC		 5792 {
5793 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5794 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5795 }
c19d1205 5796 else
fe56b6ce
NC		 5797 {
5798 func (stream, "{%u}", off);
5799 value_in_comment = off;
5800 }
c19d1205
ZW		 5801 }
5802 }
5803 break;
5804
5805 case 'w':
5806 {
5807 unsigned int Sbit = (given & 0x01000000) >> 24;
5808 unsigned int type = (given & 0x00600000) >> 21;
05413229 5809
c19d1205
ZW		 5810 switch (type)
5811 {
5812 case 0: func (stream, Sbit ? "sb" : "b"); break;
5813 case 1: func (stream, Sbit ? "sh" : "h"); break;
5814 case 2:
5815 if (Sbit)
5816 func (stream, "??");
5817 break;
5818 case 3:
5819 func (stream, "??");
5820 break;
5821 }
5822 }
5823 break;
5824
5825 case 'm':
5826 {
5827 int started = 0;
5828 int reg;
5829
5830 func (stream, "{");
5831 for (reg = 0; reg < 16; reg++)
5832 if ((given & (1 << reg)) != 0)
5833 {
5834 if (started)
5835 func (stream, ", ");
5836 started = 1;
5837 func (stream, "%s", arm_regnames[reg]);
5838 }
5839 func (stream, "}");
5840 }
5841 break;
5842
5843 case 'E':
5844 {
5845 unsigned int msb = (given & 0x0000001f);
5846 unsigned int lsb = 0;
fe56b6ce 5847
c19d1205
ZW		 5848 lsb |= (given & 0x000000c0u) >> 6;
5849 lsb |= (given & 0x00007000u) >> 10;
5850 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5851 }
5852 break;
5853
5854 case 'F':
5855 {
5856 unsigned int width = (given & 0x0000001f) + 1;
5857 unsigned int lsb = 0;
fe56b6ce 5858
c19d1205
ZW		 5859 lsb |= (given & 0x000000c0u) >> 6;
5860 lsb |= (given & 0x00007000u) >> 10;
5861 func (stream, "#%u, #%u", lsb, width);
5862 }
5863 break;
5864
5865 case 'b':
5866 {
5867 unsigned int S = (given & 0x04000000u) >> 26;
5868 unsigned int J1 = (given & 0x00002000u) >> 13;
5869 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5870 bfd_vma offset = 0;
c19d1205
ZW		 5871
5872 offset |= !S << 20;
5873 offset |= J2 << 19;
5874 offset |= J1 << 18;
5875 offset |= (given & 0x003f0000) >> 4;
5876 offset |= (given & 0x000007ff) << 1;
5877 offset -= (1 << 20);
5878
5879 info->print_address_func (pc + 4 + offset, info);
5880 }
5881 break;
5882
5883 case 'B':
5884 {
5885 unsigned int S = (given & 0x04000000u) >> 26;
5886 unsigned int I1 = (given & 0x00002000u) >> 13;
5887 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5888 bfd_vma offset = 0;
c19d1205
ZW		 5889
5890 offset |= !S << 24;
5891 offset |= !(I1 ^ S) << 23;
5892 offset |= !(I2 ^ S) << 22;
5893 offset |= (given & 0x03ff0000u) >> 4;
5894 offset |= (given & 0x000007ffu) << 1;
5895 offset -= (1 << 24);
36b0c57d 5896 offset += pc + 4;
c19d1205 5897
36b0c57d
PB		 5898 /* BLX target addresses are always word aligned. */
5899 if ((given & 0x00001000u) == 0)
5900 offset &= ~2u;
5901
5902 info->print_address_func (offset, info);
c19d1205
ZW		 5903 }
5904 break;
5905
5906 case 's':
5907 {
5908 unsigned int shift = 0;
fe56b6ce 5909
c19d1205
ZW		 5910 shift |= (given & 0x000000c0u) >> 6;
5911 shift |= (given & 0x00007000u) >> 10;
c1e26897 5912 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5913 func (stream, ", asr #%u", shift);
5914 else if (shift)
5915 func (stream, ", lsl #%u", shift);
5916 /* else print nothing - lsl #0 */
5917 }
5918 break;
5919
5920 case 'R':
5921 {
5922 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5923
c19d1205
ZW		 5924 if (rot)
5925 func (stream, ", ror #%u", rot * 8);
5926 }
5927 break;
5928
62b3e311 5929 case 'U':
43e65147 5930 if ((given & 0xf0) == 0x60)
62b3e311 5931 {
52e7f43d
RE		 5932 switch (given & 0xf)
5933 {
5934 case 0xf: func (stream, "sy"); break;
5935 default:
5936 func (stream, "#%d", (int) given & 0xf);
5937 break;
5938 }
62b3e311 5939 }
43e65147 5940 else
52e7f43d 5941 {
e797f7e0
MGD		 5942 const char * opt = data_barrier_option (given & 0xf);
5943 if (opt != NULL)
5944 func (stream, "%s", opt);
5945 else
5946 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5947 }
62b3e311
PB		 5948 break;
5949
5950 case 'C':
5951 if ((given & 0xff) == 0)
5952 {
5953 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5954 if (given & 0x800)
5955 func (stream, "f");
5956 if (given & 0x400)
5957 func (stream, "s");
5958 if (given & 0x200)
5959 func (stream, "x");
5960 if (given & 0x100)
5961 func (stream, "c");
5962 }
90ec0d68
MGD		 5963 else if ((given & 0x20) == 0x20)
5964 {
5965 char const* name;
5966 unsigned sysm = (given & 0xf00) >> 8;
5967
5968 sysm |= (given & 0x30);
5969 sysm |= (given & 0x00100000) >> 14;
5970 name = banked_regname (sysm);
43e65147 5971
90ec0d68
MGD		 5972 if (name != NULL)
5973 func (stream, "%s", name);
5974 else
d908c8af 5975 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5976 }
62b3e311
PB		 5977 else
5978 {
d908c8af 5979 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5980 }
5981 break;
5982
5983 case 'D':
90ec0d68
MGD		 5984 if (((given & 0xff) == 0)
5985 || ((given & 0x20) == 0x20))
5986 {
5987 char const* name;
5988 unsigned sm = (given & 0xf0000) >> 16;
5989
5990 sm |= (given & 0x30);
5991 sm |= (given & 0x00100000) >> 14;
5992 name = banked_regname (sm);
5993
5994 if (name != NULL)
5995 func (stream, "%s", name);
5996 else
d908c8af 5997 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5998 }
62b3e311 5999 else
d908c8af 6000 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6001 break;
6002
c19d1205
ZW		 6003 case '0': case '1': case '2': case '3': case '4':
6004 case '5': case '6': case '7': case '8': case '9':
6005 {
16980d0b
JB		 6006 int width;
6007 unsigned long val;
c19d1205 6008
16980d0b 6009 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6010
c19d1205
ZW		 6011 switch (*c)
6012 {
05413229
NC		 6013 case 'd':
6014 func (stream, "%lu", val);
6015 value_in_comment = val;
6016 break;
ff4a8d2b 6017
f0fba320
RL		 6018 case 'D':
6019 func (stream, "%lu", val + 1);
6020 value_in_comment = val + 1;
6021 break;
6022
05413229
NC		 6023 case 'W':
6024 func (stream, "%lu", val * 4);
6025 value_in_comment = val * 4;
6026 break;
ff4a8d2b
NC		 6027
6028 case 'R':
6029 if (val == 15)
6030 is_unpredictable = TRUE;
6031 /* Fall through. */
6032 case 'r':
6033 func (stream, "%s", arm_regnames[val]);
6034 break;
c19d1205
ZW		 6035
6036 case 'c':
c22aaad1 6037 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6038 break;
6039
6040 case '\'':
c19d1205 6041 c++;
16980d0b
JB		 6042 if (val == ((1ul << width) - 1))
6043 func (stream, "%c", *c);
c19d1205 6044 break;
43e65147 6045
c19d1205 6046 case '`':
c19d1205 6047 c++;
16980d0b
JB		 6048 if (val == 0)
6049 func (stream, "%c", *c);
c19d1205
ZW		 6050 break;
6051
6052 case '?':
fe56b6ce 6053 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6054 c += 1 << width;
c19d1205 6055 break;
43e65147 6056
0bb027fd
RR		 6057 case 'x':
6058 func (stream, "0x%lx", val & 0xffffffffUL);
6059 break;
c19d1205
ZW		 6060
6061 default:
6062 abort ();
6063 }
6064 }
6065 break;
6066
32a94698
NC		 6067 case 'L':
6068 /* PR binutils/12534
6069 If we have a PC relative offset in an LDRD or STRD
6070 instructions then display the decoded address. */
6071 if (((given >> 16) & 0xf) == 0xf)
6072 {
6073 bfd_vma offset = (given & 0xff) * 4;
6074
6075 if ((given & (1 << 23)) == 0)
6076 offset = - offset;
6077 func (stream, "\t; ");
6078 info->print_address_func ((pc & ~3) + 4 + offset, info);
6079 }
6080 break;
6081
c19d1205
ZW		 6082 default:
6083 abort ();
6084 }
6085 }
05413229
NC		 6086
6087 if (value_in_comment > 32 || value_in_comment < -16)
6088 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6089
6090 if (is_unpredictable)
6091 func (stream, UNPREDICTABLE_INSTRUCTION);
6092
4a5329c6 6093 return;
c19d1205 6094 }
252b5132 6095
58efb6c0 6096 /* No match. */
0b347048
TC		 6097 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6098 return;
252b5132
RH		 6099}
6100
e821645d
DJ		 6101/* Print data bytes on INFO->STREAM. */
6102
6103static void
fe56b6ce
NC		 6104print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6105 struct disassemble_info *info,
e821645d
DJ		 6106 long given)
6107{
6108 switch (info->bytes_per_chunk)
6109 {
6110 case 1:
6111 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6112 break;
6113 case 2:
6114 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6115 break;
6116 case 4:
6117 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6118 break;
6119 default:
6120 abort ();
6121 }
6122}
6123
22a398e1 6124/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6125 being displayed in symbol relative addresses.
6126
6127 Also disallow private symbol, with __tagsym$$ prefix,
6128 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6129
6130bfd_boolean
6131arm_symbol_is_valid (asymbol * sym,
6132 struct disassemble_info * info ATTRIBUTE_UNUSED)
6133{
6134 const char * name;
43e65147 6135
22a398e1
NC		 6136 if (sym == NULL)
6137 return FALSE;
6138
6139 name = bfd_asymbol_name (sym);
6140
d8282f0e 6141 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6142}
6143
65b48a81 6144/* Parse the string of disassembler options. */
baf0cc5e 6145
65b48a81 6146static void
f995bbe8 6147parse_arm_disassembler_options (const char *options)
dd92f639 6148{
f995bbe8 6149 const char *opt;
b34976b6 6150
65b48a81 6151 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6152 {
65b48a81
PB		 6153 if (CONST_STRNEQ (opt, "reg-names-"))
6154 {
6155 unsigned int i;
6156 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6157 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6158 {
6159 regname_selected = i;
6160 break;
6161 }
b34976b6 6162
65b48a81 6163 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6164 /* xgettext: c-format */
6165 opcodes_error_handler (_("unrecognised register name set: %s"),
6166 opt);
65b48a81
PB		 6167 }
6168 else if (CONST_STRNEQ (opt, "force-thumb"))
6169 force_thumb = 1;
6170 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6171 force_thumb = 0;
6172 else
a6743a54
AM		 6173 /* xgettext: c-format */
6174 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6175 }
b34976b6 6176
dd92f639
NC		 6177 return;
6178}
6179
5bc5ae88
RL		 6180static bfd_boolean
6181mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6182 enum map_type *map_symbol);
6183
c22aaad1
PB		 6184/* Search back through the insn stream to determine if this instruction is
6185 conditionally executed. */
fe56b6ce 6186
c22aaad1 6187static void
fe56b6ce
NC		 6188find_ifthen_state (bfd_vma pc,
6189 struct disassemble_info *info,
c22aaad1
PB		 6190 bfd_boolean little)
6191{
6192 unsigned char b[2];
6193 unsigned int insn;
6194 int status;
6195 /* COUNT is twice the number of instructions seen. It will be odd if we
6196 just crossed an instruction boundary. */
6197 int count;
6198 int it_count;
6199 unsigned int seen_it;
6200 bfd_vma addr;
6201
6202 ifthen_address = pc;
6203 ifthen_state = 0;
6204
6205 addr = pc;
6206 count = 1;
6207 it_count = 0;
6208 seen_it = 0;
6209 /* Scan backwards looking for IT instructions, keeping track of where
6210 instruction boundaries are. We don't know if something is actually an
6211 IT instruction until we find a definite instruction boundary. */
6212 for (;;)
6213 {
fe56b6ce 6214 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6215 {
6216 /* A symbol must be on an instruction boundary, and will not
6217 be within an IT block. */
6218 if (seen_it && (count & 1))
6219 break;
6220
6221 return;
6222 }
6223 addr -= 2;
fe56b6ce 6224 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6225 if (status)
6226 return;
6227
6228 if (little)
6229 insn = (b[0]) | (b[1] << 8);
6230 else
6231 insn = (b[1]) | (b[0] << 8);
6232 if (seen_it)
6233 {
6234 if ((insn & 0xf800) < 0xe800)
6235 {
6236 /* Addr + 2 is an instruction boundary. See if this matches
6237 the expected boundary based on the position of the last
6238 IT candidate. */
6239 if (count & 1)
6240 break;
6241 seen_it = 0;
6242 }
6243 }
6244 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6245 {
5bc5ae88
RL		 6246 enum map_type type = MAP_ARM;
6247 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6248
6249 if (!found || (found && type == MAP_THUMB))
6250 {
6251 /* This could be an IT instruction. */
6252 seen_it = insn;
6253 it_count = count >> 1;
6254 }
c22aaad1
PB		 6255 }
6256 if ((insn & 0xf800) >= 0xe800)
6257 count++;
6258 else
6259 count = (count + 2) | 1;
6260 /* IT blocks contain at most 4 instructions. */
6261 if (count >= 8 && !seen_it)
6262 return;
6263 }
6264 /* We found an IT instruction. */
6265 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6266 if ((ifthen_state & 0xf) == 0)
6267 ifthen_state = 0;
6268}
6269
b0e28b39
DJ		 6270/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6271 mapping symbol. */
6272
6273static int
6274is_mapping_symbol (struct disassemble_info *info, int n,
6275 enum map_type *map_type)
6276{
6277 const char *name;
6278
6279 name = bfd_asymbol_name (info->symtab[n]);
6280 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6281 && (name[2] == 0 || name[2] == '.'))
6282 {
6283 *map_type = ((name[1] == 'a') ? MAP_ARM
6284 : (name[1] == 't') ? MAP_THUMB
6285 : MAP_DATA);
6286 return TRUE;
6287 }
6288
6289 return FALSE;
6290}
6291
6292/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6293 Returns nonzero if *MAP_TYPE was set. */
6294
6295static int
6296get_map_sym_type (struct disassemble_info *info,
6297 int n,
6298 enum map_type *map_type)
6299{
6300 /* If the symbol is in a different section, ignore it. */
6301 if (info->section != NULL && info->section != info->symtab[n]->section)
6302 return FALSE;
6303
6304 return is_mapping_symbol (info, n, map_type);
6305}
6306
6307/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6308 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6309
6310static int
fe56b6ce
NC		 6311get_sym_code_type (struct disassemble_info *info,
6312 int n,
e821645d 6313 enum map_type *map_type)
2087ad84
PB		 6314{
6315 elf_symbol_type *es;
6316 unsigned int type;
b0e28b39
DJ		 6317
6318 /* If the symbol is in a different section, ignore it. */
6319 if (info->section != NULL && info->section != info->symtab[n]->section)
6320 return FALSE;
2087ad84 6321
e821645d 6322 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6323 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6324
6325 /* If the symbol has function type then use that. */
34e77a92 6326 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6327 {
39d911fc
TP		 6328 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6329 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6330 *map_type = MAP_THUMB;
6331 else
6332 *map_type = MAP_ARM;
2087ad84
PB		 6333 return TRUE;
6334 }
6335
2087ad84
PB		 6336 return FALSE;
6337}
6338
5bc5ae88
RL		 6339/* Search the mapping symbol state for instruction at pc. This is only
6340 applicable for elf target.
6341
6342 There is an assumption Here, info->private_data contains the correct AND
6343 up-to-date information about current scan process. The information will be
6344 used to speed this search process.
6345
6346 Return TRUE if the mapping state can be determined, and map_symbol
6347 will be updated accordingly. Otherwise, return FALSE. */
6348
6349static bfd_boolean
6350mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6351 enum map_type *map_symbol)
6352{
796d6298
TC		 6353 bfd_vma addr, section_vma = 0;
6354 int n, last_sym = -1;
5bc5ae88 6355 bfd_boolean found = FALSE;
796d6298
TC		 6356 bfd_boolean can_use_search_opt_p = FALSE;
6357
6358 /* Default to DATA. A text section is required by the ABI to contain an
6359 INSN mapping symbol at the start. A data section has no such
6360 requirement, hence if no mapping symbol is found the section must
6361 contain only data. This however isn't very useful if the user has
6362 fully stripped the binaries. If this is the case use the section
6363 attributes to determine the default. If we have no section default to
6364 INSN as well, as we may be disassembling some raw bytes on a baremetal
6365 HEX file or similar. */
6366 enum map_type type = MAP_DATA;
6367 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6368 type = MAP_ARM;
5bc5ae88
RL		 6369 struct arm_private_data *private_data;
6370
796d6298 6371 if (info->private_data == NULL
5bc5ae88
RL		 6372 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6373 return FALSE;
6374
6375 private_data = info->private_data;
5bc5ae88 6376
796d6298
TC		 6377 /* First, look for mapping symbols. */
6378 if (info->symtab_size != 0)
6379 {
6380 if (pc <= private_data->last_mapping_addr)
6381 private_data->last_mapping_sym = -1;
6382
6383 /* Start scanning at the start of the function, or wherever
6384 we finished last time. */
6385 n = info->symtab_pos + 1;
6386
6387 /* If the last stop offset is different from the current one it means we
6388 are disassembling a different glob of bytes. As such the optimization
6389 would not be safe and we should start over. */
6390 can_use_search_opt_p
6391 = private_data->last_mapping_sym >= 0
6392 && info->stop_offset == private_data->last_stop_offset;
6393
6394 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6395 n = private_data->last_mapping_sym;
6396
6397 /* Look down while we haven't passed the location being disassembled.
6398 The reason for this is that there's no defined order between a symbol
6399 and an mapping symbol that may be at the same address. We may have to
6400 look at least one position ahead. */
6401 for (; n < info->symtab_size; n++)
6402 {
6403 addr = bfd_asymbol_value (info->symtab[n]);
6404 if (addr > pc)
6405 break;
6406 if (get_map_sym_type (info, n, &type))
6407 {
6408 last_sym = n;
6409 found = TRUE;
6410 }
6411 }
5bc5ae88 6412
796d6298
TC		 6413 if (!found)
6414 {
6415 n = info->symtab_pos;
6416 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6417 n = private_data->last_mapping_sym;
6418
6419 /* No mapping symbol found at this address. Look backwards
6420 for a preceeding one, but don't go pass the section start
6421 otherwise a data section with no mapping symbol can pick up
6422 a text mapping symbol of a preceeding section. The documentation
6423 says section can be NULL, in which case we will seek up all the
6424 way to the top. */
6425 if (info->section)
6426 section_vma = info->section->vma;
6427
6428 for (; n >= 0; n--)
6429 {
6430 addr = bfd_asymbol_value (info->symtab[n]);
6431 if (addr < section_vma)
6432 break;
6433
6434 if (get_map_sym_type (info, n, &type))
6435 {
6436 last_sym = n;
6437 found = TRUE;
6438 break;
6439 }
6440 }
6441 }
6442 }
6443
6444 /* If no mapping symbol was found, try looking up without a mapping
6445 symbol. This is done by walking up from the current PC to the nearest
6446 symbol. We don't actually have to loop here since symtab_pos will
6447 contain the nearest symbol already. */
6448 if (!found)
5bc5ae88 6449 {
796d6298
TC		 6450 n = info->symtab_pos;
6451 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 6452 {
796d6298
TC		 6453 last_sym = n;
6454 found = TRUE;
5bc5ae88
RL		 6455 }
6456 }
6457
796d6298
TC		 6458 private_data->last_mapping_sym = last_sym;
6459 private_data->last_type = type;
6460 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 6461
6462 *map_symbol = type;
6463 return found;
6464}
6465
0313a2b8
NC		 6466/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6467 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6468 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6469
6470 FIXME: This could more efficiently implemented as a constant array,
6471 although it would also be less robust. */
6472
6473static void
6474select_arm_features (unsigned long mach,
6475 arm_feature_set * features)
6476{
c0c468d5
TP		 6477 arm_feature_set arch_fset;
6478 const arm_feature_set fpu_any = FPU_ANY;
6479
1af1dd51
MW		 6480#undef ARM_SET_FEATURES
6481#define ARM_SET_FEATURES(FSET) \
6482 { \
6483 const arm_feature_set fset = FSET; \
c0c468d5 6484 arch_fset = fset; \
1af1dd51 6485 }
823d2571 6486
c0c468d5
TP		 6487 /* When several architecture versions share the same bfd_mach_arm_XXX value
6488 the most featureful is chosen. */
0313a2b8
NC		 6489 switch (mach)
6490 {
c0c468d5
TP		 6491 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6492 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6493 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6494 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6495 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6496 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6497 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6498 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6499 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6500 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6501 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6502 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6503 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 6504 break;
c0c468d5
TP		 6505 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6506 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6507 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6508 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
6509 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6510 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6511 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6512 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6513 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6514 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6515 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6516 case bfd_mach_arm_8:
6517 {
0632eeea
SD		 6518 /* Add bits for extensions that Armv8.5-A recognizes. */
6519 arm_feature_set armv8_5_ext_fset
6520 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6521 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6522 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 6523 break;
6524 }
6525 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6526 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6527 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6528 /* If the machine type is unknown allow all architecture types and all
6529 extensions. */
6530 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6531 default:
6532 abort ();
6533 }
1af1dd51 6534#undef ARM_SET_FEATURES
c0c468d5
TP		 6535
6536 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6537 and thus on bfd_mach_arm_XXX value. Therefore for a given
6538 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6539 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 6540}
6541
6542
58efb6c0
NC		 6543/* NOTE: There are no checks in these routines that
6544 the relevant number of data bytes exist. */
baf0cc5e 6545
58efb6c0 6546static int
4a5329c6 6547print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6548{
c19d1205
ZW		 6549 unsigned char b[4];
6550 long given;
6551 int status;
e821645d 6552 int is_thumb = FALSE;
b0e28b39 6553 int is_data = FALSE;
bd2e2557 6554 int little_code;
e821645d 6555 unsigned int size = 4;
4a5329c6 6556 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6557 bfd_boolean found = FALSE;
b0e28b39 6558 struct arm_private_data *private_data;
58efb6c0 6559
dd92f639
NC		 6560 if (info->disassembler_options)
6561 {
65b48a81 6562 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6563
58efb6c0 6564 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6565 info->disassembler_options = NULL;
6566 }
b34976b6 6567
0313a2b8
NC		 6568 /* PR 10288: Control which instructions will be disassembled. */
6569 if (info->private_data == NULL)
6570 {
b0e28b39 6571 static struct arm_private_data private;
0313a2b8
NC		 6572
6573 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6574 /* If the user did not use the -m command line switch then default to
6575 disassembling all types of ARM instruction.
43e65147 6576
0313a2b8
NC		 6577 The info->mach value has to be ignored as this will be based on
6578 the default archictecture for the target and/or hints in the notes
6579 section, but it will never be greater than the current largest arm
6580 machine value (iWMMXt2), which is only equivalent to the V5TE
6581 architecture. ARM architectures have advanced beyond the machine
6582 value encoding, and these newer architectures would be ignored if
6583 the machine value was used.
6584
6585 Ie the -m switch is used to restrict which instructions will be
6586 disassembled. If it is necessary to use the -m switch to tell
6587 objdump that an ARM binary is being disassembled, eg because the
6588 input is a raw binary file, but it is also desired to disassemble
6589 all ARM instructions then use "-marm". This will select the
6590 "unknown" arm architecture which is compatible with any ARM
6591 instruction. */
6592 info->mach = bfd_mach_arm_unknown;
6593
6594 /* Compute the architecture bitmask from the machine number.
6595 Note: This assumes that the machine number will not change
6596 during disassembly.... */
b0e28b39 6597 select_arm_features (info->mach, & private.features);
0313a2b8 6598
1fbaefec
PB		 6599 private.last_mapping_sym = -1;
6600 private.last_mapping_addr = 0;
796d6298 6601 private.last_stop_offset = 0;
b0e28b39
DJ		 6602
6603 info->private_data = & private;
0313a2b8 6604 }
b0e28b39
DJ		 6605
6606 private_data = info->private_data;
6607
bd2e2557
SS		 6608 /* Decide if our code is going to be little-endian, despite what the
6609 function argument might say. */
6610 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6611
b0e28b39
DJ		 6612 /* For ELF, consult the symbol table to determine what kind of code
6613 or data we have. */
8977d4b2 6614 if (info->symtab_size != 0
e821645d
DJ		 6615 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6616 {
6617 bfd_vma addr;
796d6298 6618 int n;
e821645d 6619 int last_sym = -1;
b0e28b39 6620 enum map_type type = MAP_ARM;
e821645d 6621
796d6298
TC		 6622 found = mapping_symbol_for_insn (pc, info, &type);
6623 last_sym = private_data->last_mapping_sym;
e821645d 6624
1fbaefec
PB		 6625 is_thumb = (private_data->last_type == MAP_THUMB);
6626 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6627
e821645d
DJ		 6628 /* Look a little bit ahead to see if we should print out
6629 two or four bytes of data. If there's a symbol,
6630 mapping or otherwise, after two bytes then don't
6631 print more. */
6632 if (is_data)
6633 {
6634 size = 4 - (pc & 3);
6635 for (n = last_sym + 1; n < info->symtab_size; n++)
6636 {
6637 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6638 if (addr > pc
6639 && (info->section == NULL
6640 || info->section == info->symtab[n]->section))
e821645d
DJ		 6641 {
6642 if (addr - pc < size)
6643 size = addr - pc;
6644 break;
6645 }
6646 }
6647 /* If the next symbol is after three bytes, we need to
6648 print only part of the data, so that we can use either
6649 .byte or .short. */
6650 if (size == 3)
6651 size = (pc & 1) ? 1 : 2;
6652 }
6653 }
6654
6655 if (info->symbols != NULL)
252b5132 6656 {
5876e06d
NC		 6657 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6658 {
2f0ca46a 6659 coff_symbol_type * cs;
b34976b6 6660
5876e06d
NC		 6661 cs = coffsymbol (*info->symbols);
6662 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6663 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6664 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6665 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6666 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6667 }
e821645d
DJ		 6668 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6669 && !found)
5876e06d 6670 {
2087ad84
PB		 6671 /* If no mapping symbol has been found then fall back to the type
6672 of the function symbol. */
e821645d
DJ		 6673 elf_symbol_type * es;
6674 unsigned int type;
2087ad84 6675
e821645d
DJ		 6676 es = *(elf_symbol_type **)(info->symbols);
6677 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6678
39d911fc
TP		 6679 is_thumb =
6680 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6681 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6682 }
e49d43ff
TG		 6683 else if (bfd_asymbol_flavour (*info->symbols)
6684 == bfd_target_mach_o_flavour)
6685 {
6686 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6687
6688 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6689 }
5876e06d 6690 }
b34976b6 6691
e821645d
DJ		 6692 if (force_thumb)
6693 is_thumb = TRUE;
6694
b8f9ee44
CL		 6695 if (is_data)
6696 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6697 else
6698 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6699
c19d1205 6700 info->bytes_per_line = 4;
252b5132 6701
1316c8b3
NC		 6702 /* PR 10263: Disassemble data if requested to do so by the user. */
6703 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6704 {
6705 int i;
6706
1316c8b3 6707 /* Size was already set above. */
e821645d
DJ		 6708 info->bytes_per_chunk = size;
6709 printer = print_insn_data;
6710
fe56b6ce 6711 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6712 given = 0;
6713 if (little)
6714 for (i = size - 1; i >= 0; i--)
6715 given = b[i] | (given << 8);
6716 else
6717 for (i = 0; i < (int) size; i++)
6718 given = b[i] | (given << 8);
6719 }
6720 else if (!is_thumb)
252b5132 6721 {
c19d1205
ZW		 6722 /* In ARM mode endianness is a straightforward issue: the instruction
6723 is four bytes long and is either ordered 0123 or 3210. */
6724 printer = print_insn_arm;
6725 info->bytes_per_chunk = 4;
4a5329c6 6726 size = 4;
c19d1205 6727
0313a2b8 6728 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6729 if (little_code)
c19d1205
ZW		 6730 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6731 else
6732 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6733 }
58efb6c0 6734 else
252b5132 6735 {
c19d1205
ZW		 6736 /* In Thumb mode we have the additional wrinkle of two
6737 instruction lengths. Fortunately, the bits that determine
6738 the length of the current instruction are always to be found
6739 in the first two bytes. */
4a5329c6 6740 printer = print_insn_thumb16;
c19d1205 6741 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6742 size = 2;
6743
fe56b6ce 6744 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6745 if (little_code)
9a2ff3f5
AM		 6746 given = (b[0]) | (b[1] << 8);
6747 else
6748 given = (b[1]) | (b[0] << 8);
6749
c19d1205 6750 if (!status)
252b5132 6751 {
c19d1205
ZW		 6752 /* These bit patterns signal a four-byte Thumb
6753 instruction. */
6754 if ((given & 0xF800) == 0xF800
6755 || (given & 0xF800) == 0xF000
6756 || (given & 0xF800) == 0xE800)
252b5132 6757 {
0313a2b8 6758 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6759 if (little_code)
c19d1205 6760 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6761 else
c19d1205
ZW		 6762 given = (b[1]) | (b[0] << 8) | (given << 16);
6763
6764 printer = print_insn_thumb32;
4a5329c6 6765 size = 4;
252b5132 6766 }
252b5132 6767 }
c22aaad1
PB		 6768
6769 if (ifthen_address != pc)
0313a2b8 6770 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6771
6772 if (ifthen_state)
6773 {
6774 if ((ifthen_state & 0xf) == 0x8)
6775 ifthen_next_state = 0;
6776 else
6777 ifthen_next_state = (ifthen_state & 0xe0)
6778 | ((ifthen_state & 0xf) << 1);
6779 }
252b5132 6780 }
b34976b6 6781
c19d1205
ZW		 6782 if (status)
6783 {
6784 info->memory_error_func (status, pc, info);
6785 return -1;
6786 }
6a56ec7e
NC		 6787 if (info->flags & INSN_HAS_RELOC)
6788 /* If the instruction has a reloc associated with it, then
6789 the offset field in the instruction will actually be the
6790 addend for the reloc. (We are using REL type relocs).
6791 In such cases, we can ignore the pc when computing
6792 addresses, since the addend is not currently pc-relative. */
6793 pc = 0;
b34976b6 6794
4a5329c6 6795 printer (pc, info, given);
c22aaad1
PB		 6796
6797 if (is_thumb)
6798 {
6799 ifthen_state = ifthen_next_state;
6800 ifthen_address += size;
6801 }
4a5329c6 6802 return size;
252b5132
RH		 6803}
6804
6805int
4a5329c6 6806print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6807{
bd2e2557
SS		 6808 /* Detect BE8-ness and record it in the disassembler info. */
6809 if (info->flavour == bfd_target_elf_flavour
6810 && info->section != NULL
6811 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6812 info->endian_code = BFD_ENDIAN_LITTLE;
6813
b34976b6 6814 return print_insn (pc, info, FALSE);
58efb6c0 6815}
01c7f630 6816
58efb6c0 6817int
4a5329c6 6818print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6819{
b34976b6 6820 return print_insn (pc, info, TRUE);
58efb6c0 6821}
252b5132 6822
471b9d15 6823const disasm_options_and_args_t *
65b48a81
PB		 6824disassembler_options_arm (void)
6825{
471b9d15 6826 static disasm_options_and_args_t *opts_and_args;
65b48a81 6827
471b9d15 6828 if (opts_and_args == NULL)
65b48a81 6829 {
471b9d15 6830 disasm_options_t *opts;
65b48a81 6831 unsigned int i;
471b9d15
MR		 6832
6833 opts_and_args = XNEW (disasm_options_and_args_t);
6834 opts_and_args->args = NULL;
6835
6836 opts = &opts_and_args->options;
65b48a81
PB		 6837 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6838 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 6839 opts->arg = NULL;
65b48a81
PB		 6840 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6841 {
6842 opts->name[i] = regnames[i].name;
6843 if (regnames[i].description != NULL)
6844 opts->description[i] = _(regnames[i].description);
6845 else
6846 opts->description[i] = NULL;
6847 }
6848 /* The array we return must be NULL terminated. */
6849 opts->name[i] = NULL;
6850 opts->description[i] = NULL;
6851 }
6852
471b9d15 6853 return opts_and_args;
65b48a81
PB		 6854}
6855
58efb6c0 6856void
4a5329c6 6857print_arm_disassembler_options (FILE *stream)
58efb6c0 6858{
65b48a81 6859 unsigned int i, max_len = 0;
58efb6c0
NC		 6860 fprintf (stream, _("\n\
6861The following ARM specific disassembler options are supported for use with\n\
6862the -M switch:\n"));
b34976b6 6863
65b48a81
PB		 6864 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6865 {
6866 unsigned int len = strlen (regnames[i].name);
6867 if (max_len < len)
6868 max_len = len;
6869 }
58efb6c0 6870
65b48a81
PB		 6871 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6872 fprintf (stream, " %s%*c %s\n",
6873 regnames[i].name,
6874 (int)(max_len - strlen (regnames[i].name)), ' ',
6875 _(regnames[i].description));
252b5132 6876}
GDB Binutils - Deliverables
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