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[AArch64] Support for ARMv8.1a Adv.SIMD instructions
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
37
6b5d3a4d 38/* FIXME: Belongs in global header. */
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Whether any mapping symbols are present in the provided symbol
61 table. -1 if we do not know yet, otherwise 0 or 1. */
62 int has_mapping_symbols;
1fbaefec
PB		 63
64 /* Track the last type (although this doesn't seem to be useful) */
65 enum map_type last_type;
66
67 /* Tracking symbol table information */
68 int last_mapping_sym;
69 bfd_vma last_mapping_addr;
b0e28b39
DJ		 70};
71
6b5d3a4d
ZW		 72struct opcode32
73{
823d2571
TG		 74 arm_feature_set arch; /* Architecture defining this insn. */
75 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 76 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 77 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 78};
79
80struct opcode16
81{
823d2571 82 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 83 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 84 const char *assembler; /* How to disassemble this insn. */
85};
b7693d02 86
8f06b2d8 87/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 88
2fbad815 89 %% %
4a5329c6 90
c22aaad1 91 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 92 %q print shifter argument
e2efe87d
MGD		 93 %u print condition code (unconditional in ARM mode,
94 UNPREDICTABLE if not AL in Thumb)
4a5329c6 95 %A print address for ldc/stc/ldf/stf instruction
16980d0b 96 %B print vstm/vldm register list
4a5329c6 97 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 98 %F print the COUNT field of a LFM/SFM instruction.
99 %P print floating point precision in arithmetic insn
100 %Q print floating point precision in ldf/stf insn
101 %R print floating point rounding mode
102
33399f07 103 %<bitfield>c print as a condition code (for vsel)
4a5329c6 104 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 105 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
106 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 107 %<bitfield>d print the bitfield in decimal
16980d0b 108 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 109 %<bitfield>x print the bitfield in hex
110 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 111 %<bitfield>f print a floating point constant if >7 else a
112 floating point register
4a5329c6
ZW		 113 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
114 %<bitfield>g print as an iWMMXt 64-bit register
115 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 116 %<bitfield>D print as a NEON D register
117 %<bitfield>Q print as a NEON Q register
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
fe56b6ce 409 /* Register load/store. */
823d2571
TG		 410 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
411 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
427 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
442
443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
444 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 451
fe56b6ce 452 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
454 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 481 /* Half-precision conversion instructions. */
823d2571
TG		 482 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
483 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
487 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 490
fe56b6ce 491 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
493 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
523 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
537 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
543 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
551 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
563 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
567 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
569 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
571 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
575 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
577 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
579 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
581 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
583 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
585 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
591 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
595 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
599 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
603 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
607 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
611 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
615 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
619 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
623 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
625 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 626
627 /* Cirrus coprocessor instructions. */
823d2571
TG		 628 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
629 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e000600, 0x0ff00f10,
790 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
792 0x0e100600, 0x0ff00f10,
793 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e200600, 0x0ff00f10,
796 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
798 0x0e300600, 0x0ff00f10,
799 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 800
62f3b8c8 801 /* VFP Fused multiply add instructions. */
823d2571
TG		 802 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
803 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 818
33399f07 819 /* FP v5. */
823d2571
TG		 820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
821 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 844
05413229 845 /* Generic coprocessor instructions. */
823d2571
TG		 846 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
848 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c500000, 0x0ff00000,
851 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
853 0x0e000000, 0x0f000010,
854 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
856 0x0e10f010, 0x0f10f010,
857 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
859 0x0e100010, 0x0f100010,
860 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
862 0x0e000010, 0x0f100010,
863 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 868
05413229 869 /* V6 coprocessor instructions. */
823d2571
TG		 870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
871 0xfc500000, 0xfff00000,
872 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
874 0xfc400000, 0xfff00000,
875 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 876
05413229 877 /* V5 coprocessor instructions. */
823d2571
TG		 878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
879 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfe000000, 0xff000010,
884 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
886 0xfe000010, 0xff100010,
887 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
889 0xfe100010, 0xff100010,
890 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
891
892 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 893};
894
16980d0b
JB		 895/* Neon opcode table: This does not encode the top byte -- that is
896 checked by the print_insn_neon routine, as it depends on whether we are
897 doing thumb32 or arm32 disassembly. */
898
899/* print_insn_neon recognizes the following format control codes:
900
901 %% %
902
c22aaad1 903 %c print condition code
e2efe87d
MGD		 904 %u print condition code (unconditional in ARM mode,
905 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 906 %A print v{st,ld}[1234] operands
907 %B print v{st,ld}[1234] any one operands
908 %C print v{st,ld}[1234] single->all operands
909 %D print scalar
910 %E print vmov, vmvn, vorr, vbic encoded constant
911 %F print vtbl,vtbx register list
912
913 %<bitfield>r print as an ARM register
914 %<bitfield>d print the bitfield in decimal
915 %<bitfield>e print the 2^N - bitfield in decimal
916 %<bitfield>D print as a NEON D register
917 %<bitfield>Q print as a NEON Q register
918 %<bitfield>R print as a NEON D or Q register
919 %<bitfield>Sn print byte scaled width limited by n
920 %<bitfield>Tn print short scaled width limited by n
921 %<bitfield>Un print long scaled width limited by n
922
923 %<bitfield>'c print specified char iff bitfield is all ones
924 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 925 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 926
927static const struct opcode32 neon_opcodes[] =
928{
fe56b6ce 929 /* Extract. */
823d2571
TG		 930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
931 0xf2b00840, 0xffb00850,
932 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
934 0xf2b00000, 0xffb00810,
935 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 936
fe56b6ce 937 /* Move data element to all lanes. */
823d2571
TG		 938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
939 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 944
fe56b6ce 945 /* Table lookup. */
823d2571
TG		 946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
947 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
950
8e79c3df 951 /* Half-precision conversions. */
823d2571
TG		 952 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
953 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 956
957 /* NEON fused multiply add instructions. */
823d2571
TG		 958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
959 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 962
fe56b6ce 963 /* Two registers, miscellaneous. */
823d2571
TG		 964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
965 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
969 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
983 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b20300, 0xffb30fd0,
1004 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1006 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b30600, 0xffb30e10,
1049 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1050
fe56b6ce 1051 /* Three registers of the same length. */
823d2571
TG		 1052 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1067 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000b00, 0xff800f10,
1130 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf2000b10, 0xff800f10,
1133 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000b00, 0xff800f10,
1142 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf2000000, 0xfe800f10,
1145 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf2000010, 0xfe800f10,
1148 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf2000100, 0xfe800f10,
1151 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153 0xf2000200, 0xfe800f10,
1154 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf2000210, 0xfe800f10,
1157 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159 0xf2000300, 0xfe800f10,
1160 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf2000310, 0xfe800f10,
1163 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165 0xf2000400, 0xfe800f10,
1166 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf2000410, 0xfe800f10,
1169 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf2000500, 0xfe800f10,
1172 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf2000510, 0xfe800f10,
1175 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177 0xf2000600, 0xfe800f10,
1178 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf2000610, 0xfe800f10,
1181 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183 0xf2000700, 0xfe800f10,
1184 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf2000710, 0xfe800f10,
1187 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189 0xf2000910, 0xfe800f10,
1190 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf2000a00, 0xfe800f10,
1193 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195 0xf2000a10, 0xfe800f10,
1196 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1197
fe56b6ce 1198 /* One register and an immediate value. */
823d2571
TG		 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1225
fe56b6ce 1226 /* Two registers and a shift amount. */
823d2571
TG		 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880950, 0xfeb80fd0,
1239 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf2900950, 0xfeb00fd0,
1262 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2a00950, 0xfea00fd0,
1307 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2a00e10, 0xfea00e90,
1346 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1347
fe56b6ce 1348 /* Three registers of different lengths. */
823d2571
TG		 1349 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1350 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2800400, 0xff800f50,
1355 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2800600, 0xff800f50,
1358 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800900, 0xff800f50,
1361 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2800b00, 0xff800f50,
1364 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2800d00, 0xff800f50,
1367 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf3800400, 0xff800f50,
1370 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf3800600, 0xff800f50,
1373 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2800000, 0xfe800f50,
1376 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2800100, 0xfe800f50,
1379 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2800200, 0xfe800f50,
1382 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2800300, 0xfe800f50,
1385 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2800500, 0xfe800f50,
1388 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf2800700, 0xfe800f50,
1391 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf2800800, 0xfe800f50,
1394 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf2800a00, 0xfe800f50,
1397 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800c00, 0xfe800f50,
1400 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1401
fe56b6ce 1402 /* Two registers and a scalar. */
823d2571
TG		 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2800240, 0xfe800f50,
1443 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2800640, 0xfe800f50,
1446 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2800a40, 0xfe800f50,
1449 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
16980d0b 1450
fe56b6ce 1451 /* Element and structure load/store. */
823d2571
TG		 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1490
1491 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1492};
1493
8f06b2d8
PB		 1494/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1495 ordered: they must be searched linearly from the top to obtain a correct
1496 match. */
1497
1498/* print_insn_arm recognizes the following format control codes:
1499
1500 %% %
1501
1502 %a print address for ldr/str instruction
1503 %s print address for ldr/str halfword/signextend instruction
c1e26897 1504 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1505 %b print branch destination
1506 %c print condition code (always bits 28-31)
1507 %m print register mask for ldm/stm instruction
1508 %o print operand2 (immediate or register + shift)
1509 %p print 'p' iff bits 12-15 are 15
1510 %t print 't' iff bit 21 set and bit 24 clear
1511 %B print arm BLX(1) destination
1512 %C print the PSR sub type.
62b3e311
PB		 1513 %U print barrier type.
1514 %P print address for pli instruction.
8f06b2d8
PB		 1515
1516 %<bitfield>r print as an ARM register
9eb6c0f1 1517 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1518 %<bitfield>R as %r but r15 is UNPREDICTABLE
1519 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1520 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8
PB		 1521 %<bitfield>d print the bitfield in decimal
1522 %<bitfield>W print the bitfield plus one in decimal
1523 %<bitfield>x print the bitfield in hex
1524 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
16980d0b
JB		 1525
1526 %<bitfield>'c print specified char iff bitfield is all ones
1527 %<bitfield>`c print specified char iff bitfield is all zeroes
1528 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1529
8f06b2d8
PB		 1530 %e print arm SMI operand (bits 0..7,8..19).
1531 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1532 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1533 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1534
8f06b2d8
PB		 1535static const struct opcode32 arm_opcodes[] =
1536{
1537 /* ARM instructions. */
823d2571
TG		 1538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1539 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1541 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1542
1543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1544 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1546 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1548 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1550 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1552 0x00800090, 0x0fa000f0,
1553 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1555 0x00a00090, 0x0fa000f0,
1556 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1557
53c4b28b 1558 /* V8 instructions. */
823d2571
TG		 1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1560 0x0320f005, 0x0fffffff, "sevl"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1562 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1564 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1566 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1568 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1570 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1572 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1574 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1576 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1578 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1580 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1582 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1584 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1586 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1588 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1590 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
dd5181d5 1591 /* CRC32 instructions. */
823d2571
TG		 1592 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1593 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1594 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1595 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1596 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1597 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1598 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1599 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1600 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1601 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1602 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1603 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1604
90ec0d68 1605 /* Virtualization Extension instructions. */
823d2571
TG		 1606 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1607 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1608
eea54501 1609 /* Integer Divide Extension instructions. */
823d2571
TG		 1610 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1611 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1612 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1613 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1614
60e5ef9f 1615 /* MP Extension instructions. */
823d2571 1616 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1617
62b3e311 1618 /* V7 instructions. */
823d2571
TG		 1619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
62b3e311 1626
c19d1205 1627 /* ARM V6T2 instructions. */
823d2571
TG		 1628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1629 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1631 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1633 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1635 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1636
1637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1638 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1640 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1641
1642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1643 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1645 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1647 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1649 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1650
f4c65163 1651 /* ARM Security extension instructions. */
823d2571
TG		 1652 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1653 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1654
8f06b2d8 1655 /* ARM V6K instructions. */
823d2571
TG		 1656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1657 0xf57ff01f, 0xffffffff, "clrex"},
1658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1659 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1661 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1663 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1665 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1667 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1669 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1670
8f06b2d8 1671 /* ARM V6K NOP hints. */
823d2571
TG		 1672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1673 0x0320f001, 0x0fffffff, "yield%c"},
1674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1675 0x0320f002, 0x0fffffff, "wfe%c"},
1676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1677 0x0320f003, 0x0fffffff, "wfi%c"},
1678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1679 0x0320f004, 0x0fffffff, "sev%c"},
1680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1681 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1682
fe56b6ce 1683 /* ARM V6 instructions. */
823d2571
TG		 1684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1685 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1687 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1689 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1691 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1693 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1695 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1697 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1699 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1701 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1703 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1705 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1707 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1709 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1711 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1713 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1715 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1717 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1719 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1721 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1723 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1725 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1727 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1729 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1731 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1733 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1735 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1737 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1739 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1741 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1743 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1745 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1747 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1749 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1751 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1753 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1755 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1757 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1759 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1761 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1763 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1765 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1767 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1769 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1771 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1773 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1775 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1777 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1779 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1781 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1783 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1785 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1787 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1789 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1791 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1793 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1795 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1797 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1799 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1801 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1803 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1805 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1807 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1809 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1811 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1813 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1815 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1817 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1819 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1821 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1823 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1825 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1827 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1829 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1831 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1833 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1835 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1837 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1839 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1841 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1843 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1845 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1847 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1849 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1851 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1853 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1855 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1857 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1859 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1861 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1863 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1865 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1867 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1869 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1871 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1873 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1875 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1877 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1879 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1881 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1883 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1885 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1887 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1889 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1891 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1893 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1895 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1897 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1899 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1901 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1903 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1905 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1907 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1909 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1911 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1913 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1915 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1917 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1919 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1928
8f06b2d8 1929 /* V5J instruction. */
823d2571
TG		 1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1931 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1932
8f06b2d8 1933 /* V5 Instructions. */
823d2571
TG		 1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1935 0xe1200070, 0xfff000f0,
1936 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1938 0xfa000000, 0xfe000000, "blx\t%B"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1940 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1942 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1943
1944 /* V5E "El Segundo" Instructions. */
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1946 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1948 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1950 0xf450f000, 0xfc70f000, "pld\t%a"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1952 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1954 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1956 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1958 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1959
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1961 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1963 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1964
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1966 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1968 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1970 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1972 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1973
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1975 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1977 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1982
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1984 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1986 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1987
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1991 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 1996
8f06b2d8 1997 /* ARM Instructions. */
823d2571
TG		 1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1999 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2000
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2002 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2004 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2006 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2008 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2010 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2012 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2013
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2015 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2017 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2019 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2021 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2022
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2024 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2028 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2031
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2038
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2040 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2045
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2047 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2049 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2052
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2054 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2056 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2058 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2059
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2063 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2065 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2066
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2070 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2072 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2073
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2077 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2079 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2080
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2084 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2086 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2087
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2089 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2091 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2093 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2094
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2098 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2100 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2101
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2105 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2107 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
2108
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2112 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2114 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2115
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2117 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2119 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2121 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2122
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2124 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2126 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2128 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2129
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2133 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2135 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2137 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2139 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2144
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2146 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2151
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2153 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2158
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2163
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2165 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2166
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2171
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2173 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2195 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x092d0000, 0x0fff0000, "push%c\t%m"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2210
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2249
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2254
2255 /* The rest. */
823d2571
TG		 2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2258 {ARM_FEATURE_CORE_LOW (0),
2259 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2260};
2261
2262/* print_insn_thumb16 recognizes the following format control codes:
2263
2264 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2265 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2266 %<bitfield>I print bitfield as a signed decimal
2267 (top bit of range being the sign bit)
2268 %N print Thumb register mask (with LR)
2269 %O print Thumb register mask (with PC)
2270 %M print Thumb register mask
2271 %b print CZB's 6-bit unsigned branch destination
2272 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2273 %c print the condition code
2274 %C print the condition code, or "s" if not conditional
2275 %x print warning if conditional an not at end of IT block"
2276 %X print "\t; unpredictable <IT:code>" if conditional
2277 %I print IT instruction suffix and operands
4547cb56 2278 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2279 %<bitfield>r print bitfield as an ARM register
2280 %<bitfield>d print bitfield as a decimal
2281 %<bitfield>H print (bitfield * 2) as a decimal
2282 %<bitfield>W print (bitfield * 4) as a decimal
2283 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2284 %<bitfield>B print Thumb branch destination (signed displacement)
2285 %<bitfield>c print bitfield as a condition code
2286 %<bitnum>'c print specified char iff bit is one
2287 %<bitnum>?ab print a if bit is one else print b. */
2288
2289static const struct opcode16 thumb_opcodes[] =
2290{
2291 /* Thumb instructions. */
2292
53c4b28b 2293 /* ARM V8 instructions. */
823d2571
TG		 2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
53c4b28b 2296
8f06b2d8 2297 /* ARM V6K no-argument instructions. */
823d2571
TG		 2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2304
2305 /* ARM V6T2 instructions. */
823d2571
TG		 2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2309
2310 /* ARM V6. */
823d2571
TG		 2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2322
2323 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2325 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2326 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2328 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2329 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2331 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2332 /* Format 4. */
823d2571
TG		 2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2349 /* format 13 */
823d2571
TG		 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2352 /* format 5 */
823d2571
TG		 2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2357 /* format 14 */
823d2571
TG		 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2360 /* format 2 */
823d2571
TG		 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2362 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2364 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2366 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2368 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2369 /* format 8 */
823d2571
TG		 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2371 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2373 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2375 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2376 /* format 7 */
823d2571
TG		 2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2378 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2380 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2381 /* format 1 */
823d2571
TG		 2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2384 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2387 /* format 3 */
823d2571
TG		 2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2392 /* format 6 */
823d2571
TG		 2393 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2395 0x4800, 0xF800,
2396 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2397 /* format 9 */
823d2571
TG		 2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2399 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2401 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2403 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2406 /* format 10 */
823d2571
TG		 2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2408 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2410 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2411 /* format 11 */
823d2571
TG		 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2413 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2415 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2416 /* format 12 */
823d2571
TG		 2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2418 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2420 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2421 /* format 15 */
823d2571
TG		 2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2424 /* format 17 */
823d2571 2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2426 /* format 16 */
823d2571
TG		 2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2430 /* format 18 */
823d2571 2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2432
2433 /* The E800 .. FFFF range is unconditionally redirected to the
2434 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2435 are processed via that table. Thus, we can never encounter a
2436 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2438 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2439};
2440
2441/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2442 We adopt the convention that hw1 is the high 16 bits of .value and
2443 .mask, hw2 the low 16 bits.
2444
2445 print_insn_thumb32 recognizes the following format control codes:
2446
2447 %% %
2448
2449 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2450 %M print a modified 12-bit immediate (same location)
2451 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2452 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2453 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2454 %S print a possibly-shifted Rm
2455
32a94698 2456 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2457 %a print the address of a plain load/store
2458 %w print the width and signedness of a core load/store
2459 %m print register mask for ldm/stm
2460
2461 %E print the lsb and width fields of a bfc/bfi instruction
2462 %F print the lsb and width fields of a sbfx/ubfx instruction
2463 %b print a conditional branch offset
2464 %B print an unconditional branch offset
2465 %s print the shift field of an SSAT instruction
2466 %R print the rotation field of an SXT instruction
62b3e311
PB		 2467 %U print barrier type.
2468 %P print address for pli instruction.
c22aaad1
PB		 2469 %c print the condition code
2470 %x print warning if conditional an not at end of IT block"
2471 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2472
2473 %<bitfield>d print bitfield in decimal
f0fba320 2474 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2475 %<bitfield>W print bitfield*4 in decimal
2476 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2477 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2478 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2479 %<bitfield>c print bitfield as a condition code
2480
16980d0b
JB		 2481 %<bitfield>'c print specified char iff bitfield is all ones
2482 %<bitfield>`c print specified char iff bitfield is all zeroes
2483 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2484
2485 With one exception at the bottom (done because BL and BLX(1) need
2486 to come dead last), this table was machine-sorted first in
2487 decreasing order of number of bits set in the mask, then in
2488 increasing numeric order of mask, then in increasing numeric order
2489 of opcode. This order is not the clearest for a human reader, but
2490 is guaranteed never to catch a special-case bit pattern with a more
2491 general mask, which is important, because this instruction encoding
2492 makes heavy use of special-case bit patterns. */
2493static const struct opcode32 thumb32_opcodes[] =
2494{
53c4b28b 2495 /* V8 instructions. */
823d2571
TG		 2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2497 0xf3af8005, 0xffffffff, "sevl%c.w"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2499 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2501 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2503 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2505 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2507 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2509 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2511 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2513 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2515 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2517 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2519 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2521 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2523 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2525 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2527 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2528
dd5181d5 2529 /* CRC32 instructions. */
823d2571
TG		 2530 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2531 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2532 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2533 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2534 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2535 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2536 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2537 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2538 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2539 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2540 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2541 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2542
62b3e311 2543 /* V7 instructions. */
823d2571
TG		 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2552 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2554 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2555
90ec0d68 2556 /* Virtualization Extension instructions. */
823d2571 2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2558 /* We skip ERET as that is SUBS pc, lr, #0. */
2559
60e5ef9f 2560 /* MP Extension instructions. */
823d2571 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2562
f4c65163 2563 /* Security extension instructions. */
823d2571 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2565
8f06b2d8 2566 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2573 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2575
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2577 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2579 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2581 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2583 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2585 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2587 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2589 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2591 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2593 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2595 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2597 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2599 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2601 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2603 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2605 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2607 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2609 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2611 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2613 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2615 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2617 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2619 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2623 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2625 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2653 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2655 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2673 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2735 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xf810f000, 0xff70f000, "pld%c\t%a"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfb100000, 0xfff000c0,
2834 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836 0xfbc00080, 0xfff000c0,
2837 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2843 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xe9400000, 0xff500000,
2910 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xe9500000, 0xff500000,
2913 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xe8600000, 0xff700000,
2916 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xe8700000, 0xff700000,
2919 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 2924
2925 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 2934
8f06b2d8 2935 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2937 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2939 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 2940
2941 /* Fallback. */
823d2571
TG		 2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2943 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2944 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 2945};
ff4a8d2b 2946
8f06b2d8
PB		 2947static const char *const arm_conditional[] =
2948{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 2949 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 2950
2951static const char *const arm_fp_const[] =
2952{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2953
2954static const char *const arm_shift[] =
2955{"lsl", "lsr", "asr", "ror"};
2956
2957typedef struct
2958{
2959 const char *name;
2960 const char *description;
2961 const char *reg_names[16];
2962}
2963arm_regname;
2964
2965static const arm_regname regnames[] =
2966{
2967 { "raw" , "Select raw register names",
2968 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
2969 { "gcc", "Select register names used by GCC",
2970 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
2971 { "std", "Select register names used in ARM's ISA documentation",
2972 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
2973 { "apcs", "Select register names used in the APCS",
2974 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
2975 { "atpcs", "Select register names used in the ATPCS",
2976 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
2977 { "special-atpcs", "Select special register names used in the ATPCS",
2978 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
2979};
2980
2981static const char *const iwmmxt_wwnames[] =
2982{"b", "h", "w", "d"};
2983
2984static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 2985{"b", "bus", "bc", "bss",
2986 "h", "hus", "hc", "hss",
2987 "w", "wus", "wc", "wss",
2988 "d", "dus", "dc", "dss"
8f06b2d8
PB		 2989};
2990
2991static const char *const iwmmxt_regnames[] =
2992{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
2993 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
2994};
2995
2996static const char *const iwmmxt_cregnames[] =
2997{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
2998 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
2999};
3000
3001/* Default to GCC register name set. */
3002static unsigned int regname_selected = 1;
3003
3004#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3005#define arm_regnames regnames[regname_selected].reg_names
3006
3007static bfd_boolean force_thumb = FALSE;
3008
c22aaad1
PB		 3009/* Current IT instruction state. This contains the same state as the IT
3010 bits in the CPSR. */
3011static unsigned int ifthen_state;
3012/* IT state for the next instruction. */
3013static unsigned int ifthen_next_state;
3014/* The address of the insn for which the IT state is valid. */
3015static bfd_vma ifthen_address;
3016#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3017/* Indicates that the current Conditional state is unconditional or outside
3018 an IT block. */
3019#define COND_UNCOND 16
c22aaad1 3020
8f06b2d8
PB		 3021\f
3022/* Functions. */
3023int
3024get_arm_regname_num_options (void)
3025{
3026 return NUM_ARM_REGNAMES;
3027}
3028
3029int
3030set_arm_regname_option (int option)
3031{
3032 int old = regname_selected;
3033 regname_selected = option;
3034 return old;
3035}
3036
3037int
fe56b6ce
NC		 3038get_arm_regnames (int option,
3039 const char **setname,
3040 const char **setdescription,
8f06b2d8
PB		 3041 const char *const **register_names)
3042{
3043 *setname = regnames[option].name;
3044 *setdescription = regnames[option].description;
3045 *register_names = regnames[option].reg_names;
3046 return 16;
3047}
3048
16980d0b
JB		 3049/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3050 Returns pointer to following character of the format string and
3051 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3052 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3053
3054static const char *
fe56b6ce
NC		 3055arm_decode_bitfield (const char *ptr,
3056 unsigned long insn,
3057 unsigned long *valuep,
3058 int *widthp)
16980d0b
JB		 3059{
3060 unsigned long value = 0;
3061 int width = 0;
3062
3063 do
3064 {
3065 int start, end;
3066 int bits;
3067
3068 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3069 start = start * 10 + *ptr - '0';
3070 if (*ptr == '-')
3071 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3072 end = end * 10 + *ptr - '0';
3073 else
3074 end = start;
3075 bits = end - start;
3076 if (bits < 0)
3077 abort ();
3078 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3079 width += bits + 1;
3080 }
3081 while (*ptr++ == ',');
3082 *valuep = value;
3083 if (widthp)
3084 *widthp = width;
3085 return ptr - 1;
3086}
3087
8f06b2d8 3088static void
37b37b2d 3089arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3090 bfd_boolean print_shift)
8f06b2d8
PB		 3091{
3092 func (stream, "%s", arm_regnames[given & 0xf]);
3093
3094 if ((given & 0xff0) != 0)
3095 {
3096 if ((given & 0x10) == 0)
3097 {
3098 int amount = (given & 0xf80) >> 7;
3099 int shift = (given & 0x60) >> 5;
3100
3101 if (amount == 0)
3102 {
3103 if (shift == 3)
3104 {
3105 func (stream, ", rrx");
3106 return;
3107 }
3108
3109 amount = 32;
3110 }
3111
37b37b2d
RE		 3112 if (print_shift)
3113 func (stream, ", %s #%d", arm_shift[shift], amount);
3114 else
3115 func (stream, ", #%d", amount);
8f06b2d8 3116 }
74bdfecf 3117 else if ((given & 0x80) == 0x80)
aefd8a40 3118 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3119 else if (print_shift)
8f06b2d8
PB		 3120 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3121 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3122 else
3123 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3124 }
3125}
3126
c1e26897
NC		 3127#define W_BIT 21
3128#define I_BIT 22
3129#define U_BIT 23
3130#define P_BIT 24
3131
3132#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3133#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3134#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3135#define PRE_BIT_SET (given & (1 << P_BIT))
3136
8f06b2d8
PB		 3137/* Print one coprocessor instruction on INFO->STREAM.
3138 Return TRUE if the instuction matched, FALSE if this is not a
3139 recognised coprocessor instruction. */
3140
3141static bfd_boolean
fe56b6ce
NC		 3142print_insn_coprocessor (bfd_vma pc,
3143 struct disassemble_info *info,
3144 long given,
8f06b2d8
PB		 3145 bfd_boolean thumb)
3146{
3147 const struct opcode32 *insn;
3148 void *stream = info->stream;
3149 fprintf_ftype func = info->fprintf_func;
3150 unsigned long mask;
2edcd244 3151 unsigned long value = 0;
c22aaad1 3152 int cond;
823d2571
TG		 3153 struct arm_private_data *private_data = info->private_data;
3154 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3155
3156 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3157
3158 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3159 {
ff4a8d2b
NC		 3160 unsigned long u_reg = 16;
3161 bfd_boolean is_unpredictable = FALSE;
05413229 3162 signed long value_in_comment = 0;
0313a2b8
NC		 3163 const char *c;
3164
823d2571 3165 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3166 switch (insn->value)
3167 {
3168 case SENTINEL_IWMMXT_START:
3169 if (info->mach != bfd_mach_arm_XScale
3170 && info->mach != bfd_mach_arm_iWMMXt
3171 && info->mach != bfd_mach_arm_iWMMXt2)
3172 do
3173 insn++;
823d2571
TG		 3174 while ((! ARM_FEATURE_ZERO (insn->arch))
3175 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3176 continue;
3177
3178 case SENTINEL_IWMMXT_END:
3179 continue;
3180
3181 case SENTINEL_GENERIC_START:
823d2571 3182 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3183 continue;
3184
3185 default:
3186 abort ();
3187 }
8f06b2d8
PB		 3188
3189 mask = insn->mask;
3190 value = insn->value;
3191 if (thumb)
3192 {
3193 /* The high 4 bits are 0xe for Arm conditional instructions, and
3194 0xe for arm unconditional instructions. The rest of the
3195 encoding is the same. */
3196 mask |= 0xf0000000;
3197 value |= 0xe0000000;
c22aaad1
PB		 3198 if (ifthen_state)
3199 cond = IFTHEN_COND;
3200 else
e2efe87d 3201 cond = COND_UNCOND;
8f06b2d8
PB		 3202 }
3203 else
3204 {
3205 /* Only match unconditional instuctions against unconditional
3206 patterns. */
3207 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3208 {
3209 mask |= 0xf0000000;
e2efe87d 3210 cond = COND_UNCOND;
c22aaad1
PB		 3211 }
3212 else
3213 {
3214 cond = (given >> 28) & 0xf;
3215 if (cond == 0xe)
e2efe87d 3216 cond = COND_UNCOND;
c22aaad1 3217 }
8f06b2d8 3218 }
823d2571 3219
0313a2b8
NC		 3220 if ((given & mask) != value)
3221 continue;
8f06b2d8 3222
823d2571 3223 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3224 continue;
3225
3226 for (c = insn->assembler; *c; c++)
3227 {
3228 if (*c == '%')
8f06b2d8 3229 {
0313a2b8 3230 switch (*++c)
8f06b2d8 3231 {
0313a2b8
NC		 3232 case '%':
3233 func (stream, "%%");
3234 break;
3235
3236 case 'A':
05413229 3237 {
79862e45 3238 int rn = (given >> 16) & 0xf;
f8b960bc 3239 bfd_vma offset = given & 0xff;
0313a2b8 3240
05413229 3241 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3242
79862e45
DJ		 3243 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3244 {
3245 /* Not unindexed. The offset is scaled. */
3246 offset = offset * 4;
3247 if (NEGATIVE_BIT_SET)
3248 offset = - offset;
3249 if (rn != 15)
3250 value_in_comment = offset;
3251 }
3252
c1e26897 3253 if (PRE_BIT_SET)
05413229
NC		 3254 {
3255 if (offset)
fe56b6ce 3256 func (stream, ", #%d]%s",
d908c8af 3257 (int) offset,
c1e26897 3258 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3259 else if (NEGATIVE_BIT_SET)
3260 func (stream, ", #-0]");
05413229
NC		 3261 else
3262 func (stream, "]");
3263 }
3264 else
3265 {
0313a2b8 3266 func (stream, "]");
8f06b2d8 3267
c1e26897 3268 if (WRITEBACK_BIT_SET)
05413229
NC		 3269 {
3270 if (offset)
d908c8af 3271 func (stream, ", #%d", (int) offset);
26d97720
NS		 3272 else if (NEGATIVE_BIT_SET)
3273 func (stream, ", #-0");
05413229
NC		 3274 }
3275 else
fe56b6ce 3276 {
26d97720
NS		 3277 func (stream, ", {%s%d}",
3278 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3279 (int) offset);
fe56b6ce
NC		 3280 value_in_comment = offset;
3281 }
05413229 3282 }
79862e45
DJ		 3283 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3284 {
3285 func (stream, "\t; ");
6844b2c2
MGD		 3286 /* For unaligned PCs, apply off-by-alignment
3287 correction. */
3288 info->print_address_func (offset + pc
3289 + info->bytes_per_chunk * 2
3290 - (pc & 3),
3291 info);
79862e45 3292 }
05413229 3293 }
0313a2b8 3294 break;
8f06b2d8 3295
0313a2b8
NC		 3296 case 'B':
3297 {
3298 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3299 int offset = (given >> 1) & 0x3f;
3300
3301 if (offset == 1)
3302 func (stream, "{d%d}", regno);
3303 else if (regno + offset > 32)
3304 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3305 else
3306 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3307 }
3308 break;
8f06b2d8 3309
e2efe87d
MGD		 3310 case 'u':
3311 if (cond != COND_UNCOND)
3312 is_unpredictable = TRUE;
3313
3314 /* Fall through. */
0313a2b8
NC		 3315 case 'c':
3316 func (stream, "%s", arm_conditional[cond]);
3317 break;
8f06b2d8 3318
0313a2b8
NC		 3319 case 'I':
3320 /* Print a Cirrus/DSP shift immediate. */
3321 /* Immediates are 7bit signed ints with bits 0..3 in
3322 bits 0..3 of opcode and bits 4..6 in bits 5..7
3323 of opcode. */
3324 {
3325 int imm;
8f06b2d8 3326
0313a2b8 3327 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3328
0313a2b8
NC		 3329 /* Is ``imm'' a negative number? */
3330 if (imm & 0x40)
3331 imm |= (-1 << 7);
8f06b2d8 3332
0313a2b8
NC		 3333 func (stream, "%d", imm);
3334 }
3335
3336 break;
8f06b2d8 3337
0313a2b8
NC		 3338 case 'F':
3339 switch (given & 0x00408000)
3340 {
3341 case 0:
3342 func (stream, "4");
3343 break;
3344 case 0x8000:
3345 func (stream, "1");
3346 break;
3347 case 0x00400000:
3348 func (stream, "2");
8f06b2d8 3349 break;
0313a2b8
NC		 3350 default:
3351 func (stream, "3");
3352 }
3353 break;
8f06b2d8 3354
0313a2b8
NC		 3355 case 'P':
3356 switch (given & 0x00080080)
3357 {
3358 case 0:
3359 func (stream, "s");
3360 break;
3361 case 0x80:
3362 func (stream, "d");
3363 break;
3364 case 0x00080000:
3365 func (stream, "e");
3366 break;
3367 default:
3368 func (stream, _("<illegal precision>"));
8f06b2d8 3369 break;
0313a2b8
NC		 3370 }
3371 break;
8f06b2d8 3372
0313a2b8
NC		 3373 case 'Q':
3374 switch (given & 0x00408000)
3375 {
3376 case 0:
3377 func (stream, "s");
8f06b2d8 3378 break;
0313a2b8
NC		 3379 case 0x8000:
3380 func (stream, "d");
8f06b2d8 3381 break;
0313a2b8
NC		 3382 case 0x00400000:
3383 func (stream, "e");
3384 break;
3385 default:
3386 func (stream, "p");
8f06b2d8 3387 break;
0313a2b8
NC		 3388 }
3389 break;
8f06b2d8 3390
0313a2b8
NC		 3391 case 'R':
3392 switch (given & 0x60)
3393 {
3394 case 0:
3395 break;
3396 case 0x20:
3397 func (stream, "p");
3398 break;
3399 case 0x40:
3400 func (stream, "m");
3401 break;
3402 default:
3403 func (stream, "z");
3404 break;
3405 }
3406 break;
16980d0b 3407
0313a2b8
NC		 3408 case '0': case '1': case '2': case '3': case '4':
3409 case '5': case '6': case '7': case '8': case '9':
3410 {
3411 int width;
8f06b2d8 3412
0313a2b8 3413 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3414
0313a2b8
NC		 3415 switch (*c)
3416 {
ff4a8d2b
NC		 3417 case 'R':
3418 if (value == 15)
3419 is_unpredictable = TRUE;
3420 /* Fall through. */
0313a2b8 3421 case 'r':
ff4a8d2b
NC		 3422 if (c[1] == 'u')
3423 {
3424 /* Eat the 'u' character. */
3425 ++ c;
3426
3427 if (u_reg == value)
3428 is_unpredictable = TRUE;
3429 u_reg = value;
3430 }
0313a2b8
NC		 3431 func (stream, "%s", arm_regnames[value]);
3432 break;
3433 case 'D':
3434 func (stream, "d%ld", value);
3435 break;
3436 case 'Q':
3437 if (value & 1)
3438 func (stream, "<illegal reg q%ld.5>", value >> 1);
3439 else
3440 func (stream, "q%ld", value >> 1);
3441 break;
3442 case 'd':
3443 func (stream, "%ld", value);
05413229 3444 value_in_comment = value;
0313a2b8
NC		 3445 break;
3446 case 'k':
3447 {
3448 int from = (given & (1 << 7)) ? 32 : 16;
3449 func (stream, "%ld", from - value);
3450 }
3451 break;
8f06b2d8 3452
0313a2b8
NC		 3453 case 'f':
3454 if (value > 7)
3455 func (stream, "#%s", arm_fp_const[value & 7]);
3456 else
3457 func (stream, "f%ld", value);
3458 break;
4146fd53 3459
0313a2b8
NC		 3460 case 'w':
3461 if (width == 2)
3462 func (stream, "%s", iwmmxt_wwnames[value]);
3463 else
3464 func (stream, "%s", iwmmxt_wwssnames[value]);
3465 break;
4146fd53 3466
0313a2b8
NC		 3467 case 'g':
3468 func (stream, "%s", iwmmxt_regnames[value]);
3469 break;
3470 case 'G':
3471 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3472 break;
8f06b2d8 3473
0313a2b8 3474 case 'x':
d1aaab3c 3475 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3476 break;
8f06b2d8 3477
33399f07
MGD		 3478 case 'c':
3479 switch (value)
3480 {
3481 case 0:
3482 func (stream, "eq");
3483 break;
3484
3485 case 1:
3486 func (stream, "vs");
3487 break;
3488
3489 case 2:
3490 func (stream, "ge");
3491 break;
3492
3493 case 3:
3494 func (stream, "gt");
3495 break;
3496
3497 default:
3498 func (stream, "??");
3499 break;
3500 }
3501 break;
3502
0313a2b8
NC		 3503 case '`':
3504 c++;
3505 if (value == 0)
3506 func (stream, "%c", *c);
3507 break;
3508 case '\'':
3509 c++;
3510 if (value == ((1ul << width) - 1))
3511 func (stream, "%c", *c);
3512 break;
3513 case '?':
fe56b6ce 3514 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3515 c += 1 << width;
3516 break;
3517 default:
3518 abort ();
3519 }
3520 break;
8f06b2d8 3521
0313a2b8
NC		 3522 case 'y':
3523 case 'z':
3524 {
3525 int single = *c++ == 'y';
3526 int regno;
3527
3528 switch (*c)
3529 {
3530 case '4': /* Sm pair */
3531 case '0': /* Sm, Dm */
3532 regno = given & 0x0000000f;
3533 if (single)
3534 {
3535 regno <<= 1;
3536 regno += (given >> 5) & 1;
16980d0b 3537 }
0313a2b8
NC		 3538 else
3539 regno += ((given >> 5) & 1) << 4;
3540 break;
8f06b2d8 3541
0313a2b8
NC		 3542 case '1': /* Sd, Dd */
3543 regno = (given >> 12) & 0x0000000f;
3544 if (single)
3545 {
3546 regno <<= 1;
3547 regno += (given >> 22) & 1;
3548 }
3549 else
3550 regno += ((given >> 22) & 1) << 4;
3551 break;
8f06b2d8 3552
0313a2b8
NC		 3553 case '2': /* Sn, Dn */
3554 regno = (given >> 16) & 0x0000000f;
3555 if (single)
8f06b2d8 3556 {
0313a2b8
NC		 3557 regno <<= 1;
3558 regno += (given >> 7) & 1;
8f06b2d8 3559 }
0313a2b8
NC		 3560 else
3561 regno += ((given >> 7) & 1) << 4;
3562 break;
7df76b80 3563
0313a2b8
NC		 3564 case '3': /* List */
3565 func (stream, "{");
3566 regno = (given >> 12) & 0x0000000f;
3567 if (single)
3568 {
3569 regno <<= 1;
3570 regno += (given >> 22) & 1;
3571 }
3572 else
3573 regno += ((given >> 22) & 1) << 4;
3574 break;
a7f8487e 3575
0313a2b8
NC		 3576 default:
3577 abort ();
8f06b2d8 3578 }
a7f8487e 3579
0313a2b8
NC		 3580 func (stream, "%c%d", single ? 's' : 'd', regno);
3581
3582 if (*c == '3')
8f06b2d8 3583 {
0313a2b8 3584 int count = given & 0xff;
a7f8487e 3585
0313a2b8
NC		 3586 if (single == 0)
3587 count >>= 1;
b34976b6 3588
0313a2b8 3589 if (--count)
8f06b2d8 3590 {
0313a2b8
NC		 3591 func (stream, "-%c%d",
3592 single ? 's' : 'd',
3593 regno + count);
8f06b2d8 3594 }
0313a2b8
NC		 3595
3596 func (stream, "}");
8f06b2d8 3597 }
0313a2b8
NC		 3598 else if (*c == '4')
3599 func (stream, ", %c%d", single ? 's' : 'd',
3600 regno + 1);
3601 }
3602 break;
3603
3604 case 'L':
3605 switch (given & 0x00400100)
3606 {
3607 case 0x00000000: func (stream, "b"); break;
3608 case 0x00400000: func (stream, "h"); break;
3609 case 0x00000100: func (stream, "w"); break;
3610 case 0x00400100: func (stream, "d"); break;
3611 default:
8f06b2d8 3612 break;
0313a2b8
NC		 3613 }
3614 break;
b34976b6 3615
0313a2b8
NC		 3616 case 'Z':
3617 {
0313a2b8
NC		 3618 /* given (20, 23) | given (0, 3) */
3619 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3620 func (stream, "%d", (int) value);
0313a2b8
NC		 3621 }
3622 break;
2d447fca 3623
0313a2b8
NC		 3624 case 'l':
3625 /* This is like the 'A' operator, except that if
3626 the width field "M" is zero, then the offset is
3627 *not* multiplied by four. */
3628 {
3629 int offset = given & 0xff;
3630 int multiplier = (given & 0x00000100) ? 4 : 1;
3631
3632 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3633
05413229
NC		 3634 if (multiplier > 1)
3635 {
3636 value_in_comment = offset * multiplier;
c1e26897 3637 if (NEGATIVE_BIT_SET)
05413229
NC		 3638 value_in_comment = - value_in_comment;
3639 }
3640
0313a2b8
NC		 3641 if (offset)
3642 {
c1e26897 3643 if (PRE_BIT_SET)
0313a2b8 3644 func (stream, ", #%s%d]%s",
c1e26897 3645 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3646 offset * multiplier,
c1e26897 3647 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3648 else
3649 func (stream, "], #%s%d",
c1e26897 3650 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3651 offset * multiplier);
2d447fca 3652 }
0313a2b8
NC		 3653 else
3654 func (stream, "]");
3655 }
3656 break;
3657
3658 case 'r':
3659 {
3660 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3661 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3662 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3663 const char *rm = arm_regnames [given & 0xf];
3664 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3665
0313a2b8 3666 switch (puw_bits)
2d447fca 3667 {
0313a2b8
NC		 3668 case 1:
3669 case 3:
3670 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3671 if (imm4)
3672 func (stream, ", lsl #%d", imm4);
3673 break;
3674
3675 case 4:
3676 case 5:
3677 case 6:
3678 case 7:
3679 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3680 if (imm4 > 0)
3681 func (stream, ", lsl #%d", imm4);
3682 func (stream, "]");
3683 if (puw_bits == 5 || puw_bits == 7)
3684 func (stream, "!");
3685 break;
3686
3687 default:
3688 func (stream, "INVALID");
2d447fca 3689 }
0313a2b8
NC		 3690 }
3691 break;
2d447fca 3692
0313a2b8
NC		 3693 case 'i':
3694 {
3695 long imm5;
3696 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3697 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3698 }
0313a2b8
NC		 3699 break;
3700
3701 default:
3702 abort ();
3703 }
252b5132 3704 }
252b5132 3705 }
0313a2b8
NC		 3706 else
3707 func (stream, "%c", *c);
252b5132 3708 }
05413229
NC		 3709
3710 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3711 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3712
ff4a8d2b
NC		 3713 if (is_unpredictable)
3714 func (stream, UNPREDICTABLE_INSTRUCTION);
3715
0313a2b8 3716 return TRUE;
252b5132 3717 }
8f06b2d8 3718 return FALSE;
252b5132
RH		 3719}
3720
05413229
NC		 3721/* Decodes and prints ARM addressing modes. Returns the offset
3722 used in the address, if any, if it is worthwhile printing the
3723 offset as a hexadecimal value in a comment at the end of the
3724 line of disassembly. */
3725
3726static signed long
62b3e311
PB		 3727print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3728{
3729 void *stream = info->stream;
3730 fprintf_ftype func = info->fprintf_func;
f8b960bc 3731 bfd_vma offset = 0;
62b3e311
PB		 3732
3733 if (((given & 0x000f0000) == 0x000f0000)
3734 && ((given & 0x02000000) == 0))
3735 {
05413229 3736 offset = given & 0xfff;
62b3e311
PB		 3737
3738 func (stream, "[pc");
3739
c1e26897 3740 if (PRE_BIT_SET)
62b3e311 3741 {
26d97720
NS		 3742 /* Pre-indexed. Elide offset of positive zero when
3743 non-writeback. */
3744 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3745 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3746
3747 if (NEGATIVE_BIT_SET)
3748 offset = -offset;
62b3e311
PB		 3749
3750 offset += pc + 8;
3751
3752 /* Cope with the possibility of write-back
3753 being used. Probably a very dangerous thing
3754 for the programmer to do, but who are we to
3755 argue ? */
26d97720 3756 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3757 }
c1e26897 3758 else /* Post indexed. */
62b3e311 3759 {
d908c8af 3760 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3761
c1e26897 3762 /* Ie ignore the offset. */
62b3e311
PB		 3763 offset = pc + 8;
3764 }
3765
3766 func (stream, "\t; ");
3767 info->print_address_func (offset, info);
05413229 3768 offset = 0;
62b3e311
PB		 3769 }
3770 else
3771 {
3772 func (stream, "[%s",
3773 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3774
3775 if (PRE_BIT_SET)
62b3e311
PB		 3776 {
3777 if ((given & 0x02000000) == 0)
3778 {
26d97720 3779 /* Elide offset of positive zero when non-writeback. */
05413229 3780 offset = given & 0xfff;
26d97720 3781 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3782 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3783 }
3784 else
3785 {
26d97720 3786 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3787 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3788 }
3789
3790 func (stream, "]%s",
c1e26897 3791 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3792 }
3793 else
3794 {
3795 if ((given & 0x02000000) == 0)
3796 {
26d97720 3797 /* Always show offset. */
05413229 3798 offset = given & 0xfff;
26d97720 3799 func (stream, "], #%s%d",
d908c8af 3800 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3801 }
3802 else
3803 {
3804 func (stream, "], %s",
c1e26897 3805 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3806 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3807 }
3808 }
84919466
MR		 3809 if (NEGATIVE_BIT_SET)
3810 offset = -offset;
62b3e311 3811 }
05413229
NC		 3812
3813 return (signed long) offset;
62b3e311
PB		 3814}
3815
16980d0b
JB		 3816/* Print one neon instruction on INFO->STREAM.
3817 Return TRUE if the instuction matched, FALSE if this is not a
3818 recognised neon instruction. */
3819
3820static bfd_boolean
3821print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3822{
3823 const struct opcode32 *insn;
3824 void *stream = info->stream;
3825 fprintf_ftype func = info->fprintf_func;
3826
3827 if (thumb)
3828 {
3829 if ((given & 0xef000000) == 0xef000000)
3830 {
0313a2b8 3831 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 3832 unsigned long bit28 = given & (1 << 28);
3833
3834 given &= 0x00ffffff;
3835 if (bit28)
3836 given |= 0xf3000000;
3837 else
3838 given |= 0xf2000000;
3839 }
3840 else if ((given & 0xff000000) == 0xf9000000)
3841 given ^= 0xf9000000 ^ 0xf4000000;
3842 else
3843 return FALSE;
3844 }
3845
3846 for (insn = neon_opcodes; insn->assembler; insn++)
3847 {
3848 if ((given & insn->mask) == insn->value)
3849 {
05413229 3850 signed long value_in_comment = 0;
e2efe87d 3851 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 3852 const char *c;
3853
3854 for (c = insn->assembler; *c; c++)
3855 {
3856 if (*c == '%')
3857 {
3858 switch (*++c)
3859 {
3860 case '%':
3861 func (stream, "%%");
3862 break;
3863
e2efe87d
MGD		 3864 case 'u':
3865 if (thumb && ifthen_state)
3866 is_unpredictable = TRUE;
3867
3868 /* Fall through. */
c22aaad1
PB		 3869 case 'c':
3870 if (thumb && ifthen_state)
3871 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3872 break;
3873
16980d0b
JB		 3874 case 'A':
3875 {
3876 static const unsigned char enc[16] =
3877 {
3878 0x4, 0x14, /* st4 0,1 */
3879 0x4, /* st1 2 */
3880 0x4, /* st2 3 */
3881 0x3, /* st3 4 */
3882 0x13, /* st3 5 */
3883 0x3, /* st1 6 */
3884 0x1, /* st1 7 */
3885 0x2, /* st2 8 */
3886 0x12, /* st2 9 */
3887 0x2, /* st1 10 */
3888 0, 0, 0, 0, 0
3889 };
3890 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3891 int rn = ((given >> 16) & 0xf);
3892 int rm = ((given >> 0) & 0xf);
3893 int align = ((given >> 4) & 0x3);
3894 int type = ((given >> 8) & 0xf);
3895 int n = enc[type] & 0xf;
3896 int stride = (enc[type] >> 4) + 1;
3897 int ix;
3898
3899 func (stream, "{");
3900 if (stride > 1)
3901 for (ix = 0; ix != n; ix++)
3902 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3903 else if (n == 1)
3904 func (stream, "d%d", rd);
3905 else
3906 func (stream, "d%d-d%d", rd, rd + n - 1);
3907 func (stream, "}, [%s", arm_regnames[rn]);
3908 if (align)
8e560766 3909 func (stream, " :%d", 32 << align);
16980d0b
JB		 3910 func (stream, "]");
3911 if (rm == 0xd)
3912 func (stream, "!");
3913 else if (rm != 0xf)
3914 func (stream, ", %s", arm_regnames[rm]);
3915 }
3916 break;
3917
3918 case 'B':
3919 {
3920 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3921 int rn = ((given >> 16) & 0xf);
3922 int rm = ((given >> 0) & 0xf);
3923 int idx_align = ((given >> 4) & 0xf);
3924 int align = 0;
3925 int size = ((given >> 10) & 0x3);
3926 int idx = idx_align >> (size + 1);
3927 int length = ((given >> 8) & 3) + 1;
3928 int stride = 1;
3929 int i;
3930
3931 if (length > 1 && size > 0)
3932 stride = (idx_align & (1 << size)) ? 2 : 1;
3933
3934 switch (length)
3935 {
3936 case 1:
3937 {
3938 int amask = (1 << size) - 1;
3939 if ((idx_align & (1 << size)) != 0)
3940 return FALSE;
3941 if (size > 0)
3942 {
3943 if ((idx_align & amask) == amask)
3944 align = 8 << size;
3945 else if ((idx_align & amask) != 0)
3946 return FALSE;
3947 }
3948 }
3949 break;
3950
3951 case 2:
3952 if (size == 2 && (idx_align & 2) != 0)
3953 return FALSE;
3954 align = (idx_align & 1) ? 16 << size : 0;
3955 break;
3956
3957 case 3:
3958 if ((size == 2 && (idx_align & 3) != 0)
3959 || (idx_align & 1) != 0)
3960 return FALSE;
3961 break;
3962
3963 case 4:
3964 if (size == 2)
3965 {
3966 if ((idx_align & 3) == 3)
3967 return FALSE;
3968 align = (idx_align & 3) * 64;
3969 }
3970 else
3971 align = (idx_align & 1) ? 32 << size : 0;
3972 break;
3973
3974 default:
3975 abort ();
3976 }
3977
3978 func (stream, "{");
3979 for (i = 0; i < length; i++)
3980 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
3981 rd + i * stride, idx);
3982 func (stream, "}, [%s", arm_regnames[rn]);
3983 if (align)
8e560766 3984 func (stream, " :%d", align);
16980d0b
JB		 3985 func (stream, "]");
3986 if (rm == 0xd)
3987 func (stream, "!");
3988 else if (rm != 0xf)
3989 func (stream, ", %s", arm_regnames[rm]);
3990 }
3991 break;
3992
3993 case 'C':
3994 {
3995 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3996 int rn = ((given >> 16) & 0xf);
3997 int rm = ((given >> 0) & 0xf);
3998 int align = ((given >> 4) & 0x1);
3999 int size = ((given >> 6) & 0x3);
4000 int type = ((given >> 8) & 0x3);
4001 int n = type + 1;
4002 int stride = ((given >> 5) & 0x1);
4003 int ix;
4004
4005 if (stride && (n == 1))
4006 n++;
4007 else
4008 stride++;
4009
4010 func (stream, "{");
4011 if (stride > 1)
4012 for (ix = 0; ix != n; ix++)
4013 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4014 else if (n == 1)
4015 func (stream, "d%d[]", rd);
4016 else
4017 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4018 func (stream, "}, [%s", arm_regnames[rn]);
4019 if (align)
4020 {
91d6fa6a 4021 align = (8 * (type + 1)) << size;
16980d0b
JB		 4022 if (type == 3)
4023 align = (size > 1) ? align >> 1 : align;
4024 if (type == 2 || (type == 0 && !size))
8e560766 4025 func (stream, " :<bad align %d>", align);
16980d0b 4026 else
8e560766 4027 func (stream, " :%d", align);
16980d0b
JB		 4028 }
4029 func (stream, "]");
4030 if (rm == 0xd)
4031 func (stream, "!");
4032 else if (rm != 0xf)
4033 func (stream, ", %s", arm_regnames[rm]);
4034 }
4035 break;
4036
4037 case 'D':
4038 {
4039 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4040 int size = (given >> 20) & 3;
4041 int reg = raw_reg & ((4 << size) - 1);
4042 int ix = raw_reg >> size >> 2;
4043
4044 func (stream, "d%d[%d]", reg, ix);
4045 }
4046 break;
4047
4048 case 'E':
fe56b6ce 4049 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4050 {
4051 int bits = 0;
4052 int cmode = (given >> 8) & 0xf;
4053 int op = (given >> 5) & 0x1;
4054 unsigned long value = 0, hival = 0;
4055 unsigned shift;
4056 int size = 0;
0dbde4cf 4057 int isfloat = 0;
16980d0b
JB		 4058
4059 bits |= ((given >> 24) & 1) << 7;
4060 bits |= ((given >> 16) & 7) << 4;
4061 bits |= ((given >> 0) & 15) << 0;
4062
4063 if (cmode < 8)
4064 {
4065 shift = (cmode >> 1) & 3;
fe56b6ce 4066 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4067 size = 32;
4068 }
4069 else if (cmode < 12)
4070 {
4071 shift = (cmode >> 1) & 1;
fe56b6ce 4072 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4073 size = 16;
4074 }
4075 else if (cmode < 14)
4076 {
4077 shift = (cmode & 1) + 1;
fe56b6ce 4078 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4079 value |= (1ul << (8 * shift)) - 1;
4080 size = 32;
4081 }
4082 else if (cmode == 14)
4083 {
4084 if (op)
4085 {
fe56b6ce 4086 /* Bit replication into bytes. */
16980d0b
JB		 4087 int ix;
4088 unsigned long mask;
4089
4090 value = 0;
4091 hival = 0;
4092 for (ix = 7; ix >= 0; ix--)
4093 {
4094 mask = ((bits >> ix) & 1) ? 0xff : 0;
4095 if (ix <= 3)
4096 value = (value << 8) | mask;
4097 else
4098 hival = (hival << 8) | mask;
4099 }
4100 size = 64;
4101 }
4102 else
4103 {
fe56b6ce
NC		 4104 /* Byte replication. */
4105 value = (unsigned long) bits;
16980d0b
JB		 4106 size = 8;
4107 }
4108 }
4109 else if (!op)
4110 {
fe56b6ce 4111 /* Floating point encoding. */
16980d0b
JB		 4112 int tmp;
4113
fe56b6ce
NC		 4114 value = (unsigned long) (bits & 0x7f) << 19;
4115 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4116 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4117 value |= (unsigned long) tmp << 24;
16980d0b 4118 size = 32;
0dbde4cf 4119 isfloat = 1;
16980d0b
JB		 4120 }
4121 else
4122 {
4123 func (stream, "<illegal constant %.8x:%x:%x>",
4124 bits, cmode, op);
4125 size = 32;
4126 break;
4127 }
4128 switch (size)
4129 {
4130 case 8:
4131 func (stream, "#%ld\t; 0x%.2lx", value, value);
4132 break;
4133
4134 case 16:
4135 func (stream, "#%ld\t; 0x%.4lx", value, value);
4136 break;
4137
4138 case 32:
0dbde4cf
JB		 4139 if (isfloat)
4140 {
4141 unsigned char valbytes[4];
4142 double fvalue;
4143
4144 /* Do this a byte at a time so we don't have to
4145 worry about the host's endianness. */
4146 valbytes[0] = value & 0xff;
4147 valbytes[1] = (value >> 8) & 0xff;
4148 valbytes[2] = (value >> 16) & 0xff;
4149 valbytes[3] = (value >> 24) & 0xff;
4150
4151 floatformat_to_double
c1e26897
NC		 4152 (& floatformat_ieee_single_little, valbytes,
4153 & fvalue);
0dbde4cf
JB		 4154
4155 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4156 value);
4157 }
4158 else
4e9d3b81 4159 func (stream, "#%ld\t; 0x%.8lx",
9d82ec38
MGD		 4160 (long) (((value & 0x80000000L) != 0)
4161 ? value | ~0xffffffffL : value),
c1e26897 4162 value);
16980d0b
JB		 4163 break;
4164
4165 case 64:
4166 func (stream, "#0x%.8lx%.8lx", hival, value);
4167 break;
4168
4169 default:
4170 abort ();
4171 }
4172 }
4173 break;
4174
4175 case 'F':
4176 {
4177 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4178 int num = (given >> 8) & 0x3;
4179
4180 if (!num)
4181 func (stream, "{d%d}", regno);
4182 else if (num + regno >= 32)
4183 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4184 else
4185 func (stream, "{d%d-d%d}", regno, regno + num);
4186 }
4187 break;
7e8e6784 4188
16980d0b
JB		 4189
4190 case '0': case '1': case '2': case '3': case '4':
4191 case '5': case '6': case '7': case '8': case '9':
4192 {
4193 int width;
4194 unsigned long value;
4195
4196 c = arm_decode_bitfield (c, given, &value, &width);
4197
4198 switch (*c)
4199 {
4200 case 'r':
4201 func (stream, "%s", arm_regnames[value]);
4202 break;
4203 case 'd':
4204 func (stream, "%ld", value);
05413229 4205 value_in_comment = value;
16980d0b
JB		 4206 break;
4207 case 'e':
4208 func (stream, "%ld", (1ul << width) - value);
4209 break;
4210
4211 case 'S':
4212 case 'T':
4213 case 'U':
05413229 4214 /* Various width encodings. */
16980d0b
JB		 4215 {
4216 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4217 int limit;
4218 unsigned low, high;
4219
4220 c++;
4221 if (*c >= '0' && *c <= '9')
4222 limit = *c - '0';
4223 else if (*c >= 'a' && *c <= 'f')
4224 limit = *c - 'a' + 10;
4225 else
4226 abort ();
4227 low = limit >> 2;
4228 high = limit & 3;
4229
4230 if (value < low || value > high)
4231 func (stream, "<illegal width %d>", base << value);
4232 else
4233 func (stream, "%d", base << value);
4234 }
4235 break;
4236 case 'R':
4237 if (given & (1 << 6))
4238 goto Q;
4239 /* FALLTHROUGH */
4240 case 'D':
4241 func (stream, "d%ld", value);
4242 break;
4243 case 'Q':
4244 Q:
4245 if (value & 1)
4246 func (stream, "<illegal reg q%ld.5>", value >> 1);
4247 else
4248 func (stream, "q%ld", value >> 1);
4249 break;
4250
4251 case '`':
4252 c++;
4253 if (value == 0)
4254 func (stream, "%c", *c);
4255 break;
4256 case '\'':
4257 c++;
4258 if (value == ((1ul << width) - 1))
4259 func (stream, "%c", *c);
4260 break;
4261 case '?':
fe56b6ce 4262 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4263 c += 1 << width;
4264 break;
4265 default:
4266 abort ();
4267 }
4268 break;
4269
4270 default:
4271 abort ();
4272 }
4273 }
4274 }
4275 else
4276 func (stream, "%c", *c);
4277 }
05413229
NC		 4278
4279 if (value_in_comment > 32 || value_in_comment < -16)
4280 func (stream, "\t; 0x%lx", value_in_comment);
4281
e2efe87d
MGD		 4282 if (is_unpredictable)
4283 func (stream, UNPREDICTABLE_INSTRUCTION);
4284
16980d0b
JB		 4285 return TRUE;
4286 }
4287 }
4288 return FALSE;
4289}
4290
90ec0d68
MGD		 4291/* Return the name of a v7A special register. */
4292
4293static const char *
4294banked_regname (unsigned reg)
4295{
4296 switch (reg)
4297 {
4298 case 15: return "CPSR";
4299 case 32: return "R8_usr";
4300 case 33: return "R9_usr";
4301 case 34: return "R10_usr";
4302 case 35: return "R11_usr";
4303 case 36: return "R12_usr";
4304 case 37: return "SP_usr";
4305 case 38: return "LR_usr";
4306 case 40: return "R8_fiq";
4307 case 41: return "R9_fiq";
4308 case 42: return "R10_fiq";
4309 case 43: return "R11_fiq";
4310 case 44: return "R12_fiq";
4311 case 45: return "SP_fiq";
4312 case 46: return "LR_fiq";
4313 case 48: return "LR_irq";
4314 case 49: return "SP_irq";
4315 case 50: return "LR_svc";
4316 case 51: return "SP_svc";
4317 case 52: return "LR_abt";
4318 case 53: return "SP_abt";
4319 case 54: return "LR_und";
4320 case 55: return "SP_und";
4321 case 60: return "LR_mon";
4322 case 61: return "SP_mon";
4323 case 62: return "ELR_hyp";
4324 case 63: return "SP_hyp";
4325 case 79: return "SPSR";
4326 case 110: return "SPSR_fiq";
4327 case 112: return "SPSR_irq";
4328 case 114: return "SPSR_svc";
4329 case 116: return "SPSR_abt";
4330 case 118: return "SPSR_und";
4331 case 124: return "SPSR_mon";
4332 case 126: return "SPSR_hyp";
4333 default: return NULL;
4334 }
4335}
4336
e797f7e0
MGD		 4337/* Return the name of the DMB/DSB option. */
4338static const char *
4339data_barrier_option (unsigned option)
4340{
4341 switch (option & 0xf)
4342 {
4343 case 0xf: return "sy";
4344 case 0xe: return "st";
4345 case 0xd: return "ld";
4346 case 0xb: return "ish";
4347 case 0xa: return "ishst";
4348 case 0x9: return "ishld";
4349 case 0x7: return "un";
4350 case 0x6: return "unst";
4351 case 0x5: return "nshld";
4352 case 0x3: return "osh";
4353 case 0x2: return "oshst";
4354 case 0x1: return "oshld";
4355 default: return NULL;
4356 }
4357}
4358
4a5329c6
ZW		 4359/* Print one ARM instruction from PC on INFO->STREAM. */
4360
4361static void
4362print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4363{
6b5d3a4d 4364 const struct opcode32 *insn;
6a51a8a8 4365 void *stream = info->stream;
6b5d3a4d 4366 fprintf_ftype func = info->fprintf_func;
b0e28b39 4367 struct arm_private_data *private_data = info->private_data;
252b5132 4368
16980d0b
JB		 4369 if (print_insn_coprocessor (pc, info, given, FALSE))
4370 return;
4371
4372 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4373 return;
4374
252b5132
RH		 4375 for (insn = arm_opcodes; insn->assembler; insn++)
4376 {
0313a2b8
NC		 4377 if ((given & insn->mask) != insn->value)
4378 continue;
823d2571
TG		 4379
4380 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4381 continue;
4382
4383 /* Special case: an instruction with all bits set in the condition field
4384 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4385 or by the catchall at the end of the table. */
4386 if ((given & 0xF0000000) != 0xF0000000
4387 || (insn->mask & 0xF0000000) == 0xF0000000
4388 || (insn->mask == 0 && insn->value == 0))
252b5132 4389 {
ff4a8d2b
NC		 4390 unsigned long u_reg = 16;
4391 unsigned long U_reg = 16;
ab8e2090 4392 bfd_boolean is_unpredictable = FALSE;
05413229 4393 signed long value_in_comment = 0;
6b5d3a4d 4394 const char *c;
b34976b6 4395
252b5132
RH		 4396 for (c = insn->assembler; *c; c++)
4397 {
4398 if (*c == '%')
4399 {
c1e26897
NC		 4400 bfd_boolean allow_unpredictable = FALSE;
4401
252b5132
RH		 4402 switch (*++c)
4403 {
4404 case '%':
4405 func (stream, "%%");
4406 break;
4407
4408 case 'a':
05413229 4409 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4410 break;
252b5132 4411
62b3e311
PB		 4412 case 'P':
4413 /* Set P address bit and use normal address
4414 printing routine. */
c1e26897 4415 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4416 break;
4417
c1e26897
NC		 4418 case 'S':
4419 allow_unpredictable = TRUE;
252b5132
RH		 4420 case 's':
4421 if ((given & 0x004f0000) == 0x004f0000)
4422 {
58efb6c0 4423 /* PC relative with immediate offset. */
f8b960bc 4424 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4425
aefd8a40
NC		 4426 if (PRE_BIT_SET)
4427 {
26d97720
NS		 4428 /* Elide positive zero offset. */
4429 if (offset || NEGATIVE_BIT_SET)
4430 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4431 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4432 else
26d97720
NS		 4433 func (stream, "[pc]\t; ");
4434 if (NEGATIVE_BIT_SET)
4435 offset = -offset;
aefd8a40
NC		 4436 info->print_address_func (offset + pc + 8, info);
4437 }
4438 else
4439 {
26d97720
NS		 4440 /* Always show the offset. */
4441 func (stream, "[pc], #%s%d",
d908c8af 4442 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4443 if (! allow_unpredictable)
4444 is_unpredictable = TRUE;
aefd8a40 4445 }
252b5132
RH		 4446 }
4447 else
4448 {
fe56b6ce
NC		 4449 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4450
b34976b6 4451 func (stream, "[%s",
252b5132 4452 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4453
c1e26897 4454 if (PRE_BIT_SET)
252b5132 4455 {
c1e26897 4456 if (IMMEDIATE_BIT_SET)
252b5132 4457 {
26d97720
NS		 4458 /* Elide offset for non-writeback
4459 positive zero. */
4460 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4461 || offset)
4462 func (stream, ", #%s%d",
4463 NEGATIVE_BIT_SET ? "-" : "", offset);
4464
4465 if (NEGATIVE_BIT_SET)
4466 offset = -offset;
945ee430 4467
fe56b6ce 4468 value_in_comment = offset;
252b5132 4469 }
945ee430 4470 else
ff4a8d2b
NC		 4471 {
4472 /* Register Offset or Register Pre-Indexed. */
4473 func (stream, ", %s%s",
4474 NEGATIVE_BIT_SET ? "-" : "",
4475 arm_regnames[given & 0xf]);
4476
4477 /* Writing back to the register that is the source/
4478 destination of the load/store is unpredictable. */
4479 if (! allow_unpredictable
4480 && WRITEBACK_BIT_SET
4481 && ((given & 0xf) == ((given >> 12) & 0xf)))
4482 is_unpredictable = TRUE;
4483 }
252b5132 4484
b34976b6 4485 func (stream, "]%s",
c1e26897 4486 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4487 }
945ee430 4488 else
252b5132 4489 {
c1e26897 4490 if (IMMEDIATE_BIT_SET)
252b5132 4491 {
945ee430 4492 /* Immediate Post-indexed. */
aefd8a40 4493 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4494 func (stream, "], #%s%d",
4495 NEGATIVE_BIT_SET ? "-" : "", offset);
4496 if (NEGATIVE_BIT_SET)
4497 offset = -offset;
fe56b6ce 4498 value_in_comment = offset;
252b5132 4499 }
945ee430 4500 else
ff4a8d2b
NC		 4501 {
4502 /* Register Post-indexed. */
4503 func (stream, "], %s%s",
4504 NEGATIVE_BIT_SET ? "-" : "",
4505 arm_regnames[given & 0xf]);
4506
4507 /* Writing back to the register that is the source/
4508 destination of the load/store is unpredictable. */
4509 if (! allow_unpredictable
4510 && (given & 0xf) == ((given >> 12) & 0xf))
4511 is_unpredictable = TRUE;
4512 }
c1e26897 4513
07a28fab
NC		 4514 if (! allow_unpredictable)
4515 {
4516 /* Writeback is automatically implied by post- addressing.
4517 Setting the W bit is unnecessary and ARM specify it as
4518 being unpredictable. */
4519 if (WRITEBACK_BIT_SET
4520 /* Specifying the PC register as the post-indexed
4521 registers is also unpredictable. */
ab8e2090
NC		 4522 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4523 is_unpredictable = TRUE;
07a28fab 4524 }
252b5132
RH		 4525 }
4526 }
4527 break;
b34976b6 4528
252b5132 4529 case 'b':
6b5d3a4d 4530 {
f8b960bc 4531 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4532 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4533 }
252b5132
RH		 4534 break;
4535
4536 case 'c':
c22aaad1
PB		 4537 if (((given >> 28) & 0xf) != 0xe)
4538 func (stream, "%s",
4539 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4540 break;
4541
4542 case 'm':
4543 {
4544 int started = 0;
4545 int reg;
4546
4547 func (stream, "{");
4548 for (reg = 0; reg < 16; reg++)
4549 if ((given & (1 << reg)) != 0)
4550 {
4551 if (started)
4552 func (stream, ", ");
4553 started = 1;
4554 func (stream, "%s", arm_regnames[reg]);
4555 }
4556 func (stream, "}");
ab8e2090
NC		 4557 if (! started)
4558 is_unpredictable = TRUE;
252b5132
RH		 4559 }
4560 break;
4561
37b37b2d 4562 case 'q':
78c66db8 4563 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4564 break;
4565
252b5132
RH		 4566 case 'o':
4567 if ((given & 0x02000000) != 0)
4568 {
a415b1cd
JB		 4569 unsigned int rotate = (given & 0xf00) >> 7;
4570 unsigned int immed = (given & 0xff);
4571 unsigned int a, i;
4572
4573 a = (((immed << (32 - rotate))
4574 | (immed >> rotate)) & 0xffffffff);
4575 /* If there is another encoding with smaller rotate,
4576 the rotate should be specified directly. */
4577 for (i = 0; i < 32; i += 2)
4578 if ((a << i | a >> (32 - i)) <= 0xff)
4579 break;
4580
4581 if (i != rotate)
4582 func (stream, "#%d, %d", immed, rotate);
4583 else
4584 func (stream, "#%d", a);
4585 value_in_comment = a;
252b5132
RH		 4586 }
4587 else
78c66db8 4588 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4589 break;
4590
4591 case 'p':
4592 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4593 {
823d2571
TG		 4594 arm_feature_set arm_ext_v6 =
4595 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4596
aefd8a40
NC		 4597 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4598 mechanism for setting PSR flag bits. They are
4599 obsolete in V6 onwards. */
823d2571
TG		 4600 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4601 arm_ext_v6))
aefd8a40
NC		 4602 func (stream, "p");
4603 }
252b5132
RH		 4604 break;
4605
4606 case 't':
4607 if ((given & 0x01200000) == 0x00200000)
4608 func (stream, "t");
4609 break;
4610
252b5132 4611 case 'A':
05413229
NC		 4612 {
4613 int offset = given & 0xff;
f02232aa 4614
05413229 4615 value_in_comment = offset * 4;
c1e26897 4616 if (NEGATIVE_BIT_SET)
05413229 4617 value_in_comment = - value_in_comment;
f02232aa 4618
05413229 4619 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4620
c1e26897 4621 if (PRE_BIT_SET)
05413229
NC		 4622 {
4623 if (offset)
fe56b6ce 4624 func (stream, ", #%d]%s",
d908c8af 4625 (int) value_in_comment,
c1e26897 4626 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4627 else
4628 func (stream, "]");
4629 }
4630 else
4631 {
4632 func (stream, "]");
f02232aa 4633
c1e26897 4634 if (WRITEBACK_BIT_SET)
05413229
NC		 4635 {
4636 if (offset)
d908c8af 4637 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4638 }
4639 else
fe56b6ce 4640 {
d908c8af 4641 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4642 value_in_comment = offset;
4643 }
05413229
NC		 4644 }
4645 }
252b5132
RH		 4646 break;
4647
077b8428
NC		 4648 case 'B':
4649 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4650 {
4651 bfd_vma address;
4652 bfd_vma offset = 0;
b34976b6 4653
c1e26897 4654 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4655 /* Is signed, hi bits should be ones. */
4656 offset = (-1) ^ 0x00ffffff;
4657
4658 /* Offset is (SignExtend(offset field)<<2). */
4659 offset += given & 0x00ffffff;
4660 offset <<= 2;
4661 address = offset + pc + 8;
b34976b6 4662
8f06b2d8
PB		 4663 if (given & 0x01000000)
4664 /* H bit allows addressing to 2-byte boundaries. */
4665 address += 2;
b1ee46c5 4666
8f06b2d8 4667 info->print_address_func (address, info);
b1ee46c5 4668 }
b1ee46c5
AH		 4669 break;
4670
252b5132 4671 case 'C':
90ec0d68
MGD		 4672 if ((given & 0x02000200) == 0x200)
4673 {
4674 const char * name;
4675 unsigned sysm = (given & 0x004f0000) >> 16;
4676
4677 sysm |= (given & 0x300) >> 4;
4678 name = banked_regname (sysm);
4679
4680 if (name != NULL)
4681 func (stream, "%s", name);
4682 else
d908c8af 4683 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4684 }
4685 else
4686 {
4687 func (stream, "%cPSR_",
4688 (given & 0x00400000) ? 'S' : 'C');
4689 if (given & 0x80000)
4690 func (stream, "f");
4691 if (given & 0x40000)
4692 func (stream, "s");
4693 if (given & 0x20000)
4694 func (stream, "x");
4695 if (given & 0x10000)
4696 func (stream, "c");
4697 }
252b5132
RH		 4698 break;
4699
62b3e311 4700 case 'U':
52e7f43d 4701 if ((given & 0xf0) == 0x60)
62b3e311 4702 {
52e7f43d
RE		 4703 switch (given & 0xf)
4704 {
4705 case 0xf: func (stream, "sy"); break;
4706 default:
4707 func (stream, "#%d", (int) given & 0xf);
4708 break;
4709 }
4710 }
4711 else
4712 {
e797f7e0
MGD		 4713 const char * opt = data_barrier_option (given & 0xf);
4714 if (opt != NULL)
4715 func (stream, "%s", opt);
4716 else
52e7f43d 4717 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4718 }
4719 break;
4720
b34976b6 4721 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4722 case '5': case '6': case '7': case '8': case '9':
4723 {
16980d0b
JB		 4724 int width;
4725 unsigned long value;
252b5132 4726
16980d0b
JB		 4727 c = arm_decode_bitfield (c, given, &value, &width);
4728
252b5132
RH		 4729 switch (*c)
4730 {
ab8e2090
NC		 4731 case 'R':
4732 if (value == 15)
4733 is_unpredictable = TRUE;
4734 /* Fall through. */
16980d0b 4735 case 'r':
9eb6c0f1
MGD		 4736 case 'T':
4737 /* We want register + 1 when decoding T. */
4738 if (*c == 'T')
4739 ++value;
4740
ff4a8d2b
NC		 4741 if (c[1] == 'u')
4742 {
4743 /* Eat the 'u' character. */
4744 ++ c;
4745
4746 if (u_reg == value)
4747 is_unpredictable = TRUE;
4748 u_reg = value;
4749 }
4750 if (c[1] == 'U')
4751 {
4752 /* Eat the 'U' character. */
4753 ++ c;
4754
4755 if (U_reg == value)
4756 is_unpredictable = TRUE;
4757 U_reg = value;
4758 }
16980d0b
JB		 4759 func (stream, "%s", arm_regnames[value]);
4760 break;
4761 case 'd':
4762 func (stream, "%ld", value);
05413229 4763 value_in_comment = value;
16980d0b
JB		 4764 break;
4765 case 'b':
4766 func (stream, "%ld", value * 8);
05413229 4767 value_in_comment = value * 8;
16980d0b
JB		 4768 break;
4769 case 'W':
4770 func (stream, "%ld", value + 1);
05413229 4771 value_in_comment = value + 1;
16980d0b
JB		 4772 break;
4773 case 'x':
4774 func (stream, "0x%08lx", value);
4775
4776 /* Some SWI instructions have special
4777 meanings. */
4778 if ((given & 0x0fffffff) == 0x0FF00000)
4779 func (stream, "\t; IMB");
4780 else if ((given & 0x0fffffff) == 0x0FF00001)
4781 func (stream, "\t; IMBRange");
4782 break;
4783 case 'X':
4784 func (stream, "%01lx", value & 0xf);
05413229 4785 value_in_comment = value;
252b5132
RH		 4786 break;
4787 case '`':
4788 c++;
16980d0b 4789 if (value == 0)
252b5132
RH		 4790 func (stream, "%c", *c);
4791 break;
4792 case '\'':
4793 c++;
16980d0b 4794 if (value == ((1ul << width) - 1))
252b5132
RH		 4795 func (stream, "%c", *c);
4796 break;
4797 case '?':
fe56b6ce 4798 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4799 c += 1 << width;
252b5132
RH		 4800 break;
4801 default:
4802 abort ();
4803 }
4804 break;
4805
0dd132b6
NC		 4806 case 'e':
4807 {
4808 int imm;
4809
4810 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4811 func (stream, "%d", imm);
fe56b6ce 4812 value_in_comment = imm;
0dd132b6
NC		 4813 }
4814 break;
4815
0a003adc
ZW		 4816 case 'E':
4817 /* LSB and WIDTH fields of BFI or BFC. The machine-
4818 language instruction encodes LSB and MSB. */
4819 {
4820 long msb = (given & 0x001f0000) >> 16;
4821 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 4822 long w = msb - lsb + 1;
fe56b6ce 4823
91d6fa6a
NC		 4824 if (w > 0)
4825 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 4826 else
4827 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4828 }
4829 break;
4830
90ec0d68
MGD		 4831 case 'R':
4832 /* Get the PSR/banked register name. */
4833 {
4834 const char * name;
4835 unsigned sysm = (given & 0x004f0000) >> 16;
4836
4837 sysm |= (given & 0x300) >> 4;
4838 name = banked_regname (sysm);
4839
4840 if (name != NULL)
4841 func (stream, "%s", name);
4842 else
d908c8af 4843 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4844 }
4845 break;
4846
0a003adc
ZW		 4847 case 'V':
4848 /* 16-bit unsigned immediate from a MOVT or MOVW
4849 instruction, encoded in bits 0:11 and 15:19. */
4850 {
4851 long hi = (given & 0x000f0000) >> 4;
4852 long lo = (given & 0x00000fff);
4853 long imm16 = hi | lo;
fe56b6ce
NC		 4854
4855 func (stream, "#%lu", imm16);
4856 value_in_comment = imm16;
0a003adc
ZW		 4857 }
4858 break;
4859
252b5132
RH		 4860 default:
4861 abort ();
4862 }
4863 }
4864 }
4865 else
4866 func (stream, "%c", *c);
4867 }
05413229
NC		 4868
4869 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4870 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 4871
4872 if (is_unpredictable)
4873 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 4874
4a5329c6 4875 return;
252b5132
RH		 4876 }
4877 }
4878 abort ();
4879}
4880
4a5329c6 4881/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 4882
4a5329c6
ZW		 4883static void
4884print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4885{
6b5d3a4d 4886 const struct opcode16 *insn;
6a51a8a8
AM		 4887 void *stream = info->stream;
4888 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 4889
4890 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 4891 if ((given & insn->mask) == insn->value)
4892 {
05413229 4893 signed long value_in_comment = 0;
6b5d3a4d 4894 const char *c = insn->assembler;
05413229 4895
c19d1205
ZW		 4896 for (; *c; c++)
4897 {
4898 int domaskpc = 0;
4899 int domasklr = 0;
4900
4901 if (*c != '%')
4902 {
4903 func (stream, "%c", *c);
4904 continue;
4905 }
252b5132 4906
c19d1205
ZW		 4907 switch (*++c)
4908 {
4909 case '%':
4910 func (stream, "%%");
4911 break;
b34976b6 4912
c22aaad1
PB		 4913 case 'c':
4914 if (ifthen_state)
4915 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4916 break;
4917
4918 case 'C':
4919 if (ifthen_state)
4920 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4921 else
4922 func (stream, "s");
4923 break;
4924
4925 case 'I':
4926 {
4927 unsigned int tmp;
4928
4929 ifthen_next_state = given & 0xff;
4930 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4931 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4932 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4933 }
4934 break;
4935
4936 case 'x':
4937 if (ifthen_next_state)
4938 func (stream, "\t; unpredictable branch in IT block\n");
4939 break;
4940
4941 case 'X':
4942 if (ifthen_state)
4943 func (stream, "\t; unpredictable <IT:%s>",
4944 arm_conditional[IFTHEN_COND]);
4945 break;
4946
c19d1205
ZW		 4947 case 'S':
4948 {
4949 long reg;
4950
4951 reg = (given >> 3) & 0x7;
4952 if (given & (1 << 6))
4953 reg += 8;
4f3c3dbb 4954
c19d1205
ZW		 4955 func (stream, "%s", arm_regnames[reg]);
4956 }
4957 break;
baf0cc5e 4958
c19d1205 4959 case 'D':
4f3c3dbb 4960 {
c19d1205
ZW		 4961 long reg;
4962
4963 reg = given & 0x7;
4964 if (given & (1 << 7))
4965 reg += 8;
4966
4967 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 4968 }
c19d1205
ZW		 4969 break;
4970
4971 case 'N':
4972 if (given & (1 << 8))
4973 domasklr = 1;
4974 /* Fall through. */
4975 case 'O':
4976 if (*c == 'O' && (given & (1 << 8)))
4977 domaskpc = 1;
4978 /* Fall through. */
4979 case 'M':
4980 {
4981 int started = 0;
4982 int reg;
4983
4984 func (stream, "{");
4985
4986 /* It would be nice if we could spot
4987 ranges, and generate the rS-rE format: */
4988 for (reg = 0; (reg < 8); reg++)
4989 if ((given & (1 << reg)) != 0)
4990 {
4991 if (started)
4992 func (stream, ", ");
4993 started = 1;
4994 func (stream, "%s", arm_regnames[reg]);
4995 }
4996
4997 if (domasklr)
4998 {
4999 if (started)
5000 func (stream, ", ");
5001 started = 1;
d908c8af 5002 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5003 }
5004
5005 if (domaskpc)
5006 {
5007 if (started)
5008 func (stream, ", ");
d908c8af 5009 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5010 }
5011
5012 func (stream, "}");
5013 }
5014 break;
5015
4547cb56
NC		 5016 case 'W':
5017 /* Print writeback indicator for a LDMIA. We are doing a
5018 writeback if the base register is not in the register
5019 mask. */
5020 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5021 func (stream, "!");
5022 break;
5023
c19d1205
ZW		 5024 case 'b':
5025 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5026 {
5027 bfd_vma address = (pc + 4
5028 + ((given & 0x00f8) >> 2)
5029 + ((given & 0x0200) >> 3));
5030 info->print_address_func (address, info);
5031 }
5032 break;
5033
5034 case 's':
5035 /* Right shift immediate -- bits 6..10; 1-31 print
5036 as themselves, 0 prints as 32. */
5037 {
5038 long imm = (given & 0x07c0) >> 6;
5039 if (imm == 0)
5040 imm = 32;
0fd3a477 5041 func (stream, "#%ld", imm);
c19d1205
ZW		 5042 }
5043 break;
5044
5045 case '0': case '1': case '2': case '3': case '4':
5046 case '5': case '6': case '7': case '8': case '9':
5047 {
5048 int bitstart = *c++ - '0';
5049 int bitend = 0;
5050
5051 while (*c >= '0' && *c <= '9')
5052 bitstart = (bitstart * 10) + *c++ - '0';
5053
5054 switch (*c)
5055 {
5056 case '-':
5057 {
f8b960bc 5058 bfd_vma reg;
c19d1205
ZW		 5059
5060 c++;
5061 while (*c >= '0' && *c <= '9')
5062 bitend = (bitend * 10) + *c++ - '0';
5063 if (!bitend)
5064 abort ();
5065 reg = given >> bitstart;
5066 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5067
c19d1205
ZW		 5068 switch (*c)
5069 {
5070 case 'r':
5071 func (stream, "%s", arm_regnames[reg]);
5072 break;
5073
5074 case 'd':
d908c8af 5075 func (stream, "%ld", (long) reg);
05413229 5076 value_in_comment = reg;
c19d1205
ZW		 5077 break;
5078
5079 case 'H':
d908c8af 5080 func (stream, "%ld", (long) (reg << 1));
05413229 5081 value_in_comment = reg << 1;
c19d1205
ZW		 5082 break;
5083
5084 case 'W':
d908c8af 5085 func (stream, "%ld", (long) (reg << 2));
05413229 5086 value_in_comment = reg << 2;
c19d1205
ZW		 5087 break;
5088
5089 case 'a':
5090 /* PC-relative address -- the bottom two
5091 bits of the address are dropped
5092 before the calculation. */
5093 info->print_address_func
5094 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5095 value_in_comment = 0;
c19d1205
ZW		 5096 break;
5097
5098 case 'x':
d908c8af 5099 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5100 break;
5101
c19d1205
ZW		 5102 case 'B':
5103 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5104 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5105 value_in_comment = 0;
c19d1205
ZW		 5106 break;
5107
5108 case 'c':
c22aaad1 5109 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5110 break;
5111
5112 default:
5113 abort ();
5114 }
5115 }
5116 break;
5117
5118 case '\'':
5119 c++;
5120 if ((given & (1 << bitstart)) != 0)
5121 func (stream, "%c", *c);
5122 break;
5123
5124 case '?':
5125 ++c;
5126 if ((given & (1 << bitstart)) != 0)
5127 func (stream, "%c", *c++);
5128 else
5129 func (stream, "%c", *++c);
5130 break;
5131
5132 default:
5133 abort ();
5134 }
5135 }
5136 break;
5137
5138 default:
5139 abort ();
5140 }
5141 }
05413229
NC		 5142
5143 if (value_in_comment > 32 || value_in_comment < -16)
5144 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5145 return;
c19d1205
ZW		 5146 }
5147
5148 /* No match. */
5149 abort ();
5150}
5151
62b3e311 5152/* Return the name of an V7M special register. */
fe56b6ce 5153
62b3e311
PB		 5154static const char *
5155psr_name (int regno)
5156{
5157 switch (regno)
5158 {
5159 case 0: return "APSR";
5160 case 1: return "IAPSR";
5161 case 2: return "EAPSR";
5162 case 3: return "PSR";
5163 case 5: return "IPSR";
5164 case 6: return "EPSR";
5165 case 7: return "IEPSR";
5166 case 8: return "MSP";
5167 case 9: return "PSP";
5168 case 16: return "PRIMASK";
5169 case 17: return "BASEPRI";
00bbc0bd 5170 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5171 case 19: return "FAULTMASK";
5172 case 20: return "CONTROL";
5173 default: return "<unknown>";
5174 }
5175}
5176
4a5329c6
ZW		 5177/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5178
5179static void
5180print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5181{
6b5d3a4d 5182 const struct opcode32 *insn;
c19d1205
ZW		 5183 void *stream = info->stream;
5184 fprintf_ftype func = info->fprintf_func;
5185
16980d0b
JB		 5186 if (print_insn_coprocessor (pc, info, given, TRUE))
5187 return;
5188
5189 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5190 return;
5191
c19d1205
ZW		 5192 for (insn = thumb32_opcodes; insn->assembler; insn++)
5193 if ((given & insn->mask) == insn->value)
5194 {
ff4a8d2b 5195 bfd_boolean is_unpredictable = FALSE;
05413229 5196 signed long value_in_comment = 0;
6b5d3a4d 5197 const char *c = insn->assembler;
05413229 5198
c19d1205
ZW		 5199 for (; *c; c++)
5200 {
5201 if (*c != '%')
5202 {
5203 func (stream, "%c", *c);
5204 continue;
5205 }
5206
5207 switch (*++c)
5208 {
5209 case '%':
5210 func (stream, "%%");
5211 break;
5212
c22aaad1
PB		 5213 case 'c':
5214 if (ifthen_state)
5215 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5216 break;
5217
5218 case 'x':
5219 if (ifthen_next_state)
5220 func (stream, "\t; unpredictable branch in IT block\n");
5221 break;
5222
5223 case 'X':
5224 if (ifthen_state)
5225 func (stream, "\t; unpredictable <IT:%s>",
5226 arm_conditional[IFTHEN_COND]);
5227 break;
5228
c19d1205
ZW		 5229 case 'I':
5230 {
5231 unsigned int imm12 = 0;
fe56b6ce 5232
c19d1205
ZW		 5233 imm12 |= (given & 0x000000ffu);
5234 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5235 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5236 func (stream, "#%u", imm12);
5237 value_in_comment = imm12;
c19d1205
ZW		 5238 }
5239 break;
5240
5241 case 'M':
5242 {
5243 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5244
c19d1205
ZW		 5245 bits |= (given & 0x000000ffu);
5246 bits |= (given & 0x00007000u) >> 4;
5247 bits |= (given & 0x04000000u) >> 15;
5248 imm8 = (bits & 0x0ff);
5249 mod = (bits & 0xf00) >> 8;
5250 switch (mod)
5251 {
5252 case 0: imm = imm8; break;
c1e26897
NC		 5253 case 1: imm = ((imm8 << 16) | imm8); break;
5254 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5255 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5256 default:
5257 mod = (bits & 0xf80) >> 7;
5258 imm8 = (bits & 0x07f) | 0x80;
5259 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5260 }
fe56b6ce
NC		 5261 func (stream, "#%u", imm);
5262 value_in_comment = imm;
c19d1205
ZW		 5263 }
5264 break;
5265
5266 case 'J':
5267 {
5268 unsigned int imm = 0;
fe56b6ce 5269
c19d1205
ZW		 5270 imm |= (given & 0x000000ffu);
5271 imm |= (given & 0x00007000u) >> 4;
5272 imm |= (given & 0x04000000u) >> 15;
5273 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5274 func (stream, "#%u", imm);
5275 value_in_comment = imm;
c19d1205
ZW		 5276 }
5277 break;
5278
5279 case 'K':
5280 {
5281 unsigned int imm = 0;
fe56b6ce 5282
c19d1205
ZW		 5283 imm |= (given & 0x000f0000u) >> 16;
5284 imm |= (given & 0x00000ff0u) >> 0;
5285 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5286 func (stream, "#%u", imm);
5287 value_in_comment = imm;
c19d1205
ZW		 5288 }
5289 break;
5290
74db7efb
NC		 5291 case 'H':
5292 {
5293 unsigned int imm = 0;
5294
5295 imm |= (given & 0x000f0000u) >> 4;
5296 imm |= (given & 0x00000fffu) >> 0;
5297 func (stream, "#%u", imm);
5298 value_in_comment = imm;
5299 }
5300 break;
5301
90ec0d68
MGD		 5302 case 'V':
5303 {
5304 unsigned int imm = 0;
5305
5306 imm |= (given & 0x00000fffu);
5307 imm |= (given & 0x000f0000u) >> 4;
5308 func (stream, "#%u", imm);
5309 value_in_comment = imm;
5310 }
5311 break;
5312
c19d1205
ZW		 5313 case 'S':
5314 {
5315 unsigned int reg = (given & 0x0000000fu);
5316 unsigned int stp = (given & 0x00000030u) >> 4;
5317 unsigned int imm = 0;
5318 imm |= (given & 0x000000c0u) >> 6;
5319 imm |= (given & 0x00007000u) >> 10;
5320
5321 func (stream, "%s", arm_regnames[reg]);
5322 switch (stp)
5323 {
5324 case 0:
5325 if (imm > 0)
5326 func (stream, ", lsl #%u", imm);
5327 break;
5328
5329 case 1:
5330 if (imm == 0)
5331 imm = 32;
5332 func (stream, ", lsr #%u", imm);
5333 break;
5334
5335 case 2:
5336 if (imm == 0)
5337 imm = 32;
5338 func (stream, ", asr #%u", imm);
5339 break;
5340
5341 case 3:
5342 if (imm == 0)
5343 func (stream, ", rrx");
5344 else
5345 func (stream, ", ror #%u", imm);
5346 }
5347 }
5348 break;
5349
5350 case 'a':
5351 {
5352 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5353 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5354 unsigned int op = (given & 0x00000f00) >> 8;
5355 unsigned int i12 = (given & 0x00000fff);
5356 unsigned int i8 = (given & 0x000000ff);
5357 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5358 bfd_vma offset = 0;
c19d1205
ZW		 5359
5360 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5361 if (U) /* 12-bit positive immediate offset. */
5362 {
5363 offset = i12;
5364 if (Rn != 15)
5365 value_in_comment = offset;
5366 }
5367 else if (Rn == 15) /* 12-bit negative immediate offset. */
5368 offset = - (int) i12;
5369 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5370 {
5371 unsigned int Rm = (i8 & 0x0f);
5372 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5373
c19d1205
ZW		 5374 func (stream, ", %s", arm_regnames[Rm]);
5375 if (sh)
5376 func (stream, ", lsl #%u", sh);
5377 func (stream, "]");
5378 break;
5379 }
5380 else switch (op)
5381 {
05413229 5382 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5383 offset = i8;
5384 break;
5385
05413229 5386 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5387 offset = -i8;
5388 break;
5389
05413229 5390 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5391 offset = i8;
5392 writeback = TRUE;
5393 break;
5394
05413229 5395 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5396 offset = -i8;
5397 writeback = TRUE;
5398 break;
5399
05413229 5400 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5401 offset = i8;
5402 postind = TRUE;
5403 break;
5404
05413229 5405 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5406 offset = -i8;
5407 postind = TRUE;
5408 break;
5409
5410 default:
5411 func (stream, ", <undefined>]");
5412 goto skip;
5413 }
5414
5415 if (postind)
d908c8af 5416 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5417 else
5418 {
5419 if (offset)
d908c8af 5420 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5421 func (stream, writeback ? "]!" : "]");
5422 }
5423
5424 if (Rn == 15)
5425 {
5426 func (stream, "\t; ");
5427 info->print_address_func (((pc + 4) & ~3) + offset, info);
5428 }
5429 }
5430 skip:
5431 break;
5432
5433 case 'A':
5434 {
c1e26897
NC		 5435 unsigned int U = ! NEGATIVE_BIT_SET;
5436 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5437 unsigned int Rn = (given & 0x000f0000) >> 16;
5438 unsigned int off = (given & 0x000000ff);
5439
5440 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5441
5442 if (PRE_BIT_SET)
c19d1205
ZW		 5443 {
5444 if (off || !U)
05413229
NC		 5445 {
5446 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5447 value_in_comment = off * 4 * U ? 1 : -1;
5448 }
c19d1205
ZW		 5449 func (stream, "]");
5450 if (W)
5451 func (stream, "!");
5452 }
5453 else
5454 {
5455 func (stream, "], ");
5456 if (W)
05413229
NC		 5457 {
5458 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5459 value_in_comment = off * 4 * U ? 1 : -1;
5460 }
c19d1205 5461 else
fe56b6ce
NC		 5462 {
5463 func (stream, "{%u}", off);
5464 value_in_comment = off;
5465 }
c19d1205
ZW		 5466 }
5467 }
5468 break;
5469
5470 case 'w':
5471 {
5472 unsigned int Sbit = (given & 0x01000000) >> 24;
5473 unsigned int type = (given & 0x00600000) >> 21;
05413229 5474
c19d1205
ZW		 5475 switch (type)
5476 {
5477 case 0: func (stream, Sbit ? "sb" : "b"); break;
5478 case 1: func (stream, Sbit ? "sh" : "h"); break;
5479 case 2:
5480 if (Sbit)
5481 func (stream, "??");
5482 break;
5483 case 3:
5484 func (stream, "??");
5485 break;
5486 }
5487 }
5488 break;
5489
5490 case 'm':
5491 {
5492 int started = 0;
5493 int reg;
5494
5495 func (stream, "{");
5496 for (reg = 0; reg < 16; reg++)
5497 if ((given & (1 << reg)) != 0)
5498 {
5499 if (started)
5500 func (stream, ", ");
5501 started = 1;
5502 func (stream, "%s", arm_regnames[reg]);
5503 }
5504 func (stream, "}");
5505 }
5506 break;
5507
5508 case 'E':
5509 {
5510 unsigned int msb = (given & 0x0000001f);
5511 unsigned int lsb = 0;
fe56b6ce 5512
c19d1205
ZW		 5513 lsb |= (given & 0x000000c0u) >> 6;
5514 lsb |= (given & 0x00007000u) >> 10;
5515 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5516 }
5517 break;
5518
5519 case 'F':
5520 {
5521 unsigned int width = (given & 0x0000001f) + 1;
5522 unsigned int lsb = 0;
fe56b6ce 5523
c19d1205
ZW		 5524 lsb |= (given & 0x000000c0u) >> 6;
5525 lsb |= (given & 0x00007000u) >> 10;
5526 func (stream, "#%u, #%u", lsb, width);
5527 }
5528 break;
5529
5530 case 'b':
5531 {
5532 unsigned int S = (given & 0x04000000u) >> 26;
5533 unsigned int J1 = (given & 0x00002000u) >> 13;
5534 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5535 bfd_vma offset = 0;
c19d1205
ZW		 5536
5537 offset |= !S << 20;
5538 offset |= J2 << 19;
5539 offset |= J1 << 18;
5540 offset |= (given & 0x003f0000) >> 4;
5541 offset |= (given & 0x000007ff) << 1;
5542 offset -= (1 << 20);
5543
5544 info->print_address_func (pc + 4 + offset, info);
5545 }
5546 break;
5547
5548 case 'B':
5549 {
5550 unsigned int S = (given & 0x04000000u) >> 26;
5551 unsigned int I1 = (given & 0x00002000u) >> 13;
5552 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5553 bfd_vma offset = 0;
c19d1205
ZW		 5554
5555 offset |= !S << 24;
5556 offset |= !(I1 ^ S) << 23;
5557 offset |= !(I2 ^ S) << 22;
5558 offset |= (given & 0x03ff0000u) >> 4;
5559 offset |= (given & 0x000007ffu) << 1;
5560 offset -= (1 << 24);
36b0c57d 5561 offset += pc + 4;
c19d1205 5562
36b0c57d
PB		 5563 /* BLX target addresses are always word aligned. */
5564 if ((given & 0x00001000u) == 0)
5565 offset &= ~2u;
5566
5567 info->print_address_func (offset, info);
c19d1205
ZW		 5568 }
5569 break;
5570
5571 case 's':
5572 {
5573 unsigned int shift = 0;
fe56b6ce 5574
c19d1205
ZW		 5575 shift |= (given & 0x000000c0u) >> 6;
5576 shift |= (given & 0x00007000u) >> 10;
c1e26897 5577 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5578 func (stream, ", asr #%u", shift);
5579 else if (shift)
5580 func (stream, ", lsl #%u", shift);
5581 /* else print nothing - lsl #0 */
5582 }
5583 break;
5584
5585 case 'R':
5586 {
5587 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5588
c19d1205
ZW		 5589 if (rot)
5590 func (stream, ", ror #%u", rot * 8);
5591 }
5592 break;
5593
62b3e311 5594 case 'U':
52e7f43d 5595 if ((given & 0xf0) == 0x60)
62b3e311 5596 {
52e7f43d
RE		 5597 switch (given & 0xf)
5598 {
5599 case 0xf: func (stream, "sy"); break;
5600 default:
5601 func (stream, "#%d", (int) given & 0xf);
5602 break;
5603 }
62b3e311 5604 }
52e7f43d
RE		 5605 else
5606 {
e797f7e0
MGD		 5607 const char * opt = data_barrier_option (given & 0xf);
5608 if (opt != NULL)
5609 func (stream, "%s", opt);
5610 else
5611 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5612 }
62b3e311
PB		 5613 break;
5614
5615 case 'C':
5616 if ((given & 0xff) == 0)
5617 {
5618 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5619 if (given & 0x800)
5620 func (stream, "f");
5621 if (given & 0x400)
5622 func (stream, "s");
5623 if (given & 0x200)
5624 func (stream, "x");
5625 if (given & 0x100)
5626 func (stream, "c");
5627 }
90ec0d68
MGD		 5628 else if ((given & 0x20) == 0x20)
5629 {
5630 char const* name;
5631 unsigned sysm = (given & 0xf00) >> 8;
5632
5633 sysm |= (given & 0x30);
5634 sysm |= (given & 0x00100000) >> 14;
5635 name = banked_regname (sysm);
5636
5637 if (name != NULL)
5638 func (stream, "%s", name);
5639 else
d908c8af 5640 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5641 }
62b3e311
PB		 5642 else
5643 {
d908c8af 5644 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5645 }
5646 break;
5647
5648 case 'D':
90ec0d68
MGD		 5649 if (((given & 0xff) == 0)
5650 || ((given & 0x20) == 0x20))
5651 {
5652 char const* name;
5653 unsigned sm = (given & 0xf0000) >> 16;
5654
5655 sm |= (given & 0x30);
5656 sm |= (given & 0x00100000) >> 14;
5657 name = banked_regname (sm);
5658
5659 if (name != NULL)
5660 func (stream, "%s", name);
5661 else
d908c8af 5662 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5663 }
62b3e311 5664 else
d908c8af 5665 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5666 break;
5667
c19d1205
ZW		 5668 case '0': case '1': case '2': case '3': case '4':
5669 case '5': case '6': case '7': case '8': case '9':
5670 {
16980d0b
JB		 5671 int width;
5672 unsigned long val;
c19d1205 5673
16980d0b
JB		 5674 c = arm_decode_bitfield (c, given, &val, &width);
5675
c19d1205
ZW		 5676 switch (*c)
5677 {
05413229
NC		 5678 case 'd':
5679 func (stream, "%lu", val);
5680 value_in_comment = val;
5681 break;
ff4a8d2b 5682
f0fba320
RL		 5683 case 'D':
5684 func (stream, "%lu", val + 1);
5685 value_in_comment = val + 1;
5686 break;
5687
05413229
NC		 5688 case 'W':
5689 func (stream, "%lu", val * 4);
5690 value_in_comment = val * 4;
5691 break;
ff4a8d2b 5692
dd5181d5
KT		 5693 case 'S':
5694 if (val == 13)
5695 is_unpredictable = TRUE;
5696 /* Fall through. */
ff4a8d2b
NC		 5697 case 'R':
5698 if (val == 15)
5699 is_unpredictable = TRUE;
5700 /* Fall through. */
5701 case 'r':
5702 func (stream, "%s", arm_regnames[val]);
5703 break;
c19d1205
ZW		 5704
5705 case 'c':
c22aaad1 5706 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5707 break;
5708
5709 case '\'':
c19d1205 5710 c++;
16980d0b
JB		 5711 if (val == ((1ul << width) - 1))
5712 func (stream, "%c", *c);
c19d1205
ZW		 5713 break;
5714
5715 case '`':
c19d1205 5716 c++;
16980d0b
JB		 5717 if (val == 0)
5718 func (stream, "%c", *c);
c19d1205
ZW		 5719 break;
5720
5721 case '?':
fe56b6ce 5722 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5723 c += 1 << width;
c19d1205 5724 break;
0bb027fd
RR		 5725
5726 case 'x':
5727 func (stream, "0x%lx", val & 0xffffffffUL);
5728 break;
c19d1205
ZW		 5729
5730 default:
5731 abort ();
5732 }
5733 }
5734 break;
5735
32a94698
NC		 5736 case 'L':
5737 /* PR binutils/12534
5738 If we have a PC relative offset in an LDRD or STRD
5739 instructions then display the decoded address. */
5740 if (((given >> 16) & 0xf) == 0xf)
5741 {
5742 bfd_vma offset = (given & 0xff) * 4;
5743
5744 if ((given & (1 << 23)) == 0)
5745 offset = - offset;
5746 func (stream, "\t; ");
5747 info->print_address_func ((pc & ~3) + 4 + offset, info);
5748 }
5749 break;
5750
c19d1205
ZW		 5751 default:
5752 abort ();
5753 }
5754 }
05413229
NC		 5755
5756 if (value_in_comment > 32 || value_in_comment < -16)
5757 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5758
5759 if (is_unpredictable)
5760 func (stream, UNPREDICTABLE_INSTRUCTION);
5761
4a5329c6 5762 return;
c19d1205 5763 }
252b5132 5764
58efb6c0 5765 /* No match. */
252b5132
RH		 5766 abort ();
5767}
5768
e821645d
DJ		 5769/* Print data bytes on INFO->STREAM. */
5770
5771static void
fe56b6ce
NC		 5772print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5773 struct disassemble_info *info,
e821645d
DJ		 5774 long given)
5775{
5776 switch (info->bytes_per_chunk)
5777 {
5778 case 1:
5779 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5780 break;
5781 case 2:
5782 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5783 break;
5784 case 4:
5785 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5786 break;
5787 default:
5788 abort ();
5789 }
5790}
5791
22a398e1 5792/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5793 being displayed in symbol relative addresses.
5794
5795 Also disallow private symbol, with __tagsym$$ prefix,
5796 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5797
5798bfd_boolean
5799arm_symbol_is_valid (asymbol * sym,
5800 struct disassemble_info * info ATTRIBUTE_UNUSED)
5801{
5802 const char * name;
5803
5804 if (sym == NULL)
5805 return FALSE;
5806
5807 name = bfd_asymbol_name (sym);
5808
d8282f0e 5809 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5810}
5811
58efb6c0 5812/* Parse an individual disassembler option. */
baf0cc5e 5813
a3d9c82d 5814void
4a5329c6 5815parse_arm_disassembler_option (char *option)
dd92f639 5816{
01c7f630 5817 if (option == NULL)
dd92f639 5818 return;
b34976b6 5819
0112cd26 5820 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 5821 {
58efb6c0 5822 int i;
b34976b6 5823
01c7f630 5824 option += 10;
58efb6c0
NC		 5825
5826 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 5827 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 5828 {
5829 regname_selected = i;
5830 break;
5831 }
b34976b6 5832
58efb6c0 5833 if (i < 0)
31e0f3cd 5834 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5835 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 5836 }
0112cd26 5837 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 5838 force_thumb = 1;
0112cd26 5839 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 5840 force_thumb = 0;
dd92f639 5841 else
31e0f3cd 5842 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5843 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 5844
dd92f639
NC		 5845 return;
5846}
5847
31e0f3cd
NC		 5848/* Parse the string of disassembler options, spliting it at whitespaces
5849 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 5850
01c7f630 5851static void
4a5329c6 5852parse_disassembler_options (char *options)
01c7f630 5853{
01c7f630
NC		 5854 if (options == NULL)
5855 return;
5856
31e0f3cd 5857 while (*options)
01c7f630 5858 {
31e0f3cd
NC		 5859 parse_arm_disassembler_option (options);
5860
5861 /* Skip forward to next seperator. */
5862 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5863 ++ options;
5864 /* Skip forward past seperators. */
5865 while (ISSPACE (*options) || (*options == ','))
5866 ++ options;
01c7f630 5867 }
01c7f630
NC		 5868}
5869
c22aaad1
PB		 5870/* Search back through the insn stream to determine if this instruction is
5871 conditionally executed. */
fe56b6ce 5872
c22aaad1 5873static void
fe56b6ce
NC		 5874find_ifthen_state (bfd_vma pc,
5875 struct disassemble_info *info,
c22aaad1
PB		 5876 bfd_boolean little)
5877{
5878 unsigned char b[2];
5879 unsigned int insn;
5880 int status;
5881 /* COUNT is twice the number of instructions seen. It will be odd if we
5882 just crossed an instruction boundary. */
5883 int count;
5884 int it_count;
5885 unsigned int seen_it;
5886 bfd_vma addr;
5887
5888 ifthen_address = pc;
5889 ifthen_state = 0;
5890
5891 addr = pc;
5892 count = 1;
5893 it_count = 0;
5894 seen_it = 0;
5895 /* Scan backwards looking for IT instructions, keeping track of where
5896 instruction boundaries are. We don't know if something is actually an
5897 IT instruction until we find a definite instruction boundary. */
5898 for (;;)
5899 {
fe56b6ce 5900 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 5901 {
5902 /* A symbol must be on an instruction boundary, and will not
5903 be within an IT block. */
5904 if (seen_it && (count & 1))
5905 break;
5906
5907 return;
5908 }
5909 addr -= 2;
fe56b6ce 5910 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 5911 if (status)
5912 return;
5913
5914 if (little)
5915 insn = (b[0]) | (b[1] << 8);
5916 else
5917 insn = (b[1]) | (b[0] << 8);
5918 if (seen_it)
5919 {
5920 if ((insn & 0xf800) < 0xe800)
5921 {
5922 /* Addr + 2 is an instruction boundary. See if this matches
5923 the expected boundary based on the position of the last
5924 IT candidate. */
5925 if (count & 1)
5926 break;
5927 seen_it = 0;
5928 }
5929 }
5930 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5931 {
5932 /* This could be an IT instruction. */
5933 seen_it = insn;
5934 it_count = count >> 1;
5935 }
5936 if ((insn & 0xf800) >= 0xe800)
5937 count++;
5938 else
5939 count = (count + 2) | 1;
5940 /* IT blocks contain at most 4 instructions. */
5941 if (count >= 8 && !seen_it)
5942 return;
5943 }
5944 /* We found an IT instruction. */
5945 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
5946 if ((ifthen_state & 0xf) == 0)
5947 ifthen_state = 0;
5948}
5949
b0e28b39
DJ		 5950/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
5951 mapping symbol. */
5952
5953static int
5954is_mapping_symbol (struct disassemble_info *info, int n,
5955 enum map_type *map_type)
5956{
5957 const char *name;
5958
5959 name = bfd_asymbol_name (info->symtab[n]);
5960 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
5961 && (name[2] == 0 || name[2] == '.'))
5962 {
5963 *map_type = ((name[1] == 'a') ? MAP_ARM
5964 : (name[1] == 't') ? MAP_THUMB
5965 : MAP_DATA);
5966 return TRUE;
5967 }
5968
5969 return FALSE;
5970}
5971
5972/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
5973 Returns nonzero if *MAP_TYPE was set. */
5974
5975static int
5976get_map_sym_type (struct disassemble_info *info,
5977 int n,
5978 enum map_type *map_type)
5979{
5980 /* If the symbol is in a different section, ignore it. */
5981 if (info->section != NULL && info->section != info->symtab[n]->section)
5982 return FALSE;
5983
5984 return is_mapping_symbol (info, n, map_type);
5985}
5986
5987/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 5988 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 5989
5990static int
fe56b6ce
NC		 5991get_sym_code_type (struct disassemble_info *info,
5992 int n,
e821645d 5993 enum map_type *map_type)
2087ad84
PB		 5994{
5995 elf_symbol_type *es;
5996 unsigned int type;
b0e28b39
DJ		 5997
5998 /* If the symbol is in a different section, ignore it. */
5999 if (info->section != NULL && info->section != info->symtab[n]->section)
6000 return FALSE;
2087ad84 6001
e821645d 6002 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6003 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6004
6005 /* If the symbol has function type then use that. */
34e77a92 6006 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6007 {
35fc36a8
RS		 6008 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6009 *map_type = MAP_THUMB;
6010 else
6011 *map_type = MAP_ARM;
2087ad84
PB		 6012 return TRUE;
6013 }
6014
2087ad84
PB		 6015 return FALSE;
6016}
6017
0313a2b8
NC		 6018/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6019 of the supplied arm_feature_set structure with bitmasks indicating
6020 the support base architectures and coprocessor extensions.
6021
6022 FIXME: This could more efficiently implemented as a constant array,
6023 although it would also be less robust. */
6024
6025static void
6026select_arm_features (unsigned long mach,
6027 arm_feature_set * features)
6028{
823d2571
TG		 6029#undef ARM_FEATURE_LOW
6030#define ARM_FEATURE_LOW(ARCH1,CEXT) \
6031 features->core[0] = (ARCH1); \
6032 features->core[1] = 0; \
0313a2b8
NC		 6033 features->coproc = (CEXT) | FPU_FPA; \
6034 return
6035
823d2571
TG		 6036#undef ARM_FEATURE_CORE_LOW
6037#define ARM_FEATURE_CORE_LOW(ARCH1) \
6038 features->core[0] = (ARCH1); \
6039 features->core[1] = 0; \
6040 features->coproc = FPU_FPA; \
6041 return
6042
0313a2b8
NC		 6043 switch (mach)
6044 {
6045 case bfd_mach_arm_2: ARM_ARCH_V2;
6046 case bfd_mach_arm_2a: ARM_ARCH_V2S;
6047 case bfd_mach_arm_3: ARM_ARCH_V3;
6048 case bfd_mach_arm_3M: ARM_ARCH_V3M;
6049 case bfd_mach_arm_4: ARM_ARCH_V4;
6050 case bfd_mach_arm_4T: ARM_ARCH_V4T;
6051 case bfd_mach_arm_5: ARM_ARCH_V5;
6052 case bfd_mach_arm_5T: ARM_ARCH_V5T;
6053 case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
6054 case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
823d2571
TG		 6055 case bfd_mach_arm_ep9312: ARM_FEATURE_LOW (ARM_AEXT_V4T, \
6056 ARM_CEXT_MAVERICK \
6057 | FPU_MAVERICK);
0313a2b8
NC		 6058 case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
6059 case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
6060 /* If the machine type is unknown allow all
6061 architecture types and all extensions. */
823d2571 6062 case bfd_mach_arm_unknown: ARM_FEATURE_LOW (-1UL, -1UL);
0313a2b8
NC		 6063 default:
6064 abort ();
6065 }
6066}
6067
6068
58efb6c0
NC		 6069/* NOTE: There are no checks in these routines that
6070 the relevant number of data bytes exist. */
baf0cc5e 6071
58efb6c0 6072static int
4a5329c6 6073print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6074{
c19d1205
ZW		 6075 unsigned char b[4];
6076 long given;
6077 int status;
e821645d 6078 int is_thumb = FALSE;
b0e28b39 6079 int is_data = FALSE;
bd2e2557 6080 int little_code;
e821645d 6081 unsigned int size = 4;
4a5329c6 6082 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6083 bfd_boolean found = FALSE;
b0e28b39 6084 struct arm_private_data *private_data;
58efb6c0 6085
dd92f639
NC		 6086 if (info->disassembler_options)
6087 {
6088 parse_disassembler_options (info->disassembler_options);
b34976b6 6089
58efb6c0 6090 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6091 info->disassembler_options = NULL;
6092 }
b34976b6 6093
0313a2b8
NC		 6094 /* PR 10288: Control which instructions will be disassembled. */
6095 if (info->private_data == NULL)
6096 {
b0e28b39 6097 static struct arm_private_data private;
0313a2b8
NC		 6098
6099 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6100 /* If the user did not use the -m command line switch then default to
6101 disassembling all types of ARM instruction.
6102
6103 The info->mach value has to be ignored as this will be based on
6104 the default archictecture for the target and/or hints in the notes
6105 section, but it will never be greater than the current largest arm
6106 machine value (iWMMXt2), which is only equivalent to the V5TE
6107 architecture. ARM architectures have advanced beyond the machine
6108 value encoding, and these newer architectures would be ignored if
6109 the machine value was used.
6110
6111 Ie the -m switch is used to restrict which instructions will be
6112 disassembled. If it is necessary to use the -m switch to tell
6113 objdump that an ARM binary is being disassembled, eg because the
6114 input is a raw binary file, but it is also desired to disassemble
6115 all ARM instructions then use "-marm". This will select the
6116 "unknown" arm architecture which is compatible with any ARM
6117 instruction. */
6118 info->mach = bfd_mach_arm_unknown;
6119
6120 /* Compute the architecture bitmask from the machine number.
6121 Note: This assumes that the machine number will not change
6122 during disassembly.... */
b0e28b39 6123 select_arm_features (info->mach, & private.features);
0313a2b8 6124
b0e28b39 6125 private.has_mapping_symbols = -1;
1fbaefec
PB		 6126 private.last_mapping_sym = -1;
6127 private.last_mapping_addr = 0;
b0e28b39
DJ		 6128
6129 info->private_data = & private;
0313a2b8 6130 }
b0e28b39
DJ		 6131
6132 private_data = info->private_data;
6133
bd2e2557
SS		 6134 /* Decide if our code is going to be little-endian, despite what the
6135 function argument might say. */
6136 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6137
b0e28b39
DJ		 6138 /* For ELF, consult the symbol table to determine what kind of code
6139 or data we have. */
8977d4b2 6140 if (info->symtab_size != 0
e821645d
DJ		 6141 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6142 {
6143 bfd_vma addr;
b0e28b39 6144 int n, start;
e821645d 6145 int last_sym = -1;
b0e28b39 6146 enum map_type type = MAP_ARM;
e821645d 6147
e821645d
DJ		 6148 /* Start scanning at the start of the function, or wherever
6149 we finished last time. */
6750a3a7
NC		 6150 /* PR 14006. When the address is 0 we are either at the start of the
6151 very first function, or else the first function in a new, unlinked
6152 executable section (eg because uf -ffunction-sections). Either way
6153 start scanning from the beginning of the symbol table, not where we
6154 left off last time. */
6155 if (pc == 0)
6156 start = 0;
6157 else
6158 {
6159 start = info->symtab_pos + 1;
6160 if (start < private_data->last_mapping_sym)
6161 start = private_data->last_mapping_sym;
6162 }
b0e28b39 6163 found = FALSE;
e821645d 6164
b0e28b39
DJ		 6165 /* First, look for mapping symbols. */
6166 if (private_data->has_mapping_symbols != 0)
e821645d 6167 {
b0e28b39
DJ		 6168 /* Scan up to the location being disassembled. */
6169 for (n = start; n < info->symtab_size; n++)
6170 {
6171 addr = bfd_asymbol_value (info->symtab[n]);
6172 if (addr > pc)
6173 break;
6174 if (get_map_sym_type (info, n, &type))
6175 {
6176 last_sym = n;
6177 found = TRUE;
6178 }
6179 }
6180
6181 if (!found)
6182 {
6183 /* No mapping symbol found at this address. Look backwards
cc643b88 6184 for a preceding one. */
b0e28b39
DJ		 6185 for (n = start - 1; n >= 0; n--)
6186 {
6187 if (get_map_sym_type (info, n, &type))
6188 {
6189 last_sym = n;
6190 found = TRUE;
6191 break;
6192 }
6193 }
6194 }
6195
6196 if (found)
6197 private_data->has_mapping_symbols = 1;
6198
6199 /* No mapping symbols were found. A leading $d may be
6200 omitted for sections which start with data; but for
6201 compatibility with legacy and stripped binaries, only
6202 assume the leading $d if there is at least one mapping
6203 symbol in the file. */
6204 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6205 {
b0e28b39
DJ		 6206 /* Look for mapping symbols, in any section. */
6207 for (n = 0; n < info->symtab_size; n++)
6208 if (is_mapping_symbol (info, n, &type))
6209 {
6210 private_data->has_mapping_symbols = 1;
6211 break;
6212 }
6213 if (private_data->has_mapping_symbols == -1)
6214 private_data->has_mapping_symbols = 0;
6215 }
6216
6217 if (!found && private_data->has_mapping_symbols == 1)
6218 {
6219 type = MAP_DATA;
e821645d
DJ		 6220 found = TRUE;
6221 }
6222 }
6223
b0e28b39
DJ		 6224 /* Next search for function symbols to separate ARM from Thumb
6225 in binaries without mapping symbols. */
e821645d
DJ		 6226 if (!found)
6227 {
b0e28b39
DJ		 6228 /* Scan up to the location being disassembled. */
6229 for (n = start; n < info->symtab_size; n++)
e821645d 6230 {
b0e28b39
DJ		 6231 addr = bfd_asymbol_value (info->symtab[n]);
6232 if (addr > pc)
6233 break;
6234 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6235 {
6236 last_sym = n;
6237 found = TRUE;
b0e28b39
DJ		 6238 }
6239 }
6240
6241 if (!found)
6242 {
6243 /* No mapping symbol found at this address. Look backwards
cc643b88 6244 for a preceding one. */
b0e28b39
DJ		 6245 for (n = start - 1; n >= 0; n--)
6246 {
6247 if (get_sym_code_type (info, n, &type))
6248 {
6249 last_sym = n;
6250 found = TRUE;
6251 break;
6252 }
e821645d
DJ		 6253 }
6254 }
6255 }
6256
1fbaefec
PB		 6257 private_data->last_mapping_sym = last_sym;
6258 private_data->last_type = type;
6259 is_thumb = (private_data->last_type == MAP_THUMB);
6260 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6261
e821645d
DJ		 6262 /* Look a little bit ahead to see if we should print out
6263 two or four bytes of data. If there's a symbol,
6264 mapping or otherwise, after two bytes then don't
6265 print more. */
6266 if (is_data)
6267 {
6268 size = 4 - (pc & 3);
6269 for (n = last_sym + 1; n < info->symtab_size; n++)
6270 {
6271 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6272 if (addr > pc
6273 && (info->section == NULL
6274 || info->section == info->symtab[n]->section))
e821645d
DJ		 6275 {
6276 if (addr - pc < size)
6277 size = addr - pc;
6278 break;
6279 }
6280 }
6281 /* If the next symbol is after three bytes, we need to
6282 print only part of the data, so that we can use either
6283 .byte or .short. */
6284 if (size == 3)
6285 size = (pc & 1) ? 1 : 2;
6286 }
6287 }
6288
6289 if (info->symbols != NULL)
252b5132 6290 {
5876e06d
NC		 6291 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6292 {
2f0ca46a 6293 coff_symbol_type * cs;
b34976b6 6294
5876e06d
NC		 6295 cs = coffsymbol (*info->symbols);
6296 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6297 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6298 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6299 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6300 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6301 }
e821645d
DJ		 6302 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6303 && !found)
5876e06d 6304 {
2087ad84
PB		 6305 /* If no mapping symbol has been found then fall back to the type
6306 of the function symbol. */
e821645d
DJ		 6307 elf_symbol_type * es;
6308 unsigned int type;
2087ad84 6309
e821645d
DJ		 6310 es = *(elf_symbol_type **)(info->symbols);
6311 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6312
35fc36a8
RS		 6313 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6314 == ST_BRANCH_TO_THUMB)
6315 || type == STT_ARM_16BIT);
5876e06d
NC		 6316 }
6317 }
b34976b6 6318
e821645d
DJ		 6319 if (force_thumb)
6320 is_thumb = TRUE;
6321
b8f9ee44
CL		 6322 if (is_data)
6323 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6324 else
6325 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6326
c19d1205 6327 info->bytes_per_line = 4;
252b5132 6328
1316c8b3
NC		 6329 /* PR 10263: Disassemble data if requested to do so by the user. */
6330 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6331 {
6332 int i;
6333
1316c8b3 6334 /* Size was already set above. */
e821645d
DJ		 6335 info->bytes_per_chunk = size;
6336 printer = print_insn_data;
6337
fe56b6ce 6338 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6339 given = 0;
6340 if (little)
6341 for (i = size - 1; i >= 0; i--)
6342 given = b[i] | (given << 8);
6343 else
6344 for (i = 0; i < (int) size; i++)
6345 given = b[i] | (given << 8);
6346 }
6347 else if (!is_thumb)
252b5132 6348 {
c19d1205
ZW		 6349 /* In ARM mode endianness is a straightforward issue: the instruction
6350 is four bytes long and is either ordered 0123 or 3210. */
6351 printer = print_insn_arm;
6352 info->bytes_per_chunk = 4;
4a5329c6 6353 size = 4;
c19d1205 6354
0313a2b8 6355 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6356 if (little_code)
c19d1205
ZW		 6357 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6358 else
6359 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6360 }
58efb6c0 6361 else
252b5132 6362 {
c19d1205
ZW		 6363 /* In Thumb mode we have the additional wrinkle of two
6364 instruction lengths. Fortunately, the bits that determine
6365 the length of the current instruction are always to be found
6366 in the first two bytes. */
4a5329c6 6367 printer = print_insn_thumb16;
c19d1205 6368 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6369 size = 2;
6370
fe56b6ce 6371 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6372 if (little_code)
9a2ff3f5
AM		 6373 given = (b[0]) | (b[1] << 8);
6374 else
6375 given = (b[1]) | (b[0] << 8);
6376
c19d1205 6377 if (!status)
252b5132 6378 {
c19d1205
ZW		 6379 /* These bit patterns signal a four-byte Thumb
6380 instruction. */
6381 if ((given & 0xF800) == 0xF800
6382 || (given & 0xF800) == 0xF000
6383 || (given & 0xF800) == 0xE800)
252b5132 6384 {
0313a2b8 6385 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6386 if (little_code)
c19d1205 6387 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6388 else
c19d1205
ZW		 6389 given = (b[1]) | (b[0] << 8) | (given << 16);
6390
6391 printer = print_insn_thumb32;
4a5329c6 6392 size = 4;
252b5132 6393 }
252b5132 6394 }
c22aaad1
PB		 6395
6396 if (ifthen_address != pc)
0313a2b8 6397 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6398
6399 if (ifthen_state)
6400 {
6401 if ((ifthen_state & 0xf) == 0x8)
6402 ifthen_next_state = 0;
6403 else
6404 ifthen_next_state = (ifthen_state & 0xe0)
6405 | ((ifthen_state & 0xf) << 1);
6406 }
252b5132 6407 }
b34976b6 6408
c19d1205
ZW		 6409 if (status)
6410 {
6411 info->memory_error_func (status, pc, info);
6412 return -1;
6413 }
6a56ec7e
NC		 6414 if (info->flags & INSN_HAS_RELOC)
6415 /* If the instruction has a reloc associated with it, then
6416 the offset field in the instruction will actually be the
6417 addend for the reloc. (We are using REL type relocs).
6418 In such cases, we can ignore the pc when computing
6419 addresses, since the addend is not currently pc-relative. */
6420 pc = 0;
b34976b6 6421
4a5329c6 6422 printer (pc, info, given);
c22aaad1
PB		 6423
6424 if (is_thumb)
6425 {
6426 ifthen_state = ifthen_next_state;
6427 ifthen_address += size;
6428 }
4a5329c6 6429 return size;
252b5132
RH		 6430}
6431
6432int
4a5329c6 6433print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6434{
bd2e2557
SS		 6435 /* Detect BE8-ness and record it in the disassembler info. */
6436 if (info->flavour == bfd_target_elf_flavour
6437 && info->section != NULL
6438 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6439 info->endian_code = BFD_ENDIAN_LITTLE;
6440
b34976b6 6441 return print_insn (pc, info, FALSE);
58efb6c0 6442}
01c7f630 6443
58efb6c0 6444int
4a5329c6 6445print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6446{
b34976b6 6447 return print_insn (pc, info, TRUE);
58efb6c0 6448}
252b5132 6449
58efb6c0 6450void
4a5329c6 6451print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6452{
6453 int i;
252b5132 6454
58efb6c0
NC		 6455 fprintf (stream, _("\n\
6456The following ARM specific disassembler options are supported for use with\n\
6457the -M switch:\n"));
b34976b6 6458
58efb6c0
NC		 6459 for (i = NUM_ARM_REGNAMES; i--;)
6460 fprintf (stream, " reg-names-%s %*c%s\n",
6461 regnames[i].name,
d5b2f4d6 6462 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6463 regnames[i].description);
6464
6465 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6466 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6467}
GDB Binutils - Deliverables
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