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[PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
73cd51e5
AV		 115 MVE_NONE
116};
117
118enum mve_unpredictable
119{
120 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
121 */
143275ea
AV		 122 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
123 fcB = 1 (vpt). */
124 UNPRED_R13, /* Unpredictable because r13 (sp) or
125 r15 (sp) used. */
9743db03 126 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 127 UNPRED_Q_GT_4, /* Unpredictable because
128 vec reg start > 4 (vld4/st4). */
129 UNPRED_Q_GT_6, /* Unpredictable because
130 vec reg start > 6 (vld2/st2). */
131 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
132 and WB bit = 1. */
73cd51e5
AV		 133 UNPRED_NONE /* No unpredictable behavior. */
134};
135
136enum mve_undefined
137{
9743db03 138 UNDEF_SIZE_3, /* undefined because size == 3. */
aef6d006
AV		 139 UNDEF_SIZE_3, /* undefined because size == 3. */
140 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
73cd51e5
AV		 141 UNDEF_NONE /* no undefined behavior. */
142};
143
6b5d3a4d
ZW		 144struct opcode32
145{
823d2571
TG		 146 arm_feature_set arch; /* Architecture defining this insn. */
147 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 148 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 149 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 150};
151
73cd51e5
AV		 152/* MVE opcodes. */
153
154struct mopcode32
155{
156 arm_feature_set arch; /* Architecture defining this insn. */
157 enum mve_instructions mve_op; /* Specific mve instruction for faster
158 decoding. */
159 unsigned long value; /* If arch is 0 then value is a sentinel. */
160 unsigned long mask; /* Recognise insn if (op & mask) == value. */
161 const char * assembler; /* How to disassemble this insn. */
162};
163
6b0dd094
AV		 164enum isa {
165 ANY,
166 T32,
167 ARM
168};
169
170
171/* Shared (between Arm and Thumb mode) opcode. */
172struct sopcode32
173{
174 enum isa isa; /* Execution mode instruction availability. */
175 arm_feature_set arch; /* Architecture defining this insn. */
176 unsigned long value; /* If arch is 0 then value is a sentinel. */
177 unsigned long mask; /* Recognise insn if (op & mask) == value. */
178 const char * assembler; /* How to disassemble this insn. */
179};
180
6b5d3a4d
ZW		 181struct opcode16
182{
823d2571 183 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 184 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 185 const char *assembler; /* How to disassemble this insn. */
186};
b7693d02 187
8f06b2d8 188/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 189
2fbad815 190 %% %
4a5329c6 191
c22aaad1 192 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 193 %q print shifter argument
e2efe87d
MGD		 194 %u print condition code (unconditional in ARM mode,
195 UNPREDICTABLE if not AL in Thumb)
4a5329c6 196 %A print address for ldc/stc/ldf/stf instruction
16980d0b 197 %B print vstm/vldm register list
efd6b359 198 %C print vscclrm register list
4a5329c6 199 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 200 %J print register for VLDR instruction
201 %K print address for VLDR instruction
4a5329c6
ZW		 202 %F print the COUNT field of a LFM/SFM instruction.
203 %P print floating point precision in arithmetic insn
204 %Q print floating point precision in ldf/stf insn
205 %R print floating point rounding mode
206
33399f07 207 %<bitfield>c print as a condition code (for vsel)
4a5329c6 208 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 209 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
210 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 211 %<bitfield>d print the bitfield in decimal
16980d0b 212 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 213 %<bitfield>x print the bitfield in hex
214 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 215 %<bitfield>f print a floating point constant if >7 else a
216 floating point register
4a5329c6
ZW		 217 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
218 %<bitfield>g print as an iWMMXt 64-bit register
219 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 220 %<bitfield>D print as a NEON D register
221 %<bitfield>Q print as a NEON Q register
c28eeff2 222 %<bitfield>V print as a NEON D or Q register
6f1c2142 223 %<bitfield>E print a quarter-float immediate value
4a5329c6 224
16980d0b 225 %y<code> print a single precision VFP reg.
2fbad815 226 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 227 %z<code> print a double precision VFP reg
2fbad815 228 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 229
16980d0b
JB		 230 %<bitfield>'c print specified char iff bitfield is all ones
231 %<bitfield>`c print specified char iff bitfield is all zeroes
232 %<bitfield>?ab... select from array of values in big endian order
43e65147 233
2fbad815 234 %L print as an iWMMXt N/M width field.
4a5329c6 235 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 236 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 237 versions.
238 %i print 5-bit immediate in bits 8,3..0
239 (print "32" when 0)
fe56b6ce 240 %r print register offset address for wldt/wstr instruction. */
2fbad815 241
21d799b5 242enum opcode_sentinel_enum
05413229
NC		 243{
244 SENTINEL_IWMMXT_START = 1,
245 SENTINEL_IWMMXT_END,
246 SENTINEL_GENERIC_START
247} opcode_sentinels;
248
aefd8a40 249#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 250#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
251#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 252#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 253
8f06b2d8 254/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 255
6b0dd094 256static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 257{
2fbad815 258 /* XScale instructions. */
6b0dd094 259 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 260 0x0e200010, 0x0fff0ff0,
261 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 262 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 263 0x0e280010, 0x0fff0ff0,
264 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 265 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 266 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 267 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 268 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 269 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 270 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 271
2fbad815 272 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 273 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
274 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 275 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 276 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 277 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 278 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 279 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 280 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 281 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 282 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 283 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 284 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 285 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 286 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 287 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 288 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 289 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 290 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 291 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 292 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 293 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 294 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 295 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 296 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 297 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 298 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 299 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 300 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 301 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 302 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 303 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 304 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 305 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 306 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 307 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 308 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 309 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 310 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 311 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 312 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 313 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 314 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 315 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 316 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 317 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 318 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 319 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 320 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 321 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 322 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 323 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 324 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 325 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 326 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 327 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 328 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 329 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 330 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 331 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 332 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 333 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 334 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 335 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 336 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 337 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 338 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 339 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 340 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 341 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 342 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 343 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 344 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 345 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 346 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 347 0x0e800120, 0x0f800ff0,
348 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 349 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 350 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 351 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 352 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 353 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 354 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 355 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 356 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 357 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 358 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 359 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 360 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 361 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 362 0x0e8000a0, 0x0f800ff0,
363 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 364 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 365 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 366 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 367 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 368 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 369 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 370 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 371 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 372 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 373 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 374 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 375 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 376 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 377 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 378 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 379 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 380 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 381 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 382 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 383 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 384 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 385 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 386 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 387 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 388 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 389 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 390 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 391 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 392 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 393 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 394 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 395 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 396 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 397 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 398 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 399 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 400 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 401 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 402 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 403 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 404 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 405 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 406 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 407 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 408 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 409 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 410 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 411 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 412 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 413 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 414 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 415 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 416 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 417 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 418 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 419 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 420 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 421 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 422 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 423 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 424 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 425 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 426 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 427 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 428
fe56b6ce 429 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 430 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 431 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 432 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 433 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 434 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 435 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 436 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 437 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 438 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 439 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 440 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 441 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 443 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 444 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 445 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 446 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 447 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 448 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 449 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 450 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 451 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 452 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 453 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 454 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 455 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 456 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 457 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 458 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 459 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 460 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 461 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 462 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 463 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 464 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 465 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 467 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 469 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 470 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 471 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 473 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 475 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 477 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 478 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 479 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 480 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 481 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 483 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 485 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 487 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 489 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 491 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 493 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 495 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 497 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 499 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 501 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 503 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 505 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 507 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 509 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 511 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 513 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 515 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 516
efd6b359
AV		 517 /* Armv8.1-M Mainline instructions. */
518 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
519 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
520 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
521 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
522
16a1fa25 523 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 524 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 525 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 526 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 527 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
528
fe56b6ce 529 /* Register load/store. */
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 531 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 533 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 535 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 537 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 539 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 541 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 543 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 545 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 547 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 549 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 551 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 553 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 554 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 555 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 557 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 559 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 561 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 562 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
563 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
564 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
565 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 566
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 568 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 570 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 572 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 574 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 575
fe56b6ce 576 /* Data transfer between ARM and NEON registers. */
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 578 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 580 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 582 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 584 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 586 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 588 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 590 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 592 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 593 /* Half-precision conversion instructions. */
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 595 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 597 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 599 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 601 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 602
fe56b6ce 603 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 605 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 607 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 609 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 611 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 613 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 615 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 617 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 619 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 621 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 623 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 625 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 627 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 629 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 631 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 633 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 635 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 637 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 639 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 641 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 643 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 645 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 647 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 649 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 651 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 653 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 655 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 657 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 659 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 661 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 663 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 665 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 667 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 669 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 671 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 673 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 675 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 677 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 679 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 681 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 683 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 685 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 687 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 689 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 691 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 693 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 695 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 697 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 699 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 701 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 703 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 705 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 707 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 709 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 711 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 713 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 715 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 717 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 719 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 721 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 723 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 725 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 727 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 729 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 731 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 733 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 735 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 737 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 739 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 741 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 742
743 /* Cirrus coprocessor instructions. */
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 745 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 747 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 749 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 751 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 753 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 755 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 757 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 759 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 761 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 763 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 765 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 767 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 768 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 769 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 770 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 771 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 772 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 773 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 775 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 777 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 779 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 781 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 783 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 785 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 787 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 789 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 791 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 793 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 795 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 797 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 799 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 801 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 803 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 805 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 807 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 808 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 809 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 811 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 812 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 813 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 814 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 815 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 817 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 819 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 821 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 823 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 825 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 827 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 829 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 831 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 833 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 835 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 837 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 839 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 840 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 841 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 843 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 845 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 847 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 849 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 851 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 853 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 855 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 857 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 859 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 861 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 863 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 865 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 867 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 869 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 871 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 873 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 875 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 877 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 879 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 881 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 883 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 885 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 887 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 889 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 891 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 893 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 895 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 897 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 899 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 901 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 903 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 905 0x0e000600, 0x0ff00f10,
906 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 908 0x0e100600, 0x0ff00f10,
909 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 911 0x0e200600, 0x0ff00f10,
912 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 914 0x0e300600, 0x0ff00f10,
915 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 916
62f3b8c8 917 /* VFP Fused multiply add instructions. */
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 919 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 921 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 923 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 925 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 927 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 929 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 931 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 933 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 934
33399f07 935 /* FP v5. */
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 937 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 939 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 941 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 943 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 945 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 947 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 949 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 951 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 953 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 955 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 957 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 959 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 960
05413229 961 /* Generic coprocessor instructions. */
6b0dd094
AV		 962 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
963 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 964 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 965 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 966 0x0c500000, 0x0ff00000,
967 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 968 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 969 0x0e000000, 0x0f000010,
970 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 971 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 972 0x0e10f010, 0x0f10f010,
973 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 974 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 975 0x0e100010, 0x0f100010,
976 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 977 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 978 0x0e000010, 0x0f100010,
979 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 980 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 981 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 982 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 983 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 984
05413229 985 /* V6 coprocessor instructions. */
6b0dd094 986 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 987 0xfc500000, 0xfff00000,
988 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 989 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 990 0xfc400000, 0xfff00000,
991 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 992
c28eeff2 993 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 994 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 995 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 996 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 997 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 998 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 999 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1000 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1001 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1002 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1003 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1004 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1005 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1006 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1007 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1008 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1009 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1010 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1011 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1012 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1013 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1014
c604a79a 1015 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1017 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1019 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1020
dec41383 1021 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1022 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1023 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1024 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1025 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1026 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1027 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1028 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1029 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1030 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1031 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1032 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1033 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1034 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1035 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1036 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1037 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1038
05413229 1039 /* V5 coprocessor instructions. */
6b0dd094 1040 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1041 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1042 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1043 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1044 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1045 0xfe000000, 0xff000010,
1046 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1047 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1048 0xfe000010, 0xff100010,
1049 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1050 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1051 0xfe100010, 0xff100010,
1052 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1053
b0c11777
RL		 1054 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1055 cp_num: bit <11:8> == 0b1001.
1056 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1057 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1058 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1059 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1060 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1061 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1062 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1063 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1064 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1065 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1066 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1067 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1068 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1069 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1070 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1071 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1072 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1073 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1074 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1076 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1077 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1078 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1079 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1080 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1081 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1082 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1083 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1084 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1085 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1086 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1088 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1090 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1092 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1094 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1096 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1098 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1100 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1102 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1103 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1104 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1105 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1106 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1107 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1108 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1109 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1110 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1111 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1112 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1113 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1114 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1115 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1116 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1117 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1118 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1120 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1121 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1122 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1123 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1124 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1125 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1126 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1127
49e8a725 1128 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1129 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1130 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1131
6b0dd094 1132 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1133};
1134
16980d0b
JB		 1135/* Neon opcode table: This does not encode the top byte -- that is
1136 checked by the print_insn_neon routine, as it depends on whether we are
1137 doing thumb32 or arm32 disassembly. */
1138
1139/* print_insn_neon recognizes the following format control codes:
1140
1141 %% %
1142
c22aaad1 1143 %c print condition code
e2efe87d
MGD		 1144 %u print condition code (unconditional in ARM mode,
1145 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1146 %A print v{st,ld}[1234] operands
1147 %B print v{st,ld}[1234] any one operands
1148 %C print v{st,ld}[1234] single->all operands
1149 %D print scalar
1150 %E print vmov, vmvn, vorr, vbic encoded constant
1151 %F print vtbl,vtbx register list
1152
1153 %<bitfield>r print as an ARM register
1154 %<bitfield>d print the bitfield in decimal
1155 %<bitfield>e print the 2^N - bitfield in decimal
1156 %<bitfield>D print as a NEON D register
1157 %<bitfield>Q print as a NEON Q register
1158 %<bitfield>R print as a NEON D or Q register
1159 %<bitfield>Sn print byte scaled width limited by n
1160 %<bitfield>Tn print short scaled width limited by n
1161 %<bitfield>Un print long scaled width limited by n
43e65147 1162
16980d0b
JB		 1163 %<bitfield>'c print specified char iff bitfield is all ones
1164 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1165 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1166
1167static const struct opcode32 neon_opcodes[] =
1168{
fe56b6ce 1169 /* Extract. */
823d2571
TG		 1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf2b00840, 0xffb00850,
1172 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf2b00000, 0xffb00810,
1175 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1176
9743db03
AV		 1177 /* Data transfer between ARM and NEON registers. */
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1187 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1190
fe56b6ce 1191 /* Move data element to all lanes. */
823d2571
TG		 1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1193 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1198
fe56b6ce 1199 /* Table lookup. */
823d2571
TG		 1200 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1201 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1203 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1204
8e79c3df 1205 /* Half-precision conversions. */
823d2571
TG		 1206 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1207 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1208 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1209 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1210
1211 /* NEON fused multiply add instructions. */
823d2571 1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1213 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1214 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1215 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1217 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1218 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1219 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1220
fe56b6ce 1221 /* Two registers, miscellaneous. */
823d2571
TG		 1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1223 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1225 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1227 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1229 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1230 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1231 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1232 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1233 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1234 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1235 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1236 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1237 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1238 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1239 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1240 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1241 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1242 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1243 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf3b20300, 0xffb30fd0,
1266 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1314 0xf3bb0600, 0xffbf0e10,
823d2571 1315 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317 0xf3b70600, 0xffbf0e10,
1318 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1319
fe56b6ce 1320 /* Three registers of the same length. */
823d2571
TG		 1321 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1322 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1323 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1324 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1326 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1328 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1330 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1332 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1333 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1334 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1336 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1338 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1340 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1360 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1362 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1363 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1364 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1366 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1368 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1370 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1372 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1374 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1376 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1378 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1380 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1382 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1384 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1386 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1388 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1390 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1392 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1394 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1396 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1398 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1400 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1402 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1404 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1406 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1408 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1412 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1414 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1416 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1418 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1420 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1422 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1424 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1426 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1428 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1430 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2000b00, 0xff800f10,
1439 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2000b10, 0xff800f10,
1442 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3000b00, 0xff800f10,
1451 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2000000, 0xfe800f10,
1454 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2000010, 0xfe800f10,
1457 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2000100, 0xfe800f10,
1460 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2000200, 0xfe800f10,
1463 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2000210, 0xfe800f10,
1466 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2000300, 0xfe800f10,
1469 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2000310, 0xfe800f10,
1472 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf2000400, 0xfe800f10,
1475 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf2000410, 0xfe800f10,
1478 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2000500, 0xfe800f10,
1481 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2000510, 0xfe800f10,
1484 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2000600, 0xfe800f10,
1487 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2000610, 0xfe800f10,
1490 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2000700, 0xfe800f10,
1493 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2000710, 0xfe800f10,
1496 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2000910, 0xfe800f10,
1499 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2000a00, 0xfe800f10,
1502 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2000a10, 0xfe800f10,
1505 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1507 0xf3000b10, 0xff800f10,
1508 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1510 0xf3000c10, 0xff800f10,
1511 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1512
fe56b6ce 1513 /* One register and an immediate value. */
823d2571
TG		 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1540
fe56b6ce 1541 /* Two registers and a shift amount. */
823d2571
TG		 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf2880950, 0xfeb80fd0,
1554 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2900950, 0xfeb00fd0,
1577 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2a00950, 0xfea00fd0,
1622 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2a00e10, 0xfea00e90,
1661 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1663 0xf2a00c10, 0xfea00e90,
1664 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1665
fe56b6ce 1666 /* Three registers of different lengths. */
823d2571
TG		 1667 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1668 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2800400, 0xff800f50,
1673 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2800600, 0xff800f50,
1676 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2800900, 0xff800f50,
1679 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2800b00, 0xff800f50,
1682 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2800d00, 0xff800f50,
1685 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf3800400, 0xff800f50,
1688 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf3800600, 0xff800f50,
1691 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2800000, 0xfe800f50,
1694 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2800100, 0xfe800f50,
1697 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2800200, 0xfe800f50,
1700 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2800300, 0xfe800f50,
1703 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2800500, 0xfe800f50,
1706 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2800700, 0xfe800f50,
1709 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf2800800, 0xfe800f50,
1712 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2800a00, 0xfe800f50,
1715 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2800c00, 0xfe800f50,
1718 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1719
fe56b6ce 1720 /* Two registers and a scalar. */
823d2571
TG		 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1724 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1725 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1726 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1732 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1733 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1734 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1740 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1741 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1742 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1752 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1753 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1754 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1758 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1759 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1760 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1764 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1765 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1766 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1772 0xf2800240, 0xfe800f50,
1773 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2800640, 0xfe800f50,
1776 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2800a40, 0xfe800f50,
1779 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1781 0xf2800e40, 0xff800f50,
1782 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1784 0xf2800f40, 0xff800f50,
1785 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1787 0xf3800e40, 0xff800f50,
1788 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1790 0xf3800f40, 0xff800f50,
1791 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1792 },
16980d0b 1793
fe56b6ce 1794 /* Element and structure load/store. */
823d2571
TG		 1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1833
1834 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1835};
1836
73cd51e5
AV		 1837/* mve opcode table. */
1838
1839/* print_insn_mve recognizes the following format control codes:
1840
1841 %% %
1842
9743db03 1843 %c print condition code
aef6d006
AV		 1844 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1845 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea
AV		 1846 %i print MVE predicate(s) for vpt and vpst
1847 %n print vector comparison code for predicated instruction
1848 %v print vector predicate for instruction in predicated
1849 block
04d54ace
AV		 1850 %w print writeback mode for MVE v{st,ld}[24]
1851 %B print v{st,ld}[24] any one operands
1852
9743db03 1853 %<bitfield>r print as an ARM register
04d54ace 1854 %<bitfield>d print the bitfield in decimal
143275ea
AV		 1855 %<bitfield>Q print as a MVE Q register
1856 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1857 UNPREDICTABLE
1858 %<bitfield>s print size for vector predicate & non VMOV instructions
1859*/
73cd51e5
AV		 1860
1861static const struct mopcode32 mve_opcodes[] =
1862{
143275ea
AV		 1863 /* MVE. */
1864
1865 {ARM_FEATURE_COPROC (FPU_MVE),
1866 MVE_VPST,
1867 0xfe310f4d, 0xffbf1fff,
1868 "vpst%i"
1869 },
1870
1871 /* Floating point VPT T1. */
1872 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1873 MVE_VPT_FP_T1,
1874 0xee310f00, 0xefb10f50,
1875 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1876 /* Floating point VPT T2. */
1877 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1878 MVE_VPT_FP_T2,
1879 0xee310f40, 0xefb10f50,
1880 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1881
1882 /* Vector VPT T1. */
1883 {ARM_FEATURE_COPROC (FPU_MVE),
1884 MVE_VPT_VEC_T1,
1885 0xfe010f00, 0xff811f51,
1886 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1887 /* Vector VPT T2. */
1888 {ARM_FEATURE_COPROC (FPU_MVE),
1889 MVE_VPT_VEC_T2,
1890 0xfe010f01, 0xff811f51,
1891 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1892 /* Vector VPT T3. */
1893 {ARM_FEATURE_COPROC (FPU_MVE),
1894 MVE_VPT_VEC_T3,
1895 0xfe011f00, 0xff811f50,
1896 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1897 /* Vector VPT T4. */
1898 {ARM_FEATURE_COPROC (FPU_MVE),
1899 MVE_VPT_VEC_T4,
1900 0xfe010f40, 0xff811f70,
1901 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1902 /* Vector VPT T5. */
1903 {ARM_FEATURE_COPROC (FPU_MVE),
1904 MVE_VPT_VEC_T5,
1905 0xfe010f60, 0xff811f70,
1906 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1907 /* Vector VPT T6. */
1908 {ARM_FEATURE_COPROC (FPU_MVE),
1909 MVE_VPT_VEC_T6,
1910 0xfe011f40, 0xff811f50,
1911 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1912
1913 /* Vector VCMP floating point T1. */
1914 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1915 MVE_VCMP_FP_T1,
1916 0xee310f00, 0xeff1ef50,
1917 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1918
1919 /* Vector VCMP floating point T2. */
1920 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1921 MVE_VCMP_FP_T2,
1922 0xee310f40, 0xeff1ef50,
1923 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1924
1925 /* Vector VCMP T1. */
1926 {ARM_FEATURE_COPROC (FPU_MVE),
1927 MVE_VCMP_VEC_T1,
1928 0xfe010f00, 0xffc1ff51,
1929 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1930 /* Vector VCMP T2. */
1931 {ARM_FEATURE_COPROC (FPU_MVE),
1932 MVE_VCMP_VEC_T2,
1933 0xfe010f01, 0xffc1ff51,
1934 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1935 /* Vector VCMP T3. */
1936 {ARM_FEATURE_COPROC (FPU_MVE),
1937 MVE_VCMP_VEC_T3,
1938 0xfe011f00, 0xffc1ff50,
1939 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1940 /* Vector VCMP T4. */
1941 {ARM_FEATURE_COPROC (FPU_MVE),
1942 MVE_VCMP_VEC_T4,
1943 0xfe010f40, 0xffc1ff70,
1944 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1945 /* Vector VCMP T5. */
1946 {ARM_FEATURE_COPROC (FPU_MVE),
1947 MVE_VCMP_VEC_T5,
1948 0xfe010f60, 0xffc1ff70,
1949 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1950 /* Vector VCMP T6. */
1951 {ARM_FEATURE_COPROC (FPU_MVE),
1952 MVE_VCMP_VEC_T6,
1953 0xfe011f40, 0xffc1ff50,
1954 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1955
9743db03
AV		 1956 /* Vector VDUP. */
1957 {ARM_FEATURE_COPROC (FPU_MVE),
1958 MVE_VDUP,
1959 0xeea00b10, 0xffb10f5f,
1960 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1961
1962 /* Vector VEOR. */
1963 {ARM_FEATURE_COPROC (FPU_MVE),
1964 MVE_VEOR,
1965 0xff000150, 0xffd11f51,
1966 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1967
1968 /* Vector VFMA, vector * scalar. */
1969 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1970 MVE_VFMA_FP_SCALAR,
1971 0xee310e40, 0xefb11f70,
1972 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1973
1974 /* Vector VFMA floating point. */
1975 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1976 MVE_VFMA_FP,
1977 0xef000c50, 0xffa11f51,
1978 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1979
1980 /* Vector VFMS floating point. */
1981 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1982 MVE_VFMS_FP,
1983 0xef200c50, 0xffa11f51,
1984 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1985
1986 /* Vector VFMAS, vector * scalar. */
1987 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1988 MVE_VFMAS_FP_SCALAR,
1989 0xee311e40, 0xefb11f70,
1990 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1991
1992 /* Vector VHADD T1. */
1993 {ARM_FEATURE_COPROC (FPU_MVE),
1994 MVE_VHADD_T1,
1995 0xef000040, 0xef811f51,
1996 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1997
1998 /* Vector VHADD T2. */
1999 {ARM_FEATURE_COPROC (FPU_MVE),
2000 MVE_VHADD_T2,
2001 0xee000f40, 0xef811f70,
2002 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2003
2004 /* Vector VHSUB T1. */
2005 {ARM_FEATURE_COPROC (FPU_MVE),
2006 MVE_VHSUB_T1,
2007 0xef000240, 0xef811f51,
2008 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2009
2010 /* Vector VHSUB T2. */
2011 {ARM_FEATURE_COPROC (FPU_MVE),
2012 MVE_VHSUB_T2,
2013 0xee001f40, 0xef811f70,
2014 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2015
2016 /* Vector VDUP. */
2017 {ARM_FEATURE_COPROC (FPU_MVE),
2018 MVE_VDUP,
2019 0xeea00b10, 0xffb10f5f,
2020 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2021
2022 /* Vector VRHADD. */
2023 {ARM_FEATURE_COPROC (FPU_MVE),
2024 MVE_VRHADD,
2025 0xef000140, 0xef811f51,
2026 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2027
04d54ace
AV		 2028 /* Vector VLD2. */
2029 {ARM_FEATURE_COPROC (FPU_MVE),
2030 MVE_VLD2,
2031 0xfc901e00, 0xff901e5f,
2032 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2033
2034 /* Vector VLD4. */
2035 {ARM_FEATURE_COPROC (FPU_MVE),
2036 MVE_VLD4,
2037 0xfc901e01, 0xff901e1f,
2038 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2039
aef6d006
AV		 2040 /* Vector VLDRB. */
2041 {ARM_FEATURE_COPROC (FPU_MVE),
2042 MVE_VLDRB_T1,
2043 0xec100e00, 0xee581e00,
2044 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2045
2046 /* Vector VLDRH. */
2047 {ARM_FEATURE_COPROC (FPU_MVE),
2048 MVE_VLDRH_T2,
2049 0xec180e00, 0xee581e00,
2050 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2051
2052 /* Vector VLDRB unsigned, variant T5. */
2053 {ARM_FEATURE_COPROC (FPU_MVE),
2054 MVE_VLDRB_T5,
2055 0xec101e00, 0xfe101f80,
2056 "vldrb%v.u8\t%13-15,22Q, %d"},
2057
2058 /* Vector VLDRH unsigned, variant T6. */
2059 {ARM_FEATURE_COPROC (FPU_MVE),
2060 MVE_VLDRH_T6,
2061 0xec101e80, 0xfe101f80,
2062 "vldrh%v.u16\t%13-15,22Q, %d"},
2063
2064 /* Vector VLDRW unsigned, variant T7. */
2065 {ARM_FEATURE_COPROC (FPU_MVE),
2066 MVE_VLDRW_T7,
2067 0xec101f00, 0xfe101f80,
2068 "vldrw%v.u32\t%13-15,22Q, %d"},
2069
04d54ace
AV		 2070 /* Vector VST2 no writeback. */
2071 {ARM_FEATURE_COPROC (FPU_MVE),
2072 MVE_VST2,
2073 0xfc801e00, 0xffb01e5f,
2074 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2075
2076 /* Vector VST2 writeback. */
2077 {ARM_FEATURE_COPROC (FPU_MVE),
2078 MVE_VST2,
2079 0xfca01e00, 0xffb01e5f,
2080 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2081
2082 /* Vector VST4 no writeback. */
2083 {ARM_FEATURE_COPROC (FPU_MVE),
2084 MVE_VST4,
2085 0xfc801e01, 0xffb01e1f,
2086 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2087
2088 /* Vector VST4 writeback. */
2089 {ARM_FEATURE_COPROC (FPU_MVE),
2090 MVE_VST4,
2091 0xfca01e01, 0xffb01e1f,
2092 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2093
aef6d006
AV		 2094 /* Vector VSTRB. */
2095 {ARM_FEATURE_COPROC (FPU_MVE),
2096 MVE_VSTRB_T1,
2097 0xec000e00, 0xfe581e00,
2098 "vstrb%v.%7-8s\t%13-15Q, %d"},
2099
2100 /* Vector VSTRH. */
2101 {ARM_FEATURE_COPROC (FPU_MVE),
2102 MVE_VSTRH_T2,
2103 0xec080e00, 0xfe581e00,
2104 "vstrh%v.%7-8s\t%13-15Q, %d"},
2105
2106 /* Vector VSTRB variant T5. */
2107 {ARM_FEATURE_COPROC (FPU_MVE),
2108 MVE_VSTRB_T5,
2109 0xec001e00, 0xfe101f80,
2110 "vstrb%v.8\t%13-15,22Q, %d"},
2111
2112 /* Vector VSTRH variant T6. */
2113 {ARM_FEATURE_COPROC (FPU_MVE),
2114 MVE_VSTRH_T6,
2115 0xec001e80, 0xfe101f80,
2116 "vstrh%v.16\t%13-15,22Q, %d"},
2117
2118 /* Vector VSTRW variant T7. */
2119 {ARM_FEATURE_COPROC (FPU_MVE),
2120 MVE_VSTRW_T7,
2121 0xec001f00, 0xfe101f80,
2122 "vstrw%v.32\t%13-15,22Q, %d"},
2123
143275ea
AV		 2124 {ARM_FEATURE_CORE_LOW (0),
2125 MVE_NONE,
2126 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2127};
2128
8f06b2d8
PB		 2129/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2130 ordered: they must be searched linearly from the top to obtain a correct
2131 match. */
2132
2133/* print_insn_arm recognizes the following format control codes:
2134
2135 %% %
2136
2137 %a print address for ldr/str instruction
2138 %s print address for ldr/str halfword/signextend instruction
c1e26897 2139 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2140 %b print branch destination
2141 %c print condition code (always bits 28-31)
2142 %m print register mask for ldm/stm instruction
2143 %o print operand2 (immediate or register + shift)
2144 %p print 'p' iff bits 12-15 are 15
2145 %t print 't' iff bit 21 set and bit 24 clear
2146 %B print arm BLX(1) destination
2147 %C print the PSR sub type.
62b3e311
PB		 2148 %U print barrier type.
2149 %P print address for pli instruction.
8f06b2d8
PB		 2150
2151 %<bitfield>r print as an ARM register
9eb6c0f1 2152 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2153 %<bitfield>R as %r but r15 is UNPREDICTABLE
2154 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2155 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2156 %<bitfield>d print the bitfield in decimal
43e65147 2157 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2158 %<bitfield>x print the bitfield in hex
2159 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2160
16980d0b
JB		 2161 %<bitfield>'c print specified char iff bitfield is all ones
2162 %<bitfield>`c print specified char iff bitfield is all zeroes
2163 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2164
8f06b2d8
PB		 2165 %e print arm SMI operand (bits 0..7,8..19).
2166 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2167 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2168 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2169
8f06b2d8
PB		 2170static const struct opcode32 arm_opcodes[] =
2171{
2172 /* ARM instructions. */
823d2571
TG		 2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2176 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2177
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2179 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2181 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2183 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2185 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2187 0x00800090, 0x0fa000f0,
2188 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2190 0x00a00090, 0x0fa000f0,
2191 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2192
105bde57 2193 /* V8.2 RAS extension instructions. */
4d1464f2 2194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2195 0xe320f010, 0xffffffff, "esb"},
2196
53c4b28b 2197 /* V8 instructions. */
823d2571
TG		 2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2199 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2200 /* Defined in V8 but is in NOP space so available to all arch. */
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2202 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2203 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2204 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2205 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2206 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2208 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2210 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2211 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2212 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2213 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2214 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2215 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2216 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2217 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2218 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2219 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2220 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2221 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2222 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2223 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2224 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2225 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2226 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2227 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2228 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2229 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 2230 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 2231 /* CRC32 instructions. */
823d2571
TG		 2232 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2233 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2234 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2235 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2236 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2237 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2238 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2239 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2240 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2241 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2242 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2243 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 2244
ddfded2f
MW		 2245 /* Privileged Access Never extension instructions. */
2246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2247 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2248
90ec0d68 2249 /* Virtualization Extension instructions. */
823d2571
TG		 2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 2252
eea54501 2253 /* Integer Divide Extension instructions. */
823d2571
TG		 2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2255 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2257 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 2258
60e5ef9f 2259 /* MP Extension instructions. */
823d2571 2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 2261
c597cc3d
SD		 2262 /* Speculation Barriers. */
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2266
62b3e311 2267 /* V7 instructions. */
823d2571
TG		 2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2276 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 2277
c19d1205 2278 /* ARM V6T2 instructions. */
823d2571
TG		 2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2280 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2282 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2284 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2286 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2287
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2289 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2291 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2292
ff8646ee 2293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2294 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 2295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2296 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2298 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2300 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 2301
f4c65163 2302 /* ARM Security extension instructions. */
823d2571
TG		 2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2304 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 2305
8f06b2d8 2306 /* ARM V6K instructions. */
823d2571
TG		 2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2308 0xf57ff01f, 0xffffffff, "clrex"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2310 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2312 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2314 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2316 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2318 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2320 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 2321
7fadb25d
SD		 2322 /* ARMv8.5-A instructions. */
2323 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2324
8f06b2d8 2325 /* ARM V6K NOP hints. */
823d2571
TG		 2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2327 0x0320f001, 0x0fffffff, "yield%c"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2329 0x0320f002, 0x0fffffff, "wfe%c"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2331 0x0320f003, 0x0fffffff, "wfi%c"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2333 0x0320f004, 0x0fffffff, "sev%c"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2335 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 2336
fe56b6ce 2337 /* ARM V6 instructions. */
823d2571
TG		 2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2339 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2341 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2343 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2345 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2347 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2349 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2351 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2353 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2355 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2357 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2359 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2361 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2363 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2365 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2367 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2369 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2371 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2373 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2375 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2377 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2379 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2381 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2383 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2385 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2387 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2389 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2391 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2393 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2395 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2397 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2399 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2401 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2403 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2405 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2407 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2409 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2411 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2413 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2415 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2417 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2419 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2421 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2423 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2425 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2427 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2429 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2431 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2433 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2435 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2437 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2439 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2441 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2443 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2445 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2447 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2449 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2451 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2453 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2455 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2457 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2459 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2461 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2463 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2465 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2467 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2469 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2471 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2473 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2475 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2477 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2479 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2481 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2483 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2485 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2487 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2489 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2491 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2493 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2495 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2497 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2499 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2501 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2503 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2505 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2507 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2509 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2511 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2513 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2515 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2517 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2519 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2521 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2523 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2525 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2527 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2529 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2531 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2533 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2535 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2537 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2539 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2541 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2543 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2545 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2547 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2549 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2551 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2553 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2555 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2557 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2559 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2561 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2563 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2565 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2567 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2569 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2571 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2573 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2575 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2577 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2579 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2581 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2582
8f06b2d8 2583 /* V5J instruction. */
823d2571
TG		 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2585 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2586
8f06b2d8 2587 /* V5 Instructions. */
823d2571
TG		 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2589 0xe1200070, 0xfff000f0,
2590 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2592 0xfa000000, 0xfe000000, "blx\t%B"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2594 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2596 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2597
2598 /* V5E "El Segundo" Instructions. */
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2600 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2602 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2604 0xf450f000, 0xfc70f000, "pld\t%a"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2606 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2608 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2610 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2612 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2613
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2615 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2617 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2618
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2620 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2622 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2624 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2626 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2627
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2629 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2631 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2633 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2635 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2636
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2638 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2640 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2641
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2643 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2645 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2647 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2649 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2650
8f06b2d8 2651 /* ARM Instructions. */
823d2571
TG		 2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2653 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2654
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2656 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2658 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2660 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2662 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2664 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2666 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2667
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2669 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2671 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2673 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2675 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2676
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2678 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2680 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2682 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2684 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2685
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2687 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2689 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2691 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2692
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2694 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2696 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2698 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2699
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2701 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2703 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2705 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2706
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2708 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2710 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2712 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2713
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2715 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2717 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2719 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2720
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2722 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2724 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2726 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2727
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2729 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2731 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2733 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2734
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2736 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2738 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2740 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2741
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2743 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2745 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2747 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2748
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2750 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2752 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2754 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2755
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2757 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2759 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2761 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2762
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2764 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2766 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2768 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2769
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2771 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2773 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2775 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2776
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2778 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2780 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2782 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2783
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2785 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2787 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2789 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2791 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2793 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2795 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2797 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2798
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2800 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2802 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2804 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2805
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2807 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2809 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2811 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2812
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2814 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2816 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2817
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2819 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2820
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2822 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2824 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2825
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2827 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2829 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2831 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2833 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2835 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2837 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2839 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2841 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2843 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2845 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2847 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2849 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2851 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2853 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2855 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2857 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2859 0x092d0000, 0x0fff0000, "push%c\t%m"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2861 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2863 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2864
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2866 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2868 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2870 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2872 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2874 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2876 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2878 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2880 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2882 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2884 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2886 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2888 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2890 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2892 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2894 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2896 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2898 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2900 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2902 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2903
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2905 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2907 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2908
2909 /* The rest. */
4ab90a7a
AV		 2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2911 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2913 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2914 {ARM_FEATURE_CORE_LOW (0),
2915 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2916};
2917
2918/* print_insn_thumb16 recognizes the following format control codes:
2919
2920 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2921 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2922 %<bitfield>I print bitfield as a signed decimal
2923 (top bit of range being the sign bit)
2924 %N print Thumb register mask (with LR)
2925 %O print Thumb register mask (with PC)
2926 %M print Thumb register mask
2927 %b print CZB's 6-bit unsigned branch destination
2928 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2929 %c print the condition code
2930 %C print the condition code, or "s" if not conditional
2931 %x print warning if conditional an not at end of IT block"
2932 %X print "\t; unpredictable <IT:code>" if conditional
2933 %I print IT instruction suffix and operands
4547cb56 2934 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2935 %<bitfield>r print bitfield as an ARM register
2936 %<bitfield>d print bitfield as a decimal
2937 %<bitfield>H print (bitfield * 2) as a decimal
2938 %<bitfield>W print (bitfield * 4) as a decimal
2939 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2940 %<bitfield>B print Thumb branch destination (signed displacement)
2941 %<bitfield>c print bitfield as a condition code
2942 %<bitnum>'c print specified char iff bit is one
2943 %<bitnum>?ab print a if bit is one else print b. */
2944
2945static const struct opcode16 thumb_opcodes[] =
2946{
2947 /* Thumb instructions. */
2948
16a1fa25
TP		 2949 /* ARMv8-M Security Extensions instructions. */
2950 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2952
53c4b28b 2953 /* ARM V8 instructions. */
823d2571
TG		 2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2957
8f06b2d8 2958 /* ARM V6K no-argument instructions. */
823d2571
TG		 2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2965
2966 /* ARM V6T2 instructions. */
ff8646ee
TP		 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2968 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2970 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2972
2973 /* ARM V6. */
823d2571
TG		 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2985
2986 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2988 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2989 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2991 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2992 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2994 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2995 /* Format 4. */
823d2571
TG		 2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3012 /* format 13 */
823d2571
TG		 3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3015 /* format 5 */
823d2571
TG		 3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3020 /* format 14 */
823d2571
TG		 3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3023 /* format 2 */
823d2571
TG		 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3025 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3027 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3029 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3031 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3032 /* format 8 */
823d2571
TG		 3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3034 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3036 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3038 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3039 /* format 7 */
823d2571
TG		 3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3041 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3043 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3044 /* format 1 */
823d2571
TG		 3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3047 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3050 /* format 3 */
823d2571
TG		 3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3055 /* format 6 */
823d2571
TG		 3056 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3058 0x4800, 0xF800,
3059 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3060 /* format 9 */
823d2571
TG		 3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3062 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3064 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3066 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3068 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3069 /* format 10 */
823d2571
TG		 3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3071 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3073 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3074 /* format 11 */
823d2571
TG		 3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3076 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3078 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3079 /* format 12 */
823d2571
TG		 3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3081 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3083 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3084 /* format 15 */
823d2571
TG		 3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3087 /* format 17 */
823d2571 3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3089 /* format 16 */
823d2571
TG		 3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3093 /* format 18 */
823d2571 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3095
3096 /* The E800 .. FFFF range is unconditionally redirected to the
3097 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3098 are processed via that table. Thus, we can never encounter a
3099 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3101 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3102};
3103
3104/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3105 We adopt the convention that hw1 is the high 16 bits of .value and
3106 .mask, hw2 the low 16 bits.
3107
3108 print_insn_thumb32 recognizes the following format control codes:
3109
3110 %% %
3111
3112 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3113 %M print a modified 12-bit immediate (same location)
3114 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3115 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3116 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3117 %S print a possibly-shifted Rm
3118
32a94698 3119 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3120 %a print the address of a plain load/store
3121 %w print the width and signedness of a core load/store
3122 %m print register mask for ldm/stm
4b5a202f 3123 %n print register mask for clrm
8f06b2d8
PB		 3124
3125 %E print the lsb and width fields of a bfc/bfi instruction
3126 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3127 %G print a fallback offset for Branch Future instructions
e5d6e09e 3128 %W print an offset for BF instruction
1caf72a5 3129 %Y print an offset for BFL instruction
1889da70 3130 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3131 %Q print an offset for Low Overhead Loop instructions
3132 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3133 %b print a conditional branch offset
3134 %B print an unconditional branch offset
3135 %s print the shift field of an SSAT instruction
3136 %R print the rotation field of an SXT instruction
62b3e311
PB		 3137 %U print barrier type.
3138 %P print address for pli instruction.
c22aaad1
PB		 3139 %c print the condition code
3140 %x print warning if conditional an not at end of IT block"
3141 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3142
3143 %<bitfield>d print bitfield in decimal
f0fba320 3144 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3145 %<bitfield>W print bitfield*4 in decimal
3146 %<bitfield>r print bitfield as an ARM register
dd5181d5 3147 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3148 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3149 %<bitfield>c print bitfield as a condition code
3150
16980d0b
JB		 3151 %<bitfield>'c print specified char iff bitfield is all ones
3152 %<bitfield>`c print specified char iff bitfield is all zeroes
3153 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3154
3155 With one exception at the bottom (done because BL and BLX(1) need
3156 to come dead last), this table was machine-sorted first in
3157 decreasing order of number of bits set in the mask, then in
3158 increasing numeric order of mask, then in increasing numeric order
3159 of opcode. This order is not the clearest for a human reader, but
3160 is guaranteed never to catch a special-case bit pattern with a more
3161 general mask, which is important, because this instruction encoding
3162 makes heavy use of special-case bit patterns. */
3163static const struct opcode32 thumb32_opcodes[] =
3164{
4b5a202f
AV		 3165 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3166 instructions. */
60f993ce
AV		 3167 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3168 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3170 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3171 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3172 0xf02fc001, 0xfffff001, "le\t%P"},
3173 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3174 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3175
4389b29a
AV		 3176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3177 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3178 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3179 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3181 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3182 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3183 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3184 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3185 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3186
4b5a202f
AV		 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3188 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3189
16a1fa25
TP		 3190 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3193 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3194 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3195 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3197 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3199 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3200
105bde57 3201 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3202 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3203 0xf3af8010, 0xffffffff, "esb"},
3204
53c4b28b 3205 /* V8 instructions. */
823d2571
TG		 3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3207 0xf3af8005, 0xffffffff, "sevl%c.w"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3209 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3211 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3213 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3215 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3217 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3219 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3221 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3223 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3225 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3227 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3229 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3231 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3233 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3235 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3237 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 3238
dd5181d5 3239 /* CRC32 instructions. */
823d2571 3240 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3241 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 3242 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3243 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 3244 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3245 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 3246 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3247 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 3248 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3249 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 3250 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3251 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 3252
c597cc3d
SD		 3253 /* Speculation Barriers. */
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3257
62b3e311 3258 /* V7 instructions. */
823d2571
TG		 3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3267 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3269 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 3270
90ec0d68 3271 /* Virtualization Extension instructions. */
823d2571 3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 3273 /* We skip ERET as that is SUBS pc, lr, #0. */
3274
60e5ef9f 3275 /* MP Extension instructions. */
823d2571 3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 3277
f4c65163 3278 /* Security extension instructions. */
823d2571 3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 3280
7fadb25d
SD		 3281 /* ARMv8.5-A instructions. */
3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3283
8f06b2d8 3284 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3291 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3293
ff8646ee 3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3295 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3297 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3299 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3301 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3303 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3305 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3307 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3309 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3311 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3313 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3315 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3317 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3319 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3321 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 3322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3323 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3325 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3327 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3329 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3331 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3333 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3335 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3337 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3339 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3341 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3343 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3345 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3347 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3349 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3351 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3353 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3355 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3357 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3359 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3361 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3363 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3365 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3367 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3369 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3371 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3373 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3375 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3377 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3379 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3381 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3383 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3385 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3387 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3389 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3391 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3393 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3395 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3397 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3399 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3401 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3403 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3405 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3407 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3409 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3411 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3413 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3415 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3417 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3419 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3421 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3423 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3425 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3427 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3429 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3431 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3433 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3435 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3437 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3439 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3441 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3443 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3445 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3447 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3449 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3451 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3453 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3455 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3457 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3459 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3461 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3463 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3465 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3467 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3469 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3471 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3473 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3475 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3477 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3479 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3481 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3483 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3485 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3487 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3489 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3491 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3493 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3495 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3497 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3499 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3501 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3511 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3513 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3515 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3517 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3519 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3523 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3525 0xf810f000, 0xff70f000, "pld%c\t%a"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3527 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3529 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3531 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3533 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3535 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3537 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3539 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3541 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3543 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3545 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3547 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3549 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3551 0xfb100000, 0xfff000c0,
3552 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3554 0xfbc00080, 0xfff000c0,
3555 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3557 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3559 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3561 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3563 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3565 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3567 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3569 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3571 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3573 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3575 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3577 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3579 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3581 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3583 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3585 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3587 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3589 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3591 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3592 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3593 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3595 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3597 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3599 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3601 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3603 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3605 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3607 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3609 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3611 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3613 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3615 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3617 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3619 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3621 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3623 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3625 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3627 0xe9400000, 0xff500000,
3628 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3630 0xe9500000, 0xff500000,
3631 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3633 0xe8600000, 0xff700000,
3634 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3636 0xe8700000, 0xff700000,
3637 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3639 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3641 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3642
3643 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3645 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3647 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3649 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3651 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3652
8f06b2d8 3653 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3655 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3657 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3658
3659 /* Fallback. */
823d2571
TG		 3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3661 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3662 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3663};
ff4a8d2b 3664
8f06b2d8
PB		 3665static const char *const arm_conditional[] =
3666{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3667 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3668
3669static const char *const arm_fp_const[] =
3670{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3671
3672static const char *const arm_shift[] =
3673{"lsl", "lsr", "asr", "ror"};
3674
3675typedef struct
3676{
3677 const char *name;
3678 const char *description;
3679 const char *reg_names[16];
3680}
3681arm_regname;
3682
3683static const arm_regname regnames[] =
3684{
65b48a81 3685 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3686 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3687 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3688 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3689 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3690 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3691 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3692 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3693 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3694 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3695 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3696 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3697 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3698 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3699};
3700
3701static const char *const iwmmxt_wwnames[] =
3702{"b", "h", "w", "d"};
3703
3704static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3705{"b", "bus", "bc", "bss",
3706 "h", "hus", "hc", "hss",
3707 "w", "wus", "wc", "wss",
3708 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3709};
3710
3711static const char *const iwmmxt_regnames[] =
3712{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3713 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3714};
3715
3716static const char *const iwmmxt_cregnames[] =
3717{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3718 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3719};
3720
143275ea
AV		 3721static const char *const vec_condnames[] =
3722{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3723};
3724
3725static const char *const mve_predicatenames[] =
3726{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3727 "eee", "ee", "eet", "e", "ett", "et", "ete"
3728};
3729
3730/* Names for 2-bit size field for mve vector isntructions. */
3731static const char *const mve_vec_sizename[] =
3732 { "8", "16", "32", "64"};
3733
3734/* Indicates whether we are processing a then predicate,
3735 else predicate or none at all. */
3736enum vpt_pred_state
3737{
3738 PRED_NONE,
3739 PRED_THEN,
3740 PRED_ELSE
3741};
3742
3743/* Information used to process a vpt block and subsequent instructions. */
3744struct vpt_block
3745{
3746 /* Are we in a vpt block. */
3747 bfd_boolean in_vpt_block;
3748
3749 /* Next predicate state if in vpt block. */
3750 enum vpt_pred_state next_pred_state;
3751
3752 /* Mask from vpt/vpst instruction. */
3753 long predicate_mask;
3754
3755 /* Instruction number in vpt block. */
3756 long current_insn_num;
3757
3758 /* Number of instructions in vpt block.. */
3759 long num_pred_insn;
3760};
3761
3762static struct vpt_block vpt_block_state =
3763{
3764 FALSE,
3765 PRED_NONE,
3766 0,
3767 0,
3768 0
3769};
3770
8f06b2d8
PB		 3771/* Default to GCC register name set. */
3772static unsigned int regname_selected = 1;
3773
65b48a81 3774#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3775#define arm_regnames regnames[regname_selected].reg_names
3776
3777static bfd_boolean force_thumb = FALSE;
3778
c22aaad1
PB		 3779/* Current IT instruction state. This contains the same state as the IT
3780 bits in the CPSR. */
3781static unsigned int ifthen_state;
3782/* IT state for the next instruction. */
3783static unsigned int ifthen_next_state;
3784/* The address of the insn for which the IT state is valid. */
3785static bfd_vma ifthen_address;
3786#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3787/* Indicates that the current Conditional state is unconditional or outside
3788 an IT block. */
3789#define COND_UNCOND 16
c22aaad1 3790
8f06b2d8
PB		 3791\f
3792/* Functions. */
143275ea
AV		 3793/* Extract the predicate mask for a VPT or VPST instruction.
3794 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
3795
3796static long
3797mve_extract_pred_mask (long given)
3798{
3799 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
3800}
3801
3802/* Return the number of instructions in a MVE predicate block. */
3803static long
3804num_instructions_vpt_block (long given)
3805{
3806 long mask = mve_extract_pred_mask (given);
3807 if (mask == 0)
3808 return 0;
3809
3810 if (mask == 8)
3811 return 1;
3812
3813 if ((mask & 7) == 4)
3814 return 2;
3815
3816 if ((mask & 3) == 2)
3817 return 3;
3818
3819 if ((mask & 1) == 1)
3820 return 4;
3821
3822 return 0;
3823}
3824
3825static void
3826mark_outside_vpt_block (void)
3827{
3828 vpt_block_state.in_vpt_block = FALSE;
3829 vpt_block_state.next_pred_state = PRED_NONE;
3830 vpt_block_state.predicate_mask = 0;
3831 vpt_block_state.current_insn_num = 0;
3832 vpt_block_state.num_pred_insn = 0;
3833}
3834
3835static void
3836mark_inside_vpt_block (long given)
3837{
3838 vpt_block_state.in_vpt_block = TRUE;
3839 vpt_block_state.next_pred_state = PRED_THEN;
3840 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
3841 vpt_block_state.current_insn_num = 0;
3842 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
3843 assert (vpt_block_state.num_pred_insn >= 1);
3844}
3845
3846static enum vpt_pred_state
3847invert_next_predicate_state (enum vpt_pred_state astate)
3848{
3849 if (astate == PRED_THEN)
3850 return PRED_ELSE;
3851 else if (astate == PRED_ELSE)
3852 return PRED_THEN;
3853 else
3854 return PRED_NONE;
3855}
3856
3857static enum vpt_pred_state
3858update_next_predicate_state (void)
3859{
3860 long pred_mask = vpt_block_state.predicate_mask;
3861 long mask_for_insn = 0;
3862
3863 switch (vpt_block_state.current_insn_num)
3864 {
3865 case 1:
3866 mask_for_insn = 8;
3867 break;
3868
3869 case 2:
3870 mask_for_insn = 4;
3871 break;
3872
3873 case 3:
3874 mask_for_insn = 2;
3875 break;
3876
3877 case 4:
3878 return PRED_NONE;
3879 }
3880
3881 if (pred_mask & mask_for_insn)
3882 return invert_next_predicate_state (vpt_block_state.next_pred_state);
3883 else
3884 return vpt_block_state.next_pred_state;
3885}
3886
3887static void
3888update_vpt_block_state (void)
3889{
3890 vpt_block_state.current_insn_num++;
3891 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
3892 {
3893 /* No more instructions to process in vpt block. */
3894 mark_outside_vpt_block ();
3895 return;
3896 }
3897
3898 vpt_block_state.next_pred_state = update_next_predicate_state ();
3899}
8f06b2d8 3900
16980d0b
JB		 3901/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3902 Returns pointer to following character of the format string and
3903 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3904 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3905
3906static const char *
fe56b6ce
NC		 3907arm_decode_bitfield (const char *ptr,
3908 unsigned long insn,
3909 unsigned long *valuep,
3910 int *widthp)
16980d0b
JB		 3911{
3912 unsigned long value = 0;
3913 int width = 0;
43e65147
L		 3914
3915 do
16980d0b
JB		 3916 {
3917 int start, end;
3918 int bits;
3919
3920 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3921 start = start * 10 + *ptr - '0';
3922 if (*ptr == '-')
3923 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3924 end = end * 10 + *ptr - '0';
3925 else
3926 end = start;
3927 bits = end - start;
3928 if (bits < 0)
3929 abort ();
3930 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3931 width += bits + 1;
3932 }
3933 while (*ptr++ == ',');
3934 *valuep = value;
3935 if (widthp)
3936 *widthp = width;
3937 return ptr - 1;
3938}
3939
8f06b2d8 3940static void
37b37b2d 3941arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3942 bfd_boolean print_shift)
8f06b2d8
PB		 3943{
3944 func (stream, "%s", arm_regnames[given & 0xf]);
3945
3946 if ((given & 0xff0) != 0)
3947 {
3948 if ((given & 0x10) == 0)
3949 {
3950 int amount = (given & 0xf80) >> 7;
3951 int shift = (given & 0x60) >> 5;
3952
3953 if (amount == 0)
3954 {
3955 if (shift == 3)
3956 {
3957 func (stream, ", rrx");
3958 return;
3959 }
3960
3961 amount = 32;
3962 }
3963
37b37b2d
RE		 3964 if (print_shift)
3965 func (stream, ", %s #%d", arm_shift[shift], amount);
3966 else
3967 func (stream, ", #%d", amount);
8f06b2d8 3968 }
74bdfecf 3969 else if ((given & 0x80) == 0x80)
aefd8a40 3970 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3971 else if (print_shift)
8f06b2d8
PB		 3972 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3973 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3974 else
3975 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3976 }
3977}
3978
73cd51e5
AV		 3979/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
3980
3981static bfd_boolean
3982is_mve_okay_in_it (enum mve_instructions matched_insn)
3983{
3984 return FALSE;
3985}
3986
3987static bfd_boolean
3988is_mve_architecture (struct disassemble_info *info)
3989{
3990 struct arm_private_data *private_data = info->private_data;
3991 arm_feature_set allowed_arches = private_data->features;
3992
3993 arm_feature_set arm_ext_v8_1m_main
3994 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
3995
3996 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3997 && !ARM_CPU_IS_ANY (allowed_arches))
3998 return TRUE;
3999 else
4000 return FALSE;
4001}
4002
143275ea
AV		 4003static bfd_boolean
4004is_vpt_instruction (long given)
4005{
4006
4007 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4008 if ((given & 0x0040e000) == 0)
4009 return FALSE;
4010
4011 /* VPT floating point T1 variant. */
4012 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4013 /* VPT floating point T2 variant. */
4014 || ((given & 0xefb10f50) == 0xee310f40)
4015 /* VPT vector T1 variant. */
4016 || ((given & 0xff811f51) == 0xfe010f00)
4017 /* VPT vector T2 variant. */
4018 || ((given & 0xff811f51) == 0xfe010f01
4019 && ((given & 0x300000) != 0x300000))
4020 /* VPT vector T3 variant. */
4021 || ((given & 0xff811f50) == 0xfe011f00)
4022 /* VPT vector T4 variant. */
4023 || ((given & 0xff811f70) == 0xfe010f40)
4024 /* VPT vector T5 variant. */
4025 || ((given & 0xff811f70) == 0xfe010f60)
4026 /* VPT vector T6 variant. */
4027 || ((given & 0xff811f50) == 0xfe011f40)
4028 /* VPST vector T variant. */
4029 || ((given & 0xffbf1fff) == 0xfe310f4d))
4030 return TRUE;
4031 else
4032 return FALSE;
4033}
4034
73cd51e5
AV		 4035/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4036 and ending bitfield = END. END must be greater than START. */
4037
4038static unsigned long
4039arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4040{
4041 int bits = end - start;
4042
4043 if (bits < 0)
4044 abort ();
4045
4046 return ((given >> start) & ((2ul << bits) - 1));
4047}
4048
4049/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4050 START:END and START2:END2. END/END2 must be greater than
4051 START/START2. */
4052
4053static unsigned long
4054arm_decode_field_multiple (unsigned long given, unsigned int start,
4055 unsigned int end, unsigned int start2,
4056 unsigned int end2)
4057{
4058 int bits = end - start;
4059 int bits2 = end2 - start2;
4060 unsigned long value = 0;
4061 int width = 0;
4062
4063 if (bits2 < 0)
4064 abort ();
4065
4066 value = arm_decode_field (given, start, end);
4067 width += bits + 1;
4068
4069 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4070 return value;
4071}
4072
4073/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4074 This helps us decode instructions that change mnemonic depending on specific
4075 operand values/encodings. */
4076
4077static bfd_boolean
4078is_mve_encoding_conflict (unsigned long given,
4079 enum mve_instructions matched_insn)
4080{
143275ea
AV		 4081 switch (matched_insn)
4082 {
4083 case MVE_VPST:
4084 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4085 return TRUE;
4086 else
4087 return FALSE;
4088
4089 case MVE_VPT_FP_T1:
4090 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4091 return TRUE;
4092 if ((arm_decode_field (given, 12, 12) == 0)
4093 && (arm_decode_field (given, 0, 0) == 1))
4094 return TRUE;
4095 return FALSE;
4096
4097 case MVE_VPT_FP_T2:
4098 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4099 return TRUE;
4100 if (arm_decode_field (given, 0, 3) == 0xd)
4101 return TRUE;
4102 return FALSE;
4103
4104 case MVE_VPT_VEC_T1:
4105 case MVE_VPT_VEC_T2:
4106 case MVE_VPT_VEC_T3:
4107 case MVE_VPT_VEC_T4:
4108 case MVE_VPT_VEC_T5:
4109 case MVE_VPT_VEC_T6:
4110 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4111 return TRUE;
4112 if (arm_decode_field (given, 20, 21) == 3)
4113 return TRUE;
4114 return FALSE;
4115
4116 case MVE_VCMP_FP_T1:
4117 if ((arm_decode_field (given, 12, 12) == 0)
4118 && (arm_decode_field (given, 0, 0) == 1))
4119 return TRUE;
4120 else
4121 return FALSE;
4122
4123 case MVE_VCMP_FP_T2:
4124 if (arm_decode_field (given, 0, 3) == 0xd)
4125 return TRUE;
4126 else
4127 return FALSE;
4128
9743db03
AV		 4129 case MVE_VHADD_T2:
4130 case MVE_VHSUB_T2:
143275ea
AV		 4131 case MVE_VCMP_VEC_T1:
4132 case MVE_VCMP_VEC_T2:
4133 case MVE_VCMP_VEC_T3:
4134 case MVE_VCMP_VEC_T4:
4135 case MVE_VCMP_VEC_T5:
4136 case MVE_VCMP_VEC_T6:
4137 if (arm_decode_field (given, 20, 21) == 3)
4138 return TRUE;
4139 else
4140 return FALSE;
4141
04d54ace
AV		 4142 case MVE_VLD2:
4143 case MVE_VLD4:
4144 case MVE_VST2:
4145 case MVE_VST4:
4146 if (arm_decode_field (given, 7, 8) == 3)
4147 return TRUE;
4148 else
4149 return FALSE;
4150
aef6d006
AV		 4151 case MVE_VSTRB_T1:
4152 case MVE_VSTRH_T2:
4153 if ((arm_decode_field (given, 24, 24) == 0)
4154 && (arm_decode_field (given, 21, 21) == 0))
4155 {
4156 return TRUE;
4157 }
4158 else if ((arm_decode_field (given, 7, 8) == 3))
4159 return TRUE;
4160 else
4161 return FALSE;
4162
4163 case MVE_VSTRB_T5:
4164 case MVE_VSTRH_T6:
4165 case MVE_VSTRW_T7:
4166 if ((arm_decode_field (given, 24, 24) == 0)
4167 && (arm_decode_field (given, 21, 21) == 0))
4168 {
4169 return TRUE;
4170 }
4171 else
4172 return FALSE;
4173
143275ea
AV		 4174 default:
4175 return FALSE;
4176
4177 }
73cd51e5
AV		 4178}
4179
aef6d006
AV		 4180static void
4181print_mve_vld_str_addr (struct disassemble_info *info,
4182 unsigned long given,
4183 enum mve_instructions matched_insn)
4184{
4185 void *stream = info->stream;
4186 fprintf_ftype func = info->fprintf_func;
4187
4188 unsigned long p, w, gpr, imm, add, mod_imm;
4189
4190 imm = arm_decode_field (given, 0, 6);
4191 mod_imm = imm;
4192
4193 switch (matched_insn)
4194 {
4195 case MVE_VLDRB_T1:
4196 case MVE_VSTRB_T1:
4197 gpr = arm_decode_field (given, 16, 18);
4198 break;
4199
4200 case MVE_VLDRH_T2:
4201 case MVE_VSTRH_T2:
4202 gpr = arm_decode_field (given, 16, 18);
4203 mod_imm = imm << 1;
4204 break;
4205
4206 case MVE_VLDRH_T6:
4207 case MVE_VSTRH_T6:
4208 gpr = arm_decode_field (given, 16, 19);
4209 mod_imm = imm << 1;
4210 break;
4211
4212 case MVE_VLDRW_T7:
4213 case MVE_VSTRW_T7:
4214 gpr = arm_decode_field (given, 16, 19);
4215 mod_imm = imm << 2;
4216 break;
4217
4218 case MVE_VLDRB_T5:
4219 case MVE_VSTRB_T5:
4220 gpr = arm_decode_field (given, 16, 19);
4221 break;
4222
4223 default:
4224 return;
4225 }
4226
4227 p = arm_decode_field (given, 24, 24);
4228 w = arm_decode_field (given, 21, 21);
4229
4230 add = arm_decode_field (given, 23, 23);
4231
4232 char * add_sub;
4233
4234 /* Don't print anything for '+' as it is implied. */
4235 if (add == 1)
4236 add_sub = "";
4237 else
4238 add_sub = "-";
4239
4240 if (p == 1)
4241 {
4242 /* Offset mode. */
4243 if (w == 0)
4244 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4245 /* Pre-indexed mode. */
4246 else
4247 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4248 }
4249 else if ((p == 0) && (w == 1))
4250 /* Post-index mode. */
4251 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4252}
4253
73cd51e5
AV		 4254/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4255 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4256 this encoding is undefined. */
4257
4258static bfd_boolean
4259is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4260 enum mve_undefined *undefined_code)
4261{
4262 *undefined_code = UNDEF_NONE;
4263
9743db03
AV		 4264 switch (matched_insn)
4265 {
4266 case MVE_VDUP:
4267 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4268 {
4269 *undefined_code = UNDEF_SIZE_3;
4270 return TRUE;
4271 }
4272 else
4273 return FALSE;
4274
4275 case MVE_VRHADD:
4276 case MVE_VHADD_T1:
4277 case MVE_VHSUB_T1:
4278 if (arm_decode_field (given, 20, 21) == 3)
4279 {
4280 *undefined_code = UNDEF_SIZE_3;
4281 return TRUE;
4282 }
4283 else
4284 return FALSE;
4285
aef6d006
AV		 4286 case MVE_VLDRB_T1:
4287 if (arm_decode_field (given, 7, 8) == 3)
4288 {
4289 *undefined_code = UNDEF_SIZE_3;
4290 return TRUE;
4291 }
4292 else
4293 return FALSE;
4294
4295 case MVE_VLDRH_T2:
4296 if (arm_decode_field (given, 7, 8) <= 1)
4297 {
4298 *undefined_code = UNDEF_SIZE_LE_1;
4299 return TRUE;
4300 }
4301 else
4302 return FALSE;
4303
4304 case MVE_VSTRB_T1:
4305 if ((arm_decode_field (given, 7, 8) == 0))
4306 {
4307 *undefined_code = UNDEF_SIZE_0;
4308 return TRUE;
4309 }
4310 else
4311 return FALSE;
4312
4313 case MVE_VSTRH_T2:
4314 if ((arm_decode_field (given, 7, 8) <= 1))
4315 {
4316 *undefined_code = UNDEF_SIZE_LE_1;
4317 return TRUE;
4318 }
4319 else
4320 return FALSE;
4321
9743db03
AV		 4322 default:
4323 return FALSE;
4324 }
73cd51e5
AV		 4325}
4326
4327/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4328 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4329 why this encoding is unpredictable. */
4330
4331static bfd_boolean
4332is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
4333 enum mve_unpredictable *unpredictable_code)
4334{
4335 *unpredictable_code = UNPRED_NONE;
4336
143275ea
AV		 4337 switch (matched_insn)
4338 {
4339 case MVE_VCMP_FP_T2:
4340 case MVE_VPT_FP_T2:
4341 if ((arm_decode_field (given, 12, 12) == 0)
4342 && (arm_decode_field (given, 5, 5) == 1))
4343 {
4344 *unpredictable_code = UNPRED_FCA_0_FCB_1;
4345 return TRUE;
4346 }
4347 else
4348 return FALSE;
73cd51e5 4349
143275ea
AV		 4350 case MVE_VPT_VEC_T4:
4351 case MVE_VPT_VEC_T5:
4352 case MVE_VPT_VEC_T6:
4353 case MVE_VCMP_VEC_T4:
4354 case MVE_VCMP_VEC_T5:
4355 case MVE_VCMP_VEC_T6:
4356 if (arm_decode_field (given, 0, 3) == 0xd)
4357 {
4358 *unpredictable_code = UNPRED_R13;
4359 return TRUE;
4360 }
4361 else
4362 return FALSE;
c1e26897 4363
9743db03
AV		 4364 case MVE_VDUP:
4365 {
4366 unsigned long gpr = arm_decode_field (given, 12, 15);
4367 if (gpr == 0xd)
4368 {
4369 *unpredictable_code = UNPRED_R13;
4370 return TRUE;
4371 }
4372 else if (gpr == 0xf)
4373 {
4374 *unpredictable_code = UNPRED_R15;
4375 return TRUE;
4376 }
4377
4378 return FALSE;
4379 }
4380
4381 case MVE_VFMA_FP_SCALAR:
4382 case MVE_VFMAS_FP_SCALAR:
4383 case MVE_VHADD_T2:
4384 case MVE_VHSUB_T2:
4385 {
4386 unsigned long gpr = arm_decode_field (given, 0, 3);
4387 if (gpr == 0xd)
4388 {
4389 *unpredictable_code = UNPRED_R13;
4390 return TRUE;
4391 }
4392 else if (gpr == 0xf)
4393 {
4394 *unpredictable_code = UNPRED_R15;
4395 return TRUE;
4396 }
4397
4398 return FALSE;
4399 }
4400
04d54ace
AV		 4401 case MVE_VLD2:
4402 case MVE_VST2:
4403 {
4404 unsigned long rn = arm_decode_field (given, 16, 19);
4405
4406 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4407 {
4408 *unpredictable_code = UNPRED_R13_AND_WB;
4409 return TRUE;
4410 }
4411
4412 if (rn == 0xf)
4413 {
4414 *unpredictable_code = UNPRED_R15;
4415 return TRUE;
4416 }
4417
4418 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
4419 {
4420 *unpredictable_code = UNPRED_Q_GT_6;
4421 return TRUE;
4422 }
4423 else
4424 return FALSE;
4425 }
4426
4427 case MVE_VLD4:
4428 case MVE_VST4:
4429 {
4430 unsigned long rn = arm_decode_field (given, 16, 19);
4431
4432 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4433 {
4434 *unpredictable_code = UNPRED_R13_AND_WB;
4435 return TRUE;
4436 }
4437
4438 if (rn == 0xf)
4439 {
4440 *unpredictable_code = UNPRED_R15;
4441 return TRUE;
4442 }
4443
4444 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
4445 {
4446 *unpredictable_code = UNPRED_Q_GT_4;
4447 return TRUE;
4448 }
4449 else
4450 return FALSE;
4451 }
4452
aef6d006
AV		 4453 case MVE_VLDRB_T5:
4454 case MVE_VLDRH_T6:
4455 case MVE_VLDRW_T7:
4456 case MVE_VSTRB_T5:
4457 case MVE_VSTRH_T6:
4458 case MVE_VSTRW_T7:
4459 {
4460 unsigned long rn = arm_decode_field (given, 16, 19);
4461
4462 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4463 {
4464 *unpredictable_code = UNPRED_R13_AND_WB;
4465 return TRUE;
4466 }
4467 else if (rn == 0xf)
4468 {
4469 *unpredictable_code = UNPRED_R15;
4470 return TRUE;
4471 }
4472 else
4473 return FALSE;
4474 }
4475
143275ea
AV		 4476 default:
4477 return FALSE;
4478 }
4479}
c1e26897 4480
73cd51e5
AV		 4481static void
4482print_mve_undefined (struct disassemble_info *info,
4483 enum mve_undefined undefined_code)
4484{
4485 void *stream = info->stream;
4486 fprintf_ftype func = info->fprintf_func;
4487
4488 func (stream, "\t\tundefined instruction: ");
4489
4490 switch (undefined_code)
4491 {
aef6d006
AV		 4492 case UNDEF_SIZE_0:
4493 func (stream, "size equals zero");
4494 break;
4495
9743db03
AV		 4496 case UNDEF_SIZE_3:
4497 func (stream, "size equals three");
4498 break;
4499
aef6d006
AV		 4500 case UNDEF_SIZE_LE_1:
4501 func (stream, "size <= 1");
4502 break;
4503
73cd51e5
AV		 4504 case UNDEF_NONE:
4505 break;
4506 }
4507
4508}
4509
4510static void
4511print_mve_unpredictable (struct disassemble_info *info,
4512 enum mve_unpredictable unpredict_code)
4513{
4514 void *stream = info->stream;
4515 fprintf_ftype func = info->fprintf_func;
4516
4517 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
4518
4519 switch (unpredict_code)
4520 {
4521 case UNPRED_IT_BLOCK:
4522 func (stream, "mve instruction in it block");
4523 break;
4524
143275ea
AV		 4525 case UNPRED_FCA_0_FCB_1:
4526 func (stream, "condition bits, fca = 0 and fcb = 1");
4527 break;
4528
4529 case UNPRED_R13:
4530 func (stream, "use of r13 (sp)");
4531 break;
4532
9743db03
AV		 4533 case UNPRED_R15:
4534 func (stream, "use of r15 (pc)");
4535 break;
4536
04d54ace
AV		 4537 case UNPRED_Q_GT_4:
4538 func (stream, "start register block > r4");
4539 break;
4540
4541 case UNPRED_Q_GT_6:
4542 func (stream, "start register block > r6");
4543 break;
4544
4545 case UNPRED_R13_AND_WB:
4546 func (stream, "use of r13 and write back");
4547 break;
4548
73cd51e5
AV		 4549 case UNPRED_NONE:
4550 break;
4551 }
4552}
4553
04d54ace
AV		 4554/* Print register block operand for mve vld2/vld4/vst2/vld4. */
4555
4556static void
4557print_mve_register_blocks (struct disassemble_info *info,
4558 unsigned long given,
4559 enum mve_instructions matched_insn)
4560{
4561 void *stream = info->stream;
4562 fprintf_ftype func = info->fprintf_func;
4563
4564 unsigned long q_reg_start = arm_decode_field_multiple (given,
4565 13, 15,
4566 22, 22);
4567 switch (matched_insn)
4568 {
4569 case MVE_VLD2:
4570 case MVE_VST2:
4571 if (q_reg_start <= 6)
4572 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
4573 else
4574 func (stream, "<illegal reg q%ld>", q_reg_start);
4575 break;
4576
4577 case MVE_VLD4:
4578 case MVE_VST4:
4579 if (q_reg_start <= 4)
4580 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
4581 q_reg_start + 1, q_reg_start + 2,
4582 q_reg_start + 3);
4583 else
4584 func (stream, "<illegal reg q%ld>", q_reg_start);
4585 break;
4586
4587 default:
4588 break;
4589 }
4590}
4591
143275ea
AV		 4592static void
4593print_instruction_predicate (struct disassemble_info *info)
4594{
4595 void *stream = info->stream;
4596 fprintf_ftype func = info->fprintf_func;
4597
4598 if (vpt_block_state.next_pred_state == PRED_THEN)
4599 func (stream, "t");
4600 else if (vpt_block_state.next_pred_state == PRED_ELSE)
4601 func (stream, "e");
4602}
4603
4604static void
4605print_mve_size (struct disassemble_info *info,
4606 unsigned long size,
4607 enum mve_instructions matched_insn)
4608{
4609 void *stream = info->stream;
4610 fprintf_ftype func = info->fprintf_func;
4611
4612 switch (matched_insn)
4613 {
4614 case MVE_VCMP_VEC_T1:
4615 case MVE_VCMP_VEC_T2:
4616 case MVE_VCMP_VEC_T3:
4617 case MVE_VCMP_VEC_T4:
4618 case MVE_VCMP_VEC_T5:
4619 case MVE_VCMP_VEC_T6:
9743db03
AV		 4620 case MVE_VHADD_T1:
4621 case MVE_VHADD_T2:
4622 case MVE_VHSUB_T1:
4623 case MVE_VHSUB_T2:
04d54ace
AV		 4624 case MVE_VLD2:
4625 case MVE_VLD4:
aef6d006
AV		 4626 case MVE_VLDRB_T1:
4627 case MVE_VLDRH_T2:
143275ea
AV		 4628 case MVE_VPT_VEC_T1:
4629 case MVE_VPT_VEC_T2:
4630 case MVE_VPT_VEC_T3:
4631 case MVE_VPT_VEC_T4:
4632 case MVE_VPT_VEC_T5:
4633 case MVE_VPT_VEC_T6:
9743db03 4634 case MVE_VRHADD:
04d54ace
AV		 4635 case MVE_VST2:
4636 case MVE_VST4:
aef6d006
AV		 4637 case MVE_VSTRB_T1:
4638 case MVE_VSTRH_T2:
143275ea
AV		 4639 if (size <= 3)
4640 func (stream, "%s", mve_vec_sizename[size]);
4641 else
4642 func (stream, "<undef size>");
4643 break;
4644
4645 case MVE_VCMP_FP_T1:
4646 case MVE_VCMP_FP_T2:
9743db03
AV		 4647 case MVE_VFMA_FP_SCALAR:
4648 case MVE_VFMA_FP:
4649 case MVE_VFMS_FP:
4650 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 4651 case MVE_VPT_FP_T1:
4652 case MVE_VPT_FP_T2:
4653 if (size == 0)
4654 func (stream, "32");
4655 else if (size == 1)
4656 func (stream, "16");
4657 break;
4658
9743db03
AV		 4659 case MVE_VDUP:
4660 switch (size)
4661 {
4662 case 0:
4663 func (stream, "32");
4664 break;
4665 case 1:
4666 func (stream, "16");
4667 break;
4668 case 2:
4669 func (stream, "8");
4670 break;
4671 default:
4672 break;
4673 }
4674 break;
4675
143275ea
AV		 4676 default:
4677 break;
4678 }
4679}
4680
4681static void
4682print_vec_condition (struct disassemble_info *info, long given,
4683 enum mve_instructions matched_insn)
4684{
4685 void *stream = info->stream;
4686 fprintf_ftype func = info->fprintf_func;
4687 long vec_cond = 0;
4688
4689 switch (matched_insn)
4690 {
4691 case MVE_VPT_FP_T1:
4692 case MVE_VCMP_FP_T1:
4693 vec_cond = (((given & 0x1000) >> 10)
4694 | ((given & 1) << 1)
4695 | ((given & 0x0080) >> 7));
4696 func (stream, "%s",vec_condnames[vec_cond]);
4697 break;
4698
4699 case MVE_VPT_FP_T2:
4700 case MVE_VCMP_FP_T2:
4701 vec_cond = (((given & 0x1000) >> 10)
4702 | ((given & 0x0020) >> 4)
4703 | ((given & 0x0080) >> 7));
4704 func (stream, "%s",vec_condnames[vec_cond]);
4705 break;
4706
4707 case MVE_VPT_VEC_T1:
4708 case MVE_VCMP_VEC_T1:
4709 vec_cond = (given & 0x0080) >> 7;
4710 func (stream, "%s",vec_condnames[vec_cond]);
4711 break;
4712
4713 case MVE_VPT_VEC_T2:
4714 case MVE_VCMP_VEC_T2:
4715 vec_cond = 2 | ((given & 0x0080) >> 7);
4716 func (stream, "%s",vec_condnames[vec_cond]);
4717 break;
4718
4719 case MVE_VPT_VEC_T3:
4720 case MVE_VCMP_VEC_T3:
4721 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
4722 func (stream, "%s",vec_condnames[vec_cond]);
4723 break;
4724
4725 case MVE_VPT_VEC_T4:
4726 case MVE_VCMP_VEC_T4:
4727 vec_cond = (given & 0x0080) >> 7;
4728 func (stream, "%s",vec_condnames[vec_cond]);
4729 break;
4730
4731 case MVE_VPT_VEC_T5:
4732 case MVE_VCMP_VEC_T5:
4733 vec_cond = 2 | ((given & 0x0080) >> 7);
4734 func (stream, "%s",vec_condnames[vec_cond]);
4735 break;
4736
4737 case MVE_VPT_VEC_T6:
4738 case MVE_VCMP_VEC_T6:
4739 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
4740 func (stream, "%s",vec_condnames[vec_cond]);
4741 break;
4742
4743 case MVE_NONE:
4744 case MVE_VPST:
4745 default:
4746 break;
4747 }
4748}
4749
4750#define W_BIT 21
4751#define I_BIT 22
4752#define U_BIT 23
4753#define P_BIT 24
4754
4755#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
4756#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
4757#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
4758#define PRE_BIT_SET (given & (1 << P_BIT))
4759
4760
8f06b2d8
PB		 4761/* Print one coprocessor instruction on INFO->STREAM.
4762 Return TRUE if the instuction matched, FALSE if this is not a
4763 recognised coprocessor instruction. */
4764
4765static bfd_boolean
fe56b6ce
NC		 4766print_insn_coprocessor (bfd_vma pc,
4767 struct disassemble_info *info,
4768 long given,
8f06b2d8
PB		 4769 bfd_boolean thumb)
4770{
6b0dd094 4771 const struct sopcode32 *insn;
8f06b2d8
PB		 4772 void *stream = info->stream;
4773 fprintf_ftype func = info->fprintf_func;
4774 unsigned long mask;
2edcd244 4775 unsigned long value = 0;
c22aaad1 4776 int cond;
8afc7bea 4777 int cp_num;
823d2571
TG		 4778 struct arm_private_data *private_data = info->private_data;
4779 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 4780 arm_feature_set arm_ext_v8_1m_main =
4781 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 4782
5b616bef 4783 allowed_arches = private_data->features;
8f06b2d8
PB		 4784
4785 for (insn = coprocessor_opcodes; insn->assembler; insn++)
4786 {
ff4a8d2b
NC		 4787 unsigned long u_reg = 16;
4788 bfd_boolean is_unpredictable = FALSE;
05413229 4789 signed long value_in_comment = 0;
0313a2b8
NC		 4790 const char *c;
4791
823d2571 4792 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 4793 switch (insn->value)
4794 {
4795 case SENTINEL_IWMMXT_START:
4796 if (info->mach != bfd_mach_arm_XScale
4797 && info->mach != bfd_mach_arm_iWMMXt
4798 && info->mach != bfd_mach_arm_iWMMXt2)
4799 do
4800 insn++;
823d2571
TG		 4801 while ((! ARM_FEATURE_ZERO (insn->arch))
4802 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 4803 continue;
4804
4805 case SENTINEL_IWMMXT_END:
4806 continue;
4807
4808 case SENTINEL_GENERIC_START:
5b616bef 4809 allowed_arches = private_data->features;
05413229
NC		 4810 continue;
4811
4812 default:
4813 abort ();
4814 }
8f06b2d8
PB		 4815
4816 mask = insn->mask;
4817 value = insn->value;
8afc7bea
RL		 4818 cp_num = (given >> 8) & 0xf;
4819
8f06b2d8
PB		 4820 if (thumb)
4821 {
4822 /* The high 4 bits are 0xe for Arm conditional instructions, and
4823 0xe for arm unconditional instructions. The rest of the
4824 encoding is the same. */
4825 mask |= 0xf0000000;
4826 value |= 0xe0000000;
c22aaad1
PB		 4827 if (ifthen_state)
4828 cond = IFTHEN_COND;
4829 else
e2efe87d 4830 cond = COND_UNCOND;
8f06b2d8
PB		 4831 }
4832 else
4833 {
4834 /* Only match unconditional instuctions against unconditional
4835 patterns. */
4836 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 4837 {
4838 mask |= 0xf0000000;
e2efe87d 4839 cond = COND_UNCOND;
c22aaad1
PB		 4840 }
4841 else
4842 {
4843 cond = (given >> 28) & 0xf;
4844 if (cond == 0xe)
e2efe87d 4845 cond = COND_UNCOND;
c22aaad1 4846 }
8f06b2d8 4847 }
823d2571 4848
6b0dd094
AV		 4849 if ((insn->isa == T32 && !thumb)
4850 || (insn->isa == ARM && thumb))
4851 continue;
4852
0313a2b8
NC		 4853 if ((given & mask) != value)
4854 continue;
8f06b2d8 4855
823d2571 4856 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 4857 continue;
4858
8afc7bea
RL		 4859 if (insn->value == 0xfe000010 /* mcr2 */
4860 || insn->value == 0xfe100010 /* mrc2 */
4861 || insn->value == 0xfc100000 /* ldc2 */
4862 || insn->value == 0xfc000000) /* stc2 */
4863 {
b0c11777 4864 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 4865 is_unpredictable = TRUE;
f08d8ce3
AV		 4866
4867 /* Armv8.1-M Mainline FP & MVE instructions. */
4868 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4869 && !ARM_CPU_IS_ANY (allowed_arches)
4870 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4871 continue;
4872
8afc7bea
RL		 4873 }
4874 else if (insn->value == 0x0e000000 /* cdp */
4875 || insn->value == 0xfe000000 /* cdp2 */
4876 || insn->value == 0x0e000010 /* mcr */
4877 || insn->value == 0x0e100010 /* mrc */
4878 || insn->value == 0x0c100000 /* ldc */
4879 || insn->value == 0x0c000000) /* stc */
4880 {
4881 /* Floating-point instructions. */
b0c11777 4882 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 4883 continue;
32c36c3c
AV		 4884
4885 /* Armv8.1-M Mainline FP & MVE instructions. */
4886 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4887 && !ARM_CPU_IS_ANY (allowed_arches)
4888 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4889 continue;
8afc7bea 4890 }
aef6d006
AV		 4891 else if ((insn->value == 0xec100f80 /* vldr (system register) */
4892 || insn->value == 0xec000f80) /* vstr (system register) */
4893 && arm_decode_field (given, 24, 24) == 0
4894 && arm_decode_field (given, 21, 21) == 0)
4895 /* If the P and W bits are both 0 then these encodings match the MVE
4896 VLDR and VSTR instructions, these are in a different table, so we
4897 don't let it match here. */
4898 continue;
4899
8afc7bea 4900
0313a2b8
NC		 4901 for (c = insn->assembler; *c; c++)
4902 {
4903 if (*c == '%')
8f06b2d8 4904 {
32c36c3c
AV		 4905 const char mod = *++c;
4906 switch (mod)
8f06b2d8 4907 {
0313a2b8
NC		 4908 case '%':
4909 func (stream, "%%");
4910 break;
4911
4912 case 'A':
32c36c3c 4913 case 'K':
05413229 4914 {
79862e45 4915 int rn = (given >> 16) & 0xf;
b0c11777 4916 bfd_vma offset = given & 0xff;
0313a2b8 4917
32c36c3c
AV		 4918 if (mod == 'K')
4919 offset = given & 0x7f;
4920
05413229 4921 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 4922
79862e45
DJ		 4923 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
4924 {
4925 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 4926 if (cp_num == 9)
4927 /* vldr.16/vstr.16 will shift the address
4928 left by 1 bit only. */
4929 offset = offset * 2;
4930 else
4931 offset = offset * 4;
4932
79862e45
DJ		 4933 if (NEGATIVE_BIT_SET)
4934 offset = - offset;
4935 if (rn != 15)
4936 value_in_comment = offset;
4937 }
4938
c1e26897 4939 if (PRE_BIT_SET)
05413229
NC		 4940 {
4941 if (offset)
fe56b6ce 4942 func (stream, ", #%d]%s",
d908c8af 4943 (int) offset,
c1e26897 4944 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 4945 else if (NEGATIVE_BIT_SET)
4946 func (stream, ", #-0]");
05413229
NC		 4947 else
4948 func (stream, "]");
4949 }
4950 else
4951 {
0313a2b8 4952 func (stream, "]");
8f06b2d8 4953
c1e26897 4954 if (WRITEBACK_BIT_SET)
05413229
NC		 4955 {
4956 if (offset)
d908c8af 4957 func (stream, ", #%d", (int) offset);
26d97720
NS		 4958 else if (NEGATIVE_BIT_SET)
4959 func (stream, ", #-0");
05413229
NC		 4960 }
4961 else
fe56b6ce 4962 {
26d97720
NS		 4963 func (stream, ", {%s%d}",
4964 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 4965 (int) offset);
fe56b6ce
NC		 4966 value_in_comment = offset;
4967 }
05413229 4968 }
79862e45
DJ		 4969 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
4970 {
4971 func (stream, "\t; ");
6844b2c2
MGD		 4972 /* For unaligned PCs, apply off-by-alignment
4973 correction. */
43e65147 4974 info->print_address_func (offset + pc
6844b2c2
MGD		 4975 + info->bytes_per_chunk * 2
4976 - (pc & 3),
dffaa15c 4977 info);
79862e45 4978 }
05413229 4979 }
0313a2b8 4980 break;
8f06b2d8 4981
0313a2b8
NC		 4982 case 'B':
4983 {
4984 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
4985 int offset = (given >> 1) & 0x3f;
4986
4987 if (offset == 1)
4988 func (stream, "{d%d}", regno);
4989 else if (regno + offset > 32)
4990 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
4991 else
4992 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
4993 }
4994 break;
8f06b2d8 4995
efd6b359
AV		 4996 case 'C':
4997 {
4998 bfd_boolean single = ((given >> 8) & 1) == 0;
4999 char reg_prefix = single ? 's' : 'd';
5000 int Dreg = (given >> 22) & 0x1;
5001 int Vdreg = (given >> 12) & 0xf;
5002 int reg = single ? ((Vdreg << 1) | Dreg)
5003 : ((Dreg << 4) | Vdreg);
5004 int num = (given >> (single ? 0 : 1)) & 0x7f;
5005 int maxreg = single ? 31 : 15;
5006 int topreg = reg + num - 1;
5007
5008 if (!num)
5009 func (stream, "{VPR}");
5010 else if (num == 1)
5011 func (stream, "{%c%d, VPR}", reg_prefix, reg);
5012 else if (topreg > maxreg)
5013 func (stream, "{%c%d-<overflow reg d%d, VPR}",
5014 reg_prefix, reg, single ? topreg >> 1 : topreg);
5015 else
5016 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
5017 reg_prefix, topreg);
5018 }
5019 break;
5020
e2efe87d
MGD		 5021 case 'u':
5022 if (cond != COND_UNCOND)
5023 is_unpredictable = TRUE;
5024
5025 /* Fall through. */
0313a2b8 5026 case 'c':
b0c11777
RL		 5027 if (cond != COND_UNCOND && cp_num == 9)
5028 is_unpredictable = TRUE;
5029
0313a2b8
NC		 5030 func (stream, "%s", arm_conditional[cond]);
5031 break;
8f06b2d8 5032
0313a2b8
NC		 5033 case 'I':
5034 /* Print a Cirrus/DSP shift immediate. */
5035 /* Immediates are 7bit signed ints with bits 0..3 in
5036 bits 0..3 of opcode and bits 4..6 in bits 5..7
5037 of opcode. */
5038 {
5039 int imm;
8f06b2d8 5040
0313a2b8 5041 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 5042
0313a2b8
NC		 5043 /* Is ``imm'' a negative number? */
5044 if (imm & 0x40)
24b4cf66 5045 imm -= 0x80;
8f06b2d8 5046
0313a2b8
NC		 5047 func (stream, "%d", imm);
5048 }
5049
5050 break;
8f06b2d8 5051
32c36c3c
AV		 5052 case 'J':
5053 {
73cd51e5
AV		 5054 unsigned long regno
5055 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 5056
5057 switch (regno)
5058 {
5059 case 0x1:
5060 func (stream, "FPSCR");
5061 break;
5062 case 0x2:
5063 func (stream, "FPSCR_nzcvqc");
5064 break;
5065 case 0xc:
5066 func (stream, "VPR");
5067 break;
5068 case 0xd:
5069 func (stream, "P0");
5070 break;
5071 case 0xe:
5072 func (stream, "FPCXTNS");
5073 break;
5074 case 0xf:
5075 func (stream, "FPCXTS");
5076 break;
5077 default:
73cd51e5 5078 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 5079 break;
5080 }
5081 }
5082 break;
5083
0313a2b8
NC		 5084 case 'F':
5085 switch (given & 0x00408000)
5086 {
5087 case 0:
5088 func (stream, "4");
5089 break;
5090 case 0x8000:
5091 func (stream, "1");
5092 break;
5093 case 0x00400000:
5094 func (stream, "2");
8f06b2d8 5095 break;
0313a2b8
NC		 5096 default:
5097 func (stream, "3");
5098 }
5099 break;
8f06b2d8 5100
0313a2b8
NC		 5101 case 'P':
5102 switch (given & 0x00080080)
5103 {
5104 case 0:
5105 func (stream, "s");
5106 break;
5107 case 0x80:
5108 func (stream, "d");
5109 break;
5110 case 0x00080000:
5111 func (stream, "e");
5112 break;
5113 default:
5114 func (stream, _("<illegal precision>"));
8f06b2d8 5115 break;
0313a2b8
NC		 5116 }
5117 break;
8f06b2d8 5118
0313a2b8
NC		 5119 case 'Q':
5120 switch (given & 0x00408000)
5121 {
5122 case 0:
5123 func (stream, "s");
8f06b2d8 5124 break;
0313a2b8
NC		 5125 case 0x8000:
5126 func (stream, "d");
8f06b2d8 5127 break;
0313a2b8
NC		 5128 case 0x00400000:
5129 func (stream, "e");
5130 break;
5131 default:
5132 func (stream, "p");
8f06b2d8 5133 break;
0313a2b8
NC		 5134 }
5135 break;
8f06b2d8 5136
0313a2b8
NC		 5137 case 'R':
5138 switch (given & 0x60)
5139 {
5140 case 0:
5141 break;
5142 case 0x20:
5143 func (stream, "p");
5144 break;
5145 case 0x40:
5146 func (stream, "m");
5147 break;
5148 default:
5149 func (stream, "z");
5150 break;
5151 }
5152 break;
16980d0b 5153
0313a2b8
NC		 5154 case '0': case '1': case '2': case '3': case '4':
5155 case '5': case '6': case '7': case '8': case '9':
5156 {
5157 int width;
8f06b2d8 5158
0313a2b8 5159 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 5160
0313a2b8
NC		 5161 switch (*c)
5162 {
ff4a8d2b
NC		 5163 case 'R':
5164 if (value == 15)
5165 is_unpredictable = TRUE;
5166 /* Fall through. */
0313a2b8 5167 case 'r':
ff4a8d2b
NC		 5168 if (c[1] == 'u')
5169 {
5170 /* Eat the 'u' character. */
5171 ++ c;
5172
5173 if (u_reg == value)
5174 is_unpredictable = TRUE;
5175 u_reg = value;
5176 }
0313a2b8
NC		 5177 func (stream, "%s", arm_regnames[value]);
5178 break;
c28eeff2
SN		 5179 case 'V':
5180 if (given & (1 << 6))
5181 goto Q;
5182 /* FALLTHROUGH */
0313a2b8
NC		 5183 case 'D':
5184 func (stream, "d%ld", value);
5185 break;
5186 case 'Q':
c28eeff2 5187 Q:
0313a2b8
NC		 5188 if (value & 1)
5189 func (stream, "<illegal reg q%ld.5>", value >> 1);
5190 else
5191 func (stream, "q%ld", value >> 1);
5192 break;
5193 case 'd':
5194 func (stream, "%ld", value);
05413229 5195 value_in_comment = value;
0313a2b8 5196 break;
6f1c2142
AM		 5197 case 'E':
5198 {
5199 /* Converts immediate 8 bit back to float value. */
5200 unsigned floatVal = (value & 0x80) << 24
5201 | (value & 0x3F) << 19
5202 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
5203
5204 /* Quarter float have a maximum value of 31.0.
5205 Get floating point value multiplied by 1e7.
5206 The maximum value stays in limit of a 32-bit int. */
5207 unsigned decVal =
5208 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
5209 (16 + (value & 0xF));
5210
5211 if (!(decVal % 1000000))
5212 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
5213 floatVal, value & 0x80 ? '-' : ' ',
5214 decVal / 10000000,
5215 decVal % 10000000 / 1000000);
5216 else if (!(decVal % 10000))
5217 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
5218 floatVal, value & 0x80 ? '-' : ' ',
5219 decVal / 10000000,
5220 decVal % 10000000 / 10000);
5221 else
5222 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
5223 floatVal, value & 0x80 ? '-' : ' ',
5224 decVal / 10000000, decVal % 10000000);
5225 break;
5226 }
0313a2b8
NC		 5227 case 'k':
5228 {
5229 int from = (given & (1 << 7)) ? 32 : 16;
5230 func (stream, "%ld", from - value);
5231 }
5232 break;
8f06b2d8 5233
0313a2b8
NC		 5234 case 'f':
5235 if (value > 7)
5236 func (stream, "#%s", arm_fp_const[value & 7]);
5237 else
5238 func (stream, "f%ld", value);
5239 break;
4146fd53 5240
0313a2b8
NC		 5241 case 'w':
5242 if (width == 2)
5243 func (stream, "%s", iwmmxt_wwnames[value]);
5244 else
5245 func (stream, "%s", iwmmxt_wwssnames[value]);
5246 break;
4146fd53 5247
0313a2b8
NC		 5248 case 'g':
5249 func (stream, "%s", iwmmxt_regnames[value]);
5250 break;
5251 case 'G':
5252 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 5253 break;
8f06b2d8 5254
0313a2b8 5255 case 'x':
d1aaab3c 5256 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 5257 break;
8f06b2d8 5258
33399f07
MGD		 5259 case 'c':
5260 switch (value)
5261 {
5262 case 0:
5263 func (stream, "eq");
5264 break;
5265
5266 case 1:
5267 func (stream, "vs");
5268 break;
5269
5270 case 2:
5271 func (stream, "ge");
5272 break;
5273
5274 case 3:
5275 func (stream, "gt");
5276 break;
5277
5278 default:
5279 func (stream, "??");
5280 break;
5281 }
5282 break;
5283
0313a2b8
NC		 5284 case '`':
5285 c++;
5286 if (value == 0)
5287 func (stream, "%c", *c);
5288 break;
5289 case '\'':
5290 c++;
5291 if (value == ((1ul << width) - 1))
5292 func (stream, "%c", *c);
5293 break;
5294 case '?':
fe56b6ce 5295 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 5296 c += 1 << width;
5297 break;
5298 default:
5299 abort ();
5300 }
dffaa15c
AM		 5301 }
5302 break;
0313a2b8 5303
dffaa15c
AM		 5304 case 'y':
5305 case 'z':
5306 {
5307 int single = *c++ == 'y';
5308 int regno;
8f06b2d8 5309
dffaa15c
AM		 5310 switch (*c)
5311 {
5312 case '4': /* Sm pair */
5313 case '0': /* Sm, Dm */
5314 regno = given & 0x0000000f;
5315 if (single)
5316 {
5317 regno <<= 1;
5318 regno += (given >> 5) & 1;
5319 }
5320 else
5321 regno += ((given >> 5) & 1) << 4;
5322 break;
8f06b2d8 5323
dffaa15c
AM		 5324 case '1': /* Sd, Dd */
5325 regno = (given >> 12) & 0x0000000f;
5326 if (single)
5327 {
5328 regno <<= 1;
5329 regno += (given >> 22) & 1;
5330 }
5331 else
5332 regno += ((given >> 22) & 1) << 4;
5333 break;
7df76b80 5334
dffaa15c
AM		 5335 case '2': /* Sn, Dn */
5336 regno = (given >> 16) & 0x0000000f;
5337 if (single)
5338 {
5339 regno <<= 1;
5340 regno += (given >> 7) & 1;
5341 }
5342 else
5343 regno += ((given >> 7) & 1) << 4;
5344 break;
a7f8487e 5345
dffaa15c
AM		 5346 case '3': /* List */
5347 func (stream, "{");
5348 regno = (given >> 12) & 0x0000000f;
5349 if (single)
5350 {
5351 regno <<= 1;
5352 regno += (given >> 22) & 1;
5353 }
5354 else
5355 regno += ((given >> 22) & 1) << 4;
5356 break;
a7f8487e 5357
dffaa15c
AM		 5358 default:
5359 abort ();
5360 }
0313a2b8 5361
dffaa15c 5362 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 5363
dffaa15c
AM		 5364 if (*c == '3')
5365 {
5366 int count = given & 0xff;
b34976b6 5367
dffaa15c
AM		 5368 if (single == 0)
5369 count >>= 1;
0313a2b8 5370
dffaa15c
AM		 5371 if (--count)
5372 {
5373 func (stream, "-%c%d",
5374 single ? 's' : 'd',
5375 regno + count);
5376 }
0313a2b8 5377
dffaa15c 5378 func (stream, "}");
0313a2b8 5379 }
dffaa15c
AM		 5380 else if (*c == '4')
5381 func (stream, ", %c%d", single ? 's' : 'd',
5382 regno + 1);
5383 }
5384 break;
b34976b6 5385
dffaa15c
AM		 5386 case 'L':
5387 switch (given & 0x00400100)
0313a2b8 5388 {
dffaa15c
AM		 5389 case 0x00000000: func (stream, "b"); break;
5390 case 0x00400000: func (stream, "h"); break;
5391 case 0x00000100: func (stream, "w"); break;
5392 case 0x00400100: func (stream, "d"); break;
5393 default:
5394 break;
0313a2b8 5395 }
dffaa15c 5396 break;
2d447fca 5397
dffaa15c
AM		 5398 case 'Z':
5399 {
5400 /* given (20, 23) | given (0, 3) */
5401 value = ((given >> 16) & 0xf0) | (given & 0xf);
5402 func (stream, "%d", (int) value);
5403 }
5404 break;
0313a2b8 5405
dffaa15c
AM		 5406 case 'l':
5407 /* This is like the 'A' operator, except that if
5408 the width field "M" is zero, then the offset is
5409 *not* multiplied by four. */
5410 {
5411 int offset = given & 0xff;
5412 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 5413
dffaa15c 5414 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 5415
dffaa15c
AM		 5416 if (multiplier > 1)
5417 {
5418 value_in_comment = offset * multiplier;
5419 if (NEGATIVE_BIT_SET)
5420 value_in_comment = - value_in_comment;
5421 }
0313a2b8 5422
dffaa15c
AM		 5423 if (offset)
5424 {
5425 if (PRE_BIT_SET)
5426 func (stream, ", #%s%d]%s",
5427 NEGATIVE_BIT_SET ? "-" : "",
5428 offset * multiplier,
5429 WRITEBACK_BIT_SET ? "!" : "");
5430 else
5431 func (stream, "], #%s%d",
5432 NEGATIVE_BIT_SET ? "-" : "",
5433 offset * multiplier);
5434 }
5435 else
5436 func (stream, "]");
5437 }
5438 break;
2d447fca 5439
dffaa15c
AM		 5440 case 'r':
5441 {
5442 int imm4 = (given >> 4) & 0xf;
5443 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
5444 int ubit = ! NEGATIVE_BIT_SET;
5445 const char *rm = arm_regnames [given & 0xf];
5446 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 5447
dffaa15c
AM		 5448 switch (puw_bits)
5449 {
5450 case 1:
5451 case 3:
5452 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
5453 if (imm4)
5454 func (stream, ", lsl #%d", imm4);
5455 break;
0313a2b8 5456
dffaa15c
AM		 5457 case 4:
5458 case 5:
5459 case 6:
5460 case 7:
5461 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
5462 if (imm4 > 0)
5463 func (stream, ", lsl #%d", imm4);
5464 func (stream, "]");
5465 if (puw_bits == 5 || puw_bits == 7)
5466 func (stream, "!");
5467 break;
2d447fca 5468
dffaa15c
AM		 5469 default:
5470 func (stream, "INVALID");
5471 }
5472 }
5473 break;
0313a2b8 5474
dffaa15c
AM		 5475 case 'i':
5476 {
5477 long imm5;
5478 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
5479 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 5480 }
dffaa15c
AM		 5481 break;
5482
5483 default:
5484 abort ();
252b5132 5485 }
252b5132 5486 }
0313a2b8
NC		 5487 else
5488 func (stream, "%c", *c);
252b5132 5489 }
05413229
NC		 5490
5491 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5492 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 5493
ff4a8d2b
NC		 5494 if (is_unpredictable)
5495 func (stream, UNPREDICTABLE_INSTRUCTION);
5496
0313a2b8 5497 return TRUE;
252b5132 5498 }
8f06b2d8 5499 return FALSE;
252b5132
RH		 5500}
5501
05413229
NC		 5502/* Decodes and prints ARM addressing modes. Returns the offset
5503 used in the address, if any, if it is worthwhile printing the
5504 offset as a hexadecimal value in a comment at the end of the
5505 line of disassembly. */
5506
5507static signed long
62b3e311
PB		 5508print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
5509{
5510 void *stream = info->stream;
5511 fprintf_ftype func = info->fprintf_func;
f8b960bc 5512 bfd_vma offset = 0;
62b3e311
PB		 5513
5514 if (((given & 0x000f0000) == 0x000f0000)
5515 && ((given & 0x02000000) == 0))
5516 {
05413229 5517 offset = given & 0xfff;
62b3e311
PB		 5518
5519 func (stream, "[pc");
5520
c1e26897 5521 if (PRE_BIT_SET)
62b3e311 5522 {
26d97720
NS		 5523 /* Pre-indexed. Elide offset of positive zero when
5524 non-writeback. */
5525 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 5526 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 5527
5528 if (NEGATIVE_BIT_SET)
5529 offset = -offset;
62b3e311
PB		 5530
5531 offset += pc + 8;
5532
5533 /* Cope with the possibility of write-back
5534 being used. Probably a very dangerous thing
5535 for the programmer to do, but who are we to
5536 argue ? */
26d97720 5537 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 5538 }
c1e26897 5539 else /* Post indexed. */
62b3e311 5540 {
d908c8af 5541 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 5542
c1e26897 5543 /* Ie ignore the offset. */
62b3e311
PB		 5544 offset = pc + 8;
5545 }
5546
5547 func (stream, "\t; ");
5548 info->print_address_func (offset, info);
05413229 5549 offset = 0;
62b3e311
PB		 5550 }
5551 else
5552 {
5553 func (stream, "[%s",
5554 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 5555
5556 if (PRE_BIT_SET)
62b3e311
PB		 5557 {
5558 if ((given & 0x02000000) == 0)
5559 {
26d97720 5560 /* Elide offset of positive zero when non-writeback. */
05413229 5561 offset = given & 0xfff;
26d97720 5562 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 5563 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 5564 }
5565 else
5566 {
26d97720 5567 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 5568 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 5569 }
5570
5571 func (stream, "]%s",
c1e26897 5572 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 5573 }
5574 else
5575 {
5576 if ((given & 0x02000000) == 0)
5577 {
26d97720 5578 /* Always show offset. */
05413229 5579 offset = given & 0xfff;
26d97720 5580 func (stream, "], #%s%d",
d908c8af 5581 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 5582 }
5583 else
5584 {
5585 func (stream, "], %s",
c1e26897 5586 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 5587 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 5588 }
5589 }
84919466
MR		 5590 if (NEGATIVE_BIT_SET)
5591 offset = -offset;
62b3e311 5592 }
05413229
NC		 5593
5594 return (signed long) offset;
62b3e311
PB		 5595}
5596
16980d0b
JB		 5597/* Print one neon instruction on INFO->STREAM.
5598 Return TRUE if the instuction matched, FALSE if this is not a
5599 recognised neon instruction. */
5600
5601static bfd_boolean
5602print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
5603{
5604 const struct opcode32 *insn;
5605 void *stream = info->stream;
5606 fprintf_ftype func = info->fprintf_func;
5607
5608 if (thumb)
5609 {
5610 if ((given & 0xef000000) == 0xef000000)
5611 {
0313a2b8 5612 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 5613 unsigned long bit28 = given & (1 << 28);
5614
5615 given &= 0x00ffffff;
5616 if (bit28)
5617 given |= 0xf3000000;
5618 else
5619 given |= 0xf2000000;
5620 }
5621 else if ((given & 0xff000000) == 0xf9000000)
5622 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 5623 /* vdup is also a valid neon instruction. */
5624 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 5625 return FALSE;
5626 }
43e65147 5627
16980d0b
JB		 5628 for (insn = neon_opcodes; insn->assembler; insn++)
5629 {
5630 if ((given & insn->mask) == insn->value)
5631 {
05413229 5632 signed long value_in_comment = 0;
e2efe87d 5633 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 5634 const char *c;
5635
5636 for (c = insn->assembler; *c; c++)
5637 {
5638 if (*c == '%')
5639 {
5640 switch (*++c)
5641 {
5642 case '%':
5643 func (stream, "%%");
5644 break;
5645
e2efe87d
MGD		 5646 case 'u':
5647 if (thumb && ifthen_state)
5648 is_unpredictable = TRUE;
5649
5650 /* Fall through. */
c22aaad1
PB		 5651 case 'c':
5652 if (thumb && ifthen_state)
5653 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5654 break;
5655
16980d0b
JB		 5656 case 'A':
5657 {
43e65147 5658 static const unsigned char enc[16] =
16980d0b
JB		 5659 {
5660 0x4, 0x14, /* st4 0,1 */
5661 0x4, /* st1 2 */
5662 0x4, /* st2 3 */
5663 0x3, /* st3 4 */
5664 0x13, /* st3 5 */
5665 0x3, /* st1 6 */
5666 0x1, /* st1 7 */
5667 0x2, /* st2 8 */
5668 0x12, /* st2 9 */
5669 0x2, /* st1 10 */
5670 0, 0, 0, 0, 0
5671 };
5672 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5673 int rn = ((given >> 16) & 0xf);
5674 int rm = ((given >> 0) & 0xf);
5675 int align = ((given >> 4) & 0x3);
5676 int type = ((given >> 8) & 0xf);
5677 int n = enc[type] & 0xf;
5678 int stride = (enc[type] >> 4) + 1;
5679 int ix;
43e65147 5680
16980d0b
JB		 5681 func (stream, "{");
5682 if (stride > 1)
5683 for (ix = 0; ix != n; ix++)
5684 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
5685 else if (n == 1)
5686 func (stream, "d%d", rd);
5687 else
5688 func (stream, "d%d-d%d", rd, rd + n - 1);
5689 func (stream, "}, [%s", arm_regnames[rn]);
5690 if (align)
8e560766 5691 func (stream, " :%d", 32 << align);
16980d0b
JB		 5692 func (stream, "]");
5693 if (rm == 0xd)
5694 func (stream, "!");
5695 else if (rm != 0xf)
5696 func (stream, ", %s", arm_regnames[rm]);
5697 }
5698 break;
43e65147 5699
16980d0b
JB		 5700 case 'B':
5701 {
5702 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5703 int rn = ((given >> 16) & 0xf);
5704 int rm = ((given >> 0) & 0xf);
5705 int idx_align = ((given >> 4) & 0xf);
5706 int align = 0;
5707 int size = ((given >> 10) & 0x3);
5708 int idx = idx_align >> (size + 1);
5709 int length = ((given >> 8) & 3) + 1;
5710 int stride = 1;
5711 int i;
5712
5713 if (length > 1 && size > 0)
5714 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 5715
16980d0b
JB		 5716 switch (length)
5717 {
5718 case 1:
5719 {
5720 int amask = (1 << size) - 1;
5721 if ((idx_align & (1 << size)) != 0)
5722 return FALSE;
5723 if (size > 0)
5724 {
5725 if ((idx_align & amask) == amask)
5726 align = 8 << size;
5727 else if ((idx_align & amask) != 0)
5728 return FALSE;
5729 }
5730 }
5731 break;
43e65147 5732
16980d0b
JB		 5733 case 2:
5734 if (size == 2 && (idx_align & 2) != 0)
5735 return FALSE;
5736 align = (idx_align & 1) ? 16 << size : 0;
5737 break;
43e65147 5738
16980d0b
JB		 5739 case 3:
5740 if ((size == 2 && (idx_align & 3) != 0)
5741 || (idx_align & 1) != 0)
5742 return FALSE;
5743 break;
43e65147 5744
16980d0b
JB		 5745 case 4:
5746 if (size == 2)
5747 {
5748 if ((idx_align & 3) == 3)
5749 return FALSE;
5750 align = (idx_align & 3) * 64;
5751 }
5752 else
5753 align = (idx_align & 1) ? 32 << size : 0;
5754 break;
43e65147 5755
16980d0b
JB		 5756 default:
5757 abort ();
5758 }
43e65147 5759
16980d0b
JB		 5760 func (stream, "{");
5761 for (i = 0; i < length; i++)
5762 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
5763 rd + i * stride, idx);
5764 func (stream, "}, [%s", arm_regnames[rn]);
5765 if (align)
8e560766 5766 func (stream, " :%d", align);
16980d0b
JB		 5767 func (stream, "]");
5768 if (rm == 0xd)
5769 func (stream, "!");
5770 else if (rm != 0xf)
5771 func (stream, ", %s", arm_regnames[rm]);
5772 }
5773 break;
43e65147 5774
16980d0b
JB		 5775 case 'C':
5776 {
5777 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5778 int rn = ((given >> 16) & 0xf);
5779 int rm = ((given >> 0) & 0xf);
5780 int align = ((given >> 4) & 0x1);
5781 int size = ((given >> 6) & 0x3);
5782 int type = ((given >> 8) & 0x3);
5783 int n = type + 1;
5784 int stride = ((given >> 5) & 0x1);
5785 int ix;
43e65147 5786
16980d0b
JB		 5787 if (stride && (n == 1))
5788 n++;
5789 else
5790 stride++;
43e65147 5791
16980d0b
JB		 5792 func (stream, "{");
5793 if (stride > 1)
5794 for (ix = 0; ix != n; ix++)
5795 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
5796 else if (n == 1)
5797 func (stream, "d%d[]", rd);
5798 else
5799 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
5800 func (stream, "}, [%s", arm_regnames[rn]);
5801 if (align)
5802 {
91d6fa6a 5803 align = (8 * (type + 1)) << size;
16980d0b
JB		 5804 if (type == 3)
5805 align = (size > 1) ? align >> 1 : align;
5806 if (type == 2 || (type == 0 && !size))
8e560766 5807 func (stream, " :<bad align %d>", align);
16980d0b 5808 else
8e560766 5809 func (stream, " :%d", align);
16980d0b
JB		 5810 }
5811 func (stream, "]");
5812 if (rm == 0xd)
5813 func (stream, "!");
5814 else if (rm != 0xf)
5815 func (stream, ", %s", arm_regnames[rm]);
5816 }
5817 break;
43e65147 5818
16980d0b
JB		 5819 case 'D':
5820 {
5821 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
5822 int size = (given >> 20) & 3;
5823 int reg = raw_reg & ((4 << size) - 1);
5824 int ix = raw_reg >> size >> 2;
43e65147 5825
16980d0b
JB		 5826 func (stream, "d%d[%d]", reg, ix);
5827 }
5828 break;
43e65147 5829
16980d0b 5830 case 'E':
fe56b6ce 5831 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 5832 {
5833 int bits = 0;
5834 int cmode = (given >> 8) & 0xf;
5835 int op = (given >> 5) & 0x1;
5836 unsigned long value = 0, hival = 0;
5837 unsigned shift;
5838 int size = 0;
0dbde4cf 5839 int isfloat = 0;
43e65147 5840
16980d0b
JB		 5841 bits |= ((given >> 24) & 1) << 7;
5842 bits |= ((given >> 16) & 7) << 4;
5843 bits |= ((given >> 0) & 15) << 0;
43e65147 5844
16980d0b
JB		 5845 if (cmode < 8)
5846 {
5847 shift = (cmode >> 1) & 3;
fe56b6ce 5848 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 5849 size = 32;
5850 }
5851 else if (cmode < 12)
5852 {
5853 shift = (cmode >> 1) & 1;
fe56b6ce 5854 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 5855 size = 16;
5856 }
5857 else if (cmode < 14)
5858 {
5859 shift = (cmode & 1) + 1;
fe56b6ce 5860 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 5861 value |= (1ul << (8 * shift)) - 1;
5862 size = 32;
5863 }
5864 else if (cmode == 14)
5865 {
5866 if (op)
5867 {
fe56b6ce 5868 /* Bit replication into bytes. */
16980d0b
JB		 5869 int ix;
5870 unsigned long mask;
43e65147 5871
16980d0b
JB		 5872 value = 0;
5873 hival = 0;
5874 for (ix = 7; ix >= 0; ix--)
5875 {
5876 mask = ((bits >> ix) & 1) ? 0xff : 0;
5877 if (ix <= 3)
5878 value = (value << 8) | mask;
5879 else
5880 hival = (hival << 8) | mask;
5881 }
5882 size = 64;
5883 }
5884 else
5885 {
fe56b6ce
NC		 5886 /* Byte replication. */
5887 value = (unsigned long) bits;
16980d0b
JB		 5888 size = 8;
5889 }
5890 }
5891 else if (!op)
5892 {
fe56b6ce 5893 /* Floating point encoding. */
16980d0b 5894 int tmp;
43e65147 5895
fe56b6ce
NC		 5896 value = (unsigned long) (bits & 0x7f) << 19;
5897 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 5898 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 5899 value |= (unsigned long) tmp << 24;
16980d0b 5900 size = 32;
0dbde4cf 5901 isfloat = 1;
16980d0b
JB		 5902 }
5903 else
5904 {
5905 func (stream, "<illegal constant %.8x:%x:%x>",
5906 bits, cmode, op);
5907 size = 32;
5908 break;
5909 }
5910 switch (size)
5911 {
5912 case 8:
5913 func (stream, "#%ld\t; 0x%.2lx", value, value);
5914 break;
43e65147 5915
16980d0b
JB		 5916 case 16:
5917 func (stream, "#%ld\t; 0x%.4lx", value, value);
5918 break;
5919
5920 case 32:
0dbde4cf
JB		 5921 if (isfloat)
5922 {
5923 unsigned char valbytes[4];
5924 double fvalue;
43e65147 5925
0dbde4cf
JB		 5926 /* Do this a byte at a time so we don't have to
5927 worry about the host's endianness. */
5928 valbytes[0] = value & 0xff;
5929 valbytes[1] = (value >> 8) & 0xff;
5930 valbytes[2] = (value >> 16) & 0xff;
5931 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 5932
5933 floatformat_to_double
c1e26897
NC		 5934 (& floatformat_ieee_single_little, valbytes,
5935 & fvalue);
43e65147 5936
0dbde4cf
JB		 5937 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5938 value);
5939 }
5940 else
4e9d3b81 5941 func (stream, "#%ld\t; 0x%.8lx",
43e65147 5942 (long) (((value & 0x80000000L) != 0)
9d82ec38 5943 ? value | ~0xffffffffL : value),
c1e26897 5944 value);
16980d0b
JB		 5945 break;
5946
5947 case 64:
5948 func (stream, "#0x%.8lx%.8lx", hival, value);
5949 break;
43e65147 5950
16980d0b
JB		 5951 default:
5952 abort ();
5953 }
5954 }
5955 break;
43e65147 5956
16980d0b
JB		 5957 case 'F':
5958 {
5959 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
5960 int num = (given >> 8) & 0x3;
43e65147 5961
16980d0b
JB		 5962 if (!num)
5963 func (stream, "{d%d}", regno);
5964 else if (num + regno >= 32)
5965 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
5966 else
5967 func (stream, "{d%d-d%d}", regno, regno + num);
5968 }
5969 break;
7e8e6784 5970
16980d0b
JB		 5971
5972 case '0': case '1': case '2': case '3': case '4':
5973 case '5': case '6': case '7': case '8': case '9':
5974 {
5975 int width;
5976 unsigned long value;
5977
5978 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5979
16980d0b
JB		 5980 switch (*c)
5981 {
5982 case 'r':
5983 func (stream, "%s", arm_regnames[value]);
5984 break;
5985 case 'd':
5986 func (stream, "%ld", value);
05413229 5987 value_in_comment = value;
16980d0b
JB		 5988 break;
5989 case 'e':
5990 func (stream, "%ld", (1ul << width) - value);
5991 break;
43e65147 5992
16980d0b
JB		 5993 case 'S':
5994 case 'T':
5995 case 'U':
05413229 5996 /* Various width encodings. */
16980d0b
JB		 5997 {
5998 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
5999 int limit;
6000 unsigned low, high;
6001
6002 c++;
6003 if (*c >= '0' && *c <= '9')
6004 limit = *c - '0';
6005 else if (*c >= 'a' && *c <= 'f')
6006 limit = *c - 'a' + 10;
6007 else
6008 abort ();
6009 low = limit >> 2;
6010 high = limit & 3;
6011
6012 if (value < low || value > high)
6013 func (stream, "<illegal width %d>", base << value);
6014 else
6015 func (stream, "%d", base << value);
6016 }
6017 break;
6018 case 'R':
6019 if (given & (1 << 6))
6020 goto Q;
6021 /* FALLTHROUGH */
6022 case 'D':
6023 func (stream, "d%ld", value);
6024 break;
6025 case 'Q':
6026 Q:
6027 if (value & 1)
6028 func (stream, "<illegal reg q%ld.5>", value >> 1);
6029 else
6030 func (stream, "q%ld", value >> 1);
6031 break;
43e65147 6032
16980d0b
JB		 6033 case '`':
6034 c++;
6035 if (value == 0)
6036 func (stream, "%c", *c);
6037 break;
6038 case '\'':
6039 c++;
6040 if (value == ((1ul << width) - 1))
6041 func (stream, "%c", *c);
6042 break;
6043 case '?':
fe56b6ce 6044 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 6045 c += 1 << width;
6046 break;
6047 default:
6048 abort ();
6049 }
16980d0b 6050 }
dffaa15c
AM		 6051 break;
6052
6053 default:
6054 abort ();
16980d0b
JB		 6055 }
6056 }
6057 else
6058 func (stream, "%c", *c);
6059 }
05413229
NC		 6060
6061 if (value_in_comment > 32 || value_in_comment < -16)
6062 func (stream, "\t; 0x%lx", value_in_comment);
6063
e2efe87d
MGD		 6064 if (is_unpredictable)
6065 func (stream, UNPREDICTABLE_INSTRUCTION);
6066
16980d0b
JB		 6067 return TRUE;
6068 }
6069 }
6070 return FALSE;
6071}
6072
73cd51e5
AV		 6073/* Print one mve instruction on INFO->STREAM.
6074 Return TRUE if the instuction matched, FALSE if this is not a
6075 recognised mve instruction. */
6076
6077static bfd_boolean
6078print_insn_mve (struct disassemble_info *info, long given)
6079{
6080 const struct mopcode32 *insn;
6081 void *stream = info->stream;
6082 fprintf_ftype func = info->fprintf_func;
6083
6084 for (insn = mve_opcodes; insn->assembler; insn++)
6085 {
6086 if (((given & insn->mask) == insn->value)
6087 && !is_mve_encoding_conflict (given, insn->mve_op))
6088 {
6089 signed long value_in_comment = 0;
6090 bfd_boolean is_unpredictable = FALSE;
6091 bfd_boolean is_undefined = FALSE;
6092 const char *c;
6093 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
6094 enum mve_undefined undefined_cond = UNDEF_NONE;
6095
6096 /* Most vector mve instruction are illegal in a it block.
6097 There are a few exceptions; check for them. */
6098 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
6099 {
6100 is_unpredictable = TRUE;
6101 unpredictable_cond = UNPRED_IT_BLOCK;
6102 }
6103 else if (is_mve_unpredictable (given, insn->mve_op,
6104 &unpredictable_cond))
6105 is_unpredictable = TRUE;
6106
6107 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
6108 is_undefined = TRUE;
6109
6110 for (c = insn->assembler; *c; c++)
6111 {
6112 if (*c == '%')
6113 {
6114 switch (*++c)
6115 {
6116 case '%':
6117 func (stream, "%%");
6118 break;
6119
143275ea
AV		 6120 case 'c':
6121 if (ifthen_state)
6122 func (stream, "%s", arm_conditional[IFTHEN_COND]);
6123 break;
6124
aef6d006
AV		 6125 case 'd':
6126 print_mve_vld_str_addr (info, given, insn->mve_op);
6127 break;
6128
143275ea
AV		 6129 case 'i':
6130 {
6131 long mve_mask = mve_extract_pred_mask (given);
6132 func (stream, "%s", mve_predicatenames[mve_mask]);
6133 }
6134 break;
6135
6136 case 'n':
6137 print_vec_condition (info, given, insn->mve_op);
6138 break;
6139
aef6d006
AV		 6140 case 'u':
6141 {
6142 if (arm_decode_field (given, 28, 28) == 0)
6143 func (stream, "s");
6144 else
6145 func (stream, "u");
6146 }
6147
143275ea
AV		 6148 case 'v':
6149 print_instruction_predicate (info);
6150 break;
6151
04d54ace
AV		 6152 case 'w':
6153 if (arm_decode_field (given, 21, 21) == 1)
6154 func (stream, "!");
6155 break;
6156
6157 case 'B':
6158 print_mve_register_blocks (info, given, insn->mve_op);
6159 break;
6160
143275ea
AV		 6161 case '0': case '1': case '2': case '3': case '4':
6162 case '5': case '6': case '7': case '8': case '9':
6163 {
6164 int width;
6165 unsigned long value;
6166
6167 c = arm_decode_bitfield (c, given, &value, &width);
6168
6169 switch (*c)
6170 {
6171 case 'Z':
6172 if (value == 13)
6173 is_unpredictable = TRUE;
6174 else if (value == 15)
6175 func (stream, "zr");
6176 else
6177 func (stream, "%s", arm_regnames[value]);
6178 break;
6179 case 's':
6180 print_mve_size (info,
6181 value,
6182 insn->mve_op);
6183 break;
9743db03
AV		 6184 case 'r':
6185 func (stream, "%s", arm_regnames[value]);
6186 break;
04d54ace
AV		 6187 case 'd':
6188 func (stream, "%ld", value);
6189 value_in_comment = value;
6190 break;
143275ea
AV		 6191 case 'Q':
6192 if (value & 0x8)
6193 func (stream, "<illegal reg q%ld.5>", value);
6194 else
6195 func (stream, "q%ld", value);
6196 break;
6197 default:
6198 abort ();
6199 }
6200 break;
6201 default:
6202 abort ();
6203 }
73cd51e5
AV		 6204 }
6205 }
6206 else
6207 func (stream, "%c", *c);
6208 }
6209
6210 if (value_in_comment > 32 || value_in_comment < -16)
6211 func (stream, "\t; 0x%lx", value_in_comment);
6212
6213 if (is_unpredictable)
6214 print_mve_unpredictable (info, unpredictable_cond);
6215
6216 if (is_undefined)
6217 print_mve_undefined (info, undefined_cond);
6218
143275ea
AV		 6219 if ((vpt_block_state.in_vpt_block == FALSE)
6220 && !ifthen_state
6221 && (is_vpt_instruction (given) == TRUE))
6222 mark_inside_vpt_block (given);
6223 else if (vpt_block_state.in_vpt_block == TRUE)
6224 update_vpt_block_state ();
6225
73cd51e5
AV		 6226 return TRUE;
6227 }
6228 }
6229 return FALSE;
6230}
6231
6232
90ec0d68
MGD		 6233/* Return the name of a v7A special register. */
6234
43e65147 6235static const char *
90ec0d68
MGD		 6236banked_regname (unsigned reg)
6237{
6238 switch (reg)
6239 {
6240 case 15: return "CPSR";
43e65147 6241 case 32: return "R8_usr";
90ec0d68
MGD		 6242 case 33: return "R9_usr";
6243 case 34: return "R10_usr";
6244 case 35: return "R11_usr";
6245 case 36: return "R12_usr";
6246 case 37: return "SP_usr";
6247 case 38: return "LR_usr";
43e65147 6248 case 40: return "R8_fiq";
90ec0d68
MGD		 6249 case 41: return "R9_fiq";
6250 case 42: return "R10_fiq";
6251 case 43: return "R11_fiq";
6252 case 44: return "R12_fiq";
6253 case 45: return "SP_fiq";
6254 case 46: return "LR_fiq";
6255 case 48: return "LR_irq";
6256 case 49: return "SP_irq";
6257 case 50: return "LR_svc";
6258 case 51: return "SP_svc";
6259 case 52: return "LR_abt";
6260 case 53: return "SP_abt";
6261 case 54: return "LR_und";
6262 case 55: return "SP_und";
6263 case 60: return "LR_mon";
6264 case 61: return "SP_mon";
6265 case 62: return "ELR_hyp";
6266 case 63: return "SP_hyp";
6267 case 79: return "SPSR";
6268 case 110: return "SPSR_fiq";
6269 case 112: return "SPSR_irq";
6270 case 114: return "SPSR_svc";
6271 case 116: return "SPSR_abt";
6272 case 118: return "SPSR_und";
6273 case 124: return "SPSR_mon";
6274 case 126: return "SPSR_hyp";
6275 default: return NULL;
6276 }
6277}
6278
e797f7e0
MGD		 6279/* Return the name of the DMB/DSB option. */
6280static const char *
6281data_barrier_option (unsigned option)
6282{
6283 switch (option & 0xf)
6284 {
6285 case 0xf: return "sy";
6286 case 0xe: return "st";
6287 case 0xd: return "ld";
6288 case 0xb: return "ish";
6289 case 0xa: return "ishst";
6290 case 0x9: return "ishld";
6291 case 0x7: return "un";
6292 case 0x6: return "unst";
6293 case 0x5: return "nshld";
6294 case 0x3: return "osh";
6295 case 0x2: return "oshst";
6296 case 0x1: return "oshld";
6297 default: return NULL;
6298 }
6299}
6300
4a5329c6
ZW		 6301/* Print one ARM instruction from PC on INFO->STREAM. */
6302
6303static void
6304print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 6305{
6b5d3a4d 6306 const struct opcode32 *insn;
6a51a8a8 6307 void *stream = info->stream;
6b5d3a4d 6308 fprintf_ftype func = info->fprintf_func;
b0e28b39 6309 struct arm_private_data *private_data = info->private_data;
252b5132 6310
16980d0b
JB		 6311 if (print_insn_coprocessor (pc, info, given, FALSE))
6312 return;
6313
6314 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 6315 return;
6316
252b5132
RH		 6317 for (insn = arm_opcodes; insn->assembler; insn++)
6318 {
0313a2b8
NC		 6319 if ((given & insn->mask) != insn->value)
6320 continue;
823d2571
TG		 6321
6322 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 6323 continue;
6324
6325 /* Special case: an instruction with all bits set in the condition field
6326 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
6327 or by the catchall at the end of the table. */
6328 if ((given & 0xF0000000) != 0xF0000000
6329 || (insn->mask & 0xF0000000) == 0xF0000000
6330 || (insn->mask == 0 && insn->value == 0))
252b5132 6331 {
ff4a8d2b
NC		 6332 unsigned long u_reg = 16;
6333 unsigned long U_reg = 16;
ab8e2090 6334 bfd_boolean is_unpredictable = FALSE;
05413229 6335 signed long value_in_comment = 0;
6b5d3a4d 6336 const char *c;
b34976b6 6337
252b5132
RH		 6338 for (c = insn->assembler; *c; c++)
6339 {
6340 if (*c == '%')
6341 {
c1e26897
NC		 6342 bfd_boolean allow_unpredictable = FALSE;
6343
252b5132
RH		 6344 switch (*++c)
6345 {
6346 case '%':
6347 func (stream, "%%");
6348 break;
6349
6350 case 'a':
05413229 6351 value_in_comment = print_arm_address (pc, info, given);
62b3e311 6352 break;
252b5132 6353
62b3e311
PB		 6354 case 'P':
6355 /* Set P address bit and use normal address
6356 printing routine. */
c1e26897 6357 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 6358 break;
6359
c1e26897
NC		 6360 case 'S':
6361 allow_unpredictable = TRUE;
1a0670f3 6362 /* Fall through. */
252b5132
RH		 6363 case 's':
6364 if ((given & 0x004f0000) == 0x004f0000)
6365 {
58efb6c0 6366 /* PC relative with immediate offset. */
f8b960bc 6367 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 6368
aefd8a40
NC		 6369 if (PRE_BIT_SET)
6370 {
26d97720
NS		 6371 /* Elide positive zero offset. */
6372 if (offset || NEGATIVE_BIT_SET)
6373 func (stream, "[pc, #%s%d]\t; ",
d908c8af 6374 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 6375 else
26d97720
NS		 6376 func (stream, "[pc]\t; ");
6377 if (NEGATIVE_BIT_SET)
6378 offset = -offset;
aefd8a40
NC		 6379 info->print_address_func (offset + pc + 8, info);
6380 }
6381 else
6382 {
26d97720
NS		 6383 /* Always show the offset. */
6384 func (stream, "[pc], #%s%d",
d908c8af 6385 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 6386 if (! allow_unpredictable)
6387 is_unpredictable = TRUE;
aefd8a40 6388 }
252b5132
RH		 6389 }
6390 else
6391 {
fe56b6ce
NC		 6392 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
6393
b34976b6 6394 func (stream, "[%s",
252b5132 6395 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 6396
c1e26897 6397 if (PRE_BIT_SET)
252b5132 6398 {
c1e26897 6399 if (IMMEDIATE_BIT_SET)
252b5132 6400 {
26d97720
NS		 6401 /* Elide offset for non-writeback
6402 positive zero. */
6403 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
6404 || offset)
6405 func (stream, ", #%s%d",
6406 NEGATIVE_BIT_SET ? "-" : "", offset);
6407
6408 if (NEGATIVE_BIT_SET)
6409 offset = -offset;
945ee430 6410
fe56b6ce 6411 value_in_comment = offset;
252b5132 6412 }
945ee430 6413 else
ff4a8d2b
NC		 6414 {
6415 /* Register Offset or Register Pre-Indexed. */
6416 func (stream, ", %s%s",
6417 NEGATIVE_BIT_SET ? "-" : "",
6418 arm_regnames[given & 0xf]);
6419
6420 /* Writing back to the register that is the source/
6421 destination of the load/store is unpredictable. */
6422 if (! allow_unpredictable
6423 && WRITEBACK_BIT_SET
6424 && ((given & 0xf) == ((given >> 12) & 0xf)))
6425 is_unpredictable = TRUE;
6426 }
252b5132 6427
b34976b6 6428 func (stream, "]%s",
c1e26897 6429 WRITEBACK_BIT_SET ? "!" : "");
252b5132 6430 }
945ee430 6431 else
252b5132 6432 {
c1e26897 6433 if (IMMEDIATE_BIT_SET)
252b5132 6434 {
945ee430 6435 /* Immediate Post-indexed. */
aefd8a40 6436 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 6437 func (stream, "], #%s%d",
6438 NEGATIVE_BIT_SET ? "-" : "", offset);
6439 if (NEGATIVE_BIT_SET)
6440 offset = -offset;
fe56b6ce 6441 value_in_comment = offset;
252b5132 6442 }
945ee430 6443 else
ff4a8d2b
NC		 6444 {
6445 /* Register Post-indexed. */
6446 func (stream, "], %s%s",
6447 NEGATIVE_BIT_SET ? "-" : "",
6448 arm_regnames[given & 0xf]);
6449
6450 /* Writing back to the register that is the source/
6451 destination of the load/store is unpredictable. */
6452 if (! allow_unpredictable
6453 && (given & 0xf) == ((given >> 12) & 0xf))
6454 is_unpredictable = TRUE;
6455 }
c1e26897 6456
07a28fab
NC		 6457 if (! allow_unpredictable)
6458 {
6459 /* Writeback is automatically implied by post- addressing.
6460 Setting the W bit is unnecessary and ARM specify it as
6461 being unpredictable. */
6462 if (WRITEBACK_BIT_SET
6463 /* Specifying the PC register as the post-indexed
6464 registers is also unpredictable. */
ab8e2090
NC		 6465 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
6466 is_unpredictable = TRUE;
07a28fab 6467 }
252b5132
RH		 6468 }
6469 }
6470 break;
b34976b6 6471
252b5132 6472 case 'b':
6b5d3a4d 6473 {
f8b960bc 6474 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 6475 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 6476 }
252b5132
RH		 6477 break;
6478
6479 case 'c':
c22aaad1
PB		 6480 if (((given >> 28) & 0xf) != 0xe)
6481 func (stream, "%s",
6482 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 6483 break;
6484
6485 case 'm':
6486 {
6487 int started = 0;
6488 int reg;
6489
6490 func (stream, "{");
6491 for (reg = 0; reg < 16; reg++)
6492 if ((given & (1 << reg)) != 0)
6493 {
6494 if (started)
6495 func (stream, ", ");
6496 started = 1;
6497 func (stream, "%s", arm_regnames[reg]);
6498 }
6499 func (stream, "}");
ab8e2090
NC		 6500 if (! started)
6501 is_unpredictable = TRUE;
252b5132
RH		 6502 }
6503 break;
6504
37b37b2d 6505 case 'q':
78c66db8 6506 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 6507 break;
6508
252b5132
RH		 6509 case 'o':
6510 if ((given & 0x02000000) != 0)
6511 {
a415b1cd
JB		 6512 unsigned int rotate = (given & 0xf00) >> 7;
6513 unsigned int immed = (given & 0xff);
6514 unsigned int a, i;
6515
6516 a = (((immed << (32 - rotate))
6517 | (immed >> rotate)) & 0xffffffff);
6518 /* If there is another encoding with smaller rotate,
6519 the rotate should be specified directly. */
6520 for (i = 0; i < 32; i += 2)
6521 if ((a << i | a >> (32 - i)) <= 0xff)
6522 break;
6523
6524 if (i != rotate)
6525 func (stream, "#%d, %d", immed, rotate);
6526 else
6527 func (stream, "#%d", a);
6528 value_in_comment = a;
252b5132
RH		 6529 }
6530 else
78c66db8 6531 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 6532 break;
6533
6534 case 'p':
6535 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 6536 {
823d2571
TG		 6537 arm_feature_set arm_ext_v6 =
6538 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
6539
aefd8a40
NC		 6540 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
6541 mechanism for setting PSR flag bits. They are
6542 obsolete in V6 onwards. */
823d2571
TG		 6543 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
6544 arm_ext_v6))
aefd8a40 6545 func (stream, "p");
4ab90a7a
AV		 6546 else
6547 is_unpredictable = TRUE;
aefd8a40 6548 }
252b5132
RH		 6549 break;
6550
6551 case 't':
6552 if ((given & 0x01200000) == 0x00200000)
6553 func (stream, "t");
6554 break;
6555
252b5132 6556 case 'A':
05413229
NC		 6557 {
6558 int offset = given & 0xff;
f02232aa 6559
05413229 6560 value_in_comment = offset * 4;
c1e26897 6561 if (NEGATIVE_BIT_SET)
05413229 6562 value_in_comment = - value_in_comment;
f02232aa 6563
05413229 6564 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 6565
c1e26897 6566 if (PRE_BIT_SET)
05413229
NC		 6567 {
6568 if (offset)
fe56b6ce 6569 func (stream, ", #%d]%s",
d908c8af 6570 (int) value_in_comment,
c1e26897 6571 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 6572 else
6573 func (stream, "]");
6574 }
6575 else
6576 {
6577 func (stream, "]");
f02232aa 6578
c1e26897 6579 if (WRITEBACK_BIT_SET)
05413229
NC		 6580 {
6581 if (offset)
d908c8af 6582 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 6583 }
6584 else
fe56b6ce 6585 {
d908c8af 6586 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 6587 value_in_comment = offset;
6588 }
05413229
NC		 6589 }
6590 }
252b5132
RH		 6591 break;
6592
077b8428
NC		 6593 case 'B':
6594 /* Print ARM V5 BLX(1) address: pc+25 bits. */
6595 {
6596 bfd_vma address;
6597 bfd_vma offset = 0;
b34976b6 6598
c1e26897 6599 if (! NEGATIVE_BIT_SET)
077b8428
NC		 6600 /* Is signed, hi bits should be ones. */
6601 offset = (-1) ^ 0x00ffffff;
6602
6603 /* Offset is (SignExtend(offset field)<<2). */
6604 offset += given & 0x00ffffff;
6605 offset <<= 2;
6606 address = offset + pc + 8;
b34976b6 6607
8f06b2d8
PB		 6608 if (given & 0x01000000)
6609 /* H bit allows addressing to 2-byte boundaries. */
6610 address += 2;
b1ee46c5 6611
8f06b2d8 6612 info->print_address_func (address, info);
b1ee46c5 6613 }
b1ee46c5
AH		 6614 break;
6615
252b5132 6616 case 'C':
90ec0d68
MGD		 6617 if ((given & 0x02000200) == 0x200)
6618 {
6619 const char * name;
6620 unsigned sysm = (given & 0x004f0000) >> 16;
6621
6622 sysm |= (given & 0x300) >> 4;
6623 name = banked_regname (sysm);
6624
6625 if (name != NULL)
6626 func (stream, "%s", name);
6627 else
d908c8af 6628 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 6629 }
6630 else
6631 {
43e65147 6632 func (stream, "%cPSR_",
90ec0d68
MGD		 6633 (given & 0x00400000) ? 'S' : 'C');
6634 if (given & 0x80000)
6635 func (stream, "f");
6636 if (given & 0x40000)
6637 func (stream, "s");
6638 if (given & 0x20000)
6639 func (stream, "x");
6640 if (given & 0x10000)
6641 func (stream, "c");
6642 }
252b5132
RH		 6643 break;
6644
62b3e311 6645 case 'U':
43e65147 6646 if ((given & 0xf0) == 0x60)
62b3e311 6647 {
52e7f43d
RE		 6648 switch (given & 0xf)
6649 {
6650 case 0xf: func (stream, "sy"); break;
6651 default:
6652 func (stream, "#%d", (int) given & 0xf);
6653 break;
6654 }
43e65147
L		 6655 }
6656 else
52e7f43d 6657 {
e797f7e0
MGD		 6658 const char * opt = data_barrier_option (given & 0xf);
6659 if (opt != NULL)
6660 func (stream, "%s", opt);
6661 else
52e7f43d 6662 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 6663 }
6664 break;
6665
b34976b6 6666 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 6667 case '5': case '6': case '7': case '8': case '9':
6668 {
16980d0b
JB		 6669 int width;
6670 unsigned long value;
252b5132 6671
16980d0b 6672 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 6673
252b5132
RH		 6674 switch (*c)
6675 {
ab8e2090
NC		 6676 case 'R':
6677 if (value == 15)
6678 is_unpredictable = TRUE;
6679 /* Fall through. */
16980d0b 6680 case 'r':
9eb6c0f1
MGD		 6681 case 'T':
6682 /* We want register + 1 when decoding T. */
6683 if (*c == 'T')
6684 ++value;
6685
ff4a8d2b
NC		 6686 if (c[1] == 'u')
6687 {
6688 /* Eat the 'u' character. */
6689 ++ c;
6690
6691 if (u_reg == value)
6692 is_unpredictable = TRUE;
6693 u_reg = value;
6694 }
6695 if (c[1] == 'U')
6696 {
6697 /* Eat the 'U' character. */
6698 ++ c;
6699
6700 if (U_reg == value)
6701 is_unpredictable = TRUE;
6702 U_reg = value;
6703 }
16980d0b
JB		 6704 func (stream, "%s", arm_regnames[value]);
6705 break;
6706 case 'd':
6707 func (stream, "%ld", value);
05413229 6708 value_in_comment = value;
16980d0b
JB		 6709 break;
6710 case 'b':
6711 func (stream, "%ld", value * 8);
05413229 6712 value_in_comment = value * 8;
16980d0b
JB		 6713 break;
6714 case 'W':
6715 func (stream, "%ld", value + 1);
05413229 6716 value_in_comment = value + 1;
16980d0b
JB		 6717 break;
6718 case 'x':
6719 func (stream, "0x%08lx", value);
6720
6721 /* Some SWI instructions have special
6722 meanings. */
6723 if ((given & 0x0fffffff) == 0x0FF00000)
6724 func (stream, "\t; IMB");
6725 else if ((given & 0x0fffffff) == 0x0FF00001)
6726 func (stream, "\t; IMBRange");
6727 break;
6728 case 'X':
6729 func (stream, "%01lx", value & 0xf);
05413229 6730 value_in_comment = value;
252b5132
RH		 6731 break;
6732 case '`':
6733 c++;
16980d0b 6734 if (value == 0)
252b5132
RH		 6735 func (stream, "%c", *c);
6736 break;
6737 case '\'':
6738 c++;
16980d0b 6739 if (value == ((1ul << width) - 1))
252b5132
RH		 6740 func (stream, "%c", *c);
6741 break;
6742 case '?':
fe56b6ce 6743 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 6744 c += 1 << width;
252b5132
RH		 6745 break;
6746 default:
6747 abort ();
6748 }
dffaa15c
AM		 6749 }
6750 break;
0dd132b6 6751
dffaa15c
AM		 6752 case 'e':
6753 {
6754 int imm;
0dd132b6 6755
dffaa15c
AM		 6756 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6757 func (stream, "%d", imm);
6758 value_in_comment = imm;
6759 }
6760 break;
fe56b6ce 6761
dffaa15c
AM		 6762 case 'E':
6763 /* LSB and WIDTH fields of BFI or BFC. The machine-
6764 language instruction encodes LSB and MSB. */
6765 {
6766 long msb = (given & 0x001f0000) >> 16;
6767 long lsb = (given & 0x00000f80) >> 7;
6768 long w = msb - lsb + 1;
0a003adc 6769
dffaa15c
AM		 6770 if (w > 0)
6771 func (stream, "#%lu, #%lu", lsb, w);
6772 else
6773 func (stream, "(invalid: %lu:%lu)", lsb, msb);
6774 }
6775 break;
90ec0d68 6776
dffaa15c
AM		 6777 case 'R':
6778 /* Get the PSR/banked register name. */
6779 {
6780 const char * name;
6781 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 6782
dffaa15c
AM		 6783 sysm |= (given & 0x300) >> 4;
6784 name = banked_regname (sysm);
90ec0d68 6785
dffaa15c
AM		 6786 if (name != NULL)
6787 func (stream, "%s", name);
6788 else
6789 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6790 }
6791 break;
fe56b6ce 6792
dffaa15c
AM		 6793 case 'V':
6794 /* 16-bit unsigned immediate from a MOVT or MOVW
6795 instruction, encoded in bits 0:11 and 15:19. */
6796 {
6797 long hi = (given & 0x000f0000) >> 4;
6798 long lo = (given & 0x00000fff);
6799 long imm16 = hi | lo;
0a003adc 6800
dffaa15c
AM		 6801 func (stream, "#%lu", imm16);
6802 value_in_comment = imm16;
252b5132 6803 }
dffaa15c
AM		 6804 break;
6805
6806 default:
6807 abort ();
252b5132
RH		 6808 }
6809 }
6810 else
6811 func (stream, "%c", *c);
6812 }
05413229
NC		 6813
6814 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 6815 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 6816
6817 if (is_unpredictable)
6818 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 6819
4a5329c6 6820 return;
252b5132
RH		 6821 }
6822 }
0b347048
TC		 6823 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6824 return;
252b5132
RH		 6825}
6826
4a5329c6 6827/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 6828
4a5329c6
ZW		 6829static void
6830print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 6831{
6b5d3a4d 6832 const struct opcode16 *insn;
6a51a8a8
AM		 6833 void *stream = info->stream;
6834 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 6835
6836 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 6837 if ((given & insn->mask) == insn->value)
6838 {
05413229 6839 signed long value_in_comment = 0;
6b5d3a4d 6840 const char *c = insn->assembler;
05413229 6841
c19d1205
ZW		 6842 for (; *c; c++)
6843 {
6844 int domaskpc = 0;
6845 int domasklr = 0;
6846
6847 if (*c != '%')
6848 {
6849 func (stream, "%c", *c);
6850 continue;
6851 }
252b5132 6852
c19d1205
ZW		 6853 switch (*++c)
6854 {
6855 case '%':
6856 func (stream, "%%");
6857 break;
b34976b6 6858
c22aaad1
PB		 6859 case 'c':
6860 if (ifthen_state)
6861 func (stream, "%s", arm_conditional[IFTHEN_COND]);
6862 break;
6863
6864 case 'C':
6865 if (ifthen_state)
6866 func (stream, "%s", arm_conditional[IFTHEN_COND]);
6867 else
6868 func (stream, "s");
6869 break;
6870
6871 case 'I':
6872 {
6873 unsigned int tmp;
6874
6875 ifthen_next_state = given & 0xff;
6876 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6877 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
6878 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
6879 }
6880 break;
6881
6882 case 'x':
6883 if (ifthen_next_state)
6884 func (stream, "\t; unpredictable branch in IT block\n");
6885 break;
6886
6887 case 'X':
6888 if (ifthen_state)
6889 func (stream, "\t; unpredictable <IT:%s>",
6890 arm_conditional[IFTHEN_COND]);
6891 break;
6892
c19d1205
ZW		 6893 case 'S':
6894 {
6895 long reg;
6896
6897 reg = (given >> 3) & 0x7;
6898 if (given & (1 << 6))
6899 reg += 8;
4f3c3dbb 6900
c19d1205
ZW		 6901 func (stream, "%s", arm_regnames[reg]);
6902 }
6903 break;
baf0cc5e 6904
c19d1205 6905 case 'D':
4f3c3dbb 6906 {
c19d1205
ZW		 6907 long reg;
6908
6909 reg = given & 0x7;
6910 if (given & (1 << 7))
6911 reg += 8;
6912
6913 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 6914 }
c19d1205
ZW		 6915 break;
6916
6917 case 'N':
6918 if (given & (1 << 8))
6919 domasklr = 1;
6920 /* Fall through. */
6921 case 'O':
6922 if (*c == 'O' && (given & (1 << 8)))
6923 domaskpc = 1;
6924 /* Fall through. */
6925 case 'M':
6926 {
6927 int started = 0;
6928 int reg;
6929
6930 func (stream, "{");
6931
6932 /* It would be nice if we could spot
6933 ranges, and generate the rS-rE format: */
6934 for (reg = 0; (reg < 8); reg++)
6935 if ((given & (1 << reg)) != 0)
6936 {
6937 if (started)
6938 func (stream, ", ");
6939 started = 1;
6940 func (stream, "%s", arm_regnames[reg]);
6941 }
6942
6943 if (domasklr)
6944 {
6945 if (started)
6946 func (stream, ", ");
6947 started = 1;
d908c8af 6948 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 6949 }
6950
6951 if (domaskpc)
6952 {
6953 if (started)
6954 func (stream, ", ");
d908c8af 6955 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 6956 }
6957
6958 func (stream, "}");
6959 }
6960 break;
6961
4547cb56
NC		 6962 case 'W':
6963 /* Print writeback indicator for a LDMIA. We are doing a
6964 writeback if the base register is not in the register
6965 mask. */
6966 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6967 func (stream, "!");
dffaa15c 6968 break;
4547cb56 6969
c19d1205
ZW		 6970 case 'b':
6971 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
6972 {
6973 bfd_vma address = (pc + 4
6974 + ((given & 0x00f8) >> 2)
6975 + ((given & 0x0200) >> 3));
6976 info->print_address_func (address, info);
6977 }
6978 break;
6979
6980 case 's':
6981 /* Right shift immediate -- bits 6..10; 1-31 print
6982 as themselves, 0 prints as 32. */
6983 {
6984 long imm = (given & 0x07c0) >> 6;
6985 if (imm == 0)
6986 imm = 32;
0fd3a477 6987 func (stream, "#%ld", imm);
c19d1205
ZW		 6988 }
6989 break;
6990
6991 case '0': case '1': case '2': case '3': case '4':
6992 case '5': case '6': case '7': case '8': case '9':
6993 {
6994 int bitstart = *c++ - '0';
6995 int bitend = 0;
6996
6997 while (*c >= '0' && *c <= '9')
6998 bitstart = (bitstart * 10) + *c++ - '0';
6999
7000 switch (*c)
7001 {
7002 case '-':
7003 {
f8b960bc 7004 bfd_vma reg;
c19d1205
ZW		 7005
7006 c++;
7007 while (*c >= '0' && *c <= '9')
7008 bitend = (bitend * 10) + *c++ - '0';
7009 if (!bitend)
7010 abort ();
7011 reg = given >> bitstart;
7012 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 7013
c19d1205
ZW		 7014 switch (*c)
7015 {
7016 case 'r':
7017 func (stream, "%s", arm_regnames[reg]);
7018 break;
7019
7020 case 'd':
d908c8af 7021 func (stream, "%ld", (long) reg);
05413229 7022 value_in_comment = reg;
c19d1205
ZW		 7023 break;
7024
7025 case 'H':
d908c8af 7026 func (stream, "%ld", (long) (reg << 1));
05413229 7027 value_in_comment = reg << 1;
c19d1205
ZW		 7028 break;
7029
7030 case 'W':
d908c8af 7031 func (stream, "%ld", (long) (reg << 2));
05413229 7032 value_in_comment = reg << 2;
c19d1205
ZW		 7033 break;
7034
7035 case 'a':
7036 /* PC-relative address -- the bottom two
7037 bits of the address are dropped
7038 before the calculation. */
7039 info->print_address_func
7040 (((pc + 4) & ~3) + (reg << 2), info);
05413229 7041 value_in_comment = 0;
c19d1205
ZW		 7042 break;
7043
7044 case 'x':
d908c8af 7045 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 7046 break;
7047
c19d1205
ZW		 7048 case 'B':
7049 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 7050 info->print_address_func (reg * 2 + pc + 4, info);
05413229 7051 value_in_comment = 0;
c19d1205
ZW		 7052 break;
7053
7054 case 'c':
c22aaad1 7055 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 7056 break;
7057
7058 default:
7059 abort ();
7060 }
7061 }
7062 break;
7063
7064 case '\'':
7065 c++;
7066 if ((given & (1 << bitstart)) != 0)
7067 func (stream, "%c", *c);
7068 break;
7069
7070 case '?':
7071 ++c;
7072 if ((given & (1 << bitstart)) != 0)
7073 func (stream, "%c", *c++);
7074 else
7075 func (stream, "%c", *++c);
7076 break;
7077
7078 default:
7079 abort ();
7080 }
7081 }
7082 break;
7083
7084 default:
7085 abort ();
7086 }
7087 }
05413229
NC		 7088
7089 if (value_in_comment > 32 || value_in_comment < -16)
7090 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 7091 return;
c19d1205
ZW		 7092 }
7093
7094 /* No match. */
0b347048
TC		 7095 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
7096 return;
c19d1205
ZW		 7097}
7098
62b3e311 7099/* Return the name of an V7M special register. */
fe56b6ce 7100
62b3e311
PB		 7101static const char *
7102psr_name (int regno)
7103{
7104 switch (regno)
7105 {
1a336194
TP		 7106 case 0x0: return "APSR";
7107 case 0x1: return "IAPSR";
7108 case 0x2: return "EAPSR";
7109 case 0x3: return "PSR";
7110 case 0x5: return "IPSR";
7111 case 0x6: return "EPSR";
7112 case 0x7: return "IEPSR";
7113 case 0x8: return "MSP";
7114 case 0x9: return "PSP";
7115 case 0xa: return "MSPLIM";
7116 case 0xb: return "PSPLIM";
7117 case 0x10: return "PRIMASK";
7118 case 0x11: return "BASEPRI";
7119 case 0x12: return "BASEPRI_MAX";
7120 case 0x13: return "FAULTMASK";
7121 case 0x14: return "CONTROL";
16a1fa25
TP		 7122 case 0x88: return "MSP_NS";
7123 case 0x89: return "PSP_NS";
1a336194
TP		 7124 case 0x8a: return "MSPLIM_NS";
7125 case 0x8b: return "PSPLIM_NS";
7126 case 0x90: return "PRIMASK_NS";
7127 case 0x91: return "BASEPRI_NS";
7128 case 0x93: return "FAULTMASK_NS";
7129 case 0x94: return "CONTROL_NS";
7130 case 0x98: return "SP_NS";
62b3e311
PB		 7131 default: return "<unknown>";
7132 }
7133}
7134
4a5329c6
ZW		 7135/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
7136
7137static void
7138print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 7139{
6b5d3a4d 7140 const struct opcode32 *insn;
c19d1205
ZW		 7141 void *stream = info->stream;
7142 fprintf_ftype func = info->fprintf_func;
73cd51e5 7143 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 7144
16980d0b
JB		 7145 if (print_insn_coprocessor (pc, info, given, TRUE))
7146 return;
7147
73cd51e5
AV		 7148 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
7149 return;
7150
7151 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 7152 return;
7153
c19d1205
ZW		 7154 for (insn = thumb32_opcodes; insn->assembler; insn++)
7155 if ((given & insn->mask) == insn->value)
7156 {
4b5a202f 7157 bfd_boolean is_clrm = FALSE;
ff4a8d2b 7158 bfd_boolean is_unpredictable = FALSE;
05413229 7159 signed long value_in_comment = 0;
6b5d3a4d 7160 const char *c = insn->assembler;
05413229 7161
c19d1205
ZW		 7162 for (; *c; c++)
7163 {
7164 if (*c != '%')
7165 {
7166 func (stream, "%c", *c);
7167 continue;
7168 }
7169
7170 switch (*++c)
7171 {
7172 case '%':
7173 func (stream, "%%");
7174 break;
7175
c22aaad1
PB		 7176 case 'c':
7177 if (ifthen_state)
7178 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7179 break;
7180
7181 case 'x':
7182 if (ifthen_next_state)
7183 func (stream, "\t; unpredictable branch in IT block\n");
7184 break;
7185
7186 case 'X':
7187 if (ifthen_state)
7188 func (stream, "\t; unpredictable <IT:%s>",
7189 arm_conditional[IFTHEN_COND]);
7190 break;
7191
c19d1205
ZW		 7192 case 'I':
7193 {
7194 unsigned int imm12 = 0;
fe56b6ce 7195
c19d1205
ZW		 7196 imm12 |= (given & 0x000000ffu);
7197 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 7198 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 7199 func (stream, "#%u", imm12);
7200 value_in_comment = imm12;
c19d1205
ZW		 7201 }
7202 break;
7203
7204 case 'M':
7205 {
7206 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 7207
c19d1205
ZW		 7208 bits |= (given & 0x000000ffu);
7209 bits |= (given & 0x00007000u) >> 4;
7210 bits |= (given & 0x04000000u) >> 15;
7211 imm8 = (bits & 0x0ff);
7212 mod = (bits & 0xf00) >> 8;
7213 switch (mod)
7214 {
7215 case 0: imm = imm8; break;
c1e26897
NC		 7216 case 1: imm = ((imm8 << 16) | imm8); break;
7217 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
7218 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 7219 default:
7220 mod = (bits & 0xf80) >> 7;
7221 imm8 = (bits & 0x07f) | 0x80;
7222 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
7223 }
fe56b6ce
NC		 7224 func (stream, "#%u", imm);
7225 value_in_comment = imm;
c19d1205
ZW		 7226 }
7227 break;
43e65147 7228
c19d1205
ZW		 7229 case 'J':
7230 {
7231 unsigned int imm = 0;
fe56b6ce 7232
c19d1205
ZW		 7233 imm |= (given & 0x000000ffu);
7234 imm |= (given & 0x00007000u) >> 4;
7235 imm |= (given & 0x04000000u) >> 15;
7236 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 7237 func (stream, "#%u", imm);
7238 value_in_comment = imm;
c19d1205
ZW		 7239 }
7240 break;
7241
7242 case 'K':
7243 {
7244 unsigned int imm = 0;
fe56b6ce 7245
c19d1205
ZW		 7246 imm |= (given & 0x000f0000u) >> 16;
7247 imm |= (given & 0x00000ff0u) >> 0;
7248 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 7249 func (stream, "#%u", imm);
7250 value_in_comment = imm;
c19d1205
ZW		 7251 }
7252 break;
7253
74db7efb
NC		 7254 case 'H':
7255 {
7256 unsigned int imm = 0;
7257
7258 imm |= (given & 0x000f0000u) >> 4;
7259 imm |= (given & 0x00000fffu) >> 0;
7260 func (stream, "#%u", imm);
7261 value_in_comment = imm;
7262 }
7263 break;
7264
90ec0d68
MGD		 7265 case 'V':
7266 {
7267 unsigned int imm = 0;
7268
7269 imm |= (given & 0x00000fffu);
7270 imm |= (given & 0x000f0000u) >> 4;
7271 func (stream, "#%u", imm);
7272 value_in_comment = imm;
7273 }
7274 break;
7275
c19d1205
ZW		 7276 case 'S':
7277 {
7278 unsigned int reg = (given & 0x0000000fu);
7279 unsigned int stp = (given & 0x00000030u) >> 4;
7280 unsigned int imm = 0;
7281 imm |= (given & 0x000000c0u) >> 6;
7282 imm |= (given & 0x00007000u) >> 10;
7283
7284 func (stream, "%s", arm_regnames[reg]);
7285 switch (stp)
7286 {
7287 case 0:
7288 if (imm > 0)
7289 func (stream, ", lsl #%u", imm);
7290 break;
7291
7292 case 1:
7293 if (imm == 0)
7294 imm = 32;
7295 func (stream, ", lsr #%u", imm);
7296 break;
7297
7298 case 2:
7299 if (imm == 0)
7300 imm = 32;
7301 func (stream, ", asr #%u", imm);
7302 break;
7303
7304 case 3:
7305 if (imm == 0)
7306 func (stream, ", rrx");
7307 else
7308 func (stream, ", ror #%u", imm);
7309 }
7310 }
7311 break;
7312
7313 case 'a':
7314 {
7315 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 7316 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 7317 unsigned int op = (given & 0x00000f00) >> 8;
7318 unsigned int i12 = (given & 0x00000fff);
7319 unsigned int i8 = (given & 0x000000ff);
7320 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 7321 bfd_vma offset = 0;
c19d1205
ZW		 7322
7323 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 7324 if (U) /* 12-bit positive immediate offset. */
7325 {
7326 offset = i12;
7327 if (Rn != 15)
7328 value_in_comment = offset;
7329 }
7330 else if (Rn == 15) /* 12-bit negative immediate offset. */
7331 offset = - (int) i12;
7332 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 7333 {
7334 unsigned int Rm = (i8 & 0x0f);
7335 unsigned int sh = (i8 & 0x30) >> 4;
05413229 7336
c19d1205
ZW		 7337 func (stream, ", %s", arm_regnames[Rm]);
7338 if (sh)
7339 func (stream, ", lsl #%u", sh);
7340 func (stream, "]");
7341 break;
7342 }
7343 else switch (op)
7344 {
05413229 7345 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 7346 offset = i8;
7347 break;
7348
05413229 7349 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 7350 offset = -i8;
7351 break;
7352
05413229 7353 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 7354 offset = i8;
7355 writeback = TRUE;
7356 break;
7357
05413229 7358 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 7359 offset = -i8;
7360 writeback = TRUE;
7361 break;
7362
05413229 7363 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 7364 offset = i8;
7365 postind = TRUE;
7366 break;
7367
05413229 7368 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 7369 offset = -i8;
7370 postind = TRUE;
7371 break;
7372
7373 default:
7374 func (stream, ", <undefined>]");
7375 goto skip;
7376 }
7377
7378 if (postind)
d908c8af 7379 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 7380 else
7381 {
7382 if (offset)
d908c8af 7383 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 7384 func (stream, writeback ? "]!" : "]");
7385 }
7386
7387 if (Rn == 15)
7388 {
7389 func (stream, "\t; ");
7390 info->print_address_func (((pc + 4) & ~3) + offset, info);
7391 }
7392 }
7393 skip:
7394 break;
7395
7396 case 'A':
7397 {
c1e26897
NC		 7398 unsigned int U = ! NEGATIVE_BIT_SET;
7399 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 7400 unsigned int Rn = (given & 0x000f0000) >> 16;
7401 unsigned int off = (given & 0x000000ff);
7402
7403 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 7404
7405 if (PRE_BIT_SET)
c19d1205
ZW		 7406 {
7407 if (off || !U)
05413229
NC		 7408 {
7409 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 7410 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 7411 }
c19d1205
ZW		 7412 func (stream, "]");
7413 if (W)
7414 func (stream, "!");
7415 }
7416 else
7417 {
7418 func (stream, "], ");
7419 if (W)
05413229
NC		 7420 {
7421 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 7422 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 7423 }
c19d1205 7424 else
fe56b6ce
NC		 7425 {
7426 func (stream, "{%u}", off);
7427 value_in_comment = off;
7428 }
c19d1205
ZW		 7429 }
7430 }
7431 break;
7432
7433 case 'w':
7434 {
7435 unsigned int Sbit = (given & 0x01000000) >> 24;
7436 unsigned int type = (given & 0x00600000) >> 21;
05413229 7437
c19d1205
ZW		 7438 switch (type)
7439 {
7440 case 0: func (stream, Sbit ? "sb" : "b"); break;
7441 case 1: func (stream, Sbit ? "sh" : "h"); break;
7442 case 2:
7443 if (Sbit)
7444 func (stream, "??");
7445 break;
7446 case 3:
7447 func (stream, "??");
7448 break;
7449 }
7450 }
7451 break;
7452
4b5a202f
AV		 7453 case 'n':
7454 is_clrm = TRUE;
7455 /* Fall through. */
c19d1205
ZW		 7456 case 'm':
7457 {
7458 int started = 0;
7459 int reg;
7460
7461 func (stream, "{");
7462 for (reg = 0; reg < 16; reg++)
7463 if ((given & (1 << reg)) != 0)
7464 {
7465 if (started)
7466 func (stream, ", ");
7467 started = 1;
4b5a202f
AV		 7468 if (is_clrm && reg == 13)
7469 func (stream, "(invalid: %s)", arm_regnames[reg]);
7470 else if (is_clrm && reg == 15)
7471 func (stream, "%s", "APSR");
7472 else
7473 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 7474 }
7475 func (stream, "}");
7476 }
7477 break;
7478
7479 case 'E':
7480 {
7481 unsigned int msb = (given & 0x0000001f);
7482 unsigned int lsb = 0;
fe56b6ce 7483
c19d1205
ZW		 7484 lsb |= (given & 0x000000c0u) >> 6;
7485 lsb |= (given & 0x00007000u) >> 10;
7486 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
7487 }
7488 break;
7489
7490 case 'F':
7491 {
7492 unsigned int width = (given & 0x0000001f) + 1;
7493 unsigned int lsb = 0;
fe56b6ce 7494
c19d1205
ZW		 7495 lsb |= (given & 0x000000c0u) >> 6;
7496 lsb |= (given & 0x00007000u) >> 10;
7497 func (stream, "#%u, #%u", lsb, width);
7498 }
7499 break;
7500
e12437dc
AV		 7501 case 'G':
7502 {
7503 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
7504 func (stream, "%x", boff);
7505 }
7506 break;
7507
e5d6e09e
AV		 7508 case 'W':
7509 {
7510 unsigned int immA = (given & 0x001f0000u) >> 16;
7511 unsigned int immB = (given & 0x000007feu) >> 1;
7512 unsigned int immC = (given & 0x00000800u) >> 11;
7513 bfd_vma offset = 0;
7514
7515 offset |= immA << 12;
7516 offset |= immB << 2;
7517 offset |= immC << 1;
7518 /* Sign extend. */
7519 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
7520
7521 info->print_address_func (pc + 4 + offset, info);
7522 }
7523 break;
7524
1caf72a5
AV		 7525 case 'Y':
7526 {
7527 unsigned int immA = (given & 0x007f0000u) >> 16;
7528 unsigned int immB = (given & 0x000007feu) >> 1;
7529 unsigned int immC = (given & 0x00000800u) >> 11;
7530 bfd_vma offset = 0;
7531
7532 offset |= immA << 12;
7533 offset |= immB << 2;
7534 offset |= immC << 1;
7535 /* Sign extend. */
7536 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
7537
7538 info->print_address_func (pc + 4 + offset, info);
7539 }
7540 break;
7541
1889da70
AV		 7542 case 'Z':
7543 {
7544 unsigned int immA = (given & 0x00010000u) >> 16;
7545 unsigned int immB = (given & 0x000007feu) >> 1;
7546 unsigned int immC = (given & 0x00000800u) >> 11;
7547 bfd_vma offset = 0;
7548
7549 offset |= immA << 12;
7550 offset |= immB << 2;
7551 offset |= immC << 1;
7552 /* Sign extend. */
7553 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
7554
7555 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 7556
7557 unsigned int T = (given & 0x00020000u) >> 17;
7558 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
7559 unsigned int boffset = (T == 1) ? 4 : 2;
7560 func (stream, ", ");
7561 func (stream, "%x", endoffset + boffset);
1889da70
AV		 7562 }
7563 break;
7564
60f993ce
AV		 7565 case 'Q':
7566 {
7567 unsigned int immh = (given & 0x000007feu) >> 1;
7568 unsigned int imml = (given & 0x00000800u) >> 11;
7569 bfd_vma imm32 = 0;
7570
7571 imm32 |= immh << 2;
7572 imm32 |= imml << 1;
7573
7574 info->print_address_func (pc + 4 + imm32, info);
7575 }
7576 break;
7577
7578 case 'P':
7579 {
7580 unsigned int immh = (given & 0x000007feu) >> 1;
7581 unsigned int imml = (given & 0x00000800u) >> 11;
7582 bfd_vma imm32 = 0;
7583
7584 imm32 |= immh << 2;
7585 imm32 |= imml << 1;
7586
7587 info->print_address_func (pc + 4 - imm32, info);
7588 }
7589 break;
7590
c19d1205
ZW		 7591 case 'b':
7592 {
7593 unsigned int S = (given & 0x04000000u) >> 26;
7594 unsigned int J1 = (given & 0x00002000u) >> 13;
7595 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 7596 bfd_vma offset = 0;
c19d1205
ZW		 7597
7598 offset |= !S << 20;
7599 offset |= J2 << 19;
7600 offset |= J1 << 18;
7601 offset |= (given & 0x003f0000) >> 4;
7602 offset |= (given & 0x000007ff) << 1;
7603 offset -= (1 << 20);
7604
7605 info->print_address_func (pc + 4 + offset, info);
7606 }
7607 break;
7608
7609 case 'B':
7610 {
7611 unsigned int S = (given & 0x04000000u) >> 26;
7612 unsigned int I1 = (given & 0x00002000u) >> 13;
7613 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 7614 bfd_vma offset = 0;
c19d1205
ZW		 7615
7616 offset |= !S << 24;
7617 offset |= !(I1 ^ S) << 23;
7618 offset |= !(I2 ^ S) << 22;
7619 offset |= (given & 0x03ff0000u) >> 4;
7620 offset |= (given & 0x000007ffu) << 1;
7621 offset -= (1 << 24);
36b0c57d 7622 offset += pc + 4;
c19d1205 7623
36b0c57d
PB		 7624 /* BLX target addresses are always word aligned. */
7625 if ((given & 0x00001000u) == 0)
7626 offset &= ~2u;
7627
7628 info->print_address_func (offset, info);
c19d1205
ZW		 7629 }
7630 break;
7631
7632 case 's':
7633 {
7634 unsigned int shift = 0;
fe56b6ce 7635
c19d1205
ZW		 7636 shift |= (given & 0x000000c0u) >> 6;
7637 shift |= (given & 0x00007000u) >> 10;
c1e26897 7638 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 7639 func (stream, ", asr #%u", shift);
7640 else if (shift)
7641 func (stream, ", lsl #%u", shift);
7642 /* else print nothing - lsl #0 */
7643 }
7644 break;
7645
7646 case 'R':
7647 {
7648 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 7649
c19d1205
ZW		 7650 if (rot)
7651 func (stream, ", ror #%u", rot * 8);
7652 }
7653 break;
7654
62b3e311 7655 case 'U':
43e65147 7656 if ((given & 0xf0) == 0x60)
62b3e311 7657 {
52e7f43d
RE		 7658 switch (given & 0xf)
7659 {
7660 case 0xf: func (stream, "sy"); break;
7661 default:
7662 func (stream, "#%d", (int) given & 0xf);
7663 break;
7664 }
62b3e311 7665 }
43e65147 7666 else
52e7f43d 7667 {
e797f7e0
MGD		 7668 const char * opt = data_barrier_option (given & 0xf);
7669 if (opt != NULL)
7670 func (stream, "%s", opt);
7671 else
7672 func (stream, "#%d", (int) given & 0xf);
52e7f43d 7673 }
62b3e311
PB		 7674 break;
7675
7676 case 'C':
7677 if ((given & 0xff) == 0)
7678 {
7679 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
7680 if (given & 0x800)
7681 func (stream, "f");
7682 if (given & 0x400)
7683 func (stream, "s");
7684 if (given & 0x200)
7685 func (stream, "x");
7686 if (given & 0x100)
7687 func (stream, "c");
7688 }
90ec0d68
MGD		 7689 else if ((given & 0x20) == 0x20)
7690 {
7691 char const* name;
7692 unsigned sysm = (given & 0xf00) >> 8;
7693
7694 sysm |= (given & 0x30);
7695 sysm |= (given & 0x00100000) >> 14;
7696 name = banked_regname (sysm);
43e65147 7697
90ec0d68
MGD		 7698 if (name != NULL)
7699 func (stream, "%s", name);
7700 else
d908c8af 7701 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 7702 }
62b3e311
PB		 7703 else
7704 {
d908c8af 7705 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 7706 }
7707 break;
7708
7709 case 'D':
90ec0d68
MGD		 7710 if (((given & 0xff) == 0)
7711 || ((given & 0x20) == 0x20))
7712 {
7713 char const* name;
7714 unsigned sm = (given & 0xf0000) >> 16;
7715
7716 sm |= (given & 0x30);
7717 sm |= (given & 0x00100000) >> 14;
7718 name = banked_regname (sm);
7719
7720 if (name != NULL)
7721 func (stream, "%s", name);
7722 else
d908c8af 7723 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 7724 }
62b3e311 7725 else
d908c8af 7726 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 7727 break;
7728
c19d1205
ZW		 7729 case '0': case '1': case '2': case '3': case '4':
7730 case '5': case '6': case '7': case '8': case '9':
7731 {
16980d0b
JB		 7732 int width;
7733 unsigned long val;
c19d1205 7734
16980d0b 7735 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 7736
c19d1205
ZW		 7737 switch (*c)
7738 {
05413229
NC		 7739 case 'd':
7740 func (stream, "%lu", val);
7741 value_in_comment = val;
7742 break;
ff4a8d2b 7743
f0fba320
RL		 7744 case 'D':
7745 func (stream, "%lu", val + 1);
7746 value_in_comment = val + 1;
7747 break;
7748
05413229
NC		 7749 case 'W':
7750 func (stream, "%lu", val * 4);
7751 value_in_comment = val * 4;
7752 break;
ff4a8d2b 7753
f1c7f421
AV		 7754 case 'S':
7755 if (val == 13)
7756 is_unpredictable = TRUE;
7757 /* Fall through. */
ff4a8d2b
NC		 7758 case 'R':
7759 if (val == 15)
7760 is_unpredictable = TRUE;
7761 /* Fall through. */
7762 case 'r':
7763 func (stream, "%s", arm_regnames[val]);
7764 break;
c19d1205
ZW		 7765
7766 case 'c':
c22aaad1 7767 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 7768 break;
7769
7770 case '\'':
c19d1205 7771 c++;
16980d0b
JB		 7772 if (val == ((1ul << width) - 1))
7773 func (stream, "%c", *c);
c19d1205 7774 break;
43e65147 7775
c19d1205 7776 case '`':
c19d1205 7777 c++;
16980d0b
JB		 7778 if (val == 0)
7779 func (stream, "%c", *c);
c19d1205
ZW		 7780 break;
7781
7782 case '?':
fe56b6ce 7783 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 7784 c += 1 << width;
c19d1205 7785 break;
43e65147 7786
0bb027fd
RR		 7787 case 'x':
7788 func (stream, "0x%lx", val & 0xffffffffUL);
7789 break;
c19d1205
ZW		 7790
7791 default:
7792 abort ();
7793 }
7794 }
7795 break;
7796
32a94698
NC		 7797 case 'L':
7798 /* PR binutils/12534
7799 If we have a PC relative offset in an LDRD or STRD
7800 instructions then display the decoded address. */
7801 if (((given >> 16) & 0xf) == 0xf)
7802 {
7803 bfd_vma offset = (given & 0xff) * 4;
7804
7805 if ((given & (1 << 23)) == 0)
7806 offset = - offset;
7807 func (stream, "\t; ");
7808 info->print_address_func ((pc & ~3) + 4 + offset, info);
7809 }
7810 break;
7811
c19d1205
ZW		 7812 default:
7813 abort ();
7814 }
7815 }
05413229
NC		 7816
7817 if (value_in_comment > 32 || value_in_comment < -16)
7818 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 7819
7820 if (is_unpredictable)
7821 func (stream, UNPREDICTABLE_INSTRUCTION);
7822
4a5329c6 7823 return;
c19d1205 7824 }
252b5132 7825
58efb6c0 7826 /* No match. */
0b347048
TC		 7827 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
7828 return;
252b5132
RH		 7829}
7830
e821645d
DJ		 7831/* Print data bytes on INFO->STREAM. */
7832
7833static void
fe56b6ce
NC		 7834print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
7835 struct disassemble_info *info,
e821645d
DJ		 7836 long given)
7837{
7838 switch (info->bytes_per_chunk)
7839 {
7840 case 1:
7841 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
7842 break;
7843 case 2:
7844 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
7845 break;
7846 case 4:
7847 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
7848 break;
7849 default:
7850 abort ();
7851 }
7852}
7853
22a398e1 7854/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 7855 being displayed in symbol relative addresses.
7856
7857 Also disallow private symbol, with __tagsym$$ prefix,
7858 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 7859
7860bfd_boolean
7861arm_symbol_is_valid (asymbol * sym,
7862 struct disassemble_info * info ATTRIBUTE_UNUSED)
7863{
7864 const char * name;
43e65147 7865
22a398e1
NC		 7866 if (sym == NULL)
7867 return FALSE;
7868
7869 name = bfd_asymbol_name (sym);
7870
d8282f0e 7871 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 7872}
7873
65b48a81 7874/* Parse the string of disassembler options. */
baf0cc5e 7875
65b48a81 7876static void
f995bbe8 7877parse_arm_disassembler_options (const char *options)
dd92f639 7878{
f995bbe8 7879 const char *opt;
b34976b6 7880
65b48a81 7881 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 7882 {
65b48a81
PB		 7883 if (CONST_STRNEQ (opt, "reg-names-"))
7884 {
7885 unsigned int i;
7886 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7887 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
7888 {
7889 regname_selected = i;
7890 break;
7891 }
b34976b6 7892
65b48a81 7893 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 7894 /* xgettext: c-format */
7895 opcodes_error_handler (_("unrecognised register name set: %s"),
7896 opt);
65b48a81
PB		 7897 }
7898 else if (CONST_STRNEQ (opt, "force-thumb"))
7899 force_thumb = 1;
7900 else if (CONST_STRNEQ (opt, "no-force-thumb"))
7901 force_thumb = 0;
7902 else
a6743a54
AM		 7903 /* xgettext: c-format */
7904 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 7905 }
b34976b6 7906
dd92f639
NC		 7907 return;
7908}
7909
5bc5ae88
RL		 7910static bfd_boolean
7911mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
7912 enum map_type *map_symbol);
7913
c22aaad1
PB		 7914/* Search back through the insn stream to determine if this instruction is
7915 conditionally executed. */
fe56b6ce 7916
c22aaad1 7917static void
fe56b6ce
NC		 7918find_ifthen_state (bfd_vma pc,
7919 struct disassemble_info *info,
c22aaad1
PB		 7920 bfd_boolean little)
7921{
7922 unsigned char b[2];
7923 unsigned int insn;
7924 int status;
7925 /* COUNT is twice the number of instructions seen. It will be odd if we
7926 just crossed an instruction boundary. */
7927 int count;
7928 int it_count;
7929 unsigned int seen_it;
7930 bfd_vma addr;
7931
7932 ifthen_address = pc;
7933 ifthen_state = 0;
7934
7935 addr = pc;
7936 count = 1;
7937 it_count = 0;
7938 seen_it = 0;
7939 /* Scan backwards looking for IT instructions, keeping track of where
7940 instruction boundaries are. We don't know if something is actually an
7941 IT instruction until we find a definite instruction boundary. */
7942 for (;;)
7943 {
fe56b6ce 7944 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 7945 {
7946 /* A symbol must be on an instruction boundary, and will not
7947 be within an IT block. */
7948 if (seen_it && (count & 1))
7949 break;
7950
7951 return;
7952 }
7953 addr -= 2;
fe56b6ce 7954 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 7955 if (status)
7956 return;
7957
7958 if (little)
7959 insn = (b[0]) | (b[1] << 8);
7960 else
7961 insn = (b[1]) | (b[0] << 8);
7962 if (seen_it)
7963 {
7964 if ((insn & 0xf800) < 0xe800)
7965 {
7966 /* Addr + 2 is an instruction boundary. See if this matches
7967 the expected boundary based on the position of the last
7968 IT candidate. */
7969 if (count & 1)
7970 break;
7971 seen_it = 0;
7972 }
7973 }
7974 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
7975 {
5bc5ae88
RL		 7976 enum map_type type = MAP_ARM;
7977 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
7978
7979 if (!found || (found && type == MAP_THUMB))
7980 {
7981 /* This could be an IT instruction. */
7982 seen_it = insn;
7983 it_count = count >> 1;
7984 }
c22aaad1
PB		 7985 }
7986 if ((insn & 0xf800) >= 0xe800)
7987 count++;
7988 else
7989 count = (count + 2) | 1;
7990 /* IT blocks contain at most 4 instructions. */
7991 if (count >= 8 && !seen_it)
7992 return;
7993 }
7994 /* We found an IT instruction. */
7995 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
7996 if ((ifthen_state & 0xf) == 0)
7997 ifthen_state = 0;
7998}
7999
b0e28b39
DJ		 8000/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
8001 mapping symbol. */
8002
8003static int
8004is_mapping_symbol (struct disassemble_info *info, int n,
8005 enum map_type *map_type)
8006{
8007 const char *name;
8008
8009 name = bfd_asymbol_name (info->symtab[n]);
8010 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
8011 && (name[2] == 0 || name[2] == '.'))
8012 {
8013 *map_type = ((name[1] == 'a') ? MAP_ARM
8014 : (name[1] == 't') ? MAP_THUMB
8015 : MAP_DATA);
8016 return TRUE;
8017 }
8018
8019 return FALSE;
8020}
8021
8022/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
8023 Returns nonzero if *MAP_TYPE was set. */
8024
8025static int
8026get_map_sym_type (struct disassemble_info *info,
8027 int n,
8028 enum map_type *map_type)
8029{
8030 /* If the symbol is in a different section, ignore it. */
8031 if (info->section != NULL && info->section != info->symtab[n]->section)
8032 return FALSE;
8033
8034 return is_mapping_symbol (info, n, map_type);
8035}
8036
8037/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 8038 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 8039
8040static int
fe56b6ce
NC		 8041get_sym_code_type (struct disassemble_info *info,
8042 int n,
e821645d 8043 enum map_type *map_type)
2087ad84
PB		 8044{
8045 elf_symbol_type *es;
8046 unsigned int type;
b0e28b39
DJ		 8047
8048 /* If the symbol is in a different section, ignore it. */
8049 if (info->section != NULL && info->section != info->symtab[n]->section)
8050 return FALSE;
2087ad84 8051
e821645d 8052 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 8053 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
8054
8055 /* If the symbol has function type then use that. */
34e77a92 8056 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 8057 {
39d911fc
TP		 8058 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
8059 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 8060 *map_type = MAP_THUMB;
8061 else
8062 *map_type = MAP_ARM;
2087ad84
PB		 8063 return TRUE;
8064 }
8065
2087ad84
PB		 8066 return FALSE;
8067}
8068
5bc5ae88
RL		 8069/* Search the mapping symbol state for instruction at pc. This is only
8070 applicable for elf target.
8071
8072 There is an assumption Here, info->private_data contains the correct AND
8073 up-to-date information about current scan process. The information will be
8074 used to speed this search process.
8075
8076 Return TRUE if the mapping state can be determined, and map_symbol
8077 will be updated accordingly. Otherwise, return FALSE. */
8078
8079static bfd_boolean
8080mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
8081 enum map_type *map_symbol)
8082{
796d6298
TC		 8083 bfd_vma addr, section_vma = 0;
8084 int n, last_sym = -1;
5bc5ae88 8085 bfd_boolean found = FALSE;
796d6298
TC		 8086 bfd_boolean can_use_search_opt_p = FALSE;
8087
8088 /* Default to DATA. A text section is required by the ABI to contain an
8089 INSN mapping symbol at the start. A data section has no such
8090 requirement, hence if no mapping symbol is found the section must
8091 contain only data. This however isn't very useful if the user has
8092 fully stripped the binaries. If this is the case use the section
8093 attributes to determine the default. If we have no section default to
8094 INSN as well, as we may be disassembling some raw bytes on a baremetal
8095 HEX file or similar. */
8096 enum map_type type = MAP_DATA;
8097 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
8098 type = MAP_ARM;
5bc5ae88
RL		 8099 struct arm_private_data *private_data;
8100
796d6298 8101 if (info->private_data == NULL
5bc5ae88
RL		 8102 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
8103 return FALSE;
8104
8105 private_data = info->private_data;
5bc5ae88 8106
796d6298
TC		 8107 /* First, look for mapping symbols. */
8108 if (info->symtab_size != 0)
8109 {
8110 if (pc <= private_data->last_mapping_addr)
8111 private_data->last_mapping_sym = -1;
8112
8113 /* Start scanning at the start of the function, or wherever
8114 we finished last time. */
8115 n = info->symtab_pos + 1;
8116
8117 /* If the last stop offset is different from the current one it means we
8118 are disassembling a different glob of bytes. As such the optimization
8119 would not be safe and we should start over. */
8120 can_use_search_opt_p
8121 = private_data->last_mapping_sym >= 0
8122 && info->stop_offset == private_data->last_stop_offset;
8123
8124 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
8125 n = private_data->last_mapping_sym;
8126
8127 /* Look down while we haven't passed the location being disassembled.
8128 The reason for this is that there's no defined order between a symbol
8129 and an mapping symbol that may be at the same address. We may have to
8130 look at least one position ahead. */
8131 for (; n < info->symtab_size; n++)
8132 {
8133 addr = bfd_asymbol_value (info->symtab[n]);
8134 if (addr > pc)
8135 break;
8136 if (get_map_sym_type (info, n, &type))
8137 {
8138 last_sym = n;
8139 found = TRUE;
8140 }
8141 }
5bc5ae88 8142
796d6298
TC		 8143 if (!found)
8144 {
8145 n = info->symtab_pos;
8146 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
8147 n = private_data->last_mapping_sym;
8148
8149 /* No mapping symbol found at this address. Look backwards
8150 for a preceeding one, but don't go pass the section start
8151 otherwise a data section with no mapping symbol can pick up
8152 a text mapping symbol of a preceeding section. The documentation
8153 says section can be NULL, in which case we will seek up all the
8154 way to the top. */
8155 if (info->section)
8156 section_vma = info->section->vma;
8157
8158 for (; n >= 0; n--)
8159 {
8160 addr = bfd_asymbol_value (info->symtab[n]);
8161 if (addr < section_vma)
8162 break;
8163
8164 if (get_map_sym_type (info, n, &type))
8165 {
8166 last_sym = n;
8167 found = TRUE;
8168 break;
8169 }
8170 }
8171 }
8172 }
8173
8174 /* If no mapping symbol was found, try looking up without a mapping
8175 symbol. This is done by walking up from the current PC to the nearest
8176 symbol. We don't actually have to loop here since symtab_pos will
8177 contain the nearest symbol already. */
8178 if (!found)
5bc5ae88 8179 {
796d6298
TC		 8180 n = info->symtab_pos;
8181 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 8182 {
796d6298
TC		 8183 last_sym = n;
8184 found = TRUE;
5bc5ae88
RL		 8185 }
8186 }
8187
796d6298
TC		 8188 private_data->last_mapping_sym = last_sym;
8189 private_data->last_type = type;
8190 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 8191
8192 *map_symbol = type;
8193 return found;
8194}
8195
0313a2b8
NC		 8196/* Given a bfd_mach_arm_XXX value, this function fills in the fields
8197 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 8198 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 8199
8200 FIXME: This could more efficiently implemented as a constant array,
8201 although it would also be less robust. */
8202
8203static void
8204select_arm_features (unsigned long mach,
8205 arm_feature_set * features)
8206{
c0c468d5
TP		 8207 arm_feature_set arch_fset;
8208 const arm_feature_set fpu_any = FPU_ANY;
8209
1af1dd51
MW		 8210#undef ARM_SET_FEATURES
8211#define ARM_SET_FEATURES(FSET) \
8212 { \
8213 const arm_feature_set fset = FSET; \
c0c468d5 8214 arch_fset = fset; \
1af1dd51 8215 }
823d2571 8216
c0c468d5
TP		 8217 /* When several architecture versions share the same bfd_mach_arm_XXX value
8218 the most featureful is chosen. */
0313a2b8
NC		 8219 switch (mach)
8220 {
c0c468d5
TP		 8221 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
8222 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
8223 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
8224 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
8225 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
8226 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
8227 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
8228 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
8229 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
8230 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 8231 case bfd_mach_arm_ep9312:
c0c468d5
TP		 8232 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
8233 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 8234 break;
c0c468d5
TP		 8235 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
8236 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
8237 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
8238 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
8239 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
8240 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
8241 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
8242 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
8243 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
8244 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
8245 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
8246 case bfd_mach_arm_8:
8247 {
0632eeea
SD		 8248 /* Add bits for extensions that Armv8.5-A recognizes. */
8249 arm_feature_set armv8_5_ext_fset
8250 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
8251 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
8252 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 8253 break;
8254 }
8255 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
8256 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
8257 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 8258 case bfd_mach_arm_8_1M_MAIN:
8259 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
8260 force_thumb = 1;
8261 break;
c0c468d5
TP		 8262 /* If the machine type is unknown allow all architecture types and all
8263 extensions. */
8264 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 8265 default:
8266 abort ();
8267 }
1af1dd51 8268#undef ARM_SET_FEATURES
c0c468d5
TP		 8269
8270 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
8271 and thus on bfd_mach_arm_XXX value. Therefore for a given
8272 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
8273 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 8274}
8275
8276
58efb6c0
NC		 8277/* NOTE: There are no checks in these routines that
8278 the relevant number of data bytes exist. */
baf0cc5e 8279
58efb6c0 8280static int
4a5329c6 8281print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 8282{
c19d1205
ZW		 8283 unsigned char b[4];
8284 long given;
8285 int status;
e821645d 8286 int is_thumb = FALSE;
b0e28b39 8287 int is_data = FALSE;
bd2e2557 8288 int little_code;
e821645d 8289 unsigned int size = 4;
4a5329c6 8290 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 8291 bfd_boolean found = FALSE;
b0e28b39 8292 struct arm_private_data *private_data;
58efb6c0 8293
dd92f639
NC		 8294 if (info->disassembler_options)
8295 {
65b48a81 8296 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 8297
58efb6c0 8298 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 8299 info->disassembler_options = NULL;
8300 }
b34976b6 8301
0313a2b8
NC		 8302 /* PR 10288: Control which instructions will be disassembled. */
8303 if (info->private_data == NULL)
8304 {
b0e28b39 8305 static struct arm_private_data private;
0313a2b8
NC		 8306
8307 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
8308 /* If the user did not use the -m command line switch then default to
8309 disassembling all types of ARM instruction.
43e65147 8310
0313a2b8
NC		 8311 The info->mach value has to be ignored as this will be based on
8312 the default archictecture for the target and/or hints in the notes
8313 section, but it will never be greater than the current largest arm
8314 machine value (iWMMXt2), which is only equivalent to the V5TE
8315 architecture. ARM architectures have advanced beyond the machine
8316 value encoding, and these newer architectures would be ignored if
8317 the machine value was used.
8318
8319 Ie the -m switch is used to restrict which instructions will be
8320 disassembled. If it is necessary to use the -m switch to tell
8321 objdump that an ARM binary is being disassembled, eg because the
8322 input is a raw binary file, but it is also desired to disassemble
8323 all ARM instructions then use "-marm". This will select the
8324 "unknown" arm architecture which is compatible with any ARM
8325 instruction. */
8326 info->mach = bfd_mach_arm_unknown;
8327
8328 /* Compute the architecture bitmask from the machine number.
8329 Note: This assumes that the machine number will not change
8330 during disassembly.... */
b0e28b39 8331 select_arm_features (info->mach, & private.features);
0313a2b8 8332
1fbaefec
PB		 8333 private.last_mapping_sym = -1;
8334 private.last_mapping_addr = 0;
796d6298 8335 private.last_stop_offset = 0;
b0e28b39
DJ		 8336
8337 info->private_data = & private;
0313a2b8 8338 }
b0e28b39
DJ		 8339
8340 private_data = info->private_data;
8341
bd2e2557
SS		 8342 /* Decide if our code is going to be little-endian, despite what the
8343 function argument might say. */
8344 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
8345
b0e28b39
DJ		 8346 /* For ELF, consult the symbol table to determine what kind of code
8347 or data we have. */
8977d4b2 8348 if (info->symtab_size != 0
e821645d
DJ		 8349 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
8350 {
8351 bfd_vma addr;
796d6298 8352 int n;
e821645d 8353 int last_sym = -1;
b0e28b39 8354 enum map_type type = MAP_ARM;
e821645d 8355
796d6298
TC		 8356 found = mapping_symbol_for_insn (pc, info, &type);
8357 last_sym = private_data->last_mapping_sym;
e821645d 8358
1fbaefec
PB		 8359 is_thumb = (private_data->last_type == MAP_THUMB);
8360 is_data = (private_data->last_type == MAP_DATA);
b34976b6 8361
e821645d
DJ		 8362 /* Look a little bit ahead to see if we should print out
8363 two or four bytes of data. If there's a symbol,
8364 mapping or otherwise, after two bytes then don't
8365 print more. */
8366 if (is_data)
8367 {
8368 size = 4 - (pc & 3);
8369 for (n = last_sym + 1; n < info->symtab_size; n++)
8370 {
8371 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 8372 if (addr > pc
8373 && (info->section == NULL
8374 || info->section == info->symtab[n]->section))
e821645d
DJ		 8375 {
8376 if (addr - pc < size)
8377 size = addr - pc;
8378 break;
8379 }
8380 }
8381 /* If the next symbol is after three bytes, we need to
8382 print only part of the data, so that we can use either
8383 .byte or .short. */
8384 if (size == 3)
8385 size = (pc & 1) ? 1 : 2;
8386 }
8387 }
8388
8389 if (info->symbols != NULL)
252b5132 8390 {
5876e06d
NC		 8391 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
8392 {
2f0ca46a 8393 coff_symbol_type * cs;
b34976b6 8394
5876e06d
NC		 8395 cs = coffsymbol (*info->symbols);
8396 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
8397 || cs->native->u.syment.n_sclass == C_THUMBSTAT
8398 || cs->native->u.syment.n_sclass == C_THUMBLABEL
8399 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
8400 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
8401 }
e821645d
DJ		 8402 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
8403 && !found)
5876e06d 8404 {
2087ad84
PB		 8405 /* If no mapping symbol has been found then fall back to the type
8406 of the function symbol. */
e821645d
DJ		 8407 elf_symbol_type * es;
8408 unsigned int type;
2087ad84 8409
e821645d
DJ		 8410 es = *(elf_symbol_type **)(info->symbols);
8411 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 8412
39d911fc
TP		 8413 is_thumb =
8414 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
8415 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 8416 }
e49d43ff
TG		 8417 else if (bfd_asymbol_flavour (*info->symbols)
8418 == bfd_target_mach_o_flavour)
8419 {
8420 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
8421
8422 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
8423 }
5876e06d 8424 }
b34976b6 8425
e821645d
DJ		 8426 if (force_thumb)
8427 is_thumb = TRUE;
8428
b8f9ee44
CL		 8429 if (is_data)
8430 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
8431 else
8432 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
8433
c19d1205 8434 info->bytes_per_line = 4;
252b5132 8435
1316c8b3
NC		 8436 /* PR 10263: Disassemble data if requested to do so by the user. */
8437 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 8438 {
8439 int i;
8440
1316c8b3 8441 /* Size was already set above. */
e821645d
DJ		 8442 info->bytes_per_chunk = size;
8443 printer = print_insn_data;
8444
fe56b6ce 8445 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 8446 given = 0;
8447 if (little)
8448 for (i = size - 1; i >= 0; i--)
8449 given = b[i] | (given << 8);
8450 else
8451 for (i = 0; i < (int) size; i++)
8452 given = b[i] | (given << 8);
8453 }
8454 else if (!is_thumb)
252b5132 8455 {
c19d1205
ZW		 8456 /* In ARM mode endianness is a straightforward issue: the instruction
8457 is four bytes long and is either ordered 0123 or 3210. */
8458 printer = print_insn_arm;
8459 info->bytes_per_chunk = 4;
4a5329c6 8460 size = 4;
c19d1205 8461
0313a2b8 8462 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 8463 if (little_code)
c19d1205
ZW		 8464 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
8465 else
8466 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 8467 }
58efb6c0 8468 else
252b5132 8469 {
c19d1205
ZW		 8470 /* In Thumb mode we have the additional wrinkle of two
8471 instruction lengths. Fortunately, the bits that determine
8472 the length of the current instruction are always to be found
8473 in the first two bytes. */
4a5329c6 8474 printer = print_insn_thumb16;
c19d1205 8475 info->bytes_per_chunk = 2;
4a5329c6
ZW		 8476 size = 2;
8477
fe56b6ce 8478 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 8479 if (little_code)
9a2ff3f5
AM		 8480 given = (b[0]) | (b[1] << 8);
8481 else
8482 given = (b[1]) | (b[0] << 8);
8483
c19d1205 8484 if (!status)
252b5132 8485 {
c19d1205
ZW		 8486 /* These bit patterns signal a four-byte Thumb
8487 instruction. */
8488 if ((given & 0xF800) == 0xF800
8489 || (given & 0xF800) == 0xF000
8490 || (given & 0xF800) == 0xE800)
252b5132 8491 {
0313a2b8 8492 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 8493 if (little_code)
c19d1205 8494 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 8495 else
c19d1205
ZW		 8496 given = (b[1]) | (b[0] << 8) | (given << 16);
8497
8498 printer = print_insn_thumb32;
4a5329c6 8499 size = 4;
252b5132 8500 }
252b5132 8501 }
c22aaad1
PB		 8502
8503 if (ifthen_address != pc)
0313a2b8 8504 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 8505
8506 if (ifthen_state)
8507 {
8508 if ((ifthen_state & 0xf) == 0x8)
8509 ifthen_next_state = 0;
8510 else
8511 ifthen_next_state = (ifthen_state & 0xe0)
8512 | ((ifthen_state & 0xf) << 1);
8513 }
252b5132 8514 }
b34976b6 8515
c19d1205
ZW		 8516 if (status)
8517 {
8518 info->memory_error_func (status, pc, info);
8519 return -1;
8520 }
6a56ec7e
NC		 8521 if (info->flags & INSN_HAS_RELOC)
8522 /* If the instruction has a reloc associated with it, then
8523 the offset field in the instruction will actually be the
8524 addend for the reloc. (We are using REL type relocs).
8525 In such cases, we can ignore the pc when computing
8526 addresses, since the addend is not currently pc-relative. */
8527 pc = 0;
b34976b6 8528
4a5329c6 8529 printer (pc, info, given);
c22aaad1
PB		 8530
8531 if (is_thumb)
8532 {
8533 ifthen_state = ifthen_next_state;
8534 ifthen_address += size;
8535 }
4a5329c6 8536 return size;
252b5132
RH		 8537}
8538
8539int
4a5329c6 8540print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 8541{
bd2e2557
SS		 8542 /* Detect BE8-ness and record it in the disassembler info. */
8543 if (info->flavour == bfd_target_elf_flavour
8544 && info->section != NULL
8545 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
8546 info->endian_code = BFD_ENDIAN_LITTLE;
8547
b34976b6 8548 return print_insn (pc, info, FALSE);
58efb6c0 8549}
01c7f630 8550
58efb6c0 8551int
4a5329c6 8552print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 8553{
b34976b6 8554 return print_insn (pc, info, TRUE);
58efb6c0 8555}
252b5132 8556
471b9d15 8557const disasm_options_and_args_t *
65b48a81
PB		 8558disassembler_options_arm (void)
8559{
471b9d15 8560 static disasm_options_and_args_t *opts_and_args;
65b48a81 8561
471b9d15 8562 if (opts_and_args == NULL)
65b48a81 8563 {
471b9d15 8564 disasm_options_t *opts;
65b48a81 8565 unsigned int i;
471b9d15
MR		 8566
8567 opts_and_args = XNEW (disasm_options_and_args_t);
8568 opts_and_args->args = NULL;
8569
8570 opts = &opts_and_args->options;
65b48a81
PB		 8571 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
8572 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 8573 opts->arg = NULL;
65b48a81
PB		 8574 for (i = 0; i < NUM_ARM_OPTIONS; i++)
8575 {
8576 opts->name[i] = regnames[i].name;
8577 if (regnames[i].description != NULL)
8578 opts->description[i] = _(regnames[i].description);
8579 else
8580 opts->description[i] = NULL;
8581 }
8582 /* The array we return must be NULL terminated. */
8583 opts->name[i] = NULL;
8584 opts->description[i] = NULL;
8585 }
8586
471b9d15 8587 return opts_and_args;
65b48a81
PB		 8588}
8589
58efb6c0 8590void
4a5329c6 8591print_arm_disassembler_options (FILE *stream)
58efb6c0 8592{
65b48a81 8593 unsigned int i, max_len = 0;
58efb6c0
NC		 8594 fprintf (stream, _("\n\
8595The following ARM specific disassembler options are supported for use with\n\
8596the -M switch:\n"));
b34976b6 8597
65b48a81
PB		 8598 for (i = 0; i < NUM_ARM_OPTIONS; i++)
8599 {
8600 unsigned int len = strlen (regnames[i].name);
8601 if (max_len < len)
8602 max_len = len;
8603 }
58efb6c0 8604
65b48a81
PB		 8605 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
8606 fprintf (stream, " %s%*c %s\n",
8607 regnames[i].name,
8608 (int)(max_len - strlen (regnames[i].name)), ' ',
8609 _(regnames[i].description));
252b5132 8610}
GDB Binutils - Deliverables
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