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Reviewed and approved by Daniel Jacobowitz and Thiemo Seufer
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
0dd132b6 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modification by James G. Smith (jsmith@cygnus.co.uk)
6
e16bb312 7 This file is part of libopcodes.
252b5132 8
e16bb312
NC		 9 This program is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2 of the License, or (at your option)
12 any later version.
252b5132 13
e16bb312
NC		 14 This program is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
252b5132 18
e16bb312
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
f4321104 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
37
6b5d3a4d 38/* FIXME: Belongs in global header. */
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
6b5d3a4d
ZW		 47struct opcode32
48{
49 unsigned long arch; /* Architecture defining this insn. */
50 unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
51 const char *assembler; /* How to disassemble this insn. */
52};
53
54struct opcode16
55{
56 unsigned long arch; /* Architecture defining this insn. */
57 unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
58 const char *assembler; /* How to disassemble this insn. */
59};
b7693d02 60
8f06b2d8 61/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 62
2fbad815 63 %% %
4a5329c6 64
c22aaad1
PB		 65 %c print condition code (always bits 28-31 in ARM mode)
66 %u print condition code (unconditional in ARM mode)
4a5329c6 67 %A print address for ldc/stc/ldf/stf instruction
16980d0b
JB		 68 %B print vstm/vldm register list
69 %C print vstr/vldr address operand
4a5329c6 70 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 71 %F print the COUNT field of a LFM/SFM instruction.
72 %P print floating point precision in arithmetic insn
73 %Q print floating point precision in ldf/stf insn
74 %R print floating point rounding mode
75
76 %<bitfield>r print as an ARM register
2fbad815 77 %<bitfield>d print the bitfield in decimal
16980d0b 78 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 79 %<bitfield>x print the bitfield in hex
80 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 81 %<bitfield>f print a floating point constant if >7 else a
82 floating point register
4a5329c6
ZW		 83 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
84 %<bitfield>g print as an iWMMXt 64-bit register
85 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 86 %<bitfield>D print as a NEON D register
87 %<bitfield>Q print as a NEON Q register
4a5329c6 88
16980d0b 89 %y<code> print a single precision VFP reg.
2fbad815 90 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 91 %z<code> print a double precision VFP reg
2fbad815 92 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 93
16980d0b
JB		 94 %<bitfield>'c print specified char iff bitfield is all ones
95 %<bitfield>`c print specified char iff bitfield is all zeroes
96 %<bitfield>?ab... select from array of values in big endian order
97
2fbad815 98 %L print as an iWMMXt N/M width field.
4a5329c6 99 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8
PB		 100 %l like 'A' except use byte offsets for 'B' & 'H'
101 versions. */
2fbad815 102
8f06b2d8 103/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 104
8f06b2d8 105static const struct opcode32 coprocessor_opcodes[] =
2fbad815 106{
2fbad815
RE		 107 /* XScale instructions. */
108 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
109 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
110 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
111 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
112 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
113
114 /* Intel Wireless MMX technology instructions. */
115#define FIRST_IWMMXT_INSN 0x0e130130
116#define IWMMXT_INSN_COUNT 47
117 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
118 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
119 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
120 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
121 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
122 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
123 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
124 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
125 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
126 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
127 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
128 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
129 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
130 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
131 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
132 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
133 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
134 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
135 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
136 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
137 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
138 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
139 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
140 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
141 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
142 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
143 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
144 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
145 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
146 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
147 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
148 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
149 {ARM_CEXT_XSCALE, 0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
150 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
151 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
152 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
153 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
154 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
155 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
156 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
157 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
158 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
159 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
160 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
161 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
162 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
163 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
164 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
165 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
166
8f06b2d8
PB		 167 /* Floating point coprocessor (FPA) instructions */
168 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
169 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
170 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
171 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
172 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
173 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
174 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
175 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
176 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
177 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
178 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
179 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
180 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
181 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
182 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
183 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
184 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
185 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
186 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
187 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
188 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
189 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
190 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
191 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
192 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
193 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
194 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
195 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
196 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
197 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
198 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
199 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
200 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
201 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
202 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
203 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
204 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
205 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
206 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
207 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
208 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
209 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
210 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 211
16980d0b 212 /* Register load/store */
1f3c39b9
JB		 213 {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
214 {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
215 {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
216 {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
16980d0b
JB		 217 {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
218 {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
16980d0b
JB		 219
220 /* Data transfer between ARM and NEON registers */
221 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
222 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
223 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
224 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
225 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
226 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
227 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
228 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
229 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
230 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
231 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
232 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
233 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
234 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
235
2fbad815 236 /* Floating point coprocessor (VFP) instructions */
2fbad815 237 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
2fbad815
RE		 238 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
239 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
240 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
241 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
242 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
16980d0b
JB		 243 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
244 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
245 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
246 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
247 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
248 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
249 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
250 {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
251 {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
2fbad815 252 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"},
16980d0b
JB		 253 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"},
254 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
255 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
256 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
257 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
258 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
259 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
260 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
261 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
262 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
263 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
264 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
265 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
266 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
267 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
268 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
269 {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
270 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
271 {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
272 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
273 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
274 {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
275 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
276 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
277 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
278 {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
279 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
280 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
281 {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%16-19,0-3d"},
282 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%16-19,0-3d"},
283 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %y4"},
284 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
285 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
286 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
287 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
288 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
289 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
290 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
291 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
292 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
293 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
294 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
295 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
296 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
297 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
298 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
299 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
300 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
301 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
302 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
303 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
304 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
305 {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
306 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
307 {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
308 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
309 {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
310 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
311 {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
312 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
313 {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
314 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
315 {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
2fbad815
RE		 316
317 /* Cirrus coprocessor instructions. */
318 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
319 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
320 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
321 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
322 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
323 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
324 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
325 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
326 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
327 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
328 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
329 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
330 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
331 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
332 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
333 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
334 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
335 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
336 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
337 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
338 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
339 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
340 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
341 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
342 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
343 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
344 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
345 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
346 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
347 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
348 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
349 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
350 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
351 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
352 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
353 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
354 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
355 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
356 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
357 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
358 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
359 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
360 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
361 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
362 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
363 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
364 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
365 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
366 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
367 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
368 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
369 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
19590ef7
RE		 370 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
371 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
2fbad815
RE		 372 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
373 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
374 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
375 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
376 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
377 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
378 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
379 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
380 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
381 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
382 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
383 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
384 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
385 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
386 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
387 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
388 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
389 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
390 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
391 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
392 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
393 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
394 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
395 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
396 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
397 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
19590ef7
RE		 398 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
399 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
400 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
401 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815
RE		 402
403 /* Generic coprocessor instructions */
404 {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
405 {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
406 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
407 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
408 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
409 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
410 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
411
8f06b2d8 412 /* V6 coprocessor instructions */
c22aaad1
PB		 413 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
414 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
8f06b2d8
PB		 415
416 /* V5 coprocessor instructions */
c22aaad1
PB		 417 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
418 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
419 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
420 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
421 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
16980d0b 422
b13dd07a 423 {0, 0, 0, 0}
2fbad815
RE		 424};
425
16980d0b
JB		 426/* Neon opcode table: This does not encode the top byte -- that is
427 checked by the print_insn_neon routine, as it depends on whether we are
428 doing thumb32 or arm32 disassembly. */
429
430/* print_insn_neon recognizes the following format control codes:
431
432 %% %
433
c22aaad1 434 %c print condition code
16980d0b
JB		 435 %A print v{st,ld}[1234] operands
436 %B print v{st,ld}[1234] any one operands
437 %C print v{st,ld}[1234] single->all operands
438 %D print scalar
439 %E print vmov, vmvn, vorr, vbic encoded constant
440 %F print vtbl,vtbx register list
441
442 %<bitfield>r print as an ARM register
443 %<bitfield>d print the bitfield in decimal
444 %<bitfield>e print the 2^N - bitfield in decimal
445 %<bitfield>D print as a NEON D register
446 %<bitfield>Q print as a NEON Q register
447 %<bitfield>R print as a NEON D or Q register
448 %<bitfield>Sn print byte scaled width limited by n
449 %<bitfield>Tn print short scaled width limited by n
450 %<bitfield>Un print long scaled width limited by n
451
452 %<bitfield>'c print specified char iff bitfield is all ones
453 %<bitfield>`c print specified char iff bitfield is all zeroes
454 %<bitfield>?ab... select from array of values in big endian order */
455
456static const struct opcode32 neon_opcodes[] =
457{
458 /* Extract */
c22aaad1
PB		 459 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
460 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b
JB		 461
462 /* Move data element to all lanes */
c22aaad1
PB		 463 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
464 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
465 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b
JB		 466
467 /* Table lookup */
c22aaad1
PB		 468 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
469 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
16980d0b
JB		 470
471 /* Two registers, miscellaneous */
c22aaad1
PB		 472 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
473 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
474 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
475 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
476 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
477 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
478 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19S2\t%12-15,22D, %0-3,5Q"},
479 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
480 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
481 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
482 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
483 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
484 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
485 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
486 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
487 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
488 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
489 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
490 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
491 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
492 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
493 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
494 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
495 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
496 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
497 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
498 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
499 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
500 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
501 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
502 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
503 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
504 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b
JB		 505
506 /* Three registers of the same length */
c22aaad1
PB		 507 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
508 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
509 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
510 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
511 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
512 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
513 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
514 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
515 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
516 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
517 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
518 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
519 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
520 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
521 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
522 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
523 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
524 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
525 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
526 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
527 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
528 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
529 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
530 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
531 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
532 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
533 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
534 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
535 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
536 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
537 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
538 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
539 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
540 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
541 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
542 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
543 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
544 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
545 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
546 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
547 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
548 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
549 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
550 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
551 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
552 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
553 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
554 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
555 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
556 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
557 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
558 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
559 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b
JB		 560
561 /* One register and an immediate value */
c22aaad1
PB		 562 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
563 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
564 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
565 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
566 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
567 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
568 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
569 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
570 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
571 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
572 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
573 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
574 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b
JB		 575
576 /* Two registers and a shift amount */
c22aaad1
PB		 577 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
578 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
579 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
580 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
581 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
582 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
583 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
584 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
585 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
586 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
587 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
588 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
589 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
590 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
591 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
592 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
593 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
594 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
595 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
596 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
597 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
598 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
599 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
600 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
601 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
602 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
603 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
604 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
605 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
606 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
607 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
608 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
609 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
610 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
611 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
612 {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
613 {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
614 {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
615 {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
616 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
617 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
618 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
619 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
620 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
621 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
622 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
623 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
624 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
625 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
626 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
627 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
628 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
629 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
630 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
631 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
632 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
633 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
634 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b
JB		 635
636 /* Three registers of different lengths */
c22aaad1
PB		 637 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
638 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
639 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
640 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
641 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
642 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
643 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
644 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
645 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
646 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
647 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
648 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
649 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
650 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
651 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
652 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
653 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b
JB		 654
655 /* Two registers and a scalar */
c22aaad1
PB		 656 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
657 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
658 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
659 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
660 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
661 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
662 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
663 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
664 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
665 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
666 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
667 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
668 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
669 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
670 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
671 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
672 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
673 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
674 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
675 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
676 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
677 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
16980d0b
JB		 678
679 /* Element and structure load/store */
c22aaad1
PB		 680 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
681 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
682 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
683 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
684 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
685 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
686 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
687 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
688 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
689 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
690 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
691 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
692 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
693 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
694 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
695 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
696 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
697 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
698 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
16980d0b
JB		 699
700 {0,0 ,0, 0}
701};
702
8f06b2d8
PB		 703/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
704 ordered: they must be searched linearly from the top to obtain a correct
705 match. */
706
707/* print_insn_arm recognizes the following format control codes:
708
709 %% %
710
711 %a print address for ldr/str instruction
712 %s print address for ldr/str halfword/signextend instruction
713 %b print branch destination
714 %c print condition code (always bits 28-31)
715 %m print register mask for ldm/stm instruction
716 %o print operand2 (immediate or register + shift)
717 %p print 'p' iff bits 12-15 are 15
718 %t print 't' iff bit 21 set and bit 24 clear
719 %B print arm BLX(1) destination
720 %C print the PSR sub type.
62b3e311
PB		 721 %U print barrier type.
722 %P print address for pli instruction.
8f06b2d8
PB		 723
724 %<bitfield>r print as an ARM register
725 %<bitfield>d print the bitfield in decimal
726 %<bitfield>W print the bitfield plus one in decimal
727 %<bitfield>x print the bitfield in hex
728 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
16980d0b
JB		 729
730 %<bitfield>'c print specified char iff bitfield is all ones
731 %<bitfield>`c print specified char iff bitfield is all zeroes
732 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 733
8f06b2d8
PB		 734 %e print arm SMI operand (bits 0..7,8..19).
735 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
736 %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
2fbad815 737
8f06b2d8
PB		 738static const struct opcode32 arm_opcodes[] =
739{
740 /* ARM instructions. */
741 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
742 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
743 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
744 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
745 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
746 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
747 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
c19d1205 748
62b3e311
PB		 749 /* V7 instructions. */
750 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
751 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
752 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
753 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
754 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
755
c19d1205 756 /* ARM V6T2 instructions. */
8f06b2d8
PB		 757 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
758 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
759 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
760 {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
761 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
762 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
763 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
764 {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
765 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 766
8f06b2d8 767 /* ARM V6Z instructions. */
3eb17e6b 768 {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 769
8f06b2d8
PB		 770 /* ARM V6K instructions. */
771 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
772 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
773 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
774 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
775 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
776 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
777 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
c19d1205 778
8f06b2d8
PB		 779 /* ARM V6K NOP hints. */
780 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
781 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
782 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
783 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
784 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 785
8f06b2d8
PB		 786 /* ARM V6 instructions. */
787 {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
788 {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
789 {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
790 {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
791 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
792 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
793 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
794 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
795 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
796 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
797 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
798 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
799 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
800 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
801 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
802 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
803 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
804 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
805 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
806 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
807 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
808 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
809 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
810 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
811 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
812 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
813 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
814 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
815 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
816 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
817 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
818 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
819 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
820 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
821 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
822 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
823 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
824 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
825 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
826 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
827 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
828 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
829 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
830 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
831 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
832 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
833 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
834 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
835 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
836 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
837 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
838 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
839 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
840 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
841 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
842 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
843 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
844 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
845 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
846 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
847 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
848 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
849 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
850 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
851 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
852 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
853 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
854 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
855 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
856 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
857 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
858 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
859 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
860 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
861 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
862 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
863 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
864 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
865 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
866 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
867 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
868 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
869 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
870 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
871 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
872 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
873 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
874 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
875 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
876 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
877 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
878 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
879 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
880 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
881 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
882 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
883 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
884 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
f1022c90 885 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
8f06b2d8
PB		 886 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
887 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
888 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
889 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
890 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
891 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
892 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
893 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
894 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
895 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
896 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
897 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
898 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
899 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
900 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
901 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
902 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
903 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
904 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
905 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
906 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
907 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
908 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
c19d1205 909
8f06b2d8
PB		 910 /* V5J instruction. */
911 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
c19d1205 912
8f06b2d8
PB		 913 /* V5 Instructions. */
914 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
915 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
916 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
917 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
c19d1205 918
8f06b2d8
PB		 919 /* V5E "El Segundo" Instructions. */
920 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
921 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
922 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
923 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
924 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
925 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
926 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
c19d1205 927
8f06b2d8
PB		 928 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
929 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
c19d1205 930
8f06b2d8
PB		 931 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
932 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
933 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
934 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
c19d1205 935
8f06b2d8
PB		 936 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
937 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
938 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
939 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
4a5329c6 940
8f06b2d8
PB		 941 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
942 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
4a5329c6 943
8f06b2d8
PB		 944 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
945 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
946 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
947 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
c19d1205 948
8f06b2d8
PB		 949 /* ARM Instructions. */
950 {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
951 {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
952 {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
953 {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
954 {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
955 {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
956 {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
957 {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
958 {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
959 {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
960 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
961 {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
962 {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
963 {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
964 {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
965 {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
966 {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
967 {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
968 {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
969 {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
970 {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
971 {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
972 {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
973 {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
974 {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
975 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
976 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
977 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
c16d2bf0 978 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 979
980 /* The rest. */
981 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
982 {0, 0x00000000, 0x00000000, 0}
983};
984
985/* print_insn_thumb16 recognizes the following format control codes:
986
987 %S print Thumb register (bits 3..5 as high number if bit 6 set)
988 %D print Thumb register (bits 0..2 as high number if bit 7 set)
989 %<bitfield>I print bitfield as a signed decimal
990 (top bit of range being the sign bit)
991 %N print Thumb register mask (with LR)
992 %O print Thumb register mask (with PC)
993 %M print Thumb register mask
994 %b print CZB's 6-bit unsigned branch destination
995 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 996 %c print the condition code
997 %C print the condition code, or "s" if not conditional
998 %x print warning if conditional an not at end of IT block"
999 %X print "\t; unpredictable <IT:code>" if conditional
1000 %I print IT instruction suffix and operands
8f06b2d8
PB		 1001 %<bitfield>r print bitfield as an ARM register
1002 %<bitfield>d print bitfield as a decimal
1003 %<bitfield>H print (bitfield * 2) as a decimal
1004 %<bitfield>W print (bitfield * 4) as a decimal
1005 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1006 %<bitfield>B print Thumb branch destination (signed displacement)
1007 %<bitfield>c print bitfield as a condition code
1008 %<bitnum>'c print specified char iff bit is one
1009 %<bitnum>?ab print a if bit is one else print b. */
1010
1011static const struct opcode16 thumb_opcodes[] =
1012{
1013 /* Thumb instructions. */
1014
1015 /* ARM V6K no-argument instructions. */
c22aaad1
PB		 1016 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1017 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1018 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1019 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1020 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1021 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 1022
1023 /* ARM V6T2 instructions. */
c22aaad1
PB		 1024 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1025 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1026 {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 1027
1028 /* ARM V6. */
c22aaad1
PB		 1029 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1030 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1031 {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1032 {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1033 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1034 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1035 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1036 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1037 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1038 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1039 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 1040
1041 /* ARM V5 ISA extends Thumb. */
c22aaad1 1042 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 1043 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
c22aaad1 1044 {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 1045 /* ARM V4T ISA (Thumb v1). */
c22aaad1 1046 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
8f06b2d8 1047 /* Format 4. */
c22aaad1
PB		 1048 {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1049 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1050 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1051 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1052 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1053 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1054 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1055 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1056 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1057 {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1058 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1059 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1060 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1061 {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1062 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1063 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 1064 /* format 13 */
c22aaad1
PB		 1065 {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1066 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 1067 /* format 5 */
c22aaad1
PB		 1068 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1069 {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1070 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1071 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 1072 /* format 14 */
c22aaad1
PB		 1073 {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1074 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 1075 /* format 2 */
c22aaad1
PB		 1076 {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1077 {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1078 {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1079 {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 1080 /* format 8 */
c22aaad1
PB		 1081 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1082 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1083 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 1084 /* format 7 */
c22aaad1
PB		 1085 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1086 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 1087 /* format 1 */
c22aaad1
PB		 1088 {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1089 {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1090 {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 1091 /* format 3 */
c22aaad1
PB		 1092 {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1093 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1094 {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1095 {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 1096 /* format 6 */
c22aaad1 1097 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
8f06b2d8 1098 /* format 9 */
c22aaad1
PB		 1099 {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1100 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1101 {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1102 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 1103 /* format 10 */
c22aaad1
PB		 1104 {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1105 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 1106 /* format 11 */
c22aaad1
PB		 1107 {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1108 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 1109 /* format 12 */
c22aaad1
PB		 1110 {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
1111 {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 1112 /* format 15 */
c22aaad1
PB		 1113 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1114 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
8f06b2d8 1115 /* format 17 */
c22aaad1 1116 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 1117 /* format 16 */
c22aaad1 1118 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 1119 /* format 18 */
c22aaad1 1120 {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 1121
1122 /* The E800 .. FFFF range is unconditionally redirected to the
1123 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1124 are processed via that table. Thus, we can never encounter a
1125 bare "second half of BL/BLX(1)" instruction here. */
1126 {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
1127 {0, 0, 0, 0}
1128};
1129
1130/* Thumb32 opcodes use the same table structure as the ARM opcodes.
1131 We adopt the convention that hw1 is the high 16 bits of .value and
1132 .mask, hw2 the low 16 bits.
1133
1134 print_insn_thumb32 recognizes the following format control codes:
1135
1136 %% %
1137
1138 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1139 %M print a modified 12-bit immediate (same location)
1140 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1141 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1142 %S print a possibly-shifted Rm
1143
1144 %a print the address of a plain load/store
1145 %w print the width and signedness of a core load/store
1146 %m print register mask for ldm/stm
1147
1148 %E print the lsb and width fields of a bfc/bfi instruction
1149 %F print the lsb and width fields of a sbfx/ubfx instruction
1150 %b print a conditional branch offset
1151 %B print an unconditional branch offset
1152 %s print the shift field of an SSAT instruction
1153 %R print the rotation field of an SXT instruction
62b3e311
PB		 1154 %U print barrier type.
1155 %P print address for pli instruction.
c22aaad1
PB		 1156 %c print the condition code
1157 %x print warning if conditional an not at end of IT block"
1158 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 1159
1160 %<bitfield>d print bitfield in decimal
1161 %<bitfield>W print bitfield*4 in decimal
1162 %<bitfield>r print bitfield as an ARM register
1163 %<bitfield>c print bitfield as a condition code
1164
16980d0b
JB		 1165 %<bitfield>'c print specified char iff bitfield is all ones
1166 %<bitfield>`c print specified char iff bitfield is all zeroes
1167 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 1168
1169 With one exception at the bottom (done because BL and BLX(1) need
1170 to come dead last), this table was machine-sorted first in
1171 decreasing order of number of bits set in the mask, then in
1172 increasing numeric order of mask, then in increasing numeric order
1173 of opcode. This order is not the clearest for a human reader, but
1174 is guaranteed never to catch a special-case bit pattern with a more
1175 general mask, which is important, because this instruction encoding
1176 makes heavy use of special-case bit patterns. */
1177static const struct opcode32 thumb32_opcodes[] =
1178{
62b3e311 1179 /* V7 instructions. */
c22aaad1
PB		 1180 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1181 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1182 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1183 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1184 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1185 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1186 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 1187
8f06b2d8 1188 /* Instructions defined in the basic V6T2 set. */
c22aaad1
PB		 1189 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1190 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1191 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1192 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1193 {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
1194 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1195
1196 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1197 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1198 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1199 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1200 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1201 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1202 {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
1203 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1204 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1205 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1206 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1207 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1208 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1209 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1210 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1211 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1212 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t#%0-4d%21'!"},
1213 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t#%0-4d%21'!"},
1214 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1215 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1216 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1217 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1218 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1219 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1220 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1221 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1222 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1223 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1224 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1225 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1226 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1227 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1228 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1229 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1230 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1231 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1232 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1233 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1234 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1235 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1236 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1237 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1238 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1239 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1240 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1241 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1242 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"},
1243 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1244 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1245 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1246 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1247 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"},
1248 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1249 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1250 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1251 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1252 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1253 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1254 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1255 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1256 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1257 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1258 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1259 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1260 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1261 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1262 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"},
1263 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1264 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1265 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"},
1266 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1267 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"},
1268 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1269 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1270 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1271 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1272 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1273 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1274 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1275 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1276 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1277 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1278 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1279 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1280 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1281 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1282 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1283 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1284 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1285 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1286 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1287 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1288 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1289 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1290 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1291 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1292 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1293 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1294 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1295 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1296 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1297 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1298 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1299 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1300 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1301 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1302 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1303 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1304 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1305 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1306 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1307 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1308 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1309 {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1310 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1311 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1312 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1313 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1314 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1315 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1316 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1317 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1318 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1319 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1320 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1321 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1322 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1323 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1324 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1325 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1326 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1327 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1328 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1329 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1330 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1331 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1332 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1333 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1334 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1335 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1336 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1337 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1338 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1339 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1340 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1341 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1342 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1343 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1344 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1345 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1346 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1347 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1348 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1349 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1350 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1351 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1352 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1353 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1354 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1355 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1356 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1357 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1358 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1359 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1360 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1361 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1362 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
1363 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
1364 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1365 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 1366
1367 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1368 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1369 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
c22aaad1
PB		 1370 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1371 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 1372
8f06b2d8 1373 /* These have been 32-bit since the invention of Thumb. */
c22aaad1
PB		 1374 {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
1375 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 1376
1377 /* Fallback. */
1378 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
1379 {0, 0, 0, 0}
1380};
1381
1382static const char *const arm_conditional[] =
1383{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 1384 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 1385
1386static const char *const arm_fp_const[] =
1387{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1388
1389static const char *const arm_shift[] =
1390{"lsl", "lsr", "asr", "ror"};
1391
1392typedef struct
1393{
1394 const char *name;
1395 const char *description;
1396 const char *reg_names[16];
1397}
1398arm_regname;
1399
1400static const arm_regname regnames[] =
1401{
1402 { "raw" , "Select raw register names",
1403 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1404 { "gcc", "Select register names used by GCC",
1405 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1406 { "std", "Select register names used in ARM's ISA documentation",
1407 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1408 { "apcs", "Select register names used in the APCS",
1409 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1410 { "atpcs", "Select register names used in the ATPCS",
1411 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1412 { "special-atpcs", "Select special register names used in the ATPCS",
1413 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1414};
1415
1416static const char *const iwmmxt_wwnames[] =
1417{"b", "h", "w", "d"};
1418
1419static const char *const iwmmxt_wwssnames[] =
1420{"b", "bus", "b", "bss",
1421 "h", "hus", "h", "hss",
1422 "w", "wus", "w", "wss",
1423 "d", "dus", "d", "dss"
1424};
1425
1426static const char *const iwmmxt_regnames[] =
1427{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1428 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1429};
1430
1431static const char *const iwmmxt_cregnames[] =
1432{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1433 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1434};
1435
1436/* Default to GCC register name set. */
1437static unsigned int regname_selected = 1;
1438
1439#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1440#define arm_regnames regnames[regname_selected].reg_names
1441
1442static bfd_boolean force_thumb = FALSE;
1443
c22aaad1
PB		 1444/* Current IT instruction state. This contains the same state as the IT
1445 bits in the CPSR. */
1446static unsigned int ifthen_state;
1447/* IT state for the next instruction. */
1448static unsigned int ifthen_next_state;
1449/* The address of the insn for which the IT state is valid. */
1450static bfd_vma ifthen_address;
1451#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1452
8f06b2d8
PB		 1453\f
1454/* Functions. */
1455int
1456get_arm_regname_num_options (void)
1457{
1458 return NUM_ARM_REGNAMES;
1459}
1460
1461int
1462set_arm_regname_option (int option)
1463{
1464 int old = regname_selected;
1465 regname_selected = option;
1466 return old;
1467}
1468
1469int
1470get_arm_regnames (int option, const char **setname, const char **setdescription,
1471 const char *const **register_names)
1472{
1473 *setname = regnames[option].name;
1474 *setdescription = regnames[option].description;
1475 *register_names = regnames[option].reg_names;
1476 return 16;
1477}
1478
16980d0b
JB		 1479/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1480 Returns pointer to following character of the format string and
1481 fills in *VALUEP and *WIDTHP with the extracted value and number of
1482 bits extracted. WIDTHP can be NULL. */
1483
1484static const char *
1485arm_decode_bitfield (const char *ptr, unsigned long insn,
1486 unsigned long *valuep, int *widthp)
1487{
1488 unsigned long value = 0;
1489 int width = 0;
1490
1491 do
1492 {
1493 int start, end;
1494 int bits;
1495
1496 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1497 start = start * 10 + *ptr - '0';
1498 if (*ptr == '-')
1499 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1500 end = end * 10 + *ptr - '0';
1501 else
1502 end = start;
1503 bits = end - start;
1504 if (bits < 0)
1505 abort ();
1506 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1507 width += bits + 1;
1508 }
1509 while (*ptr++ == ',');
1510 *valuep = value;
1511 if (widthp)
1512 *widthp = width;
1513 return ptr - 1;
1514}
1515
8f06b2d8
PB		 1516static void
1517arm_decode_shift (long given, fprintf_ftype func, void *stream)
1518{
1519 func (stream, "%s", arm_regnames[given & 0xf]);
1520
1521 if ((given & 0xff0) != 0)
1522 {
1523 if ((given & 0x10) == 0)
1524 {
1525 int amount = (given & 0xf80) >> 7;
1526 int shift = (given & 0x60) >> 5;
1527
1528 if (amount == 0)
1529 {
1530 if (shift == 3)
1531 {
1532 func (stream, ", rrx");
1533 return;
1534 }
1535
1536 amount = 32;
1537 }
1538
1539 func (stream, ", %s #%d", arm_shift[shift], amount);
1540 }
1541 else
1542 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1543 arm_regnames[(given & 0xf00) >> 8]);
1544 }
1545}
1546
1547/* Print one coprocessor instruction on INFO->STREAM.
1548 Return TRUE if the instuction matched, FALSE if this is not a
1549 recognised coprocessor instruction. */
1550
1551static bfd_boolean
16980d0b 1552print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
8f06b2d8
PB		 1553 bfd_boolean thumb)
1554{
1555 const struct opcode32 *insn;
1556 void *stream = info->stream;
1557 fprintf_ftype func = info->fprintf_func;
1558 unsigned long mask;
1559 unsigned long value;
c22aaad1 1560 int cond;
8f06b2d8
PB		 1561
1562 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1563 {
1564 if (insn->value == FIRST_IWMMXT_INSN
1565 && info->mach != bfd_mach_arm_XScale
1566 && info->mach != bfd_mach_arm_iWMMXt)
1567 insn = insn + IWMMXT_INSN_COUNT;
1568
1569 mask = insn->mask;
1570 value = insn->value;
1571 if (thumb)
1572 {
1573 /* The high 4 bits are 0xe for Arm conditional instructions, and
1574 0xe for arm unconditional instructions. The rest of the
1575 encoding is the same. */
1576 mask |= 0xf0000000;
1577 value |= 0xe0000000;
c22aaad1
PB		 1578 if (ifthen_state)
1579 cond = IFTHEN_COND;
1580 else
1581 cond = 16;
8f06b2d8
PB		 1582 }
1583 else
1584 {
1585 /* Only match unconditional instuctions against unconditional
1586 patterns. */
1587 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 1588 {
1589 mask |= 0xf0000000;
1590 cond = 16;
1591 }
1592 else
1593 {
1594 cond = (given >> 28) & 0xf;
1595 if (cond == 0xe)
1596 cond = 16;
1597 }
8f06b2d8
PB		 1598 }
1599 if ((given & mask) == value)
1600 {
1601 const char *c;
1602
1603 for (c = insn->assembler; *c; c++)
1604 {
1605 if (*c == '%')
1606 {
1607 switch (*++c)
1608 {
1609 case '%':
1610 func (stream, "%%");
1611 break;
1612
1613 case 'A':
1614 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1615
1616 if ((given & (1 << 24)) != 0)
1617 {
1618 int offset = given & 0xff;
1619
1620 if (offset)
1621 func (stream, ", #%s%d]%s",
1622 ((given & 0x00800000) == 0 ? "-" : ""),
1623 offset * 4,
1624 ((given & 0x00200000) != 0 ? "!" : ""));
1625 else
1626 func (stream, "]");
1627 }
1628 else
1629 {
1630 int offset = given & 0xff;
1631
1632 func (stream, "]");
1633
1634 if (given & (1 << 21))
1635 {
1636 if (offset)
1637 func (stream, ", #%s%d",
1638 ((given & 0x00800000) == 0 ? "-" : ""),
1639 offset * 4);
1640 }
1641 else
1642 func (stream, ", {%d}", offset);
1643 }
1644 break;
1645
16980d0b
JB		 1646 case 'B':
1647 {
1648 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
1649 int offset = (given >> 1) & 0x3f;
1650
1651 if (offset == 1)
1652 func (stream, "{d%d}", regno);
1653 else if (regno + offset > 32)
1654 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1655 else
1656 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
1657 }
1658 break;
1659
1660 case 'C':
1661 {
1662 int rn = (given >> 16) & 0xf;
1663 int offset = (given & 0xff) * 4;
1664 int add = (given >> 23) & 1;
1665
1666 func (stream, "[%s", arm_regnames[rn]);
1667
1668 if (offset)
1669 {
1670 if (!add)
1671 offset = -offset;
1672 func (stream, ", #%d", offset);
1673 }
1674 func (stream, "]");
1675 if (rn == 15)
1676 {
1677 func (stream, "\t; ");
1678 /* FIXME: Unsure if info->bytes_per_chunk is the
1679 right thing to use here. */
1680 info->print_address_func (offset + pc
1681 + info->bytes_per_chunk * 2, info);
1682 }
1683 }
1684 break;
c22aaad1 1685
8f06b2d8 1686 case 'c':
c22aaad1 1687 func (stream, "%s", arm_conditional[cond]);
8f06b2d8
PB		 1688 break;
1689
1690 case 'I':
1691 /* Print a Cirrus/DSP shift immediate. */
1692 /* Immediates are 7bit signed ints with bits 0..3 in
1693 bits 0..3 of opcode and bits 4..6 in bits 5..7
1694 of opcode. */
1695 {
1696 int imm;
1697
1698 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1699
1700 /* Is ``imm'' a negative number? */
1701 if (imm & 0x40)
1702 imm |= (-1 << 7);
1703
1704 func (stream, "%d", imm);
1705 }
1706
1707 break;
1708
1709 case 'F':
1710 switch (given & 0x00408000)
1711 {
1712 case 0:
1713 func (stream, "4");
1714 break;
1715 case 0x8000:
1716 func (stream, "1");
1717 break;
1718 case 0x00400000:
1719 func (stream, "2");
1720 break;
1721 default:
1722 func (stream, "3");
1723 }
1724 break;
1725
1726 case 'P':
1727 switch (given & 0x00080080)
1728 {
1729 case 0:
1730 func (stream, "s");
1731 break;
1732 case 0x80:
1733 func (stream, "d");
1734 break;
1735 case 0x00080000:
1736 func (stream, "e");
1737 break;
1738 default:
1739 func (stream, _("<illegal precision>"));
1740 break;
1741 }
1742 break;
1743 case 'Q':
1744 switch (given & 0x00408000)
1745 {
1746 case 0:
1747 func (stream, "s");
1748 break;
1749 case 0x8000:
1750 func (stream, "d");
1751 break;
1752 case 0x00400000:
1753 func (stream, "e");
1754 break;
1755 default:
1756 func (stream, "p");
1757 break;
1758 }
1759 break;
1760 case 'R':
1761 switch (given & 0x60)
1762 {
1763 case 0:
1764 break;
1765 case 0x20:
1766 func (stream, "p");
1767 break;
1768 case 0x40:
1769 func (stream, "m");
1770 break;
1771 default:
1772 func (stream, "z");
1773 break;
1774 }
1775 break;
1776
1777 case '0': case '1': case '2': case '3': case '4':
1778 case '5': case '6': case '7': case '8': case '9':
1779 {
16980d0b
JB		 1780 int width;
1781 unsigned long value;
1782
1783 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8
PB		 1784
1785 switch (*c)
1786 {
16980d0b
JB		 1787 case 'r':
1788 func (stream, "%s", arm_regnames[value]);
1789 break;
1790 case 'D':
1791 func (stream, "d%ld", value);
1792 break;
1793 case 'Q':
1794 if (value & 1)
1795 func (stream, "<illegal reg q%ld.5>", value >> 1);
1796 else
1797 func (stream, "q%ld", value >> 1);
1798 break;
1799 case 'd':
1800 func (stream, "%ld", value);
1801 break;
1802 case 'k':
1803 {
1804 int from = (given & (1 << 7)) ? 32 : 16;
1805 func (stream, "%ld", from - value);
1806 }
1807 break;
1808
1809 case 'f':
1810 if (value > 7)
1811 func (stream, "#%s", arm_fp_const[value & 7]);
1812 else
1813 func (stream, "f%ld", value);
1814 break;
8f06b2d8 1815
16980d0b
JB		 1816 case 'w':
1817 if (width == 2)
1818 func (stream, "%s", iwmmxt_wwnames[value]);
1819 else
1820 func (stream, "%s", iwmmxt_wwssnames[value]);
1821 break;
8f06b2d8 1822
16980d0b
JB		 1823 case 'g':
1824 func (stream, "%s", iwmmxt_regnames[value]);
1825 break;
1826 case 'G':
1827 func (stream, "%s", iwmmxt_cregnames[value]);
1828 break;
1829 case '`':
1830 c++;
1831 if (value == 0)
1832 func (stream, "%c", *c);
1833 break;
1834 case '\'':
1835 c++;
1836 if (value == ((1ul << width) - 1))
1837 func (stream, "%c", *c);
1838 break;
1839 case '?':
1840 func (stream, "%c", c[(1 << width) - (int)value]);
1841 c += 1 << width;
1842 break;
1843 default:
1844 abort ();
1845 }
1846 break;
8f06b2d8 1847
16980d0b
JB		 1848 case 'y':
1849 case 'z':
1850 {
1851 int single = *c++ == 'y';
1852 int regno;
1853
1854 switch (*c)
1855 {
1856 case '4': /* Sm pair */
1857 func (stream, "{");
1858 /* Fall through. */
1859 case '0': /* Sm, Dm */
1860 regno = given & 0x0000000f;
1861 if (single)
8f06b2d8 1862 {
16980d0b
JB		 1863 regno <<= 1;
1864 regno += (given >> 5) & 1;
8f06b2d8 1865 }
16980d0b
JB		 1866 else
1867 regno += ((given >> 5) & 1) << 4;
1868 break;
8f06b2d8 1869
16980d0b
JB		 1870 case '1': /* Sd, Dd */
1871 regno = (given >> 12) & 0x0000000f;
1872 if (single)
8f06b2d8 1873 {
16980d0b
JB		 1874 regno <<= 1;
1875 regno += (given >> 22) & 1;
8f06b2d8 1876 }
16980d0b
JB		 1877 else
1878 regno += ((given >> 22) & 1) << 4;
1879 break;
8f06b2d8 1880
16980d0b
JB		 1881 case '2': /* Sn, Dn */
1882 regno = (given >> 16) & 0x0000000f;
1883 if (single)
8f06b2d8 1884 {
16980d0b
JB		 1885 regno <<= 1;
1886 regno += (given >> 7) & 1;
8f06b2d8 1887 }
16980d0b
JB		 1888 else
1889 regno += ((given >> 7) & 1) << 4;
1890 break;
1891
1892 case '3': /* List */
1893 func (stream, "{");
1894 regno = (given >> 12) & 0x0000000f;
1895 if (single)
8f06b2d8 1896 {
16980d0b
JB		 1897 regno <<= 1;
1898 regno += (given >> 22) & 1;
8f06b2d8 1899 }
16980d0b
JB		 1900 else
1901 regno += ((given >> 22) & 1) << 4;
1902 break;
1903
1904 default:
1905 abort ();
1906 }
8f06b2d8 1907
16980d0b 1908 func (stream, "%c%d", single ? 's' : 'd', regno);
8f06b2d8 1909
16980d0b 1910 if (*c == '3')
8f06b2d8 1911 {
16980d0b
JB		 1912 int count = given & 0xff;
1913
1914 if (single == 0)
1915 count >>= 1;
1916
1917 if (--count)
8f06b2d8 1918 {
16980d0b
JB		 1919 func (stream, "-%c%d",
1920 single ? 's' : 'd',
1921 regno + count);
8f06b2d8 1922 }
16980d0b
JB		 1923
1924 func (stream, "}");
8f06b2d8 1925 }
16980d0b
JB		 1926 else if (*c == '4')
1927 func (stream, ", %c%d}", single ? 's' : 'd',
1928 regno + 1);
1929 }
8f06b2d8 1930 break;
16980d0b 1931
8f06b2d8
PB		 1932 case 'L':
1933 switch (given & 0x00400100)
1934 {
1935 case 0x00000000: func (stream, "b"); break;
1936 case 0x00400000: func (stream, "h"); break;
1937 case 0x00000100: func (stream, "w"); break;
1938 case 0x00400100: func (stream, "d"); break;
1939 default:
1940 break;
1941 }
1942 break;
a7f8487e 1943
8f06b2d8
PB		 1944 case 'Z':
1945 {
1946 int value;
1947 /* given (20, 23) | given (0, 3) */
1948 value = ((given >> 16) & 0xf0) | (given & 0xf);
1949 func (stream, "%d", value);
1950 }
1951 break;
a7f8487e 1952
8f06b2d8
PB		 1953 case 'l':
1954 /* This is like the 'A' operator, except that if
1955 the width field "M" is zero, then the offset is
1956 *not* multiplied by four. */
1957 {
1958 int offset = given & 0xff;
1959 int multiplier = (given & 0x00000100) ? 4 : 1;
a7f8487e 1960
8f06b2d8 1961 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
b34976b6 1962
8f06b2d8
PB		 1963 if (offset)
1964 {
1965 if ((given & 0x01000000) != 0)
1966 func (stream, ", #%s%d]%s",
1967 ((given & 0x00800000) == 0 ? "-" : ""),
1968 offset * multiplier,
1969 ((given & 0x00200000) != 0 ? "!" : ""));
1970 else
1971 func (stream, "], #%s%d",
1972 ((given & 0x00800000) == 0 ? "-" : ""),
1973 offset * multiplier);
1974 }
1975 else
1976 func (stream, "]");
1977 }
1978 break;
b34976b6 1979
8f06b2d8
PB		 1980 default:
1981 abort ();
1982 }
1983 }
252b5132 1984 }
8f06b2d8
PB		 1985 else
1986 func (stream, "%c", *c);
252b5132 1987 }
8f06b2d8 1988 return TRUE;
252b5132 1989 }
252b5132 1990 }
8f06b2d8 1991 return FALSE;
252b5132
RH		 1992}
1993
62b3e311
PB		 1994static void
1995print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
1996{
1997 void *stream = info->stream;
1998 fprintf_ftype func = info->fprintf_func;
1999
2000 if (((given & 0x000f0000) == 0x000f0000)
2001 && ((given & 0x02000000) == 0))
2002 {
2003 int offset = given & 0xfff;
2004
2005 func (stream, "[pc");
2006
2007 if (given & 0x01000000)
2008 {
2009 if ((given & 0x00800000) == 0)
2010 offset = - offset;
2011
2012 /* Pre-indexed. */
2013 func (stream, ", #%d]", offset);
2014
2015 offset += pc + 8;
2016
2017 /* Cope with the possibility of write-back
2018 being used. Probably a very dangerous thing
2019 for the programmer to do, but who are we to
2020 argue ? */
2021 if (given & 0x00200000)
2022 func (stream, "!");
2023 }
2024 else
2025 {
2026 /* Post indexed. */
2027 func (stream, "], #%d", offset);
2028
2029 /* ie ignore the offset. */
2030 offset = pc + 8;
2031 }
2032
2033 func (stream, "\t; ");
2034 info->print_address_func (offset, info);
2035 }
2036 else
2037 {
2038 func (stream, "[%s",
2039 arm_regnames[(given >> 16) & 0xf]);
2040 if ((given & 0x01000000) != 0)
2041 {
2042 if ((given & 0x02000000) == 0)
2043 {
2044 int offset = given & 0xfff;
2045 if (offset)
2046 func (stream, ", #%s%d",
2047 (((given & 0x00800000) == 0)
2048 ? "-" : ""), offset);
2049 }
2050 else
2051 {
2052 func (stream, ", %s",
2053 (((given & 0x00800000) == 0)
2054 ? "-" : ""));
2055 arm_decode_shift (given, func, stream);
2056 }
2057
2058 func (stream, "]%s",
2059 ((given & 0x00200000) != 0) ? "!" : "");
2060 }
2061 else
2062 {
2063 if ((given & 0x02000000) == 0)
2064 {
2065 int offset = given & 0xfff;
2066 if (offset)
2067 func (stream, "], #%s%d",
2068 (((given & 0x00800000) == 0)
2069 ? "-" : ""), offset);
2070 else
2071 func (stream, "]");
2072 }
2073 else
2074 {
2075 func (stream, "], %s",
2076 (((given & 0x00800000) == 0)
2077 ? "-" : ""));
2078 arm_decode_shift (given, func, stream);
2079 }
2080 }
2081 }
2082}
2083
16980d0b
JB		 2084/* Print one neon instruction on INFO->STREAM.
2085 Return TRUE if the instuction matched, FALSE if this is not a
2086 recognised neon instruction. */
2087
2088static bfd_boolean
2089print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2090{
2091 const struct opcode32 *insn;
2092 void *stream = info->stream;
2093 fprintf_ftype func = info->fprintf_func;
2094
2095 if (thumb)
2096 {
2097 if ((given & 0xef000000) == 0xef000000)
2098 {
2099 /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2100 unsigned long bit28 = given & (1 << 28);
2101
2102 given &= 0x00ffffff;
2103 if (bit28)
2104 given |= 0xf3000000;
2105 else
2106 given |= 0xf2000000;
2107 }
2108 else if ((given & 0xff000000) == 0xf9000000)
2109 given ^= 0xf9000000 ^ 0xf4000000;
2110 else
2111 return FALSE;
2112 }
2113
2114 for (insn = neon_opcodes; insn->assembler; insn++)
2115 {
2116 if ((given & insn->mask) == insn->value)
2117 {
2118 const char *c;
2119
2120 for (c = insn->assembler; *c; c++)
2121 {
2122 if (*c == '%')
2123 {
2124 switch (*++c)
2125 {
2126 case '%':
2127 func (stream, "%%");
2128 break;
2129
c22aaad1
PB		 2130 case 'c':
2131 if (thumb && ifthen_state)
2132 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2133 break;
2134
16980d0b
JB		 2135 case 'A':
2136 {
2137 static const unsigned char enc[16] =
2138 {
2139 0x4, 0x14, /* st4 0,1 */
2140 0x4, /* st1 2 */
2141 0x4, /* st2 3 */
2142 0x3, /* st3 4 */
2143 0x13, /* st3 5 */
2144 0x3, /* st1 6 */
2145 0x1, /* st1 7 */
2146 0x2, /* st2 8 */
2147 0x12, /* st2 9 */
2148 0x2, /* st1 10 */
2149 0, 0, 0, 0, 0
2150 };
2151 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2152 int rn = ((given >> 16) & 0xf);
2153 int rm = ((given >> 0) & 0xf);
2154 int align = ((given >> 4) & 0x3);
2155 int type = ((given >> 8) & 0xf);
2156 int n = enc[type] & 0xf;
2157 int stride = (enc[type] >> 4) + 1;
2158 int ix;
2159
2160 func (stream, "{");
2161 if (stride > 1)
2162 for (ix = 0; ix != n; ix++)
2163 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2164 else if (n == 1)
2165 func (stream, "d%d", rd);
2166 else
2167 func (stream, "d%d-d%d", rd, rd + n - 1);
2168 func (stream, "}, [%s", arm_regnames[rn]);
2169 if (align)
2170 func (stream, ", :%d", 32 << align);
2171 func (stream, "]");
2172 if (rm == 0xd)
2173 func (stream, "!");
2174 else if (rm != 0xf)
2175 func (stream, ", %s", arm_regnames[rm]);
2176 }
2177 break;
2178
2179 case 'B':
2180 {
2181 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2182 int rn = ((given >> 16) & 0xf);
2183 int rm = ((given >> 0) & 0xf);
2184 int idx_align = ((given >> 4) & 0xf);
2185 int align = 0;
2186 int size = ((given >> 10) & 0x3);
2187 int idx = idx_align >> (size + 1);
2188 int length = ((given >> 8) & 3) + 1;
2189 int stride = 1;
2190 int i;
2191
2192 if (length > 1 && size > 0)
2193 stride = (idx_align & (1 << size)) ? 2 : 1;
2194
2195 switch (length)
2196 {
2197 case 1:
2198 {
2199 int amask = (1 << size) - 1;
2200 if ((idx_align & (1 << size)) != 0)
2201 return FALSE;
2202 if (size > 0)
2203 {
2204 if ((idx_align & amask) == amask)
2205 align = 8 << size;
2206 else if ((idx_align & amask) != 0)
2207 return FALSE;
2208 }
2209 }
2210 break;
2211
2212 case 2:
2213 if (size == 2 && (idx_align & 2) != 0)
2214 return FALSE;
2215 align = (idx_align & 1) ? 16 << size : 0;
2216 break;
2217
2218 case 3:
2219 if ((size == 2 && (idx_align & 3) != 0)
2220 || (idx_align & 1) != 0)
2221 return FALSE;
2222 break;
2223
2224 case 4:
2225 if (size == 2)
2226 {
2227 if ((idx_align & 3) == 3)
2228 return FALSE;
2229 align = (idx_align & 3) * 64;
2230 }
2231 else
2232 align = (idx_align & 1) ? 32 << size : 0;
2233 break;
2234
2235 default:
2236 abort ();
2237 }
2238
2239 func (stream, "{");
2240 for (i = 0; i < length; i++)
2241 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2242 rd + i * stride, idx);
2243 func (stream, "}, [%s", arm_regnames[rn]);
2244 if (align)
2245 func (stream, ", :%d", align);
2246 func (stream, "]");
2247 if (rm == 0xd)
2248 func (stream, "!");
2249 else if (rm != 0xf)
2250 func (stream, ", %s", arm_regnames[rm]);
2251 }
2252 break;
2253
2254 case 'C':
2255 {
2256 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2257 int rn = ((given >> 16) & 0xf);
2258 int rm = ((given >> 0) & 0xf);
2259 int align = ((given >> 4) & 0x1);
2260 int size = ((given >> 6) & 0x3);
2261 int type = ((given >> 8) & 0x3);
2262 int n = type + 1;
2263 int stride = ((given >> 5) & 0x1);
2264 int ix;
2265
2266 if (stride && (n == 1))
2267 n++;
2268 else
2269 stride++;
2270
2271 func (stream, "{");
2272 if (stride > 1)
2273 for (ix = 0; ix != n; ix++)
2274 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2275 else if (n == 1)
2276 func (stream, "d%d[]", rd);
2277 else
2278 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2279 func (stream, "}, [%s", arm_regnames[rn]);
2280 if (align)
2281 {
2282 int align = (8 * (type + 1)) << size;
2283 if (type == 3)
2284 align = (size > 1) ? align >> 1 : align;
2285 if (type == 2 || (type == 0 && !size))
2286 func (stream, ", :<bad align %d>", align);
2287 else
2288 func (stream, ", :%d", align);
2289 }
2290 func (stream, "]");
2291 if (rm == 0xd)
2292 func (stream, "!");
2293 else if (rm != 0xf)
2294 func (stream, ", %s", arm_regnames[rm]);
2295 }
2296 break;
2297
2298 case 'D':
2299 {
2300 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2301 int size = (given >> 20) & 3;
2302 int reg = raw_reg & ((4 << size) - 1);
2303 int ix = raw_reg >> size >> 2;
2304
2305 func (stream, "d%d[%d]", reg, ix);
2306 }
2307 break;
2308
2309 case 'E':
2310 /* Neon encoded constant for mov, mvn, vorr, vbic */
2311 {
2312 int bits = 0;
2313 int cmode = (given >> 8) & 0xf;
2314 int op = (given >> 5) & 0x1;
2315 unsigned long value = 0, hival = 0;
2316 unsigned shift;
2317 int size = 0;
0dbde4cf 2318 int isfloat = 0;
16980d0b
JB		 2319
2320 bits |= ((given >> 24) & 1) << 7;
2321 bits |= ((given >> 16) & 7) << 4;
2322 bits |= ((given >> 0) & 15) << 0;
2323
2324 if (cmode < 8)
2325 {
2326 shift = (cmode >> 1) & 3;
2327 value = (unsigned long)bits << (8 * shift);
2328 size = 32;
2329 }
2330 else if (cmode < 12)
2331 {
2332 shift = (cmode >> 1) & 1;
2333 value = (unsigned long)bits << (8 * shift);
2334 size = 16;
2335 }
2336 else if (cmode < 14)
2337 {
2338 shift = (cmode & 1) + 1;
2339 value = (unsigned long)bits << (8 * shift);
2340 value |= (1ul << (8 * shift)) - 1;
2341 size = 32;
2342 }
2343 else if (cmode == 14)
2344 {
2345 if (op)
2346 {
2347 /* bit replication into bytes */
2348 int ix;
2349 unsigned long mask;
2350
2351 value = 0;
2352 hival = 0;
2353 for (ix = 7; ix >= 0; ix--)
2354 {
2355 mask = ((bits >> ix) & 1) ? 0xff : 0;
2356 if (ix <= 3)
2357 value = (value << 8) | mask;
2358 else
2359 hival = (hival << 8) | mask;
2360 }
2361 size = 64;
2362 }
2363 else
2364 {
2365 /* byte replication */
2366 value = (unsigned long)bits;
2367 size = 8;
2368 }
2369 }
2370 else if (!op)
2371 {
2372 /* floating point encoding */
2373 int tmp;
2374
0dbde4cf 2375 value = (unsigned long)(bits & 0x7f) << 19;
16980d0b
JB		 2376 value |= (unsigned long)(bits & 0x80) << 24;
2377 tmp = bits & 0x40 ? 0x3c : 0x40;
2378 value |= (unsigned long)tmp << 24;
2379 size = 32;
0dbde4cf 2380 isfloat = 1;
16980d0b
JB		 2381 }
2382 else
2383 {
2384 func (stream, "<illegal constant %.8x:%x:%x>",
2385 bits, cmode, op);
2386 size = 32;
2387 break;
2388 }
2389 switch (size)
2390 {
2391 case 8:
2392 func (stream, "#%ld\t; 0x%.2lx", value, value);
2393 break;
2394
2395 case 16:
2396 func (stream, "#%ld\t; 0x%.4lx", value, value);
2397 break;
2398
2399 case 32:
0dbde4cf
JB		 2400 if (isfloat)
2401 {
2402 unsigned char valbytes[4];
2403 double fvalue;
2404
2405 /* Do this a byte at a time so we don't have to
2406 worry about the host's endianness. */
2407 valbytes[0] = value & 0xff;
2408 valbytes[1] = (value >> 8) & 0xff;
2409 valbytes[2] = (value >> 16) & 0xff;
2410 valbytes[3] = (value >> 24) & 0xff;
2411
2412 floatformat_to_double
2413 (&floatformat_ieee_single_little, valbytes,
2414 &fvalue);
2415
2416 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2417 value);
2418 }
2419 else
2420 func (stream, "#%ld\t; 0x%.8lx", value, value);
16980d0b
JB		 2421 break;
2422
2423 case 64:
2424 func (stream, "#0x%.8lx%.8lx", hival, value);
2425 break;
2426
2427 default:
2428 abort ();
2429 }
2430 }
2431 break;
2432
2433 case 'F':
2434 {
2435 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2436 int num = (given >> 8) & 0x3;
2437
2438 if (!num)
2439 func (stream, "{d%d}", regno);
2440 else if (num + regno >= 32)
2441 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2442 else
2443 func (stream, "{d%d-d%d}", regno, regno + num);
2444 }
2445 break;
2446
2447
2448 case '0': case '1': case '2': case '3': case '4':
2449 case '5': case '6': case '7': case '8': case '9':
2450 {
2451 int width;
2452 unsigned long value;
2453
2454 c = arm_decode_bitfield (c, given, &value, &width);
2455
2456 switch (*c)
2457 {
2458 case 'r':
2459 func (stream, "%s", arm_regnames[value]);
2460 break;
2461 case 'd':
2462 func (stream, "%ld", value);
2463 break;
2464 case 'e':
2465 func (stream, "%ld", (1ul << width) - value);
2466 break;
2467
2468 case 'S':
2469 case 'T':
2470 case 'U':
2471 /* various width encodings */
2472 {
2473 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2474 int limit;
2475 unsigned low, high;
2476
2477 c++;
2478 if (*c >= '0' && *c <= '9')
2479 limit = *c - '0';
2480 else if (*c >= 'a' && *c <= 'f')
2481 limit = *c - 'a' + 10;
2482 else
2483 abort ();
2484 low = limit >> 2;
2485 high = limit & 3;
2486
2487 if (value < low || value > high)
2488 func (stream, "<illegal width %d>", base << value);
2489 else
2490 func (stream, "%d", base << value);
2491 }
2492 break;
2493 case 'R':
2494 if (given & (1 << 6))
2495 goto Q;
2496 /* FALLTHROUGH */
2497 case 'D':
2498 func (stream, "d%ld", value);
2499 break;
2500 case 'Q':
2501 Q:
2502 if (value & 1)
2503 func (stream, "<illegal reg q%ld.5>", value >> 1);
2504 else
2505 func (stream, "q%ld", value >> 1);
2506 break;
2507
2508 case '`':
2509 c++;
2510 if (value == 0)
2511 func (stream, "%c", *c);
2512 break;
2513 case '\'':
2514 c++;
2515 if (value == ((1ul << width) - 1))
2516 func (stream, "%c", *c);
2517 break;
2518 case '?':
2519 func (stream, "%c", c[(1 << width) - (int)value]);
2520 c += 1 << width;
2521 break;
2522 default:
2523 abort ();
2524 }
2525 break;
2526
2527 default:
2528 abort ();
2529 }
2530 }
2531 }
2532 else
2533 func (stream, "%c", *c);
2534 }
2535 return TRUE;
2536 }
2537 }
2538 return FALSE;
2539}
2540
4a5329c6
ZW		 2541/* Print one ARM instruction from PC on INFO->STREAM. */
2542
2543static void
2544print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 2545{
6b5d3a4d 2546 const struct opcode32 *insn;
6a51a8a8 2547 void *stream = info->stream;
6b5d3a4d 2548 fprintf_ftype func = info->fprintf_func;
252b5132 2549
16980d0b
JB		 2550 if (print_insn_coprocessor (pc, info, given, FALSE))
2551 return;
2552
2553 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 2554 return;
2555
252b5132
RH		 2556 for (insn = arm_opcodes; insn->assembler; insn++)
2557 {
e16bb312
NC		 2558 if (insn->value == FIRST_IWMMXT_INSN
2559 && info->mach != bfd_mach_arm_XScale
2560 && info->mach != bfd_mach_arm_iWMMXt)
2561 insn = insn + IWMMXT_INSN_COUNT;
2562
0a003adc
ZW		 2563 if ((given & insn->mask) == insn->value
2564 /* Special case: an instruction with all bits set in the condition field
2565 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
2566 or by the catchall at the end of the table. */
2567 && ((given & 0xF0000000) != 0xF0000000
2568 || (insn->mask & 0xF0000000) == 0xF0000000
2569 || (insn->mask == 0 && insn->value == 0)))
252b5132 2570 {
6b5d3a4d 2571 const char *c;
b34976b6 2572
252b5132
RH		 2573 for (c = insn->assembler; *c; c++)
2574 {
2575 if (*c == '%')
2576 {
2577 switch (*++c)
2578 {
2579 case '%':
2580 func (stream, "%%");
2581 break;
2582
2583 case 'a':
62b3e311
PB		 2584 print_arm_address (pc, info, given);
2585 break;
252b5132 2586
62b3e311
PB		 2587 case 'P':
2588 /* Set P address bit and use normal address
2589 printing routine. */
2590 print_arm_address (pc, info, given | (1 << 24));
252b5132
RH		 2591 break;
2592
2593 case 's':
2594 if ((given & 0x004f0000) == 0x004f0000)
2595 {
58efb6c0 2596 /* PC relative with immediate offset. */
252b5132 2597 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 2598
252b5132
RH		 2599 if ((given & 0x00800000) == 0)
2600 offset = -offset;
b34976b6 2601
40536497 2602 func (stream, "[pc, #%d]\t; ", offset);
6b5d3a4d 2603 info->print_address_func (offset + pc + 8, info);
252b5132
RH		 2604 }
2605 else
2606 {
b34976b6 2607 func (stream, "[%s",
252b5132
RH		 2608 arm_regnames[(given >> 16) & 0xf]);
2609 if ((given & 0x01000000) != 0)
2610 {
58efb6c0 2611 /* Pre-indexed. */
252b5132
RH		 2612 if ((given & 0x00400000) == 0x00400000)
2613 {
58efb6c0 2614 /* Immediate. */
252b5132
RH		 2615 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2616 if (offset)
8e6446ff 2617 func (stream, ", #%s%d",
252b5132
RH		 2618 (((given & 0x00800000) == 0)
2619 ? "-" : ""), offset);
2620 }
2621 else
2622 {
58efb6c0 2623 /* Register. */
252b5132
RH		 2624 func (stream, ", %s%s",
2625 (((given & 0x00800000) == 0)
2626 ? "-" : ""),
2627 arm_regnames[given & 0xf]);
2628 }
2629
b34976b6 2630 func (stream, "]%s",
252b5132
RH		 2631 ((given & 0x00200000) != 0) ? "!" : "");
2632 }
2633 else
2634 {
58efb6c0 2635 /* Post-indexed. */
252b5132
RH		 2636 if ((given & 0x00400000) == 0x00400000)
2637 {
58efb6c0 2638 /* Immediate. */
252b5132
RH		 2639 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2640 if (offset)
8e6446ff 2641 func (stream, "], #%s%d",
252b5132
RH		 2642 (((given & 0x00800000) == 0)
2643 ? "-" : ""), offset);
b34976b6 2644 else
252b5132
RH		 2645 func (stream, "]");
2646 }
2647 else
2648 {
58efb6c0 2649 /* Register. */
252b5132
RH		 2650 func (stream, "], %s%s",
2651 (((given & 0x00800000) == 0)
2652 ? "-" : ""),
2653 arm_regnames[given & 0xf]);
2654 }
2655 }
2656 }
2657 break;
b34976b6 2658
252b5132 2659 case 'b':
6b5d3a4d
ZW		 2660 {
2661 int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
2662 info->print_address_func (disp*4 + pc + 8, info);
2663 }
252b5132
RH		 2664 break;
2665
2666 case 'c':
c22aaad1
PB		 2667 if (((given >> 28) & 0xf) != 0xe)
2668 func (stream, "%s",
2669 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 2670 break;
2671
2672 case 'm':
2673 {
2674 int started = 0;
2675 int reg;
2676
2677 func (stream, "{");
2678 for (reg = 0; reg < 16; reg++)
2679 if ((given & (1 << reg)) != 0)
2680 {
2681 if (started)
2682 func (stream, ", ");
2683 started = 1;
2684 func (stream, "%s", arm_regnames[reg]);
2685 }
2686 func (stream, "}");
2687 }
2688 break;
2689
2690 case 'o':
2691 if ((given & 0x02000000) != 0)
2692 {
2693 int rotate = (given & 0xf00) >> 7;
2694 int immed = (given & 0xff);
9f20bbfd
NC		 2695 immed = (((immed << (32 - rotate))
2696 | (immed >> rotate)) & 0xffffffff);
2697 func (stream, "#%d\t; 0x%x", immed, immed);
252b5132
RH		 2698 }
2699 else
2700 arm_decode_shift (given, func, stream);
2701 break;
2702
2703 case 'p':
2704 if ((given & 0x0000f000) == 0x0000f000)
2705 func (stream, "p");
2706 break;
2707
2708 case 't':
2709 if ((given & 0x01200000) == 0x00200000)
2710 func (stream, "t");
2711 break;
2712
252b5132
RH		 2713 case 'A':
2714 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa
NC		 2715
2716 if ((given & (1 << 24)) != 0)
252b5132
RH		 2717 {
2718 int offset = given & 0xff;
f02232aa 2719
252b5132 2720 if (offset)
8e6446ff 2721 func (stream, ", #%s%d]%s",
252b5132
RH		 2722 ((given & 0x00800000) == 0 ? "-" : ""),
2723 offset * 4,
2724 ((given & 0x00200000) != 0 ? "!" : ""));
2725 else
2726 func (stream, "]");
2727 }
2728 else
2729 {
2730 int offset = given & 0xff;
f02232aa
NC		 2731
2732 func (stream, "]");
2733
2734 if (given & (1 << 21))
2735 {
2736 if (offset)
8e6446ff 2737 func (stream, ", #%s%d",
f02232aa
NC		 2738 ((given & 0x00800000) == 0 ? "-" : ""),
2739 offset * 4);
2740 }
252b5132 2741 else
f02232aa 2742 func (stream, ", {%d}", offset);
252b5132
RH		 2743 }
2744 break;
2745
077b8428
NC		 2746 case 'B':
2747 /* Print ARM V5 BLX(1) address: pc+25 bits. */
2748 {
2749 bfd_vma address;
2750 bfd_vma offset = 0;
b34976b6 2751
077b8428
NC		 2752 if (given & 0x00800000)
2753 /* Is signed, hi bits should be ones. */
2754 offset = (-1) ^ 0x00ffffff;
2755
2756 /* Offset is (SignExtend(offset field)<<2). */
2757 offset += given & 0x00ffffff;
2758 offset <<= 2;
2759 address = offset + pc + 8;
b34976b6 2760
8f06b2d8
PB		 2761 if (given & 0x01000000)
2762 /* H bit allows addressing to 2-byte boundaries. */
2763 address += 2;
b1ee46c5 2764
8f06b2d8 2765 info->print_address_func (address, info);
b1ee46c5 2766 }
b1ee46c5
AH		 2767 break;
2768
252b5132 2769 case 'C':
6eeeb4b4
AO		 2770 func (stream, "_");
2771 if (given & 0x80000)
2772 func (stream, "f");
2773 if (given & 0x40000)
2774 func (stream, "s");
2775 if (given & 0x20000)
2776 func (stream, "x");
2777 if (given & 0x10000)
2778 func (stream, "c");
252b5132
RH		 2779 break;
2780
62b3e311
PB		 2781 case 'U':
2782 switch (given & 0xf)
2783 {
2784 case 0xf: func(stream, "sy"); break;
2785 case 0x7: func(stream, "un"); break;
2786 case 0xe: func(stream, "st"); break;
2787 case 0x6: func(stream, "unst"); break;
2788 default:
2789 func(stream, "#%d", (int)given & 0xf);
2790 break;
2791 }
2792 break;
2793
b34976b6 2794 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 2795 case '5': case '6': case '7': case '8': case '9':
2796 {
16980d0b
JB		 2797 int width;
2798 unsigned long value;
252b5132 2799
16980d0b
JB		 2800 c = arm_decode_bitfield (c, given, &value, &width);
2801
252b5132
RH		 2802 switch (*c)
2803 {
16980d0b
JB		 2804 case 'r':
2805 func (stream, "%s", arm_regnames[value]);
2806 break;
2807 case 'd':
2808 func (stream, "%ld", value);
2809 break;
2810 case 'b':
2811 func (stream, "%ld", value * 8);
2812 break;
2813 case 'W':
2814 func (stream, "%ld", value + 1);
2815 break;
2816 case 'x':
2817 func (stream, "0x%08lx", value);
2818
2819 /* Some SWI instructions have special
2820 meanings. */
2821 if ((given & 0x0fffffff) == 0x0FF00000)
2822 func (stream, "\t; IMB");
2823 else if ((given & 0x0fffffff) == 0x0FF00001)
2824 func (stream, "\t; IMBRange");
2825 break;
2826 case 'X':
2827 func (stream, "%01lx", value & 0xf);
252b5132
RH		 2828 break;
2829 case '`':
2830 c++;
16980d0b 2831 if (value == 0)
252b5132
RH		 2832 func (stream, "%c", *c);
2833 break;
2834 case '\'':
2835 c++;
16980d0b 2836 if (value == ((1ul << width) - 1))
252b5132
RH		 2837 func (stream, "%c", *c);
2838 break;
2839 case '?':
16980d0b
JB		 2840 func (stream, "%c", c[(1 << width) - (int)value]);
2841 c += 1 << width;
252b5132
RH		 2842 break;
2843 default:
2844 abort ();
2845 }
2846 break;
2847
0dd132b6
NC		 2848 case 'e':
2849 {
2850 int imm;
2851
2852 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
2853 func (stream, "%d", imm);
2854 }
2855 break;
2856
0a003adc
ZW		 2857 case 'E':
2858 /* LSB and WIDTH fields of BFI or BFC. The machine-
2859 language instruction encodes LSB and MSB. */
2860 {
2861 long msb = (given & 0x001f0000) >> 16;
2862 long lsb = (given & 0x00000f80) >> 7;
2863
2864 long width = msb - lsb + 1;
2865 if (width > 0)
2866 func (stream, "#%lu, #%lu", lsb, width);
2867 else
2868 func (stream, "(invalid: %lu:%lu)", lsb, msb);
2869 }
2870 break;
2871
2872 case 'V':
2873 /* 16-bit unsigned immediate from a MOVT or MOVW
2874 instruction, encoded in bits 0:11 and 15:19. */
2875 {
2876 long hi = (given & 0x000f0000) >> 4;
2877 long lo = (given & 0x00000fff);
2878 long imm16 = hi | lo;
2879 func (stream, "#%lu\t; 0x%lx", imm16, imm16);
2880 }
2881 break;
2882
252b5132
RH		 2883 default:
2884 abort ();
2885 }
2886 }
2887 }
2888 else
2889 func (stream, "%c", *c);
2890 }
4a5329c6 2891 return;
252b5132
RH		 2892 }
2893 }
2894 abort ();
2895}
2896
4a5329c6 2897/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 2898
4a5329c6
ZW		 2899static void
2900print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 2901{
6b5d3a4d 2902 const struct opcode16 *insn;
6a51a8a8
AM		 2903 void *stream = info->stream;
2904 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 2905
2906 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 2907 if ((given & insn->mask) == insn->value)
2908 {
6b5d3a4d 2909 const char *c = insn->assembler;
c19d1205
ZW		 2910 for (; *c; c++)
2911 {
2912 int domaskpc = 0;
2913 int domasklr = 0;
2914
2915 if (*c != '%')
2916 {
2917 func (stream, "%c", *c);
2918 continue;
2919 }
252b5132 2920
c19d1205
ZW		 2921 switch (*++c)
2922 {
2923 case '%':
2924 func (stream, "%%");
2925 break;
b34976b6 2926
c22aaad1
PB		 2927 case 'c':
2928 if (ifthen_state)
2929 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2930 break;
2931
2932 case 'C':
2933 if (ifthen_state)
2934 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2935 else
2936 func (stream, "s");
2937 break;
2938
2939 case 'I':
2940 {
2941 unsigned int tmp;
2942
2943 ifthen_next_state = given & 0xff;
2944 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
2945 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
2946 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
2947 }
2948 break;
2949
2950 case 'x':
2951 if (ifthen_next_state)
2952 func (stream, "\t; unpredictable branch in IT block\n");
2953 break;
2954
2955 case 'X':
2956 if (ifthen_state)
2957 func (stream, "\t; unpredictable <IT:%s>",
2958 arm_conditional[IFTHEN_COND]);
2959 break;
2960
c19d1205
ZW		 2961 case 'S':
2962 {
2963 long reg;
2964
2965 reg = (given >> 3) & 0x7;
2966 if (given & (1 << 6))
2967 reg += 8;
4f3c3dbb 2968
c19d1205
ZW		 2969 func (stream, "%s", arm_regnames[reg]);
2970 }
2971 break;
baf0cc5e 2972
c19d1205 2973 case 'D':
4f3c3dbb 2974 {
c19d1205
ZW		 2975 long reg;
2976
2977 reg = given & 0x7;
2978 if (given & (1 << 7))
2979 reg += 8;
2980
2981 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 2982 }
c19d1205
ZW		 2983 break;
2984
2985 case 'N':
2986 if (given & (1 << 8))
2987 domasklr = 1;
2988 /* Fall through. */
2989 case 'O':
2990 if (*c == 'O' && (given & (1 << 8)))
2991 domaskpc = 1;
2992 /* Fall through. */
2993 case 'M':
2994 {
2995 int started = 0;
2996 int reg;
2997
2998 func (stream, "{");
2999
3000 /* It would be nice if we could spot
3001 ranges, and generate the rS-rE format: */
3002 for (reg = 0; (reg < 8); reg++)
3003 if ((given & (1 << reg)) != 0)
3004 {
3005 if (started)
3006 func (stream, ", ");
3007 started = 1;
3008 func (stream, "%s", arm_regnames[reg]);
3009 }
3010
3011 if (domasklr)
3012 {
3013 if (started)
3014 func (stream, ", ");
3015 started = 1;
3016 func (stream, arm_regnames[14] /* "lr" */);
3017 }
3018
3019 if (domaskpc)
3020 {
3021 if (started)
3022 func (stream, ", ");
3023 func (stream, arm_regnames[15] /* "pc" */);
3024 }
3025
3026 func (stream, "}");
3027 }
3028 break;
3029
3030 case 'b':
3031 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3032 {
3033 bfd_vma address = (pc + 4
3034 + ((given & 0x00f8) >> 2)
3035 + ((given & 0x0200) >> 3));
3036 info->print_address_func (address, info);
3037 }
3038 break;
3039
3040 case 's':
3041 /* Right shift immediate -- bits 6..10; 1-31 print
3042 as themselves, 0 prints as 32. */
3043 {
3044 long imm = (given & 0x07c0) >> 6;
3045 if (imm == 0)
3046 imm = 32;
0fd3a477 3047 func (stream, "#%ld", imm);
c19d1205
ZW		 3048 }
3049 break;
3050
3051 case '0': case '1': case '2': case '3': case '4':
3052 case '5': case '6': case '7': case '8': case '9':
3053 {
3054 int bitstart = *c++ - '0';
3055 int bitend = 0;
3056
3057 while (*c >= '0' && *c <= '9')
3058 bitstart = (bitstart * 10) + *c++ - '0';
3059
3060 switch (*c)
3061 {
3062 case '-':
3063 {
3064 long reg;
3065
3066 c++;
3067 while (*c >= '0' && *c <= '9')
3068 bitend = (bitend * 10) + *c++ - '0';
3069 if (!bitend)
3070 abort ();
3071 reg = given >> bitstart;
3072 reg &= (2 << (bitend - bitstart)) - 1;
3073 switch (*c)
3074 {
3075 case 'r':
3076 func (stream, "%s", arm_regnames[reg]);
3077 break;
3078
3079 case 'd':
0fd3a477 3080 func (stream, "%ld", reg);
c19d1205
ZW		 3081 break;
3082
3083 case 'H':
0fd3a477 3084 func (stream, "%ld", reg << 1);
c19d1205
ZW		 3085 break;
3086
3087 case 'W':
0fd3a477 3088 func (stream, "%ld", reg << 2);
c19d1205
ZW		 3089 break;
3090
3091 case 'a':
3092 /* PC-relative address -- the bottom two
3093 bits of the address are dropped
3094 before the calculation. */
3095 info->print_address_func
3096 (((pc + 4) & ~3) + (reg << 2), info);
3097 break;
3098
3099 case 'x':
0fd3a477 3100 func (stream, "0x%04lx", reg);
c19d1205
ZW		 3101 break;
3102
c19d1205
ZW		 3103 case 'B':
3104 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 3105 info->print_address_func (reg * 2 + pc + 4, info);
c19d1205
ZW		 3106 break;
3107
3108 case 'c':
c22aaad1 3109 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 3110 break;
3111
3112 default:
3113 abort ();
3114 }
3115 }
3116 break;
3117
3118 case '\'':
3119 c++;
3120 if ((given & (1 << bitstart)) != 0)
3121 func (stream, "%c", *c);
3122 break;
3123
3124 case '?':
3125 ++c;
3126 if ((given & (1 << bitstart)) != 0)
3127 func (stream, "%c", *c++);
3128 else
3129 func (stream, "%c", *++c);
3130 break;
3131
3132 default:
3133 abort ();
3134 }
3135 }
3136 break;
3137
3138 default:
3139 abort ();
3140 }
3141 }
4a5329c6 3142 return;
c19d1205
ZW		 3143 }
3144
3145 /* No match. */
3146 abort ();
3147}
3148
62b3e311
PB		 3149/* Return the name of an V7M special register. */
3150static const char *
3151psr_name (int regno)
3152{
3153 switch (regno)
3154 {
3155 case 0: return "APSR";
3156 case 1: return "IAPSR";
3157 case 2: return "EAPSR";
3158 case 3: return "PSR";
3159 case 5: return "IPSR";
3160 case 6: return "EPSR";
3161 case 7: return "IEPSR";
3162 case 8: return "MSP";
3163 case 9: return "PSP";
3164 case 16: return "PRIMASK";
3165 case 17: return "BASEPRI";
3166 case 18: return "BASEPRI_MASK";
3167 case 19: return "FAULTMASK";
3168 case 20: return "CONTROL";
3169 default: return "<unknown>";
3170 }
3171}
3172
4a5329c6
ZW		 3173/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3174
3175static void
3176print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 3177{
6b5d3a4d 3178 const struct opcode32 *insn;
c19d1205
ZW		 3179 void *stream = info->stream;
3180 fprintf_ftype func = info->fprintf_func;
3181
16980d0b
JB		 3182 if (print_insn_coprocessor (pc, info, given, TRUE))
3183 return;
3184
3185 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 3186 return;
3187
c19d1205
ZW		 3188 for (insn = thumb32_opcodes; insn->assembler; insn++)
3189 if ((given & insn->mask) == insn->value)
3190 {
6b5d3a4d 3191 const char *c = insn->assembler;
c19d1205
ZW		 3192 for (; *c; c++)
3193 {
3194 if (*c != '%')
3195 {
3196 func (stream, "%c", *c);
3197 continue;
3198 }
3199
3200 switch (*++c)
3201 {
3202 case '%':
3203 func (stream, "%%");
3204 break;
3205
c22aaad1
PB		 3206 case 'c':
3207 if (ifthen_state)
3208 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3209 break;
3210
3211 case 'x':
3212 if (ifthen_next_state)
3213 func (stream, "\t; unpredictable branch in IT block\n");
3214 break;
3215
3216 case 'X':
3217 if (ifthen_state)
3218 func (stream, "\t; unpredictable <IT:%s>",
3219 arm_conditional[IFTHEN_COND]);
3220 break;
3221
c19d1205
ZW		 3222 case 'I':
3223 {
3224 unsigned int imm12 = 0;
3225 imm12 |= (given & 0x000000ffu);
3226 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 3227 imm12 |= (given & 0x04000000u) >> 15;
c19d1205
ZW		 3228 func (stream, "#%u\t; 0x%x", imm12, imm12);
3229 }
3230 break;
3231
3232 case 'M':
3233 {
3234 unsigned int bits = 0, imm, imm8, mod;
3235 bits |= (given & 0x000000ffu);
3236 bits |= (given & 0x00007000u) >> 4;
3237 bits |= (given & 0x04000000u) >> 15;
3238 imm8 = (bits & 0x0ff);
3239 mod = (bits & 0xf00) >> 8;
3240 switch (mod)
3241 {
3242 case 0: imm = imm8; break;
3243 case 1: imm = ((imm8<<16) | imm8); break;
3244 case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
3245 case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3246 default:
3247 mod = (bits & 0xf80) >> 7;
3248 imm8 = (bits & 0x07f) | 0x80;
3249 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3250 }
3251 func (stream, "#%u\t; 0x%x", imm, imm);
3252 }
3253 break;
3254
3255 case 'J':
3256 {
3257 unsigned int imm = 0;
3258 imm |= (given & 0x000000ffu);
3259 imm |= (given & 0x00007000u) >> 4;
3260 imm |= (given & 0x04000000u) >> 15;
3261 imm |= (given & 0x000f0000u) >> 4;
3262 func (stream, "#%u\t; 0x%x", imm, imm);
3263 }
3264 break;
3265
3266 case 'K':
3267 {
3268 unsigned int imm = 0;
3269 imm |= (given & 0x000f0000u) >> 16;
3270 imm |= (given & 0x00000ff0u) >> 0;
3271 imm |= (given & 0x0000000fu) << 12;
3272 func (stream, "#%u\t; 0x%x", imm, imm);
3273 }
3274 break;
3275
3276 case 'S':
3277 {
3278 unsigned int reg = (given & 0x0000000fu);
3279 unsigned int stp = (given & 0x00000030u) >> 4;
3280 unsigned int imm = 0;
3281 imm |= (given & 0x000000c0u) >> 6;
3282 imm |= (given & 0x00007000u) >> 10;
3283
3284 func (stream, "%s", arm_regnames[reg]);
3285 switch (stp)
3286 {
3287 case 0:
3288 if (imm > 0)
3289 func (stream, ", lsl #%u", imm);
3290 break;
3291
3292 case 1:
3293 if (imm == 0)
3294 imm = 32;
3295 func (stream, ", lsr #%u", imm);
3296 break;
3297
3298 case 2:
3299 if (imm == 0)
3300 imm = 32;
3301 func (stream, ", asr #%u", imm);
3302 break;
3303
3304 case 3:
3305 if (imm == 0)
3306 func (stream, ", rrx");
3307 else
3308 func (stream, ", ror #%u", imm);
3309 }
3310 }
3311 break;
3312
3313 case 'a':
3314 {
3315 unsigned int Rn = (given & 0x000f0000) >> 16;
3316 unsigned int U = (given & 0x00800000) >> 23;
3317 unsigned int op = (given & 0x00000f00) >> 8;
3318 unsigned int i12 = (given & 0x00000fff);
3319 unsigned int i8 = (given & 0x000000ff);
3320 bfd_boolean writeback = FALSE, postind = FALSE;
3321 int offset = 0;
3322
3323 func (stream, "[%s", arm_regnames[Rn]);
3324 if (U) /* 12-bit positive immediate offset */
3325 offset = i12;
3326 else if (Rn == 15) /* 12-bit negative immediate offset */
3327 offset = -(int)i12;
3328 else if (op == 0x0) /* shifted register offset */
3329 {
3330 unsigned int Rm = (i8 & 0x0f);
3331 unsigned int sh = (i8 & 0x30) >> 4;
3332 func (stream, ", %s", arm_regnames[Rm]);
3333 if (sh)
3334 func (stream, ", lsl #%u", sh);
3335 func (stream, "]");
3336 break;
3337 }
3338 else switch (op)
3339 {
3340 case 0xE: /* 8-bit positive immediate offset */
3341 offset = i8;
3342 break;
3343
3344 case 0xC: /* 8-bit negative immediate offset */
3345 offset = -i8;
3346 break;
3347
e9f89963 3348 case 0xF: /* 8-bit + preindex with wb */
c19d1205
ZW		 3349 offset = i8;
3350 writeback = TRUE;
3351 break;
3352
e9f89963 3353 case 0xD: /* 8-bit - preindex with wb */
c19d1205
ZW		 3354 offset = -i8;
3355 writeback = TRUE;
3356 break;
3357
e9f89963 3358 case 0xB: /* 8-bit + postindex */
c19d1205
ZW		 3359 offset = i8;
3360 postind = TRUE;
3361 break;
3362
e9f89963 3363 case 0x9: /* 8-bit - postindex */
c19d1205
ZW		 3364 offset = -i8;
3365 postind = TRUE;
3366 break;
3367
3368 default:
3369 func (stream, ", <undefined>]");
3370 goto skip;
3371 }
3372
3373 if (postind)
3374 func (stream, "], #%d", offset);
3375 else
3376 {
3377 if (offset)
3378 func (stream, ", #%d", offset);
3379 func (stream, writeback ? "]!" : "]");
3380 }
3381
3382 if (Rn == 15)
3383 {
3384 func (stream, "\t; ");
3385 info->print_address_func (((pc + 4) & ~3) + offset, info);
3386 }
3387 }
3388 skip:
3389 break;
3390
3391 case 'A':
3392 {
3393 unsigned int P = (given & 0x01000000) >> 24;
3394 unsigned int U = (given & 0x00800000) >> 23;
3395 unsigned int W = (given & 0x00400000) >> 21;
3396 unsigned int Rn = (given & 0x000f0000) >> 16;
3397 unsigned int off = (given & 0x000000ff);
3398
3399 func (stream, "[%s", arm_regnames[Rn]);
3400 if (P)
3401 {
3402 if (off || !U)
3403 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
3404 func (stream, "]");
3405 if (W)
3406 func (stream, "!");
3407 }
3408 else
3409 {
3410 func (stream, "], ");
3411 if (W)
3412 func (stream, "#%c%u", U ? '+' : '-', off * 4);
3413 else
3414 func (stream, "{%u}", off);
3415 }
3416 }
3417 break;
3418
3419 case 'w':
3420 {
3421 unsigned int Sbit = (given & 0x01000000) >> 24;
3422 unsigned int type = (given & 0x00600000) >> 21;
3423 switch (type)
3424 {
3425 case 0: func (stream, Sbit ? "sb" : "b"); break;
3426 case 1: func (stream, Sbit ? "sh" : "h"); break;
3427 case 2:
3428 if (Sbit)
3429 func (stream, "??");
3430 break;
3431 case 3:
3432 func (stream, "??");
3433 break;
3434 }
3435 }
3436 break;
3437
3438 case 'm':
3439 {
3440 int started = 0;
3441 int reg;
3442
3443 func (stream, "{");
3444 for (reg = 0; reg < 16; reg++)
3445 if ((given & (1 << reg)) != 0)
3446 {
3447 if (started)
3448 func (stream, ", ");
3449 started = 1;
3450 func (stream, "%s", arm_regnames[reg]);
3451 }
3452 func (stream, "}");
3453 }
3454 break;
3455
3456 case 'E':
3457 {
3458 unsigned int msb = (given & 0x0000001f);
3459 unsigned int lsb = 0;
3460 lsb |= (given & 0x000000c0u) >> 6;
3461 lsb |= (given & 0x00007000u) >> 10;
3462 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
3463 }
3464 break;
3465
3466 case 'F':
3467 {
3468 unsigned int width = (given & 0x0000001f) + 1;
3469 unsigned int lsb = 0;
3470 lsb |= (given & 0x000000c0u) >> 6;
3471 lsb |= (given & 0x00007000u) >> 10;
3472 func (stream, "#%u, #%u", lsb, width);
3473 }
3474 break;
3475
3476 case 'b':
3477 {
3478 unsigned int S = (given & 0x04000000u) >> 26;
3479 unsigned int J1 = (given & 0x00002000u) >> 13;
3480 unsigned int J2 = (given & 0x00000800u) >> 11;
3481 int offset = 0;
3482
3483 offset |= !S << 20;
3484 offset |= J2 << 19;
3485 offset |= J1 << 18;
3486 offset |= (given & 0x003f0000) >> 4;
3487 offset |= (given & 0x000007ff) << 1;
3488 offset -= (1 << 20);
3489
3490 info->print_address_func (pc + 4 + offset, info);
3491 }
3492 break;
3493
3494 case 'B':
3495 {
3496 unsigned int S = (given & 0x04000000u) >> 26;
3497 unsigned int I1 = (given & 0x00002000u) >> 13;
3498 unsigned int I2 = (given & 0x00000800u) >> 11;
3499 int offset = 0;
3500
3501 offset |= !S << 24;
3502 offset |= !(I1 ^ S) << 23;
3503 offset |= !(I2 ^ S) << 22;
3504 offset |= (given & 0x03ff0000u) >> 4;
3505 offset |= (given & 0x000007ffu) << 1;
3506 offset -= (1 << 24);
36b0c57d 3507 offset += pc + 4;
c19d1205 3508
36b0c57d
PB		 3509 /* BLX target addresses are always word aligned. */
3510 if ((given & 0x00001000u) == 0)
3511 offset &= ~2u;
3512
3513 info->print_address_func (offset, info);
c19d1205
ZW		 3514 }
3515 break;
3516
3517 case 's':
3518 {
3519 unsigned int shift = 0;
3520 shift |= (given & 0x000000c0u) >> 6;
3521 shift |= (given & 0x00007000u) >> 10;
3522 if (given & 0x00200000u)
3523 func (stream, ", asr #%u", shift);
3524 else if (shift)
3525 func (stream, ", lsl #%u", shift);
3526 /* else print nothing - lsl #0 */
3527 }
3528 break;
3529
3530 case 'R':
3531 {
3532 unsigned int rot = (given & 0x00000030) >> 4;
3533 if (rot)
3534 func (stream, ", ror #%u", rot * 8);
3535 }
3536 break;
3537
62b3e311
PB		 3538 case 'U':
3539 switch (given & 0xf)
3540 {
3541 case 0xf: func(stream, "sy"); break;
3542 case 0x7: func(stream, "un"); break;
3543 case 0xe: func(stream, "st"); break;
3544 case 0x6: func(stream, "unst"); break;
3545 default:
3546 func(stream, "#%d", (int)given & 0xf);
3547 break;
3548 }
3549 break;
3550
3551 case 'C':
3552 if ((given & 0xff) == 0)
3553 {
3554 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
3555 if (given & 0x800)
3556 func (stream, "f");
3557 if (given & 0x400)
3558 func (stream, "s");
3559 if (given & 0x200)
3560 func (stream, "x");
3561 if (given & 0x100)
3562 func (stream, "c");
3563 }
3564 else
3565 {
3566 func (stream, psr_name (given & 0xff));
3567 }
3568 break;
3569
3570 case 'D':
3571 if ((given & 0xff) == 0)
3572 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
3573 else
3574 func (stream, psr_name (given & 0xff));
3575 break;
3576
c19d1205
ZW		 3577 case '0': case '1': case '2': case '3': case '4':
3578 case '5': case '6': case '7': case '8': case '9':
3579 {
16980d0b
JB		 3580 int width;
3581 unsigned long val;
c19d1205 3582
16980d0b
JB		 3583 c = arm_decode_bitfield (c, given, &val, &width);
3584
c19d1205
ZW		 3585 switch (*c)
3586 {
16980d0b
JB		 3587 case 'd': func (stream, "%lu", val); break;
3588 case 'W': func (stream, "%lu", val * 4); break;
c19d1205
ZW		 3589 case 'r': func (stream, "%s", arm_regnames[val]); break;
3590
3591 case 'c':
c22aaad1 3592 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 3593 break;
3594
3595 case '\'':
c19d1205 3596 c++;
16980d0b
JB		 3597 if (val == ((1ul << width) - 1))
3598 func (stream, "%c", *c);
c19d1205
ZW		 3599 break;
3600
3601 case '`':
c19d1205 3602 c++;
16980d0b
JB		 3603 if (val == 0)
3604 func (stream, "%c", *c);
c19d1205
ZW		 3605 break;
3606
3607 case '?':
16980d0b
JB		 3608 func (stream, "%c", c[(1 << width) - (int)val]);
3609 c += 1 << width;
c19d1205
ZW		 3610 break;
3611
3612 default:
3613 abort ();
3614 }
3615 }
3616 break;
3617
3618 default:
3619 abort ();
3620 }
3621 }
4a5329c6 3622 return;
c19d1205 3623 }
252b5132 3624
58efb6c0 3625 /* No match. */
252b5132
RH		 3626 abort ();
3627}
3628
22a398e1
NC		 3629/* Disallow mapping symbols ($a, $b, $d, $t etc) from
3630 being displayed in symbol relative addresses. */
3631
3632bfd_boolean
3633arm_symbol_is_valid (asymbol * sym,
3634 struct disassemble_info * info ATTRIBUTE_UNUSED)
3635{
3636 const char * name;
3637
3638 if (sym == NULL)
3639 return FALSE;
3640
3641 name = bfd_asymbol_name (sym);
3642
3643 return (name && *name != '$');
3644}
3645
58efb6c0 3646/* Parse an individual disassembler option. */
baf0cc5e 3647
a3d9c82d 3648void
4a5329c6 3649parse_arm_disassembler_option (char *option)
dd92f639 3650{
01c7f630 3651 if (option == NULL)
dd92f639 3652 return;
b34976b6 3653
01c7f630 3654 if (strneq (option, "reg-names-", 10))
dd92f639 3655 {
58efb6c0 3656 int i;
b34976b6 3657
01c7f630 3658 option += 10;
58efb6c0
NC		 3659
3660 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 3661 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 3662 {
3663 regname_selected = i;
3664 break;
3665 }
b34976b6 3666
58efb6c0 3667 if (i < 0)
31e0f3cd 3668 /* XXX - should break 'option' at following delimiter. */
58efb6c0 3669 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 3670 }
31e0f3cd 3671 else if (strneq (option, "force-thumb", 11))
01c7f630 3672 force_thumb = 1;
31e0f3cd 3673 else if (strneq (option, "no-force-thumb", 14))
01c7f630 3674 force_thumb = 0;
dd92f639 3675 else
31e0f3cd 3676 /* XXX - should break 'option' at following delimiter. */
58efb6c0 3677 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 3678
dd92f639
NC		 3679 return;
3680}
3681
31e0f3cd
NC		 3682/* Parse the string of disassembler options, spliting it at whitespaces
3683 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 3684
01c7f630 3685static void
4a5329c6 3686parse_disassembler_options (char *options)
01c7f630 3687{
01c7f630
NC		 3688 if (options == NULL)
3689 return;
3690
31e0f3cd 3691 while (*options)
01c7f630 3692 {
31e0f3cd
NC		 3693 parse_arm_disassembler_option (options);
3694
3695 /* Skip forward to next seperator. */
3696 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
3697 ++ options;
3698 /* Skip forward past seperators. */
3699 while (ISSPACE (*options) || (*options == ','))
3700 ++ options;
01c7f630 3701 }
01c7f630
NC		 3702}
3703
c22aaad1
PB		 3704/* Search back through the insn stream to determine if this instruction is
3705 conditionally executed. */
3706static void
3707find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
3708 bfd_boolean little)
3709{
3710 unsigned char b[2];
3711 unsigned int insn;
3712 int status;
3713 /* COUNT is twice the number of instructions seen. It will be odd if we
3714 just crossed an instruction boundary. */
3715 int count;
3716 int it_count;
3717 unsigned int seen_it;
3718 bfd_vma addr;
3719
3720 ifthen_address = pc;
3721 ifthen_state = 0;
3722
3723 addr = pc;
3724 count = 1;
3725 it_count = 0;
3726 seen_it = 0;
3727 /* Scan backwards looking for IT instructions, keeping track of where
3728 instruction boundaries are. We don't know if something is actually an
3729 IT instruction until we find a definite instruction boundary. */
3730 for (;;)
3731 {
3732 if (addr == 0 || info->symbol_at_address_func(addr, info))
3733 {
3734 /* A symbol must be on an instruction boundary, and will not
3735 be within an IT block. */
3736 if (seen_it && (count & 1))
3737 break;
3738
3739 return;
3740 }
3741 addr -= 2;
3742 status = info->read_memory_func (addr, (bfd_byte *)b, 2, info);
3743 if (status)
3744 return;
3745
3746 if (little)
3747 insn = (b[0]) | (b[1] << 8);
3748 else
3749 insn = (b[1]) | (b[0] << 8);
3750 if (seen_it)
3751 {
3752 if ((insn & 0xf800) < 0xe800)
3753 {
3754 /* Addr + 2 is an instruction boundary. See if this matches
3755 the expected boundary based on the position of the last
3756 IT candidate. */
3757 if (count & 1)
3758 break;
3759 seen_it = 0;
3760 }
3761 }
3762 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
3763 {
3764 /* This could be an IT instruction. */
3765 seen_it = insn;
3766 it_count = count >> 1;
3767 }
3768 if ((insn & 0xf800) >= 0xe800)
3769 count++;
3770 else
3771 count = (count + 2) | 1;
3772 /* IT blocks contain at most 4 instructions. */
3773 if (count >= 8 && !seen_it)
3774 return;
3775 }
3776 /* We found an IT instruction. */
3777 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
3778 if ((ifthen_state & 0xf) == 0)
3779 ifthen_state = 0;
3780}
3781
58efb6c0
NC		 3782/* NOTE: There are no checks in these routines that
3783 the relevant number of data bytes exist. */
baf0cc5e 3784
58efb6c0 3785static int
4a5329c6 3786print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 3787{
c19d1205
ZW		 3788 unsigned char b[4];
3789 long given;
3790 int status;
3791 int is_thumb;
4a5329c6
ZW		 3792 int size;
3793 void (*printer) (bfd_vma, struct disassemble_info *, long);
58efb6c0 3794
dd92f639
NC		 3795 if (info->disassembler_options)
3796 {
3797 parse_disassembler_options (info->disassembler_options);
b34976b6 3798
58efb6c0 3799 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 3800 info->disassembler_options = NULL;
3801 }
b34976b6 3802
01c7f630 3803 is_thumb = force_thumb;
b34976b6 3804
01c7f630 3805 if (!is_thumb && info->symbols != NULL)
252b5132 3806 {
5876e06d
NC		 3807 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
3808 {
2f0ca46a 3809 coff_symbol_type * cs;
b34976b6 3810
5876e06d
NC		 3811 cs = coffsymbol (*info->symbols);
3812 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
3813 || cs->native->u.syment.n_sclass == C_THUMBSTAT
3814 || cs->native->u.syment.n_sclass == C_THUMBLABEL
3815 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
3816 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
3817 }
3818 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
3819 {
2f0ca46a 3820 elf_symbol_type * es;
58efb6c0 3821 unsigned int type;
b34976b6 3822
5876e06d 3823 es = *(elf_symbol_type **)(info->symbols);
58efb6c0 3824 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
b34976b6 3825
58efb6c0 3826 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
5876e06d
NC		 3827 }
3828 }
b34976b6 3829
58efb6c0 3830 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
c19d1205 3831 info->bytes_per_line = 4;
252b5132 3832
c19d1205 3833 if (!is_thumb)
252b5132 3834 {
c19d1205
ZW		 3835 /* In ARM mode endianness is a straightforward issue: the instruction
3836 is four bytes long and is either ordered 0123 or 3210. */
3837 printer = print_insn_arm;
3838 info->bytes_per_chunk = 4;
4a5329c6 3839 size = 4;
c19d1205
ZW		 3840
3841 status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
3842 if (little)
3843 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
3844 else
3845 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 3846 }
58efb6c0 3847 else
252b5132 3848 {
c19d1205
ZW		 3849 /* In Thumb mode we have the additional wrinkle of two
3850 instruction lengths. Fortunately, the bits that determine
3851 the length of the current instruction are always to be found
3852 in the first two bytes. */
4a5329c6 3853 printer = print_insn_thumb16;
c19d1205 3854 info->bytes_per_chunk = 2;
4a5329c6
ZW		 3855 size = 2;
3856
c19d1205 3857 status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
9a2ff3f5
AM		 3858 if (little)
3859 given = (b[0]) | (b[1] << 8);
3860 else
3861 given = (b[1]) | (b[0] << 8);
3862
c19d1205 3863 if (!status)
252b5132 3864 {
c19d1205
ZW		 3865 /* These bit patterns signal a four-byte Thumb
3866 instruction. */
3867 if ((given & 0xF800) == 0xF800
3868 || (given & 0xF800) == 0xF000
3869 || (given & 0xF800) == 0xE800)
252b5132 3870 {
c19d1205
ZW		 3871 status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
3872 if (little)
3873 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 3874 else
c19d1205
ZW		 3875 given = (b[1]) | (b[0] << 8) | (given << 16);
3876
3877 printer = print_insn_thumb32;
4a5329c6 3878 size = 4;
252b5132 3879 }
252b5132 3880 }
c22aaad1
PB		 3881
3882 if (ifthen_address != pc)
3883 find_ifthen_state(pc, info, little);
3884
3885 if (ifthen_state)
3886 {
3887 if ((ifthen_state & 0xf) == 0x8)
3888 ifthen_next_state = 0;
3889 else
3890 ifthen_next_state = (ifthen_state & 0xe0)
3891 | ((ifthen_state & 0xf) << 1);
3892 }
252b5132 3893 }
b34976b6 3894
c19d1205
ZW		 3895 if (status)
3896 {
3897 info->memory_error_func (status, pc, info);
3898 return -1;
3899 }
6a56ec7e
NC		 3900 if (info->flags & INSN_HAS_RELOC)
3901 /* If the instruction has a reloc associated with it, then
3902 the offset field in the instruction will actually be the
3903 addend for the reloc. (We are using REL type relocs).
3904 In such cases, we can ignore the pc when computing
3905 addresses, since the addend is not currently pc-relative. */
3906 pc = 0;
b34976b6 3907
4a5329c6 3908 printer (pc, info, given);
c22aaad1
PB		 3909
3910 if (is_thumb)
3911 {
3912 ifthen_state = ifthen_next_state;
3913 ifthen_address += size;
3914 }
4a5329c6 3915 return size;
252b5132
RH		 3916}
3917
3918int
4a5329c6 3919print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 3920{
b34976b6 3921 return print_insn (pc, info, FALSE);
58efb6c0 3922}
01c7f630 3923
58efb6c0 3924int
4a5329c6 3925print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 3926{
b34976b6 3927 return print_insn (pc, info, TRUE);
58efb6c0 3928}
252b5132 3929
58efb6c0 3930void
4a5329c6 3931print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 3932{
3933 int i;
252b5132 3934
58efb6c0
NC		 3935 fprintf (stream, _("\n\
3936The following ARM specific disassembler options are supported for use with\n\
3937the -M switch:\n"));
b34976b6 3938
58efb6c0
NC		 3939 for (i = NUM_ARM_REGNAMES; i--;)
3940 fprintf (stream, " reg-names-%s %*c%s\n",
3941 regnames[i].name,
d5b2f4d6 3942 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 3943 regnames[i].description);
3944
3945 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
3946 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
252b5132 3947}
GDB Binutils - Deliverables
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