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* armemu.c (ARMul_Emulate): Compute writeback value before
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
01c7f630 2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6This file is part of libopcodes.
7
8This program is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2 of the License, or (at your option)
11any later version.
12
13This program is distributed in the hope that it will be useful, but WITHOUT
14ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16more details.
17
18You should have received a copy of the GNU General Public License
19along with this program; if not, write to the Free Software
20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
cb6a5892 22#include "sysdep.h"
252b5132
RH		 23#include "dis-asm.h"
24#define DEFINE_TABLE
25#include "arm-opc.h"
26#include "coff/internal.h"
27#include "libcoff.h"
28#include "opintl.h"
29
30/* FIXME: This shouldn't be done here */
31#include "elf-bfd.h"
32#include "elf/internal.h"
33#include "elf/arm.h"
34
01c7f630 35#ifndef streq
58efb6c0 36#define streq(a,b) (strcmp ((a), (b)) == 0)
01c7f630 37#endif
58efb6c0 38
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
5876e06d 47static char * arm_conditional[] =
252b5132
RH		 48{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
50
58efb6c0
NC		 51typedef struct
52{
53 const char * name;
54 const char * description;
55 const char * reg_names[16];
56}
57arm_regname;
dd92f639 58
58efb6c0
NC		 59static arm_regname regnames[] =
60{
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
7c03c75e
SB		 63 { "gcc", "Select register names used by GCC",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
58efb6c0
NC		 65 { "std", "Select register names used in ARM's ISA documentation",
66 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
67 { "apcs", "Select register names used in the APCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
69 { "atpcs", "Select register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
a7f8487e 71 { "special-atpcs", "Select special register names used in the ATPCS",
58efb6c0
NC		 72 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
73};
74
7c03c75e 75/* Default to GCC register name set. */
58efb6c0
NC		 76static unsigned int regname_selected = 1;
77
78#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
79#define arm_regnames regnames[regname_selected].reg_names
252b5132 80
01c7f630
NC		 81static boolean force_thumb = false;
82
5876e06d 83static char * arm_fp_const[] =
252b5132
RH		 84{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
85
5876e06d 86static char * arm_shift[] =
252b5132 87{"lsl", "lsr", "asr", "ror"};
01c7f630
NC		 88\f
89/* Forward declarations. */
90static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
91static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
92static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
01c7f630 93static void parse_disassembler_options PARAMS ((char *));
58efb6c0 94static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
a7f8487e
FN		 95int get_arm_regname_num_options (void);
96int set_arm_regname_option (int option);
97int get_arm_regnames (int option, const char **setname,
98 const char **setdescription,
99 const char ***register_names);
01c7f630
NC		 100\f
101/* Functions. */
a7f8487e
FN		 102int
103get_arm_regname_num_options (void)
104{
105 return NUM_ARM_REGNAMES;
106}
107
108int
109set_arm_regname_option (int option)
110{
111 int old = regname_selected;
112 regname_selected = option;
113 return old;
114}
115
116int
117get_arm_regnames (int option, const char **setname,
118 const char **setdescription,
119 const char ***register_names)
120{
121 *setname = regnames[option].name;
122 *setdescription = regnames[option].description;
123 *register_names = regnames[option].reg_names;
124 return 16;
125}
126
252b5132
RH		 127static void
128arm_decode_shift (given, func, stream)
129 long given;
130 fprintf_ftype func;
5876e06d 131 void * stream;
252b5132
RH		 132{
133 func (stream, "%s", arm_regnames[given & 0xf]);
5876e06d 134
252b5132
RH		 135 if ((given & 0xff0) != 0)
136 {
137 if ((given & 0x10) == 0)
138 {
139 int amount = (given & 0xf80) >> 7;
140 int shift = (given & 0x60) >> 5;
5876e06d 141
252b5132
RH		 142 if (amount == 0)
143 {
144 if (shift == 3)
145 {
146 func (stream, ", rrx");
147 return;
148 }
5876e06d 149
252b5132
RH		 150 amount = 32;
151 }
5876e06d 152
252b5132
RH		 153 func (stream, ", %s #%d", arm_shift[shift], amount);
154 }
155 else
156 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
157 arm_regnames[(given & 0xf00) >> 8]);
158 }
159}
160
161/* Print one instruction from PC on INFO->STREAM.
162 Return the size of the instruction (always 4 on ARM). */
252b5132
RH		 163static int
164print_insn_arm (pc, info, given)
5876e06d
NC		 165 bfd_vma pc;
166 struct disassemble_info * info;
167 long given;
252b5132
RH		 168{
169 struct arm_opcode * insn;
170 void * stream = info->stream;
171 fprintf_ftype func = info->fprintf_func;
172
173 for (insn = arm_opcodes; insn->assembler; insn++)
174 {
175 if ((given & insn->mask) == insn->value)
176 {
177 char * c;
178
179 for (c = insn->assembler; *c; c++)
180 {
181 if (*c == '%')
182 {
183 switch (*++c)
184 {
185 case '%':
186 func (stream, "%%");
187 break;
188
189 case 'a':
190 if (((given & 0x000f0000) == 0x000f0000)
191 && ((given & 0x02000000) == 0))
192 {
193 int offset = given & 0xfff;
194
195 func (stream, "[pc");
196
197 if (given & 0x01000000)
198 {
199 if ((given & 0x00800000) == 0)
200 offset = - offset;
201
202 /* pre-indexed */
203 func (stream, ", #%x]", offset);
204
205 offset += pc + 8;
206
58efb6c0
NC		 207 /* Cope with the possibility of write-back
208 being used. Probably a very dangerous thing
209 for the programmer to do, but who are we to
210 argue ? */
252b5132
RH		 211 if (given & 0x00200000)
212 func (stream, "!");
213 }
214 else
215 {
58efb6c0 216 /* Post indexed. */
252b5132
RH		 217 func (stream, "], #%x", offset);
218
58efb6c0 219 offset = pc + 8; /* ie ignore the offset. */
252b5132
RH		 220 }
221
222 func (stream, "\t; ");
223 info->print_address_func (offset, info);
224 }
225 else
226 {
227 func (stream, "[%s",
228 arm_regnames[(given >> 16) & 0xf]);
229 if ((given & 0x01000000) != 0)
230 {
231 if ((given & 0x02000000) == 0)
232 {
233 int offset = given & 0xfff;
234 if (offset)
235 func (stream, ", %s#%d",
236 (((given & 0x00800000) == 0)
237 ? "-" : ""), offset);
238 }
239 else
240 {
241 func (stream, ", %s",
242 (((given & 0x00800000) == 0)
243 ? "-" : ""));
244 arm_decode_shift (given, func, stream);
245 }
246
247 func (stream, "]%s",
248 ((given & 0x00200000) != 0) ? "!" : "");
249 }
250 else
251 {
252 if ((given & 0x02000000) == 0)
253 {
254 int offset = given & 0xfff;
255 if (offset)
256 func (stream, "], %s#%d",
257 (((given & 0x00800000) == 0)
258 ? "-" : ""), offset);
259 else
260 func (stream, "]");
261 }
262 else
263 {
264 func (stream, "], %s",
265 (((given & 0x00800000) == 0)
266 ? "-" : ""));
267 arm_decode_shift (given, func, stream);
268 }
269 }
270 }
271 break;
272
273 case 's':
274 if ((given & 0x004f0000) == 0x004f0000)
275 {
58efb6c0 276 /* PC relative with immediate offset. */
252b5132 277 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
886796f9 278
252b5132
RH		 279 if ((given & 0x00800000) == 0)
280 offset = -offset;
886796f9
NC		 281
282 func (stream, "[pc, #%x]\t; ", offset);
283
252b5132
RH		 284 (*info->print_address_func)
285 (offset + pc + 8, info);
286 }
287 else
288 {
289 func (stream, "[%s",
290 arm_regnames[(given >> 16) & 0xf]);
291 if ((given & 0x01000000) != 0)
292 {
58efb6c0 293 /* Pre-indexed. */
252b5132
RH		 294 if ((given & 0x00400000) == 0x00400000)
295 {
58efb6c0 296 /* Immediate. */
252b5132
RH		 297 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
298 if (offset)
299 func (stream, ", %s#%d",
300 (((given & 0x00800000) == 0)
301 ? "-" : ""), offset);
302 }
303 else
304 {
58efb6c0 305 /* Register. */
252b5132
RH		 306 func (stream, ", %s%s",
307 (((given & 0x00800000) == 0)
308 ? "-" : ""),
309 arm_regnames[given & 0xf]);
310 }
311
312 func (stream, "]%s",
313 ((given & 0x00200000) != 0) ? "!" : "");
314 }
315 else
316 {
58efb6c0 317 /* Post-indexed. */
252b5132
RH		 318 if ((given & 0x00400000) == 0x00400000)
319 {
58efb6c0 320 /* Immediate. */
252b5132
RH		 321 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
322 if (offset)
323 func (stream, "], %s#%d",
324 (((given & 0x00800000) == 0)
325 ? "-" : ""), offset);
326 else
327 func (stream, "]");
328 }
329 else
330 {
58efb6c0 331 /* Register. */
252b5132
RH		 332 func (stream, "], %s%s",
333 (((given & 0x00800000) == 0)
334 ? "-" : ""),
335 arm_regnames[given & 0xf]);
336 }
337 }
338 }
339 break;
340
341 case 'b':
342 (*info->print_address_func)
343 (BDISP (given) * 4 + pc + 8, info);
344 break;
345
346 case 'c':
347 func (stream, "%s",
348 arm_conditional [(given >> 28) & 0xf]);
349 break;
350
351 case 'm':
352 {
353 int started = 0;
354 int reg;
355
356 func (stream, "{");
357 for (reg = 0; reg < 16; reg++)
358 if ((given & (1 << reg)) != 0)
359 {
360 if (started)
361 func (stream, ", ");
362 started = 1;
363 func (stream, "%s", arm_regnames[reg]);
364 }
365 func (stream, "}");
366 }
367 break;
368
369 case 'o':
370 if ((given & 0x02000000) != 0)
371 {
372 int rotate = (given & 0xf00) >> 7;
373 int immed = (given & 0xff);
9f20bbfd
NC		 374 immed = (((immed << (32 - rotate))
375 | (immed >> rotate)) & 0xffffffff);
376 func (stream, "#%d\t; 0x%x", immed, immed);
252b5132
RH		 377 }
378 else
379 arm_decode_shift (given, func, stream);
380 break;
381
382 case 'p':
383 if ((given & 0x0000f000) == 0x0000f000)
384 func (stream, "p");
385 break;
386
387 case 't':
388 if ((given & 0x01200000) == 0x00200000)
389 func (stream, "t");
390 break;
391
392 case 'h':
393 if ((given & 0x00000020) == 0x00000020)
394 func (stream, "h");
395 else
396 func (stream, "b");
397 break;
398
399 case 'A':
400 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
401 if ((given & 0x01000000) != 0)
402 {
403 int offset = given & 0xff;
404 if (offset)
405 func (stream, ", %s#%d]%s",
406 ((given & 0x00800000) == 0 ? "-" : ""),
407 offset * 4,
408 ((given & 0x00200000) != 0 ? "!" : ""));
409 else
410 func (stream, "]");
411 }
412 else
413 {
414 int offset = given & 0xff;
415 if (offset)
416 func (stream, "], %s#%d",
417 ((given & 0x00800000) == 0 ? "-" : ""),
418 offset * 4);
419 else
420 func (stream, "]");
421 }
422 break;
423
424 case 'C':
322f2c45 425 switch (given & 0x000f0000)
252b5132
RH		 426 {
427 default:
428 func (stream, "_???");
429 break;
430 case 0x90000:
431 func (stream, "_all");
432 break;
433 case 0x10000:
322f2c45
NC		 434 func (stream, "_c");
435 break;
436 case 0x20000:
437 func (stream, "_x");
438 break;
439 case 0x40000:
440 func (stream, "_s");
252b5132
RH		 441 break;
442 case 0x80000:
322f2c45 443 func (stream, "_f");
252b5132
RH		 444 break;
445 }
446 break;
447
448 case 'F':
449 switch (given & 0x00408000)
450 {
451 case 0:
452 func (stream, "4");
453 break;
454 case 0x8000:
455 func (stream, "1");
456 break;
457 case 0x00400000:
458 func (stream, "2");
459 break;
460 default:
461 func (stream, "3");
462 }
463 break;
464
465 case 'P':
466 switch (given & 0x00080080)
467 {
468 case 0:
469 func (stream, "s");
470 break;
471 case 0x80:
472 func (stream, "d");
473 break;
474 case 0x00080000:
475 func (stream, "e");
476 break;
477 default:
478 func (stream, _("<illegal precision>"));
479 break;
480 }
481 break;
482 case 'Q':
483 switch (given & 0x00408000)
484 {
485 case 0:
486 func (stream, "s");
487 break;
488 case 0x8000:
489 func (stream, "d");
490 break;
491 case 0x00400000:
492 func (stream, "e");
493 break;
494 default:
495 func (stream, "p");
496 break;
497 }
498 break;
499 case 'R':
500 switch (given & 0x60)
501 {
502 case 0:
503 break;
504 case 0x20:
505 func (stream, "p");
506 break;
507 case 0x40:
508 func (stream, "m");
509 break;
510 default:
511 func (stream, "z");
512 break;
513 }
514 break;
515
516 case '0': case '1': case '2': case '3': case '4':
517 case '5': case '6': case '7': case '8': case '9':
518 {
519 int bitstart = *c++ - '0';
520 int bitend = 0;
521 while (*c >= '0' && *c <= '9')
522 bitstart = (bitstart * 10) + *c++ - '0';
523
524 switch (*c)
525 {
526 case '-':
527 c++;
58efb6c0 528
252b5132
RH		 529 while (*c >= '0' && *c <= '9')
530 bitend = (bitend * 10) + *c++ - '0';
58efb6c0 531
252b5132
RH		 532 if (!bitend)
533 abort ();
58efb6c0 534
252b5132
RH		 535 switch (*c)
536 {
537 case 'r':
538 {
539 long reg;
58efb6c0 540
252b5132
RH		 541 reg = given >> bitstart;
542 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 543
252b5132
RH		 544 func (stream, "%s", arm_regnames[reg]);
545 }
546 break;
547 case 'd':
548 {
549 long reg;
58efb6c0 550
252b5132
RH		 551 reg = given >> bitstart;
552 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 553
252b5132
RH		 554 func (stream, "%d", reg);
555 }
556 break;
557 case 'x':
558 {
559 long reg;
58efb6c0 560
252b5132
RH		 561 reg = given >> bitstart;
562 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 563
252b5132 564 func (stream, "0x%08x", reg);
5876e06d 565
58efb6c0
NC		 566 /* Some SWI instructions have special
567 meanings. */
5876e06d
NC		 568 if ((given & 0x0fffffff) == 0x0FF00000)
569 func (stream, "\t; IMB");
570 else if ((given & 0x0fffffff) == 0x0FF00001)
571 func (stream, "\t; IMBRange");
252b5132
RH		 572 }
573 break;
cfbd315c
DL		 574 case 'X':
575 {
576 long reg;
58efb6c0 577
cfbd315c
DL		 578 reg = given >> bitstart;
579 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 580
cfbd315c
DL		 581 func (stream, "%01x", reg & 0xf);
582 }
583 break;
252b5132
RH		 584 case 'f':
585 {
586 long reg;
58efb6c0 587
252b5132
RH		 588 reg = given >> bitstart;
589 reg &= (2 << (bitend - bitstart)) - 1;
58efb6c0 590
252b5132
RH		 591 if (reg > 7)
592 func (stream, "#%s",
593 arm_fp_const[reg & 7]);
594 else
595 func (stream, "f%d", reg);
596 }
597 break;
598 default:
599 abort ();
600 }
601 break;
58efb6c0 602
252b5132
RH		 603 case '`':
604 c++;
605 if ((given & (1 << bitstart)) == 0)
606 func (stream, "%c", *c);
607 break;
608 case '\'':
609 c++;
610 if ((given & (1 << bitstart)) != 0)
611 func (stream, "%c", *c);
612 break;
613 case '?':
614 ++c;
615 if ((given & (1 << bitstart)) != 0)
616 func (stream, "%c", *c++);
617 else
618 func (stream, "%c", *++c);
619 break;
620 default:
621 abort ();
622 }
623 break;
624
625 default:
626 abort ();
627 }
628 }
629 }
630 else
631 func (stream, "%c", *c);
632 }
633 return 4;
634 }
635 }
636 abort ();
637}
638
639/* Print one instruction from PC on INFO->STREAM.
640 Return the size of the instruction. */
252b5132
RH		 641static int
642print_insn_thumb (pc, info, given)
5876e06d
NC		 643 bfd_vma pc;
644 struct disassemble_info * info;
645 long given;
252b5132 646{
5876e06d
NC		 647 struct thumb_opcode * insn;
648 void * stream = info->stream;
649 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 650
651 for (insn = thumb_opcodes; insn->assembler; insn++)
652 {
653 if ((given & insn->mask) == insn->value)
654 {
5876e06d 655 char * c = insn->assembler;
252b5132 656
58efb6c0
NC		 657 /* Special processing for Thumb 2 instruction BL sequence: */
658 if (!*c) /* Check for empty (not NULL) assembler string. */
252b5132
RH		 659 {
660 info->bytes_per_chunk = 4;
661 info->bytes_per_line = 4;
662
a3d9c82d
NC		 663 func (stream, "bl\t");
664
58efb6c0 665 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
252b5132
RH		 666 return 4;
667 }
668 else
669 {
670 info->bytes_per_chunk = 2;
671 info->bytes_per_line = 4;
672
673 given &= 0xffff;
58efb6c0 674
252b5132
RH		 675 for (; *c; c++)
676 {
677 if (*c == '%')
678 {
679 int domaskpc = 0;
680 int domasklr = 0;
5876e06d 681
252b5132
RH		 682 switch (*++c)
683 {
684 case '%':
685 func (stream, "%%");
686 break;
687
688 case 'S':
689 {
690 long reg;
58efb6c0 691
252b5132
RH		 692 reg = (given >> 3) & 0x7;
693 if (given & (1 << 6))
694 reg += 8;
58efb6c0 695
252b5132
RH		 696 func (stream, "%s", arm_regnames[reg]);
697 }
698 break;
699
700 case 'D':
701 {
702 long reg;
5876e06d 703
252b5132
RH		 704 reg = given & 0x7;
705 if (given & (1 << 7))
706 reg += 8;
58efb6c0 707
252b5132
RH		 708 func (stream, "%s", arm_regnames[reg]);
709 }
710 break;
711
712 case 'T':
713 func (stream, "%s",
714 arm_conditional [(given >> 8) & 0xf]);
715 break;
716
717 case 'N':
718 if (given & (1 << 8))
719 domasklr = 1;
58efb6c0 720 /* Fall through. */
252b5132
RH		 721 case 'O':
722 if (*c == 'O' && (given & (1 << 8)))
723 domaskpc = 1;
58efb6c0 724 /* Fall through. */
252b5132
RH		 725 case 'M':
726 {
727 int started = 0;
728 int reg;
5876e06d 729
252b5132 730 func (stream, "{");
58efb6c0 731
252b5132
RH		 732 /* It would be nice if we could spot
733 ranges, and generate the rS-rE format: */
734 for (reg = 0; (reg < 8); reg++)
735 if ((given & (1 << reg)) != 0)
736 {
737 if (started)
738 func (stream, ", ");
739 started = 1;
740 func (stream, "%s", arm_regnames[reg]);
741 }
742
743 if (domasklr)
744 {
745 if (started)
746 func (stream, ", ");
747 started = 1;
a7f8487e 748 func (stream, arm_regnames[14] /* "lr" */);
252b5132
RH		 749 }
750
751 if (domaskpc)
752 {
753 if (started)
754 func (stream, ", ");
a7f8487e 755 func (stream, arm_regnames[15] /* "pc" */);
252b5132
RH		 756 }
757
758 func (stream, "}");
759 }
760 break;
761
762
763 case '0': case '1': case '2': case '3': case '4':
764 case '5': case '6': case '7': case '8': case '9':
765 {
766 int bitstart = *c++ - '0';
767 int bitend = 0;
5876e06d 768
252b5132
RH		 769 while (*c >= '0' && *c <= '9')
770 bitstart = (bitstart * 10) + *c++ - '0';
771
772 switch (*c)
773 {
774 case '-':
775 {
776 long reg;
5876e06d 777
252b5132
RH		 778 c++;
779 while (*c >= '0' && *c <= '9')
780 bitend = (bitend * 10) + *c++ - '0';
781 if (!bitend)
782 abort ();
783 reg = given >> bitstart;
784 reg &= (2 << (bitend - bitstart)) - 1;
785 switch (*c)
786 {
787 case 'r':
788 func (stream, "%s", arm_regnames[reg]);
789 break;
790
791 case 'd':
792 func (stream, "%d", reg);
793 break;
794
795 case 'H':
796 func (stream, "%d", reg << 1);
797 break;
798
799 case 'W':
800 func (stream, "%d", reg << 2);
801 break;
802
803 case 'a':
804 /* PC-relative address -- the bottom two
58efb6c0
NC		 805 bits of the address are dropped
806 before the calculation. */
252b5132
RH		 807 info->print_address_func
808 (((pc + 4) & ~3) + (reg << 2), info);
809 break;
810
811 case 'x':
812 func (stream, "0x%04x", reg);
813 break;
814
815 case 'I':
816 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
817 func (stream, "%d", reg);
818 break;
819
820 case 'B':
821 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
822 (*info->print_address_func)
823 (reg * 2 + pc + 4, info);
824 break;
825
826 default:
5876e06d 827 abort ();
252b5132
RH		 828 }
829 }
830 break;
831
832 case '\'':
833 c++;
834 if ((given & (1 << bitstart)) != 0)
835 func (stream, "%c", *c);
836 break;
837
838 case '?':
839 ++c;
840 if ((given & (1 << bitstart)) != 0)
841 func (stream, "%c", *c++);
842 else
843 func (stream, "%c", *++c);
844 break;
845
846 default:
5876e06d 847 abort ();
252b5132
RH		 848 }
849 }
850 break;
851
852 default:
853 abort ();
854 }
855 }
856 else
857 func (stream, "%c", *c);
858 }
859 }
860 return 2;
861 }
862 }
863
58efb6c0 864 /* No match. */
252b5132
RH		 865 abort ();
866}
867
58efb6c0 868/* Parse an individual disassembler option. */
a3d9c82d
NC		 869void
870parse_arm_disassembler_option (option)
01c7f630 871 char * option;
dd92f639 872{
01c7f630 873 if (option == NULL)
dd92f639
NC		 874 return;
875
01c7f630 876 if (strneq (option, "reg-names-", 10))
dd92f639 877 {
58efb6c0
NC		 878 int i;
879
01c7f630 880 option += 10;
58efb6c0
NC		 881
882 for (i = NUM_ARM_REGNAMES; i--;)
883 if (streq (option, regnames[i].name))
884 {
885 regname_selected = i;
886 break;
887 }
dd92f639 888
58efb6c0
NC		 889 if (i < 0)
890 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 891 }
01c7f630
NC		 892 else if (streq (option, "force-thumb"))
893 force_thumb = 1;
894 else if (streq (option, "no-force-thumb"))
895 force_thumb = 0;
dd92f639 896 else
58efb6c0 897 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
dd92f639
NC		 898
899 return;
900}
901
58efb6c0 902/* Parse the string of disassembler options, spliting it at whitespaces. */
01c7f630
NC		 903static void
904parse_disassembler_options (options)
905 char * options;
906{
907 char * space;
908
909 if (options == NULL)
910 return;
911
912 do
913 {
914 space = strchr (options, ' ');
915
916 if (space)
917 {
918 * space = '\0';
a3d9c82d 919 parse_arm_disassembler_option (options);
01c7f630
NC		 920 * space = ' ';
921 options = space + 1;
922 }
923 else
a3d9c82d 924 parse_arm_disassembler_option (options);
01c7f630
NC		 925 }
926 while (space);
927}
928
58efb6c0
NC		 929/* NOTE: There are no checks in these routines that
930 the relevant number of data bytes exist. */
931static int
932print_insn (pc, info, little)
252b5132 933 bfd_vma pc;
5876e06d 934 struct disassemble_info * info;
58efb6c0 935 boolean little;
252b5132
RH		 936{
937 unsigned char b[4];
938 long given;
939 int status;
252b5132 940 int is_thumb;
58efb6c0 941
dd92f639
NC		 942 if (info->disassembler_options)
943 {
944 parse_disassembler_options (info->disassembler_options);
945
58efb6c0 946 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 947 info->disassembler_options = NULL;
948 }
949
01c7f630
NC		 950 is_thumb = force_thumb;
951
952 if (!is_thumb && info->symbols != NULL)
252b5132 953 {
5876e06d
NC		 954 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
955 {
2f0ca46a
NC		 956 coff_symbol_type * cs;
957
5876e06d
NC		 958 cs = coffsymbol (*info->symbols);
959 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
960 || cs->native->u.syment.n_sclass == C_THUMBSTAT
961 || cs->native->u.syment.n_sclass == C_THUMBLABEL
962 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
963 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
964 }
965 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
966 {
2f0ca46a 967 elf_symbol_type * es;
58efb6c0 968 unsigned int type;
2f0ca46a 969
5876e06d 970 es = *(elf_symbol_type **)(info->symbols);
58efb6c0
NC		 971 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
972
973 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
5876e06d
NC		 974 }
975 }
58efb6c0 976
252b5132 977 info->bytes_per_chunk = 4;
58efb6c0 978 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
252b5132 979
58efb6c0 980 if (little)
252b5132 981 {
58efb6c0
NC		 982 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
983 if (status != 0 && is_thumb)
984 {
985 info->bytes_per_chunk = 2;
986
987 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
988 b[3] = b[2] = 0;
989 }
990
991 if (status != 0)
992 {
993 info->memory_error_func (status, pc, info);
994 return -1;
995 }
996
997 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
252b5132 998 }
58efb6c0 999 else
252b5132 1000 {
58efb6c0
NC		 1001 status = info->read_memory_func
1002 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
1003 if (status != 0)
252b5132 1004 {
58efb6c0
NC		 1005 info->memory_error_func (status, pc, info);
1006 return -1;
1007 }
1008
1009 if (is_thumb)
1010 {
1011 if (pc & 0x2)
252b5132 1012 {
58efb6c0
NC		 1013 given = (b[2] << 8) | b[3];
1014
1015 status = info->read_memory_func
1016 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
1017 if (status != 0)
1018 {
1019 info->memory_error_func (status, pc + 4, info);
1020 return -1;
1021 }
1022
1023 given |= (b[0] << 24) | (b[1] << 16);
252b5132 1024 }
58efb6c0
NC		 1025 else
1026 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
252b5132
RH		 1027 }
1028 else
58efb6c0 1029 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
252b5132 1030 }
58efb6c0 1031
252b5132 1032 if (is_thumb)
5876e06d 1033 status = print_insn_thumb (pc, info, given);
252b5132 1034 else
5876e06d 1035 status = print_insn_arm (pc, info, given);
252b5132
RH		 1036
1037 return status;
1038}
1039
1040int
58efb6c0 1041print_insn_big_arm (pc, info)
252b5132
RH		 1042 bfd_vma pc;
1043 struct disassemble_info * info;
1044{
58efb6c0
NC		 1045 return print_insn (pc, info, false);
1046}
01c7f630 1047
58efb6c0
NC		 1048int
1049print_insn_little_arm (pc, info)
1050 bfd_vma pc;
1051 struct disassemble_info * info;
1052{
1053 return print_insn (pc, info, true);
1054}
252b5132 1055
58efb6c0
NC		 1056void
1057print_arm_disassembler_options (FILE * stream)
1058{
1059 int i;
252b5132 1060
58efb6c0
NC		 1061 fprintf (stream, _("\n\
1062The following ARM specific disassembler options are supported for use with\n\
1063the -M switch:\n"));
01c7f630 1064
58efb6c0
NC		 1065 for (i = NUM_ARM_REGNAMES; i--;)
1066 fprintf (stream, " reg-names-%s %*c%s\n",
1067 regnames[i].name,
1068 14 - strlen (regnames[i].name), ' ',
1069 regnames[i].description);
1070
1071 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1072 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
252b5132 1073}
GDB Binutils - Deliverables
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