[deliverable/binutils-gdb.git] / opcodes / avr-dis.c

/* Disassemble AVR instructions.
   Copyright 1999, 2000, 2002, 2004, 2005 Free Software Foundation, Inc.

   Contributed by Denis Chertykov <denisc@overta.ru>

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#include <assert.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"
#include "libiberty.h"

struct avr_opcodes_s
{
  char *name;
  char *constraints;
  char *opcode;
  int insn_size;		/* In words.  */
  int isa;
  unsigned int bin_opcode;
};

#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},

const struct avr_opcodes_s avr_opcodes[] =
{
  #include "opcode/avr.h"
  {NULL, NULL, NULL, 0, 0, 0}
};

static int
avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
             char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
{
  int ok = 1;
  *sym = 0;

  switch (constraint)
    {
      /* Any register operand.  */
    case 'r':
      if (regs)
	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register.  */
      else
	insn = (insn & 0x01f0) >> 4; /* Destination register.  */
      
      sprintf (buf, "r%d", insn);
      break;

    case 'd':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 0xf));
      else
	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
      break;
      
    case 'w':
      sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
      break;
      
    case 'a':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 7));
      else
	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
      break;

    case 'v':
      if (regs)
	sprintf (buf, "r%d", (insn & 0xf) * 2);
      else
	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
      break;

    case 'e':
      {
	char *xyz;

	switch (insn & 0x100f)
	  {
	    case 0x0000: xyz = "Z";  break;
	    case 0x1001: xyz = "Z+"; break;
	    case 0x1002: xyz = "-Z"; break;
	    case 0x0008: xyz = "Y";  break;
	    case 0x1009: xyz = "Y+"; break;
	    case 0x100a: xyz = "-Y"; break;
	    case 0x100c: xyz = "X";  break;
	    case 0x100d: xyz = "X+"; break;
	    case 0x100e: xyz = "-X"; break;
	    default: xyz = "??"; ok = 0;
	  }
	sprintf (buf, xyz);

	if (AVR_UNDEF_P (insn))
	  sprintf (comment, _("undefined"));
      }
      break;

    case 'z':
      *buf++ = 'Z';
      if (insn & 0x1)
	*buf++ = '+';
      *buf = '\0';
      if (AVR_UNDEF_P (insn))
	sprintf (comment, _("undefined"));
      break;

    case 'b':
      {
	unsigned int x;
	
	x = (insn & 7);
	x |= (insn >> 7) & (3 << 3);
	x |= (insn >> 8) & (1 << 5);
	
	if (insn & 0x8)
	  *buf++ = 'Y';
	else
	  *buf++ = 'Z';
	sprintf (buf, "+%d", x);
	sprintf (comment, "0x%02x", x);
      }
      break;
      
    case 'h':
      *sym = 1;
      *sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2;
      sprintf (buf, "0x");
      break;
      
    case 'L':
      {
	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
        *sym = 1;
        *sym_addr = pc + 2 + rel_addr;
	sprintf (comment, "0x");
      }
      break;

    case 'l':
      {
	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
        *sym = 1;
        *sym_addr = pc + 2 + rel_addr;
	sprintf (comment, "0x");
      }
      break;

    case 'i':
      sprintf (buf, "0x%04X", insn2);
      break;
      
    case 'M':
      sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
      sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
      break;

    case 'n':
      sprintf (buf, "??");
      fprintf (stderr, _("Internal disassembler error"));
      ok = 0;
      break;
      
    case 'K':
      {
	unsigned int x;

	x = (insn & 0xf) | ((insn >> 2) & 0x30);
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case 's':
      sprintf (buf, "%d", insn & 7);
      break;
      
    case 'S':
      sprintf (buf, "%d", (insn >> 4) & 7);
      break;
      
    case 'P':
      {
	unsigned int x;

	x = (insn & 0xf);
	x |= (insn >> 5) & 0x30;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;

    case 'p':
      {
	unsigned int x;
	
	x = (insn >> 3) & 0x1f;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case '?':
      *buf = '\0';
      break;
      
    default:
      sprintf (buf, "??");
      fprintf (stderr, _("unknown constraint `%c'"), constraint);
      ok = 0;
    }

    return ok;
}

static unsigned short
avrdis_opcode (bfd_vma addr, disassemble_info *info)
{
  bfd_byte buffer[2];
  int status;

  status = info->read_memory_func (addr, buffer, 2, info);

  if (status == 0)
    return bfd_getl16 (buffer);

  info->memory_error_func (status, addr, info);
  return -1;
}


int
print_insn_avr (bfd_vma addr, disassemble_info *info)
{
  unsigned int insn, insn2;
  const struct avr_opcodes_s *opcode;
  static unsigned int *maskptr;
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  static unsigned int *avr_bin_masks;
  static int initialized;
  int cmd_len = 2;
  int ok = 0;
  char op1[20], op2[20], comment1[40], comment2[40];
  int sym_op1 = 0, sym_op2 = 0;
  bfd_vma sym_addr1, sym_addr2;

  if (!initialized)
    {
      unsigned int nopcodes;

      nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
      
      avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));

      for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	   opcode->name;
	   opcode++, maskptr++)
	{
	  char * s;
	  unsigned int bin = 0;
	  unsigned int mask = 0;
	
	  for (s = opcode->opcode; *s; ++s)
	    {
	      bin <<= 1;
	      mask <<= 1;
	      bin |= (*s == '1');
	      mask |= (*s == '1' || *s == '0');
	    }
	  assert (s - opcode->opcode == 16);
	  assert (opcode->bin_opcode == bin);
	  *maskptr = mask;
	}

      initialized = 1;
    }

  insn = avrdis_opcode (addr, info);
  
  for (opcode = avr_opcodes, maskptr = avr_bin_masks;
       opcode->name;
       opcode++, maskptr++)
    if ((insn & *maskptr) == opcode->bin_opcode)
      break;
  
  /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
     `std b+0,r' as `st b,r' (next entry in the table).  */

  if (AVR_DISP0_P (insn))
    opcode++;

  op1[0] = 0;
  op2[0] = 0;
  comment1[0] = 0;
  comment2[0] = 0;

  if (opcode->name)
    {
      char *op = opcode->constraints;

      insn2 = 0;
      ok = 1;

      if (opcode->insn_size > 1)
	{
	  insn2 = avrdis_opcode (addr + 2, info);
	  cmd_len = 4;
	}

      if (*op && *op != '?')
	{
	  int regs = REGISTER_P (*op);

	  ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);

	  if (ok && *(++op) == ',')
	    ok = avr_operand (insn, insn2, addr, *(++op), op2,
			      *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
	}
    }

  if (!ok)
    {
      /* Unknown opcode, or invalid combination of operands.  */
      sprintf (op1, "0x%04x", insn);
      op2[0] = 0;
      sprintf (comment1, "????");
      comment2[0] = 0;
    }

  (*prin) (stream, "%s", ok ? opcode->name : ".word");

  if (*op1)
      (*prin) (stream, "\t%s", op1);

  if (*op2)
    (*prin) (stream, ", %s", op2);

  if (*comment1)
    (*prin) (stream, "\t; %s", comment1);

  if (sym_op1)
    info->print_address_func (sym_addr1, info);

  if (*comment2)
    (*prin) (stream, " %s", comment2);

  if (sym_op2)
    info->print_address_func (sym_addr2, info);

  return cmd_len;
}
Commit	Line	Data
adde6300	1	/* Disassemble AVR instructions.
47b0e7ad	2	Copyright 1999, 2000, 2002, 2004, 2005 Free Software Foundation, Inc.
adde6300 AM	3
	4	Contributed by Denis Chertykov <denisc@overta.ru>
	5
47b0e7ad NC	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
adde6300	10
47b0e7ad NC	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
adde6300	15
47b0e7ad NC	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
adde6300	19
bab84c47	20	#include <assert.h>
0d8dfecf	21	#include "sysdep.h"
adde6300 AM	22	#include "dis-asm.h"
adde6300 AM	23	#include "opintl.h"
11041102	24	#include "libiberty.h"
3c504221	25
bab84c47	26	struct avr_opcodes_s
adde6300	27	{
bab84c47 DC	28	char *name;
	29	char *constraints;
	30	char *opcode;
47b0e7ad	31	int insn_size; /* In words. */
bab84c47 DC	32	int isa;
bab84c47 DC	33	unsigned int bin_opcode;
bab84c47	34	};
adde6300	35
bab84c47	36	#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
11041102	37	{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
adde6300	38
11041102	39	const struct avr_opcodes_s avr_opcodes[] =
adde6300	40	{
bab84c47	41	#include "opcode/avr.h"
11041102	42	{NULL, NULL, NULL, 0, 0, 0}
bab84c47	43	};
adde6300	44
463f102c	45	static int
246f4c05 SS	46	avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
246f4c05 SS	47	char buf, char comment, int regs, int sym, bfd_vma sym_addr)
adde6300	48	{
463f102c	49	int ok = 1;
246f4c05	50	*sym = 0;
463f102c	51
bab84c47 DC	52	switch (constraint)
	53	{
	54	/* Any register operand. */
	55	case 'r':
	56	if (regs)
47b0e7ad	57	insn = (insn & 0xf) \| ((insn & 0x0200) >> 5); /* Source register. */
bab84c47	58	else
47b0e7ad	59	insn = (insn & 0x01f0) >> 4; /* Destination register. */
bab84c47 DC	60
	61	sprintf (buf, "r%d", insn);
	62	break;
	63
	64	case 'd':
	65	if (regs)
	66	sprintf (buf, "r%d", 16 + (insn & 0xf));
	67	else
	68	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
	69	break;
	70
	71	case 'w':
	72	sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
	73	break;
	74
	75	case 'a':
	76	if (regs)
	77	sprintf (buf, "r%d", 16 + (insn & 7));
	78	else
	79	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
	80	break;
adde6300	81
bab84c47 DC	82	case 'v':
	83	if (regs)
	84	sprintf (buf, "r%d", (insn & 0xf) * 2);
	85	else
	86	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
	87	break;
	88
	89	case 'e':
463f102c DC	90	{
	91	char *xyz;
	92
	93	switch (insn & 0x100f)
	94	{
	95	case 0x0000: xyz = "Z"; break;
	96	case 0x1001: xyz = "Z+"; break;
	97	case 0x1002: xyz = "-Z"; break;
	98	case 0x0008: xyz = "Y"; break;
	99	case 0x1009: xyz = "Y+"; break;
	100	case 0x100a: xyz = "-Y"; break;
	101	case 0x100c: xyz = "X"; break;
	102	case 0x100d: xyz = "X+"; break;
	103	case 0x100e: xyz = "-X"; break;
	104	default: xyz = "??"; ok = 0;
	105	}
	106	sprintf (buf, xyz);
	107
	108	if (AVR_UNDEF_P (insn))
	109	sprintf (comment, _("undefined"));
	110	}
bab84c47 DC	111	break;
	112
	113	case 'z':
	114	*buf++ = 'Z';
	115	if (insn & 0x1)
	116	*buf++ = '+';
	117	*buf = '\0';
463f102c DC	118	if (AVR_UNDEF_P (insn))
463f102c DC	119	sprintf (comment, _("undefined"));
bab84c47 DC	120	break;
	121
	122	case 'b':
	123	{
463f102c	124	unsigned int x;
bab84c47 DC	125
	126	x = (insn & 7);
	127	x \|= (insn >> 7) & (3 << 3);
	128	x \|= (insn >> 8) & (1 << 5);
	129
	130	if (insn & 0x8)
	131	*buf++ = 'Y';
	132	else
	133	*buf++ = 'Z';
	134	sprintf (buf, "+%d", x);
	135	sprintf (comment, "0x%02x", x);
	136	}
	137	break;
	138
	139	case 'h':
246f4c05 SS	140	*sym = 1;
	141	sym_addr = ((((insn & 1) \| ((insn & 0x1f0) >> 3)) << 16) \| insn2) 2;
	142	sprintf (buf, "0x");
bab84c47 DC	143	break;
	144
	145	case 'L':
	146	{
	147	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	148	sprintf (buf, ".%+-8d", rel_addr);
246f4c05 SS	149	*sym = 1;
	150	*sym_addr = pc + 2 + rel_addr;
	151	sprintf (comment, "0x");
bab84c47 DC	152	}
	153	break;
	154
	155	case 'l':
	156	{
	157	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	158	sprintf (buf, ".%+-8d", rel_addr);
246f4c05 SS	159	*sym = 1;
	160	*sym_addr = pc + 2 + rel_addr;
	161	sprintf (comment, "0x");
bab84c47 DC	162	}
	163	break;
	164
	165	case 'i':
	166	sprintf (buf, "0x%04X", insn2);
	167	break;
	168
	169	case 'M':
	170	sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	171	sprintf (comment, "%d", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	172	break;
	173
	174	case 'n':
463f102c DC	175	sprintf (buf, "??");
	176	fprintf (stderr, _("Internal disassembler error"));
	177	ok = 0;
bab84c47 DC	178	break;
	179
	180	case 'K':
463f102c DC	181	{
	182	unsigned int x;
	183
	184	x = (insn & 0xf) \| ((insn >> 2) & 0x30);
	185	sprintf (buf, "0x%02x", x);
	186	sprintf (comment, "%d", x);
	187	}
bab84c47 DC	188	break;
	189
	190	case 's':
	191	sprintf (buf, "%d", insn & 7);
	192	break;
	193
	194	case 'S':
	195	sprintf (buf, "%d", (insn >> 4) & 7);
	196	break;
	197
	198	case 'P':
	199	{
	200	unsigned int x;
47b0e7ad	201
bab84c47 DC	202	x = (insn & 0xf);
	203	x \|= (insn >> 5) & 0x30;
	204	sprintf (buf, "0x%02x", x);
	205	sprintf (comment, "%d", x);
	206	}
	207	break;
	208
	209	case 'p':
	210	{
	211	unsigned int x;
	212
	213	x = (insn >> 3) & 0x1f;
	214	sprintf (buf, "0x%02x", x);
	215	sprintf (comment, "%d", x);
	216	}
	217	break;
	218
	219	case '?':
	220	*buf = '\0';
	221	break;
	222
	223	default:
463f102c DC	224	sprintf (buf, "??");
	225	fprintf (stderr, _("unknown constraint `%c'"), constraint);
	226	ok = 0;
bab84c47	227	}
463f102c DC	228
463f102c DC	229	return ok;
adde6300 AM	230	}
adde6300 AM	231
bab84c47	232	static unsigned short
47b0e7ad	233	avrdis_opcode (bfd_vma addr, disassemble_info *info)
adde6300 AM	234	{
	235	bfd_byte buffer[2];
	236	int status;
47b0e7ad NC	237
	238	status = info->read_memory_func (addr, buffer, 2, info);
	239
	240	if (status == 0)
	241	return bfd_getl16 (buffer);
	242
	243	info->memory_error_func (status, addr, info);
	244	return -1;
adde6300 AM	245	}
	246
	247
	248	int
47b0e7ad	249	print_insn_avr (bfd_vma addr, disassemble_info *info)
adde6300	250	{
bab84c47	251	unsigned int insn, insn2;
11041102 KD	252	const struct avr_opcodes_s *opcode;
11041102 KD	253	static unsigned int *maskptr;
adde6300 AM	254	void *stream = info->stream;
adde6300 AM	255	fprintf_ftype prin = info->fprintf_func;
11041102	256	static unsigned int *avr_bin_masks;
bab84c47	257	static int initialized;
adde6300	258	int cmd_len = 2;
463f102c DC	259	int ok = 0;
463f102c DC	260	char op1[20], op2[20], comment1[40], comment2[40];
246f4c05 SS	261	int sym_op1 = 0, sym_op2 = 0;
246f4c05 SS	262	bfd_vma sym_addr1, sym_addr2;
adde6300	263
bab84c47 DC	264	if (!initialized)
bab84c47 DC	265	{
11041102 KD	266	unsigned int nopcodes;
	267
	268	nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
bab84c47	269
47b0e7ad	270	avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
11041102 KD	271
	272	for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	273	opcode->name;
	274	opcode++, maskptr++)
bab84c47 DC	275	{
	276	char * s;
	277	unsigned int bin = 0;
	278	unsigned int mask = 0;
	279
	280	for (s = opcode->opcode; *s; ++s)
	281	{
	282	bin <<= 1;
	283	mask <<= 1;
	284	bin \|= (*s == '1');
	285	mask \|= (s == '1' \|\| s == '0');
	286	}
	287	assert (s - opcode->opcode == 16);
	288	assert (opcode->bin_opcode == bin);
11041102	289	*maskptr = mask;
bab84c47	290	}
11041102 KD	291
11041102 KD	292	initialized = 1;
bab84c47	293	}
adde6300	294
bab84c47 DC	295	insn = avrdis_opcode (addr, info);
bab84c47 DC	296
11041102 KD	297	for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	298	opcode->name;
	299	opcode++, maskptr++)
47b0e7ad NC	300	if ((insn & *maskptr) == opcode->bin_opcode)
47b0e7ad NC	301	break;
bab84c47	302
463f102c DC	303	/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
	304	`std b+0,r' as `st b,r' (next entry in the table). */
	305
	306	if (AVR_DISP0_P (insn))
	307	opcode++;
	308
	309	op1[0] = 0;
	310	op2[0] = 0;
	311	comment1[0] = 0;
	312	comment2[0] = 0;
	313
bab84c47	314	if (opcode->name)
adde6300	315	{
bab84c47 DC	316	char *op = opcode->constraints;
bab84c47 DC	317
00d2865b	318	insn2 = 0;
463f102c	319	ok = 1;
bab84c47 DC	320
	321	if (opcode->insn_size > 1)
	322	{
	323	insn2 = avrdis_opcode (addr + 2, info);
	324	cmd_len = 4;
	325	}
	326
	327	if (op && op != '?')
	328	{
	329	int regs = REGISTER_P (*op);
	330
246f4c05	331	ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);
bab84c47	332
463f102c DC	333	if (ok && *(++op) == ',')
463f102c DC	334	ok = avr_operand (insn, insn2, addr, *(++op), op2,
246f4c05	335	*comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
bab84c47	336	}
463f102c	337	}
bab84c47	338
463f102c DC	339	if (!ok)
	340	{
	341	/* Unknown opcode, or invalid combination of operands. */
	342	sprintf (op1, "0x%04x", insn);
	343	op2[0] = 0;
	344	sprintf (comment1, "????");
	345	comment2[0] = 0;
	346	}
bab84c47	347
463f102c	348	(*prin) (stream, "%s", ok ? opcode->name : ".word");
bab84c47	349
463f102c	350	if (*op1)
246f4c05	351	(*prin) (stream, "\t%s", op1);
bab84c47	352
463f102c DC	353	if (*op2)
	354	(*prin) (stream, ", %s", op2);
	355
	356	if (*comment1)
	357	(*prin) (stream, "\t; %s", comment1);
	358
246f4c05	359	if (sym_op1)
73f643e9	360	info->print_address_func (sym_addr1, info);
246f4c05	361
463f102c DC	362	if (*comment2)
463f102c DC	363	(*prin) (stream, " %s", comment2);
bab84c47	364
246f4c05	365	if (sym_op2)
73f643e9	366	info->print_address_func (sym_addr2, info);
246f4c05	367
adde6300 AM	368	return cmd_len;
adde6300 AM	369	}