[deliverable/binutils-gdb.git] / opcodes / avr-dis.c

/* Disassemble AVR instructions.
   Copyright 1999, 2000 Free Software Foundation, Inc.

   Contributed by Denis Chertykov <denisc@overta.ru>

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <assert.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"
#include "libiberty.h"

struct avr_opcodes_s
{
  char *name;
  char *constraints;
  char *opcode;
  int insn_size;		/* in words */
  int isa;
  unsigned int bin_opcode;
};

#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},

const struct avr_opcodes_s avr_opcodes[] =
{
  #include "opcode/avr.h"
  {NULL, NULL, NULL, 0, 0, 0}
};

static int avr_operand PARAMS ((unsigned int, unsigned int,
				unsigned int, int, char *, char *, int));

static int
avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
     unsigned int insn;
     unsigned int insn2;
     unsigned int pc;
     int constraint;
     char *buf;
     char *comment;
     int regs;
{
  int ok = 1;

  switch (constraint)
    {
      /* Any register operand.  */
    case 'r':
      if (regs)
	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
      else
	insn = (insn & 0x01f0) >> 4; /* destination register */
      
      sprintf (buf, "r%d", insn);
      break;

    case 'd':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 0xf));
      else
	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
      break;
      
    case 'w':
      sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
      break;
      
    case 'a':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 7));
      else
	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
      break;

    case 'v':
      if (regs)
	sprintf (buf, "r%d", (insn & 0xf) * 2);
      else
	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
      break;

    case 'e':
      {
	char *xyz;

	switch (insn & 0x100f)
	  {
	    case 0x0000: xyz = "Z";  break;
	    case 0x1001: xyz = "Z+"; break;
	    case 0x1002: xyz = "-Z"; break;
	    case 0x0008: xyz = "Y";  break;
	    case 0x1009: xyz = "Y+"; break;
	    case 0x100a: xyz = "-Y"; break;
	    case 0x100c: xyz = "X";  break;
	    case 0x100d: xyz = "X+"; break;
	    case 0x100e: xyz = "-X"; break;
	    default: xyz = "??"; ok = 0;
	  }
	sprintf (buf, xyz);

	if (AVR_UNDEF_P (insn))
	  sprintf (comment, _("undefined"));
      }
      break;

    case 'z':
      *buf++ = 'Z';
      if (insn & 0x1)
	*buf++ = '+';
      *buf = '\0';
      if (AVR_UNDEF_P (insn))
	sprintf (comment, _("undefined"));
      break;

    case 'b':
      {
	unsigned int x;
	
	x = (insn & 7);
	x |= (insn >> 7) & (3 << 3);
	x |= (insn >> 8) & (1 << 5);
	
	if (insn & 0x8)
	  *buf++ = 'Y';
	else
	  *buf++ = 'Z';
	sprintf (buf, "+%d", x);
	sprintf (comment, "0x%02x", x);
      }
      break;
      
    case 'h':
      sprintf (buf, "0x%x",
	       ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2);
      break;
      
    case 'L':
      {
	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'l':
      {
	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'i':
      sprintf (buf, "0x%04X", insn2);
      break;
      
    case 'M':
      sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
      sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
      break;

    case 'n':
      sprintf (buf, "??");
      fprintf (stderr, _("Internal disassembler error"));
      ok = 0;
      break;
      
    case 'K':
      {
	unsigned int x;

	x = (insn & 0xf) | ((insn >> 2) & 0x30);
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case 's':
      sprintf (buf, "%d", insn & 7);
      break;
      
    case 'S':
      sprintf (buf, "%d", (insn >> 4) & 7);
      break;
      
    case 'P':
      {
	unsigned int x;
	x = (insn & 0xf);
	x |= (insn >> 5) & 0x30;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;

    case 'p':
      {
	unsigned int x;
	
	x = (insn >> 3) & 0x1f;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case '?':
      *buf = '\0';
      break;
      
    default:
      sprintf (buf, "??");
      fprintf (stderr, _("unknown constraint `%c'"), constraint);
      ok = 0;
    }

    return ok;
}

static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));

static unsigned short
avrdis_opcode (addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  bfd_byte buffer[2];
  int status;
  status = info->read_memory_func(addr, buffer, 2, info);
  if (status != 0)
    {
      info->memory_error_func(status, addr, info);
      return -1;
    }
  return bfd_getl16 (buffer);
}


int
print_insn_avr(addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  unsigned int insn, insn2;
  const struct avr_opcodes_s *opcode;
  static unsigned int *maskptr;
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  static unsigned int *avr_bin_masks;
  static int initialized;
  int cmd_len = 2;
  int ok = 0;
  char op1[20], op2[20], comment1[40], comment2[40];

  if (!initialized)
    {
      unsigned int nopcodes;

      nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
      
      avr_bin_masks = (unsigned int *)
	xmalloc (nopcodes * sizeof (unsigned int));

      for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	   opcode->name;
	   opcode++, maskptr++)
	{
	  char * s;
	  unsigned int bin = 0;
	  unsigned int mask = 0;
	
	  for (s = opcode->opcode; *s; ++s)
	    {
	      bin <<= 1;
	      mask <<= 1;
	      bin |= (*s == '1');
	      mask |= (*s == '1' || *s == '0');
	    }
	  assert (s - opcode->opcode == 16);
	  assert (opcode->bin_opcode == bin);
	  *maskptr = mask;
	}

      initialized = 1;
    }

  insn = avrdis_opcode (addr, info);
  
  for (opcode = avr_opcodes, maskptr = avr_bin_masks;
       opcode->name;
       opcode++, maskptr++)
    {
      if ((insn & *maskptr) == opcode->bin_opcode)
	break;
    }
  
  /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
     `std b+0,r' as `st b,r' (next entry in the table).  */

  if (AVR_DISP0_P (insn))
    opcode++;

  op1[0] = 0;
  op2[0] = 0;
  comment1[0] = 0;
  comment2[0] = 0;

  if (opcode->name)
    {
      char *op = opcode->constraints;

      insn2 = 0;
      ok = 1;

      if (opcode->insn_size > 1)
	{
	  insn2 = avrdis_opcode (addr + 2, info);
	  cmd_len = 4;
	}

      if (*op && *op != '?')
	{
	  int regs = REGISTER_P (*op);

	  ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0);

	  if (ok && *(++op) == ',')
	    ok = avr_operand (insn, insn2, addr, *(++op), op2,
			      *comment1 ? comment2 : comment1, regs);
	}
    }

  if (!ok)
    {
      /* Unknown opcode, or invalid combination of operands.  */
      sprintf (op1, "0x%04x", insn);
      op2[0] = 0;
      sprintf (comment1, "????");
      comment2[0] = 0;
    }

  (*prin) (stream, "%s", ok ? opcode->name : ".word");

  if (*op1)
    (*prin) (stream, "\t%s", op1);

  if (*op2)
    (*prin) (stream, ", %s", op2);

  if (*comment1)
    (*prin) (stream, "\t; %s", comment1);

  if (*comment2)
    (*prin) (stream, " %s", comment2);

  return cmd_len;
}
Commit	Line	Data
adde6300	1	/* Disassemble AVR instructions.
060d22b0	2	Copyright 1999, 2000 Free Software Foundation, Inc.
adde6300 AM	3
	4	Contributed by Denis Chertykov <denisc@overta.ru>
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	19
bab84c47	20	#include <assert.h>
0d8dfecf	21	#include "sysdep.h"
adde6300 AM	22	#include "dis-asm.h"
adde6300 AM	23	#include "opintl.h"
11041102	24	#include "libiberty.h"
3c504221	25
bab84c47	26	struct avr_opcodes_s
adde6300	27	{
bab84c47 DC	28	char *name;
	29	char *constraints;
	30	char *opcode;
	31	int insn_size; /* in words */
	32	int isa;
	33	unsigned int bin_opcode;
bab84c47	34	};
adde6300	35
bab84c47	36	#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
11041102	37	{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
adde6300	38
11041102	39	const struct avr_opcodes_s avr_opcodes[] =
adde6300	40	{
bab84c47	41	#include "opcode/avr.h"
11041102	42	{NULL, NULL, NULL, 0, 0, 0}
bab84c47	43	};
adde6300	44
463f102c DC	45	static int avr_operand PARAMS ((unsigned int, unsigned int,
463f102c DC	46	unsigned int, int, char , char , int));
adde6300	47
463f102c	48	static int
bab84c47 DC	49	avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
	50	unsigned int insn;
	51	unsigned int insn2;
	52	unsigned int pc;
	53	int constraint;
	54	char *buf;
	55	char *comment;
	56	int regs;
adde6300	57	{
463f102c DC	58	int ok = 1;
463f102c DC	59
bab84c47 DC	60	switch (constraint)
	61	{
	62	/* Any register operand. */
	63	case 'r':
	64	if (regs)
	65	insn = (insn & 0xf) \| ((insn & 0x0200) >> 5); /* source register */
	66	else
	67	insn = (insn & 0x01f0) >> 4; /* destination register */
	68
	69	sprintf (buf, "r%d", insn);
	70	break;
	71
	72	case 'd':
	73	if (regs)
	74	sprintf (buf, "r%d", 16 + (insn & 0xf));
	75	else
	76	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
	77	break;
	78
	79	case 'w':
	80	sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
	81	break;
	82
	83	case 'a':
	84	if (regs)
	85	sprintf (buf, "r%d", 16 + (insn & 7));
	86	else
	87	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
	88	break;
adde6300	89
bab84c47 DC	90	case 'v':
	91	if (regs)
	92	sprintf (buf, "r%d", (insn & 0xf) * 2);
	93	else
	94	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
	95	break;
	96
	97	case 'e':
463f102c DC	98	{
	99	char *xyz;
	100
	101	switch (insn & 0x100f)
	102	{
	103	case 0x0000: xyz = "Z"; break;
	104	case 0x1001: xyz = "Z+"; break;
	105	case 0x1002: xyz = "-Z"; break;
	106	case 0x0008: xyz = "Y"; break;
	107	case 0x1009: xyz = "Y+"; break;
	108	case 0x100a: xyz = "-Y"; break;
	109	case 0x100c: xyz = "X"; break;
	110	case 0x100d: xyz = "X+"; break;
	111	case 0x100e: xyz = "-X"; break;
	112	default: xyz = "??"; ok = 0;
	113	}
	114	sprintf (buf, xyz);
	115
	116	if (AVR_UNDEF_P (insn))
	117	sprintf (comment, _("undefined"));
	118	}
bab84c47 DC	119	break;
	120
	121	case 'z':
	122	*buf++ = 'Z';
	123	if (insn & 0x1)
	124	*buf++ = '+';
	125	*buf = '\0';
463f102c DC	126	if (AVR_UNDEF_P (insn))
463f102c DC	127	sprintf (comment, _("undefined"));
bab84c47 DC	128	break;
	129
	130	case 'b':
	131	{
463f102c	132	unsigned int x;
bab84c47 DC	133
	134	x = (insn & 7);
	135	x \|= (insn >> 7) & (3 << 3);
	136	x \|= (insn >> 8) & (1 << 5);
	137
	138	if (insn & 0x8)
	139	*buf++ = 'Y';
	140	else
	141	*buf++ = 'Z';
	142	sprintf (buf, "+%d", x);
	143	sprintf (comment, "0x%02x", x);
	144	}
	145	break;
	146
	147	case 'h':
8776c5fe DC	148	sprintf (buf, "0x%x",
8776c5fe DC	149	((((insn & 1) \| ((insn & 0x1f0) >> 3)) << 16) \| insn2) * 2);
bab84c47 DC	150	break;
	151
	152	case 'L':
	153	{
	154	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	155	sprintf (buf, ".%+-8d", rel_addr);
	156	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	157	}
	158	break;
	159
	160	case 'l':
	161	{
	162	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	163	sprintf (buf, ".%+-8d", rel_addr);
	164	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	165	}
	166	break;
	167
	168	case 'i':
	169	sprintf (buf, "0x%04X", insn2);
	170	break;
	171
	172	case 'M':
	173	sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	174	sprintf (comment, "%d", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	175	break;
	176
	177	case 'n':
463f102c DC	178	sprintf (buf, "??");
	179	fprintf (stderr, _("Internal disassembler error"));
	180	ok = 0;
bab84c47 DC	181	break;
	182
	183	case 'K':
463f102c DC	184	{
	185	unsigned int x;
	186
	187	x = (insn & 0xf) \| ((insn >> 2) & 0x30);
	188	sprintf (buf, "0x%02x", x);
	189	sprintf (comment, "%d", x);
	190	}
bab84c47 DC	191	break;
	192
	193	case 's':
	194	sprintf (buf, "%d", insn & 7);
	195	break;
	196
	197	case 'S':
	198	sprintf (buf, "%d", (insn >> 4) & 7);
	199	break;
	200
	201	case 'P':
	202	{
	203	unsigned int x;
	204	x = (insn & 0xf);
	205	x \|= (insn >> 5) & 0x30;
	206	sprintf (buf, "0x%02x", x);
	207	sprintf (comment, "%d", x);
	208	}
	209	break;
	210
	211	case 'p':
	212	{
	213	unsigned int x;
	214
	215	x = (insn >> 3) & 0x1f;
	216	sprintf (buf, "0x%02x", x);
	217	sprintf (comment, "%d", x);
	218	}
	219	break;
	220
	221	case '?':
	222	*buf = '\0';
	223	break;
	224
	225	default:
463f102c DC	226	sprintf (buf, "??");
	227	fprintf (stderr, _("unknown constraint `%c'"), constraint);
	228	ok = 0;
bab84c47	229	}
463f102c DC	230
463f102c DC	231	return ok;
adde6300 AM	232	}
adde6300 AM	233
bab84c47	234	static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
adde6300	235
bab84c47	236	static unsigned short
adde6300 AM	237	avrdis_opcode (addr, info)
	238	bfd_vma addr;
	239	disassemble_info *info;
	240	{
	241	bfd_byte buffer[2];
	242	int status;
	243	status = info->read_memory_func(addr, buffer, 2, info);
	244	if (status != 0)
	245	{
	246	info->memory_error_func(status, addr, info);
	247	return -1;
	248	}
	249	return bfd_getl16 (buffer);
	250	}
	251
	252
	253	int
	254	print_insn_avr(addr, info)
	255	bfd_vma addr;
	256	disassemble_info *info;
	257	{
bab84c47	258	unsigned int insn, insn2;
11041102 KD	259	const struct avr_opcodes_s *opcode;
11041102 KD	260	static unsigned int *maskptr;
adde6300 AM	261	void *stream = info->stream;
adde6300 AM	262	fprintf_ftype prin = info->fprintf_func;
11041102	263	static unsigned int *avr_bin_masks;
bab84c47	264	static int initialized;
adde6300	265	int cmd_len = 2;
463f102c DC	266	int ok = 0;
463f102c DC	267	char op1[20], op2[20], comment1[40], comment2[40];
adde6300	268
bab84c47 DC	269	if (!initialized)
bab84c47 DC	270	{
11041102 KD	271	unsigned int nopcodes;
	272
	273	nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
bab84c47	274
11041102 KD	275	avr_bin_masks = (unsigned int *)
	276	xmalloc (nopcodes * sizeof (unsigned int));
	277
	278	for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	279	opcode->name;
	280	opcode++, maskptr++)
bab84c47 DC	281	{
	282	char * s;
	283	unsigned int bin = 0;
	284	unsigned int mask = 0;
	285
	286	for (s = opcode->opcode; *s; ++s)
	287	{
	288	bin <<= 1;
	289	mask <<= 1;
	290	bin \|= (*s == '1');
	291	mask \|= (s == '1' \|\| s == '0');
	292	}
	293	assert (s - opcode->opcode == 16);
	294	assert (opcode->bin_opcode == bin);
11041102	295	*maskptr = mask;
bab84c47	296	}
11041102 KD	297
11041102 KD	298	initialized = 1;
bab84c47	299	}
adde6300	300
bab84c47 DC	301	insn = avrdis_opcode (addr, info);
bab84c47 DC	302
11041102 KD	303	for (opcode = avr_opcodes, maskptr = avr_bin_masks;
	304	opcode->name;
	305	opcode++, maskptr++)
adde6300	306	{
11041102	307	if ((insn & *maskptr) == opcode->bin_opcode)
bab84c47	308	break;
adde6300	309	}
bab84c47	310
463f102c DC	311	/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
	312	`std b+0,r' as `st b,r' (next entry in the table). */
	313
	314	if (AVR_DISP0_P (insn))
	315	opcode++;
	316
	317	op1[0] = 0;
	318	op2[0] = 0;
	319	comment1[0] = 0;
	320	comment2[0] = 0;
	321
bab84c47	322	if (opcode->name)
adde6300	323	{
bab84c47 DC	324	char *op = opcode->constraints;
bab84c47 DC	325
00d2865b	326	insn2 = 0;
463f102c	327	ok = 1;
bab84c47 DC	328
	329	if (opcode->insn_size > 1)
	330	{
	331	insn2 = avrdis_opcode (addr + 2, info);
	332	cmd_len = 4;
	333	}
	334
	335	if (op && op != '?')
	336	{
	337	int regs = REGISTER_P (*op);
	338
463f102c	339	ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0);
bab84c47	340
463f102c DC	341	if (ok && *(++op) == ',')
	342	ok = avr_operand (insn, insn2, addr, *(++op), op2,
	343	*comment1 ? comment2 : comment1, regs);
bab84c47	344	}
463f102c	345	}
bab84c47	346
463f102c DC	347	if (!ok)
	348	{
	349	/* Unknown opcode, or invalid combination of operands. */
	350	sprintf (op1, "0x%04x", insn);
	351	op2[0] = 0;
	352	sprintf (comment1, "????");
	353	comment2[0] = 0;
	354	}
bab84c47	355
463f102c	356	(*prin) (stream, "%s", ok ? opcode->name : ".word");
bab84c47	357
463f102c DC	358	if (*op1)
463f102c DC	359	(*prin) (stream, "\t%s", op1);
bab84c47	360
463f102c DC	361	if (*op2)
	362	(*prin) (stream, ", %s", op2);
	363
	364	if (*comment1)
	365	(*prin) (stream, "\t; %s", comment1);
	366
	367	if (*comment2)
	368	(*prin) (stream, " %s", comment2);
bab84c47	369
adde6300 AM	370	return cmd_len;
adde6300 AM	371	}