projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
5eb3690e 2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
69b8ea4a 3 Free Software Foundation, Inc.
4b7f6baa 4
9b201bb5
NC		 5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
4b7f6baa 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
4b7f6baa 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
4b7f6baa
CM		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
5eb3690e 22#include "sysdep.h"
4b7f6baa 23#include <stdio.h>
4b7f6baa
CM		 24
25#include "opcode/bfin.h"
26
4b7f6baa
CM		 27#ifndef PRINTF
28#define PRINTF printf
29#endif
30
31#ifndef EXIT
32#define EXIT exit
33#endif
34
35typedef long TIword;
36
b7d48530
NC		 37#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
38#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
39#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
40#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
4b7f6baa
CM		 41
42#include "dis-asm.h"
b7d48530 43
b21c9cb4
BS		 44typedef unsigned int bu32;
45
528c6277
MF		 46static char comment = 0;
47static char parallel = 0;
48
4b7f6baa
CM		 49typedef enum
50{
51 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 52 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
53 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
54 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
55 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 56} const_forms_t;
57
528c6277 58static const struct
4b7f6baa 59{
528c6277
MF		 60 const char *name;
61 const int nbits;
62 const char reloc;
63 const char issigned;
64 const char pcrel;
65 const char scale;
66 const char offset;
67 const char negative;
68 const char positive;
69 const char decimal;
70 const char leading;
71 const char exact;
4b7f6baa
CM		 72} constant_formats[] =
73{
086134ec
BS		 74 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
75 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
82 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
83 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
84 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
85 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
87 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
88 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
90 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
94 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
95 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
97 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
98 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
99 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
100 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
103 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
104 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
106 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
107 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
109 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
111 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
112 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
113 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
115 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
116 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 117};
118
528c6277
MF		 119static const char *
120fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 121{
122 static char buf[60];
123
124 if (constant_formats[cf].reloc)
125 {
126 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
127 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
128 if (constant_formats[cf].pcrel)
129 ea += pc;
130
602427c4
MF		 131 /* truncate to 32-bits for proper symbol lookup/matching */
132 ea = (bu32)ea;
7a360e83 133
602427c4
MF		 134 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
135 {
086134ec
BS		 136 outf->print_address_func (ea, outf);
137 return "";
602427c4
MF		 138 }
139 else
140 {
0af1713e 141 sprintf (buf, "%lx", (unsigned long) x);
086134ec 142 return buf;
602427c4 143 }
4b7f6baa
CM		 144 }
145
146 /* Negative constants have an implied sign bit. */
147 if (constant_formats[cf].negative)
148 {
149 int nb = constant_formats[cf].nbits + 1;
b7d48530 150
4b7f6baa
CM		 151 x = x | (1 << constant_formats[cf].nbits);
152 x = SIGNEXTEND (x, nb);
153 }
154 else
155 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
156
157 if (constant_formats[cf].offset)
158 x += constant_formats[cf].offset;
159
160 if (constant_formats[cf].scale)
161 x <<= constant_formats[cf].scale;
162
086134ec 163 if (constant_formats[cf].decimal)
5de10af0 164 sprintf (buf, "%*li", constant_formats[cf].leading, x);
4b7f6baa 165 else
086134ec
BS		 166 {
167 if (constant_formats[cf].issigned && x < 0)
168 sprintf (buf, "-0x%x", abs (x));
169 else
0af1713e 170 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 171 }
4b7f6baa
CM		 172
173 return buf;
174}
175
b21c9cb4
BS		 176static bu32
177fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
178{
179 if (0 && constant_formats[cf].reloc)
180 {
181 bu32 ea = (((constant_formats[cf].pcrel
086134ec
BS		 182 ? SIGNEXTEND (x, constant_formats[cf].nbits)
183 : x) + constant_formats[cf].offset)
184 << constant_formats[cf].scale);
b21c9cb4 185 if (constant_formats[cf].pcrel)
086134ec 186 ea += pc;
b21c9cb4
BS		 187
188 return ea;
189 }
190
191 /* Negative constants have an implied sign bit. */
192 if (constant_formats[cf].negative)
193 {
194 int nb = constant_formats[cf].nbits + 1;
195 x = x | (1 << constant_formats[cf].nbits);
196 x = SIGNEXTEND (x, nb);
197 }
198 else if (constant_formats[cf].issigned)
199 x = SIGNEXTEND (x, constant_formats[cf].nbits);
200
201 x += constant_formats[cf].offset;
202 x <<= constant_formats[cf].scale;
203
204 return x;
205}
206
4b7f6baa
CM		 207enum machine_registers
208{
209 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
210 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
211 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
212 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
213 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
214 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
215 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
216 REG_L2, REG_L3,
217 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
218 REG_AQ, REG_V, REG_VS,
219 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 220 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 221 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
222 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
223 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
224 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
225 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
226 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
227 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
228 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 229 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 230 REG_LASTREG,
231};
232
233enum reg_class
234{
235 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
236 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
237 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
238 rc_sysregs3, rc_allregs,
239 LIM_REG_CLASSES
240};
241
69b8ea4a 242static const char * const reg_names[] =
4b7f6baa
CM		 243{
244 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
245 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
246 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
247 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 248 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 249 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
250 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
251 "L2", "L3",
252 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
253 "AQ", "V", "VS",
254 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 255 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 256 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
257 "RETE", "EMUDAT",
258 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
259 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
260 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
261 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
262 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
263 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
264 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 265 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 266 "LASTREG",
267 0
268};
269
270#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
271
272/* RL(0..7). */
69b8ea4a 273static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 274{
275 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
276};
277
b7d48530 278#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 279
280/* RH(0..7). */
69b8ea4a 281static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 282{
283 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
284};
285
b7d48530 286#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 287
288/* R(0..7). */
69b8ea4a 289static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 290{
291 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
292};
293
b7d48530 294#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 295
296/* R BYTE(0..7). */
69b8ea4a 297static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 298{
299 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
300};
301
b7d48530 302#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 303
304/* P(0..5) SP FP. */
69b8ea4a 305static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 306{
307 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
308};
309
b7d48530
NC		 310#define pregs(x) REGNAME (decode_pregs[(x) & 7])
311#define spfp(x) REGNAME (decode_spfp[(x) & 1])
602427c4 312#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
b7d48530
NC		 313#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
314#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
315#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 316
317/* I(0..3). */
69b8ea4a 318static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 319{
320 REG_I0, REG_I1, REG_I2, REG_I3,
321};
322
b7d48530 323#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 324
325/* M(0..3). */
69b8ea4a 326static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 327{
328 REG_M0, REG_M1, REG_M2, REG_M3,
329};
330
b7d48530
NC		 331#define mregs(x) REGNAME (decode_mregs[(x) & 3])
332#define bregs(x) REGNAME (decode_bregs[(x) & 3])
333#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 334
335/* dregs pregs. */
69b8ea4a 336static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 337{
338 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
339 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
340};
341
b7d48530 342#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 343
344/* [dregs pregs]. */
69b8ea4a 345static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 346{
347 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
348 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
349};
350
602427c4 351#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
4b7f6baa
CM		 352
353/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 354static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 355{
356 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
357 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
358 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
359 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
360};
361
602427c4 362#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
4b7f6baa
CM		 363
364/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 365static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 366{
367 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
368 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
369 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
370 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
371};
372
602427c4
MF		 373#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
374
4b7f6baa 375/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 376static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 377{
378 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
379 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 380 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 381 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
382};
383
602427c4 384#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
4b7f6baa 385
69b8ea4a 386static const enum machine_registers decode_statbits[] =
4b7f6baa 387{
22215ae0
MF		 388 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
389 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
390 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
391 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
392 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
393 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
394 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
395 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 396};
397
ad15c38e 398#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 399
400/* LC0 LC1. */
69b8ea4a 401static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 402{
403 REG_LC0, REG_LC1,
404};
405
b7d48530
NC		 406#define counters(x) REGNAME (decode_counters[(x) & 1])
407#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 408
409/* [dregs pregs (iregs mregs) (bregs lregs)
410 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 411static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 412{
413 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
414 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
415 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
416 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 417 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 418 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
419 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 420 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
421 REG_LASTREG,
4b7f6baa
CM		 422};
423
50e2162a
MF		 424#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
425#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 426#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 427#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
428#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 429#define IS_SYSREG(g,r) \
430 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 431#define IS_RESERVEDREG(g,r) \
432 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
433
434#define allreg(r,g) (!IS_RESERVEDREG (g, r))
435#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 436
602427c4 437#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
b7d48530 438#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 439#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 440#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
441#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
442#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
443#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
444#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
445#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
446#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
447#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
448#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 449#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 450#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
451#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
452#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
453#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
454#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
455#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
456#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
457#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
458#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
459#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 460#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 461#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
462#define imm3(x) fmtconst (c_imm3, x, 0, outf)
463#define imm4(x) fmtconst (c_imm4, x, 0, outf)
464#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
465#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 466#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 467#define imm6(x) fmtconst (c_imm6, x, 0, outf)
468#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 469#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 470#define imm8(x) fmtconst (c_imm8, x, 0, outf)
471#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
472#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 473#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 474#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 475#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 476#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
477#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 478#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
479#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 480
481/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 482#ifndef OUTS
500cccad 483#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
4b7f6baa
CM		 484#endif
485
4b7f6baa
CM		 486static void
487amod0 (int s0, int x0, disassemble_info *outf)
488{
b7d48530 489 if (s0 == 1 && x0 == 0)
086134ec 490 OUTS (outf, " (S)");
4b7f6baa 491 else if (s0 == 0 && x0 == 1)
086134ec 492 OUTS (outf, " (CO)");
4b7f6baa 493 else if (s0 == 1 && x0 == 1)
086134ec 494 OUTS (outf, " (SCO)");
4b7f6baa
CM		 495}
496
497static void
498amod1 (int s0, int x0, disassemble_info *outf)
499{
500 if (s0 == 0 && x0 == 0)
086134ec 501 OUTS (outf, " (NS)");
4b7f6baa 502 else if (s0 == 1 && x0 == 0)
086134ec 503 OUTS (outf, " (S)");
4b7f6baa
CM		 504}
505
506static void
507amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
508{
b7d48530 509 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 510 OUTS (outf, " (S)");
4b7f6baa 511 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 512 OUTS (outf, " (CO)");
4b7f6baa 513 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 514 OUTS (outf, " (SCO)");
4b7f6baa 515 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 516 OUTS (outf, " (ASR)");
4b7f6baa 517 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 518 OUTS (outf, " (S, ASR)");
4b7f6baa 519 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 520 OUTS (outf, " (CO, ASR)");
4b7f6baa 521 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 522 OUTS (outf, " (SCO, ASR)");
4b7f6baa 523 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 524 OUTS (outf, " (ASL)");
4b7f6baa 525 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 526 OUTS (outf, " (S, ASL)");
4b7f6baa 527 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 528 OUTS (outf, " (CO, ASL)");
4b7f6baa 529 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 530 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 531}
532
533static void
534searchmod (int r0, disassemble_info *outf)
535{
b7d48530
NC		 536 if (r0 == 0)
537 OUTS (outf, "GT");
538 else if (r0 == 1)
539 OUTS (outf, "GE");
540 else if (r0 == 2)
541 OUTS (outf, "LT");
542 else if (r0 == 3)
543 OUTS (outf, "LE");
4b7f6baa
CM		 544}
545
546static void
547aligndir (int r0, disassemble_info *outf)
548{
b7d48530 549 if (r0 == 1)
086134ec 550 OUTS (outf, " (R)");
4b7f6baa
CM		 551}
552
553static int
602427c4 554decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 555{
528c6277 556 const char *s0, *s1;
4b7f6baa
CM		 557
558 if (h0)
559 s0 = dregs_hi (src0);
560 else
561 s0 = dregs_lo (src0);
562
563 if (h1)
564 s1 = dregs_hi (src1);
565 else
566 s1 = dregs_lo (src1);
567
568 OUTS (outf, s0);
569 OUTS (outf, " * ");
570 OUTS (outf, s1);
571 return 0;
572}
573
574static int
602427c4 575decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 576{
528c6277
MF		 577 const char *a;
578 const char *sop = "<unknown op>";
4b7f6baa
CM		 579
580 if (which)
086134ec 581 a = "A1";
4b7f6baa 582 else
086134ec 583 a = "A0";
4b7f6baa
CM		 584
585 if (op == 3)
586 {
587 OUTS (outf, a);
588 return 0;
589 }
590
591 switch (op)
592 {
086134ec
BS		 593 case 0: sop = " = "; break;
594 case 1: sop = " += "; break;
595 case 2: sop = " -= "; break;
b7d48530 596 default: break;
4b7f6baa
CM		 597 }
598
599 OUTS (outf, a);
4b7f6baa 600 OUTS (outf, sop);
4b7f6baa
CM		 601 decode_multfunc (h0, h1, src0, src1, outf);
602
603 return 0;
604}
605
606static void
607decode_optmode (int mod, int MM, disassemble_info *outf)
608{
609 if (mod == 0 && MM == 0)
610 return;
611
612 OUTS (outf, " (");
613
614 if (MM && !mod)
615 {
616 OUTS (outf, "M)");
617 return;
618 }
619
620 if (MM)
621 OUTS (outf, "M, ");
b7d48530 622
4b7f6baa
CM		 623 if (mod == M_S2RND)
624 OUTS (outf, "S2RND");
625 else if (mod == M_T)
626 OUTS (outf, "T");
627 else if (mod == M_W32)
628 OUTS (outf, "W32");
629 else if (mod == M_FU)
630 OUTS (outf, "FU");
631 else if (mod == M_TFU)
632 OUTS (outf, "TFU");
633 else if (mod == M_IS)
634 OUTS (outf, "IS");
635 else if (mod == M_ISS2)
636 OUTS (outf, "ISS2");
637 else if (mod == M_IH)
638 OUTS (outf, "IH");
639 else if (mod == M_IU)
640 OUTS (outf, "IU");
641 else
642 abort ();
643
644 OUTS (outf, ")");
645}
b7d48530 646
e5bc4265 647static struct saved_state
b21c9cb4
BS		 648{
649 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
e5bc4265 650 bu32 ax[2], aw[2];
b21c9cb4 651 bu32 lt[2], lc[2], lb[2];
e5bc4265 652 bu32 rets;
602427c4 653} saved_state;
b21c9cb4
BS		 654
655#define DREG(x) (saved_state.dpregs[x])
602427c4 656#define GREG(x, i) DPREG ((x) | ((i) << 3))
b21c9cb4
BS		 657#define DPREG(x) (saved_state.dpregs[x])
658#define DREG(x) (saved_state.dpregs[x])
602427c4 659#define PREG(x) (saved_state.dpregs[(x) + 8])
b21c9cb4
BS		 660#define SPREG PREG (6)
661#define FPREG PREG (7)
662#define IREG(x) (saved_state.iregs[x])
663#define MREG(x) (saved_state.mregs[x])
664#define BREG(x) (saved_state.bregs[x])
665#define LREG(x) (saved_state.lregs[x])
e5bc4265
MF		 666#define AXREG(x) (saved_state.ax[x])
667#define AWREG(x) (saved_state.aw[x])
668#define LCREG(x) (saved_state.lc[x])
669#define LTREG(x) (saved_state.lt[x])
670#define LBREG(x) (saved_state.lb[x])
b21c9cb4 671#define RETSREG (saved_state.rets)
b21c9cb4
BS		 672
673static bu32 *
674get_allreg (int grp, int reg)
675{
676 int fullreg = (grp << 3) | reg;
677 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
678 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
679 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
680 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
681 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
682 , , , , , , , ,
683 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
684 REG_CYCLES2,
685 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
686 REG_LASTREG */
687 switch (fullreg >> 2)
688 {
e5bc4265
MF		 689 case 0: case 1: return &DREG (reg);
690 case 2: case 3: return &PREG (reg);
691 case 4: return &IREG (reg & 3);
692 case 5: return &MREG (reg & 3);
693 case 6: return &BREG (reg & 3);
694 case 7: return &LREG (reg & 3);
b21c9cb4
BS		 695 default:
696 switch (fullreg)
086134ec 697 {
e5bc4265
MF		 698 case 32: return &AXREG (0);
699 case 33: return &AWREG (0);
700 case 34: return &AXREG (1);
701 case 35: return &AWREG (1);
702 case 39: return &RETSREG;
703 case 48: return &LCREG (0);
704 case 49: return &LTREG (0);
705 case 50: return &LBREG (0);
706 case 51: return &LCREG (1);
707 case 52: return &LTREG (1);
708 case 53: return &LBREG (1);
086134ec 709 }
b21c9cb4 710 }
e5bc4265 711 abort ();
b21c9cb4
BS		 712}
713
4b7f6baa
CM		 714static int
715decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
716{
b7d48530
NC		 717 /* ProgCtrl
718 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
719 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
720 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 721 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
722 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
723
724 if (prgfunc == 0 && poprnd == 0)
b7d48530 725 OUTS (outf, "NOP");
219b747a
MF		 726 else if (parallel)
727 return 0;
4b7f6baa 728 else if (prgfunc == 1 && poprnd == 0)
b7d48530 729 OUTS (outf, "RTS");
4b7f6baa 730 else if (prgfunc == 1 && poprnd == 1)
b7d48530 731 OUTS (outf, "RTI");
4b7f6baa 732 else if (prgfunc == 1 && poprnd == 2)
b7d48530 733 OUTS (outf, "RTX");
4b7f6baa 734 else if (prgfunc == 1 && poprnd == 3)
b7d48530 735 OUTS (outf, "RTN");
4b7f6baa 736 else if (prgfunc == 1 && poprnd == 4)
b7d48530 737 OUTS (outf, "RTE");
4b7f6baa 738 else if (prgfunc == 2 && poprnd == 0)
b7d48530 739 OUTS (outf, "IDLE");
4b7f6baa 740 else if (prgfunc == 2 && poprnd == 3)
b7d48530 741 OUTS (outf, "CSYNC");
4b7f6baa 742 else if (prgfunc == 2 && poprnd == 4)
b7d48530 743 OUTS (outf, "SSYNC");
4b7f6baa 744 else if (prgfunc == 2 && poprnd == 5)
b7d48530 745 OUTS (outf, "EMUEXCPT");
50e2162a 746 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 747 {
086134ec 748 OUTS (outf, "CLI ");
4b7f6baa 749 OUTS (outf, dregs (poprnd));
4b7f6baa 750 }
50e2162a 751 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 752 {
086134ec 753 OUTS (outf, "STI ");
4b7f6baa 754 OUTS (outf, dregs (poprnd));
4b7f6baa 755 }
50e2162a 756 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 757 {
086134ec 758 OUTS (outf, "JUMP (");
4b7f6baa
CM		 759 OUTS (outf, pregs (poprnd));
760 OUTS (outf, ")");
4b7f6baa 761 }
50e2162a 762 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 763 {
086134ec 764 OUTS (outf, "CALL (");
4b7f6baa
CM		 765 OUTS (outf, pregs (poprnd));
766 OUTS (outf, ")");
4b7f6baa 767 }
50e2162a 768 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 769 {
086134ec 770 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 771 OUTS (outf, pregs (poprnd));
772 OUTS (outf, ")");
4b7f6baa 773 }
50e2162a 774 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 775 {
086134ec 776 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 777 OUTS (outf, pregs (poprnd));
778 OUTS (outf, ")");
4b7f6baa
CM		 779 }
780 else if (prgfunc == 9)
781 {
086134ec 782 OUTS (outf, "RAISE ");
4b7f6baa 783 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 784 }
785 else if (prgfunc == 10)
786 {
086134ec 787 OUTS (outf, "EXCPT ");
4b7f6baa 788 OUTS (outf, uimm4 (poprnd));
4b7f6baa 789 }
219b747a 790 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 791 {
086134ec 792 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 793 OUTS (outf, pregs (poprnd));
794 OUTS (outf, ")");
4b7f6baa
CM		 795 }
796 else
b7d48530
NC		 797 return 0;
798 return 2;
4b7f6baa
CM		 799}
800
801static int
802decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
803{
b7d48530
NC		 804 /* CaCTRL
805 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
806 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
807 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 808 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
809 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
810 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
811
219b747a
MF		 812 if (parallel)
813 return 0;
814
4b7f6baa
CM		 815 if (a == 0 && op == 0)
816 {
4b7f6baa
CM		 817 OUTS (outf, "PREFETCH[");
818 OUTS (outf, pregs (reg));
819 OUTS (outf, "]");
4b7f6baa
CM		 820 }
821 else if (a == 0 && op == 1)
822 {
4b7f6baa
CM		 823 OUTS (outf, "FLUSHINV[");
824 OUTS (outf, pregs (reg));
825 OUTS (outf, "]");
4b7f6baa
CM		 826 }
827 else if (a == 0 && op == 2)
828 {
4b7f6baa
CM		 829 OUTS (outf, "FLUSH[");
830 OUTS (outf, pregs (reg));
831 OUTS (outf, "]");
4b7f6baa
CM		 832 }
833 else if (a == 0 && op == 3)
834 {
4b7f6baa
CM		 835 OUTS (outf, "IFLUSH[");
836 OUTS (outf, pregs (reg));
837 OUTS (outf, "]");
4b7f6baa
CM		 838 }
839 else if (a == 1 && op == 0)
840 {
4b7f6baa
CM		 841 OUTS (outf, "PREFETCH[");
842 OUTS (outf, pregs (reg));
843 OUTS (outf, "++]");
4b7f6baa
CM		 844 }
845 else if (a == 1 && op == 1)
846 {
4b7f6baa
CM		 847 OUTS (outf, "FLUSHINV[");
848 OUTS (outf, pregs (reg));
849 OUTS (outf, "++]");
4b7f6baa
CM		 850 }
851 else if (a == 1 && op == 2)
852 {
4b7f6baa
CM		 853 OUTS (outf, "FLUSH[");
854 OUTS (outf, pregs (reg));
855 OUTS (outf, "++]");
4b7f6baa
CM		 856 }
857 else if (a == 1 && op == 3)
858 {
4b7f6baa
CM		 859 OUTS (outf, "IFLUSH[");
860 OUTS (outf, pregs (reg));
861 OUTS (outf, "++]");
4b7f6baa
CM		 862 }
863 else
b7d48530
NC		 864 return 0;
865 return 2;
4b7f6baa
CM		 866}
867
868static int
869decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
870{
b7d48530
NC		 871 /* PushPopReg
872 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
873 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
874 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 875 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
876 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
877 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
878
219b747a
MF		 879 if (parallel)
880 return 0;
881
50e2162a 882 if (W == 0 && mostreg (reg, grp))
4b7f6baa 883 {
4b7f6baa
CM		 884 OUTS (outf, allregs (reg, grp));
885 OUTS (outf, " = [SP++]");
4b7f6baa 886 }
219b747a 887 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 888 {
4b7f6baa
CM		 889 OUTS (outf, "[--SP] = ");
890 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 891 }
892 else
b7d48530
NC		 893 return 0;
894 return 2;
4b7f6baa
CM		 895}
896
897static int
898decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
899{
b7d48530
NC		 900 /* PushPopMultiple
901 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
902 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 904 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
905 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
906 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
907 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
908 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 909
219b747a
MF		 910 if (parallel)
911 return 0;
912
775f1cf0
MF		 913 if (pr > 5)
914 return 0;
915
4b7f6baa
CM		 916 if (W == 1 && d == 1 && p == 1)
917 {
4b7f6baa 918 OUTS (outf, "[--SP] = (R7:");
086134ec 919 OUTS (outf, imm5d (dr));
4b7f6baa 920 OUTS (outf, ", P5:");
086134ec 921 OUTS (outf, imm5d (pr));
4b7f6baa 922 OUTS (outf, ")");
4b7f6baa 923 }
219b747a 924 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 925 {
4b7f6baa 926 OUTS (outf, "[--SP] = (R7:");
086134ec 927 OUTS (outf, imm5d (dr));
4b7f6baa 928 OUTS (outf, ")");
4b7f6baa 929 }
219b747a 930 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 931 {
4b7f6baa 932 OUTS (outf, "[--SP] = (P5:");
086134ec 933 OUTS (outf, imm5d (pr));
4b7f6baa 934 OUTS (outf, ")");
4b7f6baa
CM		 935 }
936 else if (W == 0 && d == 1 && p == 1)
937 {
4b7f6baa 938 OUTS (outf, "(R7:");
086134ec 939 OUTS (outf, imm5d (dr));
4b7f6baa 940 OUTS (outf, ", P5:");
086134ec 941 OUTS (outf, imm5d (pr));
4b7f6baa 942 OUTS (outf, ") = [SP++]");
4b7f6baa 943 }
219b747a 944 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 945 {
4b7f6baa 946 OUTS (outf, "(R7:");
086134ec 947 OUTS (outf, imm5d (dr));
4b7f6baa 948 OUTS (outf, ") = [SP++]");
4b7f6baa 949 }
219b747a 950 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 951 {
4b7f6baa 952 OUTS (outf, "(P5:");
086134ec 953 OUTS (outf, imm5d (pr));
4b7f6baa 954 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 955 }
956 else
b7d48530
NC		 957 return 0;
958 return 2;
4b7f6baa
CM		 959}
960
961static int
962decode_ccMV_0 (TIword iw0, disassemble_info *outf)
963{
b7d48530
NC		 964 /* ccMV
965 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
966 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
967 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 968 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
969 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
970 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
971 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
972 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
973
219b747a
MF		 974 if (parallel)
975 return 0;
976
4b7f6baa
CM		 977 if (T == 1)
978 {
4b7f6baa
CM		 979 OUTS (outf, "IF CC ");
980 OUTS (outf, gregs (dst, d));
981 OUTS (outf, " = ");
982 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 983 }
984 else if (T == 0)
985 {
086134ec 986 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 987 OUTS (outf, gregs (dst, d));
988 OUTS (outf, " = ");
989 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 990 }
991 else
b7d48530
NC		 992 return 0;
993 return 2;
4b7f6baa
CM		 994}
995
996static int
997decode_CCflag_0 (TIword iw0, disassemble_info *outf)
998{
b7d48530
NC		 999 /* CCflag
1000 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1001 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1003 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1004 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1005 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1006 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1007 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1008
219b747a
MF		 1009 if (parallel)
1010 return 0;
1011
4b7f6baa
CM		 1012 if (opc == 0 && I == 0 && G == 0)
1013 {
086134ec 1014 OUTS (outf, "CC = ");
4b7f6baa 1015 OUTS (outf, dregs (x));
086134ec 1016 OUTS (outf, " == ");
4b7f6baa 1017 OUTS (outf, dregs (y));
4b7f6baa
CM		 1018 }
1019 else if (opc == 1 && I == 0 && G == 0)
1020 {
086134ec 1021 OUTS (outf, "CC = ");
4b7f6baa 1022 OUTS (outf, dregs (x));
086134ec 1023 OUTS (outf, " < ");
4b7f6baa 1024 OUTS (outf, dregs (y));
4b7f6baa
CM		 1025 }
1026 else if (opc == 2 && I == 0 && G == 0)
1027 {
086134ec 1028 OUTS (outf, "CC = ");
4b7f6baa 1029 OUTS (outf, dregs (x));
086134ec 1030 OUTS (outf, " <= ");
4b7f6baa 1031 OUTS (outf, dregs (y));
4b7f6baa
CM		 1032 }
1033 else if (opc == 3 && I == 0 && G == 0)
1034 {
086134ec 1035 OUTS (outf, "CC = ");
4b7f6baa 1036 OUTS (outf, dregs (x));
086134ec 1037 OUTS (outf, " < ");
4b7f6baa 1038 OUTS (outf, dregs (y));
086134ec 1039 OUTS (outf, " (IU)");
4b7f6baa
CM		 1040 }
1041 else if (opc == 4 && I == 0 && G == 0)
1042 {
086134ec 1043 OUTS (outf, "CC = ");
4b7f6baa 1044 OUTS (outf, dregs (x));
086134ec 1045 OUTS (outf, " <= ");
4b7f6baa 1046 OUTS (outf, dregs (y));
086134ec 1047 OUTS (outf, " (IU)");
4b7f6baa
CM		 1048 }
1049 else if (opc == 0 && I == 1 && G == 0)
1050 {
086134ec 1051 OUTS (outf, "CC = ");
4b7f6baa 1052 OUTS (outf, dregs (x));
086134ec 1053 OUTS (outf, " == ");
4b7f6baa 1054 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1055 }
1056 else if (opc == 1 && I == 1 && G == 0)
1057 {
086134ec 1058 OUTS (outf, "CC = ");
4b7f6baa 1059 OUTS (outf, dregs (x));
086134ec 1060 OUTS (outf, " < ");
4b7f6baa 1061 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1062 }
1063 else if (opc == 2 && I == 1 && G == 0)
1064 {
086134ec 1065 OUTS (outf, "CC = ");
4b7f6baa 1066 OUTS (outf, dregs (x));
086134ec 1067 OUTS (outf, " <= ");
4b7f6baa 1068 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1069 }
1070 else if (opc == 3 && I == 1 && G == 0)
1071 {
086134ec 1072 OUTS (outf, "CC = ");
4b7f6baa 1073 OUTS (outf, dregs (x));
086134ec 1074 OUTS (outf, " < ");
4b7f6baa 1075 OUTS (outf, uimm3 (y));
086134ec 1076 OUTS (outf, " (IU)");
4b7f6baa
CM		 1077 }
1078 else if (opc == 4 && I == 1 && G == 0)
1079 {
086134ec 1080 OUTS (outf, "CC = ");
4b7f6baa 1081 OUTS (outf, dregs (x));
086134ec 1082 OUTS (outf, " <= ");
4b7f6baa 1083 OUTS (outf, uimm3 (y));
086134ec 1084 OUTS (outf, " (IU)");
4b7f6baa
CM		 1085 }
1086 else if (opc == 0 && I == 0 && G == 1)
1087 {
086134ec 1088 OUTS (outf, "CC = ");
4b7f6baa 1089 OUTS (outf, pregs (x));
086134ec 1090 OUTS (outf, " == ");
4b7f6baa 1091 OUTS (outf, pregs (y));
4b7f6baa
CM		 1092 }
1093 else if (opc == 1 && I == 0 && G == 1)
1094 {
086134ec 1095 OUTS (outf, "CC = ");
4b7f6baa 1096 OUTS (outf, pregs (x));
086134ec 1097 OUTS (outf, " < ");
4b7f6baa 1098 OUTS (outf, pregs (y));
4b7f6baa
CM		 1099 }
1100 else if (opc == 2 && I == 0 && G == 1)
1101 {
086134ec 1102 OUTS (outf, "CC = ");
4b7f6baa 1103 OUTS (outf, pregs (x));
086134ec 1104 OUTS (outf, " <= ");
4b7f6baa 1105 OUTS (outf, pregs (y));
4b7f6baa
CM		 1106 }
1107 else if (opc == 3 && I == 0 && G == 1)
1108 {
086134ec 1109 OUTS (outf, "CC = ");
4b7f6baa 1110 OUTS (outf, pregs (x));
086134ec 1111 OUTS (outf, " < ");
4b7f6baa 1112 OUTS (outf, pregs (y));
086134ec 1113 OUTS (outf, " (IU)");
4b7f6baa
CM		 1114 }
1115 else if (opc == 4 && I == 0 && G == 1)
1116 {
086134ec 1117 OUTS (outf, "CC = ");
4b7f6baa 1118 OUTS (outf, pregs (x));
086134ec 1119 OUTS (outf, " <= ");
4b7f6baa 1120 OUTS (outf, pregs (y));
086134ec 1121 OUTS (outf, " (IU)");
4b7f6baa
CM		 1122 }
1123 else if (opc == 0 && I == 1 && G == 1)
1124 {
086134ec 1125 OUTS (outf, "CC = ");
4b7f6baa 1126 OUTS (outf, pregs (x));
086134ec 1127 OUTS (outf, " == ");
4b7f6baa 1128 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1129 }
1130 else if (opc == 1 && I == 1 && G == 1)
1131 {
086134ec 1132 OUTS (outf, "CC = ");
4b7f6baa 1133 OUTS (outf, pregs (x));
086134ec 1134 OUTS (outf, " < ");
4b7f6baa 1135 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1136 }
1137 else if (opc == 2 && I == 1 && G == 1)
1138 {
086134ec 1139 OUTS (outf, "CC = ");
4b7f6baa 1140 OUTS (outf, pregs (x));
086134ec 1141 OUTS (outf, " <= ");
4b7f6baa 1142 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1143 }
1144 else if (opc == 3 && I == 1 && G == 1)
1145 {
086134ec 1146 OUTS (outf, "CC = ");
4b7f6baa 1147 OUTS (outf, pregs (x));
086134ec 1148 OUTS (outf, " < ");
4b7f6baa 1149 OUTS (outf, uimm3 (y));
086134ec 1150 OUTS (outf, " (IU)");
4b7f6baa
CM		 1151 }
1152 else if (opc == 4 && I == 1 && G == 1)
1153 {
086134ec 1154 OUTS (outf, "CC = ");
4b7f6baa 1155 OUTS (outf, pregs (x));
086134ec 1156 OUTS (outf, " <= ");
4b7f6baa 1157 OUTS (outf, uimm3 (y));
086134ec 1158 OUTS (outf, " (IU)");
4b7f6baa 1159 }
219b747a 1160 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1161 OUTS (outf, "CC = A0 == A1");
b7d48530 1162
219b747a 1163 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1164 OUTS (outf, "CC = A0 < A1");
b7d48530 1165
219b747a 1166 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1167 OUTS (outf, "CC = A0 <= A1");
b7d48530 1168
4b7f6baa 1169 else
b7d48530
NC		 1170 return 0;
1171 return 2;
4b7f6baa
CM		 1172}
1173
1174static int
1175decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1176{
b7d48530
NC		 1177 /* CC2dreg
1178 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1179 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1180 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1181 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1182 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1183
219b747a
MF		 1184 if (parallel)
1185 return 0;
1186
4b7f6baa
CM		 1187 if (op == 0)
1188 {
4b7f6baa 1189 OUTS (outf, dregs (reg));
086134ec 1190 OUTS (outf, " = CC");
4b7f6baa
CM		 1191 }
1192 else if (op == 1)
1193 {
086134ec 1194 OUTS (outf, "CC = ");
4b7f6baa 1195 OUTS (outf, dregs (reg));
4b7f6baa 1196 }
50e2162a 1197 else if (op == 3 && reg == 0)
086134ec 1198 OUTS (outf, "CC = !CC");
4b7f6baa 1199 else
b7d48530
NC		 1200 return 0;
1201
1202 return 2;
4b7f6baa
CM		 1203}
1204
1205static int
1206decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1207{
b7d48530
NC		 1208 /* CC2stat
1209 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1211 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1212 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1213 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1214 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1215
b2459327 1216 const char *bitname = statbits (cbit);
219b747a
MF		 1217
1218 if (parallel)
1219 return 0;
1220
b2459327
MF		 1221 if (decode_statbits[cbit] == REG_LASTREG)
1222 {
1223 /* All ASTAT bits except CC may be operated on in hardware, but may
1224 not have a dedicated insn, so still decode "valid" insns. */
1225 static char bitnames[64];
1226 if (cbit != 5)
1227 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1228 else
219b747a
MF		 1229 return 0;
1230
b2459327
MF		 1231 bitname = bitnames;
1232 }
1233
4b7f6baa
CM		 1234 if (op == 0 && D == 0)
1235 {
4b7f6baa 1236 OUTS (outf, "CC = ");
b2459327 1237 OUTS (outf, bitname);
4b7f6baa
CM		 1238 }
1239 else if (op == 1 && D == 0)
1240 {
086134ec 1241 OUTS (outf, "CC |= ");
b2459327 1242 OUTS (outf, bitname);
4b7f6baa
CM		 1243 }
1244 else if (op == 2 && D == 0)
1245 {
086134ec 1246 OUTS (outf, "CC &= ");
b2459327 1247 OUTS (outf, bitname);
4b7f6baa
CM		 1248 }
1249 else if (op == 3 && D == 0)
1250 {
086134ec 1251 OUTS (outf, "CC ^= ");
b2459327 1252 OUTS (outf, bitname);
4b7f6baa
CM		 1253 }
1254 else if (op == 0 && D == 1)
1255 {
b2459327 1256 OUTS (outf, bitname);
086134ec 1257 OUTS (outf, " = CC");
4b7f6baa
CM		 1258 }
1259 else if (op == 1 && D == 1)
1260 {
b2459327 1261 OUTS (outf, bitname);
086134ec 1262 OUTS (outf, " |= CC");
4b7f6baa
CM		 1263 }
1264 else if (op == 2 && D == 1)
1265 {
b2459327 1266 OUTS (outf, bitname);
086134ec 1267 OUTS (outf, " &= CC");
4b7f6baa
CM		 1268 }
1269 else if (op == 3 && D == 1)
1270 {
b2459327 1271 OUTS (outf, bitname);
086134ec 1272 OUTS (outf, " ^= CC");
4b7f6baa
CM		 1273 }
1274 else
b7d48530
NC		 1275 return 0;
1276
1277 return 2;
4b7f6baa
CM		 1278}
1279
1280static int
1281decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1282{
b7d48530
NC		 1283 /* BRCC
1284 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1285 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1286 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1287 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1288 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1289 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1290
219b747a
MF		 1291 if (parallel)
1292 return 0;
1293
4b7f6baa
CM		 1294 if (T == 1 && B == 1)
1295 {
086134ec 1296 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1297 OUTS (outf, pcrel10 (offset));
086134ec 1298 OUTS (outf, " (BP)");
4b7f6baa
CM		 1299 }
1300 else if (T == 0 && B == 1)
1301 {
086134ec 1302 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1303 OUTS (outf, pcrel10 (offset));
086134ec 1304 OUTS (outf, " (BP)");
4b7f6baa
CM		 1305 }
1306 else if (T == 1)
1307 {
086134ec 1308 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1309 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1310 }
1311 else if (T == 0)
1312 {
086134ec 1313 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1314 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1315 }
1316 else
b7d48530
NC		 1317 return 0;
1318
1319 return 2;
4b7f6baa
CM		 1320}
1321
1322static int
1323decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1324{
b7d48530
NC		 1325 /* UJUMP
1326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1327 | 0 | 0 | 1 | 0 |.offset........................................|
1328 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1329 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1330
219b747a
MF		 1331 if (parallel)
1332 return 0;
1333
086134ec 1334 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1335 OUTS (outf, pcrel12 (offset));
b7d48530 1336 return 2;
4b7f6baa
CM		 1337}
1338
1339static int
1340decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1341{
b7d48530
NC		 1342 /* REGMV
1343 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1344 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1345 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1346 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1347 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1348 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1349 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1350
602427c4 1351 /* Reserved slots cannot be a src/dst. */
35fc57f3
MF		 1352 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1353 goto invalid_move;
1354
1355 /* Standard register moves */
1356 if ((gs < 2) || /* Dregs/Pregs as source */
1357 (gd < 2) || /* Dregs/Pregs as dest */
1358 (gs == 4 && src < 4) || /* Accumulators as source */
1359 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1360 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1361 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1362 goto valid_move;
1363
1364 /* dareg = dareg (IMBL) */
1365 if (gs < 4 && gd < 4)
1366 goto valid_move;
1367
1368 /* USP can be src to sysregs, but not dagregs. */
1369 if ((gs == 7 && src == 0) && (gd >= 4))
1370 goto valid_move;
1371
1372 /* USP can move between genregs (only check Accumulators). */
1373 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1374 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1375 goto valid_move;
1376
1377 /* Still here ? Invalid reg pair. */
1378 invalid_move:
1379 return 0;
c958a8a8 1380
35fc57f3 1381 valid_move:
4b7f6baa 1382 OUTS (outf, allregs (dst, gd));
086134ec 1383 OUTS (outf, " = ");
4b7f6baa 1384 OUTS (outf, allregs (src, gs));
b7d48530 1385 return 2;
4b7f6baa
CM		 1386}
1387
1388static int
1389decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1390{
b7d48530
NC		 1391 /* ALU2op
1392 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1393 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1394 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1395 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1396 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1397 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1398
1399 if (opc == 0)
1400 {
4b7f6baa 1401 OUTS (outf, dregs (dst));
086134ec 1402 OUTS (outf, " >>>= ");
4b7f6baa 1403 OUTS (outf, dregs (src));
4b7f6baa
CM		 1404 }
1405 else if (opc == 1)
1406 {
4b7f6baa 1407 OUTS (outf, dregs (dst));
086134ec 1408 OUTS (outf, " >>= ");
4b7f6baa 1409 OUTS (outf, dregs (src));
4b7f6baa
CM		 1410 }
1411 else if (opc == 2)
1412 {
4b7f6baa 1413 OUTS (outf, dregs (dst));
086134ec 1414 OUTS (outf, " <<= ");
4b7f6baa 1415 OUTS (outf, dregs (src));
4b7f6baa
CM		 1416 }
1417 else if (opc == 3)
1418 {
4b7f6baa 1419 OUTS (outf, dregs (dst));
086134ec 1420 OUTS (outf, " *= ");
4b7f6baa 1421 OUTS (outf, dregs (src));
4b7f6baa
CM		 1422 }
1423 else if (opc == 4)
1424 {
4b7f6baa 1425 OUTS (outf, dregs (dst));
086134ec 1426 OUTS (outf, " = (");
4b7f6baa 1427 OUTS (outf, dregs (dst));
086134ec 1428 OUTS (outf, " + ");
4b7f6baa 1429 OUTS (outf, dregs (src));
086134ec 1430 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1431 }
1432 else if (opc == 5)
1433 {
4b7f6baa 1434 OUTS (outf, dregs (dst));
086134ec 1435 OUTS (outf, " = (");
4b7f6baa 1436 OUTS (outf, dregs (dst));
086134ec 1437 OUTS (outf, " + ");
4b7f6baa 1438 OUTS (outf, dregs (src));
086134ec 1439 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1440 }
1441 else if (opc == 8)
1442 {
086134ec 1443 OUTS (outf, "DIVQ (");
4b7f6baa 1444 OUTS (outf, dregs (dst));
086134ec 1445 OUTS (outf, ", ");
4b7f6baa
CM		 1446 OUTS (outf, dregs (src));
1447 OUTS (outf, ")");
4b7f6baa
CM		 1448 }
1449 else if (opc == 9)
1450 {
086134ec 1451 OUTS (outf, "DIVS (");
4b7f6baa 1452 OUTS (outf, dregs (dst));
086134ec 1453 OUTS (outf, ", ");
4b7f6baa
CM		 1454 OUTS (outf, dregs (src));
1455 OUTS (outf, ")");
4b7f6baa
CM		 1456 }
1457 else if (opc == 10)
1458 {
4b7f6baa 1459 OUTS (outf, dregs (dst));
086134ec 1460 OUTS (outf, " = ");
4b7f6baa 1461 OUTS (outf, dregs_lo (src));
086134ec 1462 OUTS (outf, " (X)");
4b7f6baa
CM		 1463 }
1464 else if (opc == 11)
1465 {
4b7f6baa 1466 OUTS (outf, dregs (dst));
086134ec 1467 OUTS (outf, " = ");
4b7f6baa 1468 OUTS (outf, dregs_lo (src));
086134ec 1469 OUTS (outf, " (Z)");
4b7f6baa
CM		 1470 }
1471 else if (opc == 12)
1472 {
4b7f6baa 1473 OUTS (outf, dregs (dst));
086134ec 1474 OUTS (outf, " = ");
4b7f6baa 1475 OUTS (outf, dregs_byte (src));
086134ec 1476 OUTS (outf, " (X)");
4b7f6baa
CM		 1477 }
1478 else if (opc == 13)
1479 {
4b7f6baa 1480 OUTS (outf, dregs (dst));
086134ec 1481 OUTS (outf, " = ");
4b7f6baa 1482 OUTS (outf, dregs_byte (src));
086134ec 1483 OUTS (outf, " (Z)");
4b7f6baa
CM		 1484 }
1485 else if (opc == 14)
1486 {
4b7f6baa 1487 OUTS (outf, dregs (dst));
086134ec 1488 OUTS (outf, " = -");
4b7f6baa 1489 OUTS (outf, dregs (src));
4b7f6baa
CM		 1490 }
1491 else if (opc == 15)
1492 {
4b7f6baa 1493 OUTS (outf, dregs (dst));
086134ec 1494 OUTS (outf, " =~ ");
4b7f6baa 1495 OUTS (outf, dregs (src));
4b7f6baa
CM		 1496 }
1497 else
b7d48530
NC		 1498 return 0;
1499
1500 return 2;
4b7f6baa
CM		 1501}
1502
1503static int
1504decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1505{
b7d48530
NC		 1506 /* PTR2op
1507 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1508 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1509 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1510 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1511 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1512 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1513
1514 if (opc == 0)
1515 {
4b7f6baa 1516 OUTS (outf, pregs (dst));
086134ec 1517 OUTS (outf, " -= ");
4b7f6baa 1518 OUTS (outf, pregs (src));
4b7f6baa
CM		 1519 }
1520 else if (opc == 1)
1521 {
4b7f6baa 1522 OUTS (outf, pregs (dst));
086134ec 1523 OUTS (outf, " = ");
4b7f6baa 1524 OUTS (outf, pregs (src));
086134ec 1525 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1526 }
1527 else if (opc == 3)
1528 {
4b7f6baa 1529 OUTS (outf, pregs (dst));
086134ec 1530 OUTS (outf, " = ");
4b7f6baa 1531 OUTS (outf, pregs (src));
086134ec 1532 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1533 }
1534 else if (opc == 4)
1535 {
4b7f6baa 1536 OUTS (outf, pregs (dst));
086134ec 1537 OUTS (outf, " = ");
4b7f6baa 1538 OUTS (outf, pregs (src));
086134ec 1539 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1540 }
1541 else if (opc == 5)
1542 {
4b7f6baa 1543 OUTS (outf, pregs (dst));
086134ec 1544 OUTS (outf, " += ");
4b7f6baa 1545 OUTS (outf, pregs (src));
086134ec 1546 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1547 }
1548 else if (opc == 6)
1549 {
4b7f6baa 1550 OUTS (outf, pregs (dst));
086134ec 1551 OUTS (outf, " = (");
4b7f6baa 1552 OUTS (outf, pregs (dst));
086134ec 1553 OUTS (outf, " + ");
4b7f6baa 1554 OUTS (outf, pregs (src));
086134ec 1555 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1556 }
1557 else if (opc == 7)
1558 {
4b7f6baa 1559 OUTS (outf, pregs (dst));
086134ec 1560 OUTS (outf, " = (");
4b7f6baa 1561 OUTS (outf, pregs (dst));
086134ec 1562 OUTS (outf, " + ");
4b7f6baa 1563 OUTS (outf, pregs (src));
086134ec 1564 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1565 }
1566 else
b7d48530
NC		 1567 return 0;
1568
1569 return 2;
4b7f6baa
CM		 1570}
1571
1572static int
1573decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1574{
b7d48530
NC		 1575 /* LOGI2op
1576 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1577 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1578 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1579 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1580 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1581 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1582
219b747a
MF		 1583 if (parallel)
1584 return 0;
1585
4b7f6baa
CM		 1586 if (opc == 0)
1587 {
086134ec 1588 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1589 OUTS (outf, dregs (dst));
086134ec 1590 OUTS (outf, ", ");
4b7f6baa 1591 OUTS (outf, uimm5 (src));
086134ec
BS		 1592 OUTS (outf, ");\t\t/* bit");
1593 OUTS (outf, imm7d (src));
1594 OUTS (outf, " */");
1595 comment = 1;
4b7f6baa
CM		 1596 }
1597 else if (opc == 1)
1598 {
4b7f6baa
CM		 1599 OUTS (outf, "CC = BITTST (");
1600 OUTS (outf, dregs (dst));
086134ec 1601 OUTS (outf, ", ");
4b7f6baa 1602 OUTS (outf, uimm5 (src));
086134ec
BS		 1603 OUTS (outf, ");\t\t/* bit");
1604 OUTS (outf, imm7d (src));
1605 OUTS (outf, " */");
1606 comment = 1;
4b7f6baa
CM		 1607 }
1608 else if (opc == 2)
1609 {
4b7f6baa
CM		 1610 OUTS (outf, "BITSET (");
1611 OUTS (outf, dregs (dst));
086134ec 1612 OUTS (outf, ", ");
4b7f6baa 1613 OUTS (outf, uimm5 (src));
086134ec
BS		 1614 OUTS (outf, ");\t\t/* bit");
1615 OUTS (outf, imm7d (src));
1616 OUTS (outf, " */");
1617 comment = 1;
4b7f6baa
CM		 1618 }
1619 else if (opc == 3)
1620 {
4b7f6baa
CM		 1621 OUTS (outf, "BITTGL (");
1622 OUTS (outf, dregs (dst));
086134ec 1623 OUTS (outf, ", ");
4b7f6baa 1624 OUTS (outf, uimm5 (src));
086134ec
BS		 1625 OUTS (outf, ");\t\t/* bit");
1626 OUTS (outf, imm7d (src));
1627 OUTS (outf, " */");
1628 comment = 1;
4b7f6baa
CM		 1629 }
1630 else if (opc == 4)
1631 {
4b7f6baa
CM		 1632 OUTS (outf, "BITCLR (");
1633 OUTS (outf, dregs (dst));
086134ec 1634 OUTS (outf, ", ");
4b7f6baa 1635 OUTS (outf, uimm5 (src));
086134ec
BS		 1636 OUTS (outf, ");\t\t/* bit");
1637 OUTS (outf, imm7d (src));
1638 OUTS (outf, " */");
1639 comment = 1;
4b7f6baa
CM		 1640 }
1641 else if (opc == 5)
1642 {
4b7f6baa 1643 OUTS (outf, dregs (dst));
086134ec 1644 OUTS (outf, " >>>= ");
4b7f6baa 1645 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1646 }
1647 else if (opc == 6)
1648 {
4b7f6baa 1649 OUTS (outf, dregs (dst));
086134ec 1650 OUTS (outf, " >>= ");
4b7f6baa 1651 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1652 }
1653 else if (opc == 7)
1654 {
4b7f6baa 1655 OUTS (outf, dregs (dst));
086134ec 1656 OUTS (outf, " <<= ");
4b7f6baa 1657 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1658 }
1659 else
b7d48530
NC		 1660 return 0;
1661
1662 return 2;
4b7f6baa
CM		 1663}
1664
1665static int
1666decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1667{
b7d48530
NC		 1668 /* COMP3op
1669 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1670 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1671 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1672 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1673 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1674 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1675 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1676
1677 if (opc == 5 && src1 == src0)
1678 {
4b7f6baa 1679 OUTS (outf, pregs (dst));
086134ec 1680 OUTS (outf, " = ");
4b7f6baa 1681 OUTS (outf, pregs (src0));
086134ec 1682 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1683 }
1684 else if (opc == 1)
1685 {
4b7f6baa 1686 OUTS (outf, dregs (dst));
086134ec 1687 OUTS (outf, " = ");
4b7f6baa 1688 OUTS (outf, dregs (src0));
086134ec 1689 OUTS (outf, " - ");
4b7f6baa 1690 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1691 }
1692 else if (opc == 2)
1693 {
4b7f6baa 1694 OUTS (outf, dregs (dst));
086134ec 1695 OUTS (outf, " = ");
4b7f6baa 1696 OUTS (outf, dregs (src0));
086134ec 1697 OUTS (outf, " & ");
4b7f6baa 1698 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1699 }
1700 else if (opc == 3)
1701 {
4b7f6baa 1702 OUTS (outf, dregs (dst));
086134ec 1703 OUTS (outf, " = ");
4b7f6baa 1704 OUTS (outf, dregs (src0));
086134ec 1705 OUTS (outf, " | ");
4b7f6baa 1706 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1707 }
1708 else if (opc == 4)
1709 {
4b7f6baa 1710 OUTS (outf, dregs (dst));
086134ec 1711 OUTS (outf, " = ");
4b7f6baa 1712 OUTS (outf, dregs (src0));
086134ec 1713 OUTS (outf, " ^ ");
4b7f6baa 1714 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1715 }
1716 else if (opc == 5)
1717 {
4b7f6baa 1718 OUTS (outf, pregs (dst));
086134ec 1719 OUTS (outf, " = ");
4b7f6baa 1720 OUTS (outf, pregs (src0));
086134ec 1721 OUTS (outf, " + ");
4b7f6baa 1722 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1723 }
1724 else if (opc == 6)
1725 {
4b7f6baa 1726 OUTS (outf, pregs (dst));
086134ec 1727 OUTS (outf, " = ");
4b7f6baa 1728 OUTS (outf, pregs (src0));
086134ec 1729 OUTS (outf, " + (");
4b7f6baa 1730 OUTS (outf, pregs (src1));
086134ec 1731 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1732 }
1733 else if (opc == 7)
1734 {
4b7f6baa 1735 OUTS (outf, pregs (dst));
086134ec 1736 OUTS (outf, " = ");
4b7f6baa 1737 OUTS (outf, pregs (src0));
086134ec 1738 OUTS (outf, " + (");
4b7f6baa 1739 OUTS (outf, pregs (src1));
086134ec 1740 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1741 }
1742 else if (opc == 0)
1743 {
4b7f6baa 1744 OUTS (outf, dregs (dst));
086134ec 1745 OUTS (outf, " = ");
4b7f6baa 1746 OUTS (outf, dregs (src0));
086134ec 1747 OUTS (outf, " + ");
4b7f6baa 1748 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1749 }
1750 else
b7d48530
NC		 1751 return 0;
1752
1753 return 2;
4b7f6baa
CM		 1754}
1755
1756static int
1757decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1758{
b7d48530
NC		 1759 /* COMPI2opD
1760 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1761 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1762 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1763 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1764 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1765 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1766
086134ec
BS		 1767 bu32 *pval = get_allreg (0, dst);
1768
219b747a
MF		 1769 if (parallel)
1770 return 0;
1771
086134ec
BS		 1772 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1773 to combine them, so it prints out the right values.
1774 Here we keep track of the registers. */
1775 if (op == 0)
1776 {
1777 *pval = imm7_val (src);
1778 if (src & 0x40)
1779 *pval |= 0xFFFFFF80;
1780 else
1781 *pval &= 0x7F;
1782 }
1783
4b7f6baa
CM		 1784 if (op == 0)
1785 {
4b7f6baa 1786 OUTS (outf, dregs (dst));
086134ec 1787 OUTS (outf, " = ");
4b7f6baa 1788 OUTS (outf, imm7 (src));
086134ec
BS		 1789 OUTS (outf, " (X);\t\t/*\t\t");
1790 OUTS (outf, dregs (dst));
1791 OUTS (outf, "=");
1792 OUTS (outf, uimm32 (*pval));
1793 OUTS (outf, "(");
1794 OUTS (outf, imm32 (*pval));
1795 OUTS (outf, ") */");
1796 comment = 1;
4b7f6baa
CM		 1797 }
1798 else if (op == 1)
1799 {
4b7f6baa 1800 OUTS (outf, dregs (dst));
086134ec 1801 OUTS (outf, " += ");
4b7f6baa 1802 OUTS (outf, imm7 (src));
086134ec
BS		 1803 OUTS (outf, ";\t\t/* (");
1804 OUTS (outf, imm7d (src));
1805 OUTS (outf, ") */");
1806 comment = 1;
4b7f6baa
CM		 1807 }
1808 else
b7d48530
NC		 1809 return 0;
1810
1811 return 2;
4b7f6baa
CM		 1812}
1813
1814static int
1815decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1816{
b7d48530
NC		 1817 /* COMPI2opP
1818 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1819 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1820 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1821 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1822 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1823 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1824
086134ec
BS		 1825 bu32 *pval = get_allreg (1, dst);
1826
219b747a
MF		 1827 if (parallel)
1828 return 0;
1829
086134ec
BS		 1830 if (op == 0)
1831 {
1832 *pval = imm7_val (src);
1833 if (src & 0x40)
1834 *pval |= 0xFFFFFF80;
1835 else
1836 *pval &= 0x7F;
1837 }
1838
4b7f6baa
CM		 1839 if (op == 0)
1840 {
4b7f6baa 1841 OUTS (outf, pregs (dst));
086134ec 1842 OUTS (outf, " = ");
4b7f6baa 1843 OUTS (outf, imm7 (src));
086134ec
BS		 1844 OUTS (outf, " (X);\t\t/*\t\t");
1845 OUTS (outf, pregs (dst));
1846 OUTS (outf, "=");
1847 OUTS (outf, uimm32 (*pval));
1848 OUTS (outf, "(");
1849 OUTS (outf, imm32 (*pval));
1850 OUTS (outf, ") */");
1851 comment = 1;
4b7f6baa
CM		 1852 }
1853 else if (op == 1)
1854 {
4b7f6baa 1855 OUTS (outf, pregs (dst));
086134ec 1856 OUTS (outf, " += ");
4b7f6baa 1857 OUTS (outf, imm7 (src));
086134ec
BS		 1858 OUTS (outf, ";\t\t/* (");
1859 OUTS (outf, imm7d (src));
1860 OUTS (outf, ") */");
1861 comment = 1;
4b7f6baa
CM		 1862 }
1863 else
b7d48530
NC		 1864 return 0;
1865
1866 return 2;
4b7f6baa
CM		 1867}
1868
1869static int
1870decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1871{
b7d48530
NC		 1872 /* LDSTpmod
1873 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1874 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1875 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1876 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1877 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1878 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1879 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1880 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1881
1882 if (aop == 1 && W == 0 && idx == ptr)
1883 {
4b7f6baa 1884 OUTS (outf, dregs_lo (reg));
086134ec 1885 OUTS (outf, " = W[");
4b7f6baa
CM		 1886 OUTS (outf, pregs (ptr));
1887 OUTS (outf, "]");
4b7f6baa
CM		 1888 }
1889 else if (aop == 2 && W == 0 && idx == ptr)
1890 {
4b7f6baa 1891 OUTS (outf, dregs_hi (reg));
086134ec 1892 OUTS (outf, " = W[");
4b7f6baa
CM		 1893 OUTS (outf, pregs (ptr));
1894 OUTS (outf, "]");
4b7f6baa
CM		 1895 }
1896 else if (aop == 1 && W == 1 && idx == ptr)
1897 {
4b7f6baa
CM		 1898 OUTS (outf, "W[");
1899 OUTS (outf, pregs (ptr));
086134ec 1900 OUTS (outf, "] = ");
4b7f6baa 1901 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1902 }
1903 else if (aop == 2 && W == 1 && idx == ptr)
1904 {
4b7f6baa
CM		 1905 OUTS (outf, "W[");
1906 OUTS (outf, pregs (ptr));
086134ec 1907 OUTS (outf, "] = ");
4b7f6baa 1908 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1909 }
1910 else if (aop == 0 && W == 0)
1911 {
4b7f6baa 1912 OUTS (outf, dregs (reg));
086134ec 1913 OUTS (outf, " = [");
4b7f6baa 1914 OUTS (outf, pregs (ptr));
086134ec 1915 OUTS (outf, " ++ ");
4b7f6baa
CM		 1916 OUTS (outf, pregs (idx));
1917 OUTS (outf, "]");
4b7f6baa
CM		 1918 }
1919 else if (aop == 1 && W == 0)
1920 {
4b7f6baa 1921 OUTS (outf, dregs_lo (reg));
086134ec 1922 OUTS (outf, " = W[");
4b7f6baa 1923 OUTS (outf, pregs (ptr));
086134ec 1924 OUTS (outf, " ++ ");
4b7f6baa
CM		 1925 OUTS (outf, pregs (idx));
1926 OUTS (outf, "]");
4b7f6baa
CM		 1927 }
1928 else if (aop == 2 && W == 0)
1929 {
4b7f6baa 1930 OUTS (outf, dregs_hi (reg));
086134ec 1931 OUTS (outf, " = W[");
4b7f6baa 1932 OUTS (outf, pregs (ptr));
086134ec 1933 OUTS (outf, " ++ ");
4b7f6baa
CM		 1934 OUTS (outf, pregs (idx));
1935 OUTS (outf, "]");
4b7f6baa
CM		 1936 }
1937 else if (aop == 3 && W == 0)
1938 {
4b7f6baa 1939 OUTS (outf, dregs (reg));
086134ec 1940 OUTS (outf, " = W[");
4b7f6baa 1941 OUTS (outf, pregs (ptr));
086134ec 1942 OUTS (outf, " ++ ");
4b7f6baa
CM		 1943 OUTS (outf, pregs (idx));
1944 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1945 }
1946 else if (aop == 3 && W == 1)
1947 {
4b7f6baa 1948 OUTS (outf, dregs (reg));
086134ec 1949 OUTS (outf, " = W[");
4b7f6baa 1950 OUTS (outf, pregs (ptr));
086134ec 1951 OUTS (outf, " ++ ");
4b7f6baa 1952 OUTS (outf, pregs (idx));
086134ec 1953 OUTS (outf, "] (X)");
4b7f6baa
CM		 1954 }
1955 else if (aop == 0 && W == 1)
1956 {
4b7f6baa
CM		 1957 OUTS (outf, "[");
1958 OUTS (outf, pregs (ptr));
086134ec 1959 OUTS (outf, " ++ ");
4b7f6baa 1960 OUTS (outf, pregs (idx));
086134ec 1961 OUTS (outf, "] = ");
4b7f6baa 1962 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1963 }
1964 else if (aop == 1 && W == 1)
1965 {
4b7f6baa
CM		 1966 OUTS (outf, "W[");
1967 OUTS (outf, pregs (ptr));
086134ec 1968 OUTS (outf, " ++ ");
4b7f6baa 1969 OUTS (outf, pregs (idx));
086134ec 1970 OUTS (outf, "] = ");
4b7f6baa 1971 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1972 }
1973 else if (aop == 2 && W == 1)
1974 {
4b7f6baa
CM		 1975 OUTS (outf, "W[");
1976 OUTS (outf, pregs (ptr));
086134ec 1977 OUTS (outf, " ++ ");
4b7f6baa 1978 OUTS (outf, pregs (idx));
086134ec 1979 OUTS (outf, "] = ");
4b7f6baa 1980 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1981 }
1982 else
b7d48530
NC		 1983 return 0;
1984
1985 return 2;
4b7f6baa
CM		 1986}
1987
1988static int
1989decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1990{
b7d48530
NC		 1991 /* dagMODim
1992 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1993 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1994 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1995 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1996 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1997 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1998 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1999
2000 if (op == 0 && br == 1)
2001 {
4b7f6baa 2002 OUTS (outf, iregs (i));
086134ec 2003 OUTS (outf, " += ");
4b7f6baa 2004 OUTS (outf, mregs (m));
086134ec 2005 OUTS (outf, " (BREV)");
4b7f6baa
CM		 2006 }
2007 else if (op == 0)
2008 {
4b7f6baa 2009 OUTS (outf, iregs (i));
086134ec 2010 OUTS (outf, " += ");
4b7f6baa 2011 OUTS (outf, mregs (m));
4b7f6baa 2012 }
219b747a 2013 else if (op == 1 && br == 0)
4b7f6baa 2014 {
4b7f6baa 2015 OUTS (outf, iregs (i));
086134ec 2016 OUTS (outf, " -= ");
4b7f6baa 2017 OUTS (outf, mregs (m));
4b7f6baa
CM		 2018 }
2019 else
b7d48530
NC		 2020 return 0;
2021
2022 return 2;
4b7f6baa
CM		 2023}
2024
2025static int
2026decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2027{
b7d48530
NC		 2028 /* dagMODik
2029 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2030 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2032 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2033 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2034
2035 if (op == 0)
2036 {
4b7f6baa 2037 OUTS (outf, iregs (i));
086134ec 2038 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2039 }
2040 else if (op == 1)
2041 {
4b7f6baa 2042 OUTS (outf, iregs (i));
086134ec 2043 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2044 }
2045 else if (op == 2)
2046 {
4b7f6baa 2047 OUTS (outf, iregs (i));
086134ec 2048 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2049 }
2050 else if (op == 3)
2051 {
4b7f6baa 2052 OUTS (outf, iregs (i));
086134ec 2053 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2054 }
2055 else
b7d48530
NC		 2056 return 0;
2057
602427c4
MF		 2058 if (! parallel)
2059 {
2060 OUTS (outf, ";\t\t/* ( ");
2061 if (op == 0 || op == 1)
2062 OUTS (outf, "2");
2063 else if (op == 2 || op == 3)
086134ec 2064 OUTS (outf, "4");
602427c4
MF		 2065 OUTS (outf, ") */");
2066 comment = 1;
2067 }
086134ec 2068
b7d48530 2069 return 2;
4b7f6baa
CM		 2070}
2071
2072static int
2073decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2074{
b7d48530
NC		 2075 /* dspLDST
2076 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2077 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2078 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2079 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2080 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2081 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2082 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2083 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2084
2085 if (aop == 0 && W == 0 && m == 0)
2086 {
4b7f6baa 2087 OUTS (outf, dregs (reg));
086134ec 2088 OUTS (outf, " = [");
4b7f6baa
CM		 2089 OUTS (outf, iregs (i));
2090 OUTS (outf, "++]");
4b7f6baa
CM		 2091 }
2092 else if (aop == 0 && W == 0 && m == 1)
2093 {
4b7f6baa 2094 OUTS (outf, dregs_lo (reg));
086134ec 2095 OUTS (outf, " = W[");
4b7f6baa
CM		 2096 OUTS (outf, iregs (i));
2097 OUTS (outf, "++]");
4b7f6baa
CM		 2098 }
2099 else if (aop == 0 && W == 0 && m == 2)
2100 {
4b7f6baa 2101 OUTS (outf, dregs_hi (reg));
086134ec 2102 OUTS (outf, " = W[");
4b7f6baa
CM		 2103 OUTS (outf, iregs (i));
2104 OUTS (outf, "++]");
4b7f6baa
CM		 2105 }
2106 else if (aop == 1 && W == 0 && m == 0)
2107 {
4b7f6baa 2108 OUTS (outf, dregs (reg));
086134ec 2109 OUTS (outf, " = [");
4b7f6baa
CM		 2110 OUTS (outf, iregs (i));
2111 OUTS (outf, "--]");
4b7f6baa
CM		 2112 }
2113 else if (aop == 1 && W == 0 && m == 1)
2114 {
4b7f6baa 2115 OUTS (outf, dregs_lo (reg));
086134ec 2116 OUTS (outf, " = W[");
4b7f6baa
CM		 2117 OUTS (outf, iregs (i));
2118 OUTS (outf, "--]");
4b7f6baa
CM		 2119 }
2120 else if (aop == 1 && W == 0 && m == 2)
2121 {
4b7f6baa 2122 OUTS (outf, dregs_hi (reg));
086134ec 2123 OUTS (outf, " = W[");
4b7f6baa
CM		 2124 OUTS (outf, iregs (i));
2125 OUTS (outf, "--]");
4b7f6baa
CM		 2126 }
2127 else if (aop == 2 && W == 0 && m == 0)
2128 {
4b7f6baa 2129 OUTS (outf, dregs (reg));
086134ec 2130 OUTS (outf, " = [");
4b7f6baa
CM		 2131 OUTS (outf, iregs (i));
2132 OUTS (outf, "]");
4b7f6baa
CM		 2133 }
2134 else if (aop == 2 && W == 0 && m == 1)
2135 {
4b7f6baa 2136 OUTS (outf, dregs_lo (reg));
086134ec 2137 OUTS (outf, " = W[");
4b7f6baa
CM		 2138 OUTS (outf, iregs (i));
2139 OUTS (outf, "]");
4b7f6baa
CM		 2140 }
2141 else if (aop == 2 && W == 0 && m == 2)
2142 {
4b7f6baa 2143 OUTS (outf, dregs_hi (reg));
086134ec 2144 OUTS (outf, " = W[");
4b7f6baa
CM		 2145 OUTS (outf, iregs (i));
2146 OUTS (outf, "]");
4b7f6baa
CM		 2147 }
2148 else if (aop == 0 && W == 1 && m == 0)
2149 {
4b7f6baa
CM		 2150 OUTS (outf, "[");
2151 OUTS (outf, iregs (i));
086134ec 2152 OUTS (outf, "++] = ");
4b7f6baa 2153 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2154 }
2155 else if (aop == 0 && W == 1 && m == 1)
2156 {
4b7f6baa
CM		 2157 OUTS (outf, "W[");
2158 OUTS (outf, iregs (i));
086134ec 2159 OUTS (outf, "++] = ");
4b7f6baa 2160 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2161 }
2162 else if (aop == 0 && W == 1 && m == 2)
2163 {
4b7f6baa
CM		 2164 OUTS (outf, "W[");
2165 OUTS (outf, iregs (i));
086134ec 2166 OUTS (outf, "++] = ");
4b7f6baa 2167 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2168 }
2169 else if (aop == 1 && W == 1 && m == 0)
2170 {
4b7f6baa
CM		 2171 OUTS (outf, "[");
2172 OUTS (outf, iregs (i));
086134ec 2173 OUTS (outf, "--] = ");
4b7f6baa 2174 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2175 }
2176 else if (aop == 1 && W == 1 && m == 1)
2177 {
4b7f6baa
CM		 2178 OUTS (outf, "W[");
2179 OUTS (outf, iregs (i));
086134ec 2180 OUTS (outf, "--] = ");
4b7f6baa 2181 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2182 }
2183 else if (aop == 1 && W == 1 && m == 2)
2184 {
4b7f6baa
CM		 2185 OUTS (outf, "W[");
2186 OUTS (outf, iregs (i));
086134ec 2187 OUTS (outf, "--] = ");
4b7f6baa 2188 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2189 }
2190 else if (aop == 2 && W == 1 && m == 0)
2191 {
4b7f6baa
CM		 2192 OUTS (outf, "[");
2193 OUTS (outf, iregs (i));
086134ec 2194 OUTS (outf, "] = ");
4b7f6baa 2195 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2196 }
2197 else if (aop == 2 && W == 1 && m == 1)
2198 {
4b7f6baa
CM		 2199 OUTS (outf, "W[");
2200 OUTS (outf, iregs (i));
086134ec 2201 OUTS (outf, "] = ");
4b7f6baa 2202 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2203 }
2204 else if (aop == 2 && W == 1 && m == 2)
2205 {
4b7f6baa
CM		 2206 OUTS (outf, "W[");
2207 OUTS (outf, iregs (i));
086134ec 2208 OUTS (outf, "] = ");
4b7f6baa 2209 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2210 }
2211 else if (aop == 3 && W == 0)
2212 {
4b7f6baa 2213 OUTS (outf, dregs (reg));
086134ec 2214 OUTS (outf, " = [");
4b7f6baa 2215 OUTS (outf, iregs (i));
086134ec 2216 OUTS (outf, " ++ ");
4b7f6baa
CM		 2217 OUTS (outf, mregs (m));
2218 OUTS (outf, "]");
4b7f6baa
CM		 2219 }
2220 else if (aop == 3 && W == 1)
2221 {
4b7f6baa
CM		 2222 OUTS (outf, "[");
2223 OUTS (outf, iregs (i));
086134ec 2224 OUTS (outf, " ++ ");
4b7f6baa 2225 OUTS (outf, mregs (m));
086134ec 2226 OUTS (outf, "] = ");
4b7f6baa 2227 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2228 }
2229 else
b7d48530
NC		 2230 return 0;
2231
2232 return 2;
4b7f6baa
CM		 2233}
2234
2235static int
2236decode_LDST_0 (TIword iw0, disassemble_info *outf)
2237{
b7d48530
NC		 2238 /* LDST
2239 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2240 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2241 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2242 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2243 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2244 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2245 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2246 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2247 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2248
2249 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2250 {
4b7f6baa 2251 OUTS (outf, dregs (reg));
086134ec 2252 OUTS (outf, " = [");
4b7f6baa
CM		 2253 OUTS (outf, pregs (ptr));
2254 OUTS (outf, "++]");
4b7f6baa 2255 }
219b747a 2256 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2257 {
4b7f6baa 2258 OUTS (outf, pregs (reg));
086134ec 2259 OUTS (outf, " = [");
4b7f6baa
CM		 2260 OUTS (outf, pregs (ptr));
2261 OUTS (outf, "++]");
4b7f6baa
CM		 2262 }
2263 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2264 {
4b7f6baa 2265 OUTS (outf, dregs (reg));
086134ec 2266 OUTS (outf, " = W[");
4b7f6baa
CM		 2267 OUTS (outf, pregs (ptr));
2268 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2269 }
2270 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2271 {
4b7f6baa 2272 OUTS (outf, dregs (reg));
086134ec 2273 OUTS (outf, " = W[");
4b7f6baa 2274 OUTS (outf, pregs (ptr));
086134ec 2275 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2276 }
2277 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2278 {
4b7f6baa 2279 OUTS (outf, dregs (reg));
086134ec 2280 OUTS (outf, " = B[");
4b7f6baa
CM		 2281 OUTS (outf, pregs (ptr));
2282 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2283 }
2284 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2285 {
4b7f6baa 2286 OUTS (outf, dregs (reg));
086134ec 2287 OUTS (outf, " = B[");
4b7f6baa 2288 OUTS (outf, pregs (ptr));
086134ec 2289 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2290 }
2291 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2292 {
4b7f6baa 2293 OUTS (outf, dregs (reg));
086134ec 2294 OUTS (outf, " = [");
4b7f6baa
CM		 2295 OUTS (outf, pregs (ptr));
2296 OUTS (outf, "--]");
4b7f6baa 2297 }
219b747a 2298 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2299 {
4b7f6baa 2300 OUTS (outf, pregs (reg));
086134ec 2301 OUTS (outf, " = [");
4b7f6baa
CM		 2302 OUTS (outf, pregs (ptr));
2303 OUTS (outf, "--]");
4b7f6baa
CM		 2304 }
2305 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2306 {
4b7f6baa 2307 OUTS (outf, dregs (reg));
086134ec 2308 OUTS (outf, " = W[");
4b7f6baa
CM		 2309 OUTS (outf, pregs (ptr));
2310 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2311 }
2312 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2313 {
4b7f6baa 2314 OUTS (outf, dregs (reg));
086134ec 2315 OUTS (outf, " = W[");
4b7f6baa 2316 OUTS (outf, pregs (ptr));
086134ec 2317 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2318 }
2319 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2320 {
4b7f6baa 2321 OUTS (outf, dregs (reg));
086134ec 2322 OUTS (outf, " = B[");
4b7f6baa
CM		 2323 OUTS (outf, pregs (ptr));
2324 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2325 }
2326 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2327 {
4b7f6baa 2328 OUTS (outf, dregs (reg));
086134ec 2329 OUTS (outf, " = B[");
4b7f6baa 2330 OUTS (outf, pregs (ptr));
086134ec 2331 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2332 }
2333 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2334 {
4b7f6baa 2335 OUTS (outf, dregs (reg));
086134ec 2336 OUTS (outf, " = [");
4b7f6baa
CM		 2337 OUTS (outf, pregs (ptr));
2338 OUTS (outf, "]");
4b7f6baa
CM		 2339 }
2340 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2341 {
4b7f6baa 2342 OUTS (outf, pregs (reg));
086134ec 2343 OUTS (outf, " = [");
4b7f6baa
CM		 2344 OUTS (outf, pregs (ptr));
2345 OUTS (outf, "]");
4b7f6baa
CM		 2346 }
2347 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2348 {
4b7f6baa 2349 OUTS (outf, dregs (reg));
086134ec 2350 OUTS (outf, " = W[");
4b7f6baa
CM		 2351 OUTS (outf, pregs (ptr));
2352 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2353 }
2354 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2355 {
4b7f6baa 2356 OUTS (outf, dregs (reg));
086134ec 2357 OUTS (outf, " = W[");
4b7f6baa 2358 OUTS (outf, pregs (ptr));
086134ec 2359 OUTS (outf, "] (X)");
4b7f6baa
CM		 2360 }
2361 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2362 {
4b7f6baa 2363 OUTS (outf, dregs (reg));
086134ec 2364 OUTS (outf, " = B[");
4b7f6baa
CM		 2365 OUTS (outf, pregs (ptr));
2366 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2367 }
2368 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2369 {
4b7f6baa 2370 OUTS (outf, dregs (reg));
086134ec 2371 OUTS (outf, " = B[");
4b7f6baa 2372 OUTS (outf, pregs (ptr));
086134ec 2373 OUTS (outf, "] (X)");
4b7f6baa
CM		 2374 }
2375 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2376 {
4b7f6baa
CM		 2377 OUTS (outf, "[");
2378 OUTS (outf, pregs (ptr));
086134ec 2379 OUTS (outf, "++] = ");
4b7f6baa 2380 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2381 }
2382 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2383 {
4b7f6baa
CM		 2384 OUTS (outf, "[");
2385 OUTS (outf, pregs (ptr));
086134ec 2386 OUTS (outf, "++] = ");
4b7f6baa 2387 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2388 }
2389 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2390 {
4b7f6baa
CM		 2391 OUTS (outf, "W[");
2392 OUTS (outf, pregs (ptr));
086134ec 2393 OUTS (outf, "++] = ");
4b7f6baa 2394 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2395 }
2396 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2397 {
4b7f6baa
CM		 2398 OUTS (outf, "B[");
2399 OUTS (outf, pregs (ptr));
086134ec 2400 OUTS (outf, "++] = ");
4b7f6baa 2401 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2402 }
2403 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2404 {
4b7f6baa
CM		 2405 OUTS (outf, "[");
2406 OUTS (outf, pregs (ptr));
086134ec 2407 OUTS (outf, "--] = ");
4b7f6baa 2408 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2409 }
2410 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2411 {
4b7f6baa
CM		 2412 OUTS (outf, "[");
2413 OUTS (outf, pregs (ptr));
086134ec 2414 OUTS (outf, "--] = ");
4b7f6baa 2415 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2416 }
2417 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2418 {
4b7f6baa
CM		 2419 OUTS (outf, "W[");
2420 OUTS (outf, pregs (ptr));
086134ec 2421 OUTS (outf, "--] = ");
4b7f6baa 2422 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2423 }
2424 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2425 {
4b7f6baa
CM		 2426 OUTS (outf, "B[");
2427 OUTS (outf, pregs (ptr));
086134ec 2428 OUTS (outf, "--] = ");
4b7f6baa 2429 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2430 }
2431 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2432 {
4b7f6baa
CM		 2433 OUTS (outf, "[");
2434 OUTS (outf, pregs (ptr));
086134ec 2435 OUTS (outf, "] = ");
4b7f6baa 2436 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2437 }
2438 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2439 {
4b7f6baa
CM		 2440 OUTS (outf, "[");
2441 OUTS (outf, pregs (ptr));
086134ec 2442 OUTS (outf, "] = ");
4b7f6baa 2443 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2444 }
2445 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2446 {
4b7f6baa
CM		 2447 OUTS (outf, "W[");
2448 OUTS (outf, pregs (ptr));
086134ec 2449 OUTS (outf, "] = ");
4b7f6baa 2450 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2451 }
2452 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2453 {
4b7f6baa
CM		 2454 OUTS (outf, "B[");
2455 OUTS (outf, pregs (ptr));
086134ec 2456 OUTS (outf, "] = ");
4b7f6baa 2457 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2458 }
2459 else
b7d48530
NC		 2460 return 0;
2461
2462 return 2;
4b7f6baa
CM		 2463}
2464
2465static int
2466decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2467{
b7d48530
NC		 2468 /* LDSTiiFP
2469 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2470 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2471 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2472 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2473 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2474 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2475
2476 if (W == 0)
2477 {
4b7f6baa 2478 OUTS (outf, dpregs (reg));
086134ec 2479 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2480 OUTS (outf, negimm5s4 (offset));
2481 OUTS (outf, "]");
4b7f6baa
CM		 2482 }
2483 else if (W == 1)
2484 {
086134ec 2485 OUTS (outf, "[FP ");
4b7f6baa 2486 OUTS (outf, negimm5s4 (offset));
086134ec 2487 OUTS (outf, "] = ");
4b7f6baa 2488 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2489 }
2490 else
b7d48530
NC		 2491 return 0;
2492
2493 return 2;
4b7f6baa
CM		 2494}
2495
2496static int
2497decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2498{
b7d48530
NC		 2499 /* LDSTii
2500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2501 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2503 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2504 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2505 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2506 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2507 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2508
2509 if (W == 0 && op == 0)
2510 {
4b7f6baa 2511 OUTS (outf, dregs (reg));
086134ec 2512 OUTS (outf, " = [");
4b7f6baa 2513 OUTS (outf, pregs (ptr));
086134ec 2514 OUTS (outf, " + ");
4b7f6baa
CM		 2515 OUTS (outf, uimm4s4 (offset));
2516 OUTS (outf, "]");
4b7f6baa
CM		 2517 }
2518 else if (W == 0 && op == 1)
2519 {
4b7f6baa 2520 OUTS (outf, dregs (reg));
086134ec 2521 OUTS (outf, " = W[");
4b7f6baa 2522 OUTS (outf, pregs (ptr));
086134ec 2523 OUTS (outf, " + ");
4b7f6baa
CM		 2524 OUTS (outf, uimm4s2 (offset));
2525 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2526 }
2527 else if (W == 0 && op == 2)
2528 {
4b7f6baa 2529 OUTS (outf, dregs (reg));
086134ec 2530 OUTS (outf, " = W[");
4b7f6baa 2531 OUTS (outf, pregs (ptr));
086134ec 2532 OUTS (outf, " + ");
4b7f6baa 2533 OUTS (outf, uimm4s2 (offset));
086134ec 2534 OUTS (outf, "] (X)");
4b7f6baa
CM		 2535 }
2536 else if (W == 0 && op == 3)
2537 {
4b7f6baa 2538 OUTS (outf, pregs (reg));
086134ec 2539 OUTS (outf, " = [");
4b7f6baa 2540 OUTS (outf, pregs (ptr));
086134ec 2541 OUTS (outf, " + ");
4b7f6baa
CM		 2542 OUTS (outf, uimm4s4 (offset));
2543 OUTS (outf, "]");
4b7f6baa
CM		 2544 }
2545 else if (W == 1 && op == 0)
2546 {
4b7f6baa
CM		 2547 OUTS (outf, "[");
2548 OUTS (outf, pregs (ptr));
086134ec 2549 OUTS (outf, " + ");
4b7f6baa 2550 OUTS (outf, uimm4s4 (offset));
086134ec 2551 OUTS (outf, "] = ");
4b7f6baa 2552 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2553 }
2554 else if (W == 1 && op == 1)
2555 {
086134ec 2556 OUTS (outf, "W[");
4b7f6baa 2557 OUTS (outf, pregs (ptr));
086134ec 2558 OUTS (outf, " + ");
4b7f6baa 2559 OUTS (outf, uimm4s2 (offset));
086134ec 2560 OUTS (outf, "] = ");
4b7f6baa 2561 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2562 }
2563 else if (W == 1 && op == 3)
2564 {
4b7f6baa
CM		 2565 OUTS (outf, "[");
2566 OUTS (outf, pregs (ptr));
086134ec 2567 OUTS (outf, " + ");
4b7f6baa 2568 OUTS (outf, uimm4s4 (offset));
086134ec 2569 OUTS (outf, "] = ");
4b7f6baa 2570 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2571 }
2572 else
b7d48530
NC		 2573 return 0;
2574
2575 return 2;
4b7f6baa
CM		 2576}
2577
2578static int
2579decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2580{
b7d48530
NC		 2581 /* LoopSetup
2582 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2583 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2584 |.reg...........| - | - |.eoffset...............................|
2585 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2586 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2587 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2588 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2589 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2590 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2591
219b747a
MF		 2592 if (parallel)
2593 return 0;
2594
298c1ec2
MF		 2595 if (reg > 7)
2596 return 0;
2597
4b7f6baa
CM		 2598 if (rop == 0)
2599 {
4b7f6baa 2600 OUTS (outf, "LSETUP");
086134ec 2601 OUTS (outf, "(0x");
4b7f6baa 2602 OUTS (outf, pcrel4 (soffset));
086134ec 2603 OUTS (outf, ", 0x");
4b7f6baa 2604 OUTS (outf, lppcrel10 (eoffset));
086134ec 2605 OUTS (outf, ") ");
4b7f6baa 2606 OUTS (outf, counters (c));
4b7f6baa
CM		 2607 }
2608 else if (rop == 1)
2609 {
4b7f6baa 2610 OUTS (outf, "LSETUP");
086134ec 2611 OUTS (outf, "(0x");
4b7f6baa 2612 OUTS (outf, pcrel4 (soffset));
086134ec 2613 OUTS (outf, ", 0x");
4b7f6baa 2614 OUTS (outf, lppcrel10 (eoffset));
086134ec 2615 OUTS (outf, ") ");
4b7f6baa 2616 OUTS (outf, counters (c));
086134ec 2617 OUTS (outf, " = ");
4b7f6baa 2618 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2619 }
2620 else if (rop == 3)
2621 {
4b7f6baa 2622 OUTS (outf, "LSETUP");
086134ec 2623 OUTS (outf, "(0x");
4b7f6baa 2624 OUTS (outf, pcrel4 (soffset));
086134ec 2625 OUTS (outf, ", 0x");
4b7f6baa 2626 OUTS (outf, lppcrel10 (eoffset));
086134ec 2627 OUTS (outf, ") ");
4b7f6baa 2628 OUTS (outf, counters (c));
086134ec 2629 OUTS (outf, " = ");
4b7f6baa 2630 OUTS (outf, pregs (reg));
086134ec 2631 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2632 }
2633 else
b7d48530
NC		 2634 return 0;
2635
2636 return 4;
4b7f6baa
CM		 2637}
2638
2639static int
2640decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2641{
b7d48530
NC		 2642 /* LDIMMhalf
2643 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2644 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2645 |.hword.........................................................|
2646 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2647 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2648 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2649 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2650 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2651 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2652 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2653
b21c9cb4
BS		 2654 bu32 *pval = get_allreg (grp, reg);
2655
219b747a
MF		 2656 if (parallel)
2657 return 0;
2658
b21c9cb4
BS		 2659 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2660 to combine them, so it prints out the right values.
2661 Here we keep track of the registers. */
2662 if (H == 0 && S == 1 && Z == 0)
2663 {
2664 /* regs = imm16 (x) */
2665 *pval = imm16_val (hword);
086134ec
BS		 2666 if (hword & 0x8000)
2667 *pval |= 0xFFFF0000;
2668 else
2669 *pval &= 0xFFFF;
b21c9cb4
BS		 2670 }
2671 else if (H == 0 && S == 0 && Z == 1)
2672 {
2673 /* regs = luimm16 (Z) */
2674 *pval = luimm16_val (hword);
086134ec 2675 *pval &= 0xFFFF;
b21c9cb4
BS		 2676 }
2677 else if (H == 0 && S == 0 && Z == 0)
2678 {
2679 /* regs_lo = luimm16 */
2680 *pval &= 0xFFFF0000;
2681 *pval |= luimm16_val (hword);
2682 }
2683 else if (H == 1 && S == 0 && Z == 0)
2684 {
2685 /* regs_hi = huimm16 */
2686 *pval &= 0xFFFF;
2687 *pval |= luimm16_val (hword) << 16;
2688 }
2689
2690 /* Here we do the disassembly */
4b7f6baa
CM		 2691 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2692 {
4b7f6baa 2693 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2694 OUTS (outf, " = ");
2695 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2696 }
2697 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2698 {
4b7f6baa 2699 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2700 OUTS (outf, " = ");
2701 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2702 }
2703 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2704 {
4b7f6baa 2705 OUTS (outf, dregs (reg));
086134ec 2706 OUTS (outf, " = ");
4b7f6baa
CM		 2707 OUTS (outf, imm16 (hword));
2708 OUTS (outf, " (X)");
4b7f6baa
CM		 2709 }
2710 else if (H == 0 && S == 1 && Z == 0)
602427c4 2711 {
4b7f6baa 2712 OUTS (outf, regs (reg, grp));
086134ec 2713 OUTS (outf, " = ");
4b7f6baa
CM		 2714 OUTS (outf, imm16 (hword));
2715 OUTS (outf, " (X)");
4b7f6baa
CM		 2716 }
2717 else if (H == 0 && S == 0 && Z == 1)
2718 {
4b7f6baa 2719 OUTS (outf, regs (reg, grp));
086134ec
BS		 2720 OUTS (outf, " = ");
2721 OUTS (outf, uimm16 (hword));
2722 OUTS (outf, " (Z)");
4b7f6baa
CM		 2723 }
2724 else if (H == 0 && S == 0 && Z == 0)
2725 {
4b7f6baa 2726 OUTS (outf, regs_lo (reg, grp));
086134ec 2727 OUTS (outf, " = ");
b21c9cb4 2728 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2729 }
2730 else if (H == 1 && S == 0 && Z == 0)
2731 {
4b7f6baa 2732 OUTS (outf, regs_hi (reg, grp));
086134ec 2733 OUTS (outf, " = ");
b21c9cb4 2734 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2735 }
2736 else
b7d48530
NC		 2737 return 0;
2738
b21c9cb4 2739 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2740 if (S == 0 && Z == 0)
b21c9cb4 2741 {
086134ec
BS		 2742 OUTS (outf, ";\t\t/* (");
2743 OUTS (outf, imm16d (hword));
2744 OUTS (outf, ")\t");
2745
b21c9cb4 2746 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2747 if (*pval < 0xFFC00000 && grp == 1)
2748 {
2749 OUTS (outf, regs (reg, grp));
2750 OUTS (outf, "=0x");
2751 OUTS (outf, huimm32e (*pval));
2752 }
b21c9cb4 2753 else
086134ec
BS		 2754 {
2755 OUTS (outf, regs (reg, grp));
2756 OUTS (outf, "=0x");
2757 OUTS (outf, huimm32e (*pval));
2758 OUTS (outf, "(");
2759 OUTS (outf, imm32 (*pval));
2760 OUTS (outf, ")");
2761 }
b21c9cb4
BS		 2762
2763 OUTS (outf, " */");
086134ec
BS		 2764 comment = 1;
2765 }
2766 if (S == 1 || Z == 1)
2767 {
602427c4
MF		 2768 OUTS (outf, ";\t\t/*\t\t");
2769 OUTS (outf, regs (reg, grp));
2770 OUTS (outf, "=0x");
2771 OUTS (outf, huimm32e (*pval));
2772 OUTS (outf, "(");
2773 OUTS (outf, imm32 (*pval));
2774 OUTS (outf, ") */");
2775 comment = 1;
b21c9cb4 2776 }
b7d48530 2777 return 4;
4b7f6baa
CM		 2778}
2779
2780static int
2781decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2782{
b7d48530
NC		 2783 /* CALLa
2784 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2785 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2786 |.lsw...........................................................|
2787 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2788 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2789 int lsw = ((iw1 >> 0) & 0xffff);
2790 int msw = ((iw0 >> 0) & 0xff);
2791
219b747a
MF		 2792 if (parallel)
2793 return 0;
2794
4b7f6baa 2795 if (S == 1)
086134ec 2796 OUTS (outf, "CALL 0x");
4b7f6baa 2797 else if (S == 0)
086134ec 2798 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2799 else
b7d48530
NC		 2800 return 0;
2801
2802 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2803 return 4;
4b7f6baa
CM		 2804}
2805
2806static int
2807decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2808{
b7d48530
NC		 2809 /* LDSTidxI
2810 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2811 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2812 |.offset........................................................|
2813 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2814 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2815 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2816 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2817 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2818 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2819 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2820
2821 if (W == 0 && sz == 0 && Z == 0)
2822 {
4b7f6baa 2823 OUTS (outf, dregs (reg));
086134ec 2824 OUTS (outf, " = [");
4b7f6baa 2825 OUTS (outf, pregs (ptr));
086134ec 2826 OUTS (outf, " + ");
4b7f6baa
CM		 2827 OUTS (outf, imm16s4 (offset));
2828 OUTS (outf, "]");
4b7f6baa
CM		 2829 }
2830 else if (W == 0 && sz == 0 && Z == 1)
2831 {
4b7f6baa 2832 OUTS (outf, pregs (reg));
086134ec 2833 OUTS (outf, " = [");
4b7f6baa 2834 OUTS (outf, pregs (ptr));
086134ec 2835 OUTS (outf, " + ");
4b7f6baa
CM		 2836 OUTS (outf, imm16s4 (offset));
2837 OUTS (outf, "]");
4b7f6baa
CM		 2838 }
2839 else if (W == 0 && sz == 1 && Z == 0)
2840 {
4b7f6baa 2841 OUTS (outf, dregs (reg));
086134ec 2842 OUTS (outf, " = W[");
4b7f6baa 2843 OUTS (outf, pregs (ptr));
086134ec 2844 OUTS (outf, " + ");
4b7f6baa
CM		 2845 OUTS (outf, imm16s2 (offset));
2846 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2847 }
2848 else if (W == 0 && sz == 1 && Z == 1)
2849 {
4b7f6baa 2850 OUTS (outf, dregs (reg));
086134ec 2851 OUTS (outf, " = W[");
4b7f6baa 2852 OUTS (outf, pregs (ptr));
086134ec 2853 OUTS (outf, " + ");
4b7f6baa 2854 OUTS (outf, imm16s2 (offset));
086134ec 2855 OUTS (outf, "] (X)");
4b7f6baa
CM		 2856 }
2857 else if (W == 0 && sz == 2 && Z == 0)
2858 {
4b7f6baa 2859 OUTS (outf, dregs (reg));
086134ec 2860 OUTS (outf, " = B[");
4b7f6baa 2861 OUTS (outf, pregs (ptr));
086134ec 2862 OUTS (outf, " + ");
4b7f6baa
CM		 2863 OUTS (outf, imm16 (offset));
2864 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2865 }
2866 else if (W == 0 && sz == 2 && Z == 1)
2867 {
4b7f6baa 2868 OUTS (outf, dregs (reg));
086134ec 2869 OUTS (outf, " = B[");
4b7f6baa 2870 OUTS (outf, pregs (ptr));
086134ec 2871 OUTS (outf, " + ");
4b7f6baa 2872 OUTS (outf, imm16 (offset));
086134ec 2873 OUTS (outf, "] (X)");
4b7f6baa
CM		 2874 }
2875 else if (W == 1 && sz == 0 && Z == 0)
2876 {
4b7f6baa
CM		 2877 OUTS (outf, "[");
2878 OUTS (outf, pregs (ptr));
086134ec 2879 OUTS (outf, " + ");
4b7f6baa 2880 OUTS (outf, imm16s4 (offset));
086134ec 2881 OUTS (outf, "] = ");
4b7f6baa 2882 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2883 }
2884 else if (W == 1 && sz == 0 && Z == 1)
2885 {
4b7f6baa
CM		 2886 OUTS (outf, "[");
2887 OUTS (outf, pregs (ptr));
086134ec 2888 OUTS (outf, " + ");
4b7f6baa 2889 OUTS (outf, imm16s4 (offset));
086134ec 2890 OUTS (outf, "] = ");
4b7f6baa 2891 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2892 }
2893 else if (W == 1 && sz == 1 && Z == 0)
2894 {
4b7f6baa
CM		 2895 OUTS (outf, "W[");
2896 OUTS (outf, pregs (ptr));
086134ec 2897 OUTS (outf, " + ");
4b7f6baa 2898 OUTS (outf, imm16s2 (offset));
086134ec 2899 OUTS (outf, "] = ");
4b7f6baa 2900 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2901 }
2902 else if (W == 1 && sz == 2 && Z == 0)
2903 {
4b7f6baa
CM		 2904 OUTS (outf, "B[");
2905 OUTS (outf, pregs (ptr));
086134ec 2906 OUTS (outf, " + ");
4b7f6baa 2907 OUTS (outf, imm16 (offset));
086134ec 2908 OUTS (outf, "] = ");
4b7f6baa 2909 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2910 }
2911 else
b7d48530
NC		 2912 return 0;
2913
2914 return 4;
4b7f6baa
CM		 2915}
2916
2917static int
2918decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2919{
b7d48530
NC		 2920 /* linkage
2921 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2922 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2923 |.framesize.....................................................|
2924 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2925 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2926 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2927
219b747a
MF		 2928 if (parallel)
2929 return 0;
2930
4b7f6baa
CM		 2931 if (R == 0)
2932 {
4b7f6baa
CM		 2933 OUTS (outf, "LINK ");
2934 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2935 OUTS (outf, ";\t\t/* (");
2936 OUTS (outf, uimm16s4d (framesize));
2937 OUTS (outf, ") */");
2938 comment = 1;
4b7f6baa
CM		 2939 }
2940 else if (R == 1)
b7d48530 2941 OUTS (outf, "UNLINK");
4b7f6baa 2942 else
b7d48530
NC		 2943 return 0;
2944
2945 return 4;
4b7f6baa
CM		 2946}
2947
2948static int
2949decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2950{
b7d48530
NC		 2951 /* dsp32mac
2952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2953 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2954 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2956 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2957 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2958 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2959 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2960 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2961 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2962 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2963 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2964 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2965 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2966 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2967 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2968 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2969 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2970
2971 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2972 return 0;
2973
2974 if (op1 == 3 && MM)
2975 return 0;
2976
2977 if ((w1 || w0) && mmod == M_W32)
2978 return 0;
2979
ee171c8f 2980 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 2981 return 0;
2982
2983 if (w1 == 1 || op1 != 3)
2984 {
2985 if (w1)
2986 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2987
2988 if (op1 == 3)
2989 OUTS (outf, " = A1");
2990 else
2991 {
2992 if (w1)
2993 OUTS (outf, " = (");
2994 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2995 if (w1)
2996 OUTS (outf, ")");
2997 }
2998
2999 if (w0 == 1 || op0 != 3)
3000 {
3001 if (MM)
3002 OUTS (outf, " (M)");
4b7f6baa
CM		 3003 OUTS (outf, ", ");
3004 }
3005 }
3006
3007 if (w0 == 1 || op0 != 3)
3008 {
67171547
MF		 3009 /* Clear MM option since it only matters for MAC1, and if we made
3010 it this far, we've already shown it or we want to ignore it. */
3011 MM = 0;
3012
4b7f6baa
CM		 3013 if (w0)
3014 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3015
3016 if (op0 == 3)
3017 OUTS (outf, " = A0");
3018 else
3019 {
3020 if (w0)
3021 OUTS (outf, " = (");
3022 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3023 if (w0)
3024 OUTS (outf, ")");
3025 }
3026 }
3027
3028 decode_optmode (mmod, MM, outf);
3029
3030 return 4;
3031}
3032
3033static int
3034decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3035{
b7d48530
NC		 3036 /* dsp32mult
3037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3038 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3039 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3040 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3041 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3042 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3043 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3044 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3045 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3046 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3047 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3048 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3049 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3050 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3051 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3052 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3053
3054 if (w1 == 0 && w0 == 0)
3055 return 0;
b7d48530 3056
4b7f6baa
CM		 3057 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3058 return 0;
b7d48530 3059
4b7f6baa
CM		 3060 if (w1)
3061 {
4db66394 3062 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
4b7f6baa
CM		 3063 OUTS (outf, " = ");
3064 decode_multfunc (h01, h11, src0, src1, outf);
3065
3066 if (w0)
3067 {
3068 if (MM)
3069 OUTS (outf, " (M)");
3070 MM = 0;
3071 OUTS (outf, ", ");
3072 }
3073 }
3074
3075 if (w0)
3076 {
4db66394 3077 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
4b7f6baa
CM		 3078 OUTS (outf, " = ");
3079 decode_multfunc (h00, h10, src0, src1, outf);
3080 }
3081
3082 decode_optmode (mmod, MM, outf);
3083 return 4;
3084}
3085
3086static int
3087decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3088{
b7d48530
NC		 3089 /* dsp32alu
3090 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3091 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3092 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3093 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3094 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3095 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3096 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3097 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3098 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3099 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3100 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3101 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3102 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3103
3104 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3105 {
086134ec 3106 OUTS (outf, "A0.L = ");
4b7f6baa 3107 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3108 }
3109 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3110 {
086134ec 3111 OUTS (outf, "A1.H = ");
4b7f6baa 3112 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3113 }
3114 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3115 {
086134ec 3116 OUTS (outf, "A1.L = ");
4b7f6baa 3117 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3118 }
3119 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3120 {
086134ec 3121 OUTS (outf, "A0.H = ");
4b7f6baa 3122 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3123 }
3124 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3125 {
4b7f6baa 3126 OUTS (outf, dregs_hi (dst0));
086134ec 3127 OUTS (outf, " = ");
4b7f6baa 3128 OUTS (outf, dregs (src0));
086134ec 3129 OUTS (outf, " - ");
4b7f6baa 3130 OUTS (outf, dregs (src1));
086134ec 3131 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3132 }
3133 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3134 {
4b7f6baa 3135 OUTS (outf, dregs_hi (dst0));
086134ec 3136 OUTS (outf, " = ");
4b7f6baa 3137 OUTS (outf, dregs (src0));
086134ec 3138 OUTS (outf, " + ");
4b7f6baa 3139 OUTS (outf, dregs (src1));
086134ec 3140 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3141 }
3142 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3143 {
4b7f6baa 3144 OUTS (outf, dregs_lo (dst0));
086134ec 3145 OUTS (outf, " = ");
4b7f6baa 3146 OUTS (outf, dregs (src0));
086134ec 3147 OUTS (outf, " - ");
4b7f6baa 3148 OUTS (outf, dregs (src1));
086134ec 3149 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3150 }
3151 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3152 {
4b7f6baa 3153 OUTS (outf, dregs_lo (dst0));
086134ec 3154 OUTS (outf, " = ");
4b7f6baa 3155 OUTS (outf, dregs (src0));
086134ec 3156 OUTS (outf, " + ");
4b7f6baa 3157 OUTS (outf, dregs (src1));
086134ec 3158 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3159 }
3160 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3161 {
4b7f6baa 3162 OUTS (outf, dregs_lo (dst0));
086134ec 3163 OUTS (outf, " = ");
4b7f6baa 3164 OUTS (outf, dregs (src0));
086134ec 3165 OUTS (outf, " - ");
4b7f6baa 3166 OUTS (outf, dregs (src1));
086134ec 3167 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3168 }
3169 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3170 {
4b7f6baa 3171 OUTS (outf, dregs_hi (dst0));
086134ec 3172 OUTS (outf, " = ");
4b7f6baa 3173 OUTS (outf, dregs (src0));
086134ec 3174 OUTS (outf, " + ");
4b7f6baa 3175 OUTS (outf, dregs (src1));
086134ec 3176 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3177 }
3178 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3179 {
4b7f6baa 3180 OUTS (outf, dregs_lo (dst0));
086134ec 3181 OUTS (outf, " = ");
4b7f6baa 3182 OUTS (outf, dregs (src0));
086134ec 3183 OUTS (outf, " + ");
4b7f6baa 3184 OUTS (outf, dregs (src1));
086134ec 3185 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3186 }
3187 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3188 {
4b7f6baa 3189 OUTS (outf, dregs_hi (dst0));
086134ec 3190 OUTS (outf, " = ");
4b7f6baa 3191 OUTS (outf, dregs (src0));
086134ec 3192 OUTS (outf, " - ");
4b7f6baa 3193 OUTS (outf, dregs (src1));
086134ec 3194 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3195 }
3196 else if (HL == 1 && aop == 0 && aopcde == 2)
3197 {
4b7f6baa 3198 OUTS (outf, dregs_hi (dst0));
086134ec 3199 OUTS (outf, " = ");
4b7f6baa 3200 OUTS (outf, dregs_lo (src0));
086134ec 3201 OUTS (outf, " + ");
4b7f6baa 3202 OUTS (outf, dregs_lo (src1));
4b7f6baa 3203 amod1 (s, x, outf);
4b7f6baa
CM		 3204 }
3205 else if (HL == 1 && aop == 1 && aopcde == 2)
3206 {
4b7f6baa 3207 OUTS (outf, dregs_hi (dst0));
086134ec 3208 OUTS (outf, " = ");
4b7f6baa 3209 OUTS (outf, dregs_lo (src0));
086134ec 3210 OUTS (outf, " + ");
4b7f6baa 3211 OUTS (outf, dregs_hi (src1));
4b7f6baa 3212 amod1 (s, x, outf);
4b7f6baa
CM		 3213 }
3214 else if (HL == 1 && aop == 2 && aopcde == 2)
3215 {
4b7f6baa 3216 OUTS (outf, dregs_hi (dst0));
086134ec 3217 OUTS (outf, " = ");
4b7f6baa 3218 OUTS (outf, dregs_hi (src0));
086134ec 3219 OUTS (outf, " + ");
4b7f6baa 3220 OUTS (outf, dregs_lo (src1));
4b7f6baa 3221 amod1 (s, x, outf);
4b7f6baa
CM		 3222 }
3223 else if (HL == 1 && aop == 3 && aopcde == 2)
3224 {
4b7f6baa 3225 OUTS (outf, dregs_hi (dst0));
086134ec 3226 OUTS (outf, " = ");
4b7f6baa 3227 OUTS (outf, dregs_hi (src0));
086134ec 3228 OUTS (outf, " + ");
4b7f6baa 3229 OUTS (outf, dregs_hi (src1));
4b7f6baa 3230 amod1 (s, x, outf);
4b7f6baa
CM		 3231 }
3232 else if (HL == 0 && aop == 0 && aopcde == 3)
3233 {
4b7f6baa 3234 OUTS (outf, dregs_lo (dst0));
086134ec 3235 OUTS (outf, " = ");
4b7f6baa 3236 OUTS (outf, dregs_lo (src0));
086134ec 3237 OUTS (outf, " - ");
4b7f6baa 3238 OUTS (outf, dregs_lo (src1));
4b7f6baa 3239 amod1 (s, x, outf);
4b7f6baa
CM		 3240 }
3241 else if (HL == 0 && aop == 1 && aopcde == 3)
3242 {
4b7f6baa 3243 OUTS (outf, dregs_lo (dst0));
086134ec 3244 OUTS (outf, " = ");
4b7f6baa 3245 OUTS (outf, dregs_lo (src0));
086134ec 3246 OUTS (outf, " - ");
4b7f6baa 3247 OUTS (outf, dregs_hi (src1));
4b7f6baa 3248 amod1 (s, x, outf);
4b7f6baa
CM		 3249 }
3250 else if (HL == 0 && aop == 3 && aopcde == 2)
3251 {
4b7f6baa 3252 OUTS (outf, dregs_lo (dst0));
086134ec 3253 OUTS (outf, " = ");
4b7f6baa 3254 OUTS (outf, dregs_hi (src0));
086134ec 3255 OUTS (outf, " + ");
4b7f6baa 3256 OUTS (outf, dregs_hi (src1));
4b7f6baa 3257 amod1 (s, x, outf);
4b7f6baa
CM		 3258 }
3259 else if (HL == 1 && aop == 0 && aopcde == 3)
3260 {
4b7f6baa 3261 OUTS (outf, dregs_hi (dst0));
086134ec 3262 OUTS (outf, " = ");
4b7f6baa 3263 OUTS (outf, dregs_lo (src0));
086134ec 3264 OUTS (outf, " - ");
4b7f6baa 3265 OUTS (outf, dregs_lo (src1));
4b7f6baa 3266 amod1 (s, x, outf);
4b7f6baa
CM		 3267 }
3268 else if (HL == 1 && aop == 1 && aopcde == 3)
3269 {
4b7f6baa 3270 OUTS (outf, dregs_hi (dst0));
086134ec 3271 OUTS (outf, " = ");
4b7f6baa 3272 OUTS (outf, dregs_lo (src0));
086134ec 3273 OUTS (outf, " - ");
4b7f6baa 3274 OUTS (outf, dregs_hi (src1));
4b7f6baa 3275 amod1 (s, x, outf);
4b7f6baa
CM		 3276 }
3277 else if (HL == 1 && aop == 2 && aopcde == 3)
3278 {
4b7f6baa 3279 OUTS (outf, dregs_hi (dst0));
086134ec 3280 OUTS (outf, " = ");
4b7f6baa 3281 OUTS (outf, dregs_hi (src0));
086134ec 3282 OUTS (outf, " - ");
4b7f6baa 3283 OUTS (outf, dregs_lo (src1));
4b7f6baa 3284 amod1 (s, x, outf);
4b7f6baa
CM		 3285 }
3286 else if (HL == 1 && aop == 3 && aopcde == 3)
3287 {
4b7f6baa 3288 OUTS (outf, dregs_hi (dst0));
086134ec 3289 OUTS (outf, " = ");
4b7f6baa 3290 OUTS (outf, dregs_hi (src0));
086134ec 3291 OUTS (outf, " - ");
4b7f6baa 3292 OUTS (outf, dregs_hi (src1));
4b7f6baa 3293 amod1 (s, x, outf);
4b7f6baa
CM		 3294 }
3295 else if (HL == 0 && aop == 2 && aopcde == 2)
3296 {
4b7f6baa 3297 OUTS (outf, dregs_lo (dst0));
086134ec 3298 OUTS (outf, " = ");
4b7f6baa 3299 OUTS (outf, dregs_hi (src0));
086134ec 3300 OUTS (outf, " + ");
4b7f6baa 3301 OUTS (outf, dregs_lo (src1));
4b7f6baa 3302 amod1 (s, x, outf);
4b7f6baa
CM		 3303 }
3304 else if (HL == 0 && aop == 1 && aopcde == 2)
3305 {
4b7f6baa 3306 OUTS (outf, dregs_lo (dst0));
086134ec 3307 OUTS (outf, " = ");
4b7f6baa 3308 OUTS (outf, dregs_lo (src0));
086134ec 3309 OUTS (outf, " + ");
4b7f6baa 3310 OUTS (outf, dregs_hi (src1));
4b7f6baa 3311 amod1 (s, x, outf);
4b7f6baa
CM		 3312 }
3313 else if (HL == 0 && aop == 2 && aopcde == 3)
3314 {
4b7f6baa 3315 OUTS (outf, dregs_lo (dst0));
086134ec 3316 OUTS (outf, " = ");
4b7f6baa 3317 OUTS (outf, dregs_hi (src0));
086134ec 3318 OUTS (outf, " - ");
4b7f6baa 3319 OUTS (outf, dregs_lo (src1));
4b7f6baa 3320 amod1 (s, x, outf);
4b7f6baa
CM		 3321 }
3322 else if (HL == 0 && aop == 3 && aopcde == 3)
3323 {
4b7f6baa 3324 OUTS (outf, dregs_lo (dst0));
086134ec 3325 OUTS (outf, " = ");
4b7f6baa 3326 OUTS (outf, dregs_hi (src0));
086134ec 3327 OUTS (outf, " - ");
4b7f6baa 3328 OUTS (outf, dregs_hi (src1));
4b7f6baa 3329 amod1 (s, x, outf);
4b7f6baa
CM		 3330 }
3331 else if (HL == 0 && aop == 0 && aopcde == 2)
3332 {
4b7f6baa 3333 OUTS (outf, dregs_lo (dst0));
086134ec 3334 OUTS (outf, " = ");
4b7f6baa 3335 OUTS (outf, dregs_lo (src0));
086134ec 3336 OUTS (outf, " + ");
4b7f6baa 3337 OUTS (outf, dregs_lo (src1));
4b7f6baa 3338 amod1 (s, x, outf);
4b7f6baa
CM		 3339 }
3340 else if (aop == 0 && aopcde == 9 && s == 1)
3341 {
086134ec 3342 OUTS (outf, "A0 = ");
4b7f6baa 3343 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3344 }
3345 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3346 OUTS (outf, "A0 -= A1");
b7d48530 3347
4b7f6baa 3348 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3349 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3350
4b7f6baa
CM		 3351 else if (aop == 1 && aopcde == 22 && HL == 1)
3352 {
4b7f6baa 3353 OUTS (outf, dregs (dst0));
086134ec 3354 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3355 OUTS (outf, dregs (src0 + 1));
3356 OUTS (outf, ":");
086134ec
BS		 3357 OUTS (outf, imm5d (src0));
3358 OUTS (outf, ", ");
4b7f6baa
CM		 3359 OUTS (outf, dregs (src1 + 1));
3360 OUTS (outf, ":");
086134ec
BS		 3361 OUTS (outf, imm5d (src1));
3362 OUTS (outf, ") (TH");
4b7f6baa
CM		 3363 if (s == 1)
3364 OUTS (outf, ", R)");
3365 else
3366 OUTS (outf, ")");
4b7f6baa
CM		 3367 }
3368 else if (aop == 1 && aopcde == 22 && HL == 0)
3369 {
4b7f6baa 3370 OUTS (outf, dregs (dst0));
086134ec 3371 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3372 OUTS (outf, dregs (src0 + 1));
3373 OUTS (outf, ":");
086134ec
BS		 3374 OUTS (outf, imm5d (src0));
3375 OUTS (outf, ", ");
4b7f6baa
CM		 3376 OUTS (outf, dregs (src1 + 1));
3377 OUTS (outf, ":");
086134ec
BS		 3378 OUTS (outf, imm5d (src1));
3379 OUTS (outf, ") (TL");
4b7f6baa
CM		 3380 if (s == 1)
3381 OUTS (outf, ", R)");
3382 else
3383 OUTS (outf, ")");
4b7f6baa
CM		 3384 }
3385 else if (aop == 0 && aopcde == 22 && HL == 1)
3386 {
4b7f6baa 3387 OUTS (outf, dregs (dst0));
086134ec 3388 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3389 OUTS (outf, dregs (src0 + 1));
3390 OUTS (outf, ":");
086134ec
BS		 3391 OUTS (outf, imm5d (src0));
3392 OUTS (outf, ", ");
4b7f6baa
CM		 3393 OUTS (outf, dregs (src1 + 1));
3394 OUTS (outf, ":");
086134ec
BS		 3395 OUTS (outf, imm5d (src1));
3396 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3397 if (s == 1)
3398 OUTS (outf, ", R)");
3399 else
3400 OUTS (outf, ")");
4b7f6baa
CM		 3401 }
3402 else if (aop == 0 && aopcde == 22 && HL == 0)
3403 {
4b7f6baa 3404 OUTS (outf, dregs (dst0));
086134ec 3405 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3406 OUTS (outf, dregs (src0 + 1));
3407 OUTS (outf, ":");
086134ec
BS		 3408 OUTS (outf, imm5d (src0));
3409 OUTS (outf, ", ");
4b7f6baa
CM		 3410 OUTS (outf, dregs (src1 + 1));
3411 OUTS (outf, ":");
086134ec
BS		 3412 OUTS (outf, imm5d (src1));
3413 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3414 if (s == 1)
3415 OUTS (outf, ", R)");
3416 else
3417 OUTS (outf, ")");
4b7f6baa
CM		 3418 }
3419 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3420 OUTS (outf, "A0 = 0");
b7d48530 3421
4b7f6baa 3422 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3423 OUTS (outf, "A0 = A0 (S)");
b7d48530 3424
4b7f6baa 3425 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3426 OUTS (outf, "A1 = 0");
b7d48530 3427
4b7f6baa 3428 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3429 OUTS (outf, "A1 = A1 (S)");
b7d48530 3430
4b7f6baa 3431 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3432 OUTS (outf, "A1 = A0 = 0");
b7d48530 3433
4b7f6baa 3434 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3435 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3436
4b7f6baa 3437 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3438 OUTS (outf, "A0 = A1");
b7d48530 3439
4b7f6baa 3440 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3441 OUTS (outf, "A1 = A0");
b7d48530 3442
4b7f6baa
CM		 3443 else if (aop == 1 && aopcde == 9 && s == 0)
3444 {
086134ec 3445 OUTS (outf, "A0.X = ");
4b7f6baa 3446 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3447 }
3448 else if (aop == 1 && HL == 0 && aopcde == 11)
3449 {
4b7f6baa 3450 OUTS (outf, dregs_lo (dst0));
086134ec 3451 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3452 }
3453 else if (aop == 3 && HL == 0 && aopcde == 16)
13c02f06 3454 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
b7d48530 3455
4b7f6baa
CM		 3456 else if (aop == 0 && aopcde == 23 && HL == 1)
3457 {
4b7f6baa 3458 OUTS (outf, dregs (dst0));
086134ec 3459 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3460 OUTS (outf, dregs (src0 + 1));
3461 OUTS (outf, ":");
086134ec
BS		 3462 OUTS (outf, imm5d (src0));
3463 OUTS (outf, ", ");
4b7f6baa
CM		 3464 OUTS (outf, dregs (src1 + 1));
3465 OUTS (outf, ":");
086134ec
BS		 3466 OUTS (outf, imm5d (src1));
3467 OUTS (outf, ") (HI");
4b7f6baa
CM		 3468 if (s == 1)
3469 OUTS (outf, ", R)");
3470 else
3471 OUTS (outf, ")");
4b7f6baa
CM		 3472 }
3473 else if (aop == 3 && aopcde == 9 && s == 0)
3474 {
086134ec 3475 OUTS (outf, "A1.X = ");
4b7f6baa 3476 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3477 }
3478 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3479 OUTS (outf, "A1 = ABS A1");
b7d48530 3480
4b7f6baa 3481 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3482 OUTS (outf, "A1 = ABS A0");
b7d48530 3483
4b7f6baa
CM		 3484 else if (aop == 2 && aopcde == 9 && s == 1)
3485 {
086134ec 3486 OUTS (outf, "A1 = ");
4b7f6baa 3487 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3488 }
3489 else if (HL == 0 && aop == 3 && aopcde == 12)
3490 {
4b7f6baa 3491 OUTS (outf, dregs_lo (dst0));
086134ec 3492 OUTS (outf, " = ");
4b7f6baa 3493 OUTS (outf, dregs (src0));
086134ec 3494 OUTS (outf, " (RND)");
4b7f6baa
CM		 3495 }
3496 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3497 OUTS (outf, "A0 = ABS A1");
b7d48530 3498
4b7f6baa 3499 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3500 OUTS (outf, "A0 = ABS A0");
b7d48530 3501
4b7f6baa
CM		 3502 else if (aop == 3 && HL == 0 && aopcde == 15)
3503 {
4b7f6baa 3504 OUTS (outf, dregs (dst0));
086134ec 3505 OUTS (outf, " = -");
4b7f6baa 3506 OUTS (outf, dregs (src0));
086134ec 3507 OUTS (outf, " (V)");
4b7f6baa
CM		 3508 }
3509 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3510 {
4b7f6baa 3511 OUTS (outf, dregs (dst0));
086134ec 3512 OUTS (outf, " = -");
4b7f6baa 3513 OUTS (outf, dregs (src0));
086134ec 3514 OUTS (outf, " (S)");
4b7f6baa
CM		 3515 }
3516 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3517 {
4b7f6baa 3518 OUTS (outf, dregs (dst0));
086134ec 3519 OUTS (outf, " = -");
4b7f6baa 3520 OUTS (outf, dregs (src0));
086134ec 3521 OUTS (outf, " (NS)");
4b7f6baa
CM		 3522 }
3523 else if (aop == 1 && HL == 1 && aopcde == 11)
3524 {
4b7f6baa 3525 OUTS (outf, dregs_hi (dst0));
086134ec 3526 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3527 }
3528 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3529 OUTS (outf, "A0 += A1");
b7d48530 3530
4b7f6baa 3531 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3532 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3533
4b7f6baa 3534 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3535 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3536
4b7f6baa
CM		 3537 else if (HL == 1 && aop == 3 && aopcde == 12)
3538 {
4b7f6baa 3539 OUTS (outf, dregs_hi (dst0));
086134ec 3540 OUTS (outf, " = ");
4b7f6baa 3541 OUTS (outf, dregs (src0));
086134ec 3542 OUTS (outf, " (RND)");
4b7f6baa
CM		 3543 }
3544 else if (aop == 0 && aopcde == 23 && HL == 0)
3545 {
4b7f6baa 3546 OUTS (outf, dregs (dst0));
086134ec 3547 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3548 OUTS (outf, dregs (src0 + 1));
3549 OUTS (outf, ":");
086134ec
BS		 3550 OUTS (outf, imm5d (src0));
3551 OUTS (outf, ", ");
4b7f6baa
CM		 3552 OUTS (outf, dregs (src1 + 1));
3553 OUTS (outf, ":");
086134ec
BS		 3554 OUTS (outf, imm5d (src1));
3555 OUTS (outf, ") (LO");
4b7f6baa
CM		 3556 if (s == 1)
3557 OUTS (outf, ", R)");
3558 else
3559 OUTS (outf, ")");
4b7f6baa
CM		 3560 }
3561 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3562 OUTS (outf, "A0 = -A0");
b7d48530 3563
4b7f6baa 3564 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3565 OUTS (outf, "A0 = -A1");
b7d48530 3566
4b7f6baa 3567 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3568 OUTS (outf, "A1 = -A0");
b7d48530 3569
4b7f6baa 3570 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3571 OUTS (outf, "A1 = -A1");
b7d48530 3572
4b7f6baa
CM		 3573 else if (aop == 0 && aopcde == 12)
3574 {
4b7f6baa 3575 OUTS (outf, dregs_hi (dst0));
086134ec 3576 OUTS (outf, " = ");
4b7f6baa 3577 OUTS (outf, dregs_lo (dst0));
086134ec 3578 OUTS (outf, " = SIGN (");
4b7f6baa 3579 OUTS (outf, dregs_hi (src0));
086134ec 3580 OUTS (outf, ") * ");
4b7f6baa 3581 OUTS (outf, dregs_hi (src1));
086134ec 3582 OUTS (outf, " + SIGN (");
4b7f6baa 3583 OUTS (outf, dregs_lo (src0));
086134ec 3584 OUTS (outf, ") * ");
4b7f6baa 3585 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3586 }
3587 else if (aop == 2 && aopcde == 0)
3588 {
4b7f6baa 3589 OUTS (outf, dregs (dst0));
086134ec 3590 OUTS (outf, " = ");
4b7f6baa 3591 OUTS (outf, dregs (src0));
086134ec 3592 OUTS (outf, " -|+ ");
4b7f6baa 3593 OUTS (outf, dregs (src1));
4b7f6baa 3594 amod0 (s, x, outf);
4b7f6baa
CM		 3595 }
3596 else if (aop == 1 && aopcde == 12)
3597 {
4b7f6baa 3598 OUTS (outf, dregs (dst1));
086134ec 3599 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3600 OUTS (outf, dregs (dst0));
086134ec 3601 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3602 }
3603 else if (aop == 2 && aopcde == 4)
3604 {
4b7f6baa 3605 OUTS (outf, dregs (dst1));
086134ec 3606 OUTS (outf, " = ");
4b7f6baa 3607 OUTS (outf, dregs (src0));
086134ec 3608 OUTS (outf, " + ");
4b7f6baa 3609 OUTS (outf, dregs (src1));
086134ec 3610 OUTS (outf, ", ");
4b7f6baa 3611 OUTS (outf, dregs (dst0));
086134ec 3612 OUTS (outf, " = ");
4b7f6baa 3613 OUTS (outf, dregs (src0));
086134ec 3614 OUTS (outf, " - ");
4b7f6baa 3615 OUTS (outf, dregs (src1));
4b7f6baa 3616 amod1 (s, x, outf);
4b7f6baa
CM		 3617 }
3618 else if (HL == 0 && aopcde == 1)
3619 {
4b7f6baa 3620 OUTS (outf, dregs (dst1));
086134ec 3621 OUTS (outf, " = ");
4b7f6baa 3622 OUTS (outf, dregs (src0));
086134ec 3623 OUTS (outf, " +|+ ");
4b7f6baa 3624 OUTS (outf, dregs (src1));
086134ec 3625 OUTS (outf, ", ");
4b7f6baa 3626 OUTS (outf, dregs (dst0));
086134ec 3627 OUTS (outf, " = ");
4b7f6baa 3628 OUTS (outf, dregs (src0));
086134ec 3629 OUTS (outf, " -|- ");
4b7f6baa
CM		 3630 OUTS (outf, dregs (src1));
3631 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3632 }
3633 else if (aop == 0 && aopcde == 11)
3634 {
4b7f6baa 3635 OUTS (outf, dregs (dst0));
086134ec 3636 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3637 }
3638 else if (aop == 0 && aopcde == 10)
3639 {
4b7f6baa 3640 OUTS (outf, dregs_lo (dst0));
086134ec 3641 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3642 }
3643 else if (aop == 1 && aopcde == 10)
3644 {
4b7f6baa 3645 OUTS (outf, dregs_lo (dst0));
086134ec 3646 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3647 }
3648 else if (aop == 1 && aopcde == 0)
3649 {
4b7f6baa 3650 OUTS (outf, dregs (dst0));
086134ec 3651 OUTS (outf, " = ");
4b7f6baa 3652 OUTS (outf, dregs (src0));
086134ec 3653 OUTS (outf, " +|- ");
4b7f6baa 3654 OUTS (outf, dregs (src1));
4b7f6baa 3655 amod0 (s, x, outf);
4b7f6baa
CM		 3656 }
3657 else if (aop == 3 && aopcde == 0)
3658 {
4b7f6baa 3659 OUTS (outf, dregs (dst0));
086134ec 3660 OUTS (outf, " = ");
4b7f6baa 3661 OUTS (outf, dregs (src0));
086134ec 3662 OUTS (outf, " -|- ");
4b7f6baa 3663 OUTS (outf, dregs (src1));
4b7f6baa 3664 amod0 (s, x, outf);
4b7f6baa
CM		 3665 }
3666 else if (aop == 1 && aopcde == 4)
3667 {
4b7f6baa 3668 OUTS (outf, dregs (dst0));
086134ec 3669 OUTS (outf, " = ");
4b7f6baa 3670 OUTS (outf, dregs (src0));
086134ec 3671 OUTS (outf, " - ");
4b7f6baa 3672 OUTS (outf, dregs (src1));
4b7f6baa 3673 amod1 (s, x, outf);
4b7f6baa
CM		 3674 }
3675 else if (aop == 0 && aopcde == 17)
3676 {
4b7f6baa 3677 OUTS (outf, dregs (dst1));
086134ec 3678 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3679 OUTS (outf, dregs (dst0));
086134ec 3680 OUTS (outf, " = A1 - A0");
4b7f6baa 3681 amod1 (s, x, outf);
4b7f6baa
CM		 3682 }
3683 else if (aop == 1 && aopcde == 17)
3684 {
4b7f6baa 3685 OUTS (outf, dregs (dst1));
086134ec 3686 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3687 OUTS (outf, dregs (dst0));
086134ec 3688 OUTS (outf, " = A0 - A1");
4b7f6baa 3689 amod1 (s, x, outf);
4b7f6baa
CM		 3690 }
3691 else if (aop == 0 && aopcde == 18)
3692 {
086134ec 3693 OUTS (outf, "SAA (");
4b7f6baa
CM		 3694 OUTS (outf, dregs (src0 + 1));
3695 OUTS (outf, ":");
086134ec
BS		 3696 OUTS (outf, imm5d (src0));
3697 OUTS (outf, ", ");
4b7f6baa
CM		 3698 OUTS (outf, dregs (src1 + 1));
3699 OUTS (outf, ":");
086134ec
BS		 3700 OUTS (outf, imm5d (src1));
3701 OUTS (outf, ")");
4b7f6baa 3702 aligndir (s, outf);
4b7f6baa
CM		 3703 }
3704 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3705 OUTS (outf, "DISALGNEXCPT");
3706
4b7f6baa
CM		 3707 else if (aop == 0 && aopcde == 20)
3708 {
4b7f6baa 3709 OUTS (outf, dregs (dst0));
086134ec 3710 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3711 OUTS (outf, dregs (src0 + 1));
3712 OUTS (outf, ":");
086134ec
BS		 3713 OUTS (outf, imm5d (src0));
3714 OUTS (outf, ", ");
4b7f6baa
CM		 3715 OUTS (outf, dregs (src1 + 1));
3716 OUTS (outf, ":");
086134ec 3717 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3718 OUTS (outf, ")");
3719 aligndir (s, outf);
4b7f6baa
CM		 3720 }
3721 else if (aop == 1 && aopcde == 20)
3722 {
4b7f6baa 3723 OUTS (outf, dregs (dst0));
086134ec 3724 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3725 OUTS (outf, dregs (src0 + 1));
3726 OUTS (outf, ":");
086134ec
BS		 3727 OUTS (outf, imm5d (src0));
3728 OUTS (outf, ", ");
4b7f6baa
CM		 3729 OUTS (outf, dregs (src1 + 1));
3730 OUTS (outf, ":");
086134ec
BS		 3731 OUTS (outf, imm5d (src1));
3732 OUTS (outf, ") (T");
4b7f6baa
CM		 3733 if (s == 1)
3734 OUTS (outf, ", R)");
3735 else
3736 OUTS (outf, ")");
4b7f6baa
CM		 3737 }
3738 else if (aop == 0 && aopcde == 21)
3739 {
4b7f6baa
CM		 3740 OUTS (outf, "(");
3741 OUTS (outf, dregs (dst1));
086134ec 3742 OUTS (outf, ", ");
4b7f6baa 3743 OUTS (outf, dregs (dst0));
086134ec 3744 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3745 OUTS (outf, dregs (src0 + 1));
3746 OUTS (outf, ":");
086134ec
BS		 3747 OUTS (outf, imm5d (src0));
3748 OUTS (outf, ", ");
4b7f6baa
CM		 3749 OUTS (outf, dregs (src1 + 1));
3750 OUTS (outf, ":");
086134ec
BS		 3751 OUTS (outf, imm5d (src1));
3752 OUTS (outf, ")");
4b7f6baa 3753 aligndir (s, outf);
4b7f6baa
CM		 3754 }
3755 else if (aop == 1 && aopcde == 21)
3756 {
4b7f6baa
CM		 3757 OUTS (outf, "(");
3758 OUTS (outf, dregs (dst1));
086134ec 3759 OUTS (outf, ", ");
4b7f6baa 3760 OUTS (outf, dregs (dst0));
086134ec 3761 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3762 OUTS (outf, dregs (src0 + 1));
3763 OUTS (outf, ":");
086134ec
BS		 3764 OUTS (outf, imm5d (src0));
3765 OUTS (outf, ", ");
4b7f6baa
CM		 3766 OUTS (outf, dregs (src1 + 1));
3767 OUTS (outf, ":");
086134ec
BS		 3768 OUTS (outf, imm5d (src1));
3769 OUTS (outf, ")");
4b7f6baa 3770 aligndir (s, outf);
4b7f6baa
CM		 3771 }
3772 else if (aop == 2 && aopcde == 7)
3773 {
4b7f6baa 3774 OUTS (outf, dregs (dst0));
086134ec 3775 OUTS (outf, " = ABS ");
4b7f6baa 3776 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3777 }
3778 else if (aop == 1 && aopcde == 7)
3779 {
4b7f6baa 3780 OUTS (outf, dregs (dst0));
086134ec 3781 OUTS (outf, " = MIN (");
4b7f6baa 3782 OUTS (outf, dregs (src0));
086134ec 3783 OUTS (outf, ", ");
4b7f6baa
CM		 3784 OUTS (outf, dregs (src1));
3785 OUTS (outf, ")");
4b7f6baa
CM		 3786 }
3787 else if (aop == 0 && aopcde == 7)
3788 {
4b7f6baa 3789 OUTS (outf, dregs (dst0));
086134ec 3790 OUTS (outf, " = MAX (");
4b7f6baa 3791 OUTS (outf, dregs (src0));
086134ec 3792 OUTS (outf, ", ");
4b7f6baa
CM		 3793 OUTS (outf, dregs (src1));
3794 OUTS (outf, ")");
4b7f6baa
CM		 3795 }
3796 else if (aop == 2 && aopcde == 6)
3797 {
4b7f6baa 3798 OUTS (outf, dregs (dst0));
086134ec 3799 OUTS (outf, " = ABS ");
4b7f6baa 3800 OUTS (outf, dregs (src0));
086134ec 3801 OUTS (outf, " (V)");
4b7f6baa
CM		 3802 }
3803 else if (aop == 1 && aopcde == 6)
3804 {
4b7f6baa 3805 OUTS (outf, dregs (dst0));
086134ec 3806 OUTS (outf, " = MIN (");
4b7f6baa 3807 OUTS (outf, dregs (src0));
086134ec 3808 OUTS (outf, ", ");
4b7f6baa 3809 OUTS (outf, dregs (src1));
086134ec 3810 OUTS (outf, ") (V)");
4b7f6baa
CM		 3811 }
3812 else if (aop == 0 && aopcde == 6)
3813 {
4b7f6baa 3814 OUTS (outf, dregs (dst0));
086134ec 3815 OUTS (outf, " = MAX (");
4b7f6baa 3816 OUTS (outf, dregs (src0));
086134ec 3817 OUTS (outf, ", ");
4b7f6baa 3818 OUTS (outf, dregs (src1));
086134ec 3819 OUTS (outf, ") (V)");
4b7f6baa
CM		 3820 }
3821 else if (HL == 1 && aopcde == 1)
3822 {
4b7f6baa 3823 OUTS (outf, dregs (dst1));
086134ec 3824 OUTS (outf, " = ");
4b7f6baa 3825 OUTS (outf, dregs (src0));
086134ec 3826 OUTS (outf, " +|- ");
4b7f6baa 3827 OUTS (outf, dregs (src1));
086134ec 3828 OUTS (outf, ", ");
4b7f6baa 3829 OUTS (outf, dregs (dst0));
086134ec 3830 OUTS (outf, " = ");
4b7f6baa 3831 OUTS (outf, dregs (src0));
086134ec 3832 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3833 OUTS (outf, dregs (src1));
3834 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3835 }
3836 else if (aop == 0 && aopcde == 4)
3837 {
4b7f6baa 3838 OUTS (outf, dregs (dst0));
086134ec 3839 OUTS (outf, " = ");
4b7f6baa 3840 OUTS (outf, dregs (src0));
086134ec 3841 OUTS (outf, " + ");
4b7f6baa 3842 OUTS (outf, dregs (src1));
4b7f6baa 3843 amod1 (s, x, outf);
4b7f6baa
CM		 3844 }
3845 else if (aop == 0 && aopcde == 0)
3846 {
4b7f6baa 3847 OUTS (outf, dregs (dst0));
086134ec 3848 OUTS (outf, " = ");
4b7f6baa 3849 OUTS (outf, dregs (src0));
086134ec 3850 OUTS (outf, " +|+ ");
4b7f6baa 3851 OUTS (outf, dregs (src1));
4b7f6baa 3852 amod0 (s, x, outf);
4b7f6baa
CM		 3853 }
3854 else if (aop == 0 && aopcde == 24)
3855 {
4b7f6baa 3856 OUTS (outf, dregs (dst0));
086134ec 3857 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3858 OUTS (outf, dregs (src0));
086134ec 3859 OUTS (outf, ", ");
4b7f6baa
CM		 3860 OUTS (outf, dregs (src1));
3861 OUTS (outf, ")");
4b7f6baa
CM		 3862 }
3863 else if (aop == 1 && aopcde == 24)
3864 {
4b7f6baa
CM		 3865 OUTS (outf, "(");
3866 OUTS (outf, dregs (dst1));
086134ec 3867 OUTS (outf, ", ");
4b7f6baa
CM		 3868 OUTS (outf, dregs (dst0));
3869 OUTS (outf, ") = BYTEUNPACK ");
3870 OUTS (outf, dregs (src0 + 1));
3871 OUTS (outf, ":");
086134ec 3872 OUTS (outf, imm5d (src0));
4b7f6baa 3873 aligndir (s, outf);
4b7f6baa
CM		 3874 }
3875 else if (aopcde == 13)
3876 {
4b7f6baa
CM		 3877 OUTS (outf, "(");
3878 OUTS (outf, dregs (dst1));
086134ec 3879 OUTS (outf, ", ");
4b7f6baa
CM		 3880 OUTS (outf, dregs (dst0));
3881 OUTS (outf, ") = SEARCH ");
3882 OUTS (outf, dregs (src0));
086134ec 3883 OUTS (outf, " (");
4b7f6baa
CM		 3884 searchmod (aop, outf);
3885 OUTS (outf, ")");
4b7f6baa
CM		 3886 }
3887 else
b7d48530
NC		 3888 return 0;
3889
3890 return 4;
4b7f6baa
CM		 3891}
3892
3893static int
3894decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3895{
b7d48530
NC		 3896 /* dsp32shift
3897 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3898 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3899 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3900 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3901 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3902 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3903 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3904 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3905 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3906 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3907 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3908
4b7f6baa
CM		 3909 if (HLs == 0 && sop == 0 && sopcde == 0)
3910 {
4b7f6baa 3911 OUTS (outf, dregs_lo (dst0));
086134ec 3912 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3913 OUTS (outf, dregs_lo (src1));
3914 OUTS (outf, " BY ");
3915 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3916 }
3917 else if (HLs == 1 && sop == 0 && sopcde == 0)
3918 {
4b7f6baa 3919 OUTS (outf, dregs_lo (dst0));
086134ec 3920 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3921 OUTS (outf, dregs_hi (src1));
3922 OUTS (outf, " BY ");
3923 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3924 }
3925 else if (HLs == 2 && sop == 0 && sopcde == 0)
3926 {
4b7f6baa 3927 OUTS (outf, dregs_hi (dst0));
086134ec 3928 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3929 OUTS (outf, dregs_lo (src1));
3930 OUTS (outf, " BY ");
3931 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3932 }
3933 else if (HLs == 3 && sop == 0 && sopcde == 0)
3934 {
4b7f6baa 3935 OUTS (outf, dregs_hi (dst0));
086134ec 3936 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3937 OUTS (outf, dregs_hi (src1));
3938 OUTS (outf, " BY ");
3939 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3940 }
3941 else if (HLs == 0 && sop == 1 && sopcde == 0)
3942 {
4b7f6baa 3943 OUTS (outf, dregs_lo (dst0));
086134ec 3944 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3945 OUTS (outf, dregs_lo (src1));
3946 OUTS (outf, " BY ");
3947 OUTS (outf, dregs_lo (src0));
086134ec 3948 OUTS (outf, " (S)");
4b7f6baa
CM		 3949 }
3950 else if (HLs == 1 && sop == 1 && sopcde == 0)
3951 {
4b7f6baa 3952 OUTS (outf, dregs_lo (dst0));
086134ec 3953 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3954 OUTS (outf, dregs_hi (src1));
3955 OUTS (outf, " BY ");
3956 OUTS (outf, dregs_lo (src0));
086134ec 3957 OUTS (outf, " (S)");
4b7f6baa
CM		 3958 }
3959 else if (HLs == 2 && sop == 1 && sopcde == 0)
3960 {
4b7f6baa 3961 OUTS (outf, dregs_hi (dst0));
086134ec 3962 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3963 OUTS (outf, dregs_lo (src1));
3964 OUTS (outf, " BY ");
3965 OUTS (outf, dregs_lo (src0));
086134ec 3966 OUTS (outf, " (S)");
4b7f6baa
CM		 3967 }
3968 else if (HLs == 3 && sop == 1 && sopcde == 0)
3969 {
4b7f6baa 3970 OUTS (outf, dregs_hi (dst0));
086134ec 3971 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3972 OUTS (outf, dregs_hi (src1));
3973 OUTS (outf, " BY ");
3974 OUTS (outf, dregs_lo (src0));
086134ec 3975 OUTS (outf, " (S)");
4b7f6baa
CM		 3976 }
3977 else if (sop == 2 && sopcde == 0)
3978 {
4b7f6baa 3979 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 3980 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3981 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3982 OUTS (outf, " BY ");
3983 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3984 }
3985 else if (sop == 0 && sopcde == 3)
3986 {
4b7f6baa 3987 OUTS (outf, acc01);
086134ec 3988 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3989 OUTS (outf, acc01);
3990 OUTS (outf, " BY ");
3991 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3992 }
3993 else if (sop == 1 && sopcde == 3)
3994 {
4b7f6baa 3995 OUTS (outf, acc01);
086134ec 3996 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3997 OUTS (outf, acc01);
3998 OUTS (outf, " BY ");
3999 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4000 }
4001 else if (sop == 2 && sopcde == 3)
4002 {
4b7f6baa 4003 OUTS (outf, acc01);
086134ec 4004 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4005 OUTS (outf, acc01);
4006 OUTS (outf, " BY ");
4007 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4008 }
4009 else if (sop == 3 && sopcde == 3)
4010 {
4b7f6baa 4011 OUTS (outf, dregs (dst0));
086134ec 4012 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4013 OUTS (outf, dregs (src1));
4014 OUTS (outf, " BY ");
4015 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4016 }
4017 else if (sop == 1 && sopcde == 1)
4018 {
4b7f6baa 4019 OUTS (outf, dregs (dst0));
086134ec 4020 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4021 OUTS (outf, dregs (src1));
4022 OUTS (outf, " BY ");
4023 OUTS (outf, dregs_lo (src0));
086134ec 4024 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4025 }
4026 else if (sop == 0 && sopcde == 1)
4027 {
4b7f6baa 4028 OUTS (outf, dregs (dst0));
086134ec 4029 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4030 OUTS (outf, dregs (src1));
4031 OUTS (outf, " BY ");
4032 OUTS (outf, dregs_lo (src0));
086134ec 4033 OUTS (outf, " (V)");
4b7f6baa
CM		 4034 }
4035 else if (sop == 0 && sopcde == 2)
4036 {
4b7f6baa 4037 OUTS (outf, dregs (dst0));
086134ec 4038 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4039 OUTS (outf, dregs (src1));
4040 OUTS (outf, " BY ");
4041 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4042 }
4043 else if (sop == 1 && sopcde == 2)
4044 {
4b7f6baa 4045 OUTS (outf, dregs (dst0));
086134ec 4046 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4047 OUTS (outf, dregs (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
086134ec 4050 OUTS (outf, " (S)");
4b7f6baa
CM		 4051 }
4052 else if (sop == 2 && sopcde == 2)
4053 {
4b7f6baa 4054 OUTS (outf, dregs (dst0));
59a82d23 4055 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4056 OUTS (outf, dregs (src1));
4057 OUTS (outf, " BY ");
4058 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4059 }
4060 else if (sop == 3 && sopcde == 2)
4061 {
4b7f6baa 4062 OUTS (outf, dregs (dst0));
086134ec 4063 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4064 OUTS (outf, dregs (src1));
4065 OUTS (outf, " BY ");
4066 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4067 }
4068 else if (sop == 2 && sopcde == 1)
4069 {
4b7f6baa 4070 OUTS (outf, dregs (dst0));
59a82d23 4071 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4072 OUTS (outf, dregs (src1));
4073 OUTS (outf, " BY ");
4074 OUTS (outf, dregs_lo (src0));
086134ec 4075 OUTS (outf, " (V)");
4b7f6baa
CM		 4076 }
4077 else if (sop == 0 && sopcde == 4)
4078 {
4b7f6baa 4079 OUTS (outf, dregs (dst0));
086134ec 4080 OUTS (outf, " = PACK (");
4b7f6baa 4081 OUTS (outf, dregs_lo (src1));
086134ec 4082 OUTS (outf, ", ");
4b7f6baa
CM		 4083 OUTS (outf, dregs_lo (src0));
4084 OUTS (outf, ")");
4b7f6baa
CM		 4085 }
4086 else if (sop == 1 && sopcde == 4)
4087 {
4b7f6baa 4088 OUTS (outf, dregs (dst0));
086134ec 4089 OUTS (outf, " = PACK (");
4b7f6baa 4090 OUTS (outf, dregs_lo (src1));
086134ec 4091 OUTS (outf, ", ");
4b7f6baa
CM		 4092 OUTS (outf, dregs_hi (src0));
4093 OUTS (outf, ")");
4b7f6baa
CM		 4094 }
4095 else if (sop == 2 && sopcde == 4)
4096 {
4b7f6baa 4097 OUTS (outf, dregs (dst0));
086134ec 4098 OUTS (outf, " = PACK (");
4b7f6baa 4099 OUTS (outf, dregs_hi (src1));
086134ec 4100 OUTS (outf, ", ");
4b7f6baa
CM		 4101 OUTS (outf, dregs_lo (src0));
4102 OUTS (outf, ")");
4b7f6baa
CM		 4103 }
4104 else if (sop == 3 && sopcde == 4)
4105 {
4b7f6baa 4106 OUTS (outf, dregs (dst0));
086134ec 4107 OUTS (outf, " = PACK (");
4b7f6baa 4108 OUTS (outf, dregs_hi (src1));
086134ec 4109 OUTS (outf, ", ");
4b7f6baa
CM		 4110 OUTS (outf, dregs_hi (src0));
4111 OUTS (outf, ")");
4b7f6baa
CM		 4112 }
4113 else if (sop == 0 && sopcde == 5)
4114 {
4b7f6baa 4115 OUTS (outf, dregs_lo (dst0));
086134ec 4116 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4117 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4118 }
4119 else if (sop == 1 && sopcde == 5)
4120 {
4b7f6baa 4121 OUTS (outf, dregs_lo (dst0));
086134ec 4122 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4123 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4124 }
4125 else if (sop == 2 && sopcde == 5)
4126 {
4b7f6baa 4127 OUTS (outf, dregs_lo (dst0));
086134ec 4128 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4129 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4130 }
4131 else if (sop == 0 && sopcde == 6)
4132 {
4b7f6baa 4133 OUTS (outf, dregs_lo (dst0));
086134ec 4134 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4135 }
4136 else if (sop == 1 && sopcde == 6)
4137 {
4b7f6baa 4138 OUTS (outf, dregs_lo (dst0));
086134ec 4139 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4140 }
4141 else if (sop == 3 && sopcde == 6)
4142 {
4b7f6baa 4143 OUTS (outf, dregs_lo (dst0));
086134ec 4144 OUTS (outf, " = ONES ");
4b7f6baa 4145 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4146 }
4147 else if (sop == 0 && sopcde == 7)
4148 {
4b7f6baa 4149 OUTS (outf, dregs_lo (dst0));
086134ec 4150 OUTS (outf, " = EXPADJ (");
4b7f6baa 4151 OUTS (outf, dregs (src1));
086134ec 4152 OUTS (outf, ", ");
4b7f6baa
CM		 4153 OUTS (outf, dregs_lo (src0));
4154 OUTS (outf, ")");
4b7f6baa
CM		 4155 }
4156 else if (sop == 1 && sopcde == 7)
4157 {
4b7f6baa 4158 OUTS (outf, dregs_lo (dst0));
086134ec 4159 OUTS (outf, " = EXPADJ (");
4b7f6baa 4160 OUTS (outf, dregs (src1));
086134ec 4161 OUTS (outf, ", ");
4b7f6baa
CM		 4162 OUTS (outf, dregs_lo (src0));
4163 OUTS (outf, ") (V)");
4b7f6baa
CM		 4164 }
4165 else if (sop == 2 && sopcde == 7)
4166 {
4b7f6baa 4167 OUTS (outf, dregs_lo (dst0));
086134ec 4168 OUTS (outf, " = EXPADJ (");
4b7f6baa 4169 OUTS (outf, dregs_lo (src1));
086134ec 4170 OUTS (outf, ", ");
4b7f6baa
CM		 4171 OUTS (outf, dregs_lo (src0));
4172 OUTS (outf, ")");
4b7f6baa
CM		 4173 }
4174 else if (sop == 3 && sopcde == 7)
4175 {
4b7f6baa 4176 OUTS (outf, dregs_lo (dst0));
086134ec 4177 OUTS (outf, " = EXPADJ (");
4b7f6baa 4178 OUTS (outf, dregs_hi (src1));
086134ec 4179 OUTS (outf, ", ");
4b7f6baa
CM		 4180 OUTS (outf, dregs_lo (src0));
4181 OUTS (outf, ")");
4b7f6baa
CM		 4182 }
4183 else if (sop == 0 && sopcde == 8)
4184 {
4b7f6baa
CM		 4185 OUTS (outf, "BITMUX (");
4186 OUTS (outf, dregs (src0));
086134ec 4187 OUTS (outf, ", ");
4b7f6baa 4188 OUTS (outf, dregs (src1));
086134ec 4189 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4190 }
4191 else if (sop == 1 && sopcde == 8)
4192 {
4b7f6baa
CM		 4193 OUTS (outf, "BITMUX (");
4194 OUTS (outf, dregs (src0));
086134ec 4195 OUTS (outf, ", ");
4b7f6baa 4196 OUTS (outf, dregs (src1));
086134ec 4197 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4198 }
4199 else if (sop == 0 && sopcde == 9)
4200 {
4b7f6baa 4201 OUTS (outf, dregs_lo (dst0));
086134ec 4202 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4203 OUTS (outf, dregs (src1));
4204 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4205 }
4206 else if (sop == 1 && sopcde == 9)
4207 {
4b7f6baa 4208 OUTS (outf, dregs_lo (dst0));
086134ec 4209 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4210 OUTS (outf, dregs (src1));
4211 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4212 }
4213 else if (sop == 2 && sopcde == 9)
4214 {
4b7f6baa 4215 OUTS (outf, dregs (dst0));
086134ec 4216 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4217 OUTS (outf, dregs (src1));
086134ec 4218 OUTS (outf, ", ");
4b7f6baa 4219 OUTS (outf, dregs (src0));
086134ec 4220 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4221 }
4222 else if (sop == 3 && sopcde == 9)
4223 {
4b7f6baa 4224 OUTS (outf, dregs (dst0));
086134ec 4225 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4226 OUTS (outf, dregs (src1));
086134ec 4227 OUTS (outf, ", ");
4b7f6baa 4228 OUTS (outf, dregs (src0));
086134ec 4229 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4230 }
4231 else if (sop == 0 && sopcde == 10)
4232 {
4b7f6baa 4233 OUTS (outf, dregs (dst0));
086134ec 4234 OUTS (outf, " = EXTRACT (");
4b7f6baa 4235 OUTS (outf, dregs (src1));
086134ec 4236 OUTS (outf, ", ");
4b7f6baa
CM		 4237 OUTS (outf, dregs_lo (src0));
4238 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4239 }
4240 else if (sop == 1 && sopcde == 10)
4241 {
4b7f6baa 4242 OUTS (outf, dregs (dst0));
086134ec 4243 OUTS (outf, " = EXTRACT (");
4b7f6baa 4244 OUTS (outf, dregs (src1));
086134ec 4245 OUTS (outf, ", ");
4b7f6baa 4246 OUTS (outf, dregs_lo (src0));
086134ec 4247 OUTS (outf, ") (X)");
4b7f6baa
CM		 4248 }
4249 else if (sop == 2 && sopcde == 10)
4250 {
4b7f6baa 4251 OUTS (outf, dregs (dst0));
086134ec 4252 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4253 OUTS (outf, dregs (src1));
086134ec 4254 OUTS (outf, ", ");
4b7f6baa
CM		 4255 OUTS (outf, dregs (src0));
4256 OUTS (outf, ")");
4b7f6baa
CM		 4257 }
4258 else if (sop == 3 && sopcde == 10)
4259 {
4b7f6baa 4260 OUTS (outf, dregs (dst0));
086134ec 4261 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4262 OUTS (outf, dregs (src1));
086134ec 4263 OUTS (outf, ", ");
4b7f6baa 4264 OUTS (outf, dregs (src0));
086134ec 4265 OUTS (outf, ") (X)");
4b7f6baa
CM		 4266 }
4267 else if (sop == 0 && sopcde == 11)
4268 {
4b7f6baa 4269 OUTS (outf, dregs_lo (dst0));
086134ec 4270 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4271 OUTS (outf, dregs (src0));
4272 OUTS (outf, ")");
4b7f6baa
CM		 4273 }
4274 else if (sop == 1 && sopcde == 11)
4275 {
4b7f6baa 4276 OUTS (outf, dregs_lo (dst0));
086134ec 4277 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4278 OUTS (outf, dregs (src0));
4279 OUTS (outf, ")");
4b7f6baa
CM		 4280 }
4281 else if (sop == 0 && sopcde == 12)
086134ec 4282 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4283
4b7f6baa
CM		 4284 else if (sop == 1 && sopcde == 12)
4285 {
4b7f6baa 4286 OUTS (outf, dregs_lo (dst0));
086134ec 4287 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4288 }
4289 else if (sop == 0 && sopcde == 13)
4290 {
4b7f6baa 4291 OUTS (outf, dregs (dst0));
086134ec 4292 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4293 OUTS (outf, dregs (src1));
086134ec 4294 OUTS (outf, ", ");
4b7f6baa
CM		 4295 OUTS (outf, dregs (src0));
4296 OUTS (outf, ")");
4b7f6baa
CM		 4297 }
4298 else if (sop == 1 && sopcde == 13)
4299 {
4b7f6baa 4300 OUTS (outf, dregs (dst0));
086134ec 4301 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4302 OUTS (outf, dregs (src1));
086134ec 4303 OUTS (outf, ", ");
4b7f6baa
CM		 4304 OUTS (outf, dregs (src0));
4305 OUTS (outf, ")");
4b7f6baa
CM		 4306 }
4307 else if (sop == 2 && sopcde == 13)
4308 {
4b7f6baa 4309 OUTS (outf, dregs (dst0));
086134ec 4310 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4311 OUTS (outf, dregs (src1));
086134ec 4312 OUTS (outf, ", ");
4b7f6baa
CM		 4313 OUTS (outf, dregs (src0));
4314 OUTS (outf, ")");
4b7f6baa
CM		 4315 }
4316 else
b7d48530
NC		 4317 return 0;
4318
4319 return 4;
4b7f6baa
CM		 4320}
4321
4322static int
4323decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4324{
b7d48530
NC		 4325 /* dsp32shiftimm
4326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4327 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4328 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4329 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4330 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4331 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4332 int bit8 = ((iw1 >> 8) & 0x1);
4333 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4334 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4335 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4336 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4337 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa 4338
331f1cbe 4339 if (sop == 0 && sopcde == 0)
4b7f6baa 4340 {
331f1cbe
BS		 4341 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4342 OUTS (outf, " = ");
4343 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4344 OUTS (outf, " >>> ");
4b7f6baa 4345 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4346 }
331f1cbe 4347 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4348 {
331f1cbe
BS		 4349 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4350 OUTS (outf, " = ");
4351 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4352 OUTS (outf, " << ");
4b7f6baa 4353 OUTS (outf, uimm4 (immag));
331f1cbe 4354 OUTS (outf, " (S)");
4b7f6baa 4355 }
331f1cbe 4356 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4357 {
331f1cbe
BS		 4358 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4359 OUTS (outf, " = ");
4360 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4361 OUTS (outf, " >>> ");
4b7f6baa 4362 OUTS (outf, uimm4 (newimmag));
331f1cbe 4363 OUTS (outf, " (S)");
4b7f6baa 4364 }
331f1cbe 4365 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4366 {
331f1cbe
BS		 4367 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4368 OUTS (outf, " = ");
4369 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4370 OUTS (outf, " << ");
4b7f6baa 4371 OUTS (outf, uimm4 (immag));
4b7f6baa 4372 }
331f1cbe 4373 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4374 {
331f1cbe
BS		 4375 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4376 OUTS (outf, " = ");
4377 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4378 OUTS (outf, " >> ");
4b7f6baa 4379 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4380 }
4b7f6baa
CM		 4381 else if (sop == 2 && sopcde == 3 && HLs == 1)
4382 {
086134ec 4383 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4384 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4385 }
4386 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4387 {
086134ec 4388 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4389 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4390 }
4391 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4392 {
086134ec 4393 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4394 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4395 }
4396 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4397 {
086134ec 4398 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4399 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4400 }
4401 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4402 {
086134ec 4403 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4404 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4405 }
4406 else if (sop == 1 && sopcde == 3 && HLs == 0)
4407 {
086134ec 4408 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4409 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4410 }
4411 else if (sop == 1 && sopcde == 3 && HLs == 1)
4412 {
086134ec 4413 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4414 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4415 }
4416 else if (sop == 2 && sopcde == 3 && HLs == 0)
4417 {
086134ec 4418 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4419 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4420 }
4421 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4422 {
4b7f6baa 4423 OUTS (outf, dregs (dst0));
086134ec 4424 OUTS (outf, " = ");
4b7f6baa 4425 OUTS (outf, dregs (src1));
086134ec 4426 OUTS (outf, " << ");
4b7f6baa
CM		 4427 OUTS (outf, uimm5 (immag));
4428 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4429 }
4430 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4431 {
4b7f6baa 4432 OUTS (outf, dregs (dst0));
086134ec 4433 OUTS (outf, " = ");
4b7f6baa 4434 OUTS (outf, dregs (src1));
086134ec 4435 OUTS (outf, " >>> ");
4b7f6baa 4436 OUTS (outf, imm5 (-immag));
0b7691fd 4437 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4438 }
4439 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4440 {
4b7f6baa 4441 OUTS (outf, dregs (dst0));
086134ec 4442 OUTS (outf, " = ");
4b7f6baa
CM		 4443 OUTS (outf, dregs (src1));
4444 OUTS (outf, " >> ");
4445 OUTS (outf, uimm5 (newimmag));
4446 OUTS (outf, " (V)");
4b7f6baa
CM		 4447 }
4448 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4449 {
4b7f6baa 4450 OUTS (outf, dregs (dst0));
086134ec 4451 OUTS (outf, " = ");
4b7f6baa 4452 OUTS (outf, dregs (src1));
086134ec 4453 OUTS (outf, " << ");
4b7f6baa
CM		 4454 OUTS (outf, imm5 (immag));
4455 OUTS (outf, " (V)");
4b7f6baa
CM		 4456 }
4457 else if (sop == 0 && sopcde == 1)
4458 {
4b7f6baa 4459 OUTS (outf, dregs (dst0));
086134ec 4460 OUTS (outf, " = ");
4b7f6baa 4461 OUTS (outf, dregs (src1));
086134ec 4462 OUTS (outf, " >>> ");
4b7f6baa
CM		 4463 OUTS (outf, uimm5 (newimmag));
4464 OUTS (outf, " (V)");
4b7f6baa
CM		 4465 }
4466 else if (sop == 1 && sopcde == 2)
4467 {
4b7f6baa 4468 OUTS (outf, dregs (dst0));
086134ec 4469 OUTS (outf, " = ");
4b7f6baa 4470 OUTS (outf, dregs (src1));
086134ec 4471 OUTS (outf, " << ");
4b7f6baa 4472 OUTS (outf, uimm5 (immag));
086134ec 4473 OUTS (outf, " (S)");
4b7f6baa
CM		 4474 }
4475 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4476 {
4b7f6baa 4477 OUTS (outf, dregs (dst0));
086134ec 4478 OUTS (outf, " = ");
4b7f6baa 4479 OUTS (outf, dregs (src1));
086134ec 4480 OUTS (outf, " >> ");
4b7f6baa 4481 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4482 }
4483 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4484 {
4b7f6baa 4485 OUTS (outf, dregs (dst0));
086134ec 4486 OUTS (outf, " = ");
4b7f6baa 4487 OUTS (outf, dregs (src1));
086134ec 4488 OUTS (outf, " << ");
4b7f6baa 4489 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4490 }
4491 else if (sop == 3 && sopcde == 2)
4492 {
4b7f6baa 4493 OUTS (outf, dregs (dst0));
086134ec 4494 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4495 OUTS (outf, dregs (src1));
4496 OUTS (outf, " BY ");
4497 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4498 }
4499 else if (sop == 0 && sopcde == 2)
4500 {
4b7f6baa 4501 OUTS (outf, dregs (dst0));
086134ec 4502 OUTS (outf, " = ");
4b7f6baa 4503 OUTS (outf, dregs (src1));
086134ec 4504 OUTS (outf, " >>> ");
4b7f6baa 4505 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4506 }
4507 else
b7d48530
NC		 4508 return 0;
4509
4510 return 4;
4b7f6baa
CM		 4511}
4512
4513static int
4514decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4515{
b7d48530
NC		 4516 /* pseudoDEBUG
4517 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4518 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4519 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4520 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4521 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4522 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4523
219b747a
MF		 4524 if (parallel)
4525 return 0;
4526
4b7f6baa 4527 if (reg == 0 && fn == 3)
b7d48530
NC		 4528 OUTS (outf, "DBG A0");
4529
4b7f6baa 4530 else if (reg == 1 && fn == 3)
b7d48530
NC		 4531 OUTS (outf, "DBG A1");
4532
4b7f6baa 4533 else if (reg == 3 && fn == 3)
b7d48530
NC		 4534 OUTS (outf, "ABORT");
4535
4b7f6baa 4536 else if (reg == 4 && fn == 3)
b7d48530
NC		 4537 OUTS (outf, "HLT");
4538
4b7f6baa 4539 else if (reg == 5 && fn == 3)
b7d48530
NC		 4540 OUTS (outf, "DBGHALT");
4541
4b7f6baa
CM		 4542 else if (reg == 6 && fn == 3)
4543 {
086134ec 4544 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4545 OUTS (outf, dregs (grp));
4546 OUTS (outf, ")");
4b7f6baa
CM		 4547 }
4548 else if (reg == 7 && fn == 3)
b7d48530
NC		 4549 OUTS (outf, "DBG");
4550
4b7f6baa
CM		 4551 else if (grp == 0 && fn == 2)
4552 {
73a63ccf 4553 OUTS (outf, "OUTC ");
4b7f6baa 4554 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4555 }
4556 else if (fn == 0)
4557 {
a01eda85 4558 OUTS (outf, "DBG ");
4b7f6baa 4559 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4560 }
4561 else if (fn == 1)
4562 {
9805c0a5 4563 OUTS (outf, "PRNT ");
4b7f6baa 4564 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4565 }
4566 else
b7d48530
NC		 4567 return 0;
4568
4569 return 2;
4b7f6baa
CM		 4570}
4571
73a63ccf
MF		 4572static int
4573decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4574{
4575 /* psedoOChar
4576 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4577 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4578 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4579 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4580
219b747a
MF		 4581 if (parallel)
4582 return 0;
4583
73a63ccf
MF		 4584 OUTS (outf, "OUTC ");
4585 OUTS (outf, uimm8 (ch));
4586
4587 return 2;
4588}
4589
4b7f6baa
CM		 4590static int
4591decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4592{
b7d48530
NC		 4593 /* pseudodbg_assert
4594 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4595 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4596 |.expected......................................................|
4597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4598 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4599 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4600 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4601 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4602
219b747a
MF		 4603 if (parallel)
4604 return 0;
4605
4b7f6baa
CM		 4606 if (dbgop == 0)
4607 {
086134ec 4608 OUTS (outf, "DBGA (");
66a6900a 4609 OUTS (outf, regs_lo (regtest, grp));
086134ec 4610 OUTS (outf, ", ");
4b7f6baa
CM		 4611 OUTS (outf, uimm16 (expected));
4612 OUTS (outf, ")");
4b7f6baa
CM		 4613 }
4614 else if (dbgop == 1)
4615 {
086134ec 4616 OUTS (outf, "DBGA (");
66a6900a 4617 OUTS (outf, regs_hi (regtest, grp));
086134ec 4618 OUTS (outf, ", ");
4b7f6baa
CM		 4619 OUTS (outf, uimm16 (expected));
4620 OUTS (outf, ")");
4b7f6baa
CM		 4621 }
4622 else if (dbgop == 2)
4623 {
086134ec 4624 OUTS (outf, "DBGAL (");
66a6900a 4625 OUTS (outf, allregs (regtest, grp));
086134ec 4626 OUTS (outf, ", ");
4b7f6baa
CM		 4627 OUTS (outf, uimm16 (expected));
4628 OUTS (outf, ")");
4b7f6baa
CM		 4629 }
4630 else if (dbgop == 3)
4631 {
086134ec 4632 OUTS (outf, "DBGAH (");
66a6900a 4633 OUTS (outf, allregs (regtest, grp));
086134ec 4634 OUTS (outf, ", ");
4b7f6baa
CM		 4635 OUTS (outf, uimm16 (expected));
4636 OUTS (outf, ")");
4b7f6baa
CM		 4637 }
4638 else
b7d48530
NC		 4639 return 0;
4640 return 4;
4b7f6baa
CM		 4641}
4642
ad15c38e 4643static int
4b7f6baa
CM		 4644_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4645{
4b7f6baa
CM		 4646 bfd_byte buf[4];
4647 TIword iw0;
4648 TIword iw1;
4649 int status;
b7d48530
NC		 4650 int rv = 0;
4651
4b7f6baa 4652 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
c7e2358a
AM		 4653 /* FIXME */
4654 (void) status;
4b7f6baa 4655 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
c7e2358a
AM		 4656 /* FIXME */
4657 (void) status;
4b7f6baa
CM		 4658
4659 iw0 = bfd_getl16 (buf);
4660 iw1 = bfd_getl16 (buf + 2);
4661
4662 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4663 {
219b747a
MF		 4664 if (parallel)
4665 {
602427c4
MF		 4666 OUTS (outf, "ILLEGAL");
4667 return 0;
219b747a 4668 }
086134ec 4669 OUTS (outf, "MNOP");
4b7f6baa
CM		 4670 return 4;
4671 }
4672 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4673 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4674 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4675 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4676 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4677 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4678 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4679 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4680 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4681 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4682 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4683 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4684 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4685 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4686 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4687 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4688 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4689 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4690 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4691 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4692 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4693 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4694 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4695 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4696 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4697 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4698 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4699 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4700 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4701 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4702 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4703 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4704 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4705 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4706 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4707 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4708 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4709 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4710 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4711 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4712 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4713 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4714 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4715 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4716 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4717 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4718 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4719 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4720 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4721 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4722 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4723 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4724 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4725 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4726 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4727 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4728 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4729 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4730 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4731 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4732 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4733 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4734 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4735 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4736 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4737 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4738 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4739 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4740 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4741 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4742 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4743 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4744 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4745 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4746
219b747a
MF		 4747 if (rv == 0)
4748 OUTS (outf, "ILLEGAL");
4749
b7d48530 4750 return rv;
4b7f6baa
CM		 4751}
4752
4b7f6baa
CM		 4753int
4754print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4755{
471e4e36
JZ		 4756 bfd_byte buf[2];
4757 unsigned short iw0;
4758 int status;
4b7f6baa 4759 int count = 0;
471e4e36
JZ		 4760
4761 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
c7e2358a
AM		 4762 /* FIXME */
4763 (void) status;
471e4e36 4764 iw0 = bfd_getl16 (buf);
4b7f6baa
CM		 4765
4766 count += _print_insn_bfin (pc, outf);
471e4e36 4767
4b7f6baa 4768 /* Proper display of multiple issue instructions. */
471e4e36 4769
219b747a 4770 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
b7d48530 4771 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4772 {
219b747a
MF		 4773 int legal = 1;
4774 int len;
4775
086134ec 4776 parallel = 1;
f5caf9f4 4777 OUTS (outf, " || ");
219b747a 4778 len = _print_insn_bfin (pc + 4, outf);
f5caf9f4 4779 OUTS (outf, " || ");
219b747a 4780 if (len != 2)
602427c4 4781 legal = 0;
219b747a
MF		 4782 len = _print_insn_bfin (pc + 6, outf);
4783 if (len != 2)
4784 legal = 0;
4785
4786 if (legal)
4787 count = 8;
4788 else
4789 {
f5caf9f4 4790 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
219b747a
MF		 4791 comment = 1;
4792 count = 0;
4793 }
086134ec 4794 parallel = 0;
4b7f6baa 4795 }
219b747a 4796
086134ec 4797 if (!comment)
f5caf9f4 4798 OUTS (outf, ";");
086134ec 4799
219b747a
MF		 4800 if (count == 0)
4801 return 2;
4802
086134ec
BS		 4803 comment = 0;
4804
4b7f6baa
CM		 4805 return count;
4806}
GDB Binutils - Deliverables
This page took 0.995265 seconds and 4 git commands to generate.