[deliverable/binutils-gdb.git] / opcodes / d30v-dis.c

/* Disassemble D30V instructions.
   Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include <stdio.h>
#include "sysdep.h"
#include "opcode/d30v.h"
#include "dis-asm.h"
#include "opintl.h"

#define PC_MASK 0xFFFFFFFF

/* Return 0 if lookup fails,
   1 if found and only one form,
   2 if found and there are short and long forms.  */

static int
lookup_opcode (struct d30v_insn *insn, long num, int is_long)
{
  int i = 0, index;
  struct d30v_format *f;
  struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
  int op1 = (num >> 25) & 0x7;
  int op2 = (num >> 20) & 0x1f;
  int mod = (num >> 18) & 0x3;

  /* Find the opcode.  */
  do
    {
      if ((op->op1 == op1) && (op->op2 == op2))
	break;
      op++;
    }
  while (op->name);

  if (!op || !op->name)
    return 0;

  while (op->op1 == op1 && op->op2 == op2)
    {
      /* Scan through all the formats for the opcode.  */
      index = op->format[i++];
      do
	{
	  f = (struct d30v_format *) &d30v_format_table[index];
	  while (f->form == index)
	    {
	      if ((!is_long || f->form >= LONG) && (f->modifier == mod))
		{
		  insn->form = f;
		  break;
		}
	      f++;
	    }
	  if (insn->form)
	    break;
	}
      while ((index = op->format[i++]) != 0);
      if (insn->form)
	break;
      op++;
      i = 0;
    }
  if (insn->form == NULL)
    return 0;

  insn->op = op;
  insn->ecc = (num >> 28) & 0x7;
  if (op->format[1])
    return 2;
  else
    return 1;
}

static int
extract_value (long long num, struct d30v_operand *oper, int is_long)
{
  int val;
  int shift = 12 - oper->position;
  int mask = (0xFFFFFFFF >> (32 - oper->bits));

  if (is_long)
    {
      if (oper->bits == 32)
	/* Piece together 32-bit constant.  */
	val = ((num & 0x3FFFF)
	       | ((num & 0xFF00000) >> 2)
	       | ((num & 0x3F00000000LL) >> 6));
      else
	val = (num >> (32 + shift)) & mask;
    }
  else
    val = (num >> shift) & mask;

  if (oper->flags & OPERAND_SHIFT)
    val <<= 3;

  return val;
}

static void
print_insn (struct disassemble_info *info,
	    bfd_vma memaddr,
	    long long num,
	    struct d30v_insn *insn,
	    int is_long,
	    int show_ext)
{
  int val, opnum, need_comma = 0;
  struct d30v_operand *oper;
  int i, match, opind = 0, need_paren = 0, found_control = 0;

  (*info->fprintf_func) (info->stream, "%s", insn->op->name);

  /* Check for CMP or CMPU.  */
  if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
    {
      opind++;
      val =
	extract_value (num,
		       (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
		       is_long);
      (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
    }

  /* Add in ".s" or ".l".  */
  if (show_ext == 2)
    {
      if (is_long)
	(*info->fprintf_func) (info->stream, ".l");
      else
	(*info->fprintf_func) (info->stream, ".s");
    }

  if (insn->ecc)
    (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);

  (*info->fprintf_func) (info->stream, "\t");

  while ((opnum = insn->form->operands[opind++]) != 0)
    {
      int bits;

      oper = (struct d30v_operand *) &d30v_operand_table[opnum];
      bits = oper->bits;
      if (oper->flags & OPERAND_SHIFT)
	bits += 3;

      if (need_comma
	  && oper->flags != OPERAND_PLUS
	  && oper->flags != OPERAND_MINUS)
	{
	  need_comma = 0;
	  (*info->fprintf_func) (info->stream, ", ");
	}

      if (oper->flags == OPERAND_ATMINUS)
	{
	  (*info->fprintf_func) (info->stream, "@-");
	  continue;
	}
      if (oper->flags == OPERAND_MINUS)
	{
	  (*info->fprintf_func) (info->stream, "-");
	  continue;
	}
      if (oper->flags == OPERAND_PLUS)
	{
	  (*info->fprintf_func) (info->stream, "+");
	  continue;
	}
      if (oper->flags == OPERAND_ATSIGN)
	{
	  (*info->fprintf_func) (info->stream, "@");
	  continue;
	}
      if (oper->flags == OPERAND_ATPAR)
	{
	  (*info->fprintf_func) (info->stream, "@(");
	  need_paren = 1;
	  continue;
	}

      if (oper->flags == OPERAND_SPECIAL)
	continue;

      val = extract_value (num, oper, is_long);

      if (oper->flags & OPERAND_REG)
	{
	  match = 0;
	  if (oper->flags & OPERAND_CONTROL)
	    {
	      struct d30v_operand *oper3 =
		(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	      int id = extract_value (num, oper3, is_long);

	      found_control = 1;
	      switch (id)
		{
		case 0:
		  val |= OPERAND_CONTROL;
		  break;
		case 1:
		case 2:
		  val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
		  break;
		case 3:
		  val |= OPERAND_FLAG;
		  break;
		default:
		  fprintf (stderr, "illegal id (%d)\n", id);
		}
	    }
	  else if (oper->flags & OPERAND_ACC)
	    val |= OPERAND_ACC;
	  else if (oper->flags & OPERAND_FLAG)
	    val |= OPERAND_FLAG;
	  for (i = 0; i < reg_name_cnt (); i++)
	    {
	      if (val == pre_defined_registers[i].value)
		{
		  if (pre_defined_registers[i].pname)
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].pname);
		  else
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].name);
		  match = 1;
		  break;
		}
	    }
	  if (match == 0)
	    {
	      /* This would only get executed if a register was not in
		 the register table.  */
	      (*info->fprintf_func)
		(info->stream, _("<unknown register %d>"), val & 0x3F);
	    }
	}
      /* repeati has a relocation, but its first argument is a plain
	 immediate.  OTOH instructions like djsri have a pc-relative
	 delay target, but an absolute jump target.  Therefore, a test
	 of insn->op->reloc_flag is not specific enough; we must test
	 if the actual operand we are handling now is pc-relative.  */
      else if (oper->flags & OPERAND_PCREL)
	{
	  int neg = 0;

	  /* IMM6S3 is unsigned.  */
	  if (oper->flags & OPERAND_SIGNED || bits == 32)
	    {
	      long max;
	      max = (1 << (bits - 1));
	      if (val & max)
		{
		  if (bits == 32)
		    val = -val;
		  else
		    val = -val & ((1 << bits) - 1);
		  neg = 1;
		}
	    }
	  if (neg)
	    {
	      (*info->fprintf_func) (info->stream, "-%x\t(", val);
	      (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	  else
	    {
	      (*info->fprintf_func) (info->stream, "%x\t(", val);
	      (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	}
      else if (insn->op->reloc_flag == RELOC_ABS)
	{
	  (*info->print_address_func) (val, info);
	}
      else
	{
	  if (oper->flags & OPERAND_SIGNED)
	    {
	      int max = (1 << (bits - 1));

	      if (val & max)
		{
		  val = -val;
		  if (bits < 32)
		    val &= ((1 << bits) - 1);
		  (*info->fprintf_func) (info->stream, "-");
		}
	    }
	  (*info->fprintf_func) (info->stream, "0x%x", val);
	}
      /* If there is another operand, then write a comma and space.  */
      if (insn->form->operands[opind] && !(found_control && opind == 2))
	need_comma = 1;
    }
  if (need_paren)
    (*info->fprintf_func) (info->stream, ")");
}

int
print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
{
  int status, result;
  bfd_byte buffer[12];
  unsigned long in1, in2;
  struct d30v_insn insn;
  long long num;

  insn.form = NULL;

  info->bytes_per_line = 8;
  info->bytes_per_chunk = 4;
  info->display_endian = BFD_ENDIAN_BIG;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  in1 = bfd_getb32 (buffer);

  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
  if (status != 0)
    {
      info->bytes_per_line = 8;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
      return 4;
    }
  in2 = bfd_getb32 (buffer);

  if (in1 & in2 & FM01)
    {
      /* LONG instruction.  */
      if (!(result = lookup_opcode (&insn, in1, 1)))
	{
	  (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
	  return 8;
	}
      num = (long long) in1 << 32 | in2;
      print_insn (info, memaddr, num, &insn, 1, result);
    }
  else
    {
      num = in1;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, num, &insn, 0, result);

      switch (((in1 >> 31) << 1) | (in2 >> 31))
	{
	case 0:
	  (*info->fprintf_func) (info->stream, "\t||\t");
	  break;
	case 1:
	  (*info->fprintf_func) (info->stream, "\t->\t");
	  break;
	case 2:
	  (*info->fprintf_func) (info->stream, "\t<-\t");
	default:
	  break;
	}

      insn.form = NULL;
      num = in2;
      if (!(result = lookup_opcode (&insn, in2, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
      else
	print_insn (info, memaddr, num, &insn, 0, result);
    }
  return 8;
}
Commit	Line	Data
252b5132	1	/* Disassemble D30V instructions.
47b0e7ad	2	Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
252b5132	3
47b0e7ad NC	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
252b5132	8
47b0e7ad NC	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
252b5132	13
47b0e7ad NC	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	17	MA 02110-1301, USA. */
252b5132 RH	18
252b5132 RH	19	#include <stdio.h>
0d8dfecf	20	#include "sysdep.h"
2dcee538	21	#include "opcode/d30v.h"
252b5132 RH	22	#include "dis-asm.h"
	23	#include "opintl.h"
	24
	25	#define PC_MASK 0xFFFFFFFF
	26
2dcee538 KH	27	/* Return 0 if lookup fails,
	28	1 if found and only one form,
	29	2 if found and there are short and long forms. */
252b5132	30
252b5132	31	static int
47b0e7ad	32	lookup_opcode (struct d30v_insn *insn, long num, int is_long)
252b5132	33	{
2dcee538	34	int i = 0, index;
252b5132	35	struct d30v_format *f;
2dcee538	36	struct d30v_opcode op = (struct d30v_opcode ) d30v_opcode_table;
252b5132 RH	37	int op1 = (num >> 25) & 0x7;
	38	int op2 = (num >> 20) & 0x1f;
	39	int mod = (num >> 18) & 0x3;
	40
2dcee538 KH	41	/* Find the opcode. */
	42	do
	43	{
	44	if ((op->op1 == op1) && (op->op2 == op2))
	45	break;
	46	op++;
	47	}
	48	while (op->name);
252b5132 RH	49
	50	if (!op \|\| !op->name)
	51	return 0;
	52
	53	while (op->op1 == op1 && op->op2 == op2)
	54	{
2dcee538	55	/* Scan through all the formats for the opcode. */
252b5132	56	index = op->format[i++];
2dcee538	57	do
252b5132	58	{
2dcee538	59	f = (struct d30v_format *) &d30v_format_table[index];
252b5132 RH	60	while (f->form == index)
	61	{
	62	if ((!is_long \|\| f->form >= LONG) && (f->modifier == mod))
	63	{
	64	insn->form = f;
	65	break;
	66	}
	67	f++;
	68	}
	69	if (insn->form)
	70	break;
2dcee538 KH	71	}
2dcee538 KH	72	while ((index = op->format[i++]) != 0);
252b5132 RH	73	if (insn->form)
	74	break;
	75	op++;
2dcee538	76	i = 0;
252b5132 RH	77	}
	78	if (insn->form == NULL)
	79	return 0;
	80
	81	insn->op = op;
	82	insn->ecc = (num >> 28) & 0x7;
	83	if (op->format[1])
	84	return 2;
	85	else
	86	return 1;
	87	}
	88
47b0e7ad NC	89	static int
	90	extract_value (long long num, struct d30v_operand *oper, int is_long)
	91	{
	92	int val;
	93	int shift = 12 - oper->position;
	94	int mask = (0xFFFFFFFF >> (32 - oper->bits));
	95
	96	if (is_long)
	97	{
	98	if (oper->bits == 32)
	99	/* Piece together 32-bit constant. */
	100	val = ((num & 0x3FFFF)
	101	\| ((num & 0xFF00000) >> 2)
	102	\| ((num & 0x3F00000000LL) >> 6));
	103	else
	104	val = (num >> (32 + shift)) & mask;
	105	}
	106	else
	107	val = (num >> shift) & mask;
	108
	109	if (oper->flags & OPERAND_SHIFT)
	110	val <<= 3;
	111
	112	return val;
	113	}
	114
2dcee538	115	static void
47b0e7ad NC	116	print_insn (struct disassemble_info *info,
	117	bfd_vma memaddr,
	118	long long num,
	119	struct d30v_insn *insn,
	120	int is_long,
	121	int show_ext)
252b5132	122	{
2dcee538	123	int val, opnum, need_comma = 0;
252b5132	124	struct d30v_operand *oper;
2dcee538	125	int i, match, opind = 0, need_paren = 0, found_control = 0;
252b5132	126
2dcee538	127	(*info->fprintf_func) (info->stream, "%s", insn->op->name);
252b5132	128
2dcee538	129	/* Check for CMP or CMPU. */
252b5132 RH	130	if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
	131	{
	132	opind++;
2dcee538 KH	133	val =
	134	extract_value (num,
	135	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
	136	is_long);
	137	(*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
252b5132 RH	138	}
252b5132 RH	139
2dcee538	140	/* Add in ".s" or ".l". */
252b5132 RH	141	if (show_ext == 2)
	142	{
	143	if (is_long)
	144	(*info->fprintf_func) (info->stream, ".l");
	145	else
	146	(*info->fprintf_func) (info->stream, ".s");
	147	}
	148
	149	if (insn->ecc)
2dcee538	150	(*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);
252b5132 RH	151
	152	(*info->fprintf_func) (info->stream, "\t");
	153
	154	while ((opnum = insn->form->operands[opind++]) != 0)
	155	{
	156	int bits;
47b0e7ad	157
2dcee538	158	oper = (struct d30v_operand *) &d30v_operand_table[opnum];
252b5132 RH	159	bits = oper->bits;
	160	if (oper->flags & OPERAND_SHIFT)
	161	bits += 3;
	162
2dcee538 KH	163	if (need_comma
	164	&& oper->flags != OPERAND_PLUS
	165	&& oper->flags != OPERAND_MINUS)
252b5132	166	{
2dcee538	167	need_comma = 0;
252b5132 RH	168	(*info->fprintf_func) (info->stream, ", ");
	169	}
	170
	171	if (oper->flags == OPERAND_ATMINUS)
	172	{
	173	(*info->fprintf_func) (info->stream, "@-");
	174	continue;
	175	}
	176	if (oper->flags == OPERAND_MINUS)
	177	{
2dcee538	178	(*info->fprintf_func) (info->stream, "-");
252b5132 RH	179	continue;
	180	}
	181	if (oper->flags == OPERAND_PLUS)
	182	{
2dcee538	183	(*info->fprintf_func) (info->stream, "+");
252b5132 RH	184	continue;
	185	}
	186	if (oper->flags == OPERAND_ATSIGN)
	187	{
2dcee538	188	(*info->fprintf_func) (info->stream, "@");
252b5132 RH	189	continue;
	190	}
	191	if (oper->flags == OPERAND_ATPAR)
	192	{
2dcee538	193	(*info->fprintf_func) (info->stream, "@(");
252b5132 RH	194	need_paren = 1;
	195	continue;
	196	}
	197
	198	if (oper->flags == OPERAND_SPECIAL)
	199	continue;
	200
2dcee538 KH	201	val = extract_value (num, oper, is_long);
2dcee538 KH	202
252b5132 RH	203	if (oper->flags & OPERAND_REG)
	204	{
	205	match = 0;
	206	if (oper->flags & OPERAND_CONTROL)
	207	{
2dcee538 KH	208	struct d30v_operand *oper3 =
	209	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	210	int id = extract_value (num, oper3, is_long);
47b0e7ad	211
252b5132	212	found_control = 1;
2dcee538	213	switch (id)
252b5132 RH	214	{
	215	case 0:
	216	val \|= OPERAND_CONTROL;
	217	break;
	218	case 1:
	219	case 2:
	220	val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
	221	break;
	222	case 3:
	223	val \|= OPERAND_FLAG;
	224	break;
	225	default:
2dcee538	226	fprintf (stderr, "illegal id (%d)\n", id);
252b5132 RH	227	}
	228	}
	229	else if (oper->flags & OPERAND_ACC)
	230	val \|= OPERAND_ACC;
	231	else if (oper->flags & OPERAND_FLAG)
	232	val \|= OPERAND_FLAG;
2dcee538	233	for (i = 0; i < reg_name_cnt (); i++)
252b5132 RH	234	{
	235	if (val == pre_defined_registers[i].value)
	236	{
	237	if (pre_defined_registers[i].pname)
	238	(*info->fprintf_func)
2dcee538	239	(info->stream, "%s", pre_defined_registers[i].pname);
252b5132 RH	240	else
252b5132 RH	241	(*info->fprintf_func)
2dcee538 KH	242	(info->stream, "%s", pre_defined_registers[i].name);
2dcee538 KH	243	match = 1;
252b5132 RH	244	break;
	245	}
	246	}
2dcee538	247	if (match == 0)
252b5132	248	{
2dcee538 KH	249	/* This would only get executed if a register was not in
2dcee538 KH	250	the register table. */
252b5132	251	(*info->fprintf_func)
2dcee538	252	(info->stream, _("<unknown register %d>"), val & 0x3F);
252b5132 RH	253	}
252b5132 RH	254	}
866afedc NC	255	/* repeati has a relocation, but its first argument is a plain
866afedc NC	256	immediate. OTOH instructions like djsri have a pc-relative
d9a35582	257	delay target, but an absolute jump target. Therefore, a test
866afedc NC	258	of insn->op->reloc_flag is not specific enough; we must test
	259	if the actual operand we are handling now is pc-relative. */
	260	else if (oper->flags & OPERAND_PCREL)
252b5132	261	{
866afedc	262	int neg = 0;
2dcee538	263
866afedc NC	264	/* IMM6S3 is unsigned. */
866afedc NC	265	if (oper->flags & OPERAND_SIGNED \|\| bits == 32)
252b5132	266	{
866afedc NC	267	long max;
	268	max = (1 << (bits - 1));
	269	if (val & max)
	270	{
	271	if (bits == 32)
	272	val = -val;
	273	else
2dcee538	274	val = -val & ((1 << bits) - 1);
866afedc NC	275	neg = 1;
	276	}
	277	}
	278	if (neg)
	279	{
2dcee538	280	(*info->fprintf_func) (info->stream, "-%x\t(", val);
866afedc NC	281	(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
866afedc NC	282	(*info->fprintf_func) (info->stream, ")");
252b5132	283	}
866afedc	284	else
252b5132	285	{
2dcee538	286	(*info->fprintf_func) (info->stream, "%x\t(", val);
866afedc NC	287	(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
866afedc NC	288	(*info->fprintf_func) (info->stream, ")");
252b5132	289	}
252b5132 RH	290	}
	291	else if (insn->op->reloc_flag == RELOC_ABS)
	292	{
	293	(*info->print_address_func) (val, info);
	294	}
	295	else
	296	{
	297	if (oper->flags & OPERAND_SIGNED)
	298	{
	299	int max = (1 << (bits - 1));
47b0e7ad	300
252b5132 RH	301	if (val & max)
	302	{
	303	val = -val;
	304	if (bits < 32)
	305	val &= ((1 << bits) - 1);
	306	(*info->fprintf_func) (info->stream, "-");
	307	}
	308	}
2dcee538	309	(*info->fprintf_func) (info->stream, "0x%x", val);
252b5132	310	}
2dcee538	311	/* If there is another operand, then write a comma and space. */
252b5132 RH	312	if (insn->form->operands[opind] && !(found_control && opind == 2))
	313	need_comma = 1;
	314	}
	315	if (need_paren)
	316	(*info->fprintf_func) (info->stream, ")");
	317	}
	318
47b0e7ad NC	319	int
47b0e7ad NC	320	print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
252b5132	321	{
47b0e7ad NC	322	int status, result;
	323	bfd_byte buffer[12];
	324	unsigned long in1, in2;
	325	struct d30v_insn insn;
	326	long long num;
252b5132	327
47b0e7ad NC	328	insn.form = NULL;
	329
	330	info->bytes_per_line = 8;
	331	info->bytes_per_chunk = 4;
	332	info->display_endian = BFD_ENDIAN_BIG;
	333
	334	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	335	if (status != 0)
252b5132	336	{
47b0e7ad NC	337	(*info->memory_error_func) (status, memaddr, info);
	338	return -1;
	339	}
	340	in1 = bfd_getb32 (buffer);
	341
	342	status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
	343	if (status != 0)
	344	{
	345	info->bytes_per_line = 8;
	346	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	347	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	348	else
	349	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
	350	return 4;
	351	}
	352	in2 = bfd_getb32 (buffer);
	353
	354	if (in1 & in2 & FM01)
	355	{
	356	/* LONG instruction. */
	357	if (!(result = lookup_opcode (&insn, in1, 1)))
252b5132	358	{
0fd3a477	359	(*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
47b0e7ad	360	return 8;
252b5132	361	}
47b0e7ad NC	362	num = (long long) in1 << 32 \| in2;
47b0e7ad NC	363	print_insn (info, memaddr, num, &insn, 1, result);
252b5132 RH	364	}
252b5132 RH	365	else
47b0e7ad NC	366	{
	367	num = in1;
	368	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	369	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	370	else
47b0e7ad NC	371	print_insn (info, memaddr, num, &insn, 0, result);
252b5132	372
47b0e7ad NC	373	switch (((in1 >> 31) << 1) \| (in2 >> 31))
	374	{
	375	case 0:
	376	(*info->fprintf_func) (info->stream, "\t\|\|\t");
	377	break;
	378	case 1:
	379	(*info->fprintf_func) (info->stream, "\t->\t");
	380	break;
	381	case 2:
	382	(*info->fprintf_func) (info->stream, "\t<-\t");
	383	default:
	384	break;
	385	}
252b5132	386
47b0e7ad NC	387	insn.form = NULL;
	388	num = in2;
	389	if (!(result = lookup_opcode (&insn, in2, 0)))
0fd3a477	390	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
47b0e7ad NC	391	else
	392	print_insn (info, memaddr, num, &insn, 0, result);
	393	}
	394	return 8;
252b5132	395	}