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* configure.in: check whether host and target makefile
[deliverable/binutils-gdb.git] / opcodes / d30v-opc.c
CommitLineData
b2e3f844
MH		 1/* d30v-opc.c -- D30V opcode list
2 Copyright 1997 Free Software Foundation, Inc.
3 Written by Martin Hunt, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <stdio.h>
22#include "ansidecl.h"
23#include "opcode/d30v.h"
24
25
26/* This table is sorted. */
27/* If you add anything, it MUST be in alphabetical order */
28/* The first field is the name the assembler uses when looking */
29/* up orcodes. The second field is the name the disassembler will use. */
30/* This allows the assembler to assemble references to r63 (for example) */
31/* or "sp". The disassembler will always use the preferred form (sp) */
32const struct pd_reg pre_defined_registers[] =
33{
34 { "a0", NULL, OPERAND_ACC+0 },
35 { "a1", NULL, OPERAND_ACC+1 },
d51bcb70
KR		 36 { "bpc", NULL, OPERAND_CONTROL+3 },
37 { "bpsw", NULL, OPERAND_CONTROL+1 },
b2e3f844 38 { "c", "c", OPERAND_FLAG+7 },
d51bcb70
KR		 39 { "cr0", "psw", OPERAND_CONTROL },
40 { "cr1", "bpsw", OPERAND_CONTROL+1 },
41 { "cr10", "mod_s", OPERAND_CONTROL+10 },
42 { "cr11", "mod_e", OPERAND_CONTROL+11 },
b2e3f844
MH		 43 { "cr12", NULL, OPERAND_CONTROL+12 },
44 { "cr13", NULL, OPERAND_CONTROL+13 },
d51bcb70 45 { "cr14", "iba", OPERAND_CONTROL+14 },
b2e3f844 46 { "cr15", NULL, OPERAND_CONTROL+15 },
d51bcb70
KR		 47 { "cr16", NULL, OPERAND_CONTROL+16 },
48 { "cr17", NULL, OPERAND_CONTROL+17 },
49 { "cr18", NULL, OPERAND_CONTROL+18 },
50 { "cr19", NULL, OPERAND_CONTROL+19 },
51 { "cr2", "pc", OPERAND_CONTROL+2 },
52 { "cr20", NULL, OPERAND_CONTROL+20 },
53 { "cr21", NULL, OPERAND_CONTROL+21 },
54 { "cr22", NULL, OPERAND_CONTROL+22 },
55 { "cr23", NULL, OPERAND_CONTROL+23 },
56 { "cr24", NULL, OPERAND_CONTROL+24 },
57 { "cr25", NULL, OPERAND_CONTROL+25 },
58 { "cr26", NULL, OPERAND_CONTROL+26 },
59 { "cr27", NULL, OPERAND_CONTROL+27 },
60 { "cr28", NULL, OPERAND_CONTROL+28 },
61 { "cr29", NULL, OPERAND_CONTROL+29 },
62 { "cr3", "bpc", OPERAND_CONTROL+3 },
63 { "cr30", NULL, OPERAND_CONTROL+30 },
64 { "cr31", NULL, OPERAND_CONTROL+31 },
65 { "cr32", NULL, OPERAND_CONTROL+32 },
66 { "cr33", NULL, OPERAND_CONTROL+33 },
67 { "cr34", NULL, OPERAND_CONTROL+34 },
68 { "cr35", NULL, OPERAND_CONTROL+35 },
69 { "cr36", NULL, OPERAND_CONTROL+36 },
70 { "cr37", NULL, OPERAND_CONTROL+37 },
71 { "cr38", NULL, OPERAND_CONTROL+38 },
72 { "cr39", NULL, OPERAND_CONTROL+39 },
73 { "cr4", "dpsw", OPERAND_CONTROL+4 },
74 { "cr40", NULL, OPERAND_CONTROL+40 },
75 { "cr41", NULL, OPERAND_CONTROL+41 },
76 { "cr42", NULL, OPERAND_CONTROL+42 },
77 { "cr43", NULL, OPERAND_CONTROL+43 },
78 { "cr44", NULL, OPERAND_CONTROL+44 },
79 { "cr45", NULL, OPERAND_CONTROL+45 },
80 { "cr46", NULL, OPERAND_CONTROL+46 },
81 { "cr47", NULL, OPERAND_CONTROL+47 },
82 { "cr48", NULL, OPERAND_CONTROL+48 },
83 { "cr49", NULL, OPERAND_CONTROL+49 },
84 { "cr5","dpc", OPERAND_CONTROL+5 },
85 { "cr50", NULL, OPERAND_CONTROL+50 },
86 { "cr51", NULL, OPERAND_CONTROL+51 },
87 { "cr52", NULL, OPERAND_CONTROL+52 },
88 { "cr53", NULL, OPERAND_CONTROL+53 },
89 { "cr54", NULL, OPERAND_CONTROL+54 },
90 { "cr55", NULL, OPERAND_CONTROL+55 },
91 { "cr56", NULL, OPERAND_CONTROL+56 },
92 { "cr57", NULL, OPERAND_CONTROL+57 },
93 { "cr58", NULL, OPERAND_CONTROL+58 },
94 { "cr59", NULL, OPERAND_CONTROL+59 },
95 { "cr6", NULL, OPERAND_CONTROL+6 },
96 { "cr60", NULL, OPERAND_CONTROL+60 },
97 { "cr61", NULL, OPERAND_CONTROL+61 },
98 { "cr62", NULL, OPERAND_CONTROL+62 },
99 { "cr63", NULL, OPERAND_CONTROL+63 },
100 { "cr7", "rpt_c", OPERAND_CONTROL+7 },
101 { "cr8", "rpt_s", OPERAND_CONTROL+8 },
102 { "cr9", "rpt_e", OPERAND_CONTROL+9 },
103 { "dpc", NULL, OPERAND_CONTROL+5 },
104 { "dpsw", NULL, OPERAND_CONTROL+4 },
b2e3f844
MH		 105 { "f0", NULL, OPERAND_FLAG+0 },
106 { "f1", NULL, OPERAND_FLAG+1 },
107 { "f2", NULL, OPERAND_FLAG+2 },
108 { "f3", NULL, OPERAND_FLAG+3 },
109 { "f4", "s", OPERAND_FLAG+4 },
110 { "f5", "v", OPERAND_FLAG+5 },
111 { "f6", "va", OPERAND_FLAG+6 },
112 { "f7", "c", OPERAND_FLAG+7 },
d51bcb70 113 { "iba", NULL, OPERAND_CONTROL+14 },
b2e3f844 114 { "link", "r62", 62 },
d51bcb70
KR		 115 { "mod_e", NULL, OPERAND_CONTROL+11 },
116 { "mod_s", NULL, OPERAND_CONTROL+10 },
117 { "pc", NULL, OPERAND_CONTROL+2 },
118 { "psw", NULL, OPERAND_CONTROL },
b2e3f844
MH		 119 { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
120 { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
121 { "r0", "0", 0 },
122 { "r1", NULL, 1 },
123 { "r10", NULL, 10 },
124 { "r11", NULL, 11 },
125 { "r12", NULL, 12 },
126 { "r13", NULL, 13 },
127 { "r14", NULL, 14 },
128 { "r15", NULL, 15 },
129 { "r16", NULL, 16 },
130 { "r17", NULL, 17 },
131 { "r18", NULL, 18 },
132 { "r19", NULL, 19 },
133 { "r2", NULL, 2 },
134 { "r20", NULL, 20 },
135 { "r21", NULL, 21 },
136 { "r22", NULL, 22 },
137 { "r23", NULL, 23 },
138 { "r24", NULL, 24 },
139 { "r25", NULL, 25 },
140 { "r26", NULL, 26 },
141 { "r27", NULL, 27 },
142 { "r28", NULL, 28 },
143 { "r29", NULL, 29 },
144 { "r3", NULL, 3 },
145 { "r30", NULL, 30 },
146 { "r31", NULL, 31 },
147 { "r32", NULL, 32 },
148 { "r33", NULL, 33 },
149 { "r34", NULL, 34 },
150 { "r35", NULL, 35 },
151 { "r36", NULL, 36 },
152 { "r37", NULL, 37 },
153 { "r38", NULL, 38 },
154 { "r39", NULL, 39 },
155 { "r4", NULL, 4 },
156 { "r40", NULL, 40 },
157 { "r41", NULL, 41 },
158 { "r42", NULL, 42 },
159 { "r43", NULL, 43 },
160 { "r44", NULL, 44 },
161 { "r45", NULL, 45 },
162 { "r46", NULL, 46 },
163 { "r47", NULL, 47 },
164 { "r48", NULL, 48 },
165 { "r49", NULL, 49 },
166 { "r5", NULL, 5 },
167 { "r50", NULL, 50 },
168 { "r51", NULL, 51 },
169 { "r52", NULL, 52 },
170 { "r53", NULL, 53 },
171 { "r54", NULL, 54 },
172 { "r55", NULL, 55 },
173 { "r56", NULL, 56 },
174 { "r57", NULL, 57 },
175 { "r58", NULL, 58 },
176 { "r59", NULL, 59 },
177 { "r6", NULL, 6 },
178 { "r60", NULL, 60 },
179 { "r61", NULL, 61 },
180 { "r62", "link", 62 },
181 { "r63", "sp", 63 },
182 { "r7", NULL, 7 },
183 { "r8", NULL, 8 },
184 { "r9", NULL, 9 },
d51bcb70
KR		 185 { "rpt_c", NULL, OPERAND_CONTROL+7 },
186 { "rpt_e", NULL, OPERAND_CONTROL+9 },
187 { "rpt_s", NULL, OPERAND_CONTROL+8 },
b2e3f844
MH		 188 { "s", NULL, OPERAND_FLAG+4 },
189 { "sp", NULL, 63 },
190 { "v", NULL, OPERAND_FLAG+5 },
191 { "va", NULL, OPERAND_FLAG+6 },
192};
193
194int
195reg_name_cnt()
196{
197 return (sizeof(pre_defined_registers) / sizeof(struct pd_reg));
198}
199
200/* OPCODE TABLE */
201/* The format of this table is defined in opcode/d30v.h */
202const struct d30v_opcode d30v_opcode_table[] = {
203 { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
204 { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
205 { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
206 { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
207 { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
208 { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
209 { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
210 { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
211 { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
212 { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
213 { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
214 { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
215 { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
216 { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
217 { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
d51bcb70 218 { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
b2e3f844
MH		 219 { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
220 { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
221 { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER, 0, 0, 0 },
222 { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER, 0, 0, 0 },
223 { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL },
224 { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL },
225 { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL },
226 { "bset", LOGIC, 0x2, { SHORT_A }, EITHER, 0, 0, 0 },
227 { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL },
228 { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL },
229 { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL },
d51bcb70
KR		 230 { "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, 0, 0 },
231 { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
232 { "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
b2e3f844
MH		 233 { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
234 { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL },
235 { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
236 { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL },
d51bcb70 237 { "dbt", BRA, 0xb, { SHORT_NONE }, MU, 0, 0, 0 },
b2e3f844
MH		 238 { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
239 { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS },
240 { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS },
241 { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS },
242 { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
243 { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
244 { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
245 { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
246 { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
247 { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
248 { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
249 { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
250 { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
251 { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
d51bcb70
KR		 252 { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
253 { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
254 { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
255 { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
b2e3f844
MH		 256 { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
257 { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
258 { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
259 { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
260 { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
261 { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
262 { "mac0", IALU2, 0x14, { SHORT_A }, IU, 0, 0, 0 },
263 { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, 0, 0, 0 },
264 { "macs0", IALU2, 0x15, { SHORT_A }, IU, 0, 0, 0 },
265 { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, 0, 0, 0 },
266 { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
267 { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
268 { "msub0", IALU2, 0x16, { SHORT_A }, IU, 0, 0, 0 },
269 { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, 0, 0, 0 },
270 { "msubs0", IALU2, 0x17, { SHORT_A }, IU, 0, 0, 0 },
271 { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, 0, 0, 0 },
272 { "mul", IALU2, 0x10, { SHORT_A }, IU, 0, 0, 0 },
273 { "mul2h", IALU2, 0, { SHORT_A }, IU, 0, 0, 0 },
274 { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, 0, 0, 0 },
275 { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, 0, 0, 0 },
276 { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, 0, 0, 0 },
277 { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, 0, 0, 0 },
278 { "mulx", IALU2, 0x18, { SHORT_AA }, IU, 0, 0, 0 },
d51bcb70 279 { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, 0, 0, 0 },
b2e3f844
MH		 280 { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, 0, 0, 0 },
281 { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
282 { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
283 { "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 },
284 { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
285 { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
286 { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
d51bcb70 287 { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
b2e3f844 288 { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
d51bcb70 289 { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
b2e3f844
MH		 290 { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM, 0 },
291 { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, 0 },
d51bcb70 292 { "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, 0 },
b2e3f844 293 { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
d51bcb70
KR		 294 { "rot2h", LOGIC, 0x15, { SHORT_A5S }, EITHER, 0, 0, 0 },
295 { "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, 0, 0 },
296 { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
297 { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
298 { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, 0, 0, 0 },
299 { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, 0, 0, 0 },
300 { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
301 { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
b2e3f844 302 { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
d51bcb70
KR		 303 { "sra2h", LOGIC, 0x11, { SHORT_A5S }, EITHER, 0, 0, 0 },
304 { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
305 { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
b2e3f844
MH		 306 { "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 },
307 { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
d51bcb70
KR		 308 { "srl2h", LOGIC, 0x13, { SHORT_A5S }, EITHER, 0, 0, 0 },
309 { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
310 { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
311 { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
312 { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
313 { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 },
b2e3f844
MH		 314 { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
315 { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
316 { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
317 { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 },
318 { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
319 { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
320 { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
321 { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
322 { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
323 { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
324 { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
325 { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
326 { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
327 { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
328 { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
329 { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM, 0 },
330 { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
d51bcb70 331 { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
b2e3f844
MH		 332 { NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
333};
334
335
336/* now define the operand types */
337/* format is length, bits, position, flags */
338const struct d30v_operand d30v_operand_table[] =
339{
340#define UNUSED (0)
341 { 0, 0, 0, 0 },
342#define Ra (UNUSED + 1)
343 { 6, 6, 0, OPERAND_REG|OPERAND_DEST },
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KR		 344#define Ra2 (Ra + 1)
345 { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG },
346#define Rb (Ra2 + 1)
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MH		 347 { 6, 6, 6, OPERAND_REG },
348#define Rc (Rb + 1)
349 { 6, 6, 12, OPERAND_REG },
350#define Aa (Rc + 1)
351 { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
352#define Ab (Aa + 1)
353 { 6, 1, 6, OPERAND_ACC|OPERAND_REG },
354#define IMM5 (Ab + 1)
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KR		 355 { 6, 5, 12, OPERAND_NUM },
356#define IMM5U (IMM5 + 1)
b2e3f844 357 { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
d51bcb70 358#define IMM5S3 (IMM5U + 1)
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MH		 359 { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
360#define IMM6 (IMM5S3 + 1)
361 { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
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KR		 362#define IMM6U (IMM6 + 1)
363 { 6, 6, 0, OPERAND_NUM },
364#define IMM6U2 (IMM6U + 1)
365 { 6, 6, 12, OPERAND_NUM },
366#define IMM6S3 (IMM6U2 + 1)
367 { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT },
368#define IMM12S3 (IMM6S3 + 1)
369 { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
370#define IMM12S3U (IMM12S3 + 1)
371 { 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT },
372#define IMM18S3 (IMM12S3U + 1)
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MH		 373 { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
374#define IMM32 (IMM18S3 + 1)
375 { 32, 32, 0, OPERAND_NUM },
376#define Fa (IMM32 + 1)
377 { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
378#define Fb (Fa + 1)
379 { 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
380#define Fc (Fb + 1)
381 { 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
382#define ATSIGN (Fc + 1)
383 { 0, 0, 0, OPERAND_ATSIGN},
384#define ATPAR (ATSIGN + 1) /* "@(" */
385 { 0, 0, 0, OPERAND_ATPAR},
386#define PLUS (ATPAR + 1) /* postincrement */
387 { 0, 0, 0, OPERAND_PLUS},
388#define MINUS (PLUS + 1) /* postdecrement */
389 { 0, 0, 0, OPERAND_MINUS},
390#define ATMINUS (MINUS + 1) /* predecrement */
391 { 0, 0, 0, OPERAND_ATMINUS},
392#define Ca (ATMINUS + 1) /* control register */
d51bcb70 393 { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
b2e3f844 394#define Cb (Ca + 1) /* control register */
d51bcb70 395 { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL},
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MH		 396#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */
397 { 3, 3, -3, OPERAND_NAME},
398#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */
399 { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST},
400#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */
401 { 6, 2, 12, OPERAND_SPECIAL},
402};
403
404/* now we need to define the instruction formats */
405const struct d30v_format d30v_format_table[] =
406{
407 { 0, 0, { 0 } },
408 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
409 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
410 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
411 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
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KR		 412 { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
413 { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
414 { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
415 { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
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MH		 416 { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
417 { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
418 { SHORT_B1, 0, { Rc } }, /* Rc */
419 { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
420 { SHORT_B3, 0, { Ra, Rc } }, /* Ra,Rc */
d51bcb70 421 { SHORT_B3, 2, { Ra, IMM12S3 } }, /* Ra,imm12 */
b2e3f844 422 { SHORT_B3b, 1, { Ra, Rc } }, /* Ra,Rc */
d51bcb70 423 { SHORT_B3b, 3, { Ra, IMM12S3 } }, /* Ra,imm12 */
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MH		 424 { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */
425 { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */
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KR		 426 { SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */
427 { SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */
428 { SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */
429 { SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */
b2e3f844 430 { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
d51bcb70 431 { SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */
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MH		 432 { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
433 { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
434 { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
435 { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */
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KR		 436 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
437 { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
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MH		 438 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
439 { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
440 { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */
441 { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */
442 { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */
443 { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
444 { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
445 { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
d51bcb70 446 { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */
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MH		 447 { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */
448 { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */
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KR		 449 { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
450 { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
b2e3f844 451 { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
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KR		 452 { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
453 { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
454 { SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
455 { SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */
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MH		 456 { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
457 { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
458 { LONG_U, 2, { IMM32 } }, /* imm32 */
459 { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */
460 { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
461 { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
d51bcb70 462 { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
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MH		 463 { LONG_2, 2, { Ra, IMM32 } }, /* Ra,imm32 */
464 { LONG_2b, 3, { Ra, IMM32 } }, /* Ra,imm32 */
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KR		 465 { LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */
466 { LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */
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MH		 467 { 0, 0, { 0 } },
468};
469
470const char *d30v_ecc_names[] =
471{
472 "al",
473 "tx",
474 "fx",
475 "xt",
476 "xf",
477 "tt",
478 "tf",
479 "res"
480};
481
482const char *d30v_cc_names[] =
483{
484 "eq",
485 "ne",
486 "gt",
487 "ge",
488 "lt",
489 "le",
490 "ps",
491 "ng",
492 NULL
493};
GDB Binutils - Deliverables
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