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[deliverable/binutils-gdb.git] / opcodes / d30v-opc.c
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252b5132 1/* d30v-opc.c -- D30V opcode list
df7b86aa
NC		 2 Copyright 1997, 1998, 1999, 2000, 2005, 2007, 2012
3 Free Software Foundation, Inc.
252b5132
RH		 4 Written by Martin Hunt, Cygnus Support
5
9b201bb5 6 This file is part of the GNU opcodes library.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
47b0e7ad
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
0d8dfecf 23#include "sysdep.h"
df7b86aa 24#include <stdio.h>
252b5132
RH		 25#include "opcode/d30v.h"
26
47b0e7ad
NC		 27/* This table is sorted.
28 If you add anything, it MUST be in alphabetical order.
29 The first field is the name the assembler uses when looking
30 up orcodes. The second field is the name the disassembler will use.
31 This allows the assembler to assemble references to r63 (for example)
32 or "sp". The disassembler will always use the preferred form (sp). */
252b5132
RH		 33const struct pd_reg pre_defined_registers[] =
34{
47b0e7ad
NC		 35 { "a0", NULL, OPERAND_ACC + 0 },
36 { "a1", NULL, OPERAND_ACC + 1 },
37 { "bpc", NULL, OPERAND_CONTROL + 3 },
38 { "bpsw", NULL, OPERAND_CONTROL + 1 },
39 { "c", "c", OPERAND_FLAG + 7 },
252b5132 40 { "cr0", "psw", OPERAND_CONTROL },
47b0e7ad
NC		 41 { "cr1", "bpsw", OPERAND_CONTROL + 1 },
42 { "cr10", "mod_s", OPERAND_CONTROL + 10 },
43 { "cr11", "mod_e", OPERAND_CONTROL + 11 },
44 { "cr12", NULL, OPERAND_CONTROL + 12 },
45 { "cr13", NULL, OPERAND_CONTROL + 13 },
46 { "cr14", "iba", OPERAND_CONTROL + 14 },
47 { "cr15", "eit_vb", OPERAND_CONTROL + 15 },
48 { "cr16", "int_s", OPERAND_CONTROL + 16 },
49 { "cr17", "int_m", OPERAND_CONTROL + 17 },
50 { "cr18", NULL, OPERAND_CONTROL + 18 },
51 { "cr19", NULL, OPERAND_CONTROL + 19 },
52 { "cr2", "pc", OPERAND_CONTROL + 2 },
53 { "cr20", NULL, OPERAND_CONTROL + 20 },
54 { "cr21", NULL, OPERAND_CONTROL + 21 },
55 { "cr22", NULL, OPERAND_CONTROL + 22 },
56 { "cr23", NULL, OPERAND_CONTROL + 23 },
57 { "cr24", NULL, OPERAND_CONTROL + 24 },
58 { "cr25", NULL, OPERAND_CONTROL + 25 },
59 { "cr26", NULL, OPERAND_CONTROL + 26 },
60 { "cr27", NULL, OPERAND_CONTROL + 27 },
61 { "cr28", NULL, OPERAND_CONTROL + 28 },
62 { "cr29", NULL, OPERAND_CONTROL + 29 },
63 { "cr3", "bpc", OPERAND_CONTROL + 3 },
64 { "cr30", NULL, OPERAND_CONTROL + 30 },
65 { "cr31", NULL, OPERAND_CONTROL + 31 },
66 { "cr32", NULL, OPERAND_CONTROL + 32 },
67 { "cr33", NULL, OPERAND_CONTROL + 33 },
68 { "cr34", NULL, OPERAND_CONTROL + 34 },
69 { "cr35", NULL, OPERAND_CONTROL + 35 },
70 { "cr36", NULL, OPERAND_CONTROL + 36 },
71 { "cr37", NULL, OPERAND_CONTROL + 37 },
72 { "cr38", NULL, OPERAND_CONTROL + 38 },
73 { "cr39", NULL, OPERAND_CONTROL + 39 },
74 { "cr4", "dpsw", OPERAND_CONTROL + 4 },
75 { "cr40", NULL, OPERAND_CONTROL + 40 },
76 { "cr41", NULL, OPERAND_CONTROL + 41 },
77 { "cr42", NULL, OPERAND_CONTROL + 42 },
78 { "cr43", NULL, OPERAND_CONTROL + 43 },
79 { "cr44", NULL, OPERAND_CONTROL + 44 },
80 { "cr45", NULL, OPERAND_CONTROL + 45 },
81 { "cr46", NULL, OPERAND_CONTROL + 46 },
82 { "cr47", NULL, OPERAND_CONTROL + 47 },
83 { "cr48", NULL, OPERAND_CONTROL + 48 },
84 { "cr49", NULL, OPERAND_CONTROL + 49 },
85 { "cr5","dpc", OPERAND_CONTROL + 5 },
86 { "cr50", NULL, OPERAND_CONTROL + 50 },
87 { "cr51", NULL, OPERAND_CONTROL + 51 },
88 { "cr52", NULL, OPERAND_CONTROL + 52 },
89 { "cr53", NULL, OPERAND_CONTROL + 53 },
90 { "cr54", NULL, OPERAND_CONTROL + 54 },
91 { "cr55", NULL, OPERAND_CONTROL + 55 },
92 { "cr56", NULL, OPERAND_CONTROL + 56 },
93 { "cr57", NULL, OPERAND_CONTROL + 57 },
94 { "cr58", NULL, OPERAND_CONTROL + 58 },
95 { "cr59", NULL, OPERAND_CONTROL + 59 },
96 { "cr6", NULL, OPERAND_CONTROL + 6 },
97 { "cr60", NULL, OPERAND_CONTROL + 60 },
98 { "cr61", NULL, OPERAND_CONTROL + 61 },
99 { "cr62", NULL, OPERAND_CONTROL + 62 },
100 { "cr63", NULL, OPERAND_CONTROL + 63 },
101 { "cr7", "rpt_c", OPERAND_CONTROL + 7 },
102 { "cr8", "rpt_s", OPERAND_CONTROL + 8 },
103 { "cr9", "rpt_e", OPERAND_CONTROL + 9 },
104 { "dpc", NULL, OPERAND_CONTROL + 5 },
105 { "dpsw", NULL, OPERAND_CONTROL + 4 },
106 { "eit_vb", NULL, OPERAND_CONTROL + 15 },
107 { "f0", NULL, OPERAND_FLAG + 0 },
108 { "f1", NULL, OPERAND_FLAG + 1 },
109 { "f2", NULL, OPERAND_FLAG + 2 },
110 { "f3", NULL, OPERAND_FLAG + 3 },
111 { "f4", "s", OPERAND_FLAG + 4 },
112 { "f5", "v", OPERAND_FLAG + 5 },
113 { "f6", "va", OPERAND_FLAG + 6 },
114 { "f7", "c", OPERAND_FLAG + 7 },
115 { "iba", NULL, OPERAND_CONTROL + 14 },
116 { "int_m", NULL, OPERAND_CONTROL + 17 },
117 { "int_s", NULL, OPERAND_CONTROL + 16 },
252b5132 118 { "link", "r62", 62 },
47b0e7ad
NC		 119 { "mod_e", NULL, OPERAND_CONTROL + 11 },
120 { "mod_s", NULL, OPERAND_CONTROL + 10 },
121 { "pc", NULL, OPERAND_CONTROL + 2 },
252b5132 122 { "psw", NULL, OPERAND_CONTROL },
47b0e7ad
NC		 123 { "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 },
124 { "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 },
252b5132
RH		 125 { "r0", NULL, 0 },
126 { "r1", NULL, 1 },
127 { "r10", NULL, 10 },
128 { "r11", NULL, 11 },
129 { "r12", NULL, 12 },
130 { "r13", NULL, 13 },
131 { "r14", NULL, 14 },
132 { "r15", NULL, 15 },
133 { "r16", NULL, 16 },
134 { "r17", NULL, 17 },
135 { "r18", NULL, 18 },
136 { "r19", NULL, 19 },
137 { "r2", NULL, 2 },
138 { "r20", NULL, 20 },
139 { "r21", NULL, 21 },
140 { "r22", NULL, 22 },
141 { "r23", NULL, 23 },
142 { "r24", NULL, 24 },
143 { "r25", NULL, 25 },
144 { "r26", NULL, 26 },
145 { "r27", NULL, 27 },
146 { "r28", NULL, 28 },
147 { "r29", NULL, 29 },
148 { "r3", NULL, 3 },
149 { "r30", NULL, 30 },
150 { "r31", NULL, 31 },
151 { "r32", NULL, 32 },
152 { "r33", NULL, 33 },
153 { "r34", NULL, 34 },
154 { "r35", NULL, 35 },
155 { "r36", NULL, 36 },
156 { "r37", NULL, 37 },
157 { "r38", NULL, 38 },
158 { "r39", NULL, 39 },
159 { "r4", NULL, 4 },
160 { "r40", NULL, 40 },
161 { "r41", NULL, 41 },
162 { "r42", NULL, 42 },
163 { "r43", NULL, 43 },
164 { "r44", NULL, 44 },
165 { "r45", NULL, 45 },
166 { "r46", NULL, 46 },
167 { "r47", NULL, 47 },
168 { "r48", NULL, 48 },
169 { "r49", NULL, 49 },
170 { "r5", NULL, 5 },
171 { "r50", NULL, 50 },
172 { "r51", NULL, 51 },
173 { "r52", NULL, 52 },
174 { "r53", NULL, 53 },
175 { "r54", NULL, 54 },
176 { "r55", NULL, 55 },
177 { "r56", NULL, 56 },
178 { "r57", NULL, 57 },
179 { "r58", NULL, 58 },
180 { "r59", NULL, 59 },
181 { "r6", NULL, 6 },
182 { "r60", NULL, 60 },
183 { "r61", NULL, 61 },
184 { "r62", "link", 62 },
185 { "r63", "sp", 63 },
186 { "r7", NULL, 7 },
187 { "r8", NULL, 8 },
188 { "r9", NULL, 9 },
47b0e7ad
NC		 189 { "rpt_c", NULL, OPERAND_CONTROL + 7 },
190 { "rpt_e", NULL, OPERAND_CONTROL + 9 },
191 { "rpt_s", NULL, OPERAND_CONTROL + 8 },
192 { "s", NULL, OPERAND_FLAG + 4 },
252b5132 193 { "sp", NULL, 63 },
47b0e7ad
NC		 194 { "v", NULL, OPERAND_FLAG + 5 },
195 { "va", NULL, OPERAND_FLAG + 6 },
252b5132
RH		 196};
197
198int
47b0e7ad 199reg_name_cnt (void)
252b5132 200{
47b0e7ad 201 return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
252b5132
RH		 202}
203
47b0e7ad
NC		 204/* OPCODE TABLE.
205 The format of this table is defined in opcode/d30v.h. */
206
207const struct d30v_opcode d30v_opcode_table[] =
208{
252b5132
RH		 209 { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
210 { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
211 { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
212 { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
213 { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
214 { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
215 { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
216 { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
217 { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
218 { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
219 { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
220 { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
221 { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
222 { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
223 { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
224 { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
225 { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
226 { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
227 { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
228 { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
866afedc
NC		 229 { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
230 { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
231 { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
252b5132 232 { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
866afedc
NC		 233 { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
234 { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
235 { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
252b5132
RH		 236 { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
237 { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
238 { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
866afedc
NC		 239 { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
240 { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
241 { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
242 { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
252b5132
RH		 243 { "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
244 { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
245 { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
246 { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
247 { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
248 { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
249 { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
250 { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
251 { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
252 { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
253 { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
254 { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
255 { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
256 { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
257 { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
258 { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
b669ceb9
CC		 259 { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
260 { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
252b5132
RH		 261 { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
262 { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
263 { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
264 { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
265 { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
266 { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
267 { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
268 { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
269 { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
270 { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
271 { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
272 { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
273 { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
274 { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
275 { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
276 { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
277 { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
278 { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
279 { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
280 { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
281 { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
282 { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
283 { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
284 { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
285 { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 },
286 { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
287 { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
288 { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
fd2a3b10 289 { "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 },
252b5132
RH		 290 { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
291 { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
292 { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
293 { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
294 { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
295 { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
296 { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
866afedc
NC		 297 { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
298 { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
252b5132
RH		 299 { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
300 { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
301 { "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
302 { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
303 { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
304 { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
305 { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
306 { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
307 { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
308 { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
309 { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
310 { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
311 { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
312 { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },
313 { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
314 { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
315 { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
316 { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
b669ceb9
CC		 317 { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
318 { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
319 { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
320 { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
321 { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
322 { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
323 { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
252b5132
RH		 324 { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
325 { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
326 { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
327 { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
328 { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
329 { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
330 { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
331 { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
332 { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
333 { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
334 { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
335 { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 },
336 { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
337 { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
338 { NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
339};
340
341
47b0e7ad
NC		 342/* Now define the operand types.
343 Format is length, bits, position, flags. */
344
252b5132
RH		 345const struct d30v_operand d30v_operand_table[] =
346{
347#define UNUSED (0)
348 { 0, 0, 0, 0 },
349#define Ra (UNUSED + 1)
47b0e7ad 350 { 6, 6, 0, OPERAND_REG | OPERAND_DEST },
252b5132 351#define Ra2 (Ra + 1)
47b0e7ad 352 { 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG },
252b5132
RH		 353#define Ra3 (Ra2 + 1)
354 { 6, 6, 0, OPERAND_REG },
355#define Rb (Ra3 + 1)
356 { 6, 6, 6, OPERAND_REG },
de827f51 357#define Rb2 (Rb + 1)
47b0e7ad 358 { 6, 6, 6, OPERAND_REG | OPERAND_DEST },
de827f51 359#define Rc (Rb2 + 1)
252b5132
RH		 360 { 6, 6, 12, OPERAND_REG },
361#define Aa (Rc + 1)
47b0e7ad 362 { 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST },
252b5132 363#define Ab (Aa + 1)
47b0e7ad 364 { 6, 1, 6, OPERAND_ACC | OPERAND_REG },
252b5132
RH		 365#define IMM5 (Ab + 1)
366 { 6, 5, 12, OPERAND_NUM },
866afedc 367#define IMM5U (IMM5 + 1)
47b0e7ad 368 { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
866afedc 369#define IMM5S3 (IMM5U + 1)
47b0e7ad 370 { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
866afedc 371#define IMM6 (IMM5S3 + 1)
47b0e7ad 372 { 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED },
866afedc 373#define IMM6U (IMM6 + 1)
252b5132 374 { 6, 6, 0, OPERAND_NUM },
866afedc 375#define IMM6U2 (IMM6U + 1)
252b5132 376 { 6, 6, 12, OPERAND_NUM },
866afedc 377#define REL6S3 (IMM6U2 + 1)
47b0e7ad 378 { 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL },
866afedc 379#define REL12S3 (REL6S3 + 1)
47b0e7ad 380 { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
866afedc 381#define IMM12S3 (REL12S3 + 1)
47b0e7ad 382 { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
866afedc 383#define REL18S3 (IMM12S3 + 1)
47b0e7ad 384 { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
866afedc 385#define IMM18S3 (REL18S3 + 1)
47b0e7ad 386 { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
866afedc 387#define REL32 (IMM18S3 + 1)
47b0e7ad 388 { 32, 32, 0, OPERAND_NUM | OPERAND_PCREL },
866afedc 389#define IMM32 (REL32 + 1)
252b5132
RH		 390 { 32, 32, 0, OPERAND_NUM },
391#define Fa (IMM32 + 1)
392 { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
393#define Fb (Fa + 1)
394 { 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
395#define Fc (Fb + 1)
396 { 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
397#define ATSIGN (Fc + 1)
398 { 0, 0, 0, OPERAND_ATSIGN},
399#define ATPAR (ATSIGN + 1) /* "@(" */
400 { 0, 0, 0, OPERAND_ATPAR},
47b0e7ad 401#define PLUS (ATPAR + 1) /* Postincrement. */
252b5132 402 { 0, 0, 0, OPERAND_PLUS},
47b0e7ad 403#define MINUS (PLUS + 1) /* Postdecrement. */
252b5132 404 { 0, 0, 0, OPERAND_MINUS},
47b0e7ad 405#define ATMINUS (MINUS + 1) /* Predecrement. */
252b5132 406 { 0, 0, 0, OPERAND_ATMINUS},
47b0e7ad
NC		 407#define Ca (ATMINUS + 1) /* Control register. */
408 { 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST},
409#define Cb (Ca + 1) /* Control register. */
410 { 6, 6, 6, OPERAND_REG | OPERAND_CONTROL},
411#define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */
252b5132 412 { 3, 3, -3, OPERAND_NAME},
47b0e7ad
NC		 413#define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */
414 { 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
415#define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */
252b5132
RH		 416 { 6, 2, 12, OPERAND_SPECIAL},
417};
418
47b0e7ad
NC		 419/* Now we need to define the instruction formats. */
420
252b5132
RH		 421const struct d30v_format d30v_format_table[] =
422{
423 { 0, 0, { 0 } },
424 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
425 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
426 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
427 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
428 { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
866afedc 429 { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
252b5132 430 { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
866afedc 431 { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
252b5132
RH		 432 { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
433 { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
434 { SHORT_B1, 0, { Rc } }, /* Rc */
435 { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
866afedc 436 { SHORT_B2r, 2, { REL18S3 } }, /* rel18 */
252b5132
RH		 437 { SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */
438 { SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */
866afedc
NC		 439 { SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */
440 { SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */
252b5132
RH		 441 { SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */
442 { SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */
866afedc
NC		 443 { SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */
444 { SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */
445 { SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */
446 { SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */
447 { SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
448 { SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */
449 { SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
450 { SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */
451 { SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */
452 { SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */
252b5132 453 { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
252b5132
RH		 454 { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
455 { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
456 { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
457 { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */
458 { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */
459 { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
460 { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */
461 { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
462 { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */
463 { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */
464 { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */
465 { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */
466 { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */
467 { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
468 { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */
469 { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */
470 { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */
de827f51
CM		 471 { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */
472 { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */
252b5132
RH		 473 { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */
474 { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */
475 { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
476 { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
477 { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
252b5132 478 { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
ba23e138 479 { SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
252b5132
RH		 480 { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
481 { LONG_U, 2, { IMM32 } }, /* imm32 */
866afedc 482 { LONG_Ur, 2, { REL32 } }, /* rel32 */
252b5132
RH		 483 { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
484 { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
485 { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
486 { LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */
866afedc 487 { LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */
252b5132 488 { LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */
866afedc
NC		 489 { LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */
490 { LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */
491 { LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */
492 { LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */
252b5132
RH		 493 { 0, 0, { 0 } },
494};
495
496const char *d30v_ecc_names[] =
497{
498 "al",
499 "tx",
500 "fx",
501 "xt",
502 "xf",
503 "tt",
504 "tf",
505 "res"
506};
507
508const char *d30v_cc_names[] =
509{
510 "eq",
511 "ne",
512 "gt",
513 "ge",
514 "lt",
515 "le",
516 "ps",
517 "ng",
518 NULL
519};
GDB Binutils - Deliverables
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