* gdb.texinfo (Commands In Python): Remove tindex entries.
[deliverable/binutils-gdb.git] / opcodes / disassemble.c
CommitLineData
252b5132 1/* Select disassembly routine for specified architecture.
aef6203b 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
9b201bb5 3 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5
NC
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
7499d566 8 it under the terms of the GNU General Public License as published by
9b201bb5 9 the Free Software Foundation; either version 3 of the License, or
7499d566 10 (at your option) any later version.
252b5132 11
7499d566
NC
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
252b5132 16
7499d566
NC
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
252b5132 21
0d8dfecf 22#include "sysdep.h"
252b5132
RH
23#include "dis-asm.h"
24
25#ifdef ARCH_all
252b5132
RH
26#define ARCH_alpha
27#define ARCH_arc
28#define ARCH_arm
adde6300 29#define ARCH_avr
4b7f6baa 30#define ARCH_bfin
3d3d428f 31#define ARCH_cr16
6c95a37f 32#define ARCH_cris
1fe1f39c 33#define ARCH_crx
252b5132
RH
34#define ARCH_d10v
35#define ARCH_d30v
d172d4ba 36#define ARCH_dlx
e729279b
NC
37#define ARCH_fr30
38#define ARCH_frv
252b5132
RH
39#define ARCH_h8300
40#define ARCH_h8500
41#define ARCH_hppa
5b93d8bb 42#define ARCH_i370
252b5132 43#define ARCH_i386
9d751335 44#define ARCH_i860
252b5132 45#define ARCH_i960
800eeca4 46#define ARCH_ia64
e729279b
NC
47#define ARCH_ip2k
48#define ARCH_iq2000
84e94c90 49#define ARCH_lm32
e729279b 50#define ARCH_m32c
252b5132 51#define ARCH_m32r
60bcf0fa
NC
52#define ARCH_m68hc11
53#define ARCH_m68hc12
e729279b 54#define ARCH_m68k
252b5132 55#define ARCH_m88k
7499d566 56#define ARCH_maxq
252b5132 57#define ARCH_mcore
bd2f2e55 58#define ARCH_mep
252b5132 59#define ARCH_mips
3c3bdf30 60#define ARCH_mmix
252b5132
RH
61#define ARCH_mn10200
62#define ARCH_mn10300
d031aafb 63#define ARCH_mt
2469cfa2 64#define ARCH_msp430
252b5132 65#define ARCH_ns32k
87e6d782 66#define ARCH_openrisc
3b16e843 67#define ARCH_or32
e135f41b 68#define ARCH_pdp11
1e608f98 69#define ARCH_pj
252b5132
RH
70#define ARCH_powerpc
71#define ARCH_rs6000
a85d7ed0 72#define ARCH_s390
1c0d3aa6 73#define ARCH_score
252b5132
RH
74#define ARCH_sh
75#define ARCH_sparc
e9f53129 76#define ARCH_spu
252b5132 77#define ARCH_tic30
026df7c5 78#define ARCH_tic4x
5c84d377 79#define ARCH_tic54x
252b5132
RH
80#define ARCH_tic80
81#define ARCH_v850
82#define ARCH_vax
83#define ARCH_w65
93fbbb04 84#define ARCH_xstormy16
d70c5fc7 85#define ARCH_xc16x
e0001a05 86#define ARCH_xtensa
3c9b82ba 87#define ARCH_z80
252b5132 88#define ARCH_z8k
d28847ce 89#define INCLUDE_SHMEDIA
252b5132
RH
90#endif
91
49f58d10
JB
92#ifdef ARCH_m32c
93#include "m32c-desc.h"
94#endif
252b5132
RH
95
96disassembler_ftype
97disassembler (abfd)
98 bfd *abfd;
99{
100 enum bfd_architecture a = bfd_get_arch (abfd);
101 disassembler_ftype disassemble;
102
103 switch (a)
104 {
105 /* If you add a case to this table, also add it to the
106 ARCH_all definition right above this function. */
252b5132
RH
107#ifdef ARCH_alpha
108 case bfd_arch_alpha:
109 disassemble = print_insn_alpha;
110 break;
111#endif
112#ifdef ARCH_arc
113 case bfd_arch_arc:
114 {
0d2bcfaf 115 disassemble = arc_get_disassembler (abfd);
252b5132
RH
116 break;
117 }
118#endif
119#ifdef ARCH_arm
120 case bfd_arch_arm:
121 if (bfd_big_endian (abfd))
122 disassemble = print_insn_big_arm;
123 else
124 disassemble = print_insn_little_arm;
125 break;
126#endif
adde6300
AM
127#ifdef ARCH_avr
128 case bfd_arch_avr:
129 disassemble = print_insn_avr;
130 break;
131#endif
4b7f6baa
CM
132#ifdef ARCH_bfin
133 case bfd_arch_bfin:
134 disassemble = print_insn_bfin;
135 break;
136#endif
3d3d428f
NC
137#ifdef ARCH_cr16
138 case bfd_arch_cr16:
139 disassemble = print_insn_cr16;
140 break;
141#endif
6c95a37f
HPN
142#ifdef ARCH_cris
143 case bfd_arch_cris:
78966507 144 disassemble = cris_get_disassembler (abfd);
6c95a37f 145 break;
1fe1f39c
NC
146#endif
147#ifdef ARCH_crx
148 case bfd_arch_crx:
149 disassemble = print_insn_crx;
150 break;
6c95a37f 151#endif
252b5132
RH
152#ifdef ARCH_d10v
153 case bfd_arch_d10v:
154 disassemble = print_insn_d10v;
155 break;
156#endif
157#ifdef ARCH_d30v
158 case bfd_arch_d30v:
159 disassemble = print_insn_d30v;
160 break;
161#endif
d172d4ba
NC
162#ifdef ARCH_dlx
163 case bfd_arch_dlx:
164 /* As far as I know we only handle big-endian DLX objects. */
165 disassemble = print_insn_dlx;
166 break;
167#endif
252b5132
RH
168#ifdef ARCH_h8300
169 case bfd_arch_h8300:
049f8936
NC
170 if (bfd_get_mach (abfd) == bfd_mach_h8300h
171 || bfd_get_mach (abfd) == bfd_mach_h8300hn)
252b5132 172 disassemble = print_insn_h8300h;
049f8936 173 else if (bfd_get_mach (abfd) == bfd_mach_h8300s
d43ff6d2 174 || bfd_get_mach (abfd) == bfd_mach_h8300sn
a53b85e2
AO
175 || bfd_get_mach (abfd) == bfd_mach_h8300sx
176 || bfd_get_mach (abfd) == bfd_mach_h8300sxn)
252b5132 177 disassemble = print_insn_h8300s;
b7ed8fad 178 else
252b5132
RH
179 disassemble = print_insn_h8300;
180 break;
181#endif
182#ifdef ARCH_h8500
183 case bfd_arch_h8500:
184 disassemble = print_insn_h8500;
185 break;
186#endif
187#ifdef ARCH_hppa
188 case bfd_arch_hppa:
189 disassemble = print_insn_hppa;
190 break;
191#endif
5b93d8bb
AM
192#ifdef ARCH_i370
193 case bfd_arch_i370:
194 disassemble = print_insn_i370;
195 break;
196#endif
252b5132
RH
197#ifdef ARCH_i386
198 case bfd_arch_i386:
e396998b 199 disassemble = print_insn_i386;
252b5132
RH
200 break;
201#endif
9d751335
JE
202#ifdef ARCH_i860
203 case bfd_arch_i860:
204 disassemble = print_insn_i860;
205 break;
206#endif
252b5132
RH
207#ifdef ARCH_i960
208 case bfd_arch_i960:
209 disassemble = print_insn_i960;
210 break;
211#endif
800eeca4
JW
212#ifdef ARCH_ia64
213 case bfd_arch_ia64:
214 disassemble = print_insn_ia64;
215 break;
216#endif
a40cbfa3
NC
217#ifdef ARCH_ip2k
218 case bfd_arch_ip2k:
219 disassemble = print_insn_ip2k;
220 break;
221#endif
252b5132
RH
222#ifdef ARCH_fr30
223 case bfd_arch_fr30:
224 disassemble = print_insn_fr30;
225 break;
226#endif
84e94c90
NC
227#ifdef ARCH_lm32
228 case bfd_arch_lm32:
229 disassemble = print_insn_lm32;
230 break;
231#endif
252b5132
RH
232#ifdef ARCH_m32r
233 case bfd_arch_m32r:
234 disassemble = print_insn_m32r;
235 break;
236#endif
60bcf0fa
NC
237#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
238 case bfd_arch_m68hc11:
239 disassemble = print_insn_m68hc11;
240 break;
241 case bfd_arch_m68hc12:
242 disassemble = print_insn_m68hc12;
243 break;
244#endif
252b5132
RH
245#ifdef ARCH_m68k
246 case bfd_arch_m68k:
247 disassemble = print_insn_m68k;
248 break;
249#endif
250#ifdef ARCH_m88k
251 case bfd_arch_m88k:
252 disassemble = print_insn_m88k;
253 break;
254#endif
7499d566
NC
255#ifdef ARCH_maxq
256 case bfd_arch_maxq:
257 disassemble = print_insn_maxq_little;
258 break;
259#endif
d031aafb
NS
260#ifdef ARCH_mt
261 case bfd_arch_mt:
262 disassemble = print_insn_mt;
ac188222
DB
263 break;
264#endif
2469cfa2
NC
265#ifdef ARCH_msp430
266 case bfd_arch_msp430:
267 disassemble = print_insn_msp430;
268 break;
269#endif
252b5132
RH
270#ifdef ARCH_ns32k
271 case bfd_arch_ns32k:
272 disassemble = print_insn_ns32k;
273 break;
274#endif
275#ifdef ARCH_mcore
276 case bfd_arch_mcore:
277 disassemble = print_insn_mcore;
278 break;
279#endif
bd2f2e55
DB
280#ifdef ARCH_mep
281 case bfd_arch_mep:
282 disassemble = print_insn_mep;
283 break;
284#endif
252b5132
RH
285#ifdef ARCH_mips
286 case bfd_arch_mips:
287 if (bfd_big_endian (abfd))
288 disassemble = print_insn_big_mips;
289 else
290 disassemble = print_insn_little_mips;
291 break;
292#endif
3c3bdf30
NC
293#ifdef ARCH_mmix
294 case bfd_arch_mmix:
295 disassemble = print_insn_mmix;
296 break;
297#endif
252b5132
RH
298#ifdef ARCH_mn10200
299 case bfd_arch_mn10200:
300 disassemble = print_insn_mn10200;
301 break;
302#endif
303#ifdef ARCH_mn10300
304 case bfd_arch_mn10300:
305 disassemble = print_insn_mn10300;
306 break;
307#endif
87e6d782
NC
308#ifdef ARCH_openrisc
309 case bfd_arch_openrisc:
310 disassemble = print_insn_openrisc;
311 break;
312#endif
3b16e843
NC
313#ifdef ARCH_or32
314 case bfd_arch_or32:
315 if (bfd_big_endian (abfd))
316 disassemble = print_insn_big_or32;
317 else
318 disassemble = print_insn_little_or32;
319 break;
320#endif
e135f41b
NC
321#ifdef ARCH_pdp11
322 case bfd_arch_pdp11:
323 disassemble = print_insn_pdp11;
324 break;
325#endif
1e608f98
ILT
326#ifdef ARCH_pj
327 case bfd_arch_pj:
328 disassemble = print_insn_pj;
329 break;
330#endif
252b5132
RH
331#ifdef ARCH_powerpc
332 case bfd_arch_powerpc:
333 if (bfd_big_endian (abfd))
334 disassemble = print_insn_big_powerpc;
335 else
336 disassemble = print_insn_little_powerpc;
337 break;
338#endif
339#ifdef ARCH_rs6000
340 case bfd_arch_rs6000:
39c20e8f 341 if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
7f6d05e8
CP
342 disassemble = print_insn_big_powerpc;
343 else
344 disassemble = print_insn_rs6000;
252b5132
RH
345 break;
346#endif
a85d7ed0
NC
347#ifdef ARCH_s390
348 case bfd_arch_s390:
349 disassemble = print_insn_s390;
350 break;
351#endif
1c0d3aa6
NC
352#ifdef ARCH_score
353 case bfd_arch_score:
354 if (bfd_big_endian (abfd))
355 disassemble = print_insn_big_score;
356 else
357 disassemble = print_insn_little_score;
358 break;
359#endif
252b5132
RH
360#ifdef ARCH_sh
361 case bfd_arch_sh:
1c509ca8 362 disassemble = print_insn_sh;
252b5132
RH
363 break;
364#endif
365#ifdef ARCH_sparc
366 case bfd_arch_sparc:
367 disassemble = print_insn_sparc;
368 break;
369#endif
e9f53129
AM
370#ifdef ARCH_spu
371 case bfd_arch_spu:
372 disassemble = print_insn_spu;
373 break;
374#endif
252b5132
RH
375#ifdef ARCH_tic30
376 case bfd_arch_tic30:
377 disassemble = print_insn_tic30;
378 break;
379#endif
026df7c5
NC
380#ifdef ARCH_tic4x
381 case bfd_arch_tic4x:
382 disassemble = print_insn_tic4x;
383 break;
384#endif
5c84d377
TW
385#ifdef ARCH_tic54x
386 case bfd_arch_tic54x:
387 disassemble = print_insn_tic54x;
388 break;
389#endif
252b5132
RH
390#ifdef ARCH_tic80
391 case bfd_arch_tic80:
392 disassemble = print_insn_tic80;
393 break;
394#endif
395#ifdef ARCH_v850
396 case bfd_arch_v850:
397 disassemble = print_insn_v850;
398 break;
399#endif
400#ifdef ARCH_w65
401 case bfd_arch_w65:
402 disassemble = print_insn_w65;
403 break;
404#endif
93fbbb04
GK
405#ifdef ARCH_xstormy16
406 case bfd_arch_xstormy16:
407 disassemble = print_insn_xstormy16;
408 break;
409#endif
d70c5fc7
NC
410#ifdef ARCH_xc16x
411 case bfd_arch_xc16x:
412 disassemble = print_insn_xc16x;
413 break;
414#endif
e0001a05
NC
415#ifdef ARCH_xtensa
416 case bfd_arch_xtensa:
417 disassemble = print_insn_xtensa;
418 break;
419#endif
3c9b82ba
NC
420#ifdef ARCH_z80
421 case bfd_arch_z80:
422 disassemble = print_insn_z80;
423 break;
424#endif
252b5132
RH
425#ifdef ARCH_z8k
426 case bfd_arch_z8k:
427 if (bfd_get_mach(abfd) == bfd_mach_z8001)
428 disassemble = print_insn_z8001;
b7ed8fad 429 else
252b5132
RH
430 disassemble = print_insn_z8002;
431 break;
432#endif
433#ifdef ARCH_vax
434 case bfd_arch_vax:
435 disassemble = print_insn_vax;
436 break;
fd3c93d5
DB
437#endif
438#ifdef ARCH_frv
439 case bfd_arch_frv:
440 disassemble = print_insn_frv;
441 break;
47b1a55a
SC
442#endif
443#ifdef ARCH_iq2000
444 case bfd_arch_iq2000:
445 disassemble = print_insn_iq2000;
446 break;
49f58d10
JB
447#endif
448#ifdef ARCH_m32c
449 case bfd_arch_m32c:
450 disassemble = print_insn_m32c;
451 break;
252b5132
RH
452#endif
453 default:
454 return 0;
455 }
456 return disassemble;
457}
94470b23
NC
458
459void
9aaaa291 460disassembler_usage (stream)
7f32bebc 461 FILE * stream ATTRIBUTE_UNUSED;
94470b23 462{
58efb6c0
NC
463#ifdef ARCH_arm
464 print_arm_disassembler_options (stream);
465#endif
640c0ccd
CD
466#ifdef ARCH_mips
467 print_mips_disassembler_options (stream);
468#endif
07dd56a9
NC
469#ifdef ARCH_powerpc
470 print_ppc_disassembler_options (stream);
471#endif
f59a29b9
L
472#ifdef ARCH_i386
473 print_i386_disassembler_options (stream);
474#endif
112b7c50
AK
475#ifdef ARCH_s390
476 print_s390_disassembler_options (stream);
477#endif
b7ed8fad 478
94470b23
NC
479 return;
480}
22a398e1
NC
481
482void
483disassemble_init_for_target (struct disassemble_info * info)
484{
485 if (info == NULL)
486 return;
487
488 switch (info->arch)
489 {
490#ifdef ARCH_arm
491 case bfd_arch_arm:
492 info->symbol_is_valid = arm_symbol_is_valid;
d99b6465 493 info->disassembler_needs_relocs = TRUE;
22a398e1 494 break;
0bcb06d2
AS
495#endif
496#ifdef ARCH_ia64
497 case bfd_arch_ia64:
498 info->skip_zeroes = 16;
499 break;
500#endif
501#ifdef ARCH_tic4x
502 case bfd_arch_tic4x:
503 info->skip_zeroes = 32;
fb53f5a8 504 break;
49f58d10 505#endif
bd2f2e55
DB
506#ifdef ARCH_mep
507 case bfd_arch_mep:
508 info->skip_zeroes = 256;
509 info->skip_zeroes_at_end = 0;
510 break;
511#endif
49f58d10
JB
512#ifdef ARCH_m32c
513 case bfd_arch_m32c:
514 info->endian = BFD_ENDIAN_BIG;
fb53f5a8
DB
515 if (! info->insn_sets)
516 {
517 info->insn_sets = cgen_bitset_create (ISA_MAX);
518 if (info->mach == bfd_mach_m16c)
519 cgen_bitset_set (info->insn_sets, ISA_M16C);
520 else
521 cgen_bitset_set (info->insn_sets, ISA_M32C);
522 }
49f58d10 523 break;
22a398e1
NC
524#endif
525 default:
526 break;
527 }
528}
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