Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
aef6203b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
1c0d3aa6 | 3 | 2004, 2005, 2006 Free Software Foundation, Inc. |
252b5132 | 4 | |
7499d566 NC |
5 | This program is free software; you can redistribute it and/or modify |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
252b5132 | 9 | |
7499d566 NC |
10 | This program is distributed in the hope that it will be useful, |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
252b5132 | 14 | |
7499d566 NC |
15 | You should have received a copy of the GNU General Public License |
16 | along with this program; if not, write to the Free Software | |
f4321104 | 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 18 | |
0d8dfecf | 19 | #include "sysdep.h" |
252b5132 RH |
20 | #include "dis-asm.h" |
21 | ||
22 | #ifdef ARCH_all | |
252b5132 RH |
23 | #define ARCH_alpha |
24 | #define ARCH_arc | |
25 | #define ARCH_arm | |
adde6300 | 26 | #define ARCH_avr |
4b7f6baa | 27 | #define ARCH_bfin |
6c95a37f | 28 | #define ARCH_cris |
1fe1f39c | 29 | #define ARCH_crx |
252b5132 RH |
30 | #define ARCH_d10v |
31 | #define ARCH_d30v | |
d172d4ba | 32 | #define ARCH_dlx |
e729279b NC |
33 | #define ARCH_fr30 |
34 | #define ARCH_frv | |
252b5132 RH |
35 | #define ARCH_h8300 |
36 | #define ARCH_h8500 | |
37 | #define ARCH_hppa | |
5b93d8bb | 38 | #define ARCH_i370 |
252b5132 | 39 | #define ARCH_i386 |
9d751335 | 40 | #define ARCH_i860 |
252b5132 | 41 | #define ARCH_i960 |
800eeca4 | 42 | #define ARCH_ia64 |
e729279b NC |
43 | #define ARCH_ip2k |
44 | #define ARCH_iq2000 | |
45 | #define ARCH_m32c | |
252b5132 | 46 | #define ARCH_m32r |
60bcf0fa NC |
47 | #define ARCH_m68hc11 |
48 | #define ARCH_m68hc12 | |
e729279b | 49 | #define ARCH_m68k |
252b5132 | 50 | #define ARCH_m88k |
7499d566 | 51 | #define ARCH_maxq |
252b5132 RH |
52 | #define ARCH_mcore |
53 | #define ARCH_mips | |
3c3bdf30 | 54 | #define ARCH_mmix |
252b5132 RH |
55 | #define ARCH_mn10200 |
56 | #define ARCH_mn10300 | |
d031aafb | 57 | #define ARCH_mt |
2469cfa2 | 58 | #define ARCH_msp430 |
252b5132 | 59 | #define ARCH_ns32k |
87e6d782 | 60 | #define ARCH_openrisc |
3b16e843 | 61 | #define ARCH_or32 |
e135f41b | 62 | #define ARCH_pdp11 |
1e608f98 | 63 | #define ARCH_pj |
252b5132 RH |
64 | #define ARCH_powerpc |
65 | #define ARCH_rs6000 | |
a85d7ed0 | 66 | #define ARCH_s390 |
1c0d3aa6 | 67 | #define ARCH_score |
252b5132 RH |
68 | #define ARCH_sh |
69 | #define ARCH_sparc | |
70 | #define ARCH_tic30 | |
026df7c5 | 71 | #define ARCH_tic4x |
5c84d377 | 72 | #define ARCH_tic54x |
252b5132 RH |
73 | #define ARCH_tic80 |
74 | #define ARCH_v850 | |
75 | #define ARCH_vax | |
76 | #define ARCH_w65 | |
93fbbb04 | 77 | #define ARCH_xstormy16 |
d70c5fc7 | 78 | #define ARCH_xc16x |
e0001a05 | 79 | #define ARCH_xtensa |
3c9b82ba | 80 | #define ARCH_z80 |
252b5132 | 81 | #define ARCH_z8k |
d28847ce | 82 | #define INCLUDE_SHMEDIA |
252b5132 RH |
83 | #endif |
84 | ||
49f58d10 JB |
85 | #ifdef ARCH_m32c |
86 | #include "m32c-desc.h" | |
87 | #endif | |
252b5132 RH |
88 | |
89 | disassembler_ftype | |
90 | disassembler (abfd) | |
91 | bfd *abfd; | |
92 | { | |
93 | enum bfd_architecture a = bfd_get_arch (abfd); | |
94 | disassembler_ftype disassemble; | |
95 | ||
96 | switch (a) | |
97 | { | |
98 | /* If you add a case to this table, also add it to the | |
99 | ARCH_all definition right above this function. */ | |
252b5132 RH |
100 | #ifdef ARCH_alpha |
101 | case bfd_arch_alpha: | |
102 | disassemble = print_insn_alpha; | |
103 | break; | |
104 | #endif | |
105 | #ifdef ARCH_arc | |
106 | case bfd_arch_arc: | |
107 | { | |
0d2bcfaf | 108 | disassemble = arc_get_disassembler (abfd); |
252b5132 RH |
109 | break; |
110 | } | |
111 | #endif | |
112 | #ifdef ARCH_arm | |
113 | case bfd_arch_arm: | |
114 | if (bfd_big_endian (abfd)) | |
115 | disassemble = print_insn_big_arm; | |
116 | else | |
117 | disassemble = print_insn_little_arm; | |
118 | break; | |
119 | #endif | |
adde6300 AM |
120 | #ifdef ARCH_avr |
121 | case bfd_arch_avr: | |
122 | disassemble = print_insn_avr; | |
123 | break; | |
124 | #endif | |
4b7f6baa CM |
125 | #ifdef ARCH_bfin |
126 | case bfd_arch_bfin: | |
127 | disassemble = print_insn_bfin; | |
128 | break; | |
129 | #endif | |
6c95a37f HPN |
130 | #ifdef ARCH_cris |
131 | case bfd_arch_cris: | |
78966507 | 132 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 133 | break; |
1fe1f39c NC |
134 | #endif |
135 | #ifdef ARCH_crx | |
136 | case bfd_arch_crx: | |
137 | disassemble = print_insn_crx; | |
138 | break; | |
6c95a37f | 139 | #endif |
252b5132 RH |
140 | #ifdef ARCH_d10v |
141 | case bfd_arch_d10v: | |
142 | disassemble = print_insn_d10v; | |
143 | break; | |
144 | #endif | |
145 | #ifdef ARCH_d30v | |
146 | case bfd_arch_d30v: | |
147 | disassemble = print_insn_d30v; | |
148 | break; | |
149 | #endif | |
d172d4ba NC |
150 | #ifdef ARCH_dlx |
151 | case bfd_arch_dlx: | |
152 | /* As far as I know we only handle big-endian DLX objects. */ | |
153 | disassemble = print_insn_dlx; | |
154 | break; | |
155 | #endif | |
252b5132 RH |
156 | #ifdef ARCH_h8300 |
157 | case bfd_arch_h8300: | |
049f8936 NC |
158 | if (bfd_get_mach (abfd) == bfd_mach_h8300h |
159 | || bfd_get_mach (abfd) == bfd_mach_h8300hn) | |
252b5132 | 160 | disassemble = print_insn_h8300h; |
049f8936 | 161 | else if (bfd_get_mach (abfd) == bfd_mach_h8300s |
d43ff6d2 | 162 | || bfd_get_mach (abfd) == bfd_mach_h8300sn |
a53b85e2 AO |
163 | || bfd_get_mach (abfd) == bfd_mach_h8300sx |
164 | || bfd_get_mach (abfd) == bfd_mach_h8300sxn) | |
252b5132 | 165 | disassemble = print_insn_h8300s; |
b7ed8fad | 166 | else |
252b5132 RH |
167 | disassemble = print_insn_h8300; |
168 | break; | |
169 | #endif | |
170 | #ifdef ARCH_h8500 | |
171 | case bfd_arch_h8500: | |
172 | disassemble = print_insn_h8500; | |
173 | break; | |
174 | #endif | |
175 | #ifdef ARCH_hppa | |
176 | case bfd_arch_hppa: | |
177 | disassemble = print_insn_hppa; | |
178 | break; | |
179 | #endif | |
5b93d8bb AM |
180 | #ifdef ARCH_i370 |
181 | case bfd_arch_i370: | |
182 | disassemble = print_insn_i370; | |
183 | break; | |
184 | #endif | |
252b5132 RH |
185 | #ifdef ARCH_i386 |
186 | case bfd_arch_i386: | |
e396998b | 187 | disassemble = print_insn_i386; |
252b5132 RH |
188 | break; |
189 | #endif | |
9d751335 JE |
190 | #ifdef ARCH_i860 |
191 | case bfd_arch_i860: | |
192 | disassemble = print_insn_i860; | |
193 | break; | |
194 | #endif | |
252b5132 RH |
195 | #ifdef ARCH_i960 |
196 | case bfd_arch_i960: | |
197 | disassemble = print_insn_i960; | |
198 | break; | |
199 | #endif | |
800eeca4 JW |
200 | #ifdef ARCH_ia64 |
201 | case bfd_arch_ia64: | |
202 | disassemble = print_insn_ia64; | |
203 | break; | |
204 | #endif | |
a40cbfa3 NC |
205 | #ifdef ARCH_ip2k |
206 | case bfd_arch_ip2k: | |
207 | disassemble = print_insn_ip2k; | |
208 | break; | |
209 | #endif | |
252b5132 RH |
210 | #ifdef ARCH_fr30 |
211 | case bfd_arch_fr30: | |
212 | disassemble = print_insn_fr30; | |
213 | break; | |
214 | #endif | |
215 | #ifdef ARCH_m32r | |
216 | case bfd_arch_m32r: | |
217 | disassemble = print_insn_m32r; | |
218 | break; | |
219 | #endif | |
60bcf0fa NC |
220 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) |
221 | case bfd_arch_m68hc11: | |
222 | disassemble = print_insn_m68hc11; | |
223 | break; | |
224 | case bfd_arch_m68hc12: | |
225 | disassemble = print_insn_m68hc12; | |
226 | break; | |
227 | #endif | |
252b5132 RH |
228 | #ifdef ARCH_m68k |
229 | case bfd_arch_m68k: | |
230 | disassemble = print_insn_m68k; | |
231 | break; | |
232 | #endif | |
233 | #ifdef ARCH_m88k | |
234 | case bfd_arch_m88k: | |
235 | disassemble = print_insn_m88k; | |
236 | break; | |
237 | #endif | |
7499d566 NC |
238 | #ifdef ARCH_maxq |
239 | case bfd_arch_maxq: | |
240 | disassemble = print_insn_maxq_little; | |
241 | break; | |
242 | #endif | |
d031aafb NS |
243 | #ifdef ARCH_mt |
244 | case bfd_arch_mt: | |
245 | disassemble = print_insn_mt; | |
ac188222 DB |
246 | break; |
247 | #endif | |
2469cfa2 NC |
248 | #ifdef ARCH_msp430 |
249 | case bfd_arch_msp430: | |
250 | disassemble = print_insn_msp430; | |
251 | break; | |
252 | #endif | |
252b5132 RH |
253 | #ifdef ARCH_ns32k |
254 | case bfd_arch_ns32k: | |
255 | disassemble = print_insn_ns32k; | |
256 | break; | |
257 | #endif | |
258 | #ifdef ARCH_mcore | |
259 | case bfd_arch_mcore: | |
260 | disassemble = print_insn_mcore; | |
261 | break; | |
262 | #endif | |
263 | #ifdef ARCH_mips | |
264 | case bfd_arch_mips: | |
265 | if (bfd_big_endian (abfd)) | |
266 | disassemble = print_insn_big_mips; | |
267 | else | |
268 | disassemble = print_insn_little_mips; | |
269 | break; | |
270 | #endif | |
3c3bdf30 NC |
271 | #ifdef ARCH_mmix |
272 | case bfd_arch_mmix: | |
273 | disassemble = print_insn_mmix; | |
274 | break; | |
275 | #endif | |
252b5132 RH |
276 | #ifdef ARCH_mn10200 |
277 | case bfd_arch_mn10200: | |
278 | disassemble = print_insn_mn10200; | |
279 | break; | |
280 | #endif | |
281 | #ifdef ARCH_mn10300 | |
282 | case bfd_arch_mn10300: | |
283 | disassemble = print_insn_mn10300; | |
284 | break; | |
285 | #endif | |
87e6d782 NC |
286 | #ifdef ARCH_openrisc |
287 | case bfd_arch_openrisc: | |
288 | disassemble = print_insn_openrisc; | |
289 | break; | |
290 | #endif | |
3b16e843 NC |
291 | #ifdef ARCH_or32 |
292 | case bfd_arch_or32: | |
293 | if (bfd_big_endian (abfd)) | |
294 | disassemble = print_insn_big_or32; | |
295 | else | |
296 | disassemble = print_insn_little_or32; | |
297 | break; | |
298 | #endif | |
e135f41b NC |
299 | #ifdef ARCH_pdp11 |
300 | case bfd_arch_pdp11: | |
301 | disassemble = print_insn_pdp11; | |
302 | break; | |
303 | #endif | |
1e608f98 ILT |
304 | #ifdef ARCH_pj |
305 | case bfd_arch_pj: | |
306 | disassemble = print_insn_pj; | |
307 | break; | |
308 | #endif | |
252b5132 RH |
309 | #ifdef ARCH_powerpc |
310 | case bfd_arch_powerpc: | |
311 | if (bfd_big_endian (abfd)) | |
312 | disassemble = print_insn_big_powerpc; | |
313 | else | |
314 | disassemble = print_insn_little_powerpc; | |
315 | break; | |
316 | #endif | |
317 | #ifdef ARCH_rs6000 | |
318 | case bfd_arch_rs6000: | |
39c20e8f | 319 | if (bfd_get_mach (abfd) == bfd_mach_ppc_620) |
7f6d05e8 CP |
320 | disassemble = print_insn_big_powerpc; |
321 | else | |
322 | disassemble = print_insn_rs6000; | |
252b5132 RH |
323 | break; |
324 | #endif | |
a85d7ed0 NC |
325 | #ifdef ARCH_s390 |
326 | case bfd_arch_s390: | |
327 | disassemble = print_insn_s390; | |
328 | break; | |
329 | #endif | |
1c0d3aa6 NC |
330 | #ifdef ARCH_score |
331 | case bfd_arch_score: | |
332 | if (bfd_big_endian (abfd)) | |
333 | disassemble = print_insn_big_score; | |
334 | else | |
335 | disassemble = print_insn_little_score; | |
336 | break; | |
337 | #endif | |
252b5132 RH |
338 | #ifdef ARCH_sh |
339 | case bfd_arch_sh: | |
1c509ca8 | 340 | disassemble = print_insn_sh; |
252b5132 RH |
341 | break; |
342 | #endif | |
343 | #ifdef ARCH_sparc | |
344 | case bfd_arch_sparc: | |
345 | disassemble = print_insn_sparc; | |
346 | break; | |
347 | #endif | |
348 | #ifdef ARCH_tic30 | |
349 | case bfd_arch_tic30: | |
350 | disassemble = print_insn_tic30; | |
351 | break; | |
352 | #endif | |
026df7c5 NC |
353 | #ifdef ARCH_tic4x |
354 | case bfd_arch_tic4x: | |
355 | disassemble = print_insn_tic4x; | |
356 | break; | |
357 | #endif | |
5c84d377 TW |
358 | #ifdef ARCH_tic54x |
359 | case bfd_arch_tic54x: | |
360 | disassemble = print_insn_tic54x; | |
361 | break; | |
362 | #endif | |
252b5132 RH |
363 | #ifdef ARCH_tic80 |
364 | case bfd_arch_tic80: | |
365 | disassemble = print_insn_tic80; | |
366 | break; | |
367 | #endif | |
368 | #ifdef ARCH_v850 | |
369 | case bfd_arch_v850: | |
370 | disassemble = print_insn_v850; | |
371 | break; | |
372 | #endif | |
373 | #ifdef ARCH_w65 | |
374 | case bfd_arch_w65: | |
375 | disassemble = print_insn_w65; | |
376 | break; | |
377 | #endif | |
93fbbb04 GK |
378 | #ifdef ARCH_xstormy16 |
379 | case bfd_arch_xstormy16: | |
380 | disassemble = print_insn_xstormy16; | |
381 | break; | |
382 | #endif | |
d70c5fc7 NC |
383 | #ifdef ARCH_xc16x |
384 | case bfd_arch_xc16x: | |
385 | disassemble = print_insn_xc16x; | |
386 | break; | |
387 | #endif | |
e0001a05 NC |
388 | #ifdef ARCH_xtensa |
389 | case bfd_arch_xtensa: | |
390 | disassemble = print_insn_xtensa; | |
391 | break; | |
392 | #endif | |
3c9b82ba NC |
393 | #ifdef ARCH_z80 |
394 | case bfd_arch_z80: | |
395 | disassemble = print_insn_z80; | |
396 | break; | |
397 | #endif | |
252b5132 RH |
398 | #ifdef ARCH_z8k |
399 | case bfd_arch_z8k: | |
400 | if (bfd_get_mach(abfd) == bfd_mach_z8001) | |
401 | disassemble = print_insn_z8001; | |
b7ed8fad | 402 | else |
252b5132 RH |
403 | disassemble = print_insn_z8002; |
404 | break; | |
405 | #endif | |
406 | #ifdef ARCH_vax | |
407 | case bfd_arch_vax: | |
408 | disassemble = print_insn_vax; | |
409 | break; | |
fd3c93d5 DB |
410 | #endif |
411 | #ifdef ARCH_frv | |
412 | case bfd_arch_frv: | |
413 | disassemble = print_insn_frv; | |
414 | break; | |
47b1a55a SC |
415 | #endif |
416 | #ifdef ARCH_iq2000 | |
417 | case bfd_arch_iq2000: | |
418 | disassemble = print_insn_iq2000; | |
419 | break; | |
49f58d10 JB |
420 | #endif |
421 | #ifdef ARCH_m32c | |
422 | case bfd_arch_m32c: | |
423 | disassemble = print_insn_m32c; | |
424 | break; | |
252b5132 RH |
425 | #endif |
426 | default: | |
427 | return 0; | |
428 | } | |
429 | return disassemble; | |
430 | } | |
94470b23 NC |
431 | |
432 | void | |
9aaaa291 | 433 | disassembler_usage (stream) |
7f32bebc | 434 | FILE * stream ATTRIBUTE_UNUSED; |
94470b23 | 435 | { |
58efb6c0 NC |
436 | #ifdef ARCH_arm |
437 | print_arm_disassembler_options (stream); | |
438 | #endif | |
640c0ccd CD |
439 | #ifdef ARCH_mips |
440 | print_mips_disassembler_options (stream); | |
441 | #endif | |
07dd56a9 NC |
442 | #ifdef ARCH_powerpc |
443 | print_ppc_disassembler_options (stream); | |
444 | #endif | |
b7ed8fad | 445 | |
94470b23 NC |
446 | return; |
447 | } | |
22a398e1 NC |
448 | |
449 | void | |
450 | disassemble_init_for_target (struct disassemble_info * info) | |
451 | { | |
452 | if (info == NULL) | |
453 | return; | |
454 | ||
455 | switch (info->arch) | |
456 | { | |
457 | #ifdef ARCH_arm | |
458 | case bfd_arch_arm: | |
459 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 460 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 461 | break; |
0bcb06d2 AS |
462 | #endif |
463 | #ifdef ARCH_ia64 | |
464 | case bfd_arch_ia64: | |
465 | info->skip_zeroes = 16; | |
466 | break; | |
467 | #endif | |
468 | #ifdef ARCH_tic4x | |
469 | case bfd_arch_tic4x: | |
470 | info->skip_zeroes = 32; | |
fb53f5a8 | 471 | break; |
49f58d10 JB |
472 | #endif |
473 | #ifdef ARCH_m32c | |
474 | case bfd_arch_m32c: | |
475 | info->endian = BFD_ENDIAN_BIG; | |
fb53f5a8 DB |
476 | if (! info->insn_sets) |
477 | { | |
478 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
479 | if (info->mach == bfd_mach_m16c) | |
480 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
481 | else | |
482 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
483 | } | |
49f58d10 | 484 | break; |
22a398e1 NC |
485 | #endif |
486 | default: | |
487 | break; | |
488 | } | |
489 | } |