Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
219d1afa | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 9 | (at your option) any later version. |
252b5132 | 10 | |
7499d566 NC |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
252b5132 | 15 | |
7499d566 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
88c1242d | 22 | #include "disassemble.h" |
65b48a81 | 23 | #include "safe-ctype.h" |
003ca0fd | 24 | #include <assert.h> |
252b5132 RH |
25 | |
26 | #ifdef ARCH_all | |
a06ea964 | 27 | #define ARCH_aarch64 |
252b5132 RH |
28 | #define ARCH_alpha |
29 | #define ARCH_arc | |
30 | #define ARCH_arm | |
adde6300 | 31 | #define ARCH_avr |
4b7f6baa | 32 | #define ARCH_bfin |
3d3d428f | 33 | #define ARCH_cr16 |
6c95a37f | 34 | #define ARCH_cris |
1fe1f39c | 35 | #define ARCH_crx |
b8891f8d | 36 | #define ARCH_csky |
252b5132 RH |
37 | #define ARCH_d10v |
38 | #define ARCH_d30v | |
d172d4ba | 39 | #define ARCH_dlx |
56b13185 | 40 | #define ARCH_epiphany |
e729279b NC |
41 | #define ARCH_fr30 |
42 | #define ARCH_frv | |
3f8107ab | 43 | #define ARCH_ft32 |
252b5132 | 44 | #define ARCH_h8300 |
252b5132 RH |
45 | #define ARCH_hppa |
46 | #define ARCH_i386 | |
800eeca4 | 47 | #define ARCH_ia64 |
e729279b NC |
48 | #define ARCH_ip2k |
49 | #define ARCH_iq2000 | |
84e94c90 | 50 | #define ARCH_lm32 |
e729279b | 51 | #define ARCH_m32c |
252b5132 | 52 | #define ARCH_m32r |
60bcf0fa NC |
53 | #define ARCH_m68hc11 |
54 | #define ARCH_m68hc12 | |
e729279b | 55 | #define ARCH_m68k |
252b5132 | 56 | #define ARCH_mcore |
bd2f2e55 | 57 | #define ARCH_mep |
a3c62988 | 58 | #define ARCH_metag |
7ba29e2a | 59 | #define ARCH_microblaze |
252b5132 | 60 | #define ARCH_mips |
3c3bdf30 | 61 | #define ARCH_mmix |
252b5132 RH |
62 | #define ARCH_mn10200 |
63 | #define ARCH_mn10300 | |
59b1530d | 64 | #define ARCH_moxie |
d031aafb | 65 | #define ARCH_mt |
2469cfa2 | 66 | #define ARCH_msp430 |
35c08157 | 67 | #define ARCH_nds32 |
fe944acf | 68 | #define ARCH_nfp |
36591ba1 | 69 | #define ARCH_nios2 |
252b5132 | 70 | #define ARCH_ns32k |
73589c9d | 71 | #define ARCH_or1k |
e135f41b | 72 | #define ARCH_pdp11 |
1e608f98 | 73 | #define ARCH_pj |
252b5132 | 74 | #define ARCH_powerpc |
11146849 | 75 | #define ARCH_pru |
0bccfb29 | 76 | #define ARCH_riscv |
252b5132 | 77 | #define ARCH_rs6000 |
99c513f6 | 78 | #define ARCH_rl78 |
c7927a3c | 79 | #define ARCH_rx |
a85d7ed0 | 80 | #define ARCH_s390 |
1c0d3aa6 | 81 | #define ARCH_score |
252b5132 RH |
82 | #define ARCH_sh |
83 | #define ARCH_sparc | |
e9f53129 | 84 | #define ARCH_spu |
252b5132 | 85 | #define ARCH_tic30 |
026df7c5 | 86 | #define ARCH_tic4x |
5c84d377 | 87 | #define ARCH_tic54x |
40b36596 | 88 | #define ARCH_tic6x |
252b5132 | 89 | #define ARCH_tic80 |
aa137e4d NC |
90 | #define ARCH_tilegx |
91 | #define ARCH_tilepro | |
252b5132 RH |
92 | #define ARCH_v850 |
93 | #define ARCH_vax | |
1945cfa5 | 94 | #define ARCH_visium |
62ecb94c | 95 | #define ARCH_wasm32 |
93fbbb04 | 96 | #define ARCH_xstormy16 |
d70c5fc7 | 97 | #define ARCH_xc16x |
f6c1a2d5 | 98 | #define ARCH_xgate |
e0001a05 | 99 | #define ARCH_xtensa |
3c9b82ba | 100 | #define ARCH_z80 |
252b5132 RH |
101 | #define ARCH_z8k |
102 | #endif | |
103 | ||
49f58d10 JB |
104 | #ifdef ARCH_m32c |
105 | #include "m32c-desc.h" | |
106 | #endif | |
252b5132 RH |
107 | |
108 | disassembler_ftype | |
b28b8b5e L |
109 | disassembler (enum bfd_architecture a, |
110 | bfd_boolean big ATTRIBUTE_UNUSED, | |
111 | unsigned long mach ATTRIBUTE_UNUSED, | |
e347efc3 | 112 | bfd *abfd ATTRIBUTE_UNUSED) |
252b5132 | 113 | { |
252b5132 RH |
114 | disassembler_ftype disassemble; |
115 | ||
116 | switch (a) | |
117 | { | |
118 | /* If you add a case to this table, also add it to the | |
119 | ARCH_all definition right above this function. */ | |
a06ea964 NC |
120 | #ifdef ARCH_aarch64 |
121 | case bfd_arch_aarch64: | |
122 | disassemble = print_insn_aarch64; | |
123 | break; | |
124 | #endif | |
252b5132 RH |
125 | #ifdef ARCH_alpha |
126 | case bfd_arch_alpha: | |
127 | disassemble = print_insn_alpha; | |
128 | break; | |
129 | #endif | |
130 | #ifdef ARCH_arc | |
131 | case bfd_arch_arc: | |
6ca4eb77 AM |
132 | disassemble = arc_get_disassembler (abfd); |
133 | break; | |
252b5132 RH |
134 | #endif |
135 | #ifdef ARCH_arm | |
136 | case bfd_arch_arm: | |
003ca0fd | 137 | if (big) |
252b5132 RH |
138 | disassemble = print_insn_big_arm; |
139 | else | |
140 | disassemble = print_insn_little_arm; | |
141 | break; | |
142 | #endif | |
adde6300 AM |
143 | #ifdef ARCH_avr |
144 | case bfd_arch_avr: | |
145 | disassemble = print_insn_avr; | |
146 | break; | |
147 | #endif | |
4b7f6baa CM |
148 | #ifdef ARCH_bfin |
149 | case bfd_arch_bfin: | |
150 | disassemble = print_insn_bfin; | |
151 | break; | |
152 | #endif | |
3d3d428f NC |
153 | #ifdef ARCH_cr16 |
154 | case bfd_arch_cr16: | |
155 | disassemble = print_insn_cr16; | |
156 | break; | |
157 | #endif | |
6c95a37f HPN |
158 | #ifdef ARCH_cris |
159 | case bfd_arch_cris: | |
78966507 | 160 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 161 | break; |
1fe1f39c NC |
162 | #endif |
163 | #ifdef ARCH_crx | |
164 | case bfd_arch_crx: | |
165 | disassemble = print_insn_crx; | |
166 | break; | |
6c95a37f | 167 | #endif |
b8891f8d AJ |
168 | #ifdef ARCH_csky |
169 | case bfd_arch_csky: | |
170 | disassemble = csky_get_disassembler (abfd); | |
171 | break; | |
172 | #endif | |
173 | ||
252b5132 RH |
174 | #ifdef ARCH_d10v |
175 | case bfd_arch_d10v: | |
176 | disassemble = print_insn_d10v; | |
177 | break; | |
178 | #endif | |
179 | #ifdef ARCH_d30v | |
180 | case bfd_arch_d30v: | |
181 | disassemble = print_insn_d30v; | |
182 | break; | |
183 | #endif | |
d172d4ba NC |
184 | #ifdef ARCH_dlx |
185 | case bfd_arch_dlx: | |
186 | /* As far as I know we only handle big-endian DLX objects. */ | |
187 | disassemble = print_insn_dlx; | |
188 | break; | |
189 | #endif | |
252b5132 RH |
190 | #ifdef ARCH_h8300 |
191 | case bfd_arch_h8300: | |
003ca0fd | 192 | if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn) |
252b5132 | 193 | disassemble = print_insn_h8300h; |
003ca0fd YQ |
194 | else if (mach == bfd_mach_h8300s |
195 | || mach == bfd_mach_h8300sn | |
196 | || mach == bfd_mach_h8300sx | |
197 | || mach == bfd_mach_h8300sxn) | |
252b5132 | 198 | disassemble = print_insn_h8300s; |
b7ed8fad | 199 | else |
252b5132 RH |
200 | disassemble = print_insn_h8300; |
201 | break; | |
202 | #endif | |
252b5132 RH |
203 | #ifdef ARCH_hppa |
204 | case bfd_arch_hppa: | |
205 | disassemble = print_insn_hppa; | |
206 | break; | |
207 | #endif | |
208 | #ifdef ARCH_i386 | |
209 | case bfd_arch_i386: | |
7b6d09fb | 210 | case bfd_arch_iamcu: |
8a9036a4 | 211 | case bfd_arch_l1om: |
7a9068fe | 212 | case bfd_arch_k1om: |
e396998b | 213 | disassemble = print_insn_i386; |
252b5132 RH |
214 | break; |
215 | #endif | |
800eeca4 JW |
216 | #ifdef ARCH_ia64 |
217 | case bfd_arch_ia64: | |
218 | disassemble = print_insn_ia64; | |
219 | break; | |
220 | #endif | |
a40cbfa3 NC |
221 | #ifdef ARCH_ip2k |
222 | case bfd_arch_ip2k: | |
223 | disassemble = print_insn_ip2k; | |
224 | break; | |
225 | #endif | |
cfb8c092 NC |
226 | #ifdef ARCH_epiphany |
227 | case bfd_arch_epiphany: | |
228 | disassemble = print_insn_epiphany; | |
229 | break; | |
230 | #endif | |
252b5132 RH |
231 | #ifdef ARCH_fr30 |
232 | case bfd_arch_fr30: | |
233 | disassemble = print_insn_fr30; | |
234 | break; | |
235 | #endif | |
84e94c90 NC |
236 | #ifdef ARCH_lm32 |
237 | case bfd_arch_lm32: | |
238 | disassemble = print_insn_lm32; | |
239 | break; | |
240 | #endif | |
252b5132 RH |
241 | #ifdef ARCH_m32r |
242 | case bfd_arch_m32r: | |
243 | disassemble = print_insn_m32r; | |
244 | break; | |
245 | #endif | |
6927f982 NC |
246 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
247 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
248 | case bfd_arch_m68hc11: |
249 | disassemble = print_insn_m68hc11; | |
250 | break; | |
251 | case bfd_arch_m68hc12: | |
252 | disassemble = print_insn_m68hc12; | |
253 | break; | |
6927f982 NC |
254 | case bfd_arch_m9s12x: |
255 | disassemble = print_insn_m9s12x; | |
256 | break; | |
257 | case bfd_arch_m9s12xg: | |
258 | disassemble = print_insn_m9s12xg; | |
259 | break; | |
60bcf0fa | 260 | #endif |
7b4ae824 JD |
261 | #if defined(ARCH_s12z) |
262 | case bfd_arch_s12z: | |
263 | disassemble = print_insn_s12z; | |
264 | break; | |
265 | #endif | |
252b5132 RH |
266 | #ifdef ARCH_m68k |
267 | case bfd_arch_m68k: | |
268 | disassemble = print_insn_m68k; | |
269 | break; | |
270 | #endif | |
d031aafb NS |
271 | #ifdef ARCH_mt |
272 | case bfd_arch_mt: | |
273 | disassemble = print_insn_mt; | |
ac188222 DB |
274 | break; |
275 | #endif | |
7ba29e2a NC |
276 | #ifdef ARCH_microblaze |
277 | case bfd_arch_microblaze: | |
278 | disassemble = print_insn_microblaze; | |
279 | break; | |
280 | #endif | |
2469cfa2 NC |
281 | #ifdef ARCH_msp430 |
282 | case bfd_arch_msp430: | |
283 | disassemble = print_insn_msp430; | |
284 | break; | |
285 | #endif | |
35c08157 KLC |
286 | #ifdef ARCH_nds32 |
287 | case bfd_arch_nds32: | |
288 | disassemble = print_insn_nds32; | |
289 | break; | |
290 | #endif | |
fe944acf FT |
291 | #ifdef ARCH_nfp |
292 | case bfd_arch_nfp: | |
293 | disassemble = print_insn_nfp; | |
294 | break; | |
295 | #endif | |
252b5132 RH |
296 | #ifdef ARCH_ns32k |
297 | case bfd_arch_ns32k: | |
298 | disassemble = print_insn_ns32k; | |
299 | break; | |
300 | #endif | |
301 | #ifdef ARCH_mcore | |
302 | case bfd_arch_mcore: | |
303 | disassemble = print_insn_mcore; | |
304 | break; | |
305 | #endif | |
bd2f2e55 DB |
306 | #ifdef ARCH_mep |
307 | case bfd_arch_mep: | |
308 | disassemble = print_insn_mep; | |
309 | break; | |
310 | #endif | |
a3c62988 NC |
311 | #ifdef ARCH_metag |
312 | case bfd_arch_metag: | |
313 | disassemble = print_insn_metag; | |
314 | break; | |
315 | #endif | |
252b5132 RH |
316 | #ifdef ARCH_mips |
317 | case bfd_arch_mips: | |
003ca0fd | 318 | if (big) |
252b5132 RH |
319 | disassemble = print_insn_big_mips; |
320 | else | |
321 | disassemble = print_insn_little_mips; | |
322 | break; | |
323 | #endif | |
3c3bdf30 NC |
324 | #ifdef ARCH_mmix |
325 | case bfd_arch_mmix: | |
326 | disassemble = print_insn_mmix; | |
327 | break; | |
328 | #endif | |
252b5132 RH |
329 | #ifdef ARCH_mn10200 |
330 | case bfd_arch_mn10200: | |
331 | disassemble = print_insn_mn10200; | |
332 | break; | |
333 | #endif | |
334 | #ifdef ARCH_mn10300 | |
335 | case bfd_arch_mn10300: | |
336 | disassemble = print_insn_mn10300; | |
337 | break; | |
338 | #endif | |
36591ba1 SL |
339 | #ifdef ARCH_nios2 |
340 | case bfd_arch_nios2: | |
003ca0fd | 341 | if (big) |
36591ba1 SL |
342 | disassemble = print_insn_big_nios2; |
343 | else | |
344 | disassemble = print_insn_little_nios2; | |
345 | break; | |
346 | #endif | |
73589c9d CS |
347 | #ifdef ARCH_or1k |
348 | case bfd_arch_or1k: | |
349 | disassemble = print_insn_or1k; | |
3b16e843 NC |
350 | break; |
351 | #endif | |
e135f41b NC |
352 | #ifdef ARCH_pdp11 |
353 | case bfd_arch_pdp11: | |
354 | disassemble = print_insn_pdp11; | |
355 | break; | |
356 | #endif | |
1e608f98 ILT |
357 | #ifdef ARCH_pj |
358 | case bfd_arch_pj: | |
359 | disassemble = print_insn_pj; | |
360 | break; | |
361 | #endif | |
252b5132 RH |
362 | #ifdef ARCH_powerpc |
363 | case bfd_arch_powerpc: | |
52fe4420 AM |
364 | #endif |
365 | #ifdef ARCH_rs6000 | |
366 | case bfd_arch_rs6000: | |
367 | #endif | |
368 | #if defined ARCH_powerpc || defined ARCH_rs6000 | |
003ca0fd | 369 | if (big) |
252b5132 RH |
370 | disassemble = print_insn_big_powerpc; |
371 | else | |
372 | disassemble = print_insn_little_powerpc; | |
373 | break; | |
374 | #endif | |
11146849 DD |
375 | #ifdef ARCH_pru |
376 | case bfd_arch_pru: | |
377 | disassemble = print_insn_pru; | |
378 | break; | |
379 | #endif | |
e23eba97 NC |
380 | #ifdef ARCH_riscv |
381 | case bfd_arch_riscv: | |
382 | disassemble = print_insn_riscv; | |
ae4c0df4 | 383 | break; |
e23eba97 | 384 | #endif |
99c513f6 DD |
385 | #ifdef ARCH_rl78 |
386 | case bfd_arch_rl78: | |
0952813b | 387 | disassemble = rl78_get_disassembler (abfd); |
99c513f6 DD |
388 | break; |
389 | #endif | |
c7927a3c NC |
390 | #ifdef ARCH_rx |
391 | case bfd_arch_rx: | |
392 | disassemble = print_insn_rx; | |
393 | break; | |
394 | #endif | |
a85d7ed0 NC |
395 | #ifdef ARCH_s390 |
396 | case bfd_arch_s390: | |
397 | disassemble = print_insn_s390; | |
398 | break; | |
399 | #endif | |
1c0d3aa6 NC |
400 | #ifdef ARCH_score |
401 | case bfd_arch_score: | |
003ca0fd | 402 | if (big) |
6ca4eb77 | 403 | disassemble = print_insn_big_score; |
1c0d3aa6 | 404 | else |
6ca4eb77 | 405 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
406 | break; |
407 | #endif | |
252b5132 RH |
408 | #ifdef ARCH_sh |
409 | case bfd_arch_sh: | |
1c509ca8 | 410 | disassemble = print_insn_sh; |
252b5132 RH |
411 | break; |
412 | #endif | |
413 | #ifdef ARCH_sparc | |
414 | case bfd_arch_sparc: | |
415 | disassemble = print_insn_sparc; | |
416 | break; | |
417 | #endif | |
e9f53129 AM |
418 | #ifdef ARCH_spu |
419 | case bfd_arch_spu: | |
420 | disassemble = print_insn_spu; | |
421 | break; | |
422 | #endif | |
252b5132 RH |
423 | #ifdef ARCH_tic30 |
424 | case bfd_arch_tic30: | |
425 | disassemble = print_insn_tic30; | |
426 | break; | |
427 | #endif | |
026df7c5 NC |
428 | #ifdef ARCH_tic4x |
429 | case bfd_arch_tic4x: | |
430 | disassemble = print_insn_tic4x; | |
431 | break; | |
432 | #endif | |
5c84d377 TW |
433 | #ifdef ARCH_tic54x |
434 | case bfd_arch_tic54x: | |
435 | disassemble = print_insn_tic54x; | |
436 | break; | |
437 | #endif | |
40b36596 JM |
438 | #ifdef ARCH_tic6x |
439 | case bfd_arch_tic6x: | |
440 | disassemble = print_insn_tic6x; | |
441 | break; | |
442 | #endif | |
252b5132 RH |
443 | #ifdef ARCH_tic80 |
444 | case bfd_arch_tic80: | |
445 | disassemble = print_insn_tic80; | |
446 | break; | |
447 | #endif | |
3f8107ab AM |
448 | #ifdef ARCH_ft32 |
449 | case bfd_arch_ft32: | |
450 | disassemble = print_insn_ft32; | |
451 | break; | |
452 | #endif | |
252b5132 RH |
453 | #ifdef ARCH_v850 |
454 | case bfd_arch_v850: | |
de863c74 | 455 | case bfd_arch_v850_rh850: |
252b5132 RH |
456 | disassemble = print_insn_v850; |
457 | break; | |
458 | #endif | |
62ecb94c PC |
459 | #ifdef ARCH_wasm32 |
460 | case bfd_arch_wasm32: | |
461 | disassemble = print_insn_wasm32; | |
462 | break; | |
463 | #endif | |
f6c1a2d5 NC |
464 | #ifdef ARCH_xgate |
465 | case bfd_arch_xgate: | |
466 | disassemble = print_insn_xgate; | |
467 | break; | |
468 | #endif | |
93fbbb04 GK |
469 | #ifdef ARCH_xstormy16 |
470 | case bfd_arch_xstormy16: | |
471 | disassemble = print_insn_xstormy16; | |
472 | break; | |
473 | #endif | |
d70c5fc7 NC |
474 | #ifdef ARCH_xc16x |
475 | case bfd_arch_xc16x: | |
476 | disassemble = print_insn_xc16x; | |
477 | break; | |
478 | #endif | |
e0001a05 NC |
479 | #ifdef ARCH_xtensa |
480 | case bfd_arch_xtensa: | |
481 | disassemble = print_insn_xtensa; | |
482 | break; | |
483 | #endif | |
3c9b82ba NC |
484 | #ifdef ARCH_z80 |
485 | case bfd_arch_z80: | |
486 | disassemble = print_insn_z80; | |
487 | break; | |
488 | #endif | |
252b5132 RH |
489 | #ifdef ARCH_z8k |
490 | case bfd_arch_z8k: | |
003ca0fd | 491 | if (mach == bfd_mach_z8001) |
252b5132 | 492 | disassemble = print_insn_z8001; |
b7ed8fad | 493 | else |
252b5132 RH |
494 | disassemble = print_insn_z8002; |
495 | break; | |
496 | #endif | |
497 | #ifdef ARCH_vax | |
498 | case bfd_arch_vax: | |
499 | disassemble = print_insn_vax; | |
500 | break; | |
fd3c93d5 | 501 | #endif |
1945cfa5 EB |
502 | #ifdef ARCH_visium |
503 | case bfd_arch_visium: | |
504 | disassemble = print_insn_visium; | |
505 | break; | |
506 | #endif | |
fd3c93d5 DB |
507 | #ifdef ARCH_frv |
508 | case bfd_arch_frv: | |
509 | disassemble = print_insn_frv; | |
510 | break; | |
47b1a55a | 511 | #endif |
59b1530d AG |
512 | #ifdef ARCH_moxie |
513 | case bfd_arch_moxie: | |
514 | disassemble = print_insn_moxie; | |
515 | break; | |
516 | #endif | |
47b1a55a SC |
517 | #ifdef ARCH_iq2000 |
518 | case bfd_arch_iq2000: | |
519 | disassemble = print_insn_iq2000; | |
520 | break; | |
49f58d10 JB |
521 | #endif |
522 | #ifdef ARCH_m32c | |
523 | case bfd_arch_m32c: | |
524 | disassemble = print_insn_m32c; | |
525 | break; | |
aa137e4d NC |
526 | #endif |
527 | #ifdef ARCH_tilegx | |
528 | case bfd_arch_tilegx: | |
529 | disassemble = print_insn_tilegx; | |
530 | break; | |
531 | #endif | |
532 | #ifdef ARCH_tilepro | |
533 | case bfd_arch_tilepro: | |
534 | disassemble = print_insn_tilepro; | |
535 | break; | |
252b5132 RH |
536 | #endif |
537 | default: | |
538 | return 0; | |
539 | } | |
540 | return disassemble; | |
541 | } | |
94470b23 NC |
542 | |
543 | void | |
e6c7cdec | 544 | disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) |
94470b23 | 545 | { |
a06ea964 NC |
546 | #ifdef ARCH_aarch64 |
547 | print_aarch64_disassembler_options (stream); | |
548 | #endif | |
37fd5ef3 CZ |
549 | #ifdef ARCH_arc |
550 | print_arc_disassembler_options (stream); | |
551 | #endif | |
58efb6c0 NC |
552 | #ifdef ARCH_arm |
553 | print_arm_disassembler_options (stream); | |
554 | #endif | |
640c0ccd CD |
555 | #ifdef ARCH_mips |
556 | print_mips_disassembler_options (stream); | |
557 | #endif | |
fe944acf FT |
558 | #ifdef ARCH_nfp |
559 | print_nfp_disassembler_options (stream); | |
560 | #endif | |
07dd56a9 NC |
561 | #ifdef ARCH_powerpc |
562 | print_ppc_disassembler_options (stream); | |
563 | #endif | |
e23eba97 NC |
564 | #ifdef ARCH_riscv |
565 | print_riscv_disassembler_options (stream); | |
566 | #endif | |
f59a29b9 L |
567 | #ifdef ARCH_i386 |
568 | print_i386_disassembler_options (stream); | |
569 | #endif | |
112b7c50 AK |
570 | #ifdef ARCH_s390 |
571 | print_s390_disassembler_options (stream); | |
572 | #endif | |
62ecb94c PC |
573 | #ifdef ARCH_wasm32 |
574 | print_wasm32_disassembler_options (stream); | |
575 | #endif | |
b7ed8fad | 576 | |
94470b23 NC |
577 | return; |
578 | } | |
22a398e1 NC |
579 | |
580 | void | |
581 | disassemble_init_for_target (struct disassemble_info * info) | |
582 | { | |
583 | if (info == NULL) | |
584 | return; | |
585 | ||
586 | switch (info->arch) | |
587 | { | |
a06ea964 NC |
588 | #ifdef ARCH_aarch64 |
589 | case bfd_arch_aarch64: | |
590 | info->symbol_is_valid = aarch64_symbol_is_valid; | |
591 | info->disassembler_needs_relocs = TRUE; | |
592 | break; | |
593 | #endif | |
22a398e1 NC |
594 | #ifdef ARCH_arm |
595 | case bfd_arch_arm: | |
596 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 597 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 598 | break; |
0bcb06d2 | 599 | #endif |
b8891f8d AJ |
600 | #ifdef ARCH_csky |
601 | case bfd_arch_csky: | |
602 | info->symbol_is_valid = csky_symbol_is_valid; | |
603 | info->disassembler_needs_relocs = TRUE; | |
604 | break; | |
605 | #endif | |
606 | ||
0bcb06d2 AS |
607 | #ifdef ARCH_ia64 |
608 | case bfd_arch_ia64: | |
609 | info->skip_zeroes = 16; | |
610 | break; | |
611 | #endif | |
612 | #ifdef ARCH_tic4x | |
613 | case bfd_arch_tic4x: | |
614 | info->skip_zeroes = 32; | |
fb53f5a8 | 615 | break; |
49f58d10 | 616 | #endif |
bd2f2e55 DB |
617 | #ifdef ARCH_mep |
618 | case bfd_arch_mep: | |
619 | info->skip_zeroes = 256; | |
620 | info->skip_zeroes_at_end = 0; | |
621 | break; | |
622 | #endif | |
a3c62988 NC |
623 | #ifdef ARCH_metag |
624 | case bfd_arch_metag: | |
625 | info->disassembler_needs_relocs = TRUE; | |
626 | break; | |
627 | #endif | |
49f58d10 JB |
628 | #ifdef ARCH_m32c |
629 | case bfd_arch_m32c: | |
6ca4eb77 AM |
630 | /* This processor in fact is little endian. The value set here |
631 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 632 | info->endian = BFD_ENDIAN_BIG; |
fb53f5a8 DB |
633 | if (! info->insn_sets) |
634 | { | |
635 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
636 | if (info->mach == bfd_mach_m16c) | |
637 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
638 | else | |
639 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
640 | } | |
49f58d10 | 641 | break; |
b240011a | 642 | #endif |
024d185c DD |
643 | #ifdef ARCH_pru |
644 | case bfd_arch_pru: | |
645 | info->disassembler_needs_relocs = TRUE; | |
646 | break; | |
647 | #endif | |
fbc22555 DD |
648 | #ifdef ARCH_powerpc |
649 | case bfd_arch_powerpc: | |
650 | #endif | |
b240011a AM |
651 | #ifdef ARCH_rs6000 |
652 | case bfd_arch_rs6000: | |
653 | #endif | |
654 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
655 | disassemble_init_powerpc (info); | |
656 | break; | |
65b48a81 | 657 | #endif |
62ecb94c PC |
658 | #ifdef ARCH_wasm32 |
659 | case bfd_arch_wasm32: | |
660 | disassemble_init_wasm32 (info); | |
661 | break; | |
662 | #endif | |
65b48a81 PB |
663 | #ifdef ARCH_s390 |
664 | case bfd_arch_s390: | |
665 | disassemble_init_s390 (info); | |
666 | break; | |
22a398e1 NC |
667 | #endif |
668 | default: | |
669 | break; | |
670 | } | |
671 | } | |
65b48a81 PB |
672 | |
673 | /* Remove whitespace and consecutive commas from OPTIONS. */ | |
674 | ||
675 | char * | |
676 | remove_whitespace_and_extra_commas (char *options) | |
677 | { | |
678 | char *str; | |
679 | size_t i, len; | |
680 | ||
681 | if (options == NULL) | |
682 | return NULL; | |
683 | ||
684 | /* Strip off all trailing whitespace and commas. */ | |
685 | for (len = strlen (options); len > 0; len--) | |
686 | { | |
687 | if (!ISSPACE (options[len - 1]) && options[len - 1] != ',') | |
688 | break; | |
689 | options[len - 1] = '\0'; | |
690 | } | |
691 | ||
692 | /* Convert all remaining whitespace to commas. */ | |
693 | for (i = 0; options[i] != '\0'; i++) | |
694 | if (ISSPACE (options[i])) | |
695 | options[i] = ','; | |
696 | ||
697 | /* Remove consecutive commas. */ | |
698 | for (str = options; *str != '\0'; str++) | |
699 | if (*str == ',' && (*(str + 1) == ',' || str == options)) | |
700 | { | |
701 | char *next = str + 1; | |
702 | while (*next == ',') | |
703 | next++; | |
704 | len = strlen (next); | |
705 | if (str != options) | |
706 | str++; | |
707 | memmove (str, next, len); | |
708 | next[len - (size_t)(next - str)] = '\0'; | |
709 | } | |
710 | return (strlen (options) != 0) ? options : NULL; | |
711 | } | |
712 | ||
713 | /* Like STRCMP, but treat ',' the same as '\0' so that we match | |
714 | strings like "foobar" against "foobar,xxyyzz,...". */ | |
715 | ||
716 | int | |
717 | disassembler_options_cmp (const char *s1, const char *s2) | |
718 | { | |
719 | unsigned char c1, c2; | |
720 | ||
721 | do | |
722 | { | |
723 | c1 = (unsigned char) *s1++; | |
724 | if (c1 == ',') | |
725 | c1 = '\0'; | |
726 | c2 = (unsigned char) *s2++; | |
727 | if (c2 == ',') | |
728 | c2 = '\0'; | |
729 | if (c1 == '\0') | |
730 | return c1 - c2; | |
731 | } | |
732 | while (c1 == c2); | |
733 | ||
734 | return c1 - c2; | |
735 | } |