projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
daily update
[deliverable/binutils-gdb.git] / opcodes / fr30-desc.c
CommitLineData
252b5132
RH		 1/* CPU data for fr30.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
9a2e995d 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
252b5132
RH		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
252b5132
RH		 26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "fr30-desc.h"
32#include "fr30-opc.h"
33#include "opintl.h"
6bb95a0f 34#include "libiberty.h"
98f70fc4 35#include "xregex.h"
252b5132
RH		 36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] =
47{
48 { "base", MACH_BASE },
49 { "fr30", MACH_FR30 },
50 { "max", MACH_MAX },
51 { 0, 0 }
52};
53
54static const CGEN_ATTR_ENTRY ISA_attr[] =
55{
56 { "fr30", ISA_FR30 },
57 { "max", ISA_MAX },
58 { 0, 0 }
59};
60
61const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
62{
6bb95a0f 63 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 64 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "RESERVED", &bool_attr[0], &bool_attr[0] },
68 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69 { "SIGNED", &bool_attr[0], &bool_attr[0] },
70 { 0, 0, 0 }
71};
72
73const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
74{
6bb95a0f 75 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 76 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78 { "PC", &bool_attr[0], &bool_attr[0] },
79 { "PROFILE", &bool_attr[0], &bool_attr[0] },
80 { 0, 0, 0 }
81};
82
83const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
84{
6bb95a0f 85 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 86 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90 { "SIGNED", &bool_attr[0], &bool_attr[0] },
91 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92 { "RELAX", &bool_attr[0], &bool_attr[0] },
93 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
95 { 0, 0, 0 }
96};
97
98const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
99{
6bb95a0f 100 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 101 { "ALIAS", &bool_attr[0], &bool_attr[0] },
102 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108 { "RELAX", &bool_attr[0], &bool_attr[0] },
109 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110 { "PBB", &bool_attr[0], &bool_attr[0] },
111 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 { 0, 0, 0 }
113};
114
115/* Instruction set variants. */
116
117static const CGEN_ISA fr30_cgen_isa_table[] = {
6bb95a0f
DB		 118 { "fr30", 16, 16, 16, 48 },
119 { 0, 0, 0, 0, 0 }
252b5132
RH		 120};
121
122/* Machine variants. */
123
124static const CGEN_MACH fr30_cgen_mach_table[] = {
fc7bc883
RH		 125 { "fr30", "fr30", MACH_FR30, 0 },
126 { 0, 0, 0, 0 }
252b5132
RH		 127};
128
129static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
130{
6bb95a0f
DB		 131 { "r0", 0, {0, {0}}, 0, 0 },
132 { "r1", 1, {0, {0}}, 0, 0 },
133 { "r2", 2, {0, {0}}, 0, 0 },
134 { "r3", 3, {0, {0}}, 0, 0 },
135 { "r4", 4, {0, {0}}, 0, 0 },
136 { "r5", 5, {0, {0}}, 0, 0 },
137 { "r6", 6, {0, {0}}, 0, 0 },
138 { "r7", 7, {0, {0}}, 0, 0 },
139 { "r8", 8, {0, {0}}, 0, 0 },
140 { "r9", 9, {0, {0}}, 0, 0 },
141 { "r10", 10, {0, {0}}, 0, 0 },
142 { "r11", 11, {0, {0}}, 0, 0 },
143 { "r12", 12, {0, {0}}, 0, 0 },
144 { "r13", 13, {0, {0}}, 0, 0 },
145 { "r14", 14, {0, {0}}, 0, 0 },
146 { "r15", 15, {0, {0}}, 0, 0 },
147 { "ac", 13, {0, {0}}, 0, 0 },
148 { "fp", 14, {0, {0}}, 0, 0 },
149 { "sp", 15, {0, {0}}, 0, 0 }
252b5132
RH		 150};
151
152CGEN_KEYWORD fr30_cgen_opval_gr_names =
153{
154 & fr30_cgen_opval_gr_names_entries[0],
6bb95a0f 155 19,
fc7bc883 156 0, 0, 0, 0, ""
252b5132
RH		 157};
158
159static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
160{
6bb95a0f
DB		 161 { "cr0", 0, {0, {0}}, 0, 0 },
162 { "cr1", 1, {0, {0}}, 0, 0 },
163 { "cr2", 2, {0, {0}}, 0, 0 },
164 { "cr3", 3, {0, {0}}, 0, 0 },
165 { "cr4", 4, {0, {0}}, 0, 0 },
166 { "cr5", 5, {0, {0}}, 0, 0 },
167 { "cr6", 6, {0, {0}}, 0, 0 },
168 { "cr7", 7, {0, {0}}, 0, 0 },
169 { "cr8", 8, {0, {0}}, 0, 0 },
170 { "cr9", 9, {0, {0}}, 0, 0 },
171 { "cr10", 10, {0, {0}}, 0, 0 },
172 { "cr11", 11, {0, {0}}, 0, 0 },
173 { "cr12", 12, {0, {0}}, 0, 0 },
174 { "cr13", 13, {0, {0}}, 0, 0 },
175 { "cr14", 14, {0, {0}}, 0, 0 },
176 { "cr15", 15, {0, {0}}, 0, 0 }
252b5132
RH		 177};
178
179CGEN_KEYWORD fr30_cgen_opval_cr_names =
180{
181 & fr30_cgen_opval_cr_names_entries[0],
6bb95a0f 182 16,
fc7bc883 183 0, 0, 0, 0, ""
252b5132
RH		 184};
185
186static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
187{
6bb95a0f
DB		 188 { "tbr", 0, {0, {0}}, 0, 0 },
189 { "rp", 1, {0, {0}}, 0, 0 },
190 { "ssp", 2, {0, {0}}, 0, 0 },
191 { "usp", 3, {0, {0}}, 0, 0 },
192 { "mdh", 4, {0, {0}}, 0, 0 },
193 { "mdl", 5, {0, {0}}, 0, 0 }
252b5132
RH		 194};
195
196CGEN_KEYWORD fr30_cgen_opval_dr_names =
197{
198 & fr30_cgen_opval_dr_names_entries[0],
6bb95a0f 199 6,
fc7bc883 200 0, 0, 0, 0, ""
252b5132
RH		 201};
202
203static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
204{
6bb95a0f 205 { "ps", 0, {0, {0}}, 0, 0 }
252b5132
RH		 206};
207
208CGEN_KEYWORD fr30_cgen_opval_h_ps =
209{
210 & fr30_cgen_opval_h_ps_entries[0],
6bb95a0f 211 1,
fc7bc883 212 0, 0, 0, 0, ""
252b5132
RH		 213};
214
215static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
216{
6bb95a0f 217 { "r13", 0, {0, {0}}, 0, 0 }
252b5132
RH		 218};
219
220CGEN_KEYWORD fr30_cgen_opval_h_r13 =
221{
222 & fr30_cgen_opval_h_r13_entries[0],
6bb95a0f 223 1,
fc7bc883 224 0, 0, 0, 0, ""
252b5132
RH		 225};
226
227static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
228{
6bb95a0f 229 { "r14", 0, {0, {0}}, 0, 0 }
252b5132
RH		 230};
231
232CGEN_KEYWORD fr30_cgen_opval_h_r14 =
233{
234 & fr30_cgen_opval_h_r14_entries[0],
6bb95a0f 235 1,
fc7bc883 236 0, 0, 0, 0, ""
252b5132
RH		 237};
238
239static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
240{
6bb95a0f 241 { "r15", 0, {0, {0}}, 0, 0 }
252b5132
RH		 242};
243
244CGEN_KEYWORD fr30_cgen_opval_h_r15 =
245{
246 & fr30_cgen_opval_h_r15_entries[0],
6bb95a0f 247 1,
fc7bc883 248 0, 0, 0, 0, ""
252b5132
RH		 249};
250
251
252b5132
RH		 252/* The hardware table. */
253
b3466c39
DB		 254#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
255#define A(a) (1 << CGEN_HW_##a)
256#else
257#define A(a) (1 << CGEN_HW_/**/a)
258#endif
252b5132
RH		 259
260const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
261{
262 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
263 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
264 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
265 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
266 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
267 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
268 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
269 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
270 { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
271 { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
272 { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
273 { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
274 { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
275 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
276 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
277 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
278 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
279 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
280 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
281 { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
282 { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
283 { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
284 { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
285 { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
286 { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 287 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
252b5132
RH		 288};
289
290#undef A
291
b3466c39 292
252b5132
RH		 293/* The instruction field table. */
294
b3466c39
DB		 295#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
296#define A(a) (1 << CGEN_IFLD_##a)
297#else
298#define A(a) (1 << CGEN_IFLD_/**/a)
299#endif
252b5132
RH		 300
301const CGEN_IFLD fr30_cgen_ifld_table[] =
302{
303 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 304 { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
252b5132
RH		 305 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } },
306 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
307 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
308 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
309 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } } },
310 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
311 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } } },
312 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
313 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
314 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
315 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
316 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
317 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
318 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
319 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
320 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
321 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
322 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
323 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
324 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
325 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
326 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
327 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } } },
328 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
329 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
330 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
331 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
332 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
333 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
334 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
335 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
336 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
337 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
338 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
339 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
340 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
341 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
342 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
343 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 344 { 0, 0, 0, 0, 0, 0, {0, {0}} }
252b5132
RH		 345};
346
347#undef A
348
b3466c39 349
9a2e995d
GH		 350
351/* multi ifield declarations */
352
353const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
354
355
356/* multi ifield definitions */
357
358const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
359{
98f70fc4
AM		 360 { 0, { (const PTR) &fr30_cgen_ifld_table[23] } },
361 { 0, { (const PTR) &fr30_cgen_ifld_table[24] } },
362 { 0, { (const PTR) 0 } }
9a2e995d
GH		 363};
364
252b5132
RH		 365/* The operand table. */
366
b3466c39
DB		 367#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
368#define A(a) (1 << CGEN_OPERAND_##a)
369#else
370#define A(a) (1 << CGEN_OPERAND_/**/a)
371#endif
372#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
373#define OPERAND(op) FR30_OPERAND_##op
374#else
375#define OPERAND(op) FR30_OPERAND_/**/op
376#endif
252b5132
RH		 377
378const CGEN_OPERAND fr30_cgen_operand_table[] =
379{
380/* pc: program counter */
381 { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
98f70fc4 382 { 0, { (const PTR) &fr30_cgen_ifld_table[0] } },
252b5132
RH		 383 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
384/* Ri: destination register */
385 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
98f70fc4 386 { 0, { (const PTR) &fr30_cgen_ifld_table[10] } },
252b5132
RH		 387 { 0, { (1<<MACH_BASE) } } },
388/* Rj: source register */
389 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
98f70fc4 390 { 0, { (const PTR) &fr30_cgen_ifld_table[9] } },
252b5132
RH		 391 { 0, { (1<<MACH_BASE) } } },
392/* Ric: target register coproc insn */
393 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
98f70fc4 394 { 0, { (const PTR) &fr30_cgen_ifld_table[14] } },
252b5132
RH		 395 { 0, { (1<<MACH_BASE) } } },
396/* Rjc: source register coproc insn */
397 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
98f70fc4 398 { 0, { (const PTR) &fr30_cgen_ifld_table[13] } },
252b5132
RH		 399 { 0, { (1<<MACH_BASE) } } },
400/* CRi: coprocessor register */
401 { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
98f70fc4 402 { 0, { (const PTR) &fr30_cgen_ifld_table[16] } },
252b5132
RH		 403 { 0, { (1<<MACH_BASE) } } },
404/* CRj: coprocessor register */
405 { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
98f70fc4 406 { 0, { (const PTR) &fr30_cgen_ifld_table[15] } },
252b5132
RH		 407 { 0, { (1<<MACH_BASE) } } },
408/* Rs1: dedicated register */
409 { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
98f70fc4 410 { 0, { (const PTR) &fr30_cgen_ifld_table[11] } },
252b5132
RH		 411 { 0, { (1<<MACH_BASE) } } },
412/* Rs2: dedicated register */
413 { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
98f70fc4 414 { 0, { (const PTR) &fr30_cgen_ifld_table[12] } },
252b5132
RH		 415 { 0, { (1<<MACH_BASE) } } },
416/* R13: General Register 13 */
417 { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
98f70fc4 418 { 0, { (const PTR) 0 } },
252b5132
RH		 419 { 0, { (1<<MACH_BASE) } } },
420/* R14: General Register 14 */
421 { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
98f70fc4 422 { 0, { (const PTR) 0 } },
252b5132
RH		 423 { 0, { (1<<MACH_BASE) } } },
424/* R15: General Register 15 */
425 { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
98f70fc4 426 { 0, { (const PTR) 0 } },
252b5132
RH		 427 { 0, { (1<<MACH_BASE) } } },
428/* ps: Program Status register */
429 { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
98f70fc4 430 { 0, { (const PTR) 0 } },
252b5132
RH		 431 { 0, { (1<<MACH_BASE) } } },
432/* u4: 4 bit unsigned immediate */
433 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
98f70fc4 434 { 0, { (const PTR) &fr30_cgen_ifld_table[17] } },
252b5132
RH		 435 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
436/* u4c: 4 bit unsigned immediate */
437 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
98f70fc4 438 { 0, { (const PTR) &fr30_cgen_ifld_table[18] } },
252b5132
RH		 439 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
440/* u8: 8 bit unsigned immediate */
441 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
98f70fc4 442 { 0, { (const PTR) &fr30_cgen_ifld_table[21] } },
252b5132
RH		 443 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
444/* i8: 8 bit unsigned immediate */
445 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
98f70fc4 446 { 0, { (const PTR) &fr30_cgen_ifld_table[22] } },
252b5132
RH		 447 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
448/* udisp6: 6 bit unsigned immediate */
449 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
98f70fc4 450 { 0, { (const PTR) &fr30_cgen_ifld_table[26] } },
252b5132
RH		 451 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
452/* disp8: 8 bit signed immediate */
453 { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
98f70fc4 454 { 0, { (const PTR) &fr30_cgen_ifld_table[27] } },
252b5132
RH		 455 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
456/* disp9: 9 bit signed immediate */
457 { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
98f70fc4 458 { 0, { (const PTR) &fr30_cgen_ifld_table[28] } },
252b5132
RH		 459 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
460/* disp10: 10 bit signed immediate */
461 { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
98f70fc4 462 { 0, { (const PTR) &fr30_cgen_ifld_table[29] } },
252b5132
RH		 463 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
464/* s10: 10 bit signed immediate */
465 { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
98f70fc4 466 { 0, { (const PTR) &fr30_cgen_ifld_table[30] } },
252b5132
RH		 467 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
468/* u10: 10 bit unsigned immediate */
469 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
98f70fc4 470 { 0, { (const PTR) &fr30_cgen_ifld_table[31] } },
252b5132
RH		 471 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
472/* i32: 32 bit immediate */
473 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
98f70fc4 474 { 0, { (const PTR) &fr30_cgen_ifld_table[25] } },
252b5132
RH		 475 { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
476/* m4: 4 bit negative immediate */
477 { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
98f70fc4 478 { 0, { (const PTR) &fr30_cgen_ifld_table[20] } },
252b5132
RH		 479 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
480/* i20: 20 bit immediate */
481 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
98f70fc4 482 { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
252b5132
RH		 483 { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
484/* dir8: 8 bit direct address */
485 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
98f70fc4 486 { 0, { (const PTR) &fr30_cgen_ifld_table[33] } },
252b5132
RH		 487 { 0, { (1<<MACH_BASE) } } },
488/* dir9: 9 bit direct address */
489 { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
98f70fc4 490 { 0, { (const PTR) &fr30_cgen_ifld_table[34] } },
252b5132
RH		 491 { 0, { (1<<MACH_BASE) } } },
492/* dir10: 10 bit direct address */
493 { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
98f70fc4 494 { 0, { (const PTR) &fr30_cgen_ifld_table[35] } },
252b5132
RH		 495 { 0, { (1<<MACH_BASE) } } },
496/* label9: 9 bit pc relative address */
497 { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
98f70fc4 498 { 0, { (const PTR) &fr30_cgen_ifld_table[32] } },
252b5132
RH		 499 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
500/* label12: 12 bit pc relative address */
501 { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
98f70fc4 502 { 0, { (const PTR) &fr30_cgen_ifld_table[36] } },
252b5132
RH		 503 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
504/* reglist_low_ld: 8 bit low register mask for ldm */
505 { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
98f70fc4 506 { 0, { (const PTR) &fr30_cgen_ifld_table[40] } },
252b5132
RH		 507 { 0, { (1<<MACH_BASE) } } },
508/* reglist_hi_ld: 8 bit high register mask for ldm */
509 { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
98f70fc4 510 { 0, { (const PTR) &fr30_cgen_ifld_table[39] } },
252b5132
RH		 511 { 0, { (1<<MACH_BASE) } } },
512/* reglist_low_st: 8 bit low register mask for stm */
513 { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
98f70fc4 514 { 0, { (const PTR) &fr30_cgen_ifld_table[38] } },
252b5132
RH		 515 { 0, { (1<<MACH_BASE) } } },
516/* reglist_hi_st: 8 bit high register mask for stm */
517 { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
98f70fc4 518 { 0, { (const PTR) &fr30_cgen_ifld_table[37] } },
252b5132
RH		 519 { 0, { (1<<MACH_BASE) } } },
520/* cc: condition codes */
521 { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
98f70fc4 522 { 0, { (const PTR) &fr30_cgen_ifld_table[7] } },
252b5132
RH		 523 { 0, { (1<<MACH_BASE) } } },
524/* ccc: coprocessor calc */
525 { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
98f70fc4 526 { 0, { (const PTR) &fr30_cgen_ifld_table[8] } },
252b5132
RH		 527 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
528/* nbit: negative bit */
529 { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
98f70fc4 530 { 0, { (const PTR) 0 } },
252b5132
RH		 531 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
532/* vbit: overflow bit */
533 { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
98f70fc4 534 { 0, { (const PTR) 0 } },
252b5132
RH		 535 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
536/* zbit: zero bit */
537 { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
98f70fc4 538 { 0, { (const PTR) 0 } },
252b5132
RH		 539 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
540/* cbit: carry bit */
541 { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
98f70fc4 542 { 0, { (const PTR) 0 } },
252b5132
RH		 543 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
544/* ibit: interrupt bit */
545 { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
98f70fc4 546 { 0, { (const PTR) 0 } },
252b5132
RH		 547 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
548/* sbit: stack bit */
549 { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
98f70fc4 550 { 0, { (const PTR) 0 } },
252b5132
RH		 551 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
552/* tbit: trace trap bit */
553 { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
98f70fc4 554 { 0, { (const PTR) 0 } },
252b5132
RH		 555 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
556/* d0bit: division 0 bit */
557 { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
98f70fc4 558 { 0, { (const PTR) 0 } },
252b5132
RH		 559 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
560/* d1bit: division 1 bit */
561 { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
98f70fc4 562 { 0, { (const PTR) 0 } },
252b5132
RH		 563 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
564/* ccr: condition code bits */
565 { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
98f70fc4 566 { 0, { (const PTR) 0 } },
252b5132
RH		 567 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
568/* scr: system condition bits */
569 { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
98f70fc4 570 { 0, { (const PTR) 0 } },
252b5132
RH		 571 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
572/* ilm: interrupt level mask */
573 { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
98f70fc4 574 { 0, { (const PTR) 0 } },
252b5132 575 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
98f70fc4
AM		 576/* sentinel */
577 { 0, 0, 0, 0, 0,
578 { 0, { (const PTR) 0 } },
579 { 0, { 0 } } }
252b5132
RH		 580};
581
582#undef A
583
252b5132
RH		 584
585/* The instruction table. */
586
b3466c39
DB		 587#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
588#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
589#define A(a) (1 << CGEN_INSN_##a)
590#else
591#define A(a) (1 << CGEN_INSN_/**/a)
592#endif
593
252b5132
RH		 594static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
595{
596 /* Special null first entry.
597 A `num' value of zero is thus invalid.
598 Also, the special `invalid' insn resides here. */
6bb95a0f 599 { 0, 0, 0, 0, {0, {0}} },
252b5132
RH		 600/* add $Rj,$Ri */
601 {
602 FR30_INSN_ADD, "add", "add", 16,
603 { 0, { (1<<MACH_BASE) } }
604 },
605/* add $u4,$Ri */
606 {
607 FR30_INSN_ADDI, "addi", "add", 16,
608 { 0, { (1<<MACH_BASE) } }
609 },
610/* add2 $m4,$Ri */
611 {
612 FR30_INSN_ADD2, "add2", "add2", 16,
613 { 0, { (1<<MACH_BASE) } }
614 },
615/* addc $Rj,$Ri */
616 {
617 FR30_INSN_ADDC, "addc", "addc", 16,
618 { 0, { (1<<MACH_BASE) } }
619 },
620/* addn $Rj,$Ri */
621 {
622 FR30_INSN_ADDN, "addn", "addn", 16,
623 { 0, { (1<<MACH_BASE) } }
624 },
625/* addn $u4,$Ri */
626 {
627 FR30_INSN_ADDNI, "addni", "addn", 16,
628 { 0, { (1<<MACH_BASE) } }
629 },
630/* addn2 $m4,$Ri */
631 {
632 FR30_INSN_ADDN2, "addn2", "addn2", 16,
633 { 0, { (1<<MACH_BASE) } }
634 },
635/* sub $Rj,$Ri */
636 {
637 FR30_INSN_SUB, "sub", "sub", 16,
638 { 0, { (1<<MACH_BASE) } }
639 },
640/* subc $Rj,$Ri */
641 {
642 FR30_INSN_SUBC, "subc", "subc", 16,
643 { 0, { (1<<MACH_BASE) } }
644 },
645/* subn $Rj,$Ri */
646 {
647 FR30_INSN_SUBN, "subn", "subn", 16,
648 { 0, { (1<<MACH_BASE) } }
649 },
650/* cmp $Rj,$Ri */
651 {
652 FR30_INSN_CMP, "cmp", "cmp", 16,
653 { 0, { (1<<MACH_BASE) } }
654 },
655/* cmp $u4,$Ri */
656 {
657 FR30_INSN_CMPI, "cmpi", "cmp", 16,
658 { 0, { (1<<MACH_BASE) } }
659 },
660/* cmp2 $m4,$Ri */
661 {
662 FR30_INSN_CMP2, "cmp2", "cmp2", 16,
663 { 0, { (1<<MACH_BASE) } }
664 },
665/* and $Rj,$Ri */
666 {
667 FR30_INSN_AND, "and", "and", 16,
668 { 0, { (1<<MACH_BASE) } }
669 },
670/* or $Rj,$Ri */
671 {
672 FR30_INSN_OR, "or", "or", 16,
673 { 0, { (1<<MACH_BASE) } }
674 },
675/* eor $Rj,$Ri */
676 {
677 FR30_INSN_EOR, "eor", "eor", 16,
678 { 0, { (1<<MACH_BASE) } }
679 },
680/* and $Rj,@$Ri */
681 {
682 FR30_INSN_ANDM, "andm", "and", 16,
683 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
684 },
685/* andh $Rj,@$Ri */
686 {
687 FR30_INSN_ANDH, "andh", "andh", 16,
688 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
689 },
690/* andb $Rj,@$Ri */
691 {
692 FR30_INSN_ANDB, "andb", "andb", 16,
693 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
694 },
695/* or $Rj,@$Ri */
696 {
697 FR30_INSN_ORM, "orm", "or", 16,
698 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
699 },
700/* orh $Rj,@$Ri */
701 {
702 FR30_INSN_ORH, "orh", "orh", 16,
703 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
704 },
705/* orb $Rj,@$Ri */
706 {
707 FR30_INSN_ORB, "orb", "orb", 16,
708 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
709 },
710/* eor $Rj,@$Ri */
711 {
712 FR30_INSN_EORM, "eorm", "eor", 16,
713 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
714 },
715/* eorh $Rj,@$Ri */
716 {
717 FR30_INSN_EORH, "eorh", "eorh", 16,
718 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
719 },
720/* eorb $Rj,@$Ri */
721 {
722 FR30_INSN_EORB, "eorb", "eorb", 16,
723 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
724 },
725/* bandl $u4,@$Ri */
726 {
727 FR30_INSN_BANDL, "bandl", "bandl", 16,
728 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
729 },
730/* borl $u4,@$Ri */
731 {
732 FR30_INSN_BORL, "borl", "borl", 16,
733 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
734 },
735/* beorl $u4,@$Ri */
736 {
737 FR30_INSN_BEORL, "beorl", "beorl", 16,
738 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
739 },
740/* bandh $u4,@$Ri */
741 {
742 FR30_INSN_BANDH, "bandh", "bandh", 16,
743 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
744 },
745/* borh $u4,@$Ri */
746 {
747 FR30_INSN_BORH, "borh", "borh", 16,
748 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
749 },
750/* beorh $u4,@$Ri */
751 {
752 FR30_INSN_BEORH, "beorh", "beorh", 16,
753 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
754 },
755/* btstl $u4,@$Ri */
756 {
757 FR30_INSN_BTSTL, "btstl", "btstl", 16,
758 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
759 },
760/* btsth $u4,@$Ri */
761 {
762 FR30_INSN_BTSTH, "btsth", "btsth", 16,
763 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
764 },
765/* mul $Rj,$Ri */
766 {
767 FR30_INSN_MUL, "mul", "mul", 16,
768 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
769 },
770/* mulu $Rj,$Ri */
771 {
772 FR30_INSN_MULU, "mulu", "mulu", 16,
773 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
774 },
775/* mulh $Rj,$Ri */
776 {
777 FR30_INSN_MULH, "mulh", "mulh", 16,
778 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
779 },
780/* muluh $Rj,$Ri */
781 {
782 FR30_INSN_MULUH, "muluh", "muluh", 16,
783 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
784 },
785/* div0s $Ri */
786 {
787 FR30_INSN_DIV0S, "div0s", "div0s", 16,
788 { 0, { (1<<MACH_BASE) } }
789 },
790/* div0u $Ri */
791 {
792 FR30_INSN_DIV0U, "div0u", "div0u", 16,
793 { 0, { (1<<MACH_BASE) } }
794 },
795/* div1 $Ri */
796 {
797 FR30_INSN_DIV1, "div1", "div1", 16,
798 { 0, { (1<<MACH_BASE) } }
799 },
800/* div2 $Ri */
801 {
802 FR30_INSN_DIV2, "div2", "div2", 16,
803 { 0, { (1<<MACH_BASE) } }
804 },
805/* div3 */
806 {
807 FR30_INSN_DIV3, "div3", "div3", 16,
808 { 0, { (1<<MACH_BASE) } }
809 },
810/* div4s */
811 {
812 FR30_INSN_DIV4S, "div4s", "div4s", 16,
813 { 0, { (1<<MACH_BASE) } }
814 },
815/* lsl $Rj,$Ri */
816 {
817 FR30_INSN_LSL, "lsl", "lsl", 16,
818 { 0, { (1<<MACH_BASE) } }
819 },
820/* lsl $u4,$Ri */
821 {
822 FR30_INSN_LSLI, "lsli", "lsl", 16,
823 { 0, { (1<<MACH_BASE) } }
824 },
825/* lsl2 $u4,$Ri */
826 {
827 FR30_INSN_LSL2, "lsl2", "lsl2", 16,
828 { 0, { (1<<MACH_BASE) } }
829 },
830/* lsr $Rj,$Ri */
831 {
832 FR30_INSN_LSR, "lsr", "lsr", 16,
833 { 0, { (1<<MACH_BASE) } }
834 },
835/* lsr $u4,$Ri */
836 {
837 FR30_INSN_LSRI, "lsri", "lsr", 16,
838 { 0, { (1<<MACH_BASE) } }
839 },
840/* lsr2 $u4,$Ri */
841 {
842 FR30_INSN_LSR2, "lsr2", "lsr2", 16,
843 { 0, { (1<<MACH_BASE) } }
844 },
845/* asr $Rj,$Ri */
846 {
847 FR30_INSN_ASR, "asr", "asr", 16,
848 { 0, { (1<<MACH_BASE) } }
849 },
850/* asr $u4,$Ri */
851 {
852 FR30_INSN_ASRI, "asri", "asr", 16,
853 { 0, { (1<<MACH_BASE) } }
854 },
855/* asr2 $u4,$Ri */
856 {
857 FR30_INSN_ASR2, "asr2", "asr2", 16,
858 { 0, { (1<<MACH_BASE) } }
859 },
860/* ldi:8 $i8,$Ri */
861 {
862 FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
863 { 0, { (1<<MACH_BASE) } }
864 },
865/* ldi:20 $i20,$Ri */
866 {
867 FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
868 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
869 },
870/* ldi:32 $i32,$Ri */
871 {
872 FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
873 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
874 },
875/* ld @$Rj,$Ri */
876 {
877 FR30_INSN_LD, "ld", "ld", 16,
878 { 0, { (1<<MACH_BASE) } }
879 },
880/* lduh @$Rj,$Ri */
881 {
882 FR30_INSN_LDUH, "lduh", "lduh", 16,
883 { 0, { (1<<MACH_BASE) } }
884 },
885/* ldub @$Rj,$Ri */
886 {
887 FR30_INSN_LDUB, "ldub", "ldub", 16,
888 { 0, { (1<<MACH_BASE) } }
889 },
890/* ld @($R13,$Rj),$Ri */
891 {
892 FR30_INSN_LDR13, "ldr13", "ld", 16,
893 { 0, { (1<<MACH_BASE) } }
894 },
895/* lduh @($R13,$Rj),$Ri */
896 {
897 FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
898 { 0, { (1<<MACH_BASE) } }
899 },
900/* ldub @($R13,$Rj),$Ri */
901 {
902 FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
903 { 0, { (1<<MACH_BASE) } }
904 },
905/* ld @($R14,$disp10),$Ri */
906 {
907 FR30_INSN_LDR14, "ldr14", "ld", 16,
908 { 0, { (1<<MACH_BASE) } }
909 },
910/* lduh @($R14,$disp9),$Ri */
911 {
912 FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
913 { 0, { (1<<MACH_BASE) } }
914 },
915/* ldub @($R14,$disp8),$Ri */
916 {
917 FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
918 { 0, { (1<<MACH_BASE) } }
919 },
920/* ld @($R15,$udisp6),$Ri */
921 {
922 FR30_INSN_LDR15, "ldr15", "ld", 16,
923 { 0, { (1<<MACH_BASE) } }
924 },
925/* ld @$R15+,$Ri */
926 {
927 FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
928 { 0, { (1<<MACH_BASE) } }
929 },
930/* ld @$R15+,$Rs2 */
931 {
932 FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
933 { 0, { (1<<MACH_BASE) } }
934 },
935/* ld @$R15+,$ps */
936 {
937 FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
938 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
939 },
940/* st $Ri,@$Rj */
941 {
942 FR30_INSN_ST, "st", "st", 16,
943 { 0, { (1<<MACH_BASE) } }
944 },
945/* sth $Ri,@$Rj */
946 {
947 FR30_INSN_STH, "sth", "sth", 16,
948 { 0, { (1<<MACH_BASE) } }
949 },
950/* stb $Ri,@$Rj */
951 {
952 FR30_INSN_STB, "stb", "stb", 16,
953 { 0, { (1<<MACH_BASE) } }
954 },
955/* st $Ri,@($R13,$Rj) */
956 {
957 FR30_INSN_STR13, "str13", "st", 16,
958 { 0, { (1<<MACH_BASE) } }
959 },
960/* sth $Ri,@($R13,$Rj) */
961 {
962 FR30_INSN_STR13H, "str13h", "sth", 16,
963 { 0, { (1<<MACH_BASE) } }
964 },
965/* stb $Ri,@($R13,$Rj) */
966 {
967 FR30_INSN_STR13B, "str13b", "stb", 16,
968 { 0, { (1<<MACH_BASE) } }
969 },
970/* st $Ri,@($R14,$disp10) */
971 {
972 FR30_INSN_STR14, "str14", "st", 16,
973 { 0, { (1<<MACH_BASE) } }
974 },
975/* sth $Ri,@($R14,$disp9) */
976 {
977 FR30_INSN_STR14H, "str14h", "sth", 16,
978 { 0, { (1<<MACH_BASE) } }
979 },
980/* stb $Ri,@($R14,$disp8) */
981 {
982 FR30_INSN_STR14B, "str14b", "stb", 16,
983 { 0, { (1<<MACH_BASE) } }
984 },
985/* st $Ri,@($R15,$udisp6) */
986 {
987 FR30_INSN_STR15, "str15", "st", 16,
988 { 0, { (1<<MACH_BASE) } }
989 },
990/* st $Ri,@-$R15 */
991 {
992 FR30_INSN_STR15GR, "str15gr", "st", 16,
993 { 0, { (1<<MACH_BASE) } }
994 },
995/* st $Rs2,@-$R15 */
996 {
997 FR30_INSN_STR15DR, "str15dr", "st", 16,
998 { 0, { (1<<MACH_BASE) } }
999 },
1000/* st $ps,@-$R15 */
1001 {
1002 FR30_INSN_STR15PS, "str15ps", "st", 16,
1003 { 0, { (1<<MACH_BASE) } }
1004 },
1005/* mov $Rj,$Ri */
1006 {
1007 FR30_INSN_MOV, "mov", "mov", 16,
1008 { 0, { (1<<MACH_BASE) } }
1009 },
1010/* mov $Rs1,$Ri */
1011 {
1012 FR30_INSN_MOVDR, "movdr", "mov", 16,
1013 { 0, { (1<<MACH_BASE) } }
1014 },
1015/* mov $ps,$Ri */
1016 {
1017 FR30_INSN_MOVPS, "movps", "mov", 16,
1018 { 0, { (1<<MACH_BASE) } }
1019 },
1020/* mov $Ri,$Rs1 */
1021 {
1022 FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
1023 { 0, { (1<<MACH_BASE) } }
1024 },
1025/* mov $Ri,$ps */
1026 {
1027 FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
1028 { 0, { (1<<MACH_BASE) } }
1029 },
1030/* jmp @$Ri */
1031 {
1032 FR30_INSN_JMP, "jmp", "jmp", 16,
1033 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1034 },
1035/* jmp:d @$Ri */
1036 {
1037 FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
1038 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1039 },
1040/* call @$Ri */
1041 {
1042 FR30_INSN_CALLR, "callr", "call", 16,
1043 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1044 },
1045/* call:d @$Ri */
1046 {
1047 FR30_INSN_CALLRD, "callrd", "call:d", 16,
1048 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1049 },
1050/* call $label12 */
1051 {
1052 FR30_INSN_CALL, "call", "call", 16,
1053 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1054 },
1055/* call:d $label12 */
1056 {
1057 FR30_INSN_CALLD, "calld", "call:d", 16,
1058 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1059 },
1060/* ret */
1061 {
1062 FR30_INSN_RET, "ret", "ret", 16,
1063 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1064 },
1065/* ret:d */
1066 {
1067 FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1068 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1069 },
1070/* int $u8 */
1071 {
1072 FR30_INSN_INT, "int", "int", 16,
1073 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1074 },
1075/* inte */
1076 {
1077 FR30_INSN_INTE, "inte", "inte", 16,
1078 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1079 },
1080/* reti */
1081 {
1082 FR30_INSN_RETI, "reti", "reti", 16,
1083 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1084 },
1085/* bra:d $label9 */
1086 {
1087 FR30_INSN_BRAD, "brad", "bra:d", 16,
1088 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1089 },
1090/* bra $label9 */
1091 {
1092 FR30_INSN_BRA, "bra", "bra", 16,
1093 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1094 },
1095/* bno:d $label9 */
1096 {
1097 FR30_INSN_BNOD, "bnod", "bno:d", 16,
1098 { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1099 },
1100/* bno $label9 */
1101 {
1102 FR30_INSN_BNO, "bno", "bno", 16,
1103 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1104 },
1105/* beq:d $label9 */
1106 {
1107 FR30_INSN_BEQD, "beqd", "beq:d", 16,
1108 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1109 },
1110/* beq $label9 */
1111 {
1112 FR30_INSN_BEQ, "beq", "beq", 16,
1113 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1114 },
1115/* bne:d $label9 */
1116 {
1117 FR30_INSN_BNED, "bned", "bne:d", 16,
1118 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1119 },
1120/* bne $label9 */
1121 {
1122 FR30_INSN_BNE, "bne", "bne", 16,
1123 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1124 },
1125/* bc:d $label9 */
1126 {
1127 FR30_INSN_BCD, "bcd", "bc:d", 16,
1128 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1129 },
1130/* bc $label9 */
1131 {
1132 FR30_INSN_BC, "bc", "bc", 16,
1133 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1134 },
1135/* bnc:d $label9 */
1136 {
1137 FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1138 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1139 },
1140/* bnc $label9 */
1141 {
1142 FR30_INSN_BNC, "bnc", "bnc", 16,
1143 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1144 },
1145/* bn:d $label9 */
1146 {
1147 FR30_INSN_BND, "bnd", "bn:d", 16,
1148 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1149 },
1150/* bn $label9 */
1151 {
1152 FR30_INSN_BN, "bn", "bn", 16,
1153 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1154 },
1155/* bp:d $label9 */
1156 {
1157 FR30_INSN_BPD, "bpd", "bp:d", 16,
1158 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1159 },
1160/* bp $label9 */
1161 {
1162 FR30_INSN_BP, "bp", "bp", 16,
1163 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1164 },
1165/* bv:d $label9 */
1166 {
1167 FR30_INSN_BVD, "bvd", "bv:d", 16,
1168 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1169 },
1170/* bv $label9 */
1171 {
1172 FR30_INSN_BV, "bv", "bv", 16,
1173 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1174 },
1175/* bnv:d $label9 */
1176 {
1177 FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1178 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1179 },
1180/* bnv $label9 */
1181 {
1182 FR30_INSN_BNV, "bnv", "bnv", 16,
1183 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1184 },
1185/* blt:d $label9 */
1186 {
1187 FR30_INSN_BLTD, "bltd", "blt:d", 16,
1188 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1189 },
1190/* blt $label9 */
1191 {
1192 FR30_INSN_BLT, "blt", "blt", 16,
1193 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1194 },
1195/* bge:d $label9 */
1196 {
1197 FR30_INSN_BGED, "bged", "bge:d", 16,
1198 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1199 },
1200/* bge $label9 */
1201 {
1202 FR30_INSN_BGE, "bge", "bge", 16,
1203 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1204 },
1205/* ble:d $label9 */
1206 {
1207 FR30_INSN_BLED, "bled", "ble:d", 16,
1208 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1209 },
1210/* ble $label9 */
1211 {
1212 FR30_INSN_BLE, "ble", "ble", 16,
1213 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1214 },
1215/* bgt:d $label9 */
1216 {
1217 FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1218 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1219 },
1220/* bgt $label9 */
1221 {
1222 FR30_INSN_BGT, "bgt", "bgt", 16,
1223 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1224 },
1225/* bls:d $label9 */
1226 {
1227 FR30_INSN_BLSD, "blsd", "bls:d", 16,
1228 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1229 },
1230/* bls $label9 */
1231 {
1232 FR30_INSN_BLS, "bls", "bls", 16,
1233 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1234 },
1235/* bhi:d $label9 */
1236 {
1237 FR30_INSN_BHID, "bhid", "bhi:d", 16,
1238 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1239 },
1240/* bhi $label9 */
1241 {
1242 FR30_INSN_BHI, "bhi", "bhi", 16,
1243 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1244 },
1245/* dmov $R13,@$dir10 */
1246 {
1247 FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1248 { 0, { (1<<MACH_BASE) } }
1249 },
1250/* dmovh $R13,@$dir9 */
1251 {
1252 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1253 { 0, { (1<<MACH_BASE) } }
1254 },
1255/* dmovb $R13,@$dir8 */
1256 {
1257 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1258 { 0, { (1<<MACH_BASE) } }
1259 },
1260/* dmov @$R13+,@$dir10 */
1261 {
1262 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1263 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1264 },
1265/* dmovh @$R13+,@$dir9 */
1266 {
1267 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1268 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1269 },
1270/* dmovb @$R13+,@$dir8 */
1271 {
1272 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1273 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1274 },
1275/* dmov @$R15+,@$dir10 */
1276 {
1277 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1278 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1279 },
1280/* dmov @$dir10,$R13 */
1281 {
1282 FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1283 { 0, { (1<<MACH_BASE) } }
1284 },
1285/* dmovh @$dir9,$R13 */
1286 {
1287 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1288 { 0, { (1<<MACH_BASE) } }
1289 },
1290/* dmovb @$dir8,$R13 */
1291 {
1292 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1293 { 0, { (1<<MACH_BASE) } }
1294 },
1295/* dmov @$dir10,@$R13+ */
1296 {
1297 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1298 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1299 },
1300/* dmovh @$dir9,@$R13+ */
1301 {
1302 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1303 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1304 },
1305/* dmovb @$dir8,@$R13+ */
1306 {
1307 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1308 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1309 },
1310/* dmov @$dir10,@-$R15 */
1311 {
1312 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1313 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1314 },
1315/* ldres @$Ri+,$u4 */
1316 {
1317 FR30_INSN_LDRES, "ldres", "ldres", 16,
1318 { 0, { (1<<MACH_BASE) } }
1319 },
1320/* stres $u4,@$Ri+ */
1321 {
1322 FR30_INSN_STRES, "stres", "stres", 16,
1323 { 0, { (1<<MACH_BASE) } }
1324 },
1325/* copop $u4c,$ccc,$CRj,$CRi */
1326 {
1327 FR30_INSN_COPOP, "copop", "copop", 32,
1328 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1329 },
1330/* copld $u4c,$ccc,$Rjc,$CRi */
1331 {
1332 FR30_INSN_COPLD, "copld", "copld", 32,
1333 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1334 },
1335/* copst $u4c,$ccc,$CRj,$Ric */
1336 {
1337 FR30_INSN_COPST, "copst", "copst", 32,
1338 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1339 },
1340/* copsv $u4c,$ccc,$CRj,$Ric */
1341 {
1342 FR30_INSN_COPSV, "copsv", "copsv", 32,
1343 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1344 },
1345/* nop */
1346 {
1347 FR30_INSN_NOP, "nop", "nop", 16,
1348 { 0, { (1<<MACH_BASE) } }
1349 },
1350/* andccr $u8 */
1351 {
1352 FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1353 { 0, { (1<<MACH_BASE) } }
1354 },
1355/* orccr $u8 */
1356 {
1357 FR30_INSN_ORCCR, "orccr", "orccr", 16,
1358 { 0, { (1<<MACH_BASE) } }
1359 },
1360/* stilm $u8 */
1361 {
1362 FR30_INSN_STILM, "stilm", "stilm", 16,
1363 { 0, { (1<<MACH_BASE) } }
1364 },
1365/* addsp $s10 */
1366 {
1367 FR30_INSN_ADDSP, "addsp", "addsp", 16,
1368 { 0, { (1<<MACH_BASE) } }
1369 },
1370/* extsb $Ri */
1371 {
1372 FR30_INSN_EXTSB, "extsb", "extsb", 16,
1373 { 0, { (1<<MACH_BASE) } }
1374 },
1375/* extub $Ri */
1376 {
1377 FR30_INSN_EXTUB, "extub", "extub", 16,
1378 { 0, { (1<<MACH_BASE) } }
1379 },
1380/* extsh $Ri */
1381 {
1382 FR30_INSN_EXTSH, "extsh", "extsh", 16,
1383 { 0, { (1<<MACH_BASE) } }
1384 },
1385/* extuh $Ri */
1386 {
1387 FR30_INSN_EXTUH, "extuh", "extuh", 16,
1388 { 0, { (1<<MACH_BASE) } }
1389 },
1390/* ldm0 ($reglist_low_ld) */
1391 {
1392 FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1393 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1394 },
1395/* ldm1 ($reglist_hi_ld) */
1396 {
1397 FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1398 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1399 },
1400/* stm0 ($reglist_low_st) */
1401 {
1402 FR30_INSN_STM0, "stm0", "stm0", 16,
1403 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1404 },
1405/* stm1 ($reglist_hi_st) */
1406 {
1407 FR30_INSN_STM1, "stm1", "stm1", 16,
1408 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1409 },
1410/* enter $u10 */
1411 {
1412 FR30_INSN_ENTER, "enter", "enter", 16,
1413 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1414 },
1415/* leave */
1416 {
1417 FR30_INSN_LEAVE, "leave", "leave", 16,
1418 { 0, { (1<<MACH_BASE) } }
1419 },
1420/* xchb @$Rj,$Ri */
1421 {
1422 FR30_INSN_XCHB, "xchb", "xchb", 16,
1423 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1424 },
1425};
1426
252b5132 1427#undef OP
b3466c39 1428#undef A
252b5132
RH		 1429
1430/* Initialize anything needed to be done once, before any cpu_open call. */
0e2ee3ca 1431static void init_tables PARAMS ((void));
252b5132
RH		 1432
1433static void
1434init_tables ()
1435{
1436}
1437
0e2ee3ca
NC		 1438static const CGEN_MACH * lookup_mach_via_bfd_name
1439 PARAMS ((const CGEN_MACH *, const char *));
1440static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1441static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1442static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1443static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1444static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1445
252b5132
RH		 1446/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
1447
1448static const CGEN_MACH *
1449lookup_mach_via_bfd_name (table, name)
1450 const CGEN_MACH *table;
1451 const char *name;
1452{
1453 while (table->name)
1454 {
1455 if (strcmp (name, table->bfd_name) == 0)
1456 return table;
1457 ++table;
1458 }
1459 abort ();
1460}
1461
1462/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1463
1464static void
1465build_hw_table (cd)
1466 CGEN_CPU_TABLE *cd;
1467{
1468 int i;
1469 int machs = cd->machs;
1470 const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1471 /* MAX_HW is only an upper bound on the number of selected entries.
1472 However each entry is indexed by it's enum so there can be holes in
1473 the table. */
1474 const CGEN_HW_ENTRY **selected =
1475 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1476
1477 cd->hw_table.init_entries = init;
1478 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1479 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1480 /* ??? For now we just use machs to determine which ones we want. */
1481 for (i = 0; init[i].name != NULL; ++i)
1482 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1483 & machs)
1484 selected[init[i].type] = &init[i];
1485 cd->hw_table.entries = selected;
1486 cd->hw_table.num_entries = MAX_HW;
1487}
1488
1489/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1490
1491static void
1492build_ifield_table (cd)
1493 CGEN_CPU_TABLE *cd;
1494{
1495 cd->ifld_table = & fr30_cgen_ifld_table[0];
1496}
1497
1498/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1499
1500static void
1501build_operand_table (cd)
1502 CGEN_CPU_TABLE *cd;
1503{
1504 int i;
1505 int machs = cd->machs;
1506 const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1507 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1508 However each entry is indexed by it's enum so there can be holes in
1509 the table. */
1510 const CGEN_OPERAND **selected =
1511 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1512
1513 cd->operand_table.init_entries = init;
1514 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1515 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1516 /* ??? For now we just use mach to determine which ones we want. */
1517 for (i = 0; init[i].name != NULL; ++i)
1518 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1519 & machs)
1520 selected[init[i].type] = &init[i];
1521 cd->operand_table.entries = selected;
1522 cd->operand_table.num_entries = MAX_OPERANDS;
1523}
1524
1525/* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1526 ??? This could leave out insns not supported by the specified mach/isa,
1527 but that would cause errors like "foo only supported by bar" to become
1528 "unknown insn", so for now we include all insns and require the app to
1529 do the checking later.
1530 ??? On the other hand, parsing of such insns may require their hardware or
1531 operand elements to be in the table [which they mightn't be]. */
1532
1533static void
1534build_insn_table (cd)
1535 CGEN_CPU_TABLE *cd;
1536{
1537 int i;
1538 const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1539 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1540
1541 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1542 for (i = 0; i < MAX_INSNS; ++i)
1543 insns[i].base = &ib[i];
1544 cd->insn_table.init_entries = insns;
1545 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1546 cd->insn_table.num_init_entries = MAX_INSNS;
1547}
1548
1549/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */
1550
1551static void
1552fr30_cgen_rebuild_tables (cd)
1553 CGEN_CPU_TABLE *cd;
1554{
fc7bc883 1555 int i;
252b5132
RH		 1556 unsigned int isas = cd->isas;
1557 unsigned int machs = cd->machs;
1558
1559 cd->int_insn_p = CGEN_INT_INSN_P;
1560
1561 /* Data derived from the isa spec. */
1562#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1563 cd->default_insn_bitsize = UNSET;
1564 cd->base_insn_bitsize = UNSET;
1565 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1566 cd->max_insn_bitsize = 0;
1567 for (i = 0; i < MAX_ISAS; ++i)
1568 if (((1 << i) & isas) != 0)
1569 {
1570 const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1571
9a2e995d
GH		 1572 /* Default insn sizes of all selected isas must be
1573 equal or we set the result to 0, meaning "unknown". */
252b5132
RH		 1574 if (cd->default_insn_bitsize == UNSET)
1575 cd->default_insn_bitsize = isa->default_insn_bitsize;
1576 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1577 ; /* this is ok */
1578 else
1579 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1580
9a2e995d
GH		 1581 /* Base insn sizes of all selected isas must be equal
1582 or we set the result to 0, meaning "unknown". */
252b5132
RH		 1583 if (cd->base_insn_bitsize == UNSET)
1584 cd->base_insn_bitsize = isa->base_insn_bitsize;
1585 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1586 ; /* this is ok */
1587 else
1588 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1589
1590 /* Set min,max insn sizes. */
1591 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1592 cd->min_insn_bitsize = isa->min_insn_bitsize;
1593 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1594 cd->max_insn_bitsize = isa->max_insn_bitsize;
252b5132
RH		 1595 }
1596
1597 /* Data derived from the mach spec. */
1598 for (i = 0; i < MAX_MACHS; ++i)
1599 if (((1 << i) & machs) != 0)
1600 {
1601 const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1602
fc7bc883
RH		 1603 if (mach->insn_chunk_bitsize != 0)
1604 {
1605 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1606 {
1607 fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1608 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1609 abort ();
1610 }
1611
1612 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1613 }
252b5132
RH		 1614 }
1615
1616 /* Determine which hw elements are used by MACH. */
1617 build_hw_table (cd);
1618
1619 /* Build the ifield table. */
1620 build_ifield_table (cd);
1621
1622 /* Determine which operands are used by MACH/ISA. */
1623 build_operand_table (cd);
1624
1625 /* Build the instruction table. */
1626 build_insn_table (cd);
1627}
1628
1629/* Initialize a cpu table and return a descriptor.
1630 It's much like opening a file, and must be the first function called.
1631 The arguments are a set of (type/value) pairs, terminated with
1632 CGEN_CPU_OPEN_END.
1633
1634 Currently supported values:
1635 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1636 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1637 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1638 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1639 CGEN_CPU_OPEN_END: terminates arguments
1640
1641 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1642 precluded.
1643
1644 ??? We only support ISO C stdargs here, not K&R.
1645 Laziness, plus experiment to see if anything requires K&R - eventually
1646 K&R will no longer be supported - e.g. GDB is currently trying this. */
1647
1648CGEN_CPU_DESC
1649fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1650{
1651 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1652 static int init_p;
1653 unsigned int isas = 0; /* 0 = "unspecified" */
1654 unsigned int machs = 0; /* 0 = "unspecified" */
1655 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1656 va_list ap;
1657
1658 if (! init_p)
1659 {
1660 init_tables ();
1661 init_p = 1;
1662 }
1663
1664 memset (cd, 0, sizeof (*cd));
1665
1666 va_start (ap, arg_type);
1667 while (arg_type != CGEN_CPU_OPEN_END)
1668 {
1669 switch (arg_type)
1670 {
1671 case CGEN_CPU_OPEN_ISAS :
1672 isas = va_arg (ap, unsigned int);
1673 break;
1674 case CGEN_CPU_OPEN_MACHS :
1675 machs = va_arg (ap, unsigned int);
1676 break;
1677 case CGEN_CPU_OPEN_BFDMACH :
1678 {
1679 const char *name = va_arg (ap, const char *);
1680 const CGEN_MACH *mach =
1681 lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1682
27fca2d8 1683 machs |= 1 << mach->num;
252b5132
RH		 1684 break;
1685 }
1686 case CGEN_CPU_OPEN_ENDIAN :
1687 endian = va_arg (ap, enum cgen_endian);
1688 break;
1689 default :
1690 fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1691 arg_type);
1692 abort (); /* ??? return NULL? */
1693 }
1694 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1695 }
1696 va_end (ap);
1697
1698 /* mach unspecified means "all" */
1699 if (machs == 0)
1700 machs = (1 << MAX_MACHS) - 1;
1701 /* base mach is always selected */
1702 machs |= 1;
1703 /* isa unspecified means "all" */
1704 if (isas == 0)
1705 isas = (1 << MAX_ISAS) - 1;
1706 if (endian == CGEN_ENDIAN_UNKNOWN)
1707 {
1708 /* ??? If target has only one, could have a default. */
1709 fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1710 abort ();
1711 }
1712
1713 cd->isas = isas;
1714 cd->machs = machs;
1715 cd->endian = endian;
1716 /* FIXME: for the sparc case we can determine insn-endianness statically.
1717 The worry here is where both data and insn endian can be independently
1718 chosen, in which case this function will need another argument.
1719 Actually, will want to allow for more arguments in the future anyway. */
1720 cd->insn_endian = endian;
1721
1722 /* Table (re)builder. */
1723 cd->rebuild_tables = fr30_cgen_rebuild_tables;
1724 fr30_cgen_rebuild_tables (cd);
1725
6bb95a0f 1726 /* Default to not allowing signed overflow. */
447b43fa
NC		 1727 cd->signed_overflow_ok_p = 0;
1728
252b5132
RH		 1729 return (CGEN_CPU_DESC) cd;
1730}
1731
1732/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1733 MACH_NAME is the bfd name of the mach. */
1734
1735CGEN_CPU_DESC
1736fr30_cgen_cpu_open_1 (mach_name, endian)
1737 const char *mach_name;
1738 enum cgen_endian endian;
1739{
1740 return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1741 CGEN_CPU_OPEN_ENDIAN, endian,
1742 CGEN_CPU_OPEN_END);
1743}
1744
1745/* Close a cpu table.
1746 ??? This can live in a machine independent file, but there's currently
1747 no place to put this file (there's no libcgen). libopcodes is the wrong
1748 place as some simulator ports use this but they don't use libopcodes. */
1749
1750void
1751fr30_cgen_cpu_close (cd)
1752 CGEN_CPU_DESC cd;
1753{
a978a3e5 1754 unsigned int i;
98f70fc4 1755 const CGEN_INSN *insns;
a978a3e5
NC		 1756
1757 if (cd->macro_insn_table.init_entries)
1758 {
1759 insns = cd->macro_insn_table.init_entries;
1760 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1761 {
1762 if (CGEN_INSN_RX ((insns)))
98f70fc4 1763 regfree (CGEN_INSN_RX (insns));
a978a3e5
NC		 1764 }
1765 }
1766
1767 if (cd->insn_table.init_entries)
1768 {
1769 insns = cd->insn_table.init_entries;
1770 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1771 {
1772 if (CGEN_INSN_RX (insns))
98f70fc4 1773 regfree (CGEN_INSN_RX (insns));
a978a3e5
NC		 1774 }
1775 }
1776
1777
1778
1779 if (cd->macro_insn_table.init_entries)
1780 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1781
252b5132
RH		 1782 if (cd->insn_table.init_entries)
1783 free ((CGEN_INSN *) cd->insn_table.init_entries);
a978a3e5 1784
252b5132
RH		 1785 if (cd->hw_table.entries)
1786 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
a978a3e5
NC		 1787
1788 if (cd->operand_table.entries)
1789 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1790
252b5132
RH		 1791 free (cd);
1792}
1793
GDB Binutils - Deliverables
This page took 0.230327 seconds and 4 git commands to generate.