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* configure.tgt (spu-*-elf*): Delete targ_extra_ofiles.
[deliverable/binutils-gdb.git] / opcodes / fr30-dis.c
CommitLineData
252b5132
RH		 1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
47b0e7ad
NC		 4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
252b5132 6
fb53f5a8 7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
47b0e7ad 8 Free Software Foundation, Inc.
252b5132 9
47b0e7ad 10 This file is part of the GNU Binutils and GDB, the GNU debugger.
252b5132 11
47b0e7ad
NC		 12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
15 any later version.
252b5132 16
47b0e7ad
NC		 17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
252b5132 21
47b0e7ad
NC		 22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software Foundation, Inc.,
24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 25
26/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29#include "sysdep.h"
30#include <stdio.h>
31#include "ansidecl.h"
32#include "dis-asm.h"
33#include "bfd.h"
34#include "symcat.h"
98f70fc4 35#include "libiberty.h"
252b5132
RH		 36#include "fr30-desc.h"
37#include "fr30-opc.h"
38#include "opintl.h"
39
40/* Default text to print if an instruction isn't recognized. */
41#define UNKNOWN_INSN_MSG _("*unknown*")
42
0e2ee3ca 43static void print_normal
ffead7ae 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
0e2ee3ca 45static void print_address
bf143b25 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
0e2ee3ca 47static void print_keyword
bf143b25 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
0e2ee3ca 49static void print_insn_normal
ffead7ae 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
0e2ee3ca 51static int print_insn
33b71eeb 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
0e2ee3ca 53static int default_print_insn
bf143b25 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
0e2ee3ca 55static int read_insn
33b71eeb 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
ffead7ae 57 unsigned long *);
252b5132 58\f
47b0e7ad 59/* -- disassembler routines inserted here. */
252b5132
RH		 60
61/* -- dis.c */
252b5132 62static void
47b0e7ad
NC		 63print_register_list (void * dis_info,
64 long value,
65 long offset,
66 int load_store) /* 0 == load, 1 == store. */
252b5132
RH		 67{
68 disassemble_info *info = dis_info;
69 int mask;
70 int index = 0;
47b0e7ad 71 char * comma = "";
252b5132
RH		 72
73 if (load_store)
74 mask = 0x80;
75 else
76 mask = 1;
77
78 if (value & mask)
79 {
0fd3a477 80 (*info->fprintf_func) (info->stream, "r%li", index + offset);
252b5132
RH		 81 comma = ",";
82 }
83
84 for (index = 1; index <= 7; ++index)
85 {
86 if (load_store)
87 mask >>= 1;
88 else
89 mask <<= 1;
90
91 if (value & mask)
92 {
0fd3a477 93 (*info->fprintf_func) (info->stream, "%sr%li", comma, index + offset);
252b5132
RH		 94 comma = ",";
95 }
96 }
97}
98
99static void
47b0e7ad
NC		 100print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
101 void * dis_info,
102 long value,
103 unsigned int attrs ATTRIBUTE_UNUSED,
104 bfd_vma pc ATTRIBUTE_UNUSED,
105 int length ATTRIBUTE_UNUSED)
252b5132 106{
47b0e7ad 107 print_register_list (dis_info, value, 8, 0 /* Load. */);
252b5132
RH		 108}
109
110static void
47b0e7ad
NC		 111print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
112 void * dis_info,
113 long value,
114 unsigned int attrs ATTRIBUTE_UNUSED,
115 bfd_vma pc ATTRIBUTE_UNUSED,
116 int length ATTRIBUTE_UNUSED)
252b5132 117{
47b0e7ad 118 print_register_list (dis_info, value, 0, 0 /* Load. */);
252b5132
RH		 119}
120
121static void
47b0e7ad
NC		 122print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
123 void * dis_info,
124 long value,
125 unsigned int attrs ATTRIBUTE_UNUSED,
126 bfd_vma pc ATTRIBUTE_UNUSED,
127 int length ATTRIBUTE_UNUSED)
252b5132 128{
47b0e7ad 129 print_register_list (dis_info, value, 8, 1 /* Store. */);
252b5132
RH		 130}
131
132static void
47b0e7ad
NC		 133print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
134 void * dis_info,
135 long value,
136 unsigned int attrs ATTRIBUTE_UNUSED,
137 bfd_vma pc ATTRIBUTE_UNUSED,
138 int length ATTRIBUTE_UNUSED)
252b5132 139{
47b0e7ad 140 print_register_list (dis_info, value, 0, 1 /* Store. */);
252b5132
RH		 141}
142
143static void
47b0e7ad
NC		 144print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
145 void * dis_info,
146 long value,
147 unsigned int attrs ATTRIBUTE_UNUSED,
148 bfd_vma pc ATTRIBUTE_UNUSED,
149 int length ATTRIBUTE_UNUSED)
252b5132
RH		 150{
151 disassemble_info *info = (disassemble_info *) dis_info;
47b0e7ad 152
252b5132
RH		 153 (*info->fprintf_func) (info->stream, "%ld", value);
154}
155/* -- */
156
0e2ee3ca 157void fr30_cgen_print_operand
47b0e7ad 158 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
0e2ee3ca 159
252b5132
RH		 160/* Main entry point for printing operands.
161 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
162 of dis-asm.h on cgen.h.
163
164 This function is basically just a big switch statement. Earlier versions
165 used tables to look up the function to use, but
166 - if the table contains both assembler and disassembler functions then
167 the disassembler contains much of the assembler and vice-versa,
168 - there's a lot of inlining possibilities as things grow,
169 - using a switch statement avoids the function call overhead.
170
171 This function could be moved into `print_insn_normal', but keeping it
172 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 173 the handlers. */
252b5132
RH		 174
175void
47b0e7ad
NC		 176fr30_cgen_print_operand (CGEN_CPU_DESC cd,
177 int opindex,
178 void * xinfo,
179 CGEN_FIELDS *fields,
180 void const *attrs ATTRIBUTE_UNUSED,
181 bfd_vma pc,
182 int length)
252b5132 183{
47b0e7ad 184 disassemble_info *info = (disassemble_info *) xinfo;
252b5132
RH		 185
186 switch (opindex)
187 {
188 case FR30_OPERAND_CRI :
189 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
190 break;
191 case FR30_OPERAND_CRJ :
192 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
193 break;
194 case FR30_OPERAND_R13 :
eb1b03df 195 print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
252b5132
RH		 196 break;
197 case FR30_OPERAND_R14 :
eb1b03df 198 print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
252b5132
RH		 199 break;
200 case FR30_OPERAND_R15 :
eb1b03df 201 print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
252b5132
RH		 202 break;
203 case FR30_OPERAND_RI :
204 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
205 break;
206 case FR30_OPERAND_RIC :
207 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
208 break;
209 case FR30_OPERAND_RJ :
210 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
211 break;
212 case FR30_OPERAND_RJC :
213 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
214 break;
215 case FR30_OPERAND_RS1 :
216 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
217 break;
218 case FR30_OPERAND_RS2 :
219 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
220 break;
221 case FR30_OPERAND_CC :
222 print_normal (cd, info, fields->f_cc, 0, pc, length);
223 break;
224 case FR30_OPERAND_CCC :
225 print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
226 break;
227 case FR30_OPERAND_DIR10 :
228 print_normal (cd, info, fields->f_dir10, 0, pc, length);
229 break;
230 case FR30_OPERAND_DIR8 :
231 print_normal (cd, info, fields->f_dir8, 0, pc, length);
232 break;
233 case FR30_OPERAND_DIR9 :
234 print_normal (cd, info, fields->f_dir9, 0, pc, length);
235 break;
236 case FR30_OPERAND_DISP10 :
237 print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
238 break;
239 case FR30_OPERAND_DISP8 :
240 print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
241 break;
242 case FR30_OPERAND_DISP9 :
243 print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
244 break;
245 case FR30_OPERAND_I20 :
246 print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
247 break;
248 case FR30_OPERAND_I32 :
249 print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
250 break;
251 case FR30_OPERAND_I8 :
252 print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
253 break;
254 case FR30_OPERAND_LABEL12 :
255 print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
256 break;
257 case FR30_OPERAND_LABEL9 :
258 print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
259 break;
260 case FR30_OPERAND_M4 :
261 print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
262 break;
263 case FR30_OPERAND_PS :
eb1b03df 264 print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
252b5132
RH		 265 break;
266 case FR30_OPERAND_REGLIST_HI_LD :
267 print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
268 break;
269 case FR30_OPERAND_REGLIST_HI_ST :
270 print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
271 break;
272 case FR30_OPERAND_REGLIST_LOW_LD :
273 print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
274 break;
275 case FR30_OPERAND_REGLIST_LOW_ST :
276 print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
277 break;
278 case FR30_OPERAND_S10 :
279 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
280 break;
281 case FR30_OPERAND_U10 :
282 print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
283 break;
284 case FR30_OPERAND_U4 :
285 print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
286 break;
287 case FR30_OPERAND_U4C :
288 print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
289 break;
290 case FR30_OPERAND_U8 :
291 print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
292 break;
293 case FR30_OPERAND_UDISP6 :
294 print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
295 break;
296
297 default :
298 /* xgettext:c-format */
299 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
300 opindex);
301 abort ();
302 }
303}
304
305cgen_print_fn * const fr30_cgen_print_handlers[] =
306{
307 print_insn_normal,
308};
309
310
311void
47b0e7ad 312fr30_cgen_init_dis (CGEN_CPU_DESC cd)
252b5132
RH		 313{
314 fr30_cgen_init_opcode_table (cd);
315 fr30_cgen_init_ibld_table (cd);
316 cd->print_handlers = & fr30_cgen_print_handlers[0];
317 cd->print_operand = fr30_cgen_print_operand;
318}
319
320\f
321/* Default print handler. */
322
323static void
ffead7ae
MM		 324print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
325 void *dis_info,
326 long value,
327 unsigned int attrs,
328 bfd_vma pc ATTRIBUTE_UNUSED,
329 int length ATTRIBUTE_UNUSED)
252b5132
RH		 330{
331 disassemble_info *info = (disassemble_info *) dis_info;
332
333#ifdef CGEN_PRINT_NORMAL
334 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
335#endif
336
337 /* Print the operand as directed by the attributes. */
338 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
339 ; /* nothing to do */
340 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
341 (*info->fprintf_func) (info->stream, "%ld", value);
342 else
343 (*info->fprintf_func) (info->stream, "0x%lx", value);
344}
345
346/* Default address handler. */
347
348static void
ffead7ae
MM		 349print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
350 void *dis_info,
351 bfd_vma value,
352 unsigned int attrs,
353 bfd_vma pc ATTRIBUTE_UNUSED,
354 int length ATTRIBUTE_UNUSED)
252b5132
RH		 355{
356 disassemble_info *info = (disassemble_info *) dis_info;
357
358#ifdef CGEN_PRINT_ADDRESS
359 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
360#endif
361
362 /* Print the operand as directed by the attributes. */
363 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
47b0e7ad 364 ; /* Nothing to do. */
252b5132
RH		 365 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
366 (*info->print_address_func) (value, info);
367 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
368 (*info->print_address_func) (value, info);
369 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
370 (*info->fprintf_func) (info->stream, "%ld", (long) value);
371 else
372 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
373}
374
375/* Keyword print handler. */
376
377static void
ffead7ae
MM		 378print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
379 void *dis_info,
380 CGEN_KEYWORD *keyword_table,
381 long value,
382 unsigned int attrs ATTRIBUTE_UNUSED)
252b5132
RH		 383{
384 disassemble_info *info = (disassemble_info *) dis_info;
385 const CGEN_KEYWORD_ENTRY *ke;
386
387 ke = cgen_keyword_lookup_value (keyword_table, value);
388 if (ke != NULL)
389 (*info->fprintf_func) (info->stream, "%s", ke->name);
390 else
391 (*info->fprintf_func) (info->stream, "???");
392}
393\f
394/* Default insn printer.
395
ffead7ae 396 DIS_INFO is defined as `void *' so the disassembler needn't know anything
252b5132
RH		 397 about disassemble_info. */
398
399static void
ffead7ae
MM		 400print_insn_normal (CGEN_CPU_DESC cd,
401 void *dis_info,
402 const CGEN_INSN *insn,
403 CGEN_FIELDS *fields,
404 bfd_vma pc,
405 int length)
252b5132
RH		 406{
407 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
408 disassemble_info *info = (disassemble_info *) dis_info;
b3466c39 409 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH		 410
411 CGEN_INIT_PRINT (cd);
412
413 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
414 {
415 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
416 {
417 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
418 continue;
419 }
420 if (CGEN_SYNTAX_CHAR_P (*syn))
421 {
422 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
423 continue;
424 }
425
426 /* We have an operand. */
427 fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
428 fields, CGEN_INSN_ATTRS (insn), pc, length);
429 }
430}
431\f
6bb95a0f
DB		 432/* Subroutine of print_insn. Reads an insn into the given buffers and updates
433 the extract info.
434 Returns 0 if all is well, non-zero otherwise. */
0e2ee3ca 435
252b5132 436static int
ffead7ae
MM		 437read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
438 bfd_vma pc,
439 disassemble_info *info,
33b71eeb 440 bfd_byte *buf,
ffead7ae
MM		 441 int buflen,
442 CGEN_EXTRACT_INFO *ex_info,
443 unsigned long *insn_value)
252b5132 444{
6bb95a0f 445 int status = (*info->read_memory_func) (pc, buf, buflen, info);
47b0e7ad 446
6bb95a0f
DB		 447 if (status != 0)
448 {
449 (*info->memory_error_func) (status, pc, info);
450 return -1;
451 }
252b5132 452
6bb95a0f
DB		 453 ex_info->dis_info = info;
454 ex_info->valid = (1 << buflen) - 1;
455 ex_info->insn_bytes = buf;
252b5132 456
b3466c39 457 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
6bb95a0f
DB		 458 return 0;
459}
460
461/* Utility to print an insn.
462 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
463 The result is the size of the insn in bytes or zero for an unknown insn
464 or -1 if an error occurs fetching data (memory_error_func will have
465 been called). */
466
467static int
ffead7ae
MM		 468print_insn (CGEN_CPU_DESC cd,
469 bfd_vma pc,
470 disassemble_info *info,
33b71eeb 471 bfd_byte *buf,
ffead7ae 472 unsigned int buflen)
6bb95a0f 473{
fc7bc883 474 CGEN_INSN_INT insn_value;
6bb95a0f
DB		 475 const CGEN_INSN_LIST *insn_list;
476 CGEN_EXTRACT_INFO ex_info;
2e1ef6b4 477 int basesize;
6bb95a0f 478
fc7bc883 479 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
2e1ef6b4
DB		 480 basesize = cd->base_insn_bitsize < buflen * 8 ?
481 cd->base_insn_bitsize : buflen * 8;
482 insn_value = cgen_get_insn_value (cd, buf, basesize);
483
fc7bc883
RH		 484
485 /* Fill in ex_info fields like read_insn would. Don't actually call
486 read_insn, since the incoming buffer is already read (and possibly
487 modified a la m32r). */
488 ex_info.valid = (1 << buflen) - 1;
489 ex_info.dis_info = info;
490 ex_info.insn_bytes = buf;
6bb95a0f 491
252b5132
RH		 492 /* The instructions are stored in hash lists.
493 Pick the first one and keep trying until we find the right one. */
494
33b71eeb 495 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
252b5132
RH		 496 while (insn_list != NULL)
497 {
498 const CGEN_INSN *insn = insn_list->insn;
499 CGEN_FIELDS fields;
500 int length;
fc7bc883 501 unsigned long insn_value_cropped;
252b5132 502
6bb95a0f 503#ifdef CGEN_VALIDATE_INSN_SUPPORTED
0e2ee3ca 504 /* Not needed as insn shouldn't be in hash lists if not supported. */
252b5132
RH		 505 /* Supported by this cpu? */
506 if (! fr30_cgen_insn_supported (cd, insn))
6bb95a0f
DB		 507 {
508 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
509 continue;
510 }
252b5132
RH		 511#endif
512
513 /* Basic bit mask must be correct. */
514 /* ??? May wish to allow target to defer this check until the extract
515 handler. */
fc7bc883
RH		 516
517 /* Base size may exceed this instruction's size. Extract the
518 relevant part from the buffer. */
0e2ee3ca 519 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
d5b2f4d6 520 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
fc7bc883
RH		 521 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
522 info->endian == BFD_ENDIAN_BIG);
523 else
524 insn_value_cropped = insn_value;
525
526 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
252b5132
RH		 527 == CGEN_INSN_BASE_VALUE (insn))
528 {
529 /* Printing is handled in two passes. The first pass parses the
530 machine insn and extracts the fields. The second pass prints
531 them. */
532
708b8a71
NC		 533 /* Make sure the entire insn is loaded into insn_value, if it
534 can fit. */
0e2ee3ca 535 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
d5b2f4d6 536 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
6bb95a0f
DB		 537 {
538 unsigned long full_insn_value;
539 int rc = read_insn (cd, pc, info, buf,
540 CGEN_INSN_BITSIZE (insn) / 8,
541 & ex_info, & full_insn_value);
542 if (rc != 0)
543 return rc;
544 length = CGEN_EXTRACT_FN (cd, insn)
545 (cd, insn, &ex_info, full_insn_value, &fields, pc);
546 }
547 else
708b8a71 548 length = CGEN_EXTRACT_FN (cd, insn)
fc7bc883 549 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
6bb95a0f 550
47b0e7ad 551 /* Length < 0 -> error. */
252b5132
RH		 552 if (length < 0)
553 return length;
554 if (length > 0)
555 {
556 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
47b0e7ad 557 /* Length is in bits, result is in bytes. */
252b5132
RH		 558 return length / 8;
559 }
560 }
561
562 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
563 }
564
565 return 0;
566}
567
568/* Default value for CGEN_PRINT_INSN.
569 The result is the size of the insn in bytes or zero for an unknown insn
570 or -1 if an error occured fetching bytes. */
571
572#ifndef CGEN_PRINT_INSN
573#define CGEN_PRINT_INSN default_print_insn
574#endif
575
576static int
ffead7ae 577default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
252b5132 578{
33b71eeb 579 bfd_byte buf[CGEN_MAX_INSN_SIZE];
fc7bc883 580 int buflen;
252b5132
RH		 581 int status;
582
fc7bc883
RH		 583 /* Attempt to read the base part of the insn. */
584 buflen = cd->base_insn_bitsize / 8;
585 status = (*info->read_memory_func) (pc, buf, buflen, info);
586
587 /* Try again with the minimum part, if min < base. */
588 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
589 {
590 buflen = cd->min_insn_bitsize / 8;
591 status = (*info->read_memory_func) (pc, buf, buflen, info);
592 }
252b5132 593
252b5132
RH		 594 if (status != 0)
595 {
596 (*info->memory_error_func) (status, pc, info);
597 return -1;
598 }
599
fc7bc883 600 return print_insn (cd, pc, info, buf, buflen);
252b5132
RH		 601}
602
603/* Main entry point.
604 Print one instruction from PC on INFO->STREAM.
605 Return the size of the instruction (in bytes). */
606
47b0e7ad
NC		 607typedef struct cpu_desc_list
608{
a978a3e5 609 struct cpu_desc_list *next;
fb53f5a8 610 CGEN_BITSET *isa;
a978a3e5
NC		 611 int mach;
612 int endian;
613 CGEN_CPU_DESC cd;
614} cpu_desc_list;
615
252b5132 616int
ffead7ae 617print_insn_fr30 (bfd_vma pc, disassemble_info *info)
252b5132 618{
a978a3e5
NC		 619 static cpu_desc_list *cd_list = 0;
620 cpu_desc_list *cl = 0;
252b5132 621 static CGEN_CPU_DESC cd = 0;
fb53f5a8 622 static CGEN_BITSET *prev_isa;
6bb95a0f
DB		 623 static int prev_mach;
624 static int prev_endian;
252b5132 625 int length;
fb53f5a8
DB		 626 CGEN_BITSET *isa;
627 int mach;
252b5132
RH		 628 int endian = (info->endian == BFD_ENDIAN_BIG
629 ? CGEN_ENDIAN_BIG
630 : CGEN_ENDIAN_LITTLE);
631 enum bfd_architecture arch;
632
633 /* ??? gdb will set mach but leave the architecture as "unknown" */
634#ifndef CGEN_BFD_ARCH
635#define CGEN_BFD_ARCH bfd_arch_fr30
636#endif
637 arch = info->arch;
638 if (arch == bfd_arch_unknown)
639 arch = CGEN_BFD_ARCH;
27fca2d8
PM		 640
641 /* There's no standard way to compute the machine or isa number
252b5132 642 so we leave it to the target. */
27fca2d8
PM		 643#ifdef CGEN_COMPUTE_MACH
644 mach = CGEN_COMPUTE_MACH (info);
645#else
646 mach = info->mach;
647#endif
648
252b5132 649#ifdef CGEN_COMPUTE_ISA
fb53f5a8
DB		 650 {
651 static CGEN_BITSET *permanent_isa;
652
653 if (!permanent_isa)
654 permanent_isa = cgen_bitset_create (MAX_ISAS);
655 isa = permanent_isa;
656 cgen_bitset_clear (isa);
657 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
658 }
252b5132 659#else
a978a3e5 660 isa = info->insn_sets;
252b5132
RH		 661#endif
662
a978a3e5 663 /* If we've switched cpu's, try to find a handle we've used before */
252b5132 664 if (cd
fb53f5a8 665 && (cgen_bitset_compare (isa, prev_isa) != 0
252b5132
RH		 666 || mach != prev_mach
667 || endian != prev_endian))
668 {
252b5132 669 cd = 0;
a978a3e5
NC		 670 for (cl = cd_list; cl; cl = cl->next)
671 {
fb53f5a8 672 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
a978a3e5
NC		 673 cl->mach == mach &&
674 cl->endian == endian)
675 {
676 cd = cl->cd;
fb53f5a8 677 prev_isa = cd->isas;
a978a3e5
NC		 678 break;
679 }
680 }
681 }
252b5132
RH		 682
683 /* If we haven't initialized yet, initialize the opcode table. */
684 if (! cd)
685 {
686 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
687 const char *mach_name;
688
689 if (!arch_type)
690 abort ();
691 mach_name = arch_type->printable_name;
692
fb53f5a8 693 prev_isa = cgen_bitset_copy (isa);
252b5132
RH		 694 prev_mach = mach;
695 prev_endian = endian;
696 cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
697 CGEN_CPU_OPEN_BFDMACH, mach_name,
698 CGEN_CPU_OPEN_ENDIAN, prev_endian,
699 CGEN_CPU_OPEN_END);
700 if (!cd)
701 abort ();
a978a3e5 702
47b0e7ad 703 /* Save this away for future reference. */
a978a3e5
NC		 704 cl = xmalloc (sizeof (struct cpu_desc_list));
705 cl->cd = cd;
fb53f5a8 706 cl->isa = prev_isa;
a978a3e5
NC		 707 cl->mach = mach;
708 cl->endian = endian;
709 cl->next = cd_list;
710 cd_list = cl;
711
252b5132
RH		 712 fr30_cgen_init_dis (cd);
713 }
714
715 /* We try to have as much common code as possible.
716 But at this point some targets need to take over. */
717 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
718 but if not possible try to move this hook elsewhere rather than
719 have two hooks. */
720 length = CGEN_PRINT_INSN (cd, pc, info);
721 if (length > 0)
722 return length;
723 if (length < 0)
724 return -1;
725
726 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
727 return cd->default_insn_bitsize / 8;
728}
GDB Binutils - Deliverables
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