* gdb.base/maint.exp: Treat $EXEEXT as optional in output.
[deliverable/binutils-gdb.git] / opcodes / fr30-ibld.c
CommitLineData
252b5132
RH
1/* Instruction building/extraction support for fr30. -*- C -*-
2
3THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4- the resultant file is machine generated, cgen-ibld.in isn't
5
060d22b0 6Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
252b5132
RH
7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25 Keep that in mind. */
26
27#include "sysdep.h"
0e2ee3ca 28#include <ctype.h>
252b5132
RH
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "fr30-desc.h"
35#include "fr30-opc.h"
36#include "opintl.h"
37
38#undef min
39#define min(a,b) ((a) < (b) ? (a) : (b))
40#undef max
41#define max(a,b) ((a) > (b) ? (a) : (b))
42
43/* Used by the ifield rtx function. */
44#define FLD(f) (fields->f)
45
46static const char * insert_normal
47 PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
48 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
49static const char * insert_insn_normal
50 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
51 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
252b5132
RH
52static int extract_normal
53 PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
54 unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int, bfd_vma, long *));
56static int extract_insn_normal
57 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
58 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
d5b2f4d6 59#if CGEN_INT_INSN_P
6bb95a0f
DB
60static void put_insn_int_value
61 PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
d5b2f4d6 62#endif
0e2ee3ca 63#if ! CGEN_INT_INSN_P
d5b2f4d6
NC
64static CGEN_INLINE void insert_1
65 PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
0e2ee3ca
NC
66static CGEN_INLINE int fill_cache
67 PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
68static CGEN_INLINE long extract_1
69 PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
70 unsigned char *, bfd_vma));
71#endif
252b5132
RH
72\f
73/* Operand insertion. */
74
75#if ! CGEN_INT_INSN_P
76
77/* Subroutine of insert_normal. */
78
79static CGEN_INLINE void
80insert_1 (cd, value, start, length, word_length, bufp)
81 CGEN_CPU_DESC cd;
82 unsigned long value;
83 int start,length,word_length;
84 unsigned char *bufp;
85{
86 unsigned long x,mask;
87 int shift;
252b5132 88
0e2ee3ca 89 x = cgen_get_insn_value (cd, bufp, word_length);
252b5132
RH
90
91 /* Written this way to avoid undefined behaviour. */
92 mask = (((1L << (length - 1)) - 1) << 1) | 1;
93 if (CGEN_INSN_LSB0_P)
94 shift = (start + 1) - length;
95 else
96 shift = (word_length - (start + length));
97 x = (x & ~(mask << shift)) | ((value & mask) << shift);
98
0e2ee3ca 99 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
252b5132
RH
100}
101
102#endif /* ! CGEN_INT_INSN_P */
103
104/* Default insertion routine.
105
106 ATTRS is a mask of the boolean attributes.
107 WORD_OFFSET is the offset in bits from the start of the insn of the value.
108 WORD_LENGTH is the length of the word in bits in which the value resides.
109 START is the starting bit number in the word, architecture origin.
110 LENGTH is the length of VALUE in bits.
111 TOTAL_LENGTH is the total length of the insn in bits.
112
113 The result is an error message or NULL if success. */
114
115/* ??? This duplicates functionality with bfd's howto table and
116 bfd_install_relocation. */
117/* ??? This doesn't handle bfd_vma's. Create another function when
118 necessary. */
119
120static const char *
121insert_normal (cd, value, attrs, word_offset, start, length, word_length,
122 total_length, buffer)
123 CGEN_CPU_DESC cd;
124 long value;
125 unsigned int attrs;
126 unsigned int word_offset, start, length, word_length, total_length;
127 CGEN_INSN_BYTES_PTR buffer;
128{
129 static char errbuf[100];
130 /* Written this way to avoid undefined behaviour. */
131 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
132
133 /* If LENGTH is zero, this operand doesn't contribute to the value. */
134 if (length == 0)
135 return NULL;
136
6bb95a0f 137#if 0
252b5132
RH
138 if (CGEN_INT_INSN_P
139 && word_offset != 0)
140 abort ();
6bb95a0f 141#endif
252b5132
RH
142
143 if (word_length > 32)
144 abort ();
145
146 /* For architectures with insns smaller than the base-insn-bitsize,
147 word_length may be too big. */
148 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
149 {
150 if (word_offset == 0
151 && word_length > total_length)
152 word_length = total_length;
153 }
154
155 /* Ensure VALUE will fit. */
fc7bc883
RH
156 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
157 {
158 long minval = - (1L << (length - 1));
159 unsigned long maxval = mask;
160
161 if ((value > 0 && (unsigned long) value > maxval)
162 || value < minval)
163 {
164 /* xgettext:c-format */
165 sprintf (errbuf,
166 _("operand out of range (%ld not between %ld and %lu)"),
167 value, minval, maxval);
168 return errbuf;
169 }
170 }
171 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
252b5132
RH
172 {
173 unsigned long maxval = mask;
6bb95a0f 174
252b5132
RH
175 if ((unsigned long) value > maxval)
176 {
177 /* xgettext:c-format */
178 sprintf (errbuf,
179 _("operand out of range (%lu not between 0 and %lu)"),
180 value, maxval);
181 return errbuf;
182 }
183 }
184 else
185 {
6bb95a0f 186 if (! cgen_signed_overflow_ok_p (cd))
252b5132 187 {
6bb95a0f
DB
188 long minval = - (1L << (length - 1));
189 long maxval = (1L << (length - 1)) - 1;
190
191 if (value < minval || value > maxval)
192 {
193 sprintf
194 /* xgettext:c-format */
195 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
196 value, minval, maxval);
197 return errbuf;
198 }
252b5132
RH
199 }
200 }
201
202#if CGEN_INT_INSN_P
203
204 {
205 int shift;
206
207 if (CGEN_INSN_LSB0_P)
6bb95a0f 208 shift = (word_offset + start + 1) - length;
252b5132 209 else
6bb95a0f 210 shift = total_length - (word_offset + start + length);
252b5132
RH
211 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
212 }
213
214#else /* ! CGEN_INT_INSN_P */
215
216 {
217 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
218
219 insert_1 (cd, value, start, length, word_length, bufp);
220 }
221
222#endif /* ! CGEN_INT_INSN_P */
223
224 return NULL;
225}
226
227/* Default insn builder (insert handler).
fc7bc883
RH
228 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
229 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
230 recorded in host byte order, otherwise BUFFER is an array of bytes
231 and the value is recorded in target byte order).
252b5132
RH
232 The result is an error message or NULL if success. */
233
234static const char *
235insert_insn_normal (cd, insn, fields, buffer, pc)
236 CGEN_CPU_DESC cd;
237 const CGEN_INSN * insn;
238 CGEN_FIELDS * fields;
239 CGEN_INSN_BYTES_PTR buffer;
240 bfd_vma pc;
241{
242 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
243 unsigned long value;
b3466c39 244 const CGEN_SYNTAX_CHAR_TYPE * syn;
252b5132
RH
245
246 CGEN_INIT_INSERT (cd);
247 value = CGEN_INSN_BASE_VALUE (insn);
248
249 /* If we're recording insns as numbers (rather than a string of bytes),
250 target byte order handling is deferred until later. */
251
252#if CGEN_INT_INSN_P
253
6bb95a0f
DB
254 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
255 CGEN_FIELDS_BITSIZE (fields), value);
252b5132
RH
256
257#else
258
0e2ee3ca 259 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
d5b2f4d6 260 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
252b5132
RH
261 value);
262
263#endif /* ! CGEN_INT_INSN_P */
264
265 /* ??? It would be better to scan the format's fields.
266 Still need to be able to insert a value based on the operand though;
267 e.g. storing a branch displacement that got resolved later.
268 Needs more thought first. */
269
b3466c39 270 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
252b5132
RH
271 {
272 const char *errmsg;
273
274 if (CGEN_SYNTAX_CHAR_P (* syn))
275 continue;
276
277 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
278 fields, buffer, pc);
279 if (errmsg)
280 return errmsg;
281 }
282
283 return NULL;
284}
6bb95a0f 285
d5b2f4d6 286#if CGEN_INT_INSN_P
6bb95a0f
DB
287/* Cover function to store an insn value into an integral insn. Must go here
288 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
289
290static void
291put_insn_int_value (cd, buf, length, insn_length, value)
fc7bc883 292 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
6bb95a0f
DB
293 CGEN_INSN_BYTES_PTR buf;
294 int length;
295 int insn_length;
296 CGEN_INSN_INT value;
297{
298 /* For architectures with insns smaller than the base-insn-bitsize,
299 length may be too big. */
300 if (length > insn_length)
301 *buf = value;
302 else
303 {
304 int shift = insn_length - length;
305 /* Written this way to avoid undefined behaviour. */
306 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
307 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
308 }
309}
d5b2f4d6 310#endif
252b5132
RH
311\f
312/* Operand extraction. */
313
314#if ! CGEN_INT_INSN_P
315
316/* Subroutine of extract_normal.
317 Ensure sufficient bytes are cached in EX_INFO.
318 OFFSET is the offset in bytes from the start of the insn of the value.
319 BYTES is the length of the needed value.
320 Returns 1 for success, 0 for failure. */
321
322static CGEN_INLINE int
323fill_cache (cd, ex_info, offset, bytes, pc)
d5b2f4d6 324 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH
325 CGEN_EXTRACT_INFO *ex_info;
326 int offset, bytes;
327 bfd_vma pc;
328{
329 /* It's doubtful that the middle part has already been fetched so
330 we don't optimize that case. kiss. */
d5b2f4d6 331 unsigned int mask;
252b5132
RH
332 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
333
334 /* First do a quick check. */
335 mask = (1 << bytes) - 1;
336 if (((ex_info->valid >> offset) & mask) == mask)
337 return 1;
338
339 /* Search for the first byte we need to read. */
340 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
341 if (! (mask & ex_info->valid))
342 break;
343
344 if (bytes)
345 {
346 int status;
347
348 pc += offset;
349 status = (*info->read_memory_func)
350 (pc, ex_info->insn_bytes + offset, bytes, info);
351
352 if (status != 0)
353 {
354 (*info->memory_error_func) (status, pc, info);
355 return 0;
356 }
357
358 ex_info->valid |= ((1 << bytes) - 1) << offset;
359 }
360
361 return 1;
362}
363
364/* Subroutine of extract_normal. */
365
366static CGEN_INLINE long
367extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
368 CGEN_CPU_DESC cd;
d5b2f4d6 369 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
252b5132
RH
370 int start,length,word_length;
371 unsigned char *bufp;
d5b2f4d6 372 bfd_vma pc ATTRIBUTE_UNUSED;
252b5132 373{
b3466c39 374 unsigned long x;
252b5132 375 int shift;
0e2ee3ca 376#if 0
252b5132
RH
377 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
378
0e2ee3ca
NC
379 x = cgen_get_insn_value (cd, bufp, word_length);
380#endif
252b5132
RH
381 if (CGEN_INSN_LSB0_P)
382 shift = (start + 1) - length;
383 else
384 shift = (word_length - (start + length));
b3466c39 385 return x >> shift;
252b5132
RH
386}
387
388#endif /* ! CGEN_INT_INSN_P */
389
390/* Default extraction routine.
391
392 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
393 or sometimes less for cases like the m32r where the base insn size is 32
394 but some insns are 16 bits.
395 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
396 but for generality we take a bitmask of all of them.
397 WORD_OFFSET is the offset in bits from the start of the insn of the value.
398 WORD_LENGTH is the length of the word in bits in which the value resides.
399 START is the starting bit number in the word, architecture origin.
400 LENGTH is the length of VALUE in bits.
401 TOTAL_LENGTH is the total length of the insn in bits.
402
403 Returns 1 for success, 0 for failure. */
404
405/* ??? The return code isn't properly used. wip. */
406
407/* ??? This doesn't handle bfd_vma's. Create another function when
408 necessary. */
409
410static int
411extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
412 word_length, total_length, pc, valuep)
413 CGEN_CPU_DESC cd;
6bb95a0f 414#if ! CGEN_INT_INSN_P
252b5132 415 CGEN_EXTRACT_INFO *ex_info;
6bb95a0f
DB
416#else
417 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
418#endif
252b5132
RH
419 CGEN_INSN_INT insn_value;
420 unsigned int attrs;
421 unsigned int word_offset, start, length, word_length, total_length;
6bb95a0f 422#if ! CGEN_INT_INSN_P
252b5132 423 bfd_vma pc;
6bb95a0f
DB
424#else
425 bfd_vma pc ATTRIBUTE_UNUSED;
426#endif
252b5132
RH
427 long *valuep;
428{
fc7bc883 429 long value, mask;
252b5132
RH
430
431 /* If LENGTH is zero, this operand doesn't contribute to the value
432 so give it a standard value of zero. */
433 if (length == 0)
434 {
435 *valuep = 0;
436 return 1;
437 }
438
6bb95a0f 439#if 0
252b5132
RH
440 if (CGEN_INT_INSN_P
441 && word_offset != 0)
442 abort ();
6bb95a0f 443#endif
252b5132
RH
444
445 if (word_length > 32)
446 abort ();
447
448 /* For architectures with insns smaller than the insn-base-bitsize,
449 word_length may be too big. */
450 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
451 {
452 if (word_offset == 0
453 && word_length > total_length)
454 word_length = total_length;
455 }
456
fc7bc883 457 /* Does the value reside in INSN_VALUE, and at the right alignment? */
252b5132 458
fc7bc883 459 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
252b5132 460 {
252b5132 461 if (CGEN_INSN_LSB0_P)
6bb95a0f 462 value = insn_value >> ((word_offset + start + 1) - length);
252b5132 463 else
6bb95a0f 464 value = insn_value >> (total_length - ( word_offset + start + length));
252b5132
RH
465 }
466
467#if ! CGEN_INT_INSN_P
468
469 else
470 {
471 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
472
473 if (word_length > 32)
474 abort ();
475
476 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
477 return 0;
478
479 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
480 }
481
482#endif /* ! CGEN_INT_INSN_P */
483
b3466c39
DB
484 /* Written this way to avoid undefined behaviour. */
485 mask = (((1L << (length - 1)) - 1) << 1) | 1;
486
487 value &= mask;
488 /* sign extend? */
489 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
490 && (value & (1L << (length - 1))))
491 value |= ~mask;
492
252b5132
RH
493 *valuep = value;
494
495 return 1;
496}
497
498/* Default insn extractor.
499
500 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
501 The extracted fields are stored in FIELDS.
502 EX_INFO is used to handle reading variable length insns.
503 Return the length of the insn in bits, or 0 if no match,
504 or -1 if an error occurs fetching data (memory_error_func will have
505 been called). */
506
507static int
508extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
509 CGEN_CPU_DESC cd;
510 const CGEN_INSN *insn;
511 CGEN_EXTRACT_INFO *ex_info;
512 CGEN_INSN_INT insn_value;
513 CGEN_FIELDS *fields;
514 bfd_vma pc;
515{
516 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
b3466c39 517 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH
518
519 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
520
521 CGEN_INIT_EXTRACT (cd);
522
523 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
524 {
525 int length;
526
527 if (CGEN_SYNTAX_CHAR_P (*syn))
528 continue;
529
530 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
531 ex_info, insn_value, fields, pc);
532 if (length <= 0)
533 return length;
534 }
535
536 /* We recognized and successfully extracted this insn. */
537 return CGEN_INSN_BITSIZE (insn);
538}
539\f
540/* machine generated code added here */
541
0e2ee3ca
NC
542const char * fr30_cgen_insert_operand
543 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
544
252b5132
RH
545/* Main entry point for operand insertion.
546
547 This function is basically just a big switch statement. Earlier versions
548 used tables to look up the function to use, but
549 - if the table contains both assembler and disassembler functions then
550 the disassembler contains much of the assembler and vice-versa,
551 - there's a lot of inlining possibilities as things grow,
552 - using a switch statement avoids the function call overhead.
553
554 This function could be moved into `parse_insn_normal', but keeping it
555 separate makes clear the interface between `parse_insn_normal' and each of
556 the handlers. It's also needed by GAS to insert operands that couldn't be
557 resolved during parsing.
558*/
559
560const char *
561fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
562 CGEN_CPU_DESC cd;
563 int opindex;
564 CGEN_FIELDS * fields;
565 CGEN_INSN_BYTES_PTR buffer;
0e2ee3ca 566 bfd_vma pc ATTRIBUTE_UNUSED;
252b5132 567{
eb1b03df 568 const char * errmsg = NULL;
252b5132
RH
569 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
570
571 switch (opindex)
572 {
573 case FR30_OPERAND_CRI :
574 errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer);
575 break;
576 case FR30_OPERAND_CRJ :
577 errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer);
578 break;
579 case FR30_OPERAND_R13 :
252b5132
RH
580 break;
581 case FR30_OPERAND_R14 :
252b5132
RH
582 break;
583 case FR30_OPERAND_R15 :
252b5132
RH
584 break;
585 case FR30_OPERAND_RI :
586 errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer);
587 break;
588 case FR30_OPERAND_RIC :
589 errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer);
590 break;
591 case FR30_OPERAND_RJ :
592 errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer);
593 break;
594 case FR30_OPERAND_RJC :
595 errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer);
596 break;
597 case FR30_OPERAND_RS1 :
598 errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer);
599 break;
600 case FR30_OPERAND_RS2 :
601 errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer);
602 break;
603 case FR30_OPERAND_CC :
604 errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer);
605 break;
606 case FR30_OPERAND_CCC :
607 errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer);
608 break;
609 case FR30_OPERAND_DIR10 :
610 {
611 long value = fields->f_dir10;
612 value = ((unsigned int) (value) >> (2));
613 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
614 }
615 break;
616 case FR30_OPERAND_DIR8 :
617 errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer);
618 break;
619 case FR30_OPERAND_DIR9 :
620 {
621 long value = fields->f_dir9;
622 value = ((unsigned int) (value) >> (1));
623 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
624 }
625 break;
626 case FR30_OPERAND_DISP10 :
627 {
628 long value = fields->f_disp10;
629 value = ((int) (value) >> (2));
630 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
631 }
632 break;
633 case FR30_OPERAND_DISP8 :
634 errmsg = insert_normal (cd, fields->f_disp8, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
635 break;
636 case FR30_OPERAND_DISP9 :
637 {
638 long value = fields->f_disp9;
639 value = ((int) (value) >> (1));
640 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
641 }
642 break;
643 case FR30_OPERAND_I20 :
644 {
645{
646 FLD (f_i20_4) = ((unsigned int) (FLD (f_i20)) >> (16));
647 FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
648}
649 errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
650 if (errmsg)
651 break;
652 errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer);
653 if (errmsg)
654 break;
655 }
656 break;
657 case FR30_OPERAND_I32 :
658 errmsg = insert_normal (cd, fields->f_i32, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, buffer);
659 break;
660 case FR30_OPERAND_I8 :
661 errmsg = insert_normal (cd, fields->f_i8, 0, 0, 4, 8, 16, total_length, buffer);
662 break;
663 case FR30_OPERAND_LABEL12 :
664 {
665 long value = fields->f_rel12;
666 value = ((int) (((value) - (((pc) + (2))))) >> (1));
667 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
668 }
669 break;
670 case FR30_OPERAND_LABEL9 :
671 {
672 long value = fields->f_rel9;
673 value = ((int) (((value) - (((pc) + (2))))) >> (1));
674 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
675 }
676 break;
677 case FR30_OPERAND_M4 :
678 {
679 long value = fields->f_m4;
680 value = ((value) & (15));
681 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
682 }
683 break;
684 case FR30_OPERAND_PS :
252b5132
RH
685 break;
686 case FR30_OPERAND_REGLIST_HI_LD :
687 errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer);
688 break;
689 case FR30_OPERAND_REGLIST_HI_ST :
690 errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer);
691 break;
692 case FR30_OPERAND_REGLIST_LOW_LD :
693 errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer);
694 break;
695 case FR30_OPERAND_REGLIST_LOW_ST :
696 errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer);
697 break;
698 case FR30_OPERAND_S10 :
699 {
700 long value = fields->f_s10;
701 value = ((int) (value) >> (2));
702 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
703 }
704 break;
705 case FR30_OPERAND_U10 :
706 {
707 long value = fields->f_u10;
708 value = ((unsigned int) (value) >> (2));
709 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
710 }
711 break;
712 case FR30_OPERAND_U4 :
713 errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer);
714 break;
715 case FR30_OPERAND_U4C :
716 errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer);
717 break;
718 case FR30_OPERAND_U8 :
719 errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer);
720 break;
721 case FR30_OPERAND_UDISP6 :
722 {
723 long value = fields->f_udisp6;
724 value = ((unsigned int) (value) >> (2));
725 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
726 }
727 break;
728
729 default :
730 /* xgettext:c-format */
731 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
732 opindex);
733 abort ();
734 }
735
736 return errmsg;
737}
738
0e2ee3ca
NC
739int fr30_cgen_extract_operand
740 PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
741 CGEN_FIELDS *, bfd_vma));
742
252b5132 743/* Main entry point for operand extraction.
eb1b03df
DE
744 The result is <= 0 for error, >0 for success.
745 ??? Actual values aren't well defined right now.
252b5132
RH
746
747 This function is basically just a big switch statement. Earlier versions
748 used tables to look up the function to use, but
749 - if the table contains both assembler and disassembler functions then
750 the disassembler contains much of the assembler and vice-versa,
751 - there's a lot of inlining possibilities as things grow,
752 - using a switch statement avoids the function call overhead.
753
754 This function could be moved into `print_insn_normal', but keeping it
755 separate makes clear the interface between `print_insn_normal' and each of
756 the handlers.
757*/
758
759int
760fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
761 CGEN_CPU_DESC cd;
762 int opindex;
763 CGEN_EXTRACT_INFO *ex_info;
764 CGEN_INSN_INT insn_value;
765 CGEN_FIELDS * fields;
766 bfd_vma pc;
767{
eb1b03df
DE
768 /* Assume success (for those operands that are nops). */
769 int length = 1;
252b5132
RH
770 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
771
772 switch (opindex)
773 {
774 case FR30_OPERAND_CRI :
775 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi);
776 break;
777 case FR30_OPERAND_CRJ :
778 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj);
779 break;
780 case FR30_OPERAND_R13 :
252b5132
RH
781 break;
782 case FR30_OPERAND_R14 :
252b5132
RH
783 break;
784 case FR30_OPERAND_R15 :
252b5132
RH
785 break;
786 case FR30_OPERAND_RI :
787 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri);
788 break;
789 case FR30_OPERAND_RIC :
790 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric);
791 break;
792 case FR30_OPERAND_RJ :
793 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj);
794 break;
795 case FR30_OPERAND_RJC :
796 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc);
797 break;
798 case FR30_OPERAND_RS1 :
799 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1);
800 break;
801 case FR30_OPERAND_RS2 :
802 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2);
803 break;
804 case FR30_OPERAND_CC :
805 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc);
806 break;
807 case FR30_OPERAND_CCC :
808 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc);
809 break;
810 case FR30_OPERAND_DIR10 :
811 {
812 long value;
813 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
814 value = ((value) << (2));
815 fields->f_dir10 = value;
816 }
817 break;
818 case FR30_OPERAND_DIR8 :
819 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8);
820 break;
821 case FR30_OPERAND_DIR9 :
822 {
823 long value;
824 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
825 value = ((value) << (1));
826 fields->f_dir9 = value;
827 }
828 break;
829 case FR30_OPERAND_DISP10 :
830 {
831 long value;
832 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
833 value = ((value) << (2));
834 fields->f_disp10 = value;
835 }
836 break;
837 case FR30_OPERAND_DISP8 :
838 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
839 break;
840 case FR30_OPERAND_DISP9 :
841 {
842 long value;
843 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
844 value = ((value) << (1));
845 fields->f_disp9 = value;
846 }
847 break;
848 case FR30_OPERAND_I20 :
849 {
850 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
6bb95a0f 851 if (length <= 0) break;
252b5132 852 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16);
6bb95a0f 853 if (length <= 0) break;
252b5132
RH
854{
855 FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16)));
856}
857 }
858 break;
859 case FR30_OPERAND_I32 :
860 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, pc, & fields->f_i32);
861 break;
862 case FR30_OPERAND_I8 :
863 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8);
864 break;
865 case FR30_OPERAND_LABEL12 :
866 {
867 long value;
868 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value);
869 value = ((((value) << (1))) + (((pc) + (2))));
870 fields->f_rel12 = value;
871 }
872 break;
873 case FR30_OPERAND_LABEL9 :
874 {
875 long value;
876 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value);
877 value = ((((value) << (1))) + (((pc) + (2))));
878 fields->f_rel9 = value;
879 }
880 break;
881 case FR30_OPERAND_M4 :
882 {
883 long value;
884 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
885 value = ((value) | (((-1) << (4))));
886 fields->f_m4 = value;
887 }
888 break;
889 case FR30_OPERAND_PS :
252b5132
RH
890 break;
891 case FR30_OPERAND_REGLIST_HI_LD :
892 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld);
893 break;
894 case FR30_OPERAND_REGLIST_HI_ST :
895 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st);
896 break;
897 case FR30_OPERAND_REGLIST_LOW_LD :
898 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld);
899 break;
900 case FR30_OPERAND_REGLIST_LOW_ST :
901 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st);
902 break;
903 case FR30_OPERAND_S10 :
904 {
905 long value;
906 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
907 value = ((value) << (2));
908 fields->f_s10 = value;
909 }
910 break;
911 case FR30_OPERAND_U10 :
912 {
913 long value;
914 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
915 value = ((value) << (2));
916 fields->f_u10 = value;
917 }
918 break;
919 case FR30_OPERAND_U4 :
920 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4);
921 break;
922 case FR30_OPERAND_U4C :
923 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c);
924 break;
925 case FR30_OPERAND_U8 :
926 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8);
927 break;
928 case FR30_OPERAND_UDISP6 :
929 {
930 long value;
931 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
932 value = ((value) << (2));
933 fields->f_udisp6 = value;
934 }
935 break;
936
937 default :
938 /* xgettext:c-format */
939 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
940 opindex);
941 abort ();
942 }
943
944 return length;
945}
946
947cgen_insert_fn * const fr30_cgen_insert_handlers[] =
948{
949 insert_insn_normal,
950};
951
952cgen_extract_fn * const fr30_cgen_extract_handlers[] =
953{
954 extract_insn_normal,
955};
956
0e2ee3ca
NC
957int fr30_cgen_get_int_operand
958 PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
959bfd_vma fr30_cgen_get_vma_operand
960 PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
961
252b5132
RH
962/* Getting values from cgen_fields is handled by a collection of functions.
963 They are distinguished by the type of the VALUE argument they return.
964 TODO: floating point, inlining support, remove cases where result type
965 not appropriate. */
966
967int
968fr30_cgen_get_int_operand (cd, opindex, fields)
d5b2f4d6 969 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH
970 int opindex;
971 const CGEN_FIELDS * fields;
972{
973 int value;
974
975 switch (opindex)
976 {
977 case FR30_OPERAND_CRI :
978 value = fields->f_CRi;
979 break;
980 case FR30_OPERAND_CRJ :
981 value = fields->f_CRj;
982 break;
983 case FR30_OPERAND_R13 :
eb1b03df 984 value = 0;
252b5132
RH
985 break;
986 case FR30_OPERAND_R14 :
eb1b03df 987 value = 0;
252b5132
RH
988 break;
989 case FR30_OPERAND_R15 :
eb1b03df 990 value = 0;
252b5132
RH
991 break;
992 case FR30_OPERAND_RI :
993 value = fields->f_Ri;
994 break;
995 case FR30_OPERAND_RIC :
996 value = fields->f_Ric;
997 break;
998 case FR30_OPERAND_RJ :
999 value = fields->f_Rj;
1000 break;
1001 case FR30_OPERAND_RJC :
1002 value = fields->f_Rjc;
1003 break;
1004 case FR30_OPERAND_RS1 :
1005 value = fields->f_Rs1;
1006 break;
1007 case FR30_OPERAND_RS2 :
1008 value = fields->f_Rs2;
1009 break;
1010 case FR30_OPERAND_CC :
1011 value = fields->f_cc;
1012 break;
1013 case FR30_OPERAND_CCC :
1014 value = fields->f_ccc;
1015 break;
1016 case FR30_OPERAND_DIR10 :
1017 value = fields->f_dir10;
1018 break;
1019 case FR30_OPERAND_DIR8 :
1020 value = fields->f_dir8;
1021 break;
1022 case FR30_OPERAND_DIR9 :
1023 value = fields->f_dir9;
1024 break;
1025 case FR30_OPERAND_DISP10 :
1026 value = fields->f_disp10;
1027 break;
1028 case FR30_OPERAND_DISP8 :
1029 value = fields->f_disp8;
1030 break;
1031 case FR30_OPERAND_DISP9 :
1032 value = fields->f_disp9;
1033 break;
1034 case FR30_OPERAND_I20 :
1035 value = fields->f_i20;
1036 break;
1037 case FR30_OPERAND_I32 :
1038 value = fields->f_i32;
1039 break;
1040 case FR30_OPERAND_I8 :
1041 value = fields->f_i8;
1042 break;
1043 case FR30_OPERAND_LABEL12 :
1044 value = fields->f_rel12;
1045 break;
1046 case FR30_OPERAND_LABEL9 :
1047 value = fields->f_rel9;
1048 break;
1049 case FR30_OPERAND_M4 :
1050 value = fields->f_m4;
1051 break;
1052 case FR30_OPERAND_PS :
eb1b03df 1053 value = 0;
252b5132
RH
1054 break;
1055 case FR30_OPERAND_REGLIST_HI_LD :
1056 value = fields->f_reglist_hi_ld;
1057 break;
1058 case FR30_OPERAND_REGLIST_HI_ST :
1059 value = fields->f_reglist_hi_st;
1060 break;
1061 case FR30_OPERAND_REGLIST_LOW_LD :
1062 value = fields->f_reglist_low_ld;
1063 break;
1064 case FR30_OPERAND_REGLIST_LOW_ST :
1065 value = fields->f_reglist_low_st;
1066 break;
1067 case FR30_OPERAND_S10 :
1068 value = fields->f_s10;
1069 break;
1070 case FR30_OPERAND_U10 :
1071 value = fields->f_u10;
1072 break;
1073 case FR30_OPERAND_U4 :
1074 value = fields->f_u4;
1075 break;
1076 case FR30_OPERAND_U4C :
1077 value = fields->f_u4c;
1078 break;
1079 case FR30_OPERAND_U8 :
1080 value = fields->f_u8;
1081 break;
1082 case FR30_OPERAND_UDISP6 :
1083 value = fields->f_udisp6;
1084 break;
1085
1086 default :
1087 /* xgettext:c-format */
1088 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
1089 opindex);
1090 abort ();
1091 }
1092
1093 return value;
1094}
1095
1096bfd_vma
1097fr30_cgen_get_vma_operand (cd, opindex, fields)
d5b2f4d6 1098 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH
1099 int opindex;
1100 const CGEN_FIELDS * fields;
1101{
1102 bfd_vma value;
1103
1104 switch (opindex)
1105 {
1106 case FR30_OPERAND_CRI :
1107 value = fields->f_CRi;
1108 break;
1109 case FR30_OPERAND_CRJ :
1110 value = fields->f_CRj;
1111 break;
1112 case FR30_OPERAND_R13 :
eb1b03df 1113 value = 0;
252b5132
RH
1114 break;
1115 case FR30_OPERAND_R14 :
eb1b03df 1116 value = 0;
252b5132
RH
1117 break;
1118 case FR30_OPERAND_R15 :
eb1b03df 1119 value = 0;
252b5132
RH
1120 break;
1121 case FR30_OPERAND_RI :
1122 value = fields->f_Ri;
1123 break;
1124 case FR30_OPERAND_RIC :
1125 value = fields->f_Ric;
1126 break;
1127 case FR30_OPERAND_RJ :
1128 value = fields->f_Rj;
1129 break;
1130 case FR30_OPERAND_RJC :
1131 value = fields->f_Rjc;
1132 break;
1133 case FR30_OPERAND_RS1 :
1134 value = fields->f_Rs1;
1135 break;
1136 case FR30_OPERAND_RS2 :
1137 value = fields->f_Rs2;
1138 break;
1139 case FR30_OPERAND_CC :
1140 value = fields->f_cc;
1141 break;
1142 case FR30_OPERAND_CCC :
1143 value = fields->f_ccc;
1144 break;
1145 case FR30_OPERAND_DIR10 :
1146 value = fields->f_dir10;
1147 break;
1148 case FR30_OPERAND_DIR8 :
1149 value = fields->f_dir8;
1150 break;
1151 case FR30_OPERAND_DIR9 :
1152 value = fields->f_dir9;
1153 break;
1154 case FR30_OPERAND_DISP10 :
1155 value = fields->f_disp10;
1156 break;
1157 case FR30_OPERAND_DISP8 :
1158 value = fields->f_disp8;
1159 break;
1160 case FR30_OPERAND_DISP9 :
1161 value = fields->f_disp9;
1162 break;
1163 case FR30_OPERAND_I20 :
1164 value = fields->f_i20;
1165 break;
1166 case FR30_OPERAND_I32 :
1167 value = fields->f_i32;
1168 break;
1169 case FR30_OPERAND_I8 :
1170 value = fields->f_i8;
1171 break;
1172 case FR30_OPERAND_LABEL12 :
1173 value = fields->f_rel12;
1174 break;
1175 case FR30_OPERAND_LABEL9 :
1176 value = fields->f_rel9;
1177 break;
1178 case FR30_OPERAND_M4 :
1179 value = fields->f_m4;
1180 break;
1181 case FR30_OPERAND_PS :
eb1b03df 1182 value = 0;
252b5132
RH
1183 break;
1184 case FR30_OPERAND_REGLIST_HI_LD :
1185 value = fields->f_reglist_hi_ld;
1186 break;
1187 case FR30_OPERAND_REGLIST_HI_ST :
1188 value = fields->f_reglist_hi_st;
1189 break;
1190 case FR30_OPERAND_REGLIST_LOW_LD :
1191 value = fields->f_reglist_low_ld;
1192 break;
1193 case FR30_OPERAND_REGLIST_LOW_ST :
1194 value = fields->f_reglist_low_st;
1195 break;
1196 case FR30_OPERAND_S10 :
1197 value = fields->f_s10;
1198 break;
1199 case FR30_OPERAND_U10 :
1200 value = fields->f_u10;
1201 break;
1202 case FR30_OPERAND_U4 :
1203 value = fields->f_u4;
1204 break;
1205 case FR30_OPERAND_U4C :
1206 value = fields->f_u4c;
1207 break;
1208 case FR30_OPERAND_U8 :
1209 value = fields->f_u8;
1210 break;
1211 case FR30_OPERAND_UDISP6 :
1212 value = fields->f_udisp6;
1213 break;
1214
1215 default :
1216 /* xgettext:c-format */
1217 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1218 opindex);
1219 abort ();
1220 }
1221
1222 return value;
1223}
1224
0e2ee3ca
NC
1225void fr30_cgen_set_int_operand
1226 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
1227void fr30_cgen_set_vma_operand
1228 PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
1229
252b5132
RH
1230/* Stuffing values in cgen_fields is handled by a collection of functions.
1231 They are distinguished by the type of the VALUE argument they accept.
1232 TODO: floating point, inlining support, remove cases where argument type
1233 not appropriate. */
1234
1235void
1236fr30_cgen_set_int_operand (cd, opindex, fields, value)
d5b2f4d6 1237 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH
1238 int opindex;
1239 CGEN_FIELDS * fields;
1240 int value;
1241{
1242 switch (opindex)
1243 {
1244 case FR30_OPERAND_CRI :
1245 fields->f_CRi = value;
1246 break;
1247 case FR30_OPERAND_CRJ :
1248 fields->f_CRj = value;
1249 break;
1250 case FR30_OPERAND_R13 :
252b5132
RH
1251 break;
1252 case FR30_OPERAND_R14 :
252b5132
RH
1253 break;
1254 case FR30_OPERAND_R15 :
252b5132
RH
1255 break;
1256 case FR30_OPERAND_RI :
1257 fields->f_Ri = value;
1258 break;
1259 case FR30_OPERAND_RIC :
1260 fields->f_Ric = value;
1261 break;
1262 case FR30_OPERAND_RJ :
1263 fields->f_Rj = value;
1264 break;
1265 case FR30_OPERAND_RJC :
1266 fields->f_Rjc = value;
1267 break;
1268 case FR30_OPERAND_RS1 :
1269 fields->f_Rs1 = value;
1270 break;
1271 case FR30_OPERAND_RS2 :
1272 fields->f_Rs2 = value;
1273 break;
1274 case FR30_OPERAND_CC :
1275 fields->f_cc = value;
1276 break;
1277 case FR30_OPERAND_CCC :
1278 fields->f_ccc = value;
1279 break;
1280 case FR30_OPERAND_DIR10 :
1281 fields->f_dir10 = value;
1282 break;
1283 case FR30_OPERAND_DIR8 :
1284 fields->f_dir8 = value;
1285 break;
1286 case FR30_OPERAND_DIR9 :
1287 fields->f_dir9 = value;
1288 break;
1289 case FR30_OPERAND_DISP10 :
1290 fields->f_disp10 = value;
1291 break;
1292 case FR30_OPERAND_DISP8 :
1293 fields->f_disp8 = value;
1294 break;
1295 case FR30_OPERAND_DISP9 :
1296 fields->f_disp9 = value;
1297 break;
1298 case FR30_OPERAND_I20 :
1299 fields->f_i20 = value;
1300 break;
1301 case FR30_OPERAND_I32 :
1302 fields->f_i32 = value;
1303 break;
1304 case FR30_OPERAND_I8 :
1305 fields->f_i8 = value;
1306 break;
1307 case FR30_OPERAND_LABEL12 :
1308 fields->f_rel12 = value;
1309 break;
1310 case FR30_OPERAND_LABEL9 :
1311 fields->f_rel9 = value;
1312 break;
1313 case FR30_OPERAND_M4 :
1314 fields->f_m4 = value;
1315 break;
1316 case FR30_OPERAND_PS :
252b5132
RH
1317 break;
1318 case FR30_OPERAND_REGLIST_HI_LD :
1319 fields->f_reglist_hi_ld = value;
1320 break;
1321 case FR30_OPERAND_REGLIST_HI_ST :
1322 fields->f_reglist_hi_st = value;
1323 break;
1324 case FR30_OPERAND_REGLIST_LOW_LD :
1325 fields->f_reglist_low_ld = value;
1326 break;
1327 case FR30_OPERAND_REGLIST_LOW_ST :
1328 fields->f_reglist_low_st = value;
1329 break;
1330 case FR30_OPERAND_S10 :
1331 fields->f_s10 = value;
1332 break;
1333 case FR30_OPERAND_U10 :
1334 fields->f_u10 = value;
1335 break;
1336 case FR30_OPERAND_U4 :
1337 fields->f_u4 = value;
1338 break;
1339 case FR30_OPERAND_U4C :
1340 fields->f_u4c = value;
1341 break;
1342 case FR30_OPERAND_U8 :
1343 fields->f_u8 = value;
1344 break;
1345 case FR30_OPERAND_UDISP6 :
1346 fields->f_udisp6 = value;
1347 break;
1348
1349 default :
1350 /* xgettext:c-format */
1351 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1352 opindex);
1353 abort ();
1354 }
1355}
1356
1357void
1358fr30_cgen_set_vma_operand (cd, opindex, fields, value)
d5b2f4d6 1359 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
252b5132
RH
1360 int opindex;
1361 CGEN_FIELDS * fields;
1362 bfd_vma value;
1363{
1364 switch (opindex)
1365 {
1366 case FR30_OPERAND_CRI :
1367 fields->f_CRi = value;
1368 break;
1369 case FR30_OPERAND_CRJ :
1370 fields->f_CRj = value;
1371 break;
1372 case FR30_OPERAND_R13 :
252b5132
RH
1373 break;
1374 case FR30_OPERAND_R14 :
252b5132
RH
1375 break;
1376 case FR30_OPERAND_R15 :
252b5132
RH
1377 break;
1378 case FR30_OPERAND_RI :
1379 fields->f_Ri = value;
1380 break;
1381 case FR30_OPERAND_RIC :
1382 fields->f_Ric = value;
1383 break;
1384 case FR30_OPERAND_RJ :
1385 fields->f_Rj = value;
1386 break;
1387 case FR30_OPERAND_RJC :
1388 fields->f_Rjc = value;
1389 break;
1390 case FR30_OPERAND_RS1 :
1391 fields->f_Rs1 = value;
1392 break;
1393 case FR30_OPERAND_RS2 :
1394 fields->f_Rs2 = value;
1395 break;
1396 case FR30_OPERAND_CC :
1397 fields->f_cc = value;
1398 break;
1399 case FR30_OPERAND_CCC :
1400 fields->f_ccc = value;
1401 break;
1402 case FR30_OPERAND_DIR10 :
1403 fields->f_dir10 = value;
1404 break;
1405 case FR30_OPERAND_DIR8 :
1406 fields->f_dir8 = value;
1407 break;
1408 case FR30_OPERAND_DIR9 :
1409 fields->f_dir9 = value;
1410 break;
1411 case FR30_OPERAND_DISP10 :
1412 fields->f_disp10 = value;
1413 break;
1414 case FR30_OPERAND_DISP8 :
1415 fields->f_disp8 = value;
1416 break;
1417 case FR30_OPERAND_DISP9 :
1418 fields->f_disp9 = value;
1419 break;
1420 case FR30_OPERAND_I20 :
1421 fields->f_i20 = value;
1422 break;
1423 case FR30_OPERAND_I32 :
1424 fields->f_i32 = value;
1425 break;
1426 case FR30_OPERAND_I8 :
1427 fields->f_i8 = value;
1428 break;
1429 case FR30_OPERAND_LABEL12 :
1430 fields->f_rel12 = value;
1431 break;
1432 case FR30_OPERAND_LABEL9 :
1433 fields->f_rel9 = value;
1434 break;
1435 case FR30_OPERAND_M4 :
1436 fields->f_m4 = value;
1437 break;
1438 case FR30_OPERAND_PS :
252b5132
RH
1439 break;
1440 case FR30_OPERAND_REGLIST_HI_LD :
1441 fields->f_reglist_hi_ld = value;
1442 break;
1443 case FR30_OPERAND_REGLIST_HI_ST :
1444 fields->f_reglist_hi_st = value;
1445 break;
1446 case FR30_OPERAND_REGLIST_LOW_LD :
1447 fields->f_reglist_low_ld = value;
1448 break;
1449 case FR30_OPERAND_REGLIST_LOW_ST :
1450 fields->f_reglist_low_st = value;
1451 break;
1452 case FR30_OPERAND_S10 :
1453 fields->f_s10 = value;
1454 break;
1455 case FR30_OPERAND_U10 :
1456 fields->f_u10 = value;
1457 break;
1458 case FR30_OPERAND_U4 :
1459 fields->f_u4 = value;
1460 break;
1461 case FR30_OPERAND_U4C :
1462 fields->f_u4c = value;
1463 break;
1464 case FR30_OPERAND_U8 :
1465 fields->f_u8 = value;
1466 break;
1467 case FR30_OPERAND_UDISP6 :
1468 fields->f_udisp6 = value;
1469 break;
1470
1471 default :
1472 /* xgettext:c-format */
1473 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1474 opindex);
1475 abort ();
1476 }
1477}
1478
1479/* Function to call before using the instruction builder tables. */
1480
1481void
1482fr30_cgen_init_ibld_table (cd)
1483 CGEN_CPU_DESC cd;
1484{
1485 cd->insert_handlers = & fr30_cgen_insert_handlers[0];
1486 cd->extract_handlers = & fr30_cgen_extract_handlers[0];
1487
1488 cd->insert_operand = fr30_cgen_insert_operand;
1489 cd->extract_operand = fr30_cgen_extract_operand;
1490
1491 cd->get_int_operand = fr30_cgen_get_int_operand;
1492 cd->set_int_operand = fr30_cgen_set_int_operand;
1493 cd->get_vma_operand = fr30_cgen_get_vma_operand;
1494 cd->set_vma_operand = fr30_cgen_set_vma_operand;
1495}
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