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Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
CommitLineData
a86481d3
DB		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6Copyright (C) 1998 Free Software Foundation, Inc.
7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "sysdep.h"
25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
29#include "symcat.h"
30#include "fr30-opc.h"
31#include "opintl.h"
32
33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
40
41/* Cover function to read and properly byteswap an insn value. */
42
43CGEN_INSN_INT
44cgen_get_insn_value (od, buf, length)
45 CGEN_OPCODE_DESC od;
46 unsigned char *buf;
47 int length;
48{
49 CGEN_INSN_INT value;
50
51 switch (length)
52 {
53 case 8:
54 value = *buf;
55 break;
56 case 16:
57 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
58 value = bfd_getb16 (buf);
59 else
60 value = bfd_getl16 (buf);
61 break;
62 case 32:
63 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
64 value = bfd_getb32 (buf);
65 else
66 value = bfd_getl32 (buf);
67 break;
68 default:
69 abort ();
70 }
71
72 return value;
73}
74
75/* Cover function to store an insn value properly byteswapped. */
76
77void
78cgen_put_insn_value (od, buf, length, value)
79 CGEN_OPCODE_DESC od;
80 unsigned char *buf;
81 int length;
82 CGEN_INSN_INT value;
83{
84 switch (length)
85 {
86 case 8:
87 buf[0] = value;
88 break;
89 case 16:
90 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
91 bfd_putb16 (value, buf);
92 else
93 bfd_putl16 (value, buf);
94 break;
95 case 32:
96 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
97 bfd_putb32 (value, buf);
98 else
99 bfd_putl32 (value, buf);
100 break;
101 default:
102 abort ();
103 }
104}
105
106/* Look up instruction INSN_VALUE and extract its fields.
107 INSN, if non-null, is the insn table entry.
108 Otherwise INSN_VALUE is examined to compute it.
109 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
110 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
111 If INSN != NULL, LENGTH must be valid.
112 ALIAS_P is non-zero if alias insns are to be included in the search.
113
114 The result a pointer to the insn table entry, or NULL if the instruction
115 wasn't recognized. */
116
117const CGEN_INSN *
118fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
119 CGEN_OPCODE_DESC od;
120 const CGEN_INSN *insn;
121 CGEN_INSN_BYTES insn_value;
122 int length;
123 CGEN_FIELDS *fields;
124 int alias_p;
125{
126 unsigned char buf[16];
127 unsigned char *bufp;
128 unsigned int base_insn;
129#if CGEN_INT_INSN_P
130 CGEN_EXTRACT_INFO *info = NULL;
131#else
132 CGEN_EXTRACT_INFO ex_info;
133 CGEN_EXTRACT_INFO *info = &ex_info;
134#endif
135
136#if ! CGEN_INT_INSN_P
137 ex_info.dis_info = NULL;
138 ex_info.bytes = insn_value;
139 ex_info.valid = -1;
140#endif
141
142 if (!insn)
143 {
144 const CGEN_INSN_LIST *insn_list;
145
146#if CGEN_INT_INSN_P
147 cgen_put_insn_value (od, buf, length, insn_value);
148 bufp = buf;
149 base_insn = insn_value; /*???*/
150#else
151 base_insn = cgen_get_insn_value (od, buf, length);
152 bufp = insn_value;
153#endif
154
155 /* The instructions are stored in hash lists.
156 Pick the first one and keep trying until we find the right one. */
157
158 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
159 while (insn_list != NULL)
160 {
161 insn = insn_list->insn;
162
163 if (alias_p
164 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
165 {
166 /* Basic bit mask must be correct. */
167 /* ??? May wish to allow target to defer this check until the
168 extract handler. */
169 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
170 {
171 /* ??? 0 is passed for `pc' */
172 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
173 insn_value, fields,
174 (bfd_vma) 0);
175 if (elength > 0)
176 {
177 /* sanity check */
178 if (length != 0 && length != elength)
179 abort ();
180 return insn;
181 }
182 }
183 }
184
185 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
186 }
187 }
188 else
189 {
190 /* Sanity check: can't pass an alias insn if ! alias_p. */
191 if (! alias_p
192 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
193 abort ();
194 /* Sanity check: length must be correct. */
195 if (length != CGEN_INSN_BITSIZE (insn))
196 abort ();
197
198 /* ??? 0 is passed for `pc' */
199 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
200 (bfd_vma) 0);
201 /* Sanity check: must succeed.
202 Could relax this later if it ever proves useful. */
203 if (length == 0)
204 abort ();
205 return insn;
206 }
207
208 return NULL;
209}
210
211/* Fill in the operand instances used by INSN whose operands are FIELDS.
212 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
213 in. */
214
215void
216fr30_cgen_get_insn_operands (od, insn, fields, indices)
217 CGEN_OPCODE_DESC od;
218 const CGEN_INSN * insn;
219 const CGEN_FIELDS * fields;
220 int *indices;
221{
222 const CGEN_OPERAND_INSTANCE *opinst;
223 int i;
224
225 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
226 opinst != NULL
227 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
228 ++i, ++opinst)
229 {
230 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
231 if (op == NULL)
232 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
233 else
234 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
235 fields);
236 }
237}
238
239/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
240 isn't known.
241 The INSN, INSN_VALUE, and LENGTH arguments are passed to
242 fr30_cgen_lookup_insn unchanged.
243
244 The result is the insn table entry or NULL if the instruction wasn't
245 recognized. */
246
247const CGEN_INSN *
248fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
249 CGEN_OPCODE_DESC od;
250 const CGEN_INSN *insn;
251 CGEN_INSN_BYTES insn_value;
252 int length;
253 int *indices;
254{
255 CGEN_FIELDS fields;
256
257 /* Pass non-zero for ALIAS_P only if INSN != NULL.
258 If INSN == NULL, we want a real insn. */
259 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
260 insn != NULL);
261 if (! insn)
262 return NULL;
263
264 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
265 return insn;
266}
267/* Attributes. */
268
269static const CGEN_ATTR_ENTRY MACH_attr[] =
270{
271 { "base", MACH_BASE },
272 { "fr30", MACH_FR30 },
273 { "max", MACH_MAX },
274 { 0, 0 }
275};
276
277const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
278{
279 { "CACHE-ADDR", NULL },
280 { "PC", NULL },
281 { "PROFILE", NULL },
282 { 0, 0 }
283};
284
285const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
286{
287 { "ABS-ADDR", NULL },
7a0737c8 288 { "HASH-PREFIX", NULL },
a86481d3
DB		 289 { "NEGATIVE", NULL },
290 { "PCREL-ADDR", NULL },
291 { "RELAX", NULL },
1c8f439e 292 { "SEM-ONLY", NULL },
a86481d3 293 { "SIGN-OPT", NULL },
7a0737c8 294 { "SIGNED", NULL },
a86481d3
DB		 295 { "UNSIGNED", NULL },
296 { 0, 0 }
297};
298
299const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
300{
301 { "ALIAS", NULL },
302 { "COND-CTI", NULL },
303 { "NO-DIS", NULL },
304 { "RELAX", NULL },
305 { "RELAXABLE", NULL },
306 { "SKIP-CTI", NULL },
307 { "UNCOND-CTI", NULL },
308 { "VIRTUAL", NULL },
309 { 0, 0 }
310};
311
312CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
313{
314 { "ac", 13 },
315 { "fp", 14 },
316 { "sp", 15 },
317 { "r0", 0 },
318 { "r1", 1 },
319 { "r2", 2 },
320 { "r3", 3 },
321 { "r4", 4 },
322 { "r5", 5 },
323 { "r6", 6 },
324 { "r7", 7 },
325 { "r8", 8 },
326 { "r9", 9 },
327 { "r10", 10 },
328 { "r11", 11 },
329 { "r12", 12 },
330 { "r13", 13 },
331 { "r14", 14 },
332 { "r15", 15 }
333};
334
335CGEN_KEYWORD fr30_cgen_opval_h_gr =
336{
337 & fr30_cgen_opval_h_gr_entries[0],
338 19
339};
340
6146431a
DB		 341CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
342{
343 { "tbr", 0 },
344 { "rp", 1 },
345 { "ssp", 2 },
7a0737c8 346 { "usp", 3 },
6146431a
DB		 347 { "mdh", 4 },
348 { "mdl", 5 }
349};
350
7a0737c8 351CGEN_KEYWORD fr30_cgen_opval_h_dr =
6146431a 352{
7a0737c8
DB		 353 & fr30_cgen_opval_h_dr_entries[0],
354 6
6146431a
DB		 355};
356
6a1254af 357CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
6146431a 358{
6146431a
DB		 359 { "ps", 1 }
360};
361
6a1254af 362CGEN_KEYWORD fr30_cgen_opval_h_ps =
6146431a 363{
6a1254af
DB		 364 & fr30_cgen_opval_h_ps_entries[0],
365 1
366};
367
368CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
369{
370 { "r13", 13 }
371};
372
373CGEN_KEYWORD fr30_cgen_opval_h_r13 =
374{
375 & fr30_cgen_opval_h_r13_entries[0],
376 1
377};
378
379CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
380{
381 { "r14", 14 }
382};
383
384CGEN_KEYWORD fr30_cgen_opval_h_r14 =
385{
386 & fr30_cgen_opval_h_r14_entries[0],
387 1
388};
389
390CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
391{
392 { "r15", 15 }
393};
394
395CGEN_KEYWORD fr30_cgen_opval_h_r15 =
396{
397 & fr30_cgen_opval_h_r15_entries[0],
398 1
6146431a
DB		 399};
400
a86481d3
DB		 401
402/* The hardware table. */
403
404#define HW_ENT(n) fr30_cgen_hw_entries[n]
405static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
406{
407 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
408 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
409 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
410 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
411 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
412 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
413 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
6146431a 414 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
6a1254af
DB		 415 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0, { 0 } } },
416 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
417 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
418 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
7a0737c8
DB		 419 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
420 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
421 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
422 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
a86481d3
DB		 423 { 0 }
424};
425
426/* The operand table. */
427
428#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
429#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
430
431const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
432{
433/* pc: program counter */
434 { "pc", & HW_ENT (HW_H_PC), 0, 0,
1c8f439e 435 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 436/* Ri: destination register */
437 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
438 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
439/* Rj: source register */
440 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
441 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 442/* Rs1: dedicated register */
443 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
444 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
445/* Rs2: dedicated register */
446 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
447 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 448/* R13: General Register 13 */
449 { "R13", & HW_ENT (HW_H_R13), 0, 0,
450 { 0, 0, { 0 } } },
451/* R14: General Register 14 */
452 { "R14", & HW_ENT (HW_H_R14), 0, 0,
453 { 0, 0, { 0 } } },
454/* R15: General Register 15 */
455 { "R15", & HW_ENT (HW_H_R15), 0, 0,
456 { 0, 0, { 0 } } },
7a0737c8 457/* ps: Program Status register */
6a1254af
DB		 458 { "ps", & HW_ENT (HW_H_PS), 0, 0,
459 { 0, 0, { 0 } } },
7a0737c8
DB		 460/* u4: 4 bit unsigned immediate */
461 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
462 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
463/* m4: 4 bit negative immediate */
464 { "m4", & HW_ENT (HW_H_UINT), 8, 4,
465 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 466/* u8: 8 bit unsigned immediate */
467 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
468 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 469/* i8: 8 bit unsigned immediate */
470 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
471 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
472/* udisp6: 6 bit unsigned immediate */
473 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
7a0737c8 474 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 475/* disp8: 8 bit signed immediate */
476 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
477 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
478/* disp9: 9 bit signed immediate */
479 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
480 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
481/* disp10: 10 bit signed immediate */
482 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
483 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
7a0737c8
DB		 484/* s10: 10 bit signed immediate */
485 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
486 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
487/* u10: 10 bit unsigned immediate */
488 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
489 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
490/* dir8: 8 bit direct address */
491 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
492 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
493/* dir9: 9 bit direct address */
494 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
495 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
496/* dir10: 10 bit direct address */
497 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
498 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
499/* label9: 9 bit pc relative address */
500 { "label9", & HW_ENT (HW_H_SINT), 8, 8,
501 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
502/* label12: 12 bit pc relative address */
503 { "label12", & HW_ENT (HW_H_SINT), 5, 11,
504 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
505/* cc: condition codes */
506 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
507 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6146431a
DB		 508/* nbit: negative bit */
509 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
1c8f439e 510 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 511/* vbit: overflow bit */
512 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
1c8f439e 513 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 514/* zbit: zero bit */
515 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
1c8f439e 516 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 517/* cbit: carry bit */
518 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
1c8f439e 519 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 520};
521
522/* Operand references. */
523
524#define INPUT CGEN_OPERAND_INSTANCE_INPUT
525#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
526
6146431a 527static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
7a0737c8
DB		 528 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
529 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
530 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
531 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
532 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
533 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
534 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
535 { 0 }
536};
537
538static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
539 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
540 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
541 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
542 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
543 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
544 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
545 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
546 { 0 }
547};
548
549static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
550 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
551 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
552 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
553 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
554 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
555 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
556 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
557 { 0 }
558};
559
560static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
561 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
a86481d3 562 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
7a0737c8
DB		 563 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
564 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
565 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
566 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
567 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
568 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
569 { 0 }
570};
571
572static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
573 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
574 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
575 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
576 { 0 }
577};
578
579static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
580 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
581 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
582 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
583 { 0 }
584};
585
586static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
a86481d3 587 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
7a0737c8 588 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
a86481d3 589 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
7a0737c8
DB		 590 { 0 }
591};
592
593static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
594 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
595 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
596 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
597 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
598 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
599 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
600 { 0 }
601};
602
603static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
604 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
605 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
6146431a
DB		 606 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
607 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
608 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
609 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
a86481d3
DB		 610 { 0 }
611};
612
7a0737c8
DB		 613static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
614 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
615 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
616 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
617 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
618 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
619 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
620 { 0 }
621};
622
623static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
624 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
625 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
626 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
627 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
628 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
629 { 0 }
630};
631
632static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
633 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
634 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
635 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
636 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
637 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
638 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
639 { 0 }
640};
641
642static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
643 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
644 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
645 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0 },
646 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
647 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
648 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
649 { 0 }
650};
651
652static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
653 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
654 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
655 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0 },
656 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
657 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
658 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
659 { 0 }
660};
661
a86481d3
DB		 662#undef INPUT
663#undef OUTPUT
664
665#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
666#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
667#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
668
669/* The instruction table.
670 This is currently non-static because the simulator accesses it
671 directly. */
672
673const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
674{
675 /* Special null first entry.
676 A `num' value of zero is thus invalid.
677 Also, the special `invalid' insn resides here. */
678 { { 0 }, 0 },
6146431a 679/* add $Rj,$Ri */
a86481d3
DB		 680 {
681 { 1, 1, 1, 1 },
7a0737c8
DB		 682 FR30_INSN_ADD, "add", "add",
683 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
684 { 16, 16, 0xff00 }, 0xa600,
685 (PTR) & fmt_add_ops[0],
686 { 0, 0, { 0 } }
687 },
688/* add $u4,$Ri */
689 {
690 { 1, 1, 1, 1 },
691 FR30_INSN_ADDI, "addi", "add",
692 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
693 { 16, 16, 0xff00 }, 0xa400,
694 (PTR) & fmt_addi_ops[0],
695 { 0, 0, { 0 } }
696 },
697/* add2 $m4,$Ri */
698 {
699 { 1, 1, 1, 1 },
700 FR30_INSN_ADD2, "add2", "add2",
701 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
702 { 16, 16, 0xff00 }, 0xa500,
703 (PTR) & fmt_add2_ops[0],
704 { 0, 0, { 0 } }
705 },
706/* addc $Rj,$Ri */
707 {
708 { 1, 1, 1, 1 },
709 FR30_INSN_ADDC, "addc", "addc",
710 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
711 { 16, 16, 0xff00 }, 0xa700,
712 (PTR) & fmt_addc_ops[0],
713 { 0, 0, { 0 } }
714 },
715/* addn $Rj,$Ri */
716 {
717 { 1, 1, 1, 1 },
718 FR30_INSN_ADDN, "addn", "addn",
719 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
720 { 16, 16, 0xff00 }, 0xa200,
721 (PTR) & fmt_addn_ops[0],
722 { 0, 0, { 0 } }
723 },
724/* addn $u4,$Ri */
725 {
726 { 1, 1, 1, 1 },
727 FR30_INSN_ADDNI, "addni", "addn",
728 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
729 { 16, 16, 0xff00 }, 0xa000,
730 (PTR) & fmt_addni_ops[0],
731 { 0, 0, { 0 } }
732 },
733/* addn2 $m4,$Ri */
734 {
735 { 1, 1, 1, 1 },
736 FR30_INSN_ADDN2, "addn2", "addn2",
737 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
738 { 16, 16, 0xff00 }, 0xa100,
739 (PTR) & fmt_addn2_ops[0],
740 { 0, 0, { 0 } }
741 },
742/* sub $Rj,$Ri */
743 {
744 { 1, 1, 1, 1 },
745 FR30_INSN_SUB, "sub", "sub",
746 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
747 { 16, 16, 0xff00 }, 0xac00,
748 (PTR) & fmt_add_ops[0],
749 { 0, 0, { 0 } }
750 },
751/* subc $Rj,$Ri */
752 {
753 { 1, 1, 1, 1 },
754 FR30_INSN_SUBC, "subc", "subc",
755 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
756 { 16, 16, 0xff00 }, 0xad00,
757 (PTR) & fmt_addc_ops[0],
758 { 0, 0, { 0 } }
759 },
760/* subn $Rj,$Ri */
761 {
762 { 1, 1, 1, 1 },
763 FR30_INSN_SUBN, "subn", "subn",
764 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
765 { 16, 16, 0xff00 }, 0xae00,
766 (PTR) & fmt_addn_ops[0],
767 { 0, 0, { 0 } }
768 },
769/* cmp $Rj,$Ri */
770 {
771 { 1, 1, 1, 1 },
772 FR30_INSN_CMP, "cmp", "cmp",
773 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
774 { 16, 16, 0xff00 }, 0xaa00,
775 (PTR) & fmt_cmp_ops[0],
776 { 0, 0, { 0 } }
777 },
778/* cmp $u4,$Ri */
779 {
780 { 1, 1, 1, 1 },
781 FR30_INSN_CMPI, "cmpi", "cmp",
782 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
783 { 16, 16, 0xff00 }, 0xa800,
784 (PTR) & fmt_cmpi_ops[0],
785 { 0, 0, { 0 } }
786 },
787/* cmp2 $m4,$Ri */
788 {
789 { 1, 1, 1, 1 },
790 FR30_INSN_CMP2, "cmp2", "cmp2",
791 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
792 { 16, 16, 0xff00 }, 0xa900,
793 (PTR) & fmt_cmp2_ops[0],
794 { 0, 0, { 0 } }
795 },
796/* and $Rj,$Ri */
797 {
798 { 1, 1, 1, 1 },
799 FR30_INSN_AND, "and", "and",
800 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
801 { 16, 16, 0xff00 }, 0x8200,
802 (PTR) & fmt_and_ops[0],
803 { 0, 0, { 0 } }
804 },
805/* or $Rj,$Ri */
806 {
807 { 1, 1, 1, 1 },
808 FR30_INSN_OR, "or", "or",
809 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
810 { 16, 16, 0xff00 }, 0x9200,
811 (PTR) & fmt_and_ops[0],
812 { 0, 0, { 0 } }
813 },
814/* eor $Rj,$Ri */
815 {
816 { 1, 1, 1, 1 },
817 FR30_INSN_EOR, "eor", "eor",
818 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
819 { 16, 16, 0xff00 }, 0x9a00,
820 (PTR) & fmt_and_ops[0],
821 { 0, 0, { 0 } }
822 },
823/* and $Rj,@$Ri */
824 {
825 { 1, 1, 1, 1 },
826 FR30_INSN_ANDM, "andm", "and",
827 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
828 { 16, 16, 0xff00 }, 0x8400,
829 (PTR) & fmt_andm_ops[0],
830 { 0, 0, { 0 } }
831 },
832/* andh $Rj,@$Ri */
833 {
834 { 1, 1, 1, 1 },
835 FR30_INSN_ANDH, "andh", "andh",
836 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
837 { 16, 16, 0xff00 }, 0x8500,
838 (PTR) & fmt_andh_ops[0],
839 { 0, 0, { 0 } }
840 },
841/* andb $Rj,@$Ri */
842 {
843 { 1, 1, 1, 1 },
844 FR30_INSN_ANDB, "andb", "andb",
845 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
846 { 16, 16, 0xff00 }, 0x8600,
847 (PTR) & fmt_andb_ops[0],
848 { 0, 0, { 0 } }
849 },
850/* or $Rj,@$Ri */
851 {
852 { 1, 1, 1, 1 },
853 FR30_INSN_ORM, "orm", "or",
854 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
855 { 16, 16, 0xff00 }, 0x9400,
856 (PTR) & fmt_andm_ops[0],
857 { 0, 0, { 0 } }
858 },
859/* orh $Rj,@$Ri */
860 {
861 { 1, 1, 1, 1 },
862 FR30_INSN_ORH, "orh", "orh",
863 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
864 { 16, 16, 0xff00 }, 0x9500,
865 (PTR) & fmt_andh_ops[0],
866 { 0, 0, { 0 } }
867 },
868/* orb $Rj,@$Ri */
869 {
870 { 1, 1, 1, 1 },
871 FR30_INSN_ORB, "orb", "orb",
872 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
873 { 16, 16, 0xff00 }, 0x9600,
874 (PTR) & fmt_andb_ops[0],
875 { 0, 0, { 0 } }
876 },
877/* eor $Rj,@$Ri */
878 {
879 { 1, 1, 1, 1 },
880 FR30_INSN_EORM, "eorm", "eor",
881 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
882 { 16, 16, 0xff00 }, 0x9c00,
883 (PTR) & fmt_andm_ops[0],
884 { 0, 0, { 0 } }
885 },
886/* eorh $Rj,@$Ri */
887 {
888 { 1, 1, 1, 1 },
889 FR30_INSN_EORH, "eorh", "eorh",
890 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
891 { 16, 16, 0xff00 }, 0x9d00,
892 (PTR) & fmt_andh_ops[0],
893 { 0, 0, { 0 } }
894 },
895/* eorb $Rj,@$Ri */
896 {
897 { 1, 1, 1, 1 },
898 FR30_INSN_EORB, "eorb", "eorb",
899 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
900 { 16, 16, 0xff00 }, 0x9e00,
901 (PTR) & fmt_andb_ops[0],
902 { 0, 0, { 0 } }
903 },
904/* bandl $u4,@$Ri */
905 {
906 { 1, 1, 1, 1 },
907 FR30_INSN_BANDL, "bandl", "bandl",
908 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
909 { 16, 16, 0xff00 }, 0x8000,
910 (PTR) 0,
911 { 0, 0, { 0 } }
912 },
913/* borl $u4,@$Ri */
914 {
915 { 1, 1, 1, 1 },
916 FR30_INSN_BORL, "borl", "borl",
917 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
918 { 16, 16, 0xff00 }, 0x9000,
919 (PTR) 0,
920 { 0, 0, { 0 } }
921 },
922/* beorl $u4,@$Ri */
923 {
924 { 1, 1, 1, 1 },
925 FR30_INSN_BEORL, "beorl", "beorl",
926 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
927 { 16, 16, 0xff00 }, 0x9800,
928 (PTR) 0,
929 { 0, 0, { 0 } }
930 },
931/* bandh $u4,@$Ri */
932 {
933 { 1, 1, 1, 1 },
934 FR30_INSN_BANDH, "bandh", "bandh",
935 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
936 { 16, 16, 0xff00 }, 0x8100,
937 (PTR) 0,
938 { 0, 0, { 0 } }
939 },
940/* borh $u4,@$Ri */
941 {
942 { 1, 1, 1, 1 },
943 FR30_INSN_BORH, "borh", "borh",
944 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
945 { 16, 16, 0xff00 }, 0x9100,
946 (PTR) 0,
947 { 0, 0, { 0 } }
948 },
949/* beorh $u4,@$Ri */
950 {
951 { 1, 1, 1, 1 },
952 FR30_INSN_BEORH, "beorh", "beorh",
953 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
954 { 16, 16, 0xff00 }, 0x9900,
955 (PTR) 0,
956 { 0, 0, { 0 } }
957 },
958/* btstl $u4,@$Ri */
959 {
960 { 1, 1, 1, 1 },
961 FR30_INSN_BTSTL, "btstl", "btstl",
962 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
963 { 16, 16, 0xff00 }, 0x8800,
964 (PTR) 0,
965 { 0, 0, { 0 } }
966 },
967/* btsth $u4,@$Ri */
968 {
969 { 1, 1, 1, 1 },
970 FR30_INSN_BTSTH, "btsth", "btsth",
971 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
972 { 16, 16, 0xff00 }, 0x8900,
973 (PTR) 0,
974 { 0, 0, { 0 } }
975 },
976/* mul $Rj,$Ri */
977 {
978 { 1, 1, 1, 1 },
979 FR30_INSN_MUL, "mul", "mul",
980 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
981 { 16, 16, 0xff00 }, 0xaf00,
982 (PTR) 0,
983 { 0, 0, { 0 } }
984 },
985/* mulu $Rj,$Ri */
986 {
987 { 1, 1, 1, 1 },
988 FR30_INSN_MULU, "mulu", "mulu",
989 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
990 { 16, 16, 0xff00 }, 0xab00,
991 (PTR) 0,
992 { 0, 0, { 0 } }
993 },
994/* mulh $Rj,$Ri */
995 {
996 { 1, 1, 1, 1 },
997 FR30_INSN_MULH, "mulh", "mulh",
998 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
999 { 16, 16, 0xff00 }, 0xbf00,
1000 (PTR) 0,
1001 { 0, 0, { 0 } }
1002 },
1003/* muluh $Rj,$Ri */
1004 {
1005 { 1, 1, 1, 1 },
1006 FR30_INSN_MULUH, "muluh", "muluh",
1007 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1008 { 16, 16, 0xff00 }, 0xbb00,
1009 (PTR) 0,
1010 { 0, 0, { 0 } }
1011 },
1012/* div0s $Ri */
1013 {
1014 { 1, 1, 1, 1 },
1015 FR30_INSN_DIV0S, "div0s", "div0s",
1016 { { MNEM, ' ', OP (RI), 0 } },
1017 { 16, 16, 0xfff0 }, 0x9740,
1018 (PTR) 0,
1019 { 0, 0, { 0 } }
1020 },
1021/* div0u $Ri */
1022 {
1023 { 1, 1, 1, 1 },
1024 FR30_INSN_DIV0U, "div0u", "div0u",
1025 { { MNEM, ' ', OP (RI), 0 } },
1026 { 16, 16, 0xfff0 }, 0x9750,
1027 (PTR) 0,
1028 { 0, 0, { 0 } }
1029 },
1030/* div1 $Ri */
1031 {
1032 { 1, 1, 1, 1 },
1033 FR30_INSN_DIV1, "div1", "div1",
1034 { { MNEM, ' ', OP (RI), 0 } },
1035 { 16, 16, 0xfff0 }, 0x9760,
1036 (PTR) 0,
1037 { 0, 0, { 0 } }
1038 },
1039/* div2 $Ri */
1040 {
1041 { 1, 1, 1, 1 },
1042 FR30_INSN_DIV2, "div2", "div2",
1043 { { MNEM, ' ', OP (RI), 0 } },
1044 { 16, 16, 0xfff0 }, 0x9770,
1045 (PTR) 0,
1046 { 0, 0, { 0 } }
1047 },
1048/* div3 */
1049 {
1050 { 1, 1, 1, 1 },
1051 FR30_INSN_DIV3, "div3", "div3",
1052 { { MNEM, 0 } },
1053 { 16, 16, 0xffff }, 0x9f60,
1054 (PTR) 0,
1055 { 0, 0, { 0 } }
1056 },
1057/* div4s */
1058 {
1059 { 1, 1, 1, 1 },
1060 FR30_INSN_DIV4S, "div4s", "div4s",
1061 { { MNEM, 0 } },
1062 { 16, 16, 0xffff }, 0x9f70,
1063 (PTR) 0,
1064 { 0, 0, { 0 } }
1065 },
1066/* lsl $Rj,$Ri */
1067 {
1068 { 1, 1, 1, 1 },
1069 FR30_INSN_LSL, "lsl", "lsl",
1070 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1071 { 16, 16, 0xff00 }, 0xb600,
1072 (PTR) 0,
1073 { 0, 0, { 0 } }
1074 },
1075/* lsl $u4,$Ri */
1076 {
1077 { 1, 1, 1, 1 },
1078 FR30_INSN_LSLI, "lsli", "lsl",
1079 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1080 { 16, 16, 0xff00 }, 0xb400,
1081 (PTR) 0,
1082 { 0, 0, { 0 } }
1083 },
1084/* lsl2 $u4,$Ri */
1085 {
1086 { 1, 1, 1, 1 },
1087 FR30_INSN_LSL2, "lsl2", "lsl2",
1088 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1089 { 16, 16, 0xff00 }, 0xb500,
1090 (PTR) 0,
1091 { 0, 0, { 0 } }
1092 },
1093/* lsr $Rj,$Ri */
1094 {
1095 { 1, 1, 1, 1 },
1096 FR30_INSN_LSR, "lsr", "lsr",
1097 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1098 { 16, 16, 0xff00 }, 0xb200,
1099 (PTR) 0,
1100 { 0, 0, { 0 } }
1101 },
1102/* lsr $u4,$Ri */
1103 {
1104 { 1, 1, 1, 1 },
1105 FR30_INSN_LSRI, "lsri", "lsr",
1106 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1107 { 16, 16, 0xff00 }, 0xb000,
1108 (PTR) 0,
1109 { 0, 0, { 0 } }
1110 },
1111/* lsr2 $u4,$Ri */
1112 {
1113 { 1, 1, 1, 1 },
1114 FR30_INSN_LSR2, "lsr2", "lsr2",
1115 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1116 { 16, 16, 0xff00 }, 0xb100,
1117 (PTR) 0,
1118 { 0, 0, { 0 } }
1119 },
1120/* asr $Rj,$Ri */
1121 {
1122 { 1, 1, 1, 1 },
1123 FR30_INSN_ASR, "asr", "asr",
1124 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1125 { 16, 16, 0xff00 }, 0xba00,
1126 (PTR) 0,
1127 { 0, 0, { 0 } }
1128 },
1129/* asr $u4,$Ri */
1130 {
1131 { 1, 1, 1, 1 },
1132 FR30_INSN_ASRI, "asri", "asr",
1133 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1134 { 16, 16, 0xff00 }, 0xb800,
1135 (PTR) 0,
1136 { 0, 0, { 0 } }
1137 },
1138/* asr2 $u4,$Ri */
1139 {
1140 { 1, 1, 1, 1 },
1141 FR30_INSN_ASR2, "asr2", "asr2",
1142 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1143 { 16, 16, 0xff00 }, 0xb900,
1144 (PTR) 0,
1145 { 0, 0, { 0 } }
1146 },
1147/* ldi:8 $i8,$Ri */
1148 {
1149 { 1, 1, 1, 1 },
1150 FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1151 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1152 { 16, 16, 0xf000 }, 0xc000,
1153 (PTR) 0,
1154 { 0, 0, { 0 } }
1155 },
1156/* ld @$Rj,$Ri */
1157 {
1158 { 1, 1, 1, 1 },
1159 FR30_INSN_LD, "ld", "ld",
1160 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1161 { 16, 16, 0xff00 }, 0x400,
1162 (PTR) 0,
1163 { 0, 0, { 0 } }
1164 },
1165/* lduh @$Rj,$Ri */
1166 {
1167 { 1, 1, 1, 1 },
1168 FR30_INSN_LDUH, "lduh", "lduh",
1169 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1170 { 16, 16, 0xff00 }, 0x500,
1171 (PTR) 0,
1172 { 0, 0, { 0 } }
1173 },
1174/* ldub @$Rj,$Ri */
1175 {
1176 { 1, 1, 1, 1 },
1177 FR30_INSN_LDUB, "ldub", "ldub",
1178 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1179 { 16, 16, 0xff00 }, 0x600,
1180 (PTR) 0,
1181 { 0, 0, { 0 } }
1182 },
6a1254af 1183/* ld @($r13,$Rj),$Ri */
7a0737c8
DB		 1184 {
1185 { 1, 1, 1, 1 },
1186 FR30_INSN_LDR13, "ldr13", "ld",
6a1254af 1187 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1188 { 16, 16, 0xff00 }, 0x0,
1189 (PTR) 0,
1190 { 0, 0, { 0 } }
1191 },
6a1254af 1192/* lduh @($r13,$Rj),$Ri */
7a0737c8
DB		 1193 {
1194 { 1, 1, 1, 1 },
1195 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
6a1254af 1196 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1197 { 16, 16, 0xff00 }, 0x100,
1198 (PTR) 0,
1199 { 0, 0, { 0 } }
1200 },
6a1254af 1201/* ldub @($r13,$Rj),$Ri */
7a0737c8
DB		 1202 {
1203 { 1, 1, 1, 1 },
1204 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
6a1254af 1205 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1206 { 16, 16, 0xff00 }, 0x200,
1207 (PTR) 0,
1208 { 0, 0, { 0 } }
1209 },
6a1254af 1210/* ld @($r14,$disp10),$Ri */
7a0737c8
DB		 1211 {
1212 { 1, 1, 1, 1 },
1213 FR30_INSN_LDR14, "ldr14", "ld",
6a1254af 1214 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1215 { 16, 16, 0xf000 }, 0x2000,
1216 (PTR) 0,
1217 { 0, 0, { 0 } }
1218 },
6a1254af 1219/* lduh @($r14,$disp9),$Ri */
7a0737c8
DB		 1220 {
1221 { 1, 1, 1, 1 },
1222 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
6a1254af 1223 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1224 { 16, 16, 0xf000 }, 0x4000,
1225 (PTR) 0,
1226 { 0, 0, { 0 } }
1227 },
6a1254af 1228/* ldub @($r14,$disp8),$Ri */
7a0737c8
DB		 1229 {
1230 { 1, 1, 1, 1 },
1231 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
6a1254af 1232 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1233 { 16, 16, 0xf000 }, 0x6000,
1234 (PTR) 0,
1235 { 0, 0, { 0 } }
1236 },
6a1254af 1237/* ld @($r15,$udisp6),$Ri */
7a0737c8
DB		 1238 {
1239 { 1, 1, 1, 1 },
1240 FR30_INSN_LDR15, "ldr15", "ld",
6a1254af 1241 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1242 { 16, 16, 0xff00 }, 0x300,
1243 (PTR) 0,
1244 { 0, 0, { 0 } }
1245 },
6a1254af 1246/* ld @$r15+,$Ri */
7a0737c8
DB		 1247 {
1248 { 1, 1, 1, 1 },
1249 FR30_INSN_LDR15GR, "ldr15gr", "ld",
6a1254af 1250 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
7a0737c8
DB		 1251 { 16, 16, 0xfff0 }, 0x700,
1252 (PTR) 0,
1253 { 0, 0, { 0 } }
1254 },
6a1254af 1255/* ld @$r15+,$Rs2 */
7a0737c8
DB		 1256 {
1257 { 1, 1, 1, 1 },
1258 FR30_INSN_LDR15DR, "ldr15dr", "ld",
6a1254af 1259 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
7a0737c8
DB		 1260 { 16, 16, 0xfff0 }, 0x780,
1261 (PTR) 0,
1262 { 0, 0, { 0 } }
1263 },
6a1254af 1264/* ld @$r15+,$ps */
7a0737c8
DB		 1265 {
1266 { 1, 1, 1, 1 },
1267 FR30_INSN_LDR15PS, "ldr15ps", "ld",
6a1254af 1268 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
7a0737c8
DB		 1269 { 16, 16, 0xffff }, 0x790,
1270 (PTR) 0,
1271 { 0, 0, { 0 } }
1272 },
6a1254af 1273/* st $Ri,@$Rj */
7a0737c8
DB		 1274 {
1275 { 1, 1, 1, 1 },
1276 FR30_INSN_ST, "st", "st",
6a1254af 1277 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1278 { 16, 16, 0xff00 }, 0x1400,
1279 (PTR) 0,
1280 { 0, 0, { 0 } }
1281 },
6a1254af 1282/* sth $Ri,@$Rj */
7a0737c8
DB		 1283 {
1284 { 1, 1, 1, 1 },
1285 FR30_INSN_STH, "sth", "sth",
6a1254af 1286 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1287 { 16, 16, 0xff00 }, 0x1500,
1288 (PTR) 0,
1289 { 0, 0, { 0 } }
1290 },
6a1254af 1291/* stb $Ri,@$Rj */
7a0737c8
DB		 1292 {
1293 { 1, 1, 1, 1 },
1294 FR30_INSN_STB, "stb", "stb",
6a1254af 1295 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1296 { 16, 16, 0xff00 }, 0x1600,
1297 (PTR) 0,
1298 { 0, 0, { 0 } }
1299 },
6a1254af 1300/* st $Ri,@($r13,$Rj) */
7a0737c8
DB		 1301 {
1302 { 1, 1, 1, 1 },
1303 FR30_INSN_STR13, "str13", "st",
6a1254af 1304 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1305 { 16, 16, 0xff00 }, 0x1000,
1306 (PTR) 0,
1307 { 0, 0, { 0 } }
1308 },
6a1254af 1309/* sth $Ri,@($r13,$Rj) */
7a0737c8
DB		 1310 {
1311 { 1, 1, 1, 1 },
1312 FR30_INSN_STR13H, "str13h", "sth",
6a1254af 1313 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1314 { 16, 16, 0xff00 }, 0x1100,
1315 (PTR) 0,
1316 { 0, 0, { 0 } }
1317 },
6a1254af 1318/* stb $Ri,@($r13,$Rj) */
7a0737c8
DB		 1319 {
1320 { 1, 1, 1, 1 },
6a1254af
DB		 1321 FR30_INSN_STR13B, "stR13b", "stb",
1322 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1323 { 16, 16, 0xff00 }, 0x1200,
1324 (PTR) 0,
1325 { 0, 0, { 0 } }
1326 },
6a1254af 1327/* st $Ri,@($r14,$disp10) */
7a0737c8
DB		 1328 {
1329 { 1, 1, 1, 1 },
1330 FR30_INSN_STR14, "str14", "st",
6a1254af 1331 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
7a0737c8
DB		 1332 { 16, 16, 0xf000 }, 0x3000,
1333 (PTR) 0,
1334 { 0, 0, { 0 } }
1335 },
6a1254af 1336/* sth $Ri,@($r14,$disp9) */
7a0737c8
DB		 1337 {
1338 { 1, 1, 1, 1 },
1339 FR30_INSN_STR14H, "str14h", "sth",
6a1254af 1340 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
7a0737c8
DB		 1341 { 16, 16, 0xf000 }, 0x5000,
1342 (PTR) 0,
1343 { 0, 0, { 0 } }
1344 },
6a1254af 1345/* stb $Ri,@($r14,$disp8) */
7a0737c8
DB		 1346 {
1347 { 1, 1, 1, 1 },
1348 FR30_INSN_STR14B, "str14b", "stb",
6a1254af 1349 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
7a0737c8
DB		 1350 { 16, 16, 0xf000 }, 0x7000,
1351 (PTR) 0,
1352 { 0, 0, { 0 } }
1353 },
6a1254af 1354/* st $Ri,@($r15,$udisp6) */
7a0737c8
DB		 1355 {
1356 { 1, 1, 1, 1 },
1357 FR30_INSN_STR15, "str15", "st",
6a1254af 1358 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
7a0737c8
DB		 1359 { 16, 16, 0xff00 }, 0x1300,
1360 (PTR) 0,
1361 { 0, 0, { 0 } }
1362 },
6a1254af 1363/* st $Ri,@-$r15 */
7a0737c8
DB		 1364 {
1365 { 1, 1, 1, 1 },
1366 FR30_INSN_STR15GR, "str15gr", "st",
6a1254af 1367 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1368 { 16, 16, 0xfff0 }, 0x1700,
1369 (PTR) 0,
1370 { 0, 0, { 0 } }
1371 },
6a1254af 1372/* st $Rs2,@-$r15 */
7a0737c8
DB		 1373 {
1374 { 1, 1, 1, 1 },
1375 FR30_INSN_STR15DR, "str15dr", "st",
6a1254af 1376 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1377 { 16, 16, 0xfff0 }, 0x1780,
1378 (PTR) 0,
1379 { 0, 0, { 0 } }
1380 },
6a1254af 1381/* st $ps,@-$r15 */
7a0737c8
DB		 1382 {
1383 { 1, 1, 1, 1 },
1384 FR30_INSN_STR15PS, "str15ps", "st",
6a1254af 1385 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1386 { 16, 16, 0xffff }, 0x1790,
1387 (PTR) 0,
1388 { 0, 0, { 0 } }
1389 },
1390/* mov $Rj,$Ri */
1391 {
1392 { 1, 1, 1, 1 },
1393 FR30_INSN_MOV, "mov", "mov",
1394 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1395 { 16, 16, 0xff00 }, 0x8b00,
1396 (PTR) 0,
1397 { 0, 0, { 0 } }
1398 },
1399/* mov $Rs1,$Ri */
1400 {
1401 { 1, 1, 1, 1 },
1402 FR30_INSN_MOVDR, "movdr", "mov",
1403 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1404 { 16, 16, 0xff00 }, 0xb700,
1405 (PTR) 0,
1406 { 0, 0, { 0 } }
1407 },
6a1254af 1408/* mov $ps,$Ri */
7a0737c8
DB		 1409 {
1410 { 1, 1, 1, 1 },
1411 FR30_INSN_MOVPS, "movps", "mov",
6a1254af 1412 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
7a0737c8
DB		 1413 { 16, 16, 0xfff0 }, 0x1710,
1414 (PTR) 0,
1415 { 0, 0, { 0 } }
1416 },
1417/* mov $Ri,$Rs1 */
1418 {
1419 { 1, 1, 1, 1 },
1420 FR30_INSN_MOV2DR, "mov2dr", "mov",
1421 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1422 { 16, 16, 0xff00 }, 0xb300,
1423 (PTR) 0,
1424 { 0, 0, { 0 } }
1425 },
6a1254af 1426/* mov $Ri,$ps */
7a0737c8
DB		 1427 {
1428 { 1, 1, 1, 1 },
1429 FR30_INSN_MOV2PS, "mov2ps", "mov",
6a1254af 1430 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
7a0737c8
DB		 1431 { 16, 16, 0xfff0 }, 0x710,
1432 (PTR) 0,
1433 { 0, 0, { 0 } }
1434 },
1435/* jmp @$Ri */
1436 {
1437 { 1, 1, 1, 1 },
1438 FR30_INSN_JMP, "jmp", "jmp",
1439 { { MNEM, ' ', '@', OP (RI), 0 } },
1440 { 16, 16, 0xfff0 }, 0x9700,
1441 (PTR) 0,
1442 { 0, 0, { 0 } }
1443 },
6a1254af
DB		 1444/* jmp:D @$Ri */
1445 {
1446 { 1, 1, 1, 1 },
1447 FR30_INSN_JMPD, "jmpd", "jmp:D",
1448 { { MNEM, ' ', '@', OP (RI), 0 } },
1449 { 16, 16, 0xfff0 }, 0x9f00,
1450 (PTR) 0,
1451 { 0, 0, { 0 } }
1452 },
7a0737c8
DB		 1453/* call $label12 */
1454 {
1455 { 1, 1, 1, 1 },
1456 FR30_INSN_CALL, "call", "call",
1457 { { MNEM, ' ', OP (LABEL12), 0 } },
1458 { 16, 16, 0xf400 }, 0xd000,
1459 (PTR) 0,
1460 { 0, 0, { 0 } }
1461 },
6a1254af
DB		 1462/* call:D $label12 */
1463 {
1464 { 1, 1, 1, 1 },
1465 FR30_INSN_CALLD, "calld", "call:D",
1466 { { MNEM, ' ', OP (LABEL12), 0 } },
1467 { 16, 16, 0xf400 }, 0xd400,
1468 (PTR) 0,
1469 { 0, 0, { 0 } }
1470 },
7a0737c8
DB		 1471/* call @$Ri */
1472 {
1473 { 1, 1, 1, 1 },
1474 FR30_INSN_CALLR, "callr", "call",
1475 { { MNEM, ' ', '@', OP (RI), 0 } },
1476 { 16, 16, 0xfff0 }, 0x9710,
1477 (PTR) 0,
1478 { 0, 0, { 0 } }
1479 },
6a1254af
DB		 1480/* call:D @$Ri */
1481 {
1482 { 1, 1, 1, 1 },
1483 FR30_INSN_CALLRD, "callrd", "call:D",
1484 { { MNEM, ' ', '@', OP (RI), 0 } },
1485 { 16, 16, 0xfff0 }, 0x9f10,
1486 (PTR) 0,
1487 { 0, 0, { 0 } }
1488 },
7a0737c8
DB		 1489/* ret */
1490 {
1491 { 1, 1, 1, 1 },
1492 FR30_INSN_RET, "ret", "ret",
1493 { { MNEM, 0 } },
1494 { 16, 16, 0xffff }, 0x9720,
1495 (PTR) 0,
1496 { 0, 0, { 0 } }
1497 },
6a1254af
DB		 1498/* ret:D */
1499 {
1500 { 1, 1, 1, 1 },
1501 FR30_INSN_RETD, "retd", "ret:D",
1502 { { MNEM, 0 } },
1503 { 16, 16, 0xffff }, 0x9f20,
1504 (PTR) 0,
1505 { 0, 0, { 0 } }
1506 },
7a0737c8
DB		 1507/* int $u8 */
1508 {
1509 { 1, 1, 1, 1 },
1510 FR30_INSN_INT, "int", "int",
1511 { { MNEM, ' ', OP (U8), 0 } },
1512 { 16, 16, 0xff00 }, 0x1f00,
1513 (PTR) 0,
1514 { 0, 0, { 0 } }
1515 },
6a1254af 1516/* inte */
7a0737c8
DB		 1517 {
1518 { 1, 1, 1, 1 },
6a1254af 1519 FR30_INSN_INTE, "inte", "inte",
7a0737c8
DB		 1520 { { MNEM, 0 } },
1521 { 16, 16, 0xffff }, 0x9f30,
1522 (PTR) 0,
1523 { 0, 0, { 0 } }
1524 },
1525/* reti */
1526 {
1527 { 1, 1, 1, 1 },
1528 FR30_INSN_RETI, "reti", "reti",
1529 { { MNEM, 0 } },
1530 { 16, 16, 0xffff }, 0x9730,
1531 (PTR) 0,
1532 { 0, 0, { 0 } }
1533 },
6a1254af 1534/* bra $label9 */
7a0737c8
DB		 1535 {
1536 { 1, 1, 1, 1 },
6a1254af 1537 FR30_INSN_BRA, "bra", "bra",
7a0737c8
DB		 1538 { { MNEM, ' ', OP (LABEL9), 0 } },
1539 { 16, 16, 0xff00 }, 0xe000,
1540 (PTR) 0,
1541 { 0, 0, { 0 } }
1542 },
6a1254af 1543/* bno $label9 */
7a0737c8
DB		 1544 {
1545 { 1, 1, 1, 1 },
6a1254af 1546 FR30_INSN_BNO, "bno", "bno",
7a0737c8
DB		 1547 { { MNEM, ' ', OP (LABEL9), 0 } },
1548 { 16, 16, 0xff00 }, 0xe100,
1549 (PTR) 0,
1550 { 0, 0, { 0 } }
1551 },
6a1254af 1552/* beq $label9 */
7a0737c8
DB		 1553 {
1554 { 1, 1, 1, 1 },
6a1254af 1555 FR30_INSN_BEQ, "beq", "beq",
7a0737c8
DB		 1556 { { MNEM, ' ', OP (LABEL9), 0 } },
1557 { 16, 16, 0xff00 }, 0xe200,
1558 (PTR) 0,
1559 { 0, 0, { 0 } }
1560 },
6a1254af 1561/* bne $label9 */
7a0737c8
DB		 1562 {
1563 { 1, 1, 1, 1 },
6a1254af 1564 FR30_INSN_BNE, "bne", "bne",
7a0737c8
DB		 1565 { { MNEM, ' ', OP (LABEL9), 0 } },
1566 { 16, 16, 0xff00 }, 0xe300,
1567 (PTR) 0,
1568 { 0, 0, { 0 } }
1569 },
6a1254af 1570/* bc $label9 */
7a0737c8
DB		 1571 {
1572 { 1, 1, 1, 1 },
6a1254af 1573 FR30_INSN_BC, "bc", "bc",
7a0737c8
DB		 1574 { { MNEM, ' ', OP (LABEL9), 0 } },
1575 { 16, 16, 0xff00 }, 0xe400,
1576 (PTR) 0,
1577 { 0, 0, { 0 } }
1578 },
6a1254af 1579/* bnc $label9 */
7a0737c8
DB		 1580 {
1581 { 1, 1, 1, 1 },
6a1254af 1582 FR30_INSN_BNC, "bnc", "bnc",
7a0737c8
DB		 1583 { { MNEM, ' ', OP (LABEL9), 0 } },
1584 { 16, 16, 0xff00 }, 0xe500,
1585 (PTR) 0,
1586 { 0, 0, { 0 } }
1587 },
6a1254af 1588/* bn $label9 */
7a0737c8
DB		 1589 {
1590 { 1, 1, 1, 1 },
6a1254af 1591 FR30_INSN_BN, "bn", "bn",
7a0737c8
DB		 1592 { { MNEM, ' ', OP (LABEL9), 0 } },
1593 { 16, 16, 0xff00 }, 0xe600,
1594 (PTR) 0,
1595 { 0, 0, { 0 } }
1596 },
6a1254af 1597/* bp $label9 */
7a0737c8
DB		 1598 {
1599 { 1, 1, 1, 1 },
6a1254af 1600 FR30_INSN_BP, "bp", "bp",
7a0737c8
DB		 1601 { { MNEM, ' ', OP (LABEL9), 0 } },
1602 { 16, 16, 0xff00 }, 0xe700,
1603 (PTR) 0,
1604 { 0, 0, { 0 } }
1605 },
6a1254af 1606/* bv $label9 */
7a0737c8
DB		 1607 {
1608 { 1, 1, 1, 1 },
6a1254af 1609 FR30_INSN_BV, "bv", "bv",
7a0737c8
DB		 1610 { { MNEM, ' ', OP (LABEL9), 0 } },
1611 { 16, 16, 0xff00 }, 0xe800,
1612 (PTR) 0,
1613 { 0, 0, { 0 } }
1614 },
6a1254af 1615/* bnv $label9 */
7a0737c8
DB		 1616 {
1617 { 1, 1, 1, 1 },
6a1254af 1618 FR30_INSN_BNV, "bnv", "bnv",
7a0737c8
DB		 1619 { { MNEM, ' ', OP (LABEL9), 0 } },
1620 { 16, 16, 0xff00 }, 0xe900,
1621 (PTR) 0,
1622 { 0, 0, { 0 } }
1623 },
6a1254af 1624/* blt $label9 */
7a0737c8
DB		 1625 {
1626 { 1, 1, 1, 1 },
6a1254af 1627 FR30_INSN_BLT, "blt", "blt",
7a0737c8
DB		 1628 { { MNEM, ' ', OP (LABEL9), 0 } },
1629 { 16, 16, 0xff00 }, 0xea00,
1630 (PTR) 0,
1631 { 0, 0, { 0 } }
1632 },
6a1254af 1633/* bge $label9 */
7a0737c8
DB		 1634 {
1635 { 1, 1, 1, 1 },
6a1254af 1636 FR30_INSN_BGE, "bge", "bge",
7a0737c8
DB		 1637 { { MNEM, ' ', OP (LABEL9), 0 } },
1638 { 16, 16, 0xff00 }, 0xeb00,
1639 (PTR) 0,
1640 { 0, 0, { 0 } }
1641 },
6a1254af 1642/* ble $label9 */
7a0737c8
DB		 1643 {
1644 { 1, 1, 1, 1 },
6a1254af 1645 FR30_INSN_BLE, "ble", "ble",
7a0737c8
DB		 1646 { { MNEM, ' ', OP (LABEL9), 0 } },
1647 { 16, 16, 0xff00 }, 0xec00,
1648 (PTR) 0,
1649 { 0, 0, { 0 } }
1650 },
6a1254af 1651/* bgt $label9 */
7a0737c8
DB		 1652 {
1653 { 1, 1, 1, 1 },
6a1254af 1654 FR30_INSN_BGT, "bgt", "bgt",
7a0737c8
DB		 1655 { { MNEM, ' ', OP (LABEL9), 0 } },
1656 { 16, 16, 0xff00 }, 0xed00,
1657 (PTR) 0,
1658 { 0, 0, { 0 } }
1659 },
6a1254af 1660/* bls $label9 */
7a0737c8
DB		 1661 {
1662 { 1, 1, 1, 1 },
6a1254af 1663 FR30_INSN_BLS, "bls", "bls",
7a0737c8
DB		 1664 { { MNEM, ' ', OP (LABEL9), 0 } },
1665 { 16, 16, 0xff00 }, 0xee00,
1666 (PTR) 0,
1667 { 0, 0, { 0 } }
1668 },
6a1254af 1669/* bhi $label9 */
7a0737c8
DB		 1670 {
1671 { 1, 1, 1, 1 },
6a1254af 1672 FR30_INSN_BHI, "bhi", "bhi",
7a0737c8
DB		 1673 { { MNEM, ' ', OP (LABEL9), 0 } },
1674 { 16, 16, 0xff00 }, 0xef00,
1675 (PTR) 0,
1676 { 0, 0, { 0 } }
1677 },
6a1254af
DB		 1678/* bra:D $label9 */
1679 {
1680 { 1, 1, 1, 1 },
1681 FR30_INSN_BRAD, "brad", "bra:D",
1682 { { MNEM, ' ', OP (LABEL9), 0 } },
1683 { 16, 16, 0xff00 }, 0xf000,
1684 (PTR) 0,
1685 { 0, 0, { 0 } }
1686 },
1687/* bno:D $label9 */
1688 {
1689 { 1, 1, 1, 1 },
1690 FR30_INSN_BNOD, "bnod", "bno:D",
1691 { { MNEM, ' ', OP (LABEL9), 0 } },
1692 { 16, 16, 0xff00 }, 0xf100,
1693 (PTR) 0,
1694 { 0, 0, { 0 } }
1695 },
1696/* beq:D $label9 */
1697 {
1698 { 1, 1, 1, 1 },
1699 FR30_INSN_BEQD, "beqd", "beq:D",
1700 { { MNEM, ' ', OP (LABEL9), 0 } },
1701 { 16, 16, 0xff00 }, 0xf200,
1702 (PTR) 0,
1703 { 0, 0, { 0 } }
1704 },
1705/* bne:D $label9 */
1706 {
1707 { 1, 1, 1, 1 },
1708 FR30_INSN_BNED, "bned", "bne:D",
1709 { { MNEM, ' ', OP (LABEL9), 0 } },
1710 { 16, 16, 0xff00 }, 0xf300,
1711 (PTR) 0,
1712 { 0, 0, { 0 } }
1713 },
1714/* bc:D $label9 */
1715 {
1716 { 1, 1, 1, 1 },
1717 FR30_INSN_BCD, "bcd", "bc:D",
1718 { { MNEM, ' ', OP (LABEL9), 0 } },
1719 { 16, 16, 0xff00 }, 0xf400,
1720 (PTR) 0,
1721 { 0, 0, { 0 } }
1722 },
1723/* bnc:D $label9 */
1724 {
1725 { 1, 1, 1, 1 },
1726 FR30_INSN_BNCD, "bncd", "bnc:D",
1727 { { MNEM, ' ', OP (LABEL9), 0 } },
1728 { 16, 16, 0xff00 }, 0xf500,
1729 (PTR) 0,
1730 { 0, 0, { 0 } }
1731 },
1732/* bn:D $label9 */
1733 {
1734 { 1, 1, 1, 1 },
1735 FR30_INSN_BND, "bnd", "bn:D",
1736 { { MNEM, ' ', OP (LABEL9), 0 } },
1737 { 16, 16, 0xff00 }, 0xf600,
1738 (PTR) 0,
1739 { 0, 0, { 0 } }
1740 },
1741/* bp:D $label9 */
1742 {
1743 { 1, 1, 1, 1 },
1744 FR30_INSN_BPD, "bpd", "bp:D",
1745 { { MNEM, ' ', OP (LABEL9), 0 } },
1746 { 16, 16, 0xff00 }, 0xf700,
1747 (PTR) 0,
1748 { 0, 0, { 0 } }
1749 },
1750/* bv:D $label9 */
1751 {
1752 { 1, 1, 1, 1 },
1753 FR30_INSN_BVD, "bvd", "bv:D",
1754 { { MNEM, ' ', OP (LABEL9), 0 } },
1755 { 16, 16, 0xff00 }, 0xf800,
1756 (PTR) 0,
1757 { 0, 0, { 0 } }
1758 },
1759/* bnv:D $label9 */
1760 {
1761 { 1, 1, 1, 1 },
1762 FR30_INSN_BNVD, "bnvd", "bnv:D",
1763 { { MNEM, ' ', OP (LABEL9), 0 } },
1764 { 16, 16, 0xff00 }, 0xf900,
1765 (PTR) 0,
1766 { 0, 0, { 0 } }
1767 },
1768/* blt:D $label9 */
1769 {
1770 { 1, 1, 1, 1 },
1771 FR30_INSN_BLTD, "bltd", "blt:D",
1772 { { MNEM, ' ', OP (LABEL9), 0 } },
1773 { 16, 16, 0xff00 }, 0xfa00,
1774 (PTR) 0,
1775 { 0, 0, { 0 } }
1776 },
1777/* bge:D $label9 */
1778 {
1779 { 1, 1, 1, 1 },
1780 FR30_INSN_BGED, "bged", "bge:D",
1781 { { MNEM, ' ', OP (LABEL9), 0 } },
1782 { 16, 16, 0xff00 }, 0xfb00,
1783 (PTR) 0,
1784 { 0, 0, { 0 } }
1785 },
1786/* ble:D $label9 */
1787 {
1788 { 1, 1, 1, 1 },
1789 FR30_INSN_BLED, "bled", "ble:D",
1790 { { MNEM, ' ', OP (LABEL9), 0 } },
1791 { 16, 16, 0xff00 }, 0xfc00,
1792 (PTR) 0,
1793 { 0, 0, { 0 } }
1794 },
1795/* bgt:D $label9 */
1796 {
1797 { 1, 1, 1, 1 },
1798 FR30_INSN_BGTD, "bgtd", "bgt:D",
1799 { { MNEM, ' ', OP (LABEL9), 0 } },
1800 { 16, 16, 0xff00 }, 0xfd00,
1801 (PTR) 0,
1802 { 0, 0, { 0 } }
1803 },
1804/* bls:D $label9 */
1805 {
1806 { 1, 1, 1, 1 },
1807 FR30_INSN_BLSD, "blsd", "bls:D",
1808 { { MNEM, ' ', OP (LABEL9), 0 } },
1809 { 16, 16, 0xff00 }, 0xfe00,
1810 (PTR) 0,
1811 { 0, 0, { 0 } }
1812 },
1813/* bhi:D $label9 */
1814 {
1815 { 1, 1, 1, 1 },
1816 FR30_INSN_BHID, "bhid", "bhi:D",
1817 { { MNEM, ' ', OP (LABEL9), 0 } },
1818 { 16, 16, 0xff00 }, 0xff00,
1819 (PTR) 0,
1820 { 0, 0, { 0 } }
1821 },
1822/* dmov @$dir10,$R13 */
7a0737c8
DB		 1823 {
1824 { 1, 1, 1, 1 },
1825 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
6a1254af 1826 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
7a0737c8
DB		 1827 { 16, 16, 0xff00 }, 0x800,
1828 (PTR) 0,
1829 { 0, 0, { 0 } }
1830 },
6a1254af 1831/* dmovh @$dir9,$R13 */
7a0737c8
DB		 1832 {
1833 { 1, 1, 1, 1 },
1834 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
6a1254af 1835 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
7a0737c8
DB		 1836 { 16, 16, 0xff00 }, 0x900,
1837 (PTR) 0,
1838 { 0, 0, { 0 } }
1839 },
6a1254af 1840/* dmovb @$dir8,$R13 */
7a0737c8
DB		 1841 {
1842 { 1, 1, 1, 1 },
1843 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
6a1254af 1844 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
7a0737c8
DB		 1845 { 16, 16, 0xff00 }, 0xa00,
1846 (PTR) 0,
1847 { 0, 0, { 0 } }
1848 },
6a1254af 1849/* dmov $R13,@$dir10 */
7a0737c8
DB		 1850 {
1851 { 1, 1, 1, 1 },
1852 FR30_INSN_DMOVR13, "dmovr13", "dmov",
6a1254af 1853 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1854 { 16, 16, 0xff00 }, 0x1800,
1855 (PTR) 0,
1856 { 0, 0, { 0 } }
1857 },
6a1254af 1858/* dmovh $R13,@$dir9 */
7a0737c8
DB		 1859 {
1860 { 1, 1, 1, 1 },
1861 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
6a1254af 1862 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
7a0737c8
DB		 1863 { 16, 16, 0xff00 }, 0x1900,
1864 (PTR) 0,
1865 { 0, 0, { 0 } }
1866 },
6a1254af 1867/* dmovb $R13,@$dir8 */
7a0737c8
DB		 1868 {
1869 { 1, 1, 1, 1 },
1870 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
6a1254af 1871 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
7a0737c8
DB		 1872 { 16, 16, 0xff00 }, 0x1a00,
1873 (PTR) 0,
1874 { 0, 0, { 0 } }
1875 },
6a1254af 1876/* dmov @$dir10,@$R13+ */
7a0737c8
DB		 1877 {
1878 { 1, 1, 1, 1 },
1879 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
6a1254af 1880 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1881 { 16, 16, 0xff00 }, 0xc00,
1882 (PTR) 0,
1883 { 0, 0, { 0 } }
1884 },
6a1254af 1885/* dmovh @$dir9,@$R13+ */
7a0737c8
DB		 1886 {
1887 { 1, 1, 1, 1 },
1888 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
6a1254af 1889 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1890 { 16, 16, 0xff00 }, 0xd00,
1891 (PTR) 0,
1892 { 0, 0, { 0 } }
1893 },
6a1254af 1894/* dmovb @$dir8,@$R13+ */
7a0737c8
DB		 1895 {
1896 { 1, 1, 1, 1 },
1897 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
6a1254af 1898 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1899 { 16, 16, 0xff00 }, 0xe00,
1900 (PTR) 0,
1901 { 0, 0, { 0 } }
1902 },
6a1254af 1903/* dmov @$R13+,@$dir10 */
7a0737c8
DB		 1904 {
1905 { 1, 1, 1, 1 },
6a1254af
DB		 1906 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1907 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1908 { 16, 16, 0xff00 }, 0x1c00,
1909 (PTR) 0,
1910 { 0, 0, { 0 } }
1911 },
6a1254af 1912/* dmovh @$R13+,@$dir9 */
7a0737c8
DB		 1913 {
1914 { 1, 1, 1, 1 },
6a1254af
DB		 1915 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1916 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
7a0737c8
DB		 1917 { 16, 16, 0xff00 }, 0x1d00,
1918 (PTR) 0,
1919 { 0, 0, { 0 } }
1920 },
6a1254af 1921/* dmovb @$R13+,@$dir8 */
7a0737c8
DB		 1922 {
1923 { 1, 1, 1, 1 },
6a1254af
DB		 1924 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1925 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
7a0737c8
DB		 1926 { 16, 16, 0xff00 }, 0x1e00,
1927 (PTR) 0,
1928 { 0, 0, { 0 } }
1929 },
6a1254af 1930/* dmov @$dir10,-$R15 */
7a0737c8
DB		 1931 {
1932 { 1, 1, 1, 1 },
1933 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
6a1254af 1934 { { MNEM, ' ', '@', OP (DIR10), ',', '-', OP (R15), 0 } },
7a0737c8
DB		 1935 { 16, 16, 0xff00 }, 0xb00,
1936 (PTR) 0,
1937 { 0, 0, { 0 } }
1938 },
6a1254af 1939/* dmov @$R15+,@$dir10 */
7a0737c8
DB		 1940 {
1941 { 1, 1, 1, 1 },
6a1254af
DB		 1942 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1943 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1944 { 16, 16, 0xff00 }, 0x1b00,
1945 (PTR) 0,
1946 { 0, 0, { 0 } }
1947 },
1948/* ldres @$Ri+,$u4 */
1949 {
1950 { 1, 1, 1, 1 },
1951 FR30_INSN_LDRES, "ldres", "ldres",
1952 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1953 { 16, 16, 0xff00 }, 0xbc00,
1954 (PTR) 0,
1955 { 0, 0, { 0 } }
1956 },
6a1254af 1957/* stres $u4,@$Ri+ */
7a0737c8
DB		 1958 {
1959 { 1, 1, 1, 1 },
6a1254af 1960 FR30_INSN_STRES, "stres", "stres",
7a0737c8
DB		 1961 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
1962 { 16, 16, 0xff00 }, 0xbd00,
1963 (PTR) 0,
1964 { 0, 0, { 0 } }
1965 },
1966/* nop */
1967 {
1968 { 1, 1, 1, 1 },
1969 FR30_INSN_NOP, "nop", "nop",
1970 { { MNEM, 0 } },
1971 { 16, 16, 0xffff }, 0x9fa0,
1972 (PTR) 0,
1973 { 0, 0, { 0 } }
1974 },
1975/* andccr $u8 */
1976 {
1977 { 1, 1, 1, 1 },
1978 FR30_INSN_ANDCCR, "andccr", "andccr",
1979 { { MNEM, ' ', OP (U8), 0 } },
1980 { 16, 16, 0xff00 }, 0x8300,
1981 (PTR) 0,
1982 { 0, 0, { 0 } }
1983 },
1984/* orccr $u8 */
1985 {
1986 { 1, 1, 1, 1 },
1987 FR30_INSN_ORCCR, "orccr", "orccr",
1988 { { MNEM, ' ', OP (U8), 0 } },
1989 { 16, 16, 0xff00 }, 0x9300,
1990 (PTR) 0,
1991 { 0, 0, { 0 } }
1992 },
1993/* stilm $u8 */
1994 {
1995 { 1, 1, 1, 1 },
1996 FR30_INSN_STILM, "stilm", "stilm",
1997 { { MNEM, ' ', OP (U8), 0 } },
1998 { 16, 16, 0xff00 }, 0x8700,
1999 (PTR) 0,
2000 { 0, 0, { 0 } }
2001 },
2002/* addsp $s10 */
2003 {
2004 { 1, 1, 1, 1 },
2005 FR30_INSN_ADDSP, "addsp", "addsp",
2006 { { MNEM, ' ', OP (S10), 0 } },
2007 { 16, 16, 0xff00 }, 0xa300,
2008 (PTR) 0,
2009 { 0, 0, { 0 } }
2010 },
2011/* extsb $Ri */
2012 {
2013 { 1, 1, 1, 1 },
2014 FR30_INSN_EXTSB, "extsb", "extsb",
2015 { { MNEM, ' ', OP (RI), 0 } },
2016 { 16, 16, 0xfff0 }, 0x9780,
2017 (PTR) 0,
2018 { 0, 0, { 0 } }
2019 },
2020/* extub $Ri */
2021 {
2022 { 1, 1, 1, 1 },
2023 FR30_INSN_EXTUB, "extub", "extub",
2024 { { MNEM, ' ', OP (RI), 0 } },
2025 { 16, 16, 0xfff0 }, 0x9790,
2026 (PTR) 0,
2027 { 0, 0, { 0 } }
2028 },
2029/* extsh $Ri */
2030 {
2031 { 1, 1, 1, 1 },
2032 FR30_INSN_EXTSH, "extsh", "extsh",
2033 { { MNEM, ' ', OP (RI), 0 } },
2034 { 16, 16, 0xfff0 }, 0x97a0,
2035 (PTR) 0,
2036 { 0, 0, { 0 } }
2037 },
2038/* extuh $Ri */
2039 {
2040 { 1, 1, 1, 1 },
2041 FR30_INSN_EXTUH, "extuh", "extuh",
2042 { { MNEM, ' ', OP (RI), 0 } },
2043 { 16, 16, 0xfff0 }, 0x97b0,
2044 (PTR) 0,
2045 { 0, 0, { 0 } }
2046 },
2047/* enter $u10 */
2048 {
2049 { 1, 1, 1, 1 },
2050 FR30_INSN_ENTER, "enter", "enter",
2051 { { MNEM, ' ', OP (U10), 0 } },
2052 { 16, 16, 0xff00 }, 0xf00,
2053 (PTR) 0,
2054 { 0, 0, { 0 } }
2055 },
2056/* leave */
2057 {
2058 { 1, 1, 1, 1 },
2059 FR30_INSN_LEAVE, "leave", "leave",
2060 { { MNEM, 0 } },
2061 { 16, 16, 0xffff }, 0x9f90,
2062 (PTR) 0,
2063 { 0, 0, { 0 } }
2064 },
2065/* xchb @$Rj,$Ri */
2066 {
2067 { 1, 1, 1, 1 },
2068 FR30_INSN_XCHB, "xchb", "xchb",
2069 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2070 { 16, 16, 0xff00 }, 0x8a00,
2071 (PTR) 0,
a86481d3
DB		 2072 { 0, 0, { 0 } }
2073 },
2074};
2075
2076#undef A
2077#undef MNEM
2078#undef OP
2079
2080static const CGEN_INSN_TABLE insn_table =
2081{
2082 & fr30_cgen_insn_table_entries[0],
2083 sizeof (CGEN_INSN),
2084 MAX_INSNS,
2085 NULL
2086};
2087
2088/* Each non-simple macro entry points to an array of expansion possibilities. */
2089
2090#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2091#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2092#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2093
2094/* The macro instruction table. */
2095
2096static const CGEN_INSN macro_insn_table_entries[] =
2097{
2098};
2099
2100#undef A
2101#undef MNEM
2102#undef OP
2103
2104static const CGEN_INSN_TABLE macro_insn_table =
2105{
2106 & macro_insn_table_entries[0],
2107 sizeof (CGEN_INSN),
2108 (sizeof (macro_insn_table_entries) /
2109 sizeof (macro_insn_table_entries[0])),
2110 NULL
2111};
2112
2113static void
2114init_tables ()
2115{
2116}
2117
2118/* Return non-zero if INSN is to be added to the hash table.
2119 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2120
2121static int
2122asm_hash_insn_p (insn)
2123 const CGEN_INSN * insn;
2124{
2125 return CGEN_ASM_HASH_P (insn);
2126}
2127
2128static int
2129dis_hash_insn_p (insn)
2130 const CGEN_INSN * insn;
2131{
2132 /* If building the hash table and the NO-DIS attribute is present,
2133 ignore. */
2134 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2135 return 0;
2136 return CGEN_DIS_HASH_P (insn);
2137}
2138
2139/* The result is the hash value of the insn.
2140 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2141
2142static unsigned int
2143asm_hash_insn (mnem)
2144 const char * mnem;
2145{
2146 return CGEN_ASM_HASH (mnem);
2147}
2148
2149/* BUF is a pointer to the insn's bytes in target order.
2150 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2151 host order. */
2152
2153static unsigned int
2154dis_hash_insn (buf, value)
2155 const char * buf;
2156 unsigned long value;
2157{
2158 return CGEN_DIS_HASH (buf, value);
2159}
2160
2161/* Initialize an opcode table and return a descriptor.
2162 It's much like opening a file, and must be the first function called. */
2163
2164CGEN_OPCODE_DESC
2165fr30_cgen_opcode_open (mach, endian)
2166 int mach;
2167 enum cgen_endian endian;
2168{
2169 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2170 static int init_p;
2171
2172 if (! init_p)
2173 {
2174 init_tables ();
2175 init_p = 1;
2176 }
2177
2178 memset (table, 0, sizeof (*table));
2179
2180 CGEN_OPCODE_MACH (table) = mach;
2181 CGEN_OPCODE_ENDIAN (table) = endian;
2182 /* FIXME: for the sparc case we can determine insn-endianness statically.
2183 The worry here is where both data and insn endian can be independently
2184 chosen, in which case this function will need another argument.
2185 Actually, will want to allow for more arguments in the future anyway. */
2186 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2187
2188 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2189
2190 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2191
2192 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2193
2194 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2195
2196 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2197 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2198 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2199
2200 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2201 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2202 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2203
2204 return (CGEN_OPCODE_DESC) table;
2205}
2206
2207/* Close an opcode table. */
2208
2209void
2210fr30_cgen_opcode_close (desc)
2211 CGEN_OPCODE_DESC desc;
2212{
2213 free (desc);
2214}
2215
2216/* Getting values from cgen_fields is handled by a collection of functions.
2217 They are distinguished by the type of the VALUE argument they return.
2218 TODO: floating point, inlining support, remove cases where result type
2219 not appropriate. */
2220
2221int
2222fr30_cgen_get_int_operand (opindex, fields)
2223 int opindex;
2224 const CGEN_FIELDS * fields;
2225{
2226 int value;
2227
2228 switch (opindex)
2229 {
2230 case FR30_OPERAND_RI :
2231 value = fields->f_Ri;
2232 break;
2233 case FR30_OPERAND_RJ :
2234 value = fields->f_Rj;
2235 break;
7a0737c8
DB		 2236 case FR30_OPERAND_RS1 :
2237 value = fields->f_Rs1;
2238 break;
2239 case FR30_OPERAND_RS2 :
2240 value = fields->f_Rs2;
2241 break;
6a1254af
DB		 2242 case FR30_OPERAND_R13 :
2243 value = fields->f_nil;
2244 break;
2245 case FR30_OPERAND_R14 :
2246 value = fields->f_nil;
2247 break;
2248 case FR30_OPERAND_R15 :
2249 value = fields->f_nil;
2250 break;
2251 case FR30_OPERAND_PS :
2252 value = fields->f_nil;
2253 break;
7a0737c8
DB		 2254 case FR30_OPERAND_U4 :
2255 value = fields->f_u4;
2256 break;
2257 case FR30_OPERAND_M4 :
2258 value = fields->f_m4;
2259 break;
6a1254af
DB		 2260 case FR30_OPERAND_U8 :
2261 value = fields->f_u8;
2262 break;
7a0737c8
DB		 2263 case FR30_OPERAND_I8 :
2264 value = fields->f_i8;
2265 break;
6a1254af
DB		 2266 case FR30_OPERAND_UDISP6 :
2267 value = fields->f_udisp6;
7a0737c8 2268 break;
6a1254af
DB		 2269 case FR30_OPERAND_DISP8 :
2270 value = fields->f_disp8;
2271 break;
2272 case FR30_OPERAND_DISP9 :
2273 value = fields->f_disp9;
2274 break;
2275 case FR30_OPERAND_DISP10 :
2276 value = fields->f_disp10;
7a0737c8
DB		 2277 break;
2278 case FR30_OPERAND_S10 :
2279 value = fields->f_s10;
2280 break;
2281 case FR30_OPERAND_U10 :
2282 value = fields->f_u10;
2283 break;
2284 case FR30_OPERAND_DIR8 :
2285 value = fields->f_dir8;
2286 break;
2287 case FR30_OPERAND_DIR9 :
2288 value = fields->f_dir9;
2289 break;
2290 case FR30_OPERAND_DIR10 :
2291 value = fields->f_dir10;
2292 break;
2293 case FR30_OPERAND_LABEL9 :
6a1254af 2294 value = fields->f_rel9;
7a0737c8
DB		 2295 break;
2296 case FR30_OPERAND_LABEL12 :
6a1254af 2297 value = fields->f_rel12;
7a0737c8
DB		 2298 break;
2299 case FR30_OPERAND_CC :
2300 value = fields->f_cc;
2301 break;
a86481d3
DB		 2302
2303 default :
2304 /* xgettext:c-format */
2305 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2306 opindex);
2307 abort ();
2308 }
2309
2310 return value;
2311}
2312
2313bfd_vma
2314fr30_cgen_get_vma_operand (opindex, fields)
2315 int opindex;
2316 const CGEN_FIELDS * fields;
2317{
2318 bfd_vma value;
2319
2320 switch (opindex)
2321 {
2322 case FR30_OPERAND_RI :
2323 value = fields->f_Ri;
2324 break;
2325 case FR30_OPERAND_RJ :
2326 value = fields->f_Rj;
2327 break;
7a0737c8
DB		 2328 case FR30_OPERAND_RS1 :
2329 value = fields->f_Rs1;
2330 break;
2331 case FR30_OPERAND_RS2 :
2332 value = fields->f_Rs2;
2333 break;
6a1254af
DB		 2334 case FR30_OPERAND_R13 :
2335 value = fields->f_nil;
2336 break;
2337 case FR30_OPERAND_R14 :
2338 value = fields->f_nil;
2339 break;
2340 case FR30_OPERAND_R15 :
2341 value = fields->f_nil;
2342 break;
2343 case FR30_OPERAND_PS :
2344 value = fields->f_nil;
2345 break;
7a0737c8
DB		 2346 case FR30_OPERAND_U4 :
2347 value = fields->f_u4;
2348 break;
2349 case FR30_OPERAND_M4 :
2350 value = fields->f_m4;
2351 break;
6a1254af
DB		 2352 case FR30_OPERAND_U8 :
2353 value = fields->f_u8;
2354 break;
7a0737c8
DB		 2355 case FR30_OPERAND_I8 :
2356 value = fields->f_i8;
2357 break;
6a1254af
DB		 2358 case FR30_OPERAND_UDISP6 :
2359 value = fields->f_udisp6;
7a0737c8 2360 break;
6a1254af
DB		 2361 case FR30_OPERAND_DISP8 :
2362 value = fields->f_disp8;
2363 break;
2364 case FR30_OPERAND_DISP9 :
2365 value = fields->f_disp9;
2366 break;
2367 case FR30_OPERAND_DISP10 :
2368 value = fields->f_disp10;
7a0737c8
DB		 2369 break;
2370 case FR30_OPERAND_S10 :
2371 value = fields->f_s10;
2372 break;
2373 case FR30_OPERAND_U10 :
2374 value = fields->f_u10;
2375 break;
2376 case FR30_OPERAND_DIR8 :
2377 value = fields->f_dir8;
2378 break;
2379 case FR30_OPERAND_DIR9 :
2380 value = fields->f_dir9;
2381 break;
2382 case FR30_OPERAND_DIR10 :
2383 value = fields->f_dir10;
2384 break;
2385 case FR30_OPERAND_LABEL9 :
6a1254af 2386 value = fields->f_rel9;
7a0737c8
DB		 2387 break;
2388 case FR30_OPERAND_LABEL12 :
6a1254af 2389 value = fields->f_rel12;
7a0737c8
DB		 2390 break;
2391 case FR30_OPERAND_CC :
2392 value = fields->f_cc;
2393 break;
a86481d3
DB		 2394
2395 default :
2396 /* xgettext:c-format */
2397 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2398 opindex);
2399 abort ();
2400 }
2401
2402 return value;
2403}
2404
2405/* Stuffing values in cgen_fields is handled by a collection of functions.
2406 They are distinguished by the type of the VALUE argument they accept.
2407 TODO: floating point, inlining support, remove cases where argument type
2408 not appropriate. */
2409
2410void
2411fr30_cgen_set_int_operand (opindex, fields, value)
2412 int opindex;
2413 CGEN_FIELDS * fields;
2414 int value;
2415{
2416 switch (opindex)
2417 {
2418 case FR30_OPERAND_RI :
2419 fields->f_Ri = value;
2420 break;
2421 case FR30_OPERAND_RJ :
2422 fields->f_Rj = value;
2423 break;
7a0737c8
DB		 2424 case FR30_OPERAND_RS1 :
2425 fields->f_Rs1 = value;
2426 break;
2427 case FR30_OPERAND_RS2 :
2428 fields->f_Rs2 = value;
2429 break;
6a1254af
DB		 2430 case FR30_OPERAND_R13 :
2431 fields->f_nil = value;
2432 break;
2433 case FR30_OPERAND_R14 :
2434 fields->f_nil = value;
2435 break;
2436 case FR30_OPERAND_R15 :
2437 fields->f_nil = value;
2438 break;
2439 case FR30_OPERAND_PS :
2440 fields->f_nil = value;
2441 break;
7a0737c8
DB		 2442 case FR30_OPERAND_U4 :
2443 fields->f_u4 = value;
2444 break;
2445 case FR30_OPERAND_M4 :
2446 fields->f_m4 = value;
2447 break;
6a1254af
DB		 2448 case FR30_OPERAND_U8 :
2449 fields->f_u8 = value;
2450 break;
7a0737c8
DB		 2451 case FR30_OPERAND_I8 :
2452 fields->f_i8 = value;
2453 break;
6a1254af
DB		 2454 case FR30_OPERAND_UDISP6 :
2455 fields->f_udisp6 = value;
2456 break;
2457 case FR30_OPERAND_DISP8 :
2458 fields->f_disp8 = value;
7a0737c8 2459 break;
6a1254af
DB		 2460 case FR30_OPERAND_DISP9 :
2461 fields->f_disp9 = value;
2462 break;
2463 case FR30_OPERAND_DISP10 :
2464 fields->f_disp10 = value;
7a0737c8
DB		 2465 break;
2466 case FR30_OPERAND_S10 :
2467 fields->f_s10 = value;
2468 break;
2469 case FR30_OPERAND_U10 :
2470 fields->f_u10 = value;
2471 break;
2472 case FR30_OPERAND_DIR8 :
2473 fields->f_dir8 = value;
2474 break;
2475 case FR30_OPERAND_DIR9 :
2476 fields->f_dir9 = value;
2477 break;
2478 case FR30_OPERAND_DIR10 :
2479 fields->f_dir10 = value;
2480 break;
2481 case FR30_OPERAND_LABEL9 :
6a1254af 2482 fields->f_rel9 = value;
7a0737c8
DB		 2483 break;
2484 case FR30_OPERAND_LABEL12 :
6a1254af 2485 fields->f_rel12 = value;
7a0737c8
DB		 2486 break;
2487 case FR30_OPERAND_CC :
2488 fields->f_cc = value;
2489 break;
a86481d3
DB		 2490
2491 default :
2492 /* xgettext:c-format */
2493 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2494 opindex);
2495 abort ();
2496 }
2497}
2498
2499void
2500fr30_cgen_set_vma_operand (opindex, fields, value)
2501 int opindex;
2502 CGEN_FIELDS * fields;
2503 bfd_vma value;
2504{
2505 switch (opindex)
2506 {
2507 case FR30_OPERAND_RI :
2508 fields->f_Ri = value;
2509 break;
2510 case FR30_OPERAND_RJ :
2511 fields->f_Rj = value;
2512 break;
7a0737c8
DB		 2513 case FR30_OPERAND_RS1 :
2514 fields->f_Rs1 = value;
2515 break;
2516 case FR30_OPERAND_RS2 :
2517 fields->f_Rs2 = value;
2518 break;
6a1254af
DB		 2519 case FR30_OPERAND_R13 :
2520 fields->f_nil = value;
2521 break;
2522 case FR30_OPERAND_R14 :
2523 fields->f_nil = value;
2524 break;
2525 case FR30_OPERAND_R15 :
2526 fields->f_nil = value;
2527 break;
2528 case FR30_OPERAND_PS :
2529 fields->f_nil = value;
2530 break;
7a0737c8
DB		 2531 case FR30_OPERAND_U4 :
2532 fields->f_u4 = value;
2533 break;
2534 case FR30_OPERAND_M4 :
2535 fields->f_m4 = value;
2536 break;
6a1254af
DB		 2537 case FR30_OPERAND_U8 :
2538 fields->f_u8 = value;
2539 break;
7a0737c8
DB		 2540 case FR30_OPERAND_I8 :
2541 fields->f_i8 = value;
2542 break;
6a1254af
DB		 2543 case FR30_OPERAND_UDISP6 :
2544 fields->f_udisp6 = value;
2545 break;
2546 case FR30_OPERAND_DISP8 :
2547 fields->f_disp8 = value;
2548 break;
2549 case FR30_OPERAND_DISP9 :
2550 fields->f_disp9 = value;
7a0737c8 2551 break;
6a1254af
DB		 2552 case FR30_OPERAND_DISP10 :
2553 fields->f_disp10 = value;
7a0737c8
DB		 2554 break;
2555 case FR30_OPERAND_S10 :
2556 fields->f_s10 = value;
2557 break;
2558 case FR30_OPERAND_U10 :
2559 fields->f_u10 = value;
2560 break;
2561 case FR30_OPERAND_DIR8 :
2562 fields->f_dir8 = value;
2563 break;
2564 case FR30_OPERAND_DIR9 :
2565 fields->f_dir9 = value;
2566 break;
2567 case FR30_OPERAND_DIR10 :
2568 fields->f_dir10 = value;
2569 break;
2570 case FR30_OPERAND_LABEL9 :
6a1254af 2571 fields->f_rel9 = value;
7a0737c8
DB		 2572 break;
2573 case FR30_OPERAND_LABEL12 :
6a1254af 2574 fields->f_rel12 = value;
7a0737c8
DB		 2575 break;
2576 case FR30_OPERAND_CC :
2577 fields->f_cc = value;
2578 break;
a86481d3
DB		 2579
2580 default :
2581 /* xgettext:c-format */
2582 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2583 opindex);
2584 abort ();
2585 }
2586}
2587
GDB Binutils - Deliverables
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