[deliverable/binutils-gdb.git] / opcodes / fr30-opc.h

/* Instruction description for fr30.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef FR30_OPC_H
#define FR30_OPC_H

#define CGEN_ARCH fr30

/* Given symbol S, return fr30_cgen_<S>.  */
#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)

/* Selected cpu families.  */
#define HAVE_CPU_FR30BF

#define CGEN_INSN_LSB0_P 0
#define CGEN_WORD_BITSIZE 32
#define CGEN_DEFAULT_INSN_BITSIZE 16
#define CGEN_BASE_INSN_BITSIZE 16
#define CGEN_MIN_INSN_BITSIZE 16
#define CGEN_MAX_INSN_BITSIZE 48
#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
#define CGEN_INT_INSN_P 0

/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */

/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
   we can't hash on everything up to the space.  */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of operands any insn or macro-insn has.  */
#define CGEN_MAX_INSN_OPERANDS 16

/* Maximum number of fields in an instruction.  */
#define CGEN_MAX_IFMT_OPERANDS 7

/* Enums.  */

/* Enum declaration for insn op1 enums.  */
typedef enum insn_op1 {
  OP1_0, OP1_1, OP1_2, OP1_3
 , OP1_4, OP1_5, OP1_6, OP1_7
 , OP1_8, OP1_9, OP1_A, OP1_B
 , OP1_C, OP1_D, OP1_E, OP1_F
} INSN_OP1;

/* Enum declaration for insn op2 enums.  */
typedef enum insn_op2 {
  OP2_0, OP2_1, OP2_2, OP2_3
 , OP2_4, OP2_5, OP2_6, OP2_7
 , OP2_8, OP2_9, OP2_A, OP2_B
 , OP2_C, OP2_D, OP2_E, OP2_F
} INSN_OP2;

/* Enum declaration for insn op3 enums.  */
typedef enum insn_op3 {
  OP3_0, OP3_1, OP3_2, OP3_3
 , OP3_4, OP3_5, OP3_6, OP3_7
 , OP3_8, OP3_9, OP3_A, OP3_B
 , OP3_C, OP3_D, OP3_E, OP3_F
} INSN_OP3;

/* Enum declaration for insn op4 enums.  */
typedef enum insn_op4 {
  OP4_0
} INSN_OP4;

/* Enum declaration for insn op5 enums.  */
typedef enum insn_op5 {
  OP5_0, OP5_1
} INSN_OP5;

/* Enum declaration for insn cc enums.  */
typedef enum insn_cc {
  CC_RA, CC_NO, CC_EQ, CC_NE
 , CC_C, CC_NC, CC_N, CC_P
 , CC_V, CC_NV, CC_LT, CC_GE
 , CC_LE, CC_GT, CC_LS, CC_HI
} INSN_CC;

/* Enum declaration for general registers.  */
typedef enum h_gr {
  H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
} H_GR;

/* Enum declaration for coprocessor registers.  */
typedef enum h_cr {
  H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
} H_CR;

/* Enum declaration for dedicated registers.  */
typedef enum h_dr {
  H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 , H_DR_MDH, H_DR_MDL
} H_DR;

/* Enum declaration for program status.  */
typedef enum h_ps {
  H_PS_PS
} H_PS;

/* Enum declaration for General Register 13 explicitely required.  */
typedef enum h_r13 {
  H_R13_R13
} H_R13;

/* Enum declaration for General Register 14 explicitely required.  */
typedef enum h_r14 {
  H_R14_R14
} H_R14;

/* Enum declaration for General Register 15 explicitely required.  */
typedef enum h_r15 {
  H_R15_R15
} H_R15;

/* Enum declaration for fr30 operand types.  */
typedef enum cgen_operand_type {
  FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4
 , FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8
 , FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10
 , FR30_OPERAND_I32, FR30_OPERAND_I20, FR30_OPERAND_LABEL9, FR30_OPERAND_DIR8
 , FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW
 , FR30_OPERAND_REGLIST_HI, FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT
 , FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT
 , FR30_OPERAND_SBIT, FR30_OPERAND_MAX
} CGEN_OPERAND_TYPE;

/* Non-boolean attributes.  */

/* Enum declaration for machine type selection.  */
typedef enum mach_attr {
  MACH_BASE, MACH_FR30, MACH_MAX
} MACH_ATTR;

/* Number of architecture variants.  */
#define MAX_MACHS ((int) MACH_MAX)

/* Number of operands types.  */
#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)

/* Maximum number of operands referenced by any insn.  */
#define MAX_OPERAND_INSTANCES 9

/* Hardware, operand and instruction attribute indices.  */

/* Enum declaration for cgen_hw attrs.  */
typedef enum cgen_hw_attr {
  CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
} CGEN_HW_ATTR;

/* Number of non-boolean elements in cgen_hw.  */
#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)

/* Hardware, operand and instruction attribute indices.  */

/* Enum declaration for cgen_ifld attrs.  */
typedef enum cgen_ifld_attr {
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
 , CGEN_IFLD_SIGNED, CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
} CGEN_IFLD_ATTR;

/* Number of non-boolean elements in cgen_ifld.  */
#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)

/* Enum declaration for fr30 ifield types.  */
typedef enum ifield_type {
  FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
 , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
 , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
 , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
 , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
 , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
 , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
 , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
 , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
 , FR30_F_REL12, FR30_F_REGLIST_HI, FR30_F_REGLIST_LOW, FR30_F_MAX
} IFIELD_TYPE;

#define MAX_IFLD ((int) FR30_F_MAX)

/* Enum declaration for cgen_operand attrs.  */
typedef enum cgen_operand_attr {
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
 , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
 , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_VIRTUAL
} CGEN_OPERAND_ATTR;

/* Number of non-boolean elements in cgen_operand.  */
#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)

/* Enum declaration for cgen_insn attrs.  */
typedef enum cgen_insn_attr {
  CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
 , CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI
 , CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
} CGEN_INSN_ATTR;

/* Number of non-boolean elements in cgen_insn.  */
#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)

/* Enum declaration for fr30 instruction types.  */
typedef enum cgen_insn_type {
  FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32
 , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13
 , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH
 , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR
 , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB
 , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14
 , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR
 , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR
 , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP
 , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL
 , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT
 , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO
 , FR30_INSN_BEQ, FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC
 , FR30_INSN_BN, FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV
 , FR30_INSN_BLT, FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT
 , FR30_INSN_BLS, FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD
 , FR30_INSN_BEQD, FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD
 , FR30_INSN_BND, FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD
 , FR30_INSN_BLTD, FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD
 , FR30_INSN_BLSD, FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H
 , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB
 , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
 , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD
 , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD
 , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR
 , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB
 , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0
 , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER
 , FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX
} CGEN_INSN_TYPE;

/* Index of `invalid' insn place holder.  */
#define CGEN_INSN_INVALID FR30_INSN_INVALID
/* Total number of insns in table.  */
#define MAX_INSNS ((int) FR30_INSN_MAX)

/* cgen.h uses things we just defined.  */
#include "opcode/cgen.h"

/* This struct records data prior to insertion or after extraction.  */
struct cgen_fields 
{
  long f_nil;
  long f_op1;
  long f_op2;
  long f_op3;
  long f_op4;
  long f_op5;
  long f_cc;
  long f_ccc;
  long f_Rj;
  long f_Ri;
  long f_Rs1;
  long f_Rs2;
  long f_Rjc;
  long f_Ric;
  long f_CRj;
  long f_CRi;
  long f_u4;
  long f_u4c;
  long f_i4;
  long f_m4;
  long f_u8;
  long f_i8;
  long f_i20_4;
  long f_i20_16;
  long f_i20;
  long f_i32;
  long f_udisp6;
  long f_disp8;
  long f_disp9;
  long f_disp10;
  long f_s10;
  long f_u10;
  long f_rel9;
  long f_dir8;
  long f_dir9;
  long f_dir10;
  long f_rel12;
  long f_reglist_hi;
  long f_reglist_low;
  int length;
};

/* Attributes.  */
extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];

/* Enum declaration for fr30 hardware types.  */
typedef enum hw_type {
  HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX
} HW_TYPE;

#define MAX_HW ((int) HW_MAX)

/* Hardware decls.  */

extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
extern CGEN_KEYWORD fr30_cgen_opval_h_r15;

#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}

/* -- opc.h */

/* ??? This can be improved upon.  */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 16
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)

/* -- */


#endif /* FR30_OPC_H */
Commit	Line	Data
a86481d3 DB	1	/* Instruction description for fr30.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
	5	Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
	6
	7	This file is part of the GNU Binutils and/or GDB, the GNU debugger.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22
	23	*/
	24
	25	#ifndef FR30_OPC_H
	26	#define FR30_OPC_H
	27
	28	#define CGEN_ARCH fr30
	29
a73911a7	30	/* Given symbol S, return fr30_cgen_<S>. */
a86481d3 DB	31	#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
	32
	33	/* Selected cpu families. */
	34	#define HAVE_CPU_FR30BF
	35
	36	#define CGEN_INSN_LSB0_P 0
	37	#define CGEN_WORD_BITSIZE 32
	38	#define CGEN_DEFAULT_INSN_BITSIZE 16
	39	#define CGEN_BASE_INSN_BITSIZE 16
	40	#define CGEN_MIN_INSN_BITSIZE 16
95b03313	41	#define CGEN_MAX_INSN_BITSIZE 48
a86481d3 DB	42	#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
	43	#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
	44	#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
	45	#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
95b03313	46	#define CGEN_INT_INSN_P 0
a86481d3 DB	47
	48	/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
	49
	50	/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
	51	e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
	52	we can't hash on everything up to the space. */
	53	#define CGEN_MNEMONIC_OPERANDS
	54	/* Maximum number of operands any insn or macro-insn has. */
	55	#define CGEN_MAX_INSN_OPERANDS 16
	56
a73911a7 DE	57	/* Maximum number of fields in an instruction. */
	58	#define CGEN_MAX_IFMT_OPERANDS 7
	59
a86481d3 DB	60	/* Enums. */
	61
	62	/* Enum declaration for insn op1 enums. */
	63	typedef enum insn_op1 {
	64	OP1_0, OP1_1, OP1_2, OP1_3
	65	, OP1_4, OP1_5, OP1_6, OP1_7
	66	, OP1_8, OP1_9, OP1_A, OP1_B
	67	, OP1_C, OP1_D, OP1_E, OP1_F
	68	} INSN_OP1;
	69
	70	/* Enum declaration for insn op2 enums. */
	71	typedef enum insn_op2 {
	72	OP2_0, OP2_1, OP2_2, OP2_3
	73	, OP2_4, OP2_5, OP2_6, OP2_7
	74	, OP2_8, OP2_9, OP2_A, OP2_B
	75	, OP2_C, OP2_D, OP2_E, OP2_F
	76	} INSN_OP2;
	77
	78	/* Enum declaration for insn op3 enums. */
	79	typedef enum insn_op3 {
	80	OP3_0, OP3_1, OP3_2, OP3_3
	81	, OP3_4, OP3_5, OP3_6, OP3_7
	82	, OP3_8, OP3_9, OP3_A, OP3_B
	83	, OP3_C, OP3_D, OP3_E, OP3_F
	84	} INSN_OP3;
	85
7a0737c8 DB	86	/* Enum declaration for insn op4 enums. */
	87	typedef enum insn_op4 {
	88	OP4_0
	89	} INSN_OP4;
	90
a86481d3 DB	91	/* Enum declaration for insn op5 enums. */
	92	typedef enum insn_op5 {
	93	OP5_0, OP5_1
	94	} INSN_OP5;
	95
7a0737c8 DB	96	/* Enum declaration for insn cc enums. */
	97	typedef enum insn_cc {
	98	CC_RA, CC_NO, CC_EQ, CC_NE
	99	, CC_C, CC_NC, CC_N, CC_P
	100	, CC_V, CC_NV, CC_LT, CC_GE
	101	, CC_LE, CC_GT, CC_LS, CC_HI
	102	} INSN_CC;
	103
a86481d3 DB	104	/* Enum declaration for general registers. */
	105	typedef enum h_gr {
	106	H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
	107	, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
	108	, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
	109	, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
	110	, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
	111	} H_GR;
	112
e17387a5 DB	113	/* Enum declaration for coprocessor registers. */
	114	typedef enum h_cr {
	115	H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
	116	, H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
	117	, H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
	118	, H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
	119	} H_CR;
	120
6146431a DB	121	/* Enum declaration for dedicated registers. */
	122	typedef enum h_dr {
	123	H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
7a0737c8	124	, H_DR_MDH, H_DR_MDL
6146431a DB	125	} H_DR;
6146431a DB	126
6a1254af DB	127	/* Enum declaration for program status. */
6a1254af DB	128	typedef enum h_ps {
9225e69c	129	H_PS_PS
6a1254af DB	130	} H_PS;
	131
	132	/* Enum declaration for General Register 13 explicitely required. */
	133	typedef enum h_r13 {
9225e69c	134	H_R13_R13
6a1254af DB	135	} H_R13;
	136
	137	/* Enum declaration for General Register 14 explicitely required. */
	138	typedef enum h_r14 {
9225e69c	139	H_R14_R14
6a1254af DB	140	} H_R14;
	141
	142	/* Enum declaration for General Register 15 explicitely required. */
	143	typedef enum h_r15 {
9225e69c	144	H_R15_R15
6a1254af	145	} H_R15;
6146431a	146
a86481d3 DB	147	/* Enum declaration for fr30 operand types. */
a86481d3 DB	148	typedef enum cgen_operand_type {
e17387a5 DB	149	FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
e17387a5 DB	150	, FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
6a1254af	151	, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
e17387a5 DB	152	, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4
	153	, FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8
	154	, FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10
a73911a7 DE	155	, FR30_OPERAND_I32, FR30_OPERAND_I20, FR30_OPERAND_LABEL9, FR30_OPERAND_DIR8
	156	, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW
	157	, FR30_OPERAND_REGLIST_HI, FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT
	158	, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT
	159	, FR30_OPERAND_SBIT, FR30_OPERAND_MAX
a86481d3 DB	160	} CGEN_OPERAND_TYPE;
	161
	162	/* Non-boolean attributes. */
	163
	164	/* Enum declaration for machine type selection. */
	165	typedef enum mach_attr {
	166	MACH_BASE, MACH_FR30, MACH_MAX
	167	} MACH_ATTR;
	168
	169	/* Number of architecture variants. */
	170	#define MAX_MACHS ((int) MACH_MAX)
	171
	172	/* Number of operands types. */
	173	#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
	174
	175	/* Maximum number of operands referenced by any insn. */
9225e69c	176	#define MAX_OPERAND_INSTANCES 9
a86481d3 DB	177
	178	/* Hardware, operand and instruction attribute indices. */
	179
	180	/* Enum declaration for cgen_hw attrs. */
	181	typedef enum cgen_hw_attr {
9225e69c	182	CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
a86481d3 DB	183	} CGEN_HW_ATTR;
	184
	185	/* Number of non-boolean elements in cgen_hw. */
	186	#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
	187
a73911a7 DE	188	/* Hardware, operand and instruction attribute indices. */
	189
	190	/* Enum declaration for cgen_ifld attrs. */
	191	typedef enum cgen_ifld_attr {
	192	CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
	193	, CGEN_IFLD_SIGNED, CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
	194	} CGEN_IFLD_ATTR;
	195
	196	/* Number of non-boolean elements in cgen_ifld. */
	197	#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)
	198
	199	/* Enum declaration for fr30 ifield types. */
	200	typedef enum ifield_type {
	201	FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
	202	, FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
	203	, FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
	204	, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
	205	, FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
	206	, FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
	207	, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
	208	, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
	209	, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
	210	, FR30_F_REL12, FR30_F_REGLIST_HI, FR30_F_REGLIST_LOW, FR30_F_MAX
	211	} IFIELD_TYPE;
	212
	213	#define MAX_IFLD ((int) FR30_F_MAX)
	214
a86481d3 DB	215	/* Enum declaration for cgen_operand attrs. */
a86481d3 DB	216	typedef enum cgen_operand_attr {
7a0737c8 DB	217	CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
7a0737c8 DB	218	, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
a73911a7	219	, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_VIRTUAL
a86481d3 DB	220	} CGEN_OPERAND_ATTR;
	221
	222	/* Number of non-boolean elements in cgen_operand. */
	223	#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
	224
	225	/* Enum declaration for cgen_insn attrs. */
	226	typedef enum cgen_insn_attr {
a73911a7 DE	227	CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
	228	, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI
	229	, CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
a86481d3 DB	230	} CGEN_INSN_ATTR;
	231
	232	/* Number of non-boolean elements in cgen_insn. */
	233	#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
	234
	235	/* Enum declaration for fr30 instruction types. */
	236	typedef enum cgen_insn_type {
7a0737c8 DB	237	FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
	238	, FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
	239	, FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
	240	, FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
	241	, FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
	242	, FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
	243	, FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
	244	, FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
	245	, FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
	246	, FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
	247	, FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
	248	, FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
	249	, FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
a73911a7 DE	250	, FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32
	251	, FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13
	252	, FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH
	253	, FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR
	254	, FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB
	255	, FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14
	256	, FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR
	257	, FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR
	258	, FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP
	259	, FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL
	260	, FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT
	261	, FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO
	262	, FR30_INSN_BEQ, FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC
	263	, FR30_INSN_BN, FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV
	264	, FR30_INSN_BLT, FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT
	265	, FR30_INSN_BLS, FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD
	266	, FR30_INSN_BEQD, FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD
	267	, FR30_INSN_BND, FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD
	268	, FR30_INSN_BLTD, FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD
	269	, FR30_INSN_BLSD, FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H
	270	, FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB
	271	, FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
	272	, FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD
	273	, FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD
	274	, FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR
	275	, FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB
	276	, FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0
	277	, FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER
	278	, FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX
a86481d3 DB	279	} CGEN_INSN_TYPE;
	280
	281	/* Index of `invalid' insn place holder. */
	282	#define CGEN_INSN_INVALID FR30_INSN_INVALID
	283	/* Total number of insns in table. */
	284	#define MAX_INSNS ((int) FR30_INSN_MAX)
	285
	286	/* cgen.h uses things we just defined. */
	287	#include "opcode/cgen.h"
	288
	289	/* This struct records data prior to insertion or after extraction. */
	290	struct cgen_fields
	291	{
	292	long f_nil;
	293	long f_op1;
	294	long f_op2;
	295	long f_op3;
7a0737c8	296	long f_op4;
a86481d3	297	long f_op5;
7a0737c8	298	long f_cc;
e17387a5	299	long f_ccc;
a86481d3 DB	300	long f_Rj;
a86481d3 DB	301	long f_Ri;
7a0737c8 DB	302	long f_Rs1;
7a0737c8 DB	303	long f_Rs2;
e17387a5 DB	304	long f_Rjc;
	305	long f_Ric;
	306	long f_CRj;
	307	long f_CRi;
a86481d3	308	long f_u4;
e17387a5	309	long f_u4c;
a86481d3 DB	310	long f_i4;
	311	long f_m4;
	312	long f_u8;
	313	long f_i8;
a73911a7 DE	314	long f_i20_4;
	315	long f_i20_16;
	316	long f_i20;
95b03313	317	long f_i32;
6a1254af DB	318	long f_udisp6;
	319	long f_disp8;
	320	long f_disp9;
	321	long f_disp10;
7a0737c8 DB	322	long f_s10;
7a0737c8 DB	323	long f_u10;
6a1254af	324	long f_rel9;
7a0737c8 DB	325	long f_dir8;
	326	long f_dir9;
	327	long f_dir10;
6a1254af	328	long f_rel12;
e17387a5 DB	329	long f_reglist_hi;
e17387a5 DB	330	long f_reglist_low;
a86481d3 DB	331	int length;
	332	};
	333
	334	/* Attributes. */
	335	extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
	336	extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
	337	extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
	338
	339	/* Enum declaration for fr30 hardware types. */
	340	typedef enum hw_type {
	341	HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
e17387a5 DB	342	, HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
	343	, HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
	344	, HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
	345	, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX
a86481d3 DB	346	} HW_TYPE;
	347
	348	#define MAX_HW ((int) HW_MAX)
	349
	350	/* Hardware decls. */
	351
	352	extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
e17387a5	353	extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
6146431a	354	extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
6a1254af DB	355	extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
	356	extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
	357	extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
	358	extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
a86481d3 DB	359
	360	#define CGEN_INIT_PARSE(od) \
	361	{\
	362	}
	363	#define CGEN_INIT_INSERT(od) \
	364	{\
	365	}
	366	#define CGEN_INIT_EXTRACT(od) \
	367	{\
	368	}
	369	#define CGEN_INIT_PRINT(od) \
	370	{\
	371	}
	372
a73911a7 DE	373	/* -- opc.h */
	374
	375	/* ??? This can be improved upon. */
	376	#undef CGEN_DIS_HASH_SIZE
	377	#define CGEN_DIS_HASH_SIZE 16
	378	#undef CGEN_DIS_HASH
	379	#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
	380
	381	/* -- */
a86481d3 DB	382
	383
	384	#endif /* FR30_OPC_H */