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[AArch64] Reject invalid immediate operands to MSR PAN
[deliverable/binutils-gdb.git] / opcodes / i370-opc.c
CommitLineData
5b93d8bb 1/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
5b93d8bb
AM		 3 PowerPC version written by Ian Lance Taylor, Cygnus Support
4 Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
5
9b201bb5 6 This file is part of the GNU opcodes library.
5b93d8bb 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
5b93d8bb 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
5b93d8bb 17
47b0e7ad
NC		 18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
5b93d8bb 22
0d8dfecf 23#include "sysdep.h"
df7b86aa 24#include <stdio.h>
5b93d8bb
AM		 25#include "opcode/i370.h"
26
27/* This file holds the i370 opcode table. The opcode table
28 includes almost all of the extended instruction mnemonics. This
29 permits the disassembler to use them, and simplifies the assembler
30 logic, at the cost of increasing the table size. The table is
31 strictly constant data, so the compiler should be able to put it in
32 the .text section.
33
34 This file also holds the operand table. All knowledge about
35 inserting operands into instructions and vice-versa is kept in this
36 file. */
37\f
47b0e7ad
NC		 38/* The functions used to insert and extract complicated operands. */
39
40static i370_insn_t
41insert_ss_b2 (i370_insn_t insn, long value,
42 const char **errmsg ATTRIBUTE_UNUSED)
43{
44 insn.i[1] |= (value & 0xf) << 28;
45 return insn;
46}
47
48static i370_insn_t
49insert_ss_d2 (i370_insn_t insn, long value,
50 const char **errmsg ATTRIBUTE_UNUSED)
51{
52 insn.i[1] |= (value & 0xfff) << 16;
53 return insn;
54}
55
56static i370_insn_t
57insert_rxf_r3 (i370_insn_t insn, long value,
58 const char **errmsg ATTRIBUTE_UNUSED)
59{
60 insn.i[1] |= (value & 0xf) << 28;
61 return insn;
62}
63
64static long
65extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
66{
67 return (insn.i[1] >>28) & 0xf;
68}
69
70static long
71extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
72{
73 return (insn.i[1] >>16) & 0xfff;
74}
5b93d8bb 75
47b0e7ad
NC		 76static long
77extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
78{
79 return (insn.i[1] >>28) & 0xf;
80}
5b93d8bb
AM		 81\f
82/* The operands table.
83 The fields are bits, shift, insert, extract, flags, name.
84 The types:
85 I370_OPERAND_GPR register, must name a register, must be present
86 I370_OPERAND_RELATIVE displacement or legnth field, must be present
87 I370_OPERAND_BASE base register; if present, must name a register
88 if absent, should take value of zero
89 I370_OPERAND_INDEX index register; if present, must name a register
90 if absent, should take value of zero
47b0e7ad 91 I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */
5b93d8bb
AM		 92
93const struct i370_operand i370_operands[] =
94{
95 /* The zero index is used to indicate the end of the list of
96 operands. */
97#define UNUSED 0
98 { 0, 0, 0, 0, 0, "unused" },
99
100 /* The R1 register field in an RR form instruction. */
101#define RR_R1 (UNUSED + 1)
102#define RR_R1_MASK (0xf << 4)
103 { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },
104
105 /* The R2 register field in an RR form instruction. */
106#define RR_R2 (RR_R1 + 1)
107#define RR_R2_MASK (0xf)
108 { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },
109
110 /* The I field in an RR form SVC-style instruction. */
111#define RR_I (RR_R2 + 1)
112#define RR_I_MASK (0xff)
113 { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },
114
115 /* The R1 register field in an RRE form instruction. */
116#define RRE_R1 (RR_I + 1)
117#define RRE_R1_MASK (0xf << 4)
118 { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },
119
120 /* The R2 register field in an RRE form instruction. */
121#define RRE_R2 (RRE_R1 + 1)
122#define RRE_R2_MASK (0xf)
123 { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },
124
125 /* The R1 register field in an RRF form instruction. */
126#define RRF_R1 (RRE_R2 + 1)
127#define RRF_R1_MASK (0xf << 4)
128 { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },
129
130 /* The R2 register field in an RRF form instruction. */
131#define RRF_R2 (RRF_R1 + 1)
132#define RRF_R2_MASK (0xf)
133 { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },
134
135 /* The R3 register field in an RRF form instruction. */
136#define RRF_R3 (RRF_R2 + 1)
137#define RRF_R3_MASK (0xf << 12)
138 { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },
139
140 /* The R1 register field in an RX or RS form instruction. */
141#define RX_R1 (RRF_R3 + 1)
142#define RX_R1_MASK (0xf << 20)
143 { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },
144
145 /* The X2 index field in an RX form instruction. */
146#define RX_X2 (RX_R1 + 1)
147#define RX_X2_MASK (0xf << 16)
148 { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},
149
150 /* The B2 base field in an RX form instruction. */
151#define RX_B2 (RX_X2 + 1)
152#define RX_B2_MASK (0xf << 12)
153 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},
154
155 /* The D2 displacement field in an RX form instruction. */
156#define RX_D2 (RX_B2 + 1)
157#define RX_D2_MASK (0xfff)
158 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},
159
160 /* The R3 register field in an RXF form instruction. */
161#define RXF_R3 (RX_D2 + 1)
162#define RXF_R3_MASK (0xf << 12)
163 { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },
164
165 /* The D2 displacement field in an RS form instruction. */
166#define RS_D2 (RXF_R3 + 1)
167#define RS_D2_MASK (0xfff)
168 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
169
170 /* The R3 register field in an RS form instruction. */
171#define RS_R3 (RS_D2 + 1)
172#define RS_R3_MASK (0xf << 16)
173 { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
174
175 /* The B2 base field in an RS form instruction. */
176#define RS_B2 (RS_R3 + 1)
177#define RS_B2_MASK (0xf << 12)
178 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
179
180 /* The optional B2 base field in an RS form instruction. */
181 /* Note that this field will almost always be absent */
182#define RS_B2_OPT (RS_B2 + 1)
183#define RS_B2_OPT_MASK (0xf << 12)
184 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
185
186 /* The R1 register field in an RSI form instruction. */
187#define RSI_R1 (RS_B2_OPT + 1)
188#define RSI_R1_MASK (0xf << 20)
189 { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },
190
191 /* The R3 register field in an RSI form instruction. */
192#define RSI_R3 (RSI_R1 + 1)
193#define RSI_R3_MASK (0xf << 16)
194 { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },
195
196 /* The I2 immediate field in an RSI form instruction. */
197#define RSI_I2 (RSI_R3 + 1)
198#define RSI_I2_MASK (0xffff)
199 { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },
200
201 /* The R1 register field in an RI form instruction. */
202#define RI_R1 (RSI_I2 + 1)
203#define RI_R1_MASK (0xf << 20)
204 { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },
205
206 /* The I2 immediate field in an RI form instruction. */
207#define RI_I2 (RI_R1 + 1)
208#define RI_I2_MASK (0xffff)
209 { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },
210
211 /* The I2 index field in an SI form instruction. */
212#define SI_I2 (RI_I2 + 1)
213#define SI_I2_MASK (0xff << 16)
214 { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},
215
216 /* The B1 base register field in an SI form instruction. */
217#define SI_B1 (SI_I2 + 1)
218#define SI_B1_MASK (0xf << 12)
219 { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },
220
221 /* The D1 displacement field in an SI form instruction. */
222#define SI_D1 (SI_B1 + 1)
223#define SI_D1_MASK (0xfff)
224 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },
225
226 /* The B2 base register field in an S form instruction. */
227#define S_B2 (SI_D1 + 1)
228#define S_B2_MASK (0xf << 12)
229 { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },
230
231 /* The D2 displacement field in an S form instruction. */
232#define S_D2 (S_B2 + 1)
233#define S_D2_MASK (0xfff)
234 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
235
fc05c67f 236 /* The L length field in an SS form instruction. */
5b93d8bb
AM		 237#define SS_L (S_D2 + 1)
238#define SS_L_MASK (0xffff<<16)
239 { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
240
241 /* The B1 base register field in an SS form instruction. */
242#define SS_B1 (SS_L + 1)
243#define SS_B1_MASK (0xf << 12)
244 { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },
245
246 /* The D1 displacement field in an SS form instruction. */
247#define SS_D1 (SS_B1 + 1)
248#define SS_D1_MASK (0xfff)
249 { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },
250
251 /* The B2 base register field in an SS form instruction. */
252#define SS_B2 (SS_D1 + 1)
253#define SS_B2_MASK (0xf << 12)
254 { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },
255
256 /* The D2 displacement field in an SS form instruction. */
257#define SS_D2 (SS_B2 + 1)
258#define SS_D2_MASK (0xfff)
259 { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
43e65147 260
5b93d8bb
AM		 261};
262
5b93d8bb
AM		 263\f
264/* Macros used to form opcodes. */
265
266/* The short-instruction opcode. */
47b0e7ad 267#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)
5b93d8bb
AM		 268#define OPS_MASK OPS (0xff)
269
270/* the extended instruction opcode */
47b0e7ad 271#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)
5b93d8bb
AM		 272#define XOPS_MASK XOPS (0xff)
273
274/* the S instruction opcode */
47b0e7ad 275#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)
5b93d8bb
AM		 276#define SOPS_MASK SOPS (0xffff)
277
278/* the E instruction opcode */
47b0e7ad 279#define EOPS(x) (((unsigned short) (x)) & 0xffff)
5b93d8bb
AM		 280#define EOPS_MASK EOPS (0xffff)
281
282/* the RI instruction opcode */
47b0e7ad
NC		 283#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \
284 ((((unsigned short) (x)) & 0x00f) << 16))
5b93d8bb
AM		 285#define ROPS_MASK ROPS (0xfff)
286
47b0e7ad 287\f
5b93d8bb
AM		 288/* An E form instruction. */
289#define E(op) (EOPS (op))
290#define E_MASK E (0xffff)
291
292/* An RR form instruction. */
293#define RR(op, r1, r2) \
47b0e7ad
NC		 294 (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
295 ((((unsigned short) (r2)) & 0xf) ))
5b93d8bb
AM		 296
297#define RR_MASK RR (0xff, 0x0, 0x0)
298
299/* An SVC-style instruction. */
300#define SVC(op, i) \
47b0e7ad 301 (OPS (op) | (((unsigned short) (i)) & 0xff))
5b93d8bb
AM		 302
303#define SVC_MASK SVC (0xff, 0x0)
304
305/* An RRE form instruction. */
306#define RRE(op, r1, r2) \
47b0e7ad
NC		 307 (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
308 ((((unsigned short) (r2)) & 0xf) ))
5b93d8bb
AM		 309
310#define RRE_MASK RRE (0xffff, 0x0, 0x0)
311
312/* An RRF form instruction. */
313#define RRF(op, r3, r1, r2) \
47b0e7ad
NC		 314 (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \
315 ((((unsigned short) (r1)) & 0xf) << 4) | \
316 ((((unsigned short) (r2)) & 0xf) ))
5b93d8bb
AM		 317
318#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
319
fc05c67f 320/* An RX form instruction. */
5b93d8bb 321#define RX(op, r1, x2, b2, d2) \
47b0e7ad
NC		 322 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
323 ((((unsigned short) (x2)) & 0xf) << 16) | \
324 ((((unsigned short) (b2)) & 0xf) << 12) | \
325 ((((unsigned short) (d2)) & 0xfff)))
5b93d8bb
AM		 326
327#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
328
fc05c67f 329/* An RXE form instruction high word. */
5b93d8bb 330#define RXEH(op, r1, x2, b2, d2) \
47b0e7ad
NC		 331 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
332 ((((unsigned short) (x2)) & 0xf) << 16) | \
333 ((((unsigned short) (b2)) & 0xf) << 12) | \
334 ((((unsigned short) (d2)) & 0xfff)))
5b93d8bb
AM		 335
336#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
337
fc05c67f 338/* An RXE form instruction low word. */
5b93d8bb 339#define RXEL(op) \
47b0e7ad 340 ((((unsigned short) (op)) & 0xff) << 16 )
5b93d8bb
AM		 341
342#define RXEL_MASK RXEL (0xff)
343
fc05c67f 344/* An RXF form instruction high word. */
5b93d8bb 345#define RXFH(op, r1, x2, b2, d2) \
47b0e7ad
NC		 346 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
347 ((((unsigned short) (x2)) & 0xf) << 16) | \
348 ((((unsigned short) (b2)) & 0xf) << 12) | \
349 ((((unsigned short) (d2)) & 0xfff)))
5b93d8bb
AM		 350
351#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
352
fc05c67f 353/* An RXF form instruction low word. */
5b93d8bb 354#define RXFL(op, r3) \
47b0e7ad
NC		 355 (((((unsigned short) (r3)) & 0xf) << 28 ) | \
356 ((((unsigned short) (op)) & 0xff) << 16 ))
5b93d8bb
AM		 357
358#define RXFL_MASK RXFL (0xff, 0)
359
fc05c67f 360/* An RS form instruction. */
5b93d8bb 361#define RS(op, r1, b3, b2, d2) \
47b0e7ad
NC		 362 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
363 ((((unsigned short) (b3)) & 0xf) << 16) | \
364 ((((unsigned short) (b2)) & 0xf) << 12) | \
365 ((((unsigned short) (d2)) & 0xfff)))
5b93d8bb
AM		 366
367#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
368
fc05c67f 369/* An RSI form instruction. */
5b93d8bb 370#define RSI(op, r1, r3, i2) \
47b0e7ad
NC		 371 (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
372 ((((unsigned short) (r3)) & 0xf) << 16) | \
373 ((((unsigned short) (i2)) & 0xffff)))
5b93d8bb
AM		 374
375#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
376
fc05c67f 377/* An RI form instruction. */
5b93d8bb 378#define RI(op, r1, i2) \
47b0e7ad
NC		 379 (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
380 ((((unsigned short) (i2)) & 0xffff)))
5b93d8bb
AM		 381
382#define RI_MASK RI (0xfff, 0x0, 0x0)
383
fc05c67f 384/* An SI form instruction. */
5b93d8bb 385#define SI(op, i2, b1, d1) \
47b0e7ad
NC		 386 (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \
387 ((((unsigned short) (b1)) & 0xf) << 12) | \
388 ((((unsigned short) (d1)) & 0xfff)))
5b93d8bb
AM		 389
390#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
391
fc05c67f 392/* An S form instruction. */
5b93d8bb
AM		 393#define S(op, b2, d2) \
394 (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \
395 ((((unsigned short)(d2)) & 0xfff)))
396
397#define S_MASK S (0xffff, 0x0, 0x0)
398
fc05c67f 399/* An SS form instruction high word. */
5b93d8bb 400#define SSH(op, l, b1, d1) \
47b0e7ad
NC		 401 (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \
402 ((((unsigned short) (b1)) & 0xf) << 12) | \
403 ((((unsigned short) (d1)) & 0xfff)))
5b93d8bb 404
fc05c67f 405/* An SS form instruction low word. */
5b93d8bb 406#define SSL(b2, d2) \
47b0e7ad
NC		 407 ( ((((unsigned short) (b1)) & 0xf) << 28) | \
408 ((((unsigned short) (d1)) & 0xfff) << 16 ))
5b93d8bb
AM		 409
410#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
411
fc05c67f 412/* An SSE form instruction high word. */
5b93d8bb 413#define SSEH(op, b1, d1) \
47b0e7ad
NC		 414 (SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \
415 ((((unsigned short) (d1)) & 0xfff)))
5b93d8bb 416
fc05c67f 417/* An SSE form instruction low word. */
5b93d8bb 418#define SSEL(b2, d2) \
47b0e7ad
NC		 419 ( ((((unsigned short) (b1)) & 0xf) << 28) | \
420 ((((unsigned short) (d1)) & 0xfff) << 16 ))
5b93d8bb
AM		 421
422#define SSE_MASK SSEH (0xffff, 0x0, 0x0)
423
424\f
425/* Smaller names for the flags so each entry in the opcodes table will
426 fit on a single line. These flags are set up so that e.g. IXA means
427 the insn is supported on the 370/XA or newer architecture.
47b0e7ad 428 Note that 370 or older obsolete insn's are not supported ... */
5b93d8bb
AM		 429#define IBF I370_OPCODE_ESA390_BF
430#define IBS I370_OPCODE_ESA390_BS
431#define ICK I370_OPCODE_ESA390_CK
432#define ICM I370_OPCODE_ESA390_CM
433#define IFX I370_OPCODE_ESA390_FX
434#define IHX I370_OPCODE_ESA390_HX
435#define IIR I370_OPCODE_ESA390_IR
436#define IMI I370_OPCODE_ESA390_MI
437#define IPC I370_OPCODE_ESA390_PC
438#define IPL I370_OPCODE_ESA390_PL
439#define IQR I370_OPCODE_ESA390_QR
440#define IRP I370_OPCODE_ESA390_RP
441#define ISA I370_OPCODE_ESA390_SA
442#define ISG I370_OPCODE_ESA390_SG
443#define ISR I370_OPCODE_ESA390_SR
444#define ITR I370_OPCODE_ESA390_SR
445#define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
446#define IESA I390 | I370_OPCODE_ESA370
447#define IXA IESA | I370_OPCODE_370_XA
448#define I370 IXA | I370_OPCODE_370
449#define I360 I370 | I370_OPCODE_360
450
451\f
452/* The opcode table.
453
454 The format of the opcode table is:
455
456 NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS }
457
458 NAME is the name of the instruction.
459 OPCODE is the instruction opcode.
460 MASK is the opcode mask; this is used to tell the disassembler
461 which bits in the actual opcode must match OPCODE.
462 FLAGS are flags indicated what processors support the instruction.
463 OPERANDS is the list of operands.
464
465 The disassembler reads the table in order and prints the first
466 instruction which matches, so this table is sorted to put more
467 specific instructions before more general instructions. It is also
468 sorted by major opcode. */
469
47b0e7ad
NC		 470const struct i370_opcode i370_opcodes[] =
471{
5b93d8bb 472/* E form instructions */
fc05c67f 473{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} },
5b93d8bb 474
fc05c67f
NC		 475{ "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} },
476{ "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} },
5b93d8bb
AM		 477
478/* RR form instructions */
fc05c67f
NC		 479{ "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
480{ "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
481{ "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
482{ "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
483{ "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
484{ "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
485{ "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
486{ "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
487{ "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
488{ "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
489{ "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
490{ "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
491{ "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
492{ "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
493{ "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
494{ "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
495{ "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
496{ "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
497{ "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
498{ "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
499{ "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
500{ "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
501{ "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
502{ "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
503{ "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
504{ "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
505{ "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
506{ "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
507{ "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
508{ "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
509{ "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
510{ "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
511{ "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
512{ "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
513{ "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
514{ "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
515{ "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
516{ "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
517{ "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
518{ "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
519{ "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
520{ "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
521{ "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
522{ "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
523{ "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
524{ "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
525{ "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
526{ "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
527{ "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
528{ "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
529{ "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
530{ "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} },
531{ "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
532{ "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
533{ "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
534{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
535{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
5b93d8bb 536
47b0e7ad 537/* Unusual RR formats. */
fc05c67f 538{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
5b93d8bb 539
47b0e7ad 540/* RRE form instructions. */
fc05c67f
NC		 541{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
542{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
543{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
544{ "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
545{ "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} },
546{ "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} },
547{ "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
548{ "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
549{ "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
550{ "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
551{ "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
552{ "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
553{ "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} },
554{ "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
555{ "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
556{ "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
557{ "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
558{ "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
559{ "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
560{ "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
561{ "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
562{ "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
563{ "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
564{ "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
565{ "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
566{ "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
567{ "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
568{ "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
569{ "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
570{ "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
571{ "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
572{ "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
573{ "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
574{ "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
575{ "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
576{ "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
577{ "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
578{ "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
579{ "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
580{ "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
581{ "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
582{ "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
583{ "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
584{ "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
585{ "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
586{ "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
587{ "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
588{ "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
589{ "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
590{ "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
591{ "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
592{ "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
593{ "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
594{ "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
595{ "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
596{ "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
597{ "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
598{ "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
599{ "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
600{ "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
601{ "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
602{ "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
603{ "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
604{ "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
605{ "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
606{ "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
607{ "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
608{ "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
609{ "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
610{ "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
611{ "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
612{ "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
613{ "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
614{ "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
615{ "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} },
616{ "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
617{ "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
618{ "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
619{ "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
620{ "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} },
621{ "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} },
622{ "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
623{ "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
624{ "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
625{ "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
626{ "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
627{ "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
628{ "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
629{ "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
630{ "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
631{ "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
632{ "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
633{ "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
634{ "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
635{ "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
636{ "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
637{ "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
638{ "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
639{ "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
640{ "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
641{ "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
642{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
643{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
5b93d8bb 644
47b0e7ad 645/* RRF form instructions. */
fc05c67f
NC		 646{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
647{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
648{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
649{ "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
650{ "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
651{ "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
652{ "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
653{ "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
654{ "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
655{ "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
656{ "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
657{ "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
658{ "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
659{ "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
660{ "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
661{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
662{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
5b93d8bb 663
47b0e7ad 664/* RX form instructions. */
fc05c67f
NC		 665{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
666{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
667{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
668{ "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
669{ "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
670{ "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
671{ "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
672{ "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
673{ "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
674{ "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
675{ "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
676{ "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
677{ "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
678{ "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
679{ "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
680{ "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
681{ "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
682{ "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
683{ "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
684{ "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
685{ "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
686{ "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
687{ "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
688{ "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
689{ "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
690{ "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
691{ "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
692{ "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
693{ "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
694{ "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
695{ "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
696{ "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
697{ "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
698{ "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
699{ "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
700{ "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
701{ "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
702{ "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
703{ "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
704{ "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
705{ "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
706{ "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
707{ "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
708{ "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
709{ "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
710{ "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
711{ "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
712{ "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
713{ "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
714{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
715{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
5b93d8bb 716
47b0e7ad 717/* RXE form instructions. */
fc05c67f
NC		 718{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
719{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
720{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
721{ "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
722{ "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
723{ "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
724{ "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
725{ "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
726{ "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
727{ "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
728{ "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
729{ "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
730{ "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
731{ "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
732{ "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
733{ "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
734{ "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
735{ "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
736{ "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
737{ "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
738{ "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
739{ "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
740{ "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
741{ "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
742{ "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
743{ "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
744{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
745{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
5b93d8bb 746
47b0e7ad 747/* RXF form instructions. */
fc05c67f
NC		 748{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
749{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
750{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
751{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
5b93d8bb 752
47b0e7ad 753/* RS form instructions. */
fc05c67f
NC		 754{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
755{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
756{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
757{ "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
758{ "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
759{ "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
760{ "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
761{ "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
762{ "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
763{ "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
764{ "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
765{ "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
766{ "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
767{ "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
768{ "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
769{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
770{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
5b93d8bb 771
47b0e7ad 772/* RS form instructions with blank R3 and optional B2 (shift left/right). */
fc05c67f
NC		 773{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
774{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
775{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
776{ "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
777{ "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
778{ "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
779{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
780{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
5b93d8bb 781
47b0e7ad 782/* RSI form instructions. */
fc05c67f
NC		 783{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
784{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
5b93d8bb 785
47b0e7ad 786/* RI form instructions. */
fc05c67f
NC		 787{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
788{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
789{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
790{ "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
791{ "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
792{ "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
793{ "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
794{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
795{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
5b93d8bb 796
47b0e7ad 797/* SI form instructions. */
fc05c67f
NC		 798{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
799{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
800{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
801{ "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
802{ "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
803{ "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
804{ "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
805{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
806{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
5b93d8bb 807
47b0e7ad 808/* S form instructions. */
26ca5450
AJ		 809{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
810{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
811{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
812{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
813{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
814{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
815{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
816{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
817{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} },
818{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
819{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
820{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} },
821{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
822{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
823{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} },
824{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
825{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
826{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
827{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
828{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
829{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
830{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
831{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
832{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
833{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
834{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
835{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
836{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
837{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
838{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
839{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
840{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
841{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
842{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
843{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
844{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
845{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} },
846{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
847{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
5b93d8bb 848
47b0e7ad 849/* SS form instructions. */
fc05c67f
NC		 850{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
851{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
852{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
853{ "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
854{ "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
855{ "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
856{ "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
857{ "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
858{ "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
859{ "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
860{ "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
861{ "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
862{ "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
863{ "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
864{ "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
865{ "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
866{ "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
867{ "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
868{ "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
869{ "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
870{ "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
871{ "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
872{ "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
873{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
874{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
5b93d8bb 875
47b0e7ad 876/* SSE form instructions. */
fc05c67f
NC		 877{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
878{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
879{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
880{ "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
5b93d8bb
AM		 881
882/* */
883};
884
885const int i370_num_opcodes =
886 sizeof (i370_opcodes) / sizeof (i370_opcodes[0]);
887\f
888/* The macro table. This is only used by the assembler. */
889
47b0e7ad
NC		 890const struct i370_macro i370_macros[] =
891{
5b93d8bb
AM		 892{ "b", 1, I370, "bc 15,%0" },
893{ "br", 1, I370, "bcr 15,%0" },
894
895{ "nop", 1, I370, "bc 0,%0" },
896{ "nopr", 1, I370, "bcr 0,%0" },
897
898{ "bh", 1, I370, "bc 2,%0" },
899{ "bhr", 1, I370, "bcr 2,%0" },
900{ "bl", 1, I370, "bc 4,%0" },
901{ "blr", 1, I370, "bcr 4,%0" },
902{ "be", 1, I370, "bc 8,%0" },
903{ "ber", 1, I370, "bcr 8,%0" },
904
905{ "bnh", 1, I370, "bc 13,%0" },
906{ "bnhr", 1, I370, "bcr 13,%0" },
907{ "bnl", 1, I370, "bc 11,%0" },
908{ "bnlr", 1, I370, "bcr 11,%0" },
909{ "bne", 1, I370, "bc 7,%0" },
910{ "bner", 1, I370, "bcr 7,%0" },
911
912{ "bp", 1, I370, "bc 2,%0" },
913{ "bpr", 1, I370, "bcr 2,%0" },
914{ "bm", 1, I370, "bc 4,%0" },
915{ "bmr", 1, I370, "bcr 4,%0" },
916{ "bz", 1, I370, "bc 8,%0" },
917{ "bzr", 1, I370, "bcr 8,%0" },
918{ "bo", 1, I370, "bc 1,%0" },
919{ "bor", 1, I370, "bcr 1,%0" },
920
921{ "bnp", 1, I370, "bc 13,%0" },
922{ "bnpr", 1, I370, "bcr 13,%0" },
923{ "bnm", 1, I370, "bc 11,%0" },
924{ "bnmr", 1, I370, "bcr 11,%0" },
925{ "bnz", 1, I370, "bc 7,%0" },
926{ "bnzr", 1, I370, "bcr 7,%0" },
927{ "bno", 1, I370, "bc 14,%0" },
928{ "bnor", 1, I370, "bcr 14,%0" },
929
930{ "sync", 0, I370, "bcr 15,0" },
931
932};
933
934const int i370_num_macros =
935 sizeof (i370_macros) / sizeof (i370_macros[0]);
GDB Binutils - Deliverables
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