Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
9b201bb5 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
252b5132 | 4 | |
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
20f0a1fc | 6 | |
9b201bb5 | 7 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 8 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
9 | the Free Software Foundation; either version 3, or (at your option) |
10 | any later version. | |
20f0a1fc | 11 | |
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
20f0a1fc NC |
16 | |
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
20 | MA 02110-1301, USA. */ | |
21 | ||
20f0a1fc NC |
22 | |
23 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
24 | July 1988 | |
25 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
26 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
27 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
28 | ||
29 | /* The main tables describing the instructions is essentially a copy | |
30 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
31 | Programmers Manual. Usually, there is a capital letter, followed | |
32 | by a small letter. The capital letter tell the addressing mode, | |
33 | and the small letter tells about the operand size. Refer to | |
34 | the Intel manual for details. */ | |
252b5132 | 35 | |
252b5132 | 36 | #include "sysdep.h" |
dabbade6 | 37 | #include "dis-asm.h" |
252b5132 | 38 | #include "opintl.h" |
0b1cf022 | 39 | #include "opcode/i386.h" |
85f10a01 | 40 | #include "libiberty.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int fetch_data (struct disassemble_info *, bfd_byte *); |
45 | static void ckprefix (void); | |
46 | static const char *prefix_name (int, int); | |
47 | static int print_insn (bfd_vma, disassemble_info *); | |
48 | static void dofloat (int); | |
49 | static void OP_ST (int, int); | |
50 | static void OP_STi (int, int); | |
51 | static int putop (const char *, int); | |
52 | static void oappend (const char *); | |
53 | static void append_seg (void); | |
54 | static void OP_indirE (int, int); | |
55 | static void print_operand_value (char *, int, bfd_vma); | |
85f10a01 | 56 | static void OP_E_extended (int, int, int); |
5d669648 | 57 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
58 | static void OP_E (int, int); |
59 | static void OP_G (int, int); | |
60 | static bfd_vma get64 (void); | |
61 | static bfd_signed_vma get32 (void); | |
62 | static bfd_signed_vma get32s (void); | |
63 | static int get16 (void); | |
64 | static void set_op (bfd_vma, int); | |
b844680a | 65 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
66 | static void OP_REG (int, int); |
67 | static void OP_IMREG (int, int); | |
68 | static void OP_I (int, int); | |
69 | static void OP_I64 (int, int); | |
70 | static void OP_sI (int, int); | |
71 | static void OP_J (int, int); | |
72 | static void OP_SEG (int, int); | |
73 | static void OP_DIR (int, int); | |
74 | static void OP_OFF (int, int); | |
75 | static void OP_OFF64 (int, int); | |
76 | static void ptr_reg (int, int); | |
77 | static void OP_ESreg (int, int); | |
78 | static void OP_DSreg (int, int); | |
79 | static void OP_C (int, int); | |
80 | static void OP_D (int, int); | |
81 | static void OP_T (int, int); | |
6f74c397 | 82 | static void OP_R (int, int); |
26ca5450 AJ |
83 | static void OP_MMX (int, int); |
84 | static void OP_XMM (int, int); | |
85 | static void OP_EM (int, int); | |
86 | static void OP_EX (int, int); | |
4d9567e0 MM |
87 | static void OP_EMC (int,int); |
88 | static void OP_MXC (int,int); | |
26ca5450 AJ |
89 | static void OP_MS (int, int); |
90 | static void OP_XS (int, int); | |
cc0ec051 | 91 | static void OP_M (int, int); |
cc0ec051 | 92 | static void OP_0f07 (int, int); |
b844680a L |
93 | static void OP_Monitor (int, int); |
94 | static void OP_Mwait (int, int); | |
46e883c5 L |
95 | static void NOP_Fixup1 (int, int); |
96 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 97 | static void OP_3DNowSuffix (int, int); |
ad19981d | 98 | static void CMP_Fixup (int, int); |
26ca5450 | 99 | static void BadOp (void); |
35c52694 | 100 | static void REP_Fixup (int, int); |
f5804c90 | 101 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 102 | static void XMM_Fixup (int, int); |
381d071f | 103 | static void CRC32_Fixup (int, int); |
85f10a01 MM |
104 | static void print_drex_arg (unsigned int, int, int); |
105 | static void OP_DREX4 (int, int); | |
106 | static void OP_DREX3 (int, int); | |
107 | static void OP_DREX_ICMP (int, int); | |
108 | static void OP_DREX_FCMP (int, int); | |
252b5132 | 109 | |
6608db57 | 110 | struct dis_private { |
252b5132 RH |
111 | /* Points to first byte not fetched. */ |
112 | bfd_byte *max_fetched; | |
0b1cf022 | 113 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 114 | bfd_vma insn_start; |
e396998b | 115 | int orig_sizeflag; |
252b5132 RH |
116 | jmp_buf bailout; |
117 | }; | |
118 | ||
cb712a9e L |
119 | enum address_mode |
120 | { | |
121 | mode_16bit, | |
122 | mode_32bit, | |
123 | mode_64bit | |
124 | }; | |
125 | ||
126 | enum address_mode address_mode; | |
52b15da3 | 127 | |
5076851f ILT |
128 | /* Flags for the prefixes for the current instruction. See below. */ |
129 | static int prefixes; | |
130 | ||
52b15da3 JH |
131 | /* REX prefix the current instruction. See below. */ |
132 | static int rex; | |
133 | /* Bits of REX we've already used. */ | |
134 | static int rex_used; | |
52b15da3 JH |
135 | /* Mark parts used in the REX prefix. When we are testing for |
136 | empty prefix (for 8bit register REX extension), just mask it | |
137 | out. Otherwise test for REX bit is excuse for existence of REX | |
138 | only in case value is nonzero. */ | |
139 | #define USED_REX(value) \ | |
140 | { \ | |
141 | if (value) \ | |
161a04f6 L |
142 | { \ |
143 | if ((rex & value)) \ | |
144 | rex_used |= (value) | REX_OPCODE; \ | |
145 | } \ | |
52b15da3 | 146 | else \ |
161a04f6 | 147 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
148 | } |
149 | ||
85f10a01 MM |
150 | /* Special 'registers' for DREX handling */ |
151 | #define DREX_REG_UNKNOWN 1000 /* not initialized */ | |
152 | #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */ | |
153 | ||
154 | /* The DREX byte has the following fields: | |
155 | Bits 7-4 -- DREX.Dest, xmm destination register | |
156 | Bit 3 -- DREX.OC0, operand config bit defines operand order | |
157 | Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register | |
158 | Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field | |
159 | Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field, | |
160 | SIB base field, or opcode reg field. */ | |
161 | #define DREX_XMM(drex) ((drex >> 4) & 0xf) | |
162 | #define DREX_OC0(drex) ((drex >> 3) & 0x1) | |
163 | ||
7d421014 ILT |
164 | /* Flags for prefixes which we somehow handled when printing the |
165 | current instruction. */ | |
166 | static int used_prefixes; | |
167 | ||
5076851f ILT |
168 | /* Flags stored in PREFIXES. */ |
169 | #define PREFIX_REPZ 1 | |
170 | #define PREFIX_REPNZ 2 | |
171 | #define PREFIX_LOCK 4 | |
172 | #define PREFIX_CS 8 | |
173 | #define PREFIX_SS 0x10 | |
174 | #define PREFIX_DS 0x20 | |
175 | #define PREFIX_ES 0x40 | |
176 | #define PREFIX_FS 0x80 | |
177 | #define PREFIX_GS 0x100 | |
178 | #define PREFIX_DATA 0x200 | |
179 | #define PREFIX_ADDR 0x400 | |
180 | #define PREFIX_FWAIT 0x800 | |
181 | ||
252b5132 RH |
182 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
183 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
184 | on error. */ | |
185 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 186 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
187 | ? 1 : fetch_data ((info), (addr))) |
188 | ||
189 | static int | |
26ca5450 | 190 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
191 | { |
192 | int status; | |
6608db57 | 193 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
194 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
195 | ||
0b1cf022 | 196 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
197 | status = (*info->read_memory_func) (start, |
198 | priv->max_fetched, | |
199 | addr - priv->max_fetched, | |
200 | info); | |
201 | else | |
202 | status = -1; | |
252b5132 RH |
203 | if (status != 0) |
204 | { | |
7d421014 | 205 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
206 | print_insn_i386 will do something sensible. Otherwise, print |
207 | an error. We do that here because this is where we know | |
208 | STATUS. */ | |
7d421014 | 209 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 210 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
211 | longjmp (priv->bailout, 1); |
212 | } | |
213 | else | |
214 | priv->max_fetched = addr; | |
215 | return 1; | |
216 | } | |
217 | ||
ce518a5f L |
218 | #define XX { NULL, 0 } |
219 | ||
220 | #define Eb { OP_E, b_mode } | |
221 | #define Ev { OP_E, v_mode } | |
222 | #define Ed { OP_E, d_mode } | |
223 | #define Edq { OP_E, dq_mode } | |
224 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
225 | #define Edqb { OP_E, dqb_mode } |
226 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 227 | #define Eq { OP_E, q_mode } |
ce518a5f L |
228 | #define indirEv { OP_indirE, stack_v_mode } |
229 | #define indirEp { OP_indirE, f_mode } | |
230 | #define stackEv { OP_E, stack_v_mode } | |
231 | #define Em { OP_E, m_mode } | |
232 | #define Ew { OP_E, w_mode } | |
233 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 234 | #define Ma { OP_M, a_mode } |
b844680a | 235 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 236 | #define Md { OP_M, d_mode } |
ce518a5f L |
237 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
238 | #define Mq { OP_M, q_mode } | |
4ee52178 | 239 | #define Mx { OP_M, x_mode } |
ce518a5f L |
240 | #define Gb { OP_G, b_mode } |
241 | #define Gv { OP_G, v_mode } | |
242 | #define Gd { OP_G, d_mode } | |
243 | #define Gdq { OP_G, dq_mode } | |
244 | #define Gm { OP_G, m_mode } | |
245 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
246 | #define Rd { OP_R, d_mode } |
247 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
248 | #define Ib { OP_I, b_mode } |
249 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
250 | #define Iv { OP_I, v_mode } | |
251 | #define Iq { OP_I, q_mode } | |
252 | #define Iv64 { OP_I64, v_mode } | |
253 | #define Iw { OP_I, w_mode } | |
254 | #define I1 { OP_I, const_1_mode } | |
255 | #define Jb { OP_J, b_mode } | |
256 | #define Jv { OP_J, v_mode } | |
257 | #define Cm { OP_C, m_mode } | |
258 | #define Dm { OP_D, m_mode } | |
259 | #define Td { OP_T, d_mode } | |
b844680a | 260 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
261 | |
262 | #define RMeAX { OP_REG, eAX_reg } | |
263 | #define RMeBX { OP_REG, eBX_reg } | |
264 | #define RMeCX { OP_REG, eCX_reg } | |
265 | #define RMeDX { OP_REG, eDX_reg } | |
266 | #define RMeSP { OP_REG, eSP_reg } | |
267 | #define RMeBP { OP_REG, eBP_reg } | |
268 | #define RMeSI { OP_REG, eSI_reg } | |
269 | #define RMeDI { OP_REG, eDI_reg } | |
270 | #define RMrAX { OP_REG, rAX_reg } | |
271 | #define RMrBX { OP_REG, rBX_reg } | |
272 | #define RMrCX { OP_REG, rCX_reg } | |
273 | #define RMrDX { OP_REG, rDX_reg } | |
274 | #define RMrSP { OP_REG, rSP_reg } | |
275 | #define RMrBP { OP_REG, rBP_reg } | |
276 | #define RMrSI { OP_REG, rSI_reg } | |
277 | #define RMrDI { OP_REG, rDI_reg } | |
278 | #define RMAL { OP_REG, al_reg } | |
279 | #define RMAL { OP_REG, al_reg } | |
280 | #define RMCL { OP_REG, cl_reg } | |
281 | #define RMDL { OP_REG, dl_reg } | |
282 | #define RMBL { OP_REG, bl_reg } | |
283 | #define RMAH { OP_REG, ah_reg } | |
284 | #define RMCH { OP_REG, ch_reg } | |
285 | #define RMDH { OP_REG, dh_reg } | |
286 | #define RMBH { OP_REG, bh_reg } | |
287 | #define RMAX { OP_REG, ax_reg } | |
288 | #define RMDX { OP_REG, dx_reg } | |
289 | ||
290 | #define eAX { OP_IMREG, eAX_reg } | |
291 | #define eBX { OP_IMREG, eBX_reg } | |
292 | #define eCX { OP_IMREG, eCX_reg } | |
293 | #define eDX { OP_IMREG, eDX_reg } | |
294 | #define eSP { OP_IMREG, eSP_reg } | |
295 | #define eBP { OP_IMREG, eBP_reg } | |
296 | #define eSI { OP_IMREG, eSI_reg } | |
297 | #define eDI { OP_IMREG, eDI_reg } | |
298 | #define AL { OP_IMREG, al_reg } | |
299 | #define CL { OP_IMREG, cl_reg } | |
300 | #define DL { OP_IMREG, dl_reg } | |
301 | #define BL { OP_IMREG, bl_reg } | |
302 | #define AH { OP_IMREG, ah_reg } | |
303 | #define CH { OP_IMREG, ch_reg } | |
304 | #define DH { OP_IMREG, dh_reg } | |
305 | #define BH { OP_IMREG, bh_reg } | |
306 | #define AX { OP_IMREG, ax_reg } | |
307 | #define DX { OP_IMREG, dx_reg } | |
308 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
309 | #define indirDX { OP_IMREG, indir_dx_reg } | |
310 | ||
311 | #define Sw { OP_SEG, w_mode } | |
312 | #define Sv { OP_SEG, v_mode } | |
313 | #define Ap { OP_DIR, 0 } | |
314 | #define Ob { OP_OFF64, b_mode } | |
315 | #define Ov { OP_OFF64, v_mode } | |
316 | #define Xb { OP_DSreg, eSI_reg } | |
317 | #define Xv { OP_DSreg, eSI_reg } | |
318 | #define Xz { OP_DSreg, eSI_reg } | |
319 | #define Yb { OP_ESreg, eDI_reg } | |
320 | #define Yv { OP_ESreg, eDI_reg } | |
321 | #define DSBX { OP_DSreg, eBX_reg } | |
322 | ||
323 | #define es { OP_REG, es_reg } | |
324 | #define ss { OP_REG, ss_reg } | |
325 | #define cs { OP_REG, cs_reg } | |
326 | #define ds { OP_REG, ds_reg } | |
327 | #define fs { OP_REG, fs_reg } | |
328 | #define gs { OP_REG, gs_reg } | |
329 | ||
330 | #define MX { OP_MMX, 0 } | |
331 | #define XM { OP_XMM, 0 } | |
332 | #define EM { OP_EM, v_mode } | |
09a2c6cf | 333 | #define EMd { OP_EM, d_mode } |
14051056 | 334 | #define EMx { OP_EM, x_mode } |
8976381e | 335 | #define EXw { OP_EX, w_mode } |
09a2c6cf L |
336 | #define EXd { OP_EX, d_mode } |
337 | #define EXq { OP_EX, q_mode } | |
338 | #define EXx { OP_EX, x_mode } | |
ce518a5f L |
339 | #define MS { OP_MS, v_mode } |
340 | #define XS { OP_XS, v_mode } | |
09335d05 | 341 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 342 | #define MXC { OP_MXC, 0 } |
ce518a5f | 343 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 344 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 345 | #define XMM0 { XMM_Fixup, 0 } |
252b5132 | 346 | |
35c52694 | 347 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
348 | #define Xbr { REP_Fixup, eSI_reg } |
349 | #define Xvr { REP_Fixup, eSI_reg } | |
350 | #define Ybr { REP_Fixup, eDI_reg } | |
351 | #define Yvr { REP_Fixup, eDI_reg } | |
352 | #define Yzr { REP_Fixup, eDI_reg } | |
353 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
354 | #define ALr { REP_Fixup, al_reg } | |
355 | #define eAXr { REP_Fixup, eAX_reg } | |
356 | ||
357 | #define cond_jump_flag { NULL, cond_jump_mode } | |
358 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 359 | |
252b5132 | 360 | /* bits in sizeflag */ |
252b5132 | 361 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
362 | #define AFLAG 2 |
363 | #define DFLAG 1 | |
364 | ||
d55ee72f L |
365 | /* byte operand */ |
366 | #define b_mode 1 | |
367 | /* operand size depends on prefixes */ | |
630c2cc5 | 368 | #define v_mode (b_mode + 1) |
d55ee72f L |
369 | /* word operand */ |
370 | #define w_mode (v_mode + 1) | |
371 | /* double word operand */ | |
372 | #define d_mode (w_mode + 1) | |
373 | /* quad word operand */ | |
374 | #define q_mode (d_mode + 1) | |
375 | /* ten-byte operand */ | |
376 | #define t_mode (q_mode + 1) | |
377 | /* 16-byte XMM operand */ | |
378 | #define x_mode (t_mode + 1) | |
379 | /* d_mode in 32bit, q_mode in 64bit mode. */ | |
380 | #define m_mode (x_mode + 1) | |
34b772a6 JB |
381 | /* pair of v_mode operands */ |
382 | #define a_mode (m_mode + 1) | |
383 | #define cond_jump_mode (a_mode + 1) | |
d55ee72f L |
384 | #define loop_jcxz_mode (cond_jump_mode + 1) |
385 | /* operand size depends on REX prefixes. */ | |
386 | #define dq_mode (loop_jcxz_mode + 1) | |
387 | /* registers like dq_mode, memory like w_mode. */ | |
388 | #define dqw_mode (dq_mode + 1) | |
389 | /* 4- or 6-byte pointer operand */ | |
390 | #define f_mode (dqw_mode + 1) | |
391 | #define const_1_mode (f_mode + 1) | |
392 | /* v_mode for stack-related opcodes. */ | |
393 | #define stack_v_mode (const_1_mode + 1) | |
394 | /* non-quad operand size depends on prefixes */ | |
395 | #define z_mode (stack_v_mode + 1) | |
396 | /* 16-byte operand */ | |
397 | #define o_mode (z_mode + 1) | |
398 | /* registers like dq_mode, memory like b_mode. */ | |
399 | #define dqb_mode (o_mode + 1) | |
400 | /* registers like dq_mode, memory like d_mode. */ | |
401 | #define dqd_mode (dqb_mode + 1) | |
402 | ||
403 | #define es_reg (dqd_mode + 1) | |
404 | #define cs_reg (es_reg + 1) | |
405 | #define ss_reg (cs_reg + 1) | |
406 | #define ds_reg (ss_reg + 1) | |
407 | #define fs_reg (ds_reg + 1) | |
408 | #define gs_reg (fs_reg + 1) | |
409 | ||
410 | #define eAX_reg (gs_reg + 1) | |
411 | #define eCX_reg (eAX_reg + 1) | |
412 | #define eDX_reg (eCX_reg + 1) | |
413 | #define eBX_reg (eDX_reg + 1) | |
414 | #define eSP_reg (eBX_reg + 1) | |
415 | #define eBP_reg (eSP_reg + 1) | |
416 | #define eSI_reg (eBP_reg + 1) | |
417 | #define eDI_reg (eSI_reg + 1) | |
418 | ||
419 | #define al_reg (eDI_reg + 1) | |
420 | #define cl_reg (al_reg + 1) | |
421 | #define dl_reg (cl_reg + 1) | |
422 | #define bl_reg (dl_reg + 1) | |
423 | #define ah_reg (bl_reg + 1) | |
424 | #define ch_reg (ah_reg + 1) | |
425 | #define dh_reg (ch_reg + 1) | |
426 | #define bh_reg (dh_reg + 1) | |
427 | ||
428 | #define ax_reg (bh_reg + 1) | |
429 | #define cx_reg (ax_reg + 1) | |
430 | #define dx_reg (cx_reg + 1) | |
431 | #define bx_reg (dx_reg + 1) | |
432 | #define sp_reg (bx_reg + 1) | |
433 | #define bp_reg (sp_reg + 1) | |
434 | #define si_reg (bp_reg + 1) | |
435 | #define di_reg (si_reg + 1) | |
436 | ||
437 | #define rAX_reg (di_reg + 1) | |
438 | #define rCX_reg (rAX_reg + 1) | |
439 | #define rDX_reg (rCX_reg + 1) | |
440 | #define rBX_reg (rDX_reg + 1) | |
441 | #define rSP_reg (rBX_reg + 1) | |
442 | #define rBP_reg (rSP_reg + 1) | |
443 | #define rSI_reg (rBP_reg + 1) | |
444 | #define rDI_reg (rSI_reg + 1) | |
445 | ||
446 | #define z_mode_ax_reg (rDI_reg + 1) | |
447 | #define indir_dx_reg (z_mode_ax_reg + 1) | |
448 | ||
449 | #define MAX_BYTEMODE indir_dx_reg | |
450 | ||
451 | /* Flags that are OR'ed into the bytemode field to pass extra | |
452 | information. */ | |
453 | #define DREX_OC1 0x10000 /* OC1 bit set */ | |
454 | #define DREX_NO_OC0 0x20000 /* OC0 bit not used */ | |
455 | #define DREX_MASK 0x40000 /* mask to delete */ | |
456 | ||
457 | #if MAX_BYTEMODE >= DREX_OC1 | |
458 | #error MAX_BYTEMODE must be less than DREX_OC1 | |
459 | #endif | |
252b5132 | 460 | |
1b0d430b L |
461 | #define FLOATCODE 1 |
462 | #define USE_REG_TABLE (FLOATCODE + 1) | |
463 | #define USE_MOD_TABLE (USE_REG_TABLE + 1) | |
464 | #define USE_RM_TABLE (USE_MOD_TABLE + 1) | |
465 | #define USE_PREFIX_TABLE (USE_RM_TABLE + 1) | |
466 | #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1) | |
467 | #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1) | |
6439fc28 | 468 | |
1ceb70f8 | 469 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 470 | |
4e7d34a6 | 471 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
472 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
473 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
474 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
475 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
476 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
477 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
1ceb70f8 L |
478 | |
479 | #define REG_80 0 | |
480 | #define REG_81 (REG_80 + 1) | |
481 | #define REG_82 (REG_81 + 1) | |
482 | #define REG_8F (REG_82 + 1) | |
483 | #define REG_C0 (REG_8F + 1) | |
484 | #define REG_C1 (REG_C0 + 1) | |
485 | #define REG_C6 (REG_C1 + 1) | |
486 | #define REG_C7 (REG_C6 + 1) | |
487 | #define REG_D0 (REG_C7 + 1) | |
488 | #define REG_D1 (REG_D0 + 1) | |
489 | #define REG_D2 (REG_D1 + 1) | |
490 | #define REG_D3 (REG_D2 + 1) | |
491 | #define REG_F6 (REG_D3 + 1) | |
492 | #define REG_F7 (REG_F6 + 1) | |
493 | #define REG_FE (REG_F7 + 1) | |
494 | #define REG_FF (REG_FE + 1) | |
495 | #define REG_0F00 (REG_FF + 1) | |
496 | #define REG_0F01 (REG_0F00 + 1) | |
b5b1fc4f L |
497 | #define REG_0F0D (REG_0F01 + 1) |
498 | #define REG_0F18 (REG_0F0D + 1) | |
1ceb70f8 L |
499 | #define REG_0F71 (REG_0F18 + 1) |
500 | #define REG_0F72 (REG_0F71 + 1) | |
501 | #define REG_0F73 (REG_0F72 + 1) | |
502 | #define REG_0FA6 (REG_0F73 + 1) | |
503 | #define REG_0FA7 (REG_0FA6 + 1) | |
504 | #define REG_0FAE (REG_0FA7 + 1) | |
505 | #define REG_0FBA (REG_0FAE + 1) | |
506 | #define REG_0FC7 (REG_0FBA + 1) | |
507 | ||
508 | #define MOD_8D 0 | |
92fddf8e | 509 | #define MOD_0F01_REG_0 (MOD_8D + 1) |
1ceb70f8 L |
510 | #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1) |
511 | #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1) | |
512 | #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1) | |
513 | #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1) | |
92fddf8e L |
514 | #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1) |
515 | #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1) | |
516 | #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1) | |
517 | #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1) | |
518 | #define MOD_0F18_REG_0 (MOD_0F17 + 1) | |
1ceb70f8 L |
519 | #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1) |
520 | #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1) | |
521 | #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1) | |
92fddf8e L |
522 | #define MOD_0F20 (MOD_0F18_REG_3 + 1) |
523 | #define MOD_0F21 (MOD_0F20 + 1) | |
524 | #define MOD_0F22 (MOD_0F21 + 1) | |
525 | #define MOD_0F23 (MOD_0F22 + 1) | |
526 | #define MOD_0F24 (MOD_0F23 + 1) | |
527 | #define MOD_0F26 (MOD_0F24 + 1) | |
75c135a8 L |
528 | #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1) |
529 | #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1) | |
530 | #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1) | |
531 | #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1) | |
532 | #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1) | |
533 | #define MOD_0F71_REG_2 (MOD_0F51 + 1) | |
1ceb70f8 L |
534 | #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1) |
535 | #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1) | |
536 | #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1) | |
537 | #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1) | |
538 | #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1) | |
539 | #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1) | |
540 | #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1) | |
541 | #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1) | |
542 | #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1) | |
543 | #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1) | |
544 | #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1) | |
545 | #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1) | |
546 | #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1) | |
475a2301 L |
547 | #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1) |
548 | #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1) | |
1ceb70f8 L |
549 | #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1) |
550 | #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1) | |
92fddf8e L |
551 | #define MOD_0FB2 (MOD_0FAE_REG_7 + 1) |
552 | #define MOD_0FB4 (MOD_0FB2 + 1) | |
553 | #define MOD_0FB5 (MOD_0FB4 + 1) | |
554 | #define MOD_0FC7_REG_6 (MOD_0FB5 + 1) | |
1ceb70f8 | 555 | #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1) |
75c135a8 L |
556 | #define MOD_0FD7 (MOD_0FC7_REG_7 + 1) |
557 | #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1) | |
558 | #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1) | |
559 | #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1) | |
560 | #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1) | |
1ceb70f8 L |
561 | #define MOD_C4_32BIT (MOD_62_32BIT + 1) |
562 | #define MOD_C5_32BIT (MOD_C4_32BIT + 1) | |
563 | ||
564 | #define RM_0F01_REG_0 0 | |
565 | #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1) | |
475a2301 L |
566 | #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1) |
567 | #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1) | |
1ceb70f8 L |
568 | #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1) |
569 | #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1) | |
570 | #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1) | |
571 | #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1) | |
572 | ||
573 | #define PREFIX_90 0 | |
574 | #define PREFIX_0F10 (PREFIX_90 + 1) | |
575 | #define PREFIX_0F11 (PREFIX_0F10 + 1) | |
576 | #define PREFIX_0F12 (PREFIX_0F11 + 1) | |
577 | #define PREFIX_0F16 (PREFIX_0F12 + 1) | |
578 | #define PREFIX_0F2A (PREFIX_0F16 + 1) | |
579 | #define PREFIX_0F2B (PREFIX_0F2A + 1) | |
580 | #define PREFIX_0F2C (PREFIX_0F2B + 1) | |
581 | #define PREFIX_0F2D (PREFIX_0F2C + 1) | |
582 | #define PREFIX_0F2E (PREFIX_0F2D + 1) | |
583 | #define PREFIX_0F2F (PREFIX_0F2E + 1) | |
584 | #define PREFIX_0F51 (PREFIX_0F2F + 1) | |
585 | #define PREFIX_0F52 (PREFIX_0F51 + 1) | |
586 | #define PREFIX_0F53 (PREFIX_0F52 + 1) | |
587 | #define PREFIX_0F58 (PREFIX_0F53 + 1) | |
588 | #define PREFIX_0F59 (PREFIX_0F58 + 1) | |
589 | #define PREFIX_0F5A (PREFIX_0F59 + 1) | |
590 | #define PREFIX_0F5B (PREFIX_0F5A + 1) | |
591 | #define PREFIX_0F5C (PREFIX_0F5B + 1) | |
592 | #define PREFIX_0F5D (PREFIX_0F5C + 1) | |
593 | #define PREFIX_0F5E (PREFIX_0F5D + 1) | |
594 | #define PREFIX_0F5F (PREFIX_0F5E + 1) | |
595 | #define PREFIX_0F60 (PREFIX_0F5F + 1) | |
596 | #define PREFIX_0F61 (PREFIX_0F60 + 1) | |
597 | #define PREFIX_0F62 (PREFIX_0F61 + 1) | |
598 | #define PREFIX_0F6C (PREFIX_0F62 + 1) | |
599 | #define PREFIX_0F6D (PREFIX_0F6C + 1) | |
600 | #define PREFIX_0F6F (PREFIX_0F6D + 1) | |
601 | #define PREFIX_0F70 (PREFIX_0F6F + 1) | |
92fddf8e L |
602 | #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1) |
603 | #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1) | |
604 | #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1) | |
1ceb70f8 L |
605 | #define PREFIX_0F79 (PREFIX_0F78 + 1) |
606 | #define PREFIX_0F7C (PREFIX_0F79 + 1) | |
607 | #define PREFIX_0F7D (PREFIX_0F7C + 1) | |
608 | #define PREFIX_0F7E (PREFIX_0F7D + 1) | |
609 | #define PREFIX_0F7F (PREFIX_0F7E + 1) | |
610 | #define PREFIX_0FB8 (PREFIX_0F7F + 1) | |
611 | #define PREFIX_0FBD (PREFIX_0FB8 + 1) | |
612 | #define PREFIX_0FC2 (PREFIX_0FBD + 1) | |
4ee52178 L |
613 | #define PREFIX_0FC3 (PREFIX_0FC2 + 1) |
614 | #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1) | |
92fddf8e | 615 | #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1) |
1ceb70f8 L |
616 | #define PREFIX_0FD6 (PREFIX_0FD0 + 1) |
617 | #define PREFIX_0FE6 (PREFIX_0FD6 + 1) | |
618 | #define PREFIX_0FE7 (PREFIX_0FE6 + 1) | |
619 | #define PREFIX_0FF0 (PREFIX_0FE7 + 1) | |
620 | #define PREFIX_0FF7 (PREFIX_0FF0 + 1) | |
621 | #define PREFIX_0F3810 (PREFIX_0FF7 + 1) | |
622 | #define PREFIX_0F3814 (PREFIX_0F3810 + 1) | |
623 | #define PREFIX_0F3815 (PREFIX_0F3814 + 1) | |
624 | #define PREFIX_0F3817 (PREFIX_0F3815 + 1) | |
625 | #define PREFIX_0F3820 (PREFIX_0F3817 + 1) | |
626 | #define PREFIX_0F3821 (PREFIX_0F3820 + 1) | |
627 | #define PREFIX_0F3822 (PREFIX_0F3821 + 1) | |
628 | #define PREFIX_0F3823 (PREFIX_0F3822 + 1) | |
629 | #define PREFIX_0F3824 (PREFIX_0F3823 + 1) | |
630 | #define PREFIX_0F3825 (PREFIX_0F3824 + 1) | |
631 | #define PREFIX_0F3828 (PREFIX_0F3825 + 1) | |
632 | #define PREFIX_0F3829 (PREFIX_0F3828 + 1) | |
633 | #define PREFIX_0F382A (PREFIX_0F3829 + 1) | |
634 | #define PREFIX_0F382B (PREFIX_0F382A + 1) | |
635 | #define PREFIX_0F3830 (PREFIX_0F382B + 1) | |
636 | #define PREFIX_0F3831 (PREFIX_0F3830 + 1) | |
637 | #define PREFIX_0F3832 (PREFIX_0F3831 + 1) | |
638 | #define PREFIX_0F3833 (PREFIX_0F3832 + 1) | |
639 | #define PREFIX_0F3834 (PREFIX_0F3833 + 1) | |
640 | #define PREFIX_0F3835 (PREFIX_0F3834 + 1) | |
641 | #define PREFIX_0F3837 (PREFIX_0F3835 + 1) | |
642 | #define PREFIX_0F3838 (PREFIX_0F3837 + 1) | |
643 | #define PREFIX_0F3839 (PREFIX_0F3838 + 1) | |
644 | #define PREFIX_0F383A (PREFIX_0F3839 + 1) | |
645 | #define PREFIX_0F383B (PREFIX_0F383A + 1) | |
646 | #define PREFIX_0F383C (PREFIX_0F383B + 1) | |
647 | #define PREFIX_0F383D (PREFIX_0F383C + 1) | |
648 | #define PREFIX_0F383E (PREFIX_0F383D + 1) | |
649 | #define PREFIX_0F383F (PREFIX_0F383E + 1) | |
650 | #define PREFIX_0F3840 (PREFIX_0F383F + 1) | |
651 | #define PREFIX_0F3841 (PREFIX_0F3840 + 1) | |
652 | #define PREFIX_0F38F0 (PREFIX_0F3841 + 1) | |
653 | #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1) | |
654 | #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1) | |
655 | #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1) | |
656 | #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1) | |
657 | #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1) | |
658 | #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1) | |
659 | #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1) | |
660 | #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1) | |
661 | #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1) | |
662 | #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1) | |
663 | #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1) | |
664 | #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1) | |
665 | #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1) | |
666 | #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1) | |
667 | #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1) | |
668 | #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1) | |
669 | #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1) | |
670 | #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1) | |
671 | #define PREFIX_0F3A60 (PREFIX_0F3A42 + 1) | |
672 | #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1) | |
673 | #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1) | |
674 | #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1) | |
4e7d34a6 L |
675 | |
676 | #define X86_64_06 0 | |
677 | #define X86_64_07 (X86_64_06 + 1) | |
678 | #define X86_64_0D (X86_64_07 + 1) | |
679 | #define X86_64_16 (X86_64_0D + 1) | |
680 | #define X86_64_17 (X86_64_16 + 1) | |
681 | #define X86_64_1E (X86_64_17 + 1) | |
682 | #define X86_64_1F (X86_64_1E + 1) | |
683 | #define X86_64_27 (X86_64_1F + 1) | |
684 | #define X86_64_2F (X86_64_27 + 1) | |
685 | #define X86_64_37 (X86_64_2F + 1) | |
686 | #define X86_64_3F (X86_64_37 + 1) | |
687 | #define X86_64_60 (X86_64_3F + 1) | |
688 | #define X86_64_61 (X86_64_60 + 1) | |
689 | #define X86_64_62 (X86_64_61 + 1) | |
690 | #define X86_64_63 (X86_64_62 + 1) | |
691 | #define X86_64_6D (X86_64_63 + 1) | |
692 | #define X86_64_6F (X86_64_6D + 1) | |
693 | #define X86_64_9A (X86_64_6F + 1) | |
694 | #define X86_64_C4 (X86_64_9A + 1) | |
695 | #define X86_64_C5 (X86_64_C4 + 1) | |
696 | #define X86_64_CE (X86_64_C5 + 1) | |
697 | #define X86_64_D4 (X86_64_CE + 1) | |
698 | #define X86_64_D5 (X86_64_D4 + 1) | |
699 | #define X86_64_EA (X86_64_D5 + 1) | |
700 | #define X86_64_0F01_REG_0 (X86_64_EA + 1) | |
701 | #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1) | |
702 | #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1) | |
703 | #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1) | |
704 | ||
705 | #define THREE_BYTE_0F24 0 | |
706 | #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1) | |
707 | #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1) | |
708 | #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1) | |
709 | #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1) | |
89b66d55 | 710 | #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1) |
4e7d34a6 | 711 | |
26ca5450 | 712 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
713 | |
714 | struct dis386 { | |
2da11e11 | 715 | const char *name; |
ce518a5f L |
716 | struct |
717 | { | |
718 | op_rtn rtn; | |
719 | int bytemode; | |
720 | } op[MAX_OPERANDS]; | |
252b5132 RH |
721 | }; |
722 | ||
723 | /* Upper case letters in the instruction names here are macros. | |
724 | 'A' => print 'b' if no register operands or suffix_always is true | |
725 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 726 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 727 | size prefix |
ed7841b3 | 728 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 729 | suffix_always is true |
252b5132 | 730 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 731 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 732 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 733 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 734 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 735 | for some of the macro letters) |
9306ca4a | 736 | 'J' => print 'l' |
42903f7f | 737 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 738 | 'L' => print 'l' if suffix_always is true |
9d141669 | 739 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 740 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 741 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 742 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
743 | or suffix_always is true. print 'q' if rex prefix is present. |
744 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
745 | is true | |
a35ca55a | 746 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 747 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
748 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
749 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 750 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 751 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 752 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
753 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
754 | suffix_always is true. | |
6dd5059a | 755 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 756 | '!' => change condition from true to false or from false to true. |
98b528ac L |
757 | '%' => add 1 upper case letter to the macro. |
758 | ||
759 | 2 upper case letter macros: | |
760 | 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
761 | or suffix_always is true | |
52b15da3 | 762 | |
6439fc28 AM |
763 | Many of the above letters print nothing in Intel mode. See "putop" |
764 | for the details. | |
52b15da3 | 765 | |
6439fc28 | 766 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 767 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 768 | |
6439fc28 | 769 | static const struct dis386 dis386[] = { |
252b5132 | 770 | /* 00 */ |
ce518a5f L |
771 | { "addB", { Eb, Gb } }, |
772 | { "addS", { Ev, Gv } }, | |
773 | { "addB", { Gb, Eb } }, | |
774 | { "addS", { Gv, Ev } }, | |
775 | { "addB", { AL, Ib } }, | |
776 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
777 | { X86_64_TABLE (X86_64_06) }, |
778 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 779 | /* 08 */ |
ce518a5f L |
780 | { "orB", { Eb, Gb } }, |
781 | { "orS", { Ev, Gv } }, | |
782 | { "orB", { Gb, Eb } }, | |
783 | { "orS", { Gv, Ev } }, | |
784 | { "orB", { AL, Ib } }, | |
785 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 786 | { X86_64_TABLE (X86_64_0D) }, |
ce518a5f | 787 | { "(bad)", { XX } }, /* 0x0f extended opcode escape */ |
252b5132 | 788 | /* 10 */ |
ce518a5f L |
789 | { "adcB", { Eb, Gb } }, |
790 | { "adcS", { Ev, Gv } }, | |
791 | { "adcB", { Gb, Eb } }, | |
792 | { "adcS", { Gv, Ev } }, | |
793 | { "adcB", { AL, Ib } }, | |
794 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
795 | { X86_64_TABLE (X86_64_16) }, |
796 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 797 | /* 18 */ |
ce518a5f L |
798 | { "sbbB", { Eb, Gb } }, |
799 | { "sbbS", { Ev, Gv } }, | |
800 | { "sbbB", { Gb, Eb } }, | |
801 | { "sbbS", { Gv, Ev } }, | |
802 | { "sbbB", { AL, Ib } }, | |
803 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
804 | { X86_64_TABLE (X86_64_1E) }, |
805 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 806 | /* 20 */ |
ce518a5f L |
807 | { "andB", { Eb, Gb } }, |
808 | { "andS", { Ev, Gv } }, | |
809 | { "andB", { Gb, Eb } }, | |
810 | { "andS", { Gv, Ev } }, | |
811 | { "andB", { AL, Ib } }, | |
812 | { "andS", { eAX, Iv } }, | |
813 | { "(bad)", { XX } }, /* SEG ES prefix */ | |
4e7d34a6 | 814 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 815 | /* 28 */ |
ce518a5f L |
816 | { "subB", { Eb, Gb } }, |
817 | { "subS", { Ev, Gv } }, | |
818 | { "subB", { Gb, Eb } }, | |
819 | { "subS", { Gv, Ev } }, | |
820 | { "subB", { AL, Ib } }, | |
821 | { "subS", { eAX, Iv } }, | |
822 | { "(bad)", { XX } }, /* SEG CS prefix */ | |
4e7d34a6 | 823 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 824 | /* 30 */ |
ce518a5f L |
825 | { "xorB", { Eb, Gb } }, |
826 | { "xorS", { Ev, Gv } }, | |
827 | { "xorB", { Gb, Eb } }, | |
828 | { "xorS", { Gv, Ev } }, | |
829 | { "xorB", { AL, Ib } }, | |
830 | { "xorS", { eAX, Iv } }, | |
831 | { "(bad)", { XX } }, /* SEG SS prefix */ | |
4e7d34a6 | 832 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 833 | /* 38 */ |
ce518a5f L |
834 | { "cmpB", { Eb, Gb } }, |
835 | { "cmpS", { Ev, Gv } }, | |
836 | { "cmpB", { Gb, Eb } }, | |
837 | { "cmpS", { Gv, Ev } }, | |
838 | { "cmpB", { AL, Ib } }, | |
839 | { "cmpS", { eAX, Iv } }, | |
840 | { "(bad)", { XX } }, /* SEG DS prefix */ | |
4e7d34a6 | 841 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 842 | /* 40 */ |
ce518a5f L |
843 | { "inc{S|}", { RMeAX } }, |
844 | { "inc{S|}", { RMeCX } }, | |
845 | { "inc{S|}", { RMeDX } }, | |
846 | { "inc{S|}", { RMeBX } }, | |
847 | { "inc{S|}", { RMeSP } }, | |
848 | { "inc{S|}", { RMeBP } }, | |
849 | { "inc{S|}", { RMeSI } }, | |
850 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 851 | /* 48 */ |
ce518a5f L |
852 | { "dec{S|}", { RMeAX } }, |
853 | { "dec{S|}", { RMeCX } }, | |
854 | { "dec{S|}", { RMeDX } }, | |
855 | { "dec{S|}", { RMeBX } }, | |
856 | { "dec{S|}", { RMeSP } }, | |
857 | { "dec{S|}", { RMeBP } }, | |
858 | { "dec{S|}", { RMeSI } }, | |
859 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 860 | /* 50 */ |
ce518a5f L |
861 | { "pushV", { RMrAX } }, |
862 | { "pushV", { RMrCX } }, | |
863 | { "pushV", { RMrDX } }, | |
864 | { "pushV", { RMrBX } }, | |
865 | { "pushV", { RMrSP } }, | |
866 | { "pushV", { RMrBP } }, | |
867 | { "pushV", { RMrSI } }, | |
868 | { "pushV", { RMrDI } }, | |
252b5132 | 869 | /* 58 */ |
ce518a5f L |
870 | { "popV", { RMrAX } }, |
871 | { "popV", { RMrCX } }, | |
872 | { "popV", { RMrDX } }, | |
873 | { "popV", { RMrBX } }, | |
874 | { "popV", { RMrSP } }, | |
875 | { "popV", { RMrBP } }, | |
876 | { "popV", { RMrSI } }, | |
877 | { "popV", { RMrDI } }, | |
252b5132 | 878 | /* 60 */ |
4e7d34a6 L |
879 | { X86_64_TABLE (X86_64_60) }, |
880 | { X86_64_TABLE (X86_64_61) }, | |
881 | { X86_64_TABLE (X86_64_62) }, | |
882 | { X86_64_TABLE (X86_64_63) }, | |
ce518a5f L |
883 | { "(bad)", { XX } }, /* seg fs */ |
884 | { "(bad)", { XX } }, /* seg gs */ | |
885 | { "(bad)", { XX } }, /* op size prefix */ | |
886 | { "(bad)", { XX } }, /* adr size prefix */ | |
252b5132 | 887 | /* 68 */ |
ce518a5f L |
888 | { "pushT", { Iq } }, |
889 | { "imulS", { Gv, Ev, Iv } }, | |
890 | { "pushT", { sIb } }, | |
891 | { "imulS", { Gv, Ev, sIb } }, | |
7c52e0e8 | 892 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 893 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 894 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 895 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 896 | /* 70 */ |
ce518a5f L |
897 | { "joH", { Jb, XX, cond_jump_flag } }, |
898 | { "jnoH", { Jb, XX, cond_jump_flag } }, | |
899 | { "jbH", { Jb, XX, cond_jump_flag } }, | |
900 | { "jaeH", { Jb, XX, cond_jump_flag } }, | |
901 | { "jeH", { Jb, XX, cond_jump_flag } }, | |
902 | { "jneH", { Jb, XX, cond_jump_flag } }, | |
903 | { "jbeH", { Jb, XX, cond_jump_flag } }, | |
904 | { "jaH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 905 | /* 78 */ |
ce518a5f L |
906 | { "jsH", { Jb, XX, cond_jump_flag } }, |
907 | { "jnsH", { Jb, XX, cond_jump_flag } }, | |
908 | { "jpH", { Jb, XX, cond_jump_flag } }, | |
909 | { "jnpH", { Jb, XX, cond_jump_flag } }, | |
910 | { "jlH", { Jb, XX, cond_jump_flag } }, | |
911 | { "jgeH", { Jb, XX, cond_jump_flag } }, | |
912 | { "jleH", { Jb, XX, cond_jump_flag } }, | |
913 | { "jgH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 914 | /* 80 */ |
1ceb70f8 L |
915 | { REG_TABLE (REG_80) }, |
916 | { REG_TABLE (REG_81) }, | |
ce518a5f | 917 | { "(bad)", { XX } }, |
1ceb70f8 | 918 | { REG_TABLE (REG_82) }, |
ce518a5f L |
919 | { "testB", { Eb, Gb } }, |
920 | { "testS", { Ev, Gv } }, | |
921 | { "xchgB", { Eb, Gb } }, | |
922 | { "xchgS", { Ev, Gv } }, | |
252b5132 | 923 | /* 88 */ |
ce518a5f L |
924 | { "movB", { Eb, Gb } }, |
925 | { "movS", { Ev, Gv } }, | |
926 | { "movB", { Gb, Eb } }, | |
927 | { "movS", { Gv, Ev } }, | |
928 | { "movD", { Sv, Sw } }, | |
1ceb70f8 | 929 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 930 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 931 | { REG_TABLE (REG_8F) }, |
252b5132 | 932 | /* 90 */ |
1ceb70f8 | 933 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
934 | { "xchgS", { RMeCX, eAX } }, |
935 | { "xchgS", { RMeDX, eAX } }, | |
936 | { "xchgS", { RMeBX, eAX } }, | |
937 | { "xchgS", { RMeSP, eAX } }, | |
938 | { "xchgS", { RMeBP, eAX } }, | |
939 | { "xchgS", { RMeSI, eAX } }, | |
940 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 941 | /* 98 */ |
7c52e0e8 L |
942 | { "cW{t|}R", { XX } }, |
943 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 944 | { X86_64_TABLE (X86_64_9A) }, |
ce518a5f L |
945 | { "(bad)", { XX } }, /* fwait */ |
946 | { "pushfT", { XX } }, | |
947 | { "popfT", { XX } }, | |
7c52e0e8 L |
948 | { "sahf", { XX } }, |
949 | { "lahf", { XX } }, | |
252b5132 | 950 | /* a0 */ |
ce518a5f L |
951 | { "movB", { AL, Ob } }, |
952 | { "movS", { eAX, Ov } }, | |
953 | { "movB", { Ob, AL } }, | |
954 | { "movS", { Ov, eAX } }, | |
7c52e0e8 L |
955 | { "movs{b|}", { Ybr, Xb } }, |
956 | { "movs{R|}", { Yvr, Xv } }, | |
957 | { "cmps{b|}", { Xb, Yb } }, | |
958 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 959 | /* a8 */ |
ce518a5f L |
960 | { "testB", { AL, Ib } }, |
961 | { "testS", { eAX, Iv } }, | |
962 | { "stosB", { Ybr, AL } }, | |
963 | { "stosS", { Yvr, eAX } }, | |
964 | { "lodsB", { ALr, Xb } }, | |
965 | { "lodsS", { eAXr, Xv } }, | |
966 | { "scasB", { AL, Yb } }, | |
967 | { "scasS", { eAX, Yv } }, | |
252b5132 | 968 | /* b0 */ |
ce518a5f L |
969 | { "movB", { RMAL, Ib } }, |
970 | { "movB", { RMCL, Ib } }, | |
971 | { "movB", { RMDL, Ib } }, | |
972 | { "movB", { RMBL, Ib } }, | |
973 | { "movB", { RMAH, Ib } }, | |
974 | { "movB", { RMCH, Ib } }, | |
975 | { "movB", { RMDH, Ib } }, | |
976 | { "movB", { RMBH, Ib } }, | |
252b5132 | 977 | /* b8 */ |
ce518a5f L |
978 | { "movS", { RMeAX, Iv64 } }, |
979 | { "movS", { RMeCX, Iv64 } }, | |
980 | { "movS", { RMeDX, Iv64 } }, | |
981 | { "movS", { RMeBX, Iv64 } }, | |
982 | { "movS", { RMeSP, Iv64 } }, | |
983 | { "movS", { RMeBP, Iv64 } }, | |
984 | { "movS", { RMeSI, Iv64 } }, | |
985 | { "movS", { RMeDI, Iv64 } }, | |
252b5132 | 986 | /* c0 */ |
1ceb70f8 L |
987 | { REG_TABLE (REG_C0) }, |
988 | { REG_TABLE (REG_C1) }, | |
ce518a5f L |
989 | { "retT", { Iw } }, |
990 | { "retT", { XX } }, | |
4e7d34a6 L |
991 | { X86_64_TABLE (X86_64_C4) }, |
992 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
993 | { REG_TABLE (REG_C6) }, |
994 | { REG_TABLE (REG_C7) }, | |
252b5132 | 995 | /* c8 */ |
ce518a5f L |
996 | { "enterT", { Iw, Ib } }, |
997 | { "leaveT", { XX } }, | |
998 | { "lretP", { Iw } }, | |
999 | { "lretP", { XX } }, | |
1000 | { "int3", { XX } }, | |
1001 | { "int", { Ib } }, | |
4e7d34a6 | 1002 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1003 | { "iretP", { XX } }, |
252b5132 | 1004 | /* d0 */ |
1ceb70f8 L |
1005 | { REG_TABLE (REG_D0) }, |
1006 | { REG_TABLE (REG_D1) }, | |
1007 | { REG_TABLE (REG_D2) }, | |
1008 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1009 | { X86_64_TABLE (X86_64_D4) }, |
1010 | { X86_64_TABLE (X86_64_D5) }, | |
ce518a5f L |
1011 | { "(bad)", { XX } }, |
1012 | { "xlat", { DSBX } }, | |
252b5132 RH |
1013 | /* d8 */ |
1014 | { FLOAT }, | |
1015 | { FLOAT }, | |
1016 | { FLOAT }, | |
1017 | { FLOAT }, | |
1018 | { FLOAT }, | |
1019 | { FLOAT }, | |
1020 | { FLOAT }, | |
1021 | { FLOAT }, | |
1022 | /* e0 */ | |
ce518a5f L |
1023 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1024 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1025 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1026 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1027 | { "inB", { AL, Ib } }, | |
1028 | { "inG", { zAX, Ib } }, | |
1029 | { "outB", { Ib, AL } }, | |
1030 | { "outG", { Ib, zAX } }, | |
252b5132 | 1031 | /* e8 */ |
ce518a5f L |
1032 | { "callT", { Jv } }, |
1033 | { "jmpT", { Jv } }, | |
4e7d34a6 | 1034 | { X86_64_TABLE (X86_64_EA) }, |
ce518a5f L |
1035 | { "jmp", { Jb } }, |
1036 | { "inB", { AL, indirDX } }, | |
1037 | { "inG", { zAX, indirDX } }, | |
1038 | { "outB", { indirDX, AL } }, | |
1039 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1040 | /* f0 */ |
ce518a5f L |
1041 | { "(bad)", { XX } }, /* lock prefix */ |
1042 | { "icebp", { XX } }, | |
1043 | { "(bad)", { XX } }, /* repne */ | |
1044 | { "(bad)", { XX } }, /* repz */ | |
1045 | { "hlt", { XX } }, | |
1046 | { "cmc", { XX } }, | |
1ceb70f8 L |
1047 | { REG_TABLE (REG_F6) }, |
1048 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1049 | /* f8 */ |
ce518a5f L |
1050 | { "clc", { XX } }, |
1051 | { "stc", { XX } }, | |
1052 | { "cli", { XX } }, | |
1053 | { "sti", { XX } }, | |
1054 | { "cld", { XX } }, | |
1055 | { "std", { XX } }, | |
1ceb70f8 L |
1056 | { REG_TABLE (REG_FE) }, |
1057 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1058 | }; |
1059 | ||
6439fc28 | 1060 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1061 | /* 00 */ |
1ceb70f8 L |
1062 | { REG_TABLE (REG_0F00 ) }, |
1063 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1064 | { "larS", { Gv, Ew } }, |
1065 | { "lslS", { Gv, Ew } }, | |
1066 | { "(bad)", { XX } }, | |
1067 | { "syscall", { XX } }, | |
1068 | { "clts", { XX } }, | |
1069 | { "sysretP", { XX } }, | |
252b5132 | 1070 | /* 08 */ |
ce518a5f L |
1071 | { "invd", { XX } }, |
1072 | { "wbinvd", { XX } }, | |
1073 | { "(bad)", { XX } }, | |
1074 | { "ud2a", { XX } }, | |
1075 | { "(bad)", { XX } }, | |
b5b1fc4f | 1076 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1077 | { "femms", { XX } }, |
1078 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1079 | /* 10 */ |
1ceb70f8 L |
1080 | { PREFIX_TABLE (PREFIX_0F10) }, |
1081 | { PREFIX_TABLE (PREFIX_0F11) }, | |
1082 | { PREFIX_TABLE (PREFIX_0F12) }, | |
1083 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
1084 | { "unpcklpX", { XM, EXx } }, |
1085 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
1086 | { PREFIX_TABLE (PREFIX_0F16) }, |
1087 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 1088 | /* 18 */ |
1ceb70f8 | 1089 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f L |
1090 | { "nopQ", { Ev } }, |
1091 | { "nopQ", { Ev } }, | |
1092 | { "nopQ", { Ev } }, | |
1093 | { "nopQ", { Ev } }, | |
1094 | { "nopQ", { Ev } }, | |
1095 | { "nopQ", { Ev } }, | |
ce518a5f | 1096 | { "nopQ", { Ev } }, |
252b5132 | 1097 | /* 20 */ |
1ceb70f8 L |
1098 | { MOD_TABLE (MOD_0F20) }, |
1099 | { MOD_TABLE (MOD_0F21) }, | |
1100 | { MOD_TABLE (MOD_0F22) }, | |
1101 | { MOD_TABLE (MOD_0F23) }, | |
1102 | { MOD_TABLE (MOD_0F24) }, | |
4e7d34a6 | 1103 | { THREE_BYTE_TABLE (THREE_BYTE_0F25) }, |
1ceb70f8 | 1104 | { MOD_TABLE (MOD_0F26) }, |
ce518a5f | 1105 | { "(bad)", { XX } }, |
252b5132 | 1106 | /* 28 */ |
09a2c6cf | 1107 | { "movapX", { XM, EXx } }, |
d5d7db8e | 1108 | { "movapX", { EXx, XM } }, |
1ceb70f8 L |
1109 | { PREFIX_TABLE (PREFIX_0F2A) }, |
1110 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
1111 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
1112 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
1113 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
1114 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 1115 | /* 30 */ |
ce518a5f L |
1116 | { "wrmsr", { XX } }, |
1117 | { "rdtsc", { XX } }, | |
1118 | { "rdmsr", { XX } }, | |
1119 | { "rdpmc", { XX } }, | |
1120 | { "sysenter", { XX } }, | |
1121 | { "sysexit", { XX } }, | |
1122 | { "(bad)", { XX } }, | |
47dd174c | 1123 | { "getsec", { XX } }, |
252b5132 | 1124 | /* 38 */ |
4e7d34a6 | 1125 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
ce518a5f | 1126 | { "(bad)", { XX } }, |
4e7d34a6 | 1127 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
ce518a5f L |
1128 | { "(bad)", { XX } }, |
1129 | { "(bad)", { XX } }, | |
1130 | { "(bad)", { XX } }, | |
1131 | { "(bad)", { XX } }, | |
1132 | { "(bad)", { XX } }, | |
252b5132 | 1133 | /* 40 */ |
ce518a5f L |
1134 | { "cmovo", { Gv, Ev } }, |
1135 | { "cmovno", { Gv, Ev } }, | |
1136 | { "cmovb", { Gv, Ev } }, | |
1137 | { "cmovae", { Gv, Ev } }, | |
1138 | { "cmove", { Gv, Ev } }, | |
1139 | { "cmovne", { Gv, Ev } }, | |
1140 | { "cmovbe", { Gv, Ev } }, | |
1141 | { "cmova", { Gv, Ev } }, | |
252b5132 | 1142 | /* 48 */ |
ce518a5f L |
1143 | { "cmovs", { Gv, Ev } }, |
1144 | { "cmovns", { Gv, Ev } }, | |
1145 | { "cmovp", { Gv, Ev } }, | |
1146 | { "cmovnp", { Gv, Ev } }, | |
1147 | { "cmovl", { Gv, Ev } }, | |
1148 | { "cmovge", { Gv, Ev } }, | |
1149 | { "cmovle", { Gv, Ev } }, | |
1150 | { "cmovg", { Gv, Ev } }, | |
252b5132 | 1151 | /* 50 */ |
75c135a8 | 1152 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
1153 | { PREFIX_TABLE (PREFIX_0F51) }, |
1154 | { PREFIX_TABLE (PREFIX_0F52) }, | |
1155 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
1156 | { "andpX", { XM, EXx } }, |
1157 | { "andnpX", { XM, EXx } }, | |
1158 | { "orpX", { XM, EXx } }, | |
1159 | { "xorpX", { XM, EXx } }, | |
252b5132 | 1160 | /* 58 */ |
1ceb70f8 L |
1161 | { PREFIX_TABLE (PREFIX_0F58) }, |
1162 | { PREFIX_TABLE (PREFIX_0F59) }, | |
1163 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
1164 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
1165 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
1166 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
1167 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
1168 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 1169 | /* 60 */ |
1ceb70f8 L |
1170 | { PREFIX_TABLE (PREFIX_0F60) }, |
1171 | { PREFIX_TABLE (PREFIX_0F61) }, | |
1172 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
1173 | { "packsswb", { MX, EM } }, |
1174 | { "pcmpgtb", { MX, EM } }, | |
1175 | { "pcmpgtw", { MX, EM } }, | |
1176 | { "pcmpgtd", { MX, EM } }, | |
1177 | { "packuswb", { MX, EM } }, | |
252b5132 | 1178 | /* 68 */ |
ce518a5f L |
1179 | { "punpckhbw", { MX, EM } }, |
1180 | { "punpckhwd", { MX, EM } }, | |
1181 | { "punpckhdq", { MX, EM } }, | |
1182 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
1183 | { PREFIX_TABLE (PREFIX_0F6C) }, |
1184 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 1185 | { "movK", { MX, Edq } }, |
1ceb70f8 | 1186 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 1187 | /* 70 */ |
1ceb70f8 L |
1188 | { PREFIX_TABLE (PREFIX_0F70) }, |
1189 | { REG_TABLE (REG_0F71) }, | |
1190 | { REG_TABLE (REG_0F72) }, | |
1191 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
1192 | { "pcmpeqb", { MX, EM } }, |
1193 | { "pcmpeqw", { MX, EM } }, | |
1194 | { "pcmpeqd", { MX, EM } }, | |
1195 | { "emms", { XX } }, | |
252b5132 | 1196 | /* 78 */ |
1ceb70f8 L |
1197 | { PREFIX_TABLE (PREFIX_0F78) }, |
1198 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 1199 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
89b66d55 | 1200 | { THREE_BYTE_TABLE (THREE_BYTE_0F7B) }, |
1ceb70f8 L |
1201 | { PREFIX_TABLE (PREFIX_0F7C) }, |
1202 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
1203 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
1204 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 1205 | /* 80 */ |
ce518a5f L |
1206 | { "joH", { Jv, XX, cond_jump_flag } }, |
1207 | { "jnoH", { Jv, XX, cond_jump_flag } }, | |
1208 | { "jbH", { Jv, XX, cond_jump_flag } }, | |
1209 | { "jaeH", { Jv, XX, cond_jump_flag } }, | |
1210 | { "jeH", { Jv, XX, cond_jump_flag } }, | |
1211 | { "jneH", { Jv, XX, cond_jump_flag } }, | |
1212 | { "jbeH", { Jv, XX, cond_jump_flag } }, | |
1213 | { "jaH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1214 | /* 88 */ |
ce518a5f L |
1215 | { "jsH", { Jv, XX, cond_jump_flag } }, |
1216 | { "jnsH", { Jv, XX, cond_jump_flag } }, | |
1217 | { "jpH", { Jv, XX, cond_jump_flag } }, | |
1218 | { "jnpH", { Jv, XX, cond_jump_flag } }, | |
1219 | { "jlH", { Jv, XX, cond_jump_flag } }, | |
1220 | { "jgeH", { Jv, XX, cond_jump_flag } }, | |
1221 | { "jleH", { Jv, XX, cond_jump_flag } }, | |
1222 | { "jgH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1223 | /* 90 */ |
ce518a5f L |
1224 | { "seto", { Eb } }, |
1225 | { "setno", { Eb } }, | |
1226 | { "setb", { Eb } }, | |
1227 | { "setae", { Eb } }, | |
1228 | { "sete", { Eb } }, | |
1229 | { "setne", { Eb } }, | |
1230 | { "setbe", { Eb } }, | |
1231 | { "seta", { Eb } }, | |
252b5132 | 1232 | /* 98 */ |
ce518a5f L |
1233 | { "sets", { Eb } }, |
1234 | { "setns", { Eb } }, | |
1235 | { "setp", { Eb } }, | |
1236 | { "setnp", { Eb } }, | |
1237 | { "setl", { Eb } }, | |
1238 | { "setge", { Eb } }, | |
1239 | { "setle", { Eb } }, | |
1240 | { "setg", { Eb } }, | |
252b5132 | 1241 | /* a0 */ |
ce518a5f L |
1242 | { "pushT", { fs } }, |
1243 | { "popT", { fs } }, | |
1244 | { "cpuid", { XX } }, | |
1245 | { "btS", { Ev, Gv } }, | |
1246 | { "shldS", { Ev, Gv, Ib } }, | |
1247 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
1248 | { REG_TABLE (REG_0FA6) }, |
1249 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 1250 | /* a8 */ |
ce518a5f L |
1251 | { "pushT", { gs } }, |
1252 | { "popT", { gs } }, | |
1253 | { "rsm", { XX } }, | |
1254 | { "btsS", { Ev, Gv } }, | |
1255 | { "shrdS", { Ev, Gv, Ib } }, | |
1256 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 1257 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 1258 | { "imulS", { Gv, Ev } }, |
252b5132 | 1259 | /* b0 */ |
ce518a5f L |
1260 | { "cmpxchgB", { Eb, Gb } }, |
1261 | { "cmpxchgS", { Ev, Gv } }, | |
1ceb70f8 | 1262 | { MOD_TABLE (MOD_0FB2) }, |
ce518a5f | 1263 | { "btrS", { Ev, Gv } }, |
1ceb70f8 L |
1264 | { MOD_TABLE (MOD_0FB4) }, |
1265 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
1266 | { "movz{bR|x}", { Gv, Eb } }, |
1267 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 1268 | /* b8 */ |
1ceb70f8 | 1269 | { PREFIX_TABLE (PREFIX_0FB8) }, |
ce518a5f | 1270 | { "ud2b", { XX } }, |
1ceb70f8 | 1271 | { REG_TABLE (REG_0FBA) }, |
ce518a5f L |
1272 | { "btcS", { Ev, Gv } }, |
1273 | { "bsfS", { Gv, Ev } }, | |
1ceb70f8 | 1274 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
1275 | { "movs{bR|x}", { Gv, Eb } }, |
1276 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 1277 | /* c0 */ |
ce518a5f L |
1278 | { "xaddB", { Eb, Gb } }, |
1279 | { "xaddS", { Ev, Gv } }, | |
1ceb70f8 | 1280 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 1281 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
1282 | { "pinsrw", { MX, Edqw, Ib } }, |
1283 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 1284 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 1285 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 1286 | /* c8 */ |
ce518a5f L |
1287 | { "bswap", { RMeAX } }, |
1288 | { "bswap", { RMeCX } }, | |
1289 | { "bswap", { RMeDX } }, | |
1290 | { "bswap", { RMeBX } }, | |
1291 | { "bswap", { RMeSP } }, | |
1292 | { "bswap", { RMeBP } }, | |
1293 | { "bswap", { RMeSI } }, | |
1294 | { "bswap", { RMeDI } }, | |
252b5132 | 1295 | /* d0 */ |
1ceb70f8 | 1296 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
1297 | { "psrlw", { MX, EM } }, |
1298 | { "psrld", { MX, EM } }, | |
1299 | { "psrlq", { MX, EM } }, | |
1300 | { "paddq", { MX, EM } }, | |
1301 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 1302 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 1303 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 1304 | /* d8 */ |
ce518a5f L |
1305 | { "psubusb", { MX, EM } }, |
1306 | { "psubusw", { MX, EM } }, | |
1307 | { "pminub", { MX, EM } }, | |
1308 | { "pand", { MX, EM } }, | |
1309 | { "paddusb", { MX, EM } }, | |
1310 | { "paddusw", { MX, EM } }, | |
1311 | { "pmaxub", { MX, EM } }, | |
1312 | { "pandn", { MX, EM } }, | |
252b5132 | 1313 | /* e0 */ |
ce518a5f L |
1314 | { "pavgb", { MX, EM } }, |
1315 | { "psraw", { MX, EM } }, | |
1316 | { "psrad", { MX, EM } }, | |
1317 | { "pavgw", { MX, EM } }, | |
1318 | { "pmulhuw", { MX, EM } }, | |
1319 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
1320 | { PREFIX_TABLE (PREFIX_0FE6) }, |
1321 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 1322 | /* e8 */ |
ce518a5f L |
1323 | { "psubsb", { MX, EM } }, |
1324 | { "psubsw", { MX, EM } }, | |
1325 | { "pminsw", { MX, EM } }, | |
1326 | { "por", { MX, EM } }, | |
1327 | { "paddsb", { MX, EM } }, | |
1328 | { "paddsw", { MX, EM } }, | |
1329 | { "pmaxsw", { MX, EM } }, | |
1330 | { "pxor", { MX, EM } }, | |
252b5132 | 1331 | /* f0 */ |
1ceb70f8 | 1332 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
1333 | { "psllw", { MX, EM } }, |
1334 | { "pslld", { MX, EM } }, | |
1335 | { "psllq", { MX, EM } }, | |
1336 | { "pmuludq", { MX, EM } }, | |
1337 | { "pmaddwd", { MX, EM } }, | |
1338 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 1339 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 1340 | /* f8 */ |
ce518a5f L |
1341 | { "psubb", { MX, EM } }, |
1342 | { "psubw", { MX, EM } }, | |
1343 | { "psubd", { MX, EM } }, | |
1344 | { "psubq", { MX, EM } }, | |
1345 | { "paddb", { MX, EM } }, | |
1346 | { "paddw", { MX, EM } }, | |
1347 | { "paddd", { MX, EM } }, | |
1348 | { "(bad)", { XX } }, | |
252b5132 RH |
1349 | }; |
1350 | ||
1351 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
1352 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1353 | /* ------------------------------- */ | |
1354 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
1355 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
1356 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
1357 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
1358 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
1359 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
1360 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
1361 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
1362 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
1363 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
1364 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
1365 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
1366 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
1367 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
1368 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
1369 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
1370 | /* ------------------------------- */ | |
1371 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
1372 | }; |
1373 | ||
1374 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
1375 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1376 | /* ------------------------------- */ | |
252b5132 | 1377 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 1378 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 1379 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 1380 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 1381 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
1382 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
1383 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 1384 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
1385 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
1386 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 1387 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 1388 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 1389 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 1390 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 1391 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 1392 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
1393 | /* ------------------------------- */ |
1394 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1395 | }; | |
1396 | ||
252b5132 RH |
1397 | static char obuf[100]; |
1398 | static char *obufp; | |
1399 | static char scratchbuf[100]; | |
1400 | static unsigned char *start_codep; | |
1401 | static unsigned char *insn_codep; | |
1402 | static unsigned char *codep; | |
b844680a L |
1403 | static const char *lock_prefix; |
1404 | static const char *data_prefix; | |
1405 | static const char *addr_prefix; | |
1406 | static const char *repz_prefix; | |
1407 | static const char *repnz_prefix; | |
252b5132 | 1408 | static disassemble_info *the_info; |
7967e09e L |
1409 | static struct |
1410 | { | |
1411 | int mod; | |
7967e09e | 1412 | int reg; |
484c222e | 1413 | int rm; |
7967e09e L |
1414 | } |
1415 | modrm; | |
4bba6815 | 1416 | static unsigned char need_modrm; |
252b5132 | 1417 | |
4bba6815 AM |
1418 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
1419 | values are stale. Hitting this abort likely indicates that you | |
1420 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
1421 | #define MODRM_CHECK if (!need_modrm) abort () | |
1422 | ||
d708bcba AM |
1423 | static const char **names64; |
1424 | static const char **names32; | |
1425 | static const char **names16; | |
1426 | static const char **names8; | |
1427 | static const char **names8rex; | |
1428 | static const char **names_seg; | |
db51cc60 L |
1429 | static const char *index64; |
1430 | static const char *index32; | |
d708bcba AM |
1431 | static const char **index16; |
1432 | ||
1433 | static const char *intel_names64[] = { | |
1434 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
1435 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
1436 | }; | |
1437 | static const char *intel_names32[] = { | |
1438 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
1439 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
1440 | }; | |
1441 | static const char *intel_names16[] = { | |
1442 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
1443 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
1444 | }; | |
1445 | static const char *intel_names8[] = { | |
1446 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
1447 | }; | |
1448 | static const char *intel_names8rex[] = { | |
1449 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
1450 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
1451 | }; | |
1452 | static const char *intel_names_seg[] = { | |
1453 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
1454 | }; | |
db51cc60 L |
1455 | static const char *intel_index64 = "riz"; |
1456 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
1457 | static const char *intel_index16[] = { |
1458 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
1459 | }; | |
1460 | ||
1461 | static const char *att_names64[] = { | |
1462 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
1463 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
1464 | }; | |
d708bcba AM |
1465 | static const char *att_names32[] = { |
1466 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 1467 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 1468 | }; |
d708bcba AM |
1469 | static const char *att_names16[] = { |
1470 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 1471 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 1472 | }; |
d708bcba AM |
1473 | static const char *att_names8[] = { |
1474 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 1475 | }; |
d708bcba AM |
1476 | static const char *att_names8rex[] = { |
1477 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
1478 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
1479 | }; | |
d708bcba AM |
1480 | static const char *att_names_seg[] = { |
1481 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 1482 | }; |
db51cc60 L |
1483 | static const char *att_index64 = "%riz"; |
1484 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
1485 | static const char *att_index16[] = { |
1486 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
1487 | }; |
1488 | ||
1ceb70f8 L |
1489 | static const struct dis386 reg_table[][8] = { |
1490 | /* REG_80 */ | |
252b5132 | 1491 | { |
ce518a5f L |
1492 | { "addA", { Eb, Ib } }, |
1493 | { "orA", { Eb, Ib } }, | |
1494 | { "adcA", { Eb, Ib } }, | |
1495 | { "sbbA", { Eb, Ib } }, | |
1496 | { "andA", { Eb, Ib } }, | |
1497 | { "subA", { Eb, Ib } }, | |
1498 | { "xorA", { Eb, Ib } }, | |
1499 | { "cmpA", { Eb, Ib } }, | |
252b5132 | 1500 | }, |
1ceb70f8 | 1501 | /* REG_81 */ |
252b5132 | 1502 | { |
ce518a5f L |
1503 | { "addQ", { Ev, Iv } }, |
1504 | { "orQ", { Ev, Iv } }, | |
1505 | { "adcQ", { Ev, Iv } }, | |
1506 | { "sbbQ", { Ev, Iv } }, | |
1507 | { "andQ", { Ev, Iv } }, | |
1508 | { "subQ", { Ev, Iv } }, | |
1509 | { "xorQ", { Ev, Iv } }, | |
1510 | { "cmpQ", { Ev, Iv } }, | |
252b5132 | 1511 | }, |
1ceb70f8 | 1512 | /* REG_82 */ |
252b5132 | 1513 | { |
ce518a5f L |
1514 | { "addQ", { Ev, sIb } }, |
1515 | { "orQ", { Ev, sIb } }, | |
1516 | { "adcQ", { Ev, sIb } }, | |
1517 | { "sbbQ", { Ev, sIb } }, | |
1518 | { "andQ", { Ev, sIb } }, | |
1519 | { "subQ", { Ev, sIb } }, | |
1520 | { "xorQ", { Ev, sIb } }, | |
1521 | { "cmpQ", { Ev, sIb } }, | |
252b5132 | 1522 | }, |
1ceb70f8 | 1523 | /* REG_8F */ |
4e7d34a6 L |
1524 | { |
1525 | { "popU", { stackEv } }, | |
1526 | { "(bad)", { XX } }, | |
1527 | { "(bad)", { XX } }, | |
1528 | { "(bad)", { XX } }, | |
1529 | { "(bad)", { XX } }, | |
1530 | { "(bad)", { XX } }, | |
1531 | { "(bad)", { XX } }, | |
1532 | { "(bad)", { XX } }, | |
1533 | }, | |
1ceb70f8 | 1534 | /* REG_C0 */ |
252b5132 | 1535 | { |
ce518a5f L |
1536 | { "rolA", { Eb, Ib } }, |
1537 | { "rorA", { Eb, Ib } }, | |
1538 | { "rclA", { Eb, Ib } }, | |
1539 | { "rcrA", { Eb, Ib } }, | |
1540 | { "shlA", { Eb, Ib } }, | |
1541 | { "shrA", { Eb, Ib } }, | |
1542 | { "(bad)", { XX } }, | |
1543 | { "sarA", { Eb, Ib } }, | |
252b5132 | 1544 | }, |
1ceb70f8 | 1545 | /* REG_C1 */ |
252b5132 | 1546 | { |
ce518a5f L |
1547 | { "rolQ", { Ev, Ib } }, |
1548 | { "rorQ", { Ev, Ib } }, | |
1549 | { "rclQ", { Ev, Ib } }, | |
1550 | { "rcrQ", { Ev, Ib } }, | |
1551 | { "shlQ", { Ev, Ib } }, | |
1552 | { "shrQ", { Ev, Ib } }, | |
1553 | { "(bad)", { XX } }, | |
1554 | { "sarQ", { Ev, Ib } }, | |
252b5132 | 1555 | }, |
1ceb70f8 | 1556 | /* REG_C6 */ |
4e7d34a6 L |
1557 | { |
1558 | { "movA", { Eb, Ib } }, | |
1559 | { "(bad)", { XX } }, | |
1560 | { "(bad)", { XX } }, | |
1561 | { "(bad)", { XX } }, | |
1562 | { "(bad)", { XX } }, | |
1563 | { "(bad)", { XX } }, | |
1564 | { "(bad)", { XX } }, | |
1565 | { "(bad)", { XX } }, | |
1566 | }, | |
1ceb70f8 | 1567 | /* REG_C7 */ |
4e7d34a6 L |
1568 | { |
1569 | { "movQ", { Ev, Iv } }, | |
1570 | { "(bad)", { XX } }, | |
1571 | { "(bad)", { XX } }, | |
1572 | { "(bad)", { XX } }, | |
1573 | { "(bad)", { XX } }, | |
1574 | { "(bad)", { XX } }, | |
1575 | { "(bad)", { XX } }, | |
1576 | { "(bad)", { XX } }, | |
1577 | }, | |
1ceb70f8 | 1578 | /* REG_D0 */ |
252b5132 | 1579 | { |
ce518a5f L |
1580 | { "rolA", { Eb, I1 } }, |
1581 | { "rorA", { Eb, I1 } }, | |
1582 | { "rclA", { Eb, I1 } }, | |
1583 | { "rcrA", { Eb, I1 } }, | |
1584 | { "shlA", { Eb, I1 } }, | |
1585 | { "shrA", { Eb, I1 } }, | |
1586 | { "(bad)", { XX } }, | |
1587 | { "sarA", { Eb, I1 } }, | |
252b5132 | 1588 | }, |
1ceb70f8 | 1589 | /* REG_D1 */ |
252b5132 | 1590 | { |
ce518a5f L |
1591 | { "rolQ", { Ev, I1 } }, |
1592 | { "rorQ", { Ev, I1 } }, | |
1593 | { "rclQ", { Ev, I1 } }, | |
1594 | { "rcrQ", { Ev, I1 } }, | |
1595 | { "shlQ", { Ev, I1 } }, | |
1596 | { "shrQ", { Ev, I1 } }, | |
1597 | { "(bad)", { XX } }, | |
1598 | { "sarQ", { Ev, I1 } }, | |
252b5132 | 1599 | }, |
1ceb70f8 | 1600 | /* REG_D2 */ |
252b5132 | 1601 | { |
ce518a5f L |
1602 | { "rolA", { Eb, CL } }, |
1603 | { "rorA", { Eb, CL } }, | |
1604 | { "rclA", { Eb, CL } }, | |
1605 | { "rcrA", { Eb, CL } }, | |
1606 | { "shlA", { Eb, CL } }, | |
1607 | { "shrA", { Eb, CL } }, | |
1608 | { "(bad)", { XX } }, | |
1609 | { "sarA", { Eb, CL } }, | |
252b5132 | 1610 | }, |
1ceb70f8 | 1611 | /* REG_D3 */ |
252b5132 | 1612 | { |
ce518a5f L |
1613 | { "rolQ", { Ev, CL } }, |
1614 | { "rorQ", { Ev, CL } }, | |
1615 | { "rclQ", { Ev, CL } }, | |
1616 | { "rcrQ", { Ev, CL } }, | |
1617 | { "shlQ", { Ev, CL } }, | |
1618 | { "shrQ", { Ev, CL } }, | |
1619 | { "(bad)", { XX } }, | |
1620 | { "sarQ", { Ev, CL } }, | |
252b5132 | 1621 | }, |
1ceb70f8 | 1622 | /* REG_F6 */ |
252b5132 | 1623 | { |
ce518a5f | 1624 | { "testA", { Eb, Ib } }, |
058f233b | 1625 | { "(bad)", { XX } }, |
ce518a5f L |
1626 | { "notA", { Eb } }, |
1627 | { "negA", { Eb } }, | |
1628 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ | |
1629 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
1630 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
1631 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 1632 | }, |
1ceb70f8 | 1633 | /* REG_F7 */ |
252b5132 | 1634 | { |
ce518a5f L |
1635 | { "testQ", { Ev, Iv } }, |
1636 | { "(bad)", { XX } }, | |
1637 | { "notQ", { Ev } }, | |
1638 | { "negQ", { Ev } }, | |
1639 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ | |
1640 | { "imulQ", { Ev } }, | |
1641 | { "divQ", { Ev } }, | |
1642 | { "idivQ", { Ev } }, | |
252b5132 | 1643 | }, |
1ceb70f8 | 1644 | /* REG_FE */ |
252b5132 | 1645 | { |
ce518a5f L |
1646 | { "incA", { Eb } }, |
1647 | { "decA", { Eb } }, | |
1648 | { "(bad)", { XX } }, | |
1649 | { "(bad)", { XX } }, | |
1650 | { "(bad)", { XX } }, | |
1651 | { "(bad)", { XX } }, | |
1652 | { "(bad)", { XX } }, | |
1653 | { "(bad)", { XX } }, | |
252b5132 | 1654 | }, |
1ceb70f8 | 1655 | /* REG_FF */ |
252b5132 | 1656 | { |
ce518a5f L |
1657 | { "incQ", { Ev } }, |
1658 | { "decQ", { Ev } }, | |
1659 | { "callT", { indirEv } }, | |
1660 | { "JcallT", { indirEp } }, | |
1661 | { "jmpT", { indirEv } }, | |
1662 | { "JjmpT", { indirEp } }, | |
1663 | { "pushU", { stackEv } }, | |
1664 | { "(bad)", { XX } }, | |
252b5132 | 1665 | }, |
1ceb70f8 | 1666 | /* REG_0F00 */ |
252b5132 | 1667 | { |
ce518a5f L |
1668 | { "sldtD", { Sv } }, |
1669 | { "strD", { Sv } }, | |
1670 | { "lldt", { Ew } }, | |
1671 | { "ltr", { Ew } }, | |
1672 | { "verr", { Ew } }, | |
1673 | { "verw", { Ew } }, | |
1674 | { "(bad)", { XX } }, | |
1675 | { "(bad)", { XX } }, | |
252b5132 | 1676 | }, |
1ceb70f8 | 1677 | /* REG_0F01 */ |
252b5132 | 1678 | { |
1ceb70f8 L |
1679 | { MOD_TABLE (MOD_0F01_REG_0) }, |
1680 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
1681 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
1682 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f L |
1683 | { "smswD", { Sv } }, |
1684 | { "(bad)", { XX } }, | |
1685 | { "lmsw", { Ew } }, | |
1ceb70f8 | 1686 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 1687 | }, |
b5b1fc4f | 1688 | /* REG_0F0D */ |
252b5132 | 1689 | { |
4e7d34a6 L |
1690 | { "prefetch", { Eb } }, |
1691 | { "prefetchw", { Eb } }, | |
1692 | { "(bad)", { XX } }, | |
1693 | { "(bad)", { XX } }, | |
1694 | { "(bad)", { XX } }, | |
1695 | { "(bad)", { XX } }, | |
1696 | { "(bad)", { XX } }, | |
1697 | { "(bad)", { XX } }, | |
252b5132 | 1698 | }, |
1ceb70f8 | 1699 | /* REG_0F18 */ |
252b5132 | 1700 | { |
1ceb70f8 L |
1701 | { MOD_TABLE (MOD_0F18_REG_0) }, |
1702 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
1703 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
1704 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
ce518a5f L |
1705 | { "(bad)", { XX } }, |
1706 | { "(bad)", { XX } }, | |
1707 | { "(bad)", { XX } }, | |
1708 | { "(bad)", { XX } }, | |
252b5132 | 1709 | }, |
1ceb70f8 | 1710 | /* REG_0F71 */ |
a6bd098c | 1711 | { |
ce518a5f L |
1712 | { "(bad)", { XX } }, |
1713 | { "(bad)", { XX } }, | |
1ceb70f8 | 1714 | { MOD_TABLE (MOD_0F71_REG_2) }, |
ce518a5f | 1715 | { "(bad)", { XX } }, |
1ceb70f8 | 1716 | { MOD_TABLE (MOD_0F71_REG_4) }, |
ce518a5f | 1717 | { "(bad)", { XX } }, |
1ceb70f8 | 1718 | { MOD_TABLE (MOD_0F71_REG_6) }, |
ce518a5f | 1719 | { "(bad)", { XX } }, |
a6bd098c | 1720 | }, |
1ceb70f8 | 1721 | /* REG_0F72 */ |
a6bd098c | 1722 | { |
ce518a5f L |
1723 | { "(bad)", { XX } }, |
1724 | { "(bad)", { XX } }, | |
1ceb70f8 | 1725 | { MOD_TABLE (MOD_0F72_REG_2) }, |
ce518a5f | 1726 | { "(bad)", { XX } }, |
1ceb70f8 | 1727 | { MOD_TABLE (MOD_0F72_REG_4) }, |
ce518a5f | 1728 | { "(bad)", { XX } }, |
1ceb70f8 | 1729 | { MOD_TABLE (MOD_0F72_REG_6) }, |
ce518a5f | 1730 | { "(bad)", { XX } }, |
a6bd098c | 1731 | }, |
1ceb70f8 | 1732 | /* REG_0F73 */ |
252b5132 | 1733 | { |
ce518a5f L |
1734 | { "(bad)", { XX } }, |
1735 | { "(bad)", { XX } }, | |
1ceb70f8 L |
1736 | { MOD_TABLE (MOD_0F73_REG_2) }, |
1737 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
ce518a5f | 1738 | { "(bad)", { XX } }, |
ce518a5f | 1739 | { "(bad)", { XX } }, |
1ceb70f8 L |
1740 | { MOD_TABLE (MOD_0F73_REG_6) }, |
1741 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 1742 | }, |
1ceb70f8 | 1743 | /* REG_0FA6 */ |
252b5132 | 1744 | { |
4e7d34a6 L |
1745 | { "montmul", { { OP_0f07, 0 } } }, |
1746 | { "xsha1", { { OP_0f07, 0 } } }, | |
1747 | { "xsha256", { { OP_0f07, 0 } } }, | |
1748 | { "(bad)", { { OP_0f07, 0 } } }, | |
1749 | { "(bad)", { { OP_0f07, 0 } } }, | |
1750 | { "(bad)", { { OP_0f07, 0 } } }, | |
1751 | { "(bad)", { { OP_0f07, 0 } } }, | |
1752 | { "(bad)", { { OP_0f07, 0 } } }, | |
1753 | }, | |
1ceb70f8 | 1754 | /* REG_0FA7 */ |
4e7d34a6 L |
1755 | { |
1756 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
1757 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
1758 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
1759 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
1760 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
1761 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
1762 | { "(bad)", { { OP_0f07, 0 } } }, | |
1763 | { "(bad)", { { OP_0f07, 0 } } }, | |
1764 | }, | |
1ceb70f8 | 1765 | /* REG_0FAE */ |
4e7d34a6 | 1766 | { |
1ceb70f8 L |
1767 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
1768 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
1769 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
1770 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 1771 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
1772 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
1773 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
1774 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 1775 | }, |
1ceb70f8 | 1776 | /* REG_0FBA */ |
252b5132 | 1777 | { |
ce518a5f L |
1778 | { "(bad)", { XX } }, |
1779 | { "(bad)", { XX } }, | |
d8faab4e L |
1780 | { "(bad)", { XX } }, |
1781 | { "(bad)", { XX } }, | |
4e7d34a6 L |
1782 | { "btQ", { Ev, Ib } }, |
1783 | { "btsQ", { Ev, Ib } }, | |
1784 | { "btrQ", { Ev, Ib } }, | |
1785 | { "btcQ", { Ev, Ib } }, | |
c608c12e | 1786 | }, |
1ceb70f8 | 1787 | /* REG_0FC7 */ |
c608c12e | 1788 | { |
b844680a | 1789 | { "(bad)", { XX } }, |
4e7d34a6 | 1790 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
d8faab4e | 1791 | { "(bad)", { XX } }, |
b844680a L |
1792 | { "(bad)", { XX } }, |
1793 | { "(bad)", { XX } }, | |
1794 | { "(bad)", { XX } }, | |
1ceb70f8 L |
1795 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
1796 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 1797 | }, |
4e7d34a6 L |
1798 | }; |
1799 | ||
1ceb70f8 L |
1800 | static const struct dis386 prefix_table[][4] = { |
1801 | /* PREFIX_90 */ | |
252b5132 | 1802 | { |
4e7d34a6 L |
1803 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
1804 | { "pause", { XX } }, | |
1805 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
1806 | { "(bad)", { XX } }, | |
0f10071e | 1807 | }, |
4e7d34a6 | 1808 | |
1ceb70f8 | 1809 | /* PREFIX_0F10 */ |
cc0ec051 | 1810 | { |
4e7d34a6 L |
1811 | { "movups", { XM, EXx } }, |
1812 | { "movss", { XM, EXd } }, | |
1813 | { "movupd", { XM, EXx } }, | |
1814 | { "movsd", { XM, EXq } }, | |
30d1c836 | 1815 | }, |
4e7d34a6 | 1816 | |
1ceb70f8 | 1817 | /* PREFIX_0F11 */ |
30d1c836 | 1818 | { |
d5d7db8e L |
1819 | { "movups", { EXx, XM } }, |
1820 | { "movss", { EXd, XM } }, | |
1821 | { "movupd", { EXx, XM } }, | |
1822 | { "movsd", { EXq, XM } }, | |
4e7d34a6 | 1823 | }, |
252b5132 | 1824 | |
1ceb70f8 | 1825 | /* PREFIX_0F12 */ |
c608c12e | 1826 | { |
1ceb70f8 | 1827 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
1828 | { "movsldup", { XM, EXx } }, |
1829 | { "movlpd", { XM, EXq } }, | |
1830 | { "movddup", { XM, EXq } }, | |
c608c12e | 1831 | }, |
4e7d34a6 | 1832 | |
1ceb70f8 | 1833 | /* PREFIX_0F16 */ |
c608c12e | 1834 | { |
1ceb70f8 | 1835 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
1836 | { "movshdup", { XM, EXx } }, |
1837 | { "movhpd", { XM, EXq } }, | |
058f233b | 1838 | { "(bad)", { XX } }, |
c608c12e | 1839 | }, |
4e7d34a6 | 1840 | |
1ceb70f8 | 1841 | /* PREFIX_0F2A */ |
c608c12e | 1842 | { |
09335d05 | 1843 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 1844 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 1845 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 1846 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 1847 | }, |
4e7d34a6 | 1848 | |
1ceb70f8 | 1849 | /* PREFIX_0F2B */ |
c608c12e | 1850 | { |
75c135a8 L |
1851 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
1852 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
1853 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
1854 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 1855 | }, |
4e7d34a6 | 1856 | |
1ceb70f8 | 1857 | /* PREFIX_0F2C */ |
c608c12e | 1858 | { |
09335d05 L |
1859 | { "cvttps2pi", { MXC, EXq } }, |
1860 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 1861 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 1862 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 1863 | }, |
4e7d34a6 | 1864 | |
1ceb70f8 | 1865 | /* PREFIX_0F2D */ |
c608c12e | 1866 | { |
4e7d34a6 L |
1867 | { "cvtps2pi", { MXC, EXq } }, |
1868 | { "cvtss2siY", { Gv, EXd } }, | |
1869 | { "cvtpd2pi", { MXC, EXx } }, | |
1870 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 1871 | }, |
4e7d34a6 | 1872 | |
1ceb70f8 | 1873 | /* PREFIX_0F2E */ |
c608c12e | 1874 | { |
4e7d34a6 L |
1875 | { "ucomiss",{ XM, EXd } }, |
1876 | { "(bad)", { XX } }, | |
1877 | { "ucomisd",{ XM, EXq } }, | |
1878 | { "(bad)", { XX } }, | |
c608c12e | 1879 | }, |
4e7d34a6 | 1880 | |
1ceb70f8 | 1881 | /* PREFIX_0F2F */ |
c608c12e | 1882 | { |
4e7d34a6 L |
1883 | { "comiss", { XM, EXd } }, |
1884 | { "(bad)", { XX } }, | |
1885 | { "comisd", { XM, EXq } }, | |
1886 | { "(bad)", { XX } }, | |
c608c12e | 1887 | }, |
4e7d34a6 | 1888 | |
1ceb70f8 | 1889 | /* PREFIX_0F51 */ |
c608c12e | 1890 | { |
4e7d34a6 L |
1891 | { "sqrtps", { XM, EXx } }, |
1892 | { "sqrtss", { XM, EXd } }, | |
1893 | { "sqrtpd", { XM, EXx } }, | |
1894 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 1895 | }, |
4e7d34a6 | 1896 | |
1ceb70f8 | 1897 | /* PREFIX_0F52 */ |
c608c12e | 1898 | { |
4e7d34a6 L |
1899 | { "rsqrtps",{ XM, EXx } }, |
1900 | { "rsqrtss",{ XM, EXd } }, | |
058f233b L |
1901 | { "(bad)", { XX } }, |
1902 | { "(bad)", { XX } }, | |
c608c12e | 1903 | }, |
4e7d34a6 | 1904 | |
1ceb70f8 | 1905 | /* PREFIX_0F53 */ |
c608c12e | 1906 | { |
4e7d34a6 L |
1907 | { "rcpps", { XM, EXx } }, |
1908 | { "rcpss", { XM, EXd } }, | |
058f233b L |
1909 | { "(bad)", { XX } }, |
1910 | { "(bad)", { XX } }, | |
c608c12e | 1911 | }, |
4e7d34a6 | 1912 | |
1ceb70f8 | 1913 | /* PREFIX_0F58 */ |
c608c12e | 1914 | { |
4e7d34a6 L |
1915 | { "addps", { XM, EXx } }, |
1916 | { "addss", { XM, EXd } }, | |
1917 | { "addpd", { XM, EXx } }, | |
1918 | { "addsd", { XM, EXq } }, | |
c608c12e | 1919 | }, |
4e7d34a6 | 1920 | |
1ceb70f8 | 1921 | /* PREFIX_0F59 */ |
c608c12e | 1922 | { |
4e7d34a6 L |
1923 | { "mulps", { XM, EXx } }, |
1924 | { "mulss", { XM, EXd } }, | |
1925 | { "mulpd", { XM, EXx } }, | |
1926 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 1927 | }, |
4e7d34a6 | 1928 | |
1ceb70f8 | 1929 | /* PREFIX_0F5A */ |
041bd2e0 | 1930 | { |
4e7d34a6 L |
1931 | { "cvtps2pd", { XM, EXq } }, |
1932 | { "cvtss2sd", { XM, EXd } }, | |
1933 | { "cvtpd2ps", { XM, EXx } }, | |
1934 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 1935 | }, |
4e7d34a6 | 1936 | |
1ceb70f8 | 1937 | /* PREFIX_0F5B */ |
041bd2e0 | 1938 | { |
09a2c6cf L |
1939 | { "cvtdq2ps", { XM, EXx } }, |
1940 | { "cvttps2dq", { XM, EXx } }, | |
1941 | { "cvtps2dq", { XM, EXx } }, | |
058f233b | 1942 | { "(bad)", { XX } }, |
041bd2e0 | 1943 | }, |
4e7d34a6 | 1944 | |
1ceb70f8 | 1945 | /* PREFIX_0F5C */ |
041bd2e0 | 1946 | { |
4e7d34a6 L |
1947 | { "subps", { XM, EXx } }, |
1948 | { "subss", { XM, EXd } }, | |
1949 | { "subpd", { XM, EXx } }, | |
1950 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 1951 | }, |
4e7d34a6 | 1952 | |
1ceb70f8 | 1953 | /* PREFIX_0F5D */ |
041bd2e0 | 1954 | { |
4e7d34a6 L |
1955 | { "minps", { XM, EXx } }, |
1956 | { "minss", { XM, EXd } }, | |
1957 | { "minpd", { XM, EXx } }, | |
1958 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 1959 | }, |
4e7d34a6 | 1960 | |
1ceb70f8 | 1961 | /* PREFIX_0F5E */ |
041bd2e0 | 1962 | { |
4e7d34a6 L |
1963 | { "divps", { XM, EXx } }, |
1964 | { "divss", { XM, EXd } }, | |
1965 | { "divpd", { XM, EXx } }, | |
1966 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 1967 | }, |
4e7d34a6 | 1968 | |
1ceb70f8 | 1969 | /* PREFIX_0F5F */ |
041bd2e0 | 1970 | { |
4e7d34a6 L |
1971 | { "maxps", { XM, EXx } }, |
1972 | { "maxss", { XM, EXd } }, | |
1973 | { "maxpd", { XM, EXx } }, | |
1974 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 1975 | }, |
4e7d34a6 | 1976 | |
1ceb70f8 | 1977 | /* PREFIX_0F60 */ |
041bd2e0 | 1978 | { |
4e7d34a6 L |
1979 | { "punpcklbw",{ MX, EMd } }, |
1980 | { "(bad)", { XX } }, | |
1981 | { "punpcklbw",{ MX, EMx } }, | |
1982 | { "(bad)", { XX } }, | |
041bd2e0 | 1983 | }, |
4e7d34a6 | 1984 | |
1ceb70f8 | 1985 | /* PREFIX_0F61 */ |
041bd2e0 | 1986 | { |
4e7d34a6 L |
1987 | { "punpcklwd",{ MX, EMd } }, |
1988 | { "(bad)", { XX } }, | |
1989 | { "punpcklwd",{ MX, EMx } }, | |
1990 | { "(bad)", { XX } }, | |
041bd2e0 | 1991 | }, |
4e7d34a6 | 1992 | |
1ceb70f8 | 1993 | /* PREFIX_0F62 */ |
041bd2e0 | 1994 | { |
4e7d34a6 L |
1995 | { "punpckldq",{ MX, EMd } }, |
1996 | { "(bad)", { XX } }, | |
1997 | { "punpckldq",{ MX, EMx } }, | |
1998 | { "(bad)", { XX } }, | |
041bd2e0 | 1999 | }, |
4e7d34a6 | 2000 | |
1ceb70f8 | 2001 | /* PREFIX_0F6C */ |
041bd2e0 | 2002 | { |
058f233b L |
2003 | { "(bad)", { XX } }, |
2004 | { "(bad)", { XX } }, | |
4e7d34a6 | 2005 | { "punpcklqdq", { XM, EXx } }, |
058f233b | 2006 | { "(bad)", { XX } }, |
0f17484f | 2007 | }, |
4e7d34a6 | 2008 | |
1ceb70f8 | 2009 | /* PREFIX_0F6D */ |
0f17484f | 2010 | { |
058f233b L |
2011 | { "(bad)", { XX } }, |
2012 | { "(bad)", { XX } }, | |
4e7d34a6 | 2013 | { "punpckhqdq", { XM, EXx } }, |
058f233b | 2014 | { "(bad)", { XX } }, |
041bd2e0 | 2015 | }, |
4e7d34a6 | 2016 | |
1ceb70f8 | 2017 | /* PREFIX_0F6F */ |
ca164297 | 2018 | { |
4e7d34a6 L |
2019 | { "movq", { MX, EM } }, |
2020 | { "movdqu", { XM, EXx } }, | |
2021 | { "movdqa", { XM, EXx } }, | |
058f233b | 2022 | { "(bad)", { XX } }, |
ca164297 | 2023 | }, |
4e7d34a6 | 2024 | |
1ceb70f8 | 2025 | /* PREFIX_0F70 */ |
4e7d34a6 L |
2026 | { |
2027 | { "pshufw", { MX, EM, Ib } }, | |
2028 | { "pshufhw",{ XM, EXx, Ib } }, | |
2029 | { "pshufd", { XM, EXx, Ib } }, | |
2030 | { "pshuflw",{ XM, EXx, Ib } }, | |
2031 | }, | |
2032 | ||
92fddf8e L |
2033 | /* PREFIX_0F73_REG_3 */ |
2034 | { | |
2035 | { "(bad)", { XX } }, | |
2036 | { "(bad)", { XX } }, | |
2037 | { "psrldq", { XS, Ib } }, | |
2038 | { "(bad)", { XX } }, | |
2039 | }, | |
2040 | ||
2041 | /* PREFIX_0F73_REG_7 */ | |
2042 | { | |
2043 | { "(bad)", { XX } }, | |
2044 | { "(bad)", { XX } }, | |
2045 | { "pslldq", { XS, Ib } }, | |
2046 | { "(bad)", { XX } }, | |
2047 | }, | |
2048 | ||
1ceb70f8 | 2049 | /* PREFIX_0F78 */ |
4e7d34a6 L |
2050 | { |
2051 | {"vmread", { Em, Gm } }, | |
2052 | {"(bad)", { XX } }, | |
2053 | {"extrq", { XS, Ib, Ib } }, | |
2054 | {"insertq", { XM, XS, Ib, Ib } }, | |
2055 | }, | |
2056 | ||
1ceb70f8 | 2057 | /* PREFIX_0F79 */ |
4e7d34a6 L |
2058 | { |
2059 | {"vmwrite", { Gm, Em } }, | |
2060 | {"(bad)", { XX } }, | |
2061 | {"extrq", { XM, XS } }, | |
2062 | {"insertq", { XM, XS } }, | |
2063 | }, | |
2064 | ||
1ceb70f8 | 2065 | /* PREFIX_0F7C */ |
ca164297 | 2066 | { |
058f233b L |
2067 | { "(bad)", { XX } }, |
2068 | { "(bad)", { XX } }, | |
09a2c6cf L |
2069 | { "haddpd", { XM, EXx } }, |
2070 | { "haddps", { XM, EXx } }, | |
ca164297 | 2071 | }, |
4e7d34a6 | 2072 | |
1ceb70f8 | 2073 | /* PREFIX_0F7D */ |
ca164297 | 2074 | { |
058f233b L |
2075 | { "(bad)", { XX } }, |
2076 | { "(bad)", { XX } }, | |
09a2c6cf L |
2077 | { "hsubpd", { XM, EXx } }, |
2078 | { "hsubps", { XM, EXx } }, | |
ca164297 | 2079 | }, |
4e7d34a6 | 2080 | |
1ceb70f8 | 2081 | /* PREFIX_0F7E */ |
ca164297 | 2082 | { |
4e7d34a6 L |
2083 | { "movK", { Edq, MX } }, |
2084 | { "movq", { XM, EXq } }, | |
2085 | { "movK", { Edq, XM } }, | |
058f233b | 2086 | { "(bad)", { XX } }, |
ca164297 | 2087 | }, |
4e7d34a6 | 2088 | |
1ceb70f8 | 2089 | /* PREFIX_0F7F */ |
ca164297 | 2090 | { |
4e7d34a6 | 2091 | { "movq", { EM, MX } }, |
d5d7db8e L |
2092 | { "movdqu", { EXx, XM } }, |
2093 | { "movdqa", { EXx, XM } }, | |
058f233b | 2094 | { "(bad)", { XX } }, |
ca164297 | 2095 | }, |
4e7d34a6 | 2096 | |
1ceb70f8 | 2097 | /* PREFIX_0FB8 */ |
ca164297 | 2098 | { |
4e7d34a6 L |
2099 | { "(bad)", { XX } }, |
2100 | { "popcntS", { Gv, Ev } }, | |
2101 | { "(bad)", { XX } }, | |
2102 | { "(bad)", { XX } }, | |
ca164297 | 2103 | }, |
4e7d34a6 | 2104 | |
1ceb70f8 | 2105 | /* PREFIX_0FBD */ |
050dfa73 | 2106 | { |
4e7d34a6 L |
2107 | { "bsrS", { Gv, Ev } }, |
2108 | { "lzcntS", { Gv, Ev } }, | |
2109 | { "bsrS", { Gv, Ev } }, | |
2110 | { "(bad)", { XX } }, | |
050dfa73 MM |
2111 | }, |
2112 | ||
1ceb70f8 | 2113 | /* PREFIX_0FC2 */ |
050dfa73 | 2114 | { |
ad19981d L |
2115 | { "cmpps", { XM, EXx, CMP } }, |
2116 | { "cmpss", { XM, EXd, CMP } }, | |
2117 | { "cmppd", { XM, EXx, CMP } }, | |
2118 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 2119 | }, |
246c51aa | 2120 | |
4ee52178 L |
2121 | /* PREFIX_0FC3 */ |
2122 | { | |
2123 | { "movntiS", { Ma, Gv } }, | |
2124 | { "(bad)", { XX } }, | |
2125 | { "(bad)", { XX } }, | |
2126 | { "(bad)", { XX } }, | |
2127 | }, | |
2128 | ||
92fddf8e L |
2129 | /* PREFIX_0FC7_REG_6 */ |
2130 | { | |
2131 | { "vmptrld",{ Mq } }, | |
2132 | { "vmxon", { Mq } }, | |
2133 | { "vmclear",{ Mq } }, | |
2134 | { "(bad)", { XX } }, | |
2135 | }, | |
2136 | ||
1ceb70f8 | 2137 | /* PREFIX_0FD0 */ |
050dfa73 | 2138 | { |
058f233b L |
2139 | { "(bad)", { XX } }, |
2140 | { "(bad)", { XX } }, | |
4e7d34a6 L |
2141 | { "addsubpd", { XM, EXx } }, |
2142 | { "addsubps", { XM, EXx } }, | |
246c51aa | 2143 | }, |
050dfa73 | 2144 | |
1ceb70f8 | 2145 | /* PREFIX_0FD6 */ |
050dfa73 | 2146 | { |
058f233b | 2147 | { "(bad)", { XX } }, |
4e7d34a6 L |
2148 | { "movq2dq",{ XM, MS } }, |
2149 | { "movq", { EXq, XM } }, | |
2150 | { "movdq2q",{ MX, XS } }, | |
050dfa73 MM |
2151 | }, |
2152 | ||
1ceb70f8 | 2153 | /* PREFIX_0FE6 */ |
7918206c | 2154 | { |
058f233b | 2155 | { "(bad)", { XX } }, |
4e7d34a6 L |
2156 | { "cvtdq2pd", { XM, EXq } }, |
2157 | { "cvttpd2dq", { XM, EXx } }, | |
2158 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 2159 | }, |
8b38ad71 | 2160 | |
1ceb70f8 | 2161 | /* PREFIX_0FE7 */ |
8b38ad71 | 2162 | { |
4ee52178 | 2163 | { "movntq", { Mq, MX } }, |
058f233b | 2164 | { "(bad)", { XX } }, |
75c135a8 | 2165 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
058f233b | 2166 | { "(bad)", { XX } }, |
4e7d34a6 L |
2167 | }, |
2168 | ||
1ceb70f8 | 2169 | /* PREFIX_0FF0 */ |
4e7d34a6 | 2170 | { |
058f233b L |
2171 | { "(bad)", { XX } }, |
2172 | { "(bad)", { XX } }, | |
2173 | { "(bad)", { XX } }, | |
1ceb70f8 | 2174 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
2175 | }, |
2176 | ||
1ceb70f8 | 2177 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
2178 | { |
2179 | { "maskmovq", { MX, MS } }, | |
058f233b | 2180 | { "(bad)", { XX } }, |
4e7d34a6 | 2181 | { "maskmovdqu", { XM, XS } }, |
058f233b | 2182 | { "(bad)", { XX } }, |
8b38ad71 | 2183 | }, |
42903f7f | 2184 | |
1ceb70f8 | 2185 | /* PREFIX_0F3810 */ |
42903f7f L |
2186 | { |
2187 | { "(bad)", { XX } }, | |
2188 | { "(bad)", { XX } }, | |
88a94849 | 2189 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
2190 | { "(bad)", { XX } }, |
2191 | }, | |
2192 | ||
1ceb70f8 | 2193 | /* PREFIX_0F3814 */ |
42903f7f L |
2194 | { |
2195 | { "(bad)", { XX } }, | |
2196 | { "(bad)", { XX } }, | |
88a94849 | 2197 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
2198 | { "(bad)", { XX } }, |
2199 | }, | |
2200 | ||
1ceb70f8 | 2201 | /* PREFIX_0F3815 */ |
42903f7f L |
2202 | { |
2203 | { "(bad)", { XX } }, | |
2204 | { "(bad)", { XX } }, | |
09a2c6cf | 2205 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
2206 | { "(bad)", { XX } }, |
2207 | }, | |
2208 | ||
1ceb70f8 | 2209 | /* PREFIX_0F3817 */ |
42903f7f L |
2210 | { |
2211 | { "(bad)", { XX } }, | |
2212 | { "(bad)", { XX } }, | |
09a2c6cf | 2213 | { "ptest", { XM, EXx } }, |
42903f7f L |
2214 | { "(bad)", { XX } }, |
2215 | }, | |
2216 | ||
1ceb70f8 | 2217 | /* PREFIX_0F3820 */ |
42903f7f L |
2218 | { |
2219 | { "(bad)", { XX } }, | |
2220 | { "(bad)", { XX } }, | |
8976381e | 2221 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
2222 | { "(bad)", { XX } }, |
2223 | }, | |
2224 | ||
1ceb70f8 | 2225 | /* PREFIX_0F3821 */ |
42903f7f L |
2226 | { |
2227 | { "(bad)", { XX } }, | |
2228 | { "(bad)", { XX } }, | |
8976381e | 2229 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
2230 | { "(bad)", { XX } }, |
2231 | }, | |
2232 | ||
1ceb70f8 | 2233 | /* PREFIX_0F3822 */ |
42903f7f L |
2234 | { |
2235 | { "(bad)", { XX } }, | |
2236 | { "(bad)", { XX } }, | |
8976381e | 2237 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
2238 | { "(bad)", { XX } }, |
2239 | }, | |
2240 | ||
1ceb70f8 | 2241 | /* PREFIX_0F3823 */ |
42903f7f L |
2242 | { |
2243 | { "(bad)", { XX } }, | |
2244 | { "(bad)", { XX } }, | |
8976381e | 2245 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
2246 | { "(bad)", { XX } }, |
2247 | }, | |
2248 | ||
1ceb70f8 | 2249 | /* PREFIX_0F3824 */ |
42903f7f L |
2250 | { |
2251 | { "(bad)", { XX } }, | |
2252 | { "(bad)", { XX } }, | |
8976381e | 2253 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
2254 | { "(bad)", { XX } }, |
2255 | }, | |
2256 | ||
1ceb70f8 | 2257 | /* PREFIX_0F3825 */ |
42903f7f L |
2258 | { |
2259 | { "(bad)", { XX } }, | |
2260 | { "(bad)", { XX } }, | |
8976381e | 2261 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
2262 | { "(bad)", { XX } }, |
2263 | }, | |
2264 | ||
1ceb70f8 | 2265 | /* PREFIX_0F3828 */ |
42903f7f L |
2266 | { |
2267 | { "(bad)", { XX } }, | |
2268 | { "(bad)", { XX } }, | |
09a2c6cf | 2269 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
2270 | { "(bad)", { XX } }, |
2271 | }, | |
2272 | ||
1ceb70f8 | 2273 | /* PREFIX_0F3829 */ |
42903f7f L |
2274 | { |
2275 | { "(bad)", { XX } }, | |
2276 | { "(bad)", { XX } }, | |
09a2c6cf | 2277 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
2278 | { "(bad)", { XX } }, |
2279 | }, | |
2280 | ||
1ceb70f8 | 2281 | /* PREFIX_0F382A */ |
42903f7f L |
2282 | { |
2283 | { "(bad)", { XX } }, | |
2284 | { "(bad)", { XX } }, | |
75c135a8 | 2285 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
2286 | { "(bad)", { XX } }, |
2287 | }, | |
2288 | ||
1ceb70f8 | 2289 | /* PREFIX_0F382B */ |
42903f7f L |
2290 | { |
2291 | { "(bad)", { XX } }, | |
2292 | { "(bad)", { XX } }, | |
09a2c6cf | 2293 | { "packusdw", { XM, EXx } }, |
42903f7f L |
2294 | { "(bad)", { XX } }, |
2295 | }, | |
2296 | ||
1ceb70f8 | 2297 | /* PREFIX_0F3830 */ |
42903f7f L |
2298 | { |
2299 | { "(bad)", { XX } }, | |
2300 | { "(bad)", { XX } }, | |
8976381e | 2301 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
2302 | { "(bad)", { XX } }, |
2303 | }, | |
2304 | ||
1ceb70f8 | 2305 | /* PREFIX_0F3831 */ |
42903f7f L |
2306 | { |
2307 | { "(bad)", { XX } }, | |
2308 | { "(bad)", { XX } }, | |
8976381e | 2309 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
2310 | { "(bad)", { XX } }, |
2311 | }, | |
2312 | ||
1ceb70f8 | 2313 | /* PREFIX_0F3832 */ |
42903f7f L |
2314 | { |
2315 | { "(bad)", { XX } }, | |
2316 | { "(bad)", { XX } }, | |
8976381e | 2317 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
2318 | { "(bad)", { XX } }, |
2319 | }, | |
2320 | ||
1ceb70f8 | 2321 | /* PREFIX_0F3833 */ |
42903f7f L |
2322 | { |
2323 | { "(bad)", { XX } }, | |
2324 | { "(bad)", { XX } }, | |
8976381e | 2325 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
2326 | { "(bad)", { XX } }, |
2327 | }, | |
2328 | ||
1ceb70f8 | 2329 | /* PREFIX_0F3834 */ |
42903f7f L |
2330 | { |
2331 | { "(bad)", { XX } }, | |
2332 | { "(bad)", { XX } }, | |
8976381e | 2333 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
2334 | { "(bad)", { XX } }, |
2335 | }, | |
2336 | ||
1ceb70f8 | 2337 | /* PREFIX_0F3835 */ |
42903f7f L |
2338 | { |
2339 | { "(bad)", { XX } }, | |
2340 | { "(bad)", { XX } }, | |
8976381e | 2341 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
2342 | { "(bad)", { XX } }, |
2343 | }, | |
2344 | ||
1ceb70f8 | 2345 | /* PREFIX_0F3837 */ |
4e7d34a6 L |
2346 | { |
2347 | { "(bad)", { XX } }, | |
2348 | { "(bad)", { XX } }, | |
2349 | { "pcmpgtq", { XM, EXx } }, | |
2350 | { "(bad)", { XX } }, | |
2351 | }, | |
2352 | ||
1ceb70f8 | 2353 | /* PREFIX_0F3838 */ |
42903f7f L |
2354 | { |
2355 | { "(bad)", { XX } }, | |
2356 | { "(bad)", { XX } }, | |
09a2c6cf | 2357 | { "pminsb", { XM, EXx } }, |
42903f7f L |
2358 | { "(bad)", { XX } }, |
2359 | }, | |
2360 | ||
1ceb70f8 | 2361 | /* PREFIX_0F3839 */ |
42903f7f L |
2362 | { |
2363 | { "(bad)", { XX } }, | |
2364 | { "(bad)", { XX } }, | |
09a2c6cf | 2365 | { "pminsd", { XM, EXx } }, |
42903f7f L |
2366 | { "(bad)", { XX } }, |
2367 | }, | |
2368 | ||
1ceb70f8 | 2369 | /* PREFIX_0F383A */ |
42903f7f L |
2370 | { |
2371 | { "(bad)", { XX } }, | |
2372 | { "(bad)", { XX } }, | |
09a2c6cf | 2373 | { "pminuw", { XM, EXx } }, |
42903f7f L |
2374 | { "(bad)", { XX } }, |
2375 | }, | |
2376 | ||
1ceb70f8 | 2377 | /* PREFIX_0F383B */ |
42903f7f L |
2378 | { |
2379 | { "(bad)", { XX } }, | |
2380 | { "(bad)", { XX } }, | |
09a2c6cf | 2381 | { "pminud", { XM, EXx } }, |
42903f7f L |
2382 | { "(bad)", { XX } }, |
2383 | }, | |
2384 | ||
1ceb70f8 | 2385 | /* PREFIX_0F383C */ |
42903f7f L |
2386 | { |
2387 | { "(bad)", { XX } }, | |
2388 | { "(bad)", { XX } }, | |
09a2c6cf | 2389 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
2390 | { "(bad)", { XX } }, |
2391 | }, | |
2392 | ||
1ceb70f8 | 2393 | /* PREFIX_0F383D */ |
42903f7f L |
2394 | { |
2395 | { "(bad)", { XX } }, | |
2396 | { "(bad)", { XX } }, | |
09a2c6cf | 2397 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
2398 | { "(bad)", { XX } }, |
2399 | }, | |
2400 | ||
1ceb70f8 | 2401 | /* PREFIX_0F383E */ |
42903f7f L |
2402 | { |
2403 | { "(bad)", { XX } }, | |
2404 | { "(bad)", { XX } }, | |
09a2c6cf | 2405 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
2406 | { "(bad)", { XX } }, |
2407 | }, | |
2408 | ||
1ceb70f8 | 2409 | /* PREFIX_0F383F */ |
42903f7f L |
2410 | { |
2411 | { "(bad)", { XX } }, | |
2412 | { "(bad)", { XX } }, | |
09a2c6cf | 2413 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
2414 | { "(bad)", { XX } }, |
2415 | }, | |
2416 | ||
1ceb70f8 | 2417 | /* PREFIX_0F3840 */ |
42903f7f L |
2418 | { |
2419 | { "(bad)", { XX } }, | |
2420 | { "(bad)", { XX } }, | |
09a2c6cf | 2421 | { "pmulld", { XM, EXx } }, |
42903f7f L |
2422 | { "(bad)", { XX } }, |
2423 | }, | |
2424 | ||
1ceb70f8 | 2425 | /* PREFIX_0F3841 */ |
42903f7f L |
2426 | { |
2427 | { "(bad)", { XX } }, | |
2428 | { "(bad)", { XX } }, | |
09a2c6cf | 2429 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
2430 | { "(bad)", { XX } }, |
2431 | }, | |
2432 | ||
1ceb70f8 | 2433 | /* PREFIX_0F38F0 */ |
4e7d34a6 L |
2434 | { |
2435 | { "(bad)", { XX } }, | |
2436 | { "(bad)", { XX } }, | |
2437 | { "(bad)", { XX } }, | |
2438 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, | |
2439 | }, | |
2440 | ||
1ceb70f8 | 2441 | /* PREFIX_0F38F1 */ |
4e7d34a6 L |
2442 | { |
2443 | { "(bad)", { XX } }, | |
2444 | { "(bad)", { XX } }, | |
2445 | { "(bad)", { XX } }, | |
2446 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, | |
2447 | }, | |
2448 | ||
1ceb70f8 | 2449 | /* PREFIX_0F3A08 */ |
42903f7f L |
2450 | { |
2451 | { "(bad)", { XX } }, | |
2452 | { "(bad)", { XX } }, | |
09a2c6cf | 2453 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
2454 | { "(bad)", { XX } }, |
2455 | }, | |
2456 | ||
1ceb70f8 | 2457 | /* PREFIX_0F3A09 */ |
42903f7f L |
2458 | { |
2459 | { "(bad)", { XX } }, | |
2460 | { "(bad)", { XX } }, | |
09a2c6cf | 2461 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
2462 | { "(bad)", { XX } }, |
2463 | }, | |
2464 | ||
1ceb70f8 | 2465 | /* PREFIX_0F3A0A */ |
42903f7f L |
2466 | { |
2467 | { "(bad)", { XX } }, | |
2468 | { "(bad)", { XX } }, | |
09335d05 | 2469 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
2470 | { "(bad)", { XX } }, |
2471 | }, | |
2472 | ||
1ceb70f8 | 2473 | /* PREFIX_0F3A0B */ |
42903f7f L |
2474 | { |
2475 | { "(bad)", { XX } }, | |
2476 | { "(bad)", { XX } }, | |
09335d05 | 2477 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
2478 | { "(bad)", { XX } }, |
2479 | }, | |
2480 | ||
1ceb70f8 | 2481 | /* PREFIX_0F3A0C */ |
42903f7f L |
2482 | { |
2483 | { "(bad)", { XX } }, | |
2484 | { "(bad)", { XX } }, | |
09a2c6cf | 2485 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
2486 | { "(bad)", { XX } }, |
2487 | }, | |
2488 | ||
1ceb70f8 | 2489 | /* PREFIX_0F3A0D */ |
42903f7f L |
2490 | { |
2491 | { "(bad)", { XX } }, | |
2492 | { "(bad)", { XX } }, | |
09a2c6cf | 2493 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
2494 | { "(bad)", { XX } }, |
2495 | }, | |
2496 | ||
1ceb70f8 | 2497 | /* PREFIX_0F3A0E */ |
42903f7f L |
2498 | { |
2499 | { "(bad)", { XX } }, | |
2500 | { "(bad)", { XX } }, | |
09a2c6cf | 2501 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
2502 | { "(bad)", { XX } }, |
2503 | }, | |
2504 | ||
1ceb70f8 | 2505 | /* PREFIX_0F3A14 */ |
42903f7f L |
2506 | { |
2507 | { "(bad)", { XX } }, | |
2508 | { "(bad)", { XX } }, | |
2509 | { "pextrb", { Edqb, XM, Ib } }, | |
2510 | { "(bad)", { XX } }, | |
2511 | }, | |
2512 | ||
1ceb70f8 | 2513 | /* PREFIX_0F3A15 */ |
42903f7f L |
2514 | { |
2515 | { "(bad)", { XX } }, | |
2516 | { "(bad)", { XX } }, | |
2517 | { "pextrw", { Edqw, XM, Ib } }, | |
2518 | { "(bad)", { XX } }, | |
2519 | }, | |
2520 | ||
1ceb70f8 | 2521 | /* PREFIX_0F3A16 */ |
42903f7f L |
2522 | { |
2523 | { "(bad)", { XX } }, | |
2524 | { "(bad)", { XX } }, | |
2525 | { "pextrK", { Edq, XM, Ib } }, | |
2526 | { "(bad)", { XX } }, | |
2527 | }, | |
2528 | ||
1ceb70f8 | 2529 | /* PREFIX_0F3A17 */ |
42903f7f L |
2530 | { |
2531 | { "(bad)", { XX } }, | |
2532 | { "(bad)", { XX } }, | |
2533 | { "extractps", { Edqd, XM, Ib } }, | |
2534 | { "(bad)", { XX } }, | |
2535 | }, | |
2536 | ||
1ceb70f8 | 2537 | /* PREFIX_0F3A20 */ |
42903f7f L |
2538 | { |
2539 | { "(bad)", { XX } }, | |
2540 | { "(bad)", { XX } }, | |
2541 | { "pinsrb", { XM, Edqb, Ib } }, | |
2542 | { "(bad)", { XX } }, | |
2543 | }, | |
2544 | ||
1ceb70f8 | 2545 | /* PREFIX_0F3A21 */ |
42903f7f L |
2546 | { |
2547 | { "(bad)", { XX } }, | |
2548 | { "(bad)", { XX } }, | |
8976381e | 2549 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
2550 | { "(bad)", { XX } }, |
2551 | }, | |
2552 | ||
1ceb70f8 | 2553 | /* PREFIX_0F3A22 */ |
42903f7f L |
2554 | { |
2555 | { "(bad)", { XX } }, | |
2556 | { "(bad)", { XX } }, | |
2557 | { "pinsrK", { XM, Edq, Ib } }, | |
2558 | { "(bad)", { XX } }, | |
2559 | }, | |
2560 | ||
1ceb70f8 | 2561 | /* PREFIX_0F3A40 */ |
42903f7f L |
2562 | { |
2563 | { "(bad)", { XX } }, | |
2564 | { "(bad)", { XX } }, | |
09a2c6cf | 2565 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
2566 | { "(bad)", { XX } }, |
2567 | }, | |
2568 | ||
1ceb70f8 | 2569 | /* PREFIX_0F3A41 */ |
42903f7f L |
2570 | { |
2571 | { "(bad)", { XX } }, | |
2572 | { "(bad)", { XX } }, | |
09a2c6cf | 2573 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
2574 | { "(bad)", { XX } }, |
2575 | }, | |
2576 | ||
1ceb70f8 | 2577 | /* PREFIX_0F3A42 */ |
42903f7f L |
2578 | { |
2579 | { "(bad)", { XX } }, | |
2580 | { "(bad)", { XX } }, | |
09a2c6cf | 2581 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f L |
2582 | { "(bad)", { XX } }, |
2583 | }, | |
381d071f | 2584 | |
1ceb70f8 | 2585 | /* PREFIX_0F3A60 */ |
381d071f L |
2586 | { |
2587 | { "(bad)", { XX } }, | |
2588 | { "(bad)", { XX } }, | |
4e7d34a6 | 2589 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
2590 | { "(bad)", { XX } }, |
2591 | }, | |
2592 | ||
1ceb70f8 | 2593 | /* PREFIX_0F3A61 */ |
381d071f L |
2594 | { |
2595 | { "(bad)", { XX } }, | |
2596 | { "(bad)", { XX } }, | |
4e7d34a6 | 2597 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f | 2598 | { "(bad)", { XX } }, |
381d071f L |
2599 | }, |
2600 | ||
1ceb70f8 | 2601 | /* PREFIX_0F3A62 */ |
381d071f L |
2602 | { |
2603 | { "(bad)", { XX } }, | |
2604 | { "(bad)", { XX } }, | |
4e7d34a6 | 2605 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f | 2606 | { "(bad)", { XX } }, |
381d071f L |
2607 | }, |
2608 | ||
1ceb70f8 | 2609 | /* PREFIX_0F3A63 */ |
381d071f L |
2610 | { |
2611 | { "(bad)", { XX } }, | |
2612 | { "(bad)", { XX } }, | |
4e7d34a6 | 2613 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f L |
2614 | { "(bad)", { XX } }, |
2615 | }, | |
4e7d34a6 | 2616 | }; |
09a2c6cf | 2617 | |
4e7d34a6 L |
2618 | static const struct dis386 x86_64_table[][2] = { |
2619 | /* X86_64_06 */ | |
09a2c6cf | 2620 | { |
4e7d34a6 L |
2621 | { "push{T|}", { es } }, |
2622 | { "(bad)", { XX } }, | |
09a2c6cf L |
2623 | }, |
2624 | ||
4e7d34a6 | 2625 | /* X86_64_07 */ |
09a2c6cf | 2626 | { |
4e7d34a6 L |
2627 | { "pop{T|}", { es } }, |
2628 | { "(bad)", { XX } }, | |
09a2c6cf L |
2629 | }, |
2630 | ||
4e7d34a6 | 2631 | /* X86_64_0D */ |
09a2c6cf | 2632 | { |
4e7d34a6 L |
2633 | { "push{T|}", { cs } }, |
2634 | { "(bad)", { XX } }, | |
09a2c6cf L |
2635 | }, |
2636 | ||
4e7d34a6 | 2637 | /* X86_64_16 */ |
09a2c6cf | 2638 | { |
4e7d34a6 L |
2639 | { "push{T|}", { ss } }, |
2640 | { "(bad)", { XX } }, | |
09a2c6cf L |
2641 | }, |
2642 | ||
4e7d34a6 | 2643 | /* X86_64_17 */ |
09a2c6cf | 2644 | { |
4e7d34a6 | 2645 | { "pop{T|}", { ss } }, |
ce518a5f | 2646 | { "(bad)", { XX } }, |
5f754f58 | 2647 | }, |
7c52e0e8 | 2648 | |
4e7d34a6 | 2649 | /* X86_64_1E */ |
5f754f58 | 2650 | { |
4e7d34a6 | 2651 | { "push{T|}", { ds } }, |
ce518a5f | 2652 | { "(bad)", { XX } }, |
5f754f58 | 2653 | }, |
7c52e0e8 | 2654 | |
4e7d34a6 | 2655 | /* X86_64_1F */ |
5f754f58 | 2656 | { |
4e7d34a6 | 2657 | { "pop{T|}", { ds } }, |
ce518a5f | 2658 | { "(bad)", { XX } }, |
5f754f58 | 2659 | }, |
7c52e0e8 | 2660 | |
4e7d34a6 | 2661 | /* X86_64_27 */ |
7c52e0e8 | 2662 | { |
4e7d34a6 | 2663 | { "daa", { XX } }, |
7c52e0e8 L |
2664 | { "(bad)", { XX } }, |
2665 | }, | |
2666 | ||
4e7d34a6 | 2667 | /* X86_64_2F */ |
7c52e0e8 | 2668 | { |
4e7d34a6 | 2669 | { "das", { XX } }, |
7c52e0e8 L |
2670 | { "(bad)", { XX } }, |
2671 | }, | |
2672 | ||
4e7d34a6 | 2673 | /* X86_64_37 */ |
7c52e0e8 | 2674 | { |
4e7d34a6 | 2675 | { "aaa", { XX } }, |
7c52e0e8 L |
2676 | { "(bad)", { XX } }, |
2677 | }, | |
2678 | ||
4e7d34a6 | 2679 | /* X86_64_3F */ |
7c52e0e8 | 2680 | { |
4e7d34a6 | 2681 | { "aas", { XX } }, |
7c52e0e8 L |
2682 | { "(bad)", { XX } }, |
2683 | }, | |
2684 | ||
4e7d34a6 | 2685 | /* X86_64_60 */ |
7c52e0e8 | 2686 | { |
4e7d34a6 | 2687 | { "pusha{P|}", { XX } }, |
7c52e0e8 L |
2688 | { "(bad)", { XX } }, |
2689 | }, | |
2690 | ||
4e7d34a6 | 2691 | /* X86_64_61 */ |
7c52e0e8 | 2692 | { |
4e7d34a6 | 2693 | { "popa{P|}", { XX } }, |
7c52e0e8 L |
2694 | { "(bad)", { XX } }, |
2695 | }, | |
2696 | ||
4e7d34a6 | 2697 | /* X86_64_62 */ |
7c52e0e8 | 2698 | { |
1ceb70f8 | 2699 | { MOD_TABLE (MOD_62_32BIT) }, |
7c52e0e8 L |
2700 | { "(bad)", { XX } }, |
2701 | }, | |
2702 | ||
4e7d34a6 | 2703 | /* X86_64_63 */ |
7c52e0e8 | 2704 | { |
4e7d34a6 L |
2705 | { "arpl", { Ew, Gw } }, |
2706 | { "movs{lq|xd}", { Gv, Ed } }, | |
7c52e0e8 L |
2707 | }, |
2708 | ||
4e7d34a6 | 2709 | /* X86_64_6D */ |
7c52e0e8 | 2710 | { |
4e7d34a6 L |
2711 | { "ins{R|}", { Yzr, indirDX } }, |
2712 | { "ins{G|}", { Yzr, indirDX } }, | |
7c52e0e8 L |
2713 | }, |
2714 | ||
4e7d34a6 | 2715 | /* X86_64_6F */ |
7c52e0e8 | 2716 | { |
4e7d34a6 L |
2717 | { "outs{R|}", { indirDXr, Xz } }, |
2718 | { "outs{G|}", { indirDXr, Xz } }, | |
7c52e0e8 L |
2719 | }, |
2720 | ||
4e7d34a6 | 2721 | /* X86_64_9A */ |
7c52e0e8 | 2722 | { |
4e7d34a6 | 2723 | { "Jcall{T|}", { Ap } }, |
7c52e0e8 L |
2724 | { "(bad)", { XX } }, |
2725 | }, | |
2726 | ||
4e7d34a6 | 2727 | /* X86_64_C4 */ |
7c52e0e8 | 2728 | { |
1ceb70f8 | 2729 | { MOD_TABLE (MOD_C4_32BIT) }, |
4e7d34a6 | 2730 | { "(bad)", { XX } }, |
7c52e0e8 L |
2731 | }, |
2732 | ||
4e7d34a6 | 2733 | /* X86_64_C5 */ |
7c52e0e8 | 2734 | { |
1ceb70f8 | 2735 | { MOD_TABLE (MOD_C5_32BIT) }, |
7c52e0e8 L |
2736 | { "(bad)", { XX } }, |
2737 | }, | |
2738 | ||
4e7d34a6 | 2739 | /* X86_64_CE */ |
7c52e0e8 L |
2740 | { |
2741 | { "into", { XX } }, | |
2742 | { "(bad)", { XX } }, | |
2743 | }, | |
2744 | ||
4e7d34a6 | 2745 | /* X86_64_D4 */ |
7c52e0e8 L |
2746 | { |
2747 | { "aam", { sIb } }, | |
2748 | { "(bad)", { XX } }, | |
2749 | }, | |
2750 | ||
4e7d34a6 | 2751 | /* X86_64_D5 */ |
7c52e0e8 L |
2752 | { |
2753 | { "aad", { sIb } }, | |
2754 | { "(bad)", { XX } }, | |
2755 | }, | |
2756 | ||
4e7d34a6 | 2757 | /* X86_64_EA */ |
7c52e0e8 L |
2758 | { |
2759 | { "Jjmp{T|}", { Ap } }, | |
2760 | { "(bad)", { XX } }, | |
2761 | }, | |
2762 | ||
4e7d34a6 | 2763 | /* X86_64_0F01_REG_0 */ |
7c52e0e8 L |
2764 | { |
2765 | { "sgdt{Q|IQ}", { M } }, | |
2766 | { "sgdt", { M } }, | |
2767 | }, | |
2768 | ||
4e7d34a6 | 2769 | /* X86_64_0F01_REG_1 */ |
7c52e0e8 L |
2770 | { |
2771 | { "sidt{Q|IQ}", { M } }, | |
2772 | { "sidt", { M } }, | |
2773 | }, | |
2774 | ||
4e7d34a6 | 2775 | /* X86_64_0F01_REG_2 */ |
7c52e0e8 L |
2776 | { |
2777 | { "lgdt{Q|Q}", { M } }, | |
2778 | { "lgdt", { M } }, | |
2779 | }, | |
2780 | ||
4e7d34a6 | 2781 | /* X86_64_0F01_REG_3 */ |
7c52e0e8 L |
2782 | { |
2783 | { "lidt{Q|Q}", { M } }, | |
2784 | { "lidt", { M } }, | |
2785 | }, | |
6439fc28 AM |
2786 | }; |
2787 | ||
96fbad73 | 2788 | static const struct dis386 three_byte_table[][256] = { |
4e7d34a6 | 2789 | /* THREE_BYTE_0F24 */ |
331d2d0d | 2790 | { |
96fbad73 | 2791 | /* 00 */ |
4e7d34a6 L |
2792 | { "fmaddps", { { OP_DREX4, q_mode } } }, |
2793 | { "fmaddpd", { { OP_DREX4, q_mode } } }, | |
2794 | { "fmaddss", { { OP_DREX4, w_mode } } }, | |
2795 | { "fmaddsd", { { OP_DREX4, d_mode } } }, | |
2796 | { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2797 | { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2798 | { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } }, | |
2799 | { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, | |
96fbad73 | 2800 | /* 08 */ |
4e7d34a6 L |
2801 | { "fmsubps", { { OP_DREX4, q_mode } } }, |
2802 | { "fmsubpd", { { OP_DREX4, q_mode } } }, | |
2803 | { "fmsubss", { { OP_DREX4, w_mode } } }, | |
2804 | { "fmsubsd", { { OP_DREX4, d_mode } } }, | |
2805 | { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2806 | { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2807 | { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } }, | |
2808 | { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, | |
85f10a01 | 2809 | /* 10 */ |
4e7d34a6 L |
2810 | { "fnmaddps", { { OP_DREX4, q_mode } } }, |
2811 | { "fnmaddpd", { { OP_DREX4, q_mode } } }, | |
2812 | { "fnmaddss", { { OP_DREX4, w_mode } } }, | |
2813 | { "fnmaddsd", { { OP_DREX4, d_mode } } }, | |
2814 | { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2815 | { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2816 | { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } }, | |
2817 | { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, | |
85f10a01 | 2818 | /* 18 */ |
4e7d34a6 L |
2819 | { "fnmsubps", { { OP_DREX4, q_mode } } }, |
2820 | { "fnmsubpd", { { OP_DREX4, q_mode } } }, | |
2821 | { "fnmsubss", { { OP_DREX4, w_mode } } }, | |
2822 | { "fnmsubsd", { { OP_DREX4, d_mode } } }, | |
2823 | { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2824 | { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2825 | { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } }, | |
2826 | { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, | |
85f10a01 | 2827 | /* 20 */ |
4e7d34a6 L |
2828 | { "permps", { { OP_DREX4, q_mode } } }, |
2829 | { "permpd", { { OP_DREX4, q_mode } } }, | |
2830 | { "pcmov", { { OP_DREX4, q_mode } } }, | |
2831 | { "pperm", { { OP_DREX4, q_mode } } }, | |
2832 | { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2833 | { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, | |
2834 | { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } }, | |
2835 | { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } }, | |
85f10a01 | 2836 | /* 28 */ |
4e7d34a6 L |
2837 | { "(bad)", { XX } }, |
2838 | { "(bad)", { XX } }, | |
2839 | { "(bad)", { XX } }, | |
2840 | { "(bad)", { XX } }, | |
2841 | { "(bad)", { XX } }, | |
2842 | { "(bad)", { XX } }, | |
2843 | { "(bad)", { XX } }, | |
2844 | { "(bad)", { XX } }, | |
85f10a01 | 2845 | /* 30 */ |
4e7d34a6 L |
2846 | { "(bad)", { XX } }, |
2847 | { "(bad)", { XX } }, | |
2848 | { "(bad)", { XX } }, | |
2849 | { "(bad)", { XX } }, | |
2850 | { "(bad)", { XX } }, | |
2851 | { "(bad)", { XX } }, | |
2852 | { "(bad)", { XX } }, | |
2853 | { "(bad)", { XX } }, | |
85f10a01 | 2854 | /* 38 */ |
4e7d34a6 L |
2855 | { "(bad)", { XX } }, |
2856 | { "(bad)", { XX } }, | |
2857 | { "(bad)", { XX } }, | |
2858 | { "(bad)", { XX } }, | |
2859 | { "(bad)", { XX } }, | |
2860 | { "(bad)", { XX } }, | |
2861 | { "(bad)", { XX } }, | |
2862 | { "(bad)", { XX } }, | |
85f10a01 | 2863 | /* 40 */ |
4e7d34a6 L |
2864 | { "protb", { { OP_DREX3, q_mode } } }, |
2865 | { "protw", { { OP_DREX3, q_mode } } }, | |
2866 | { "protd", { { OP_DREX3, q_mode } } }, | |
2867 | { "protq", { { OP_DREX3, q_mode } } }, | |
2868 | { "pshlb", { { OP_DREX3, q_mode } } }, | |
2869 | { "pshlw", { { OP_DREX3, q_mode } } }, | |
2870 | { "pshld", { { OP_DREX3, q_mode } } }, | |
2871 | { "pshlq", { { OP_DREX3, q_mode } } }, | |
85f10a01 | 2872 | /* 48 */ |
4e7d34a6 L |
2873 | { "pshab", { { OP_DREX3, q_mode } } }, |
2874 | { "pshaw", { { OP_DREX3, q_mode } } }, | |
2875 | { "pshad", { { OP_DREX3, q_mode } } }, | |
2876 | { "pshaq", { { OP_DREX3, q_mode } } }, | |
2877 | { "(bad)", { XX } }, | |
2878 | { "(bad)", { XX } }, | |
2879 | { "(bad)", { XX } }, | |
2880 | { "(bad)", { XX } }, | |
85f10a01 | 2881 | /* 50 */ |
4e7d34a6 L |
2882 | { "(bad)", { XX } }, |
2883 | { "(bad)", { XX } }, | |
2884 | { "(bad)", { XX } }, | |
2885 | { "(bad)", { XX } }, | |
2886 | { "(bad)", { XX } }, | |
2887 | { "(bad)", { XX } }, | |
2888 | { "(bad)", { XX } }, | |
2889 | { "(bad)", { XX } }, | |
85f10a01 | 2890 | /* 58 */ |
4e7d34a6 L |
2891 | { "(bad)", { XX } }, |
2892 | { "(bad)", { XX } }, | |
2893 | { "(bad)", { XX } }, | |
2894 | { "(bad)", { XX } }, | |
2895 | { "(bad)", { XX } }, | |
2896 | { "(bad)", { XX } }, | |
2897 | { "(bad)", { XX } }, | |
2898 | { "(bad)", { XX } }, | |
85f10a01 | 2899 | /* 60 */ |
4e7d34a6 L |
2900 | { "(bad)", { XX } }, |
2901 | { "(bad)", { XX } }, | |
2902 | { "(bad)", { XX } }, | |
2903 | { "(bad)", { XX } }, | |
2904 | { "(bad)", { XX } }, | |
2905 | { "(bad)", { XX } }, | |
2906 | { "(bad)", { XX } }, | |
2907 | { "(bad)", { XX } }, | |
2908 | /* 68 */ | |
2909 | { "(bad)", { XX } }, | |
2910 | { "(bad)", { XX } }, | |
2911 | { "(bad)", { XX } }, | |
2912 | { "(bad)", { XX } }, | |
2913 | { "(bad)", { XX } }, | |
2914 | { "(bad)", { XX } }, | |
2915 | { "(bad)", { XX } }, | |
2916 | { "(bad)", { XX } }, | |
85f10a01 | 2917 | /* 70 */ |
4e7d34a6 L |
2918 | { "(bad)", { XX } }, |
2919 | { "(bad)", { XX } }, | |
2920 | { "(bad)", { XX } }, | |
2921 | { "(bad)", { XX } }, | |
2922 | { "(bad)", { XX } }, | |
2923 | { "(bad)", { XX } }, | |
2924 | { "(bad)", { XX } }, | |
2925 | { "(bad)", { XX } }, | |
85f10a01 | 2926 | /* 78 */ |
4e7d34a6 L |
2927 | { "(bad)", { XX } }, |
2928 | { "(bad)", { XX } }, | |
2929 | { "(bad)", { XX } }, | |
2930 | { "(bad)", { XX } }, | |
2931 | { "(bad)", { XX } }, | |
2932 | { "(bad)", { XX } }, | |
2933 | { "(bad)", { XX } }, | |
2934 | { "(bad)", { XX } }, | |
85f10a01 | 2935 | /* 80 */ |
4e7d34a6 L |
2936 | { "(bad)", { XX } }, |
2937 | { "(bad)", { XX } }, | |
2938 | { "(bad)", { XX } }, | |
2939 | { "(bad)", { XX } }, | |
2940 | { "(bad)", { XX } }, | |
2941 | { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2942 | { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2943 | { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
85f10a01 | 2944 | /* 88 */ |
4e7d34a6 L |
2945 | { "(bad)", { XX } }, |
2946 | { "(bad)", { XX } }, | |
2947 | { "(bad)", { XX } }, | |
2948 | { "(bad)", { XX } }, | |
2949 | { "(bad)", { XX } }, | |
2950 | { "(bad)", { XX } }, | |
2951 | { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2952 | { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
85f10a01 | 2953 | /* 90 */ |
4e7d34a6 L |
2954 | { "(bad)", { XX } }, |
2955 | { "(bad)", { XX } }, | |
2956 | { "(bad)", { XX } }, | |
2957 | { "(bad)", { XX } }, | |
2958 | { "(bad)", { XX } }, | |
2959 | { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2960 | { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2961 | { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
85f10a01 | 2962 | /* 98 */ |
4e7d34a6 L |
2963 | { "(bad)", { XX } }, |
2964 | { "(bad)", { XX } }, | |
2965 | { "(bad)", { XX } }, | |
2966 | { "(bad)", { XX } }, | |
2967 | { "(bad)", { XX } }, | |
2968 | { "(bad)", { XX } }, | |
2969 | { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2970 | { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
85f10a01 | 2971 | /* a0 */ |
4e7d34a6 L |
2972 | { "(bad)", { XX } }, |
2973 | { "(bad)", { XX } }, | |
2974 | { "(bad)", { XX } }, | |
2975 | { "(bad)", { XX } }, | |
2976 | { "(bad)", { XX } }, | |
2977 | { "(bad)", { XX } }, | |
2978 | { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2979 | { "(bad)", { XX } }, | |
85f10a01 | 2980 | /* a8 */ |
4e7d34a6 L |
2981 | { "(bad)", { XX } }, |
2982 | { "(bad)", { XX } }, | |
2983 | { "(bad)", { XX } }, | |
2984 | { "(bad)", { XX } }, | |
2985 | { "(bad)", { XX } }, | |
2986 | { "(bad)", { XX } }, | |
2987 | { "(bad)", { XX } }, | |
2988 | { "(bad)", { XX } }, | |
85f10a01 | 2989 | /* b0 */ |
4e7d34a6 L |
2990 | { "(bad)", { XX } }, |
2991 | { "(bad)", { XX } }, | |
2992 | { "(bad)", { XX } }, | |
2993 | { "(bad)", { XX } }, | |
2994 | { "(bad)", { XX } }, | |
2995 | { "(bad)", { XX } }, | |
2996 | { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, | |
2997 | { "(bad)", { XX } }, | |
85f10a01 | 2998 | /* b8 */ |
4e7d34a6 L |
2999 | { "(bad)", { XX } }, |
3000 | { "(bad)", { XX } }, | |
3001 | { "(bad)", { XX } }, | |
3002 | { "(bad)", { XX } }, | |
3003 | { "(bad)", { XX } }, | |
3004 | { "(bad)", { XX } }, | |
3005 | { "(bad)", { XX } }, | |
3006 | { "(bad)", { XX } }, | |
85f10a01 | 3007 | /* c0 */ |
4e7d34a6 L |
3008 | { "(bad)", { XX } }, |
3009 | { "(bad)", { XX } }, | |
3010 | { "(bad)", { XX } }, | |
3011 | { "(bad)", { XX } }, | |
3012 | { "(bad)", { XX } }, | |
3013 | { "(bad)", { XX } }, | |
3014 | { "(bad)", { XX } }, | |
3015 | { "(bad)", { XX } }, | |
85f10a01 | 3016 | /* c8 */ |
4e7d34a6 L |
3017 | { "(bad)", { XX } }, |
3018 | { "(bad)", { XX } }, | |
3019 | { "(bad)", { XX } }, | |
3020 | { "(bad)", { XX } }, | |
3021 | { "(bad)", { XX } }, | |
3022 | { "(bad)", { XX } }, | |
3023 | { "(bad)", { XX } }, | |
3024 | { "(bad)", { XX } }, | |
85f10a01 | 3025 | /* d0 */ |
4e7d34a6 L |
3026 | { "(bad)", { XX } }, |
3027 | { "(bad)", { XX } }, | |
3028 | { "(bad)", { XX } }, | |
3029 | { "(bad)", { XX } }, | |
3030 | { "(bad)", { XX } }, | |
3031 | { "(bad)", { XX } }, | |
3032 | { "(bad)", { XX } }, | |
3033 | { "(bad)", { XX } }, | |
85f10a01 | 3034 | /* d8 */ |
4e7d34a6 L |
3035 | { "(bad)", { XX } }, |
3036 | { "(bad)", { XX } }, | |
3037 | { "(bad)", { XX } }, | |
3038 | { "(bad)", { XX } }, | |
3039 | { "(bad)", { XX } }, | |
3040 | { "(bad)", { XX } }, | |
3041 | { "(bad)", { XX } }, | |
3042 | { "(bad)", { XX } }, | |
85f10a01 | 3043 | /* e0 */ |
4e7d34a6 L |
3044 | { "(bad)", { XX } }, |
3045 | { "(bad)", { XX } }, | |
3046 | { "(bad)", { XX } }, | |
3047 | { "(bad)", { XX } }, | |
3048 | { "(bad)", { XX } }, | |
3049 | { "(bad)", { XX } }, | |
3050 | { "(bad)", { XX } }, | |
3051 | { "(bad)", { XX } }, | |
85f10a01 | 3052 | /* e8 */ |
4e7d34a6 L |
3053 | { "(bad)", { XX } }, |
3054 | { "(bad)", { XX } }, | |
3055 | { "(bad)", { XX } }, | |
3056 | { "(bad)", { XX } }, | |
3057 | { "(bad)", { XX } }, | |
3058 | { "(bad)", { XX } }, | |
3059 | { "(bad)", { XX } }, | |
3060 | { "(bad)", { XX } }, | |
85f10a01 | 3061 | /* f0 */ |
4e7d34a6 L |
3062 | { "(bad)", { XX } }, |
3063 | { "(bad)", { XX } }, | |
3064 | { "(bad)", { XX } }, | |
3065 | { "(bad)", { XX } }, | |
3066 | { "(bad)", { XX } }, | |
3067 | { "(bad)", { XX } }, | |
3068 | { "(bad)", { XX } }, | |
3069 | { "(bad)", { XX } }, | |
85f10a01 | 3070 | /* f8 */ |
4e7d34a6 L |
3071 | { "(bad)", { XX } }, |
3072 | { "(bad)", { XX } }, | |
3073 | { "(bad)", { XX } }, | |
3074 | { "(bad)", { XX } }, | |
3075 | { "(bad)", { XX } }, | |
3076 | { "(bad)", { XX } }, | |
3077 | { "(bad)", { XX } }, | |
3078 | { "(bad)", { XX } }, | |
85f10a01 | 3079 | }, |
4e7d34a6 | 3080 | /* THREE_BYTE_0F25 */ |
85f10a01 MM |
3081 | { |
3082 | /* 00 */ | |
4e7d34a6 L |
3083 | { "(bad)", { XX } }, |
3084 | { "(bad)", { XX } }, | |
3085 | { "(bad)", { XX } }, | |
3086 | { "(bad)", { XX } }, | |
3087 | { "(bad)", { XX } }, | |
3088 | { "(bad)", { XX } }, | |
3089 | { "(bad)", { XX } }, | |
3090 | { "(bad)", { XX } }, | |
85f10a01 | 3091 | /* 08 */ |
4e7d34a6 L |
3092 | { "(bad)", { XX } }, |
3093 | { "(bad)", { XX } }, | |
3094 | { "(bad)", { XX } }, | |
3095 | { "(bad)", { XX } }, | |
3096 | { "(bad)", { XX } }, | |
3097 | { "(bad)", { XX } }, | |
3098 | { "(bad)", { XX } }, | |
3099 | { "(bad)", { XX } }, | |
85f10a01 | 3100 | /* 10 */ |
4e7d34a6 L |
3101 | { "(bad)", { XX } }, |
3102 | { "(bad)", { XX } }, | |
3103 | { "(bad)", { XX } }, | |
3104 | { "(bad)", { XX } }, | |
3105 | { "(bad)", { XX } }, | |
3106 | { "(bad)", { XX } }, | |
3107 | { "(bad)", { XX } }, | |
3108 | { "(bad)", { XX } }, | |
85f10a01 | 3109 | /* 18 */ |
4e7d34a6 L |
3110 | { "(bad)", { XX } }, |
3111 | { "(bad)", { XX } }, | |
3112 | { "(bad)", { XX } }, | |
3113 | { "(bad)", { XX } }, | |
3114 | { "(bad)", { XX } }, | |
3115 | { "(bad)", { XX } }, | |
3116 | { "(bad)", { XX } }, | |
3117 | { "(bad)", { XX } }, | |
85f10a01 | 3118 | /* 20 */ |
4e7d34a6 L |
3119 | { "(bad)", { XX } }, |
3120 | { "(bad)", { XX } }, | |
3121 | { "(bad)", { XX } }, | |
3122 | { "(bad)", { XX } }, | |
3123 | { "(bad)", { XX } }, | |
3124 | { "(bad)", { XX } }, | |
3125 | { "(bad)", { XX } }, | |
3126 | { "(bad)", { XX } }, | |
85f10a01 | 3127 | /* 28 */ |
4e7d34a6 L |
3128 | { "(bad)", { XX } }, |
3129 | { "(bad)", { XX } }, | |
3130 | { "(bad)", { XX } }, | |
3131 | { "(bad)", { XX } }, | |
3132 | { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } }, | |
3133 | { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } }, | |
3134 | { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } }, | |
3135 | { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } }, | |
85f10a01 | 3136 | /* 30 */ |
4e7d34a6 L |
3137 | { "(bad)", { XX } }, |
3138 | { "(bad)", { XX } }, | |
3139 | { "(bad)", { XX } }, | |
3140 | { "(bad)", { XX } }, | |
3141 | { "(bad)", { XX } }, | |
3142 | { "(bad)", { XX } }, | |
3143 | { "(bad)", { XX } }, | |
3144 | { "(bad)", { XX } }, | |
85f10a01 | 3145 | /* 38 */ |
4e7d34a6 L |
3146 | { "(bad)", { XX } }, |
3147 | { "(bad)", { XX } }, | |
3148 | { "(bad)", { XX } }, | |
3149 | { "(bad)", { XX } }, | |
3150 | { "(bad)", { XX } }, | |
3151 | { "(bad)", { XX } }, | |
3152 | { "(bad)", { XX } }, | |
3153 | { "(bad)", { XX } }, | |
85f10a01 | 3154 | /* 40 */ |
4e7d34a6 L |
3155 | { "(bad)", { XX } }, |
3156 | { "(bad)", { XX } }, | |
3157 | { "(bad)", { XX } }, | |
3158 | { "(bad)", { XX } }, | |
3159 | { "(bad)", { XX } }, | |
3160 | { "(bad)", { XX } }, | |
3161 | { "(bad)", { XX } }, | |
3162 | { "(bad)", { XX } }, | |
85f10a01 | 3163 | /* 48 */ |
4e7d34a6 L |
3164 | { "(bad)", { XX } }, |
3165 | { "(bad)", { XX } }, | |
3166 | { "(bad)", { XX } }, | |
3167 | { "(bad)", { XX } }, | |
3168 | { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3169 | { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3170 | { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3171 | { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
85f10a01 | 3172 | /* 50 */ |
4e7d34a6 L |
3173 | { "(bad)", { XX } }, |
3174 | { "(bad)", { XX } }, | |
3175 | { "(bad)", { XX } }, | |
3176 | { "(bad)", { XX } }, | |
3177 | { "(bad)", { XX } }, | |
3178 | { "(bad)", { XX } }, | |
3179 | { "(bad)", { XX } }, | |
3180 | { "(bad)", { XX } }, | |
85f10a01 | 3181 | /* 58 */ |
4e7d34a6 L |
3182 | { "(bad)", { XX } }, |
3183 | { "(bad)", { XX } }, | |
3184 | { "(bad)", { XX } }, | |
3185 | { "(bad)", { XX } }, | |
3186 | { "(bad)", { XX } }, | |
3187 | { "(bad)", { XX } }, | |
3188 | { "(bad)", { XX } }, | |
3189 | { "(bad)", { XX } }, | |
85f10a01 | 3190 | /* 60 */ |
4e7d34a6 L |
3191 | { "(bad)", { XX } }, |
3192 | { "(bad)", { XX } }, | |
3193 | { "(bad)", { XX } }, | |
3194 | { "(bad)", { XX } }, | |
3195 | { "(bad)", { XX } }, | |
3196 | { "(bad)", { XX } }, | |
3197 | { "(bad)", { XX } }, | |
3198 | { "(bad)", { XX } }, | |
85f10a01 | 3199 | /* 68 */ |
4e7d34a6 L |
3200 | { "(bad)", { XX } }, |
3201 | { "(bad)", { XX } }, | |
3202 | { "(bad)", { XX } }, | |
3203 | { "(bad)", { XX } }, | |
3204 | { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3205 | { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3206 | { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
3207 | { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } }, | |
85f10a01 | 3208 | /* 70 */ |
4e7d34a6 L |
3209 | { "(bad)", { XX } }, |
3210 | { "(bad)", { XX } }, | |
3211 | { "(bad)", { XX } }, | |
3212 | { "(bad)", { XX } }, | |
3213 | { "(bad)", { XX } }, | |
3214 | { "(bad)", { XX } }, | |
3215 | { "(bad)", { XX } }, | |
3216 | { "(bad)", { XX } }, | |
85f10a01 | 3217 | /* 78 */ |
4e7d34a6 L |
3218 | { "(bad)", { XX } }, |
3219 | { "(bad)", { XX } }, | |
3220 | { "(bad)", { XX } }, | |
3221 | { "(bad)", { XX } }, | |
3222 | { "(bad)", { XX } }, | |
3223 | { "(bad)", { XX } }, | |
3224 | { "(bad)", { XX } }, | |
3225 | { "(bad)", { XX } }, | |
85f10a01 | 3226 | /* 80 */ |
4e7d34a6 L |
3227 | { "(bad)", { XX } }, |
3228 | { "(bad)", { XX } }, | |
3229 | { "(bad)", { XX } }, | |
3230 | { "(bad)", { XX } }, | |
3231 | { "(bad)", { XX } }, | |
3232 | { "(bad)", { XX } }, | |
3233 | { "(bad)", { XX } }, | |
3234 | { "(bad)", { XX } }, | |
3235 | /* 88 */ | |
3236 | { "(bad)", { XX } }, | |
3237 | { "(bad)", { XX } }, | |
3238 | { "(bad)", { XX } }, | |
3239 | { "(bad)", { XX } }, | |
3240 | { "(bad)", { XX } }, | |
3241 | { "(bad)", { XX } }, | |
3242 | { "(bad)", { XX } }, | |
3243 | { "(bad)", { XX } }, | |
3244 | /* 90 */ | |
3245 | { "(bad)", { XX } }, | |
3246 | { "(bad)", { XX } }, | |
3247 | { "(bad)", { XX } }, | |
3248 | { "(bad)", { XX } }, | |
3249 | { "(bad)", { XX } }, | |
3250 | { "(bad)", { XX } }, | |
3251 | { "(bad)", { XX } }, | |
3252 | { "(bad)", { XX } }, | |
3253 | /* 98 */ | |
3254 | { "(bad)", { XX } }, | |
3255 | { "(bad)", { XX } }, | |
3256 | { "(bad)", { XX } }, | |
3257 | { "(bad)", { XX } }, | |
3258 | { "(bad)", { XX } }, | |
3259 | { "(bad)", { XX } }, | |
3260 | { "(bad)", { XX } }, | |
3261 | { "(bad)", { XX } }, | |
3262 | /* a0 */ | |
3263 | { "(bad)", { XX } }, | |
3264 | { "(bad)", { XX } }, | |
3265 | { "(bad)", { XX } }, | |
3266 | { "(bad)", { XX } }, | |
3267 | { "(bad)", { XX } }, | |
3268 | { "(bad)", { XX } }, | |
3269 | { "(bad)", { XX } }, | |
3270 | { "(bad)", { XX } }, | |
3271 | /* a8 */ | |
3272 | { "(bad)", { XX } }, | |
3273 | { "(bad)", { XX } }, | |
3274 | { "(bad)", { XX } }, | |
3275 | { "(bad)", { XX } }, | |
3276 | { "(bad)", { XX } }, | |
3277 | { "(bad)", { XX } }, | |
3278 | { "(bad)", { XX } }, | |
3279 | { "(bad)", { XX } }, | |
3280 | /* b0 */ | |
3281 | { "(bad)", { XX } }, | |
3282 | { "(bad)", { XX } }, | |
3283 | { "(bad)", { XX } }, | |
3284 | { "(bad)", { XX } }, | |
3285 | { "(bad)", { XX } }, | |
3286 | { "(bad)", { XX } }, | |
3287 | { "(bad)", { XX } }, | |
3288 | { "(bad)", { XX } }, | |
3289 | /* b8 */ | |
3290 | { "(bad)", { XX } }, | |
3291 | { "(bad)", { XX } }, | |
3292 | { "(bad)", { XX } }, | |
3293 | { "(bad)", { XX } }, | |
3294 | { "(bad)", { XX } }, | |
3295 | { "(bad)", { XX } }, | |
3296 | { "(bad)", { XX } }, | |
3297 | { "(bad)", { XX } }, | |
3298 | /* c0 */ | |
3299 | { "(bad)", { XX } }, | |
3300 | { "(bad)", { XX } }, | |
3301 | { "(bad)", { XX } }, | |
3302 | { "(bad)", { XX } }, | |
3303 | { "(bad)", { XX } }, | |
3304 | { "(bad)", { XX } }, | |
3305 | { "(bad)", { XX } }, | |
3306 | { "(bad)", { XX } }, | |
3307 | /* c8 */ | |
3308 | { "(bad)", { XX } }, | |
3309 | { "(bad)", { XX } }, | |
3310 | { "(bad)", { XX } }, | |
3311 | { "(bad)", { XX } }, | |
3312 | { "(bad)", { XX } }, | |
3313 | { "(bad)", { XX } }, | |
3314 | { "(bad)", { XX } }, | |
3315 | { "(bad)", { XX } }, | |
3316 | /* d0 */ | |
3317 | { "(bad)", { XX } }, | |
3318 | { "(bad)", { XX } }, | |
3319 | { "(bad)", { XX } }, | |
3320 | { "(bad)", { XX } }, | |
3321 | { "(bad)", { XX } }, | |
3322 | { "(bad)", { XX } }, | |
3323 | { "(bad)", { XX } }, | |
3324 | { "(bad)", { XX } }, | |
3325 | /* d8 */ | |
3326 | { "(bad)", { XX } }, | |
3327 | { "(bad)", { XX } }, | |
3328 | { "(bad)", { XX } }, | |
3329 | { "(bad)", { XX } }, | |
3330 | { "(bad)", { XX } }, | |
3331 | { "(bad)", { XX } }, | |
3332 | { "(bad)", { XX } }, | |
3333 | { "(bad)", { XX } }, | |
3334 | /* e0 */ | |
3335 | { "(bad)", { XX } }, | |
3336 | { "(bad)", { XX } }, | |
3337 | { "(bad)", { XX } }, | |
3338 | { "(bad)", { XX } }, | |
3339 | { "(bad)", { XX } }, | |
3340 | { "(bad)", { XX } }, | |
3341 | { "(bad)", { XX } }, | |
3342 | { "(bad)", { XX } }, | |
3343 | /* e8 */ | |
3344 | { "(bad)", { XX } }, | |
3345 | { "(bad)", { XX } }, | |
3346 | { "(bad)", { XX } }, | |
3347 | { "(bad)", { XX } }, | |
3348 | { "(bad)", { XX } }, | |
3349 | { "(bad)", { XX } }, | |
3350 | { "(bad)", { XX } }, | |
3351 | { "(bad)", { XX } }, | |
3352 | /* f0 */ | |
3353 | { "(bad)", { XX } }, | |
3354 | { "(bad)", { XX } }, | |
3355 | { "(bad)", { XX } }, | |
3356 | { "(bad)", { XX } }, | |
3357 | { "(bad)", { XX } }, | |
3358 | { "(bad)", { XX } }, | |
3359 | { "(bad)", { XX } }, | |
3360 | { "(bad)", { XX } }, | |
3361 | /* f8 */ | |
3362 | { "(bad)", { XX } }, | |
3363 | { "(bad)", { XX } }, | |
3364 | { "(bad)", { XX } }, | |
3365 | { "(bad)", { XX } }, | |
3366 | { "(bad)", { XX } }, | |
3367 | { "(bad)", { XX } }, | |
3368 | { "(bad)", { XX } }, | |
3369 | { "(bad)", { XX } }, | |
3370 | }, | |
3371 | /* THREE_BYTE_0F38 */ | |
3372 | { | |
3373 | /* 00 */ | |
d5d7db8e L |
3374 | { "pshufb", { MX, EM } }, |
3375 | { "phaddw", { MX, EM } }, | |
3376 | { "phaddd", { MX, EM } }, | |
3377 | { "phaddsw", { MX, EM } }, | |
3378 | { "pmaddubsw", { MX, EM } }, | |
3379 | { "phsubw", { MX, EM } }, | |
3380 | { "phsubd", { MX, EM } }, | |
3381 | { "phsubsw", { MX, EM } }, | |
4e7d34a6 | 3382 | /* 08 */ |
d5d7db8e L |
3383 | { "psignb", { MX, EM } }, |
3384 | { "psignw", { MX, EM } }, | |
3385 | { "psignd", { MX, EM } }, | |
3386 | { "pmulhrsw", { MX, EM } }, | |
3387 | { "(bad)", { XX } }, | |
3388 | { "(bad)", { XX } }, | |
3389 | { "(bad)", { XX } }, | |
3390 | { "(bad)", { XX } }, | |
4e7d34a6 | 3391 | /* 10 */ |
1ceb70f8 | 3392 | { PREFIX_TABLE (PREFIX_0F3810) }, |
d5d7db8e L |
3393 | { "(bad)", { XX } }, |
3394 | { "(bad)", { XX } }, | |
3395 | { "(bad)", { XX } }, | |
1ceb70f8 L |
3396 | { PREFIX_TABLE (PREFIX_0F3814) }, |
3397 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
d5d7db8e | 3398 | { "(bad)", { XX } }, |
1ceb70f8 | 3399 | { PREFIX_TABLE (PREFIX_0F3817) }, |
4e7d34a6 | 3400 | /* 18 */ |
d5d7db8e L |
3401 | { "(bad)", { XX } }, |
3402 | { "(bad)", { XX } }, | |
3403 | { "(bad)", { XX } }, | |
3404 | { "(bad)", { XX } }, | |
3405 | { "pabsb", { MX, EM } }, | |
3406 | { "pabsw", { MX, EM } }, | |
3407 | { "pabsd", { MX, EM } }, | |
3408 | { "(bad)", { XX } }, | |
4e7d34a6 | 3409 | /* 20 */ |
1ceb70f8 L |
3410 | { PREFIX_TABLE (PREFIX_0F3820) }, |
3411 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
3412 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
3413 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
3414 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
3415 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
d5d7db8e L |
3416 | { "(bad)", { XX } }, |
3417 | { "(bad)", { XX } }, | |
4e7d34a6 | 3418 | /* 28 */ |
1ceb70f8 L |
3419 | { PREFIX_TABLE (PREFIX_0F3828) }, |
3420 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
3421 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
3422 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
d5d7db8e L |
3423 | { "(bad)", { XX } }, |
3424 | { "(bad)", { XX } }, | |
3425 | { "(bad)", { XX } }, | |
3426 | { "(bad)", { XX } }, | |
4e7d34a6 | 3427 | /* 30 */ |
1ceb70f8 L |
3428 | { PREFIX_TABLE (PREFIX_0F3830) }, |
3429 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
3430 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
3431 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
3432 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
3433 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
d5d7db8e | 3434 | { "(bad)", { XX } }, |
1ceb70f8 | 3435 | { PREFIX_TABLE (PREFIX_0F3837) }, |
4e7d34a6 | 3436 | /* 38 */ |
1ceb70f8 L |
3437 | { PREFIX_TABLE (PREFIX_0F3838) }, |
3438 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
3439 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
3440 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
3441 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
3442 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
3443 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
3444 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
4e7d34a6 | 3445 | /* 40 */ |
1ceb70f8 L |
3446 | { PREFIX_TABLE (PREFIX_0F3840) }, |
3447 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
d5d7db8e L |
3448 | { "(bad)", { XX } }, |
3449 | { "(bad)", { XX } }, | |
3450 | { "(bad)", { XX } }, | |
3451 | { "(bad)", { XX } }, | |
3452 | { "(bad)", { XX } }, | |
3453 | { "(bad)", { XX } }, | |
4e7d34a6 | 3454 | /* 48 */ |
d5d7db8e L |
3455 | { "(bad)", { XX } }, |
3456 | { "(bad)", { XX } }, | |
3457 | { "(bad)", { XX } }, | |
3458 | { "(bad)", { XX } }, | |
3459 | { "(bad)", { XX } }, | |
3460 | { "(bad)", { XX } }, | |
3461 | { "(bad)", { XX } }, | |
3462 | { "(bad)", { XX } }, | |
4e7d34a6 | 3463 | /* 50 */ |
d5d7db8e L |
3464 | { "(bad)", { XX } }, |
3465 | { "(bad)", { XX } }, | |
3466 | { "(bad)", { XX } }, | |
3467 | { "(bad)", { XX } }, | |
3468 | { "(bad)", { XX } }, | |
3469 | { "(bad)", { XX } }, | |
3470 | { "(bad)", { XX } }, | |
3471 | { "(bad)", { XX } }, | |
4e7d34a6 | 3472 | /* 58 */ |
d5d7db8e L |
3473 | { "(bad)", { XX } }, |
3474 | { "(bad)", { XX } }, | |
3475 | { "(bad)", { XX } }, | |
3476 | { "(bad)", { XX } }, | |
3477 | { "(bad)", { XX } }, | |
3478 | { "(bad)", { XX } }, | |
3479 | { "(bad)", { XX } }, | |
3480 | { "(bad)", { XX } }, | |
4e7d34a6 | 3481 | /* 60 */ |
d5d7db8e L |
3482 | { "(bad)", { XX } }, |
3483 | { "(bad)", { XX } }, | |
3484 | { "(bad)", { XX } }, | |
3485 | { "(bad)", { XX } }, | |
3486 | { "(bad)", { XX } }, | |
3487 | { "(bad)", { XX } }, | |
3488 | { "(bad)", { XX } }, | |
3489 | { "(bad)", { XX } }, | |
4e7d34a6 | 3490 | /* 68 */ |
d5d7db8e L |
3491 | { "(bad)", { XX } }, |
3492 | { "(bad)", { XX } }, | |
3493 | { "(bad)", { XX } }, | |
3494 | { "(bad)", { XX } }, | |
3495 | { "(bad)", { XX } }, | |
3496 | { "(bad)", { XX } }, | |
3497 | { "(bad)", { XX } }, | |
3498 | { "(bad)", { XX } }, | |
4e7d34a6 | 3499 | /* 70 */ |
d5d7db8e L |
3500 | { "(bad)", { XX } }, |
3501 | { "(bad)", { XX } }, | |
3502 | { "(bad)", { XX } }, | |
3503 | { "(bad)", { XX } }, | |
3504 | { "(bad)", { XX } }, | |
3505 | { "(bad)", { XX } }, | |
3506 | { "(bad)", { XX } }, | |
3507 | { "(bad)", { XX } }, | |
4e7d34a6 | 3508 | /* 78 */ |
d5d7db8e L |
3509 | { "(bad)", { XX } }, |
3510 | { "(bad)", { XX } }, | |
3511 | { "(bad)", { XX } }, | |
3512 | { "(bad)", { XX } }, | |
3513 | { "(bad)", { XX } }, | |
3514 | { "(bad)", { XX } }, | |
3515 | { "(bad)", { XX } }, | |
3516 | { "(bad)", { XX } }, | |
4e7d34a6 | 3517 | /* 80 */ |
d5d7db8e L |
3518 | { "(bad)", { XX } }, |
3519 | { "(bad)", { XX } }, | |
3520 | { "(bad)", { XX } }, | |
3521 | { "(bad)", { XX } }, | |
3522 | { "(bad)", { XX } }, | |
3523 | { "(bad)", { XX } }, | |
3524 | { "(bad)", { XX } }, | |
3525 | { "(bad)", { XX } }, | |
4e7d34a6 | 3526 | /* 88 */ |
d5d7db8e L |
3527 | { "(bad)", { XX } }, |
3528 | { "(bad)", { XX } }, | |
3529 | { "(bad)", { XX } }, | |
3530 | { "(bad)", { XX } }, | |
3531 | { "(bad)", { XX } }, | |
3532 | { "(bad)", { XX } }, | |
3533 | { "(bad)", { XX } }, | |
3534 | { "(bad)", { XX } }, | |
4e7d34a6 | 3535 | /* 90 */ |
d5d7db8e L |
3536 | { "(bad)", { XX } }, |
3537 | { "(bad)", { XX } }, | |
3538 | { "(bad)", { XX } }, | |
3539 | { "(bad)", { XX } }, | |
3540 | { "(bad)", { XX } }, | |
3541 | { "(bad)", { XX } }, | |
3542 | { "(bad)", { XX } }, | |
3543 | { "(bad)", { XX } }, | |
4e7d34a6 | 3544 | /* 98 */ |
d5d7db8e L |
3545 | { "(bad)", { XX } }, |
3546 | { "(bad)", { XX } }, | |
3547 | { "(bad)", { XX } }, | |
3548 | { "(bad)", { XX } }, | |
3549 | { "(bad)", { XX } }, | |
3550 | { "(bad)", { XX } }, | |
3551 | { "(bad)", { XX } }, | |
3552 | { "(bad)", { XX } }, | |
4e7d34a6 | 3553 | /* a0 */ |
d5d7db8e L |
3554 | { "(bad)", { XX } }, |
3555 | { "(bad)", { XX } }, | |
3556 | { "(bad)", { XX } }, | |
3557 | { "(bad)", { XX } }, | |
3558 | { "(bad)", { XX } }, | |
3559 | { "(bad)", { XX } }, | |
3560 | { "(bad)", { XX } }, | |
3561 | { "(bad)", { XX } }, | |
4e7d34a6 | 3562 | /* a8 */ |
d5d7db8e L |
3563 | { "(bad)", { XX } }, |
3564 | { "(bad)", { XX } }, | |
3565 | { "(bad)", { XX } }, | |
3566 | { "(bad)", { XX } }, | |
3567 | { "(bad)", { XX } }, | |
3568 | { "(bad)", { XX } }, | |
3569 | { "(bad)", { XX } }, | |
3570 | { "(bad)", { XX } }, | |
3571 | /* b0 */ | |
3572 | { "(bad)", { XX } }, | |
3573 | { "(bad)", { XX } }, | |
3574 | { "(bad)", { XX } }, | |
3575 | { "(bad)", { XX } }, | |
3576 | { "(bad)", { XX } }, | |
3577 | { "(bad)", { XX } }, | |
3578 | { "(bad)", { XX } }, | |
3579 | { "(bad)", { XX } }, | |
85f10a01 | 3580 | /* b8 */ |
d5d7db8e L |
3581 | { "(bad)", { XX } }, |
3582 | { "(bad)", { XX } }, | |
3583 | { "(bad)", { XX } }, | |
3584 | { "(bad)", { XX } }, | |
3585 | { "(bad)", { XX } }, | |
3586 | { "(bad)", { XX } }, | |
3587 | { "(bad)", { XX } }, | |
3588 | { "(bad)", { XX } }, | |
85f10a01 | 3589 | /* c0 */ |
d5d7db8e L |
3590 | { "(bad)", { XX } }, |
3591 | { "(bad)", { XX } }, | |
3592 | { "(bad)", { XX } }, | |
3593 | { "(bad)", { XX } }, | |
3594 | { "(bad)", { XX } }, | |
3595 | { "(bad)", { XX } }, | |
3596 | { "(bad)", { XX } }, | |
3597 | { "(bad)", { XX } }, | |
85f10a01 | 3598 | /* c8 */ |
d5d7db8e L |
3599 | { "(bad)", { XX } }, |
3600 | { "(bad)", { XX } }, | |
3601 | { "(bad)", { XX } }, | |
3602 | { "(bad)", { XX } }, | |
3603 | { "(bad)", { XX } }, | |
3604 | { "(bad)", { XX } }, | |
3605 | { "(bad)", { XX } }, | |
3606 | { "(bad)", { XX } }, | |
85f10a01 | 3607 | /* d0 */ |
d5d7db8e L |
3608 | { "(bad)", { XX } }, |
3609 | { "(bad)", { XX } }, | |
3610 | { "(bad)", { XX } }, | |
3611 | { "(bad)", { XX } }, | |
3612 | { "(bad)", { XX } }, | |
3613 | { "(bad)", { XX } }, | |
3614 | { "(bad)", { XX } }, | |
3615 | { "(bad)", { XX } }, | |
85f10a01 | 3616 | /* d8 */ |
d5d7db8e L |
3617 | { "(bad)", { XX } }, |
3618 | { "(bad)", { XX } }, | |
3619 | { "(bad)", { XX } }, | |
3620 | { "(bad)", { XX } }, | |
3621 | { "(bad)", { XX } }, | |
3622 | { "(bad)", { XX } }, | |
3623 | { "(bad)", { XX } }, | |
3624 | { "(bad)", { XX } }, | |
85f10a01 | 3625 | /* e0 */ |
d5d7db8e L |
3626 | { "(bad)", { XX } }, |
3627 | { "(bad)", { XX } }, | |
3628 | { "(bad)", { XX } }, | |
3629 | { "(bad)", { XX } }, | |
3630 | { "(bad)", { XX } }, | |
3631 | { "(bad)", { XX } }, | |
3632 | { "(bad)", { XX } }, | |
3633 | { "(bad)", { XX } }, | |
85f10a01 | 3634 | /* e8 */ |
d5d7db8e L |
3635 | { "(bad)", { XX } }, |
3636 | { "(bad)", { XX } }, | |
3637 | { "(bad)", { XX } }, | |
3638 | { "(bad)", { XX } }, | |
3639 | { "(bad)", { XX } }, | |
3640 | { "(bad)", { XX } }, | |
3641 | { "(bad)", { XX } }, | |
3642 | { "(bad)", { XX } }, | |
85f10a01 | 3643 | /* f0 */ |
1ceb70f8 L |
3644 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
3645 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
d5d7db8e L |
3646 | { "(bad)", { XX } }, |
3647 | { "(bad)", { XX } }, | |
3648 | { "(bad)", { XX } }, | |
3649 | { "(bad)", { XX } }, | |
3650 | { "(bad)", { XX } }, | |
3651 | { "(bad)", { XX } }, | |
85f10a01 | 3652 | /* f8 */ |
d5d7db8e L |
3653 | { "(bad)", { XX } }, |
3654 | { "(bad)", { XX } }, | |
3655 | { "(bad)", { XX } }, | |
3656 | { "(bad)", { XX } }, | |
3657 | { "(bad)", { XX } }, | |
3658 | { "(bad)", { XX } }, | |
3659 | { "(bad)", { XX } }, | |
3660 | { "(bad)", { XX } }, | |
85f10a01 | 3661 | }, |
4e7d34a6 | 3662 | /* THREE_BYTE_0F3A */ |
85f10a01 MM |
3663 | { |
3664 | /* 00 */ | |
d5d7db8e L |
3665 | { "(bad)", { XX } }, |
3666 | { "(bad)", { XX } }, | |
3667 | { "(bad)", { XX } }, | |
3668 | { "(bad)", { XX } }, | |
3669 | { "(bad)", { XX } }, | |
3670 | { "(bad)", { XX } }, | |
3671 | { "(bad)", { XX } }, | |
3672 | { "(bad)", { XX } }, | |
85f10a01 | 3673 | /* 08 */ |
1ceb70f8 L |
3674 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
3675 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
3676 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
3677 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
3678 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
3679 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
3680 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
d5d7db8e | 3681 | { "palignr", { MX, EM, Ib } }, |
85f10a01 | 3682 | /* 10 */ |
d5d7db8e L |
3683 | { "(bad)", { XX } }, |
3684 | { "(bad)", { XX } }, | |
3685 | { "(bad)", { XX } }, | |
3686 | { "(bad)", { XX } }, | |
1ceb70f8 L |
3687 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
3688 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
3689 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
3690 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
85f10a01 | 3691 | /* 18 */ |
d5d7db8e L |
3692 | { "(bad)", { XX } }, |
3693 | { "(bad)", { XX } }, | |
3694 | { "(bad)", { XX } }, | |
3695 | { "(bad)", { XX } }, | |
3696 | { "(bad)", { XX } }, | |
3697 | { "(bad)", { XX } }, | |
3698 | { "(bad)", { XX } }, | |
3699 | { "(bad)", { XX } }, | |
85f10a01 | 3700 | /* 20 */ |
1ceb70f8 L |
3701 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
3702 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
3703 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
d5d7db8e L |
3704 | { "(bad)", { XX } }, |
3705 | { "(bad)", { XX } }, | |
3706 | { "(bad)", { XX } }, | |
3707 | { "(bad)", { XX } }, | |
3708 | { "(bad)", { XX } }, | |
85f10a01 | 3709 | /* 28 */ |
d5d7db8e L |
3710 | { "(bad)", { XX } }, |
3711 | { "(bad)", { XX } }, | |
3712 | { "(bad)", { XX } }, | |
3713 | { "(bad)", { XX } }, | |
3714 | { "(bad)", { XX } }, | |
3715 | { "(bad)", { XX } }, | |
3716 | { "(bad)", { XX } }, | |
3717 | { "(bad)", { XX } }, | |
85f10a01 | 3718 | /* 30 */ |
d5d7db8e L |
3719 | { "(bad)", { XX } }, |
3720 | { "(bad)", { XX } }, | |
3721 | { "(bad)", { XX } }, | |
3722 | { "(bad)", { XX } }, | |
3723 | { "(bad)", { XX } }, | |
3724 | { "(bad)", { XX } }, | |
3725 | { "(bad)", { XX } }, | |
3726 | { "(bad)", { XX } }, | |
4e7d34a6 | 3727 | /* 38 */ |
d5d7db8e L |
3728 | { "(bad)", { XX } }, |
3729 | { "(bad)", { XX } }, | |
3730 | { "(bad)", { XX } }, | |
3731 | { "(bad)", { XX } }, | |
3732 | { "(bad)", { XX } }, | |
3733 | { "(bad)", { XX } }, | |
3734 | { "(bad)", { XX } }, | |
3735 | { "(bad)", { XX } }, | |
3736 | /* 40 */ | |
3737 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
3738 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
3739 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
3740 | { "(bad)", { XX } }, | |
3741 | { "(bad)", { XX } }, | |
3742 | { "(bad)", { XX } }, | |
3743 | { "(bad)", { XX } }, | |
3744 | { "(bad)", { XX } }, | |
85f10a01 | 3745 | /* 48 */ |
85f10a01 MM |
3746 | { "(bad)", { XX } }, |
3747 | { "(bad)", { XX } }, | |
3748 | { "(bad)", { XX } }, | |
3749 | { "(bad)", { XX } }, | |
3750 | { "(bad)", { XX } }, | |
3751 | { "(bad)", { XX } }, | |
3752 | { "(bad)", { XX } }, | |
3753 | { "(bad)", { XX } }, | |
d5d7db8e | 3754 | /* 50 */ |
85f10a01 MM |
3755 | { "(bad)", { XX } }, |
3756 | { "(bad)", { XX } }, | |
3757 | { "(bad)", { XX } }, | |
3758 | { "(bad)", { XX } }, | |
3759 | { "(bad)", { XX } }, | |
3760 | { "(bad)", { XX } }, | |
3761 | { "(bad)", { XX } }, | |
3762 | { "(bad)", { XX } }, | |
d5d7db8e | 3763 | /* 58 */ |
85f10a01 MM |
3764 | { "(bad)", { XX } }, |
3765 | { "(bad)", { XX } }, | |
3766 | { "(bad)", { XX } }, | |
3767 | { "(bad)", { XX } }, | |
85f10a01 MM |
3768 | { "(bad)", { XX } }, |
3769 | { "(bad)", { XX } }, | |
3770 | { "(bad)", { XX } }, | |
3771 | { "(bad)", { XX } }, | |
d5d7db8e L |
3772 | /* 60 */ |
3773 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
3774 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
3775 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
3776 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
85f10a01 MM |
3777 | { "(bad)", { XX } }, |
3778 | { "(bad)", { XX } }, | |
3779 | { "(bad)", { XX } }, | |
3780 | { "(bad)", { XX } }, | |
d5d7db8e | 3781 | /* 68 */ |
85f10a01 MM |
3782 | { "(bad)", { XX } }, |
3783 | { "(bad)", { XX } }, | |
3784 | { "(bad)", { XX } }, | |
3785 | { "(bad)", { XX } }, | |
3786 | { "(bad)", { XX } }, | |
3787 | { "(bad)", { XX } }, | |
3788 | { "(bad)", { XX } }, | |
85f10a01 | 3789 | { "(bad)", { XX } }, |
d5d7db8e | 3790 | /* 70 */ |
85f10a01 MM |
3791 | { "(bad)", { XX } }, |
3792 | { "(bad)", { XX } }, | |
3793 | { "(bad)", { XX } }, | |
d5d7db8e L |
3794 | { "(bad)", { XX } }, |
3795 | { "(bad)", { XX } }, | |
3796 | { "(bad)", { XX } }, | |
3797 | { "(bad)", { XX } }, | |
3798 | { "(bad)", { XX } }, | |
3799 | /* 78 */ | |
3800 | { "(bad)", { XX } }, | |
3801 | { "(bad)", { XX } }, | |
3802 | { "(bad)", { XX } }, | |
3803 | { "(bad)", { XX } }, | |
3804 | { "(bad)", { XX } }, | |
3805 | { "(bad)", { XX } }, | |
3806 | { "(bad)", { XX } }, | |
3807 | { "(bad)", { XX } }, | |
3808 | /* 80 */ | |
3809 | { "(bad)", { XX } }, | |
3810 | { "(bad)", { XX } }, | |
3811 | { "(bad)", { XX } }, | |
3812 | { "(bad)", { XX } }, | |
3813 | { "(bad)", { XX } }, | |
3814 | { "(bad)", { XX } }, | |
3815 | { "(bad)", { XX } }, | |
3816 | { "(bad)", { XX } }, | |
3817 | /* 88 */ | |
3818 | { "(bad)", { XX } }, | |
3819 | { "(bad)", { XX } }, | |
3820 | { "(bad)", { XX } }, | |
3821 | { "(bad)", { XX } }, | |
3822 | { "(bad)", { XX } }, | |
3823 | { "(bad)", { XX } }, | |
3824 | { "(bad)", { XX } }, | |
3825 | { "(bad)", { XX } }, | |
3826 | /* 90 */ | |
3827 | { "(bad)", { XX } }, | |
3828 | { "(bad)", { XX } }, | |
3829 | { "(bad)", { XX } }, | |
3830 | { "(bad)", { XX } }, | |
3831 | { "(bad)", { XX } }, | |
3832 | { "(bad)", { XX } }, | |
3833 | { "(bad)", { XX } }, | |
3834 | { "(bad)", { XX } }, | |
3835 | /* 98 */ | |
3836 | { "(bad)", { XX } }, | |
3837 | { "(bad)", { XX } }, | |
3838 | { "(bad)", { XX } }, | |
3839 | { "(bad)", { XX } }, | |
3840 | { "(bad)", { XX } }, | |
3841 | { "(bad)", { XX } }, | |
3842 | { "(bad)", { XX } }, | |
3843 | { "(bad)", { XX } }, | |
3844 | /* a0 */ | |
3845 | { "(bad)", { XX } }, | |
3846 | { "(bad)", { XX } }, | |
3847 | { "(bad)", { XX } }, | |
3848 | { "(bad)", { XX } }, | |
3849 | { "(bad)", { XX } }, | |
3850 | { "(bad)", { XX } }, | |
3851 | { "(bad)", { XX } }, | |
3852 | { "(bad)", { XX } }, | |
3853 | /* a8 */ | |
3854 | { "(bad)", { XX } }, | |
3855 | { "(bad)", { XX } }, | |
3856 | { "(bad)", { XX } }, | |
3857 | { "(bad)", { XX } }, | |
3858 | { "(bad)", { XX } }, | |
3859 | { "(bad)", { XX } }, | |
3860 | { "(bad)", { XX } }, | |
3861 | { "(bad)", { XX } }, | |
3862 | /* b0 */ | |
3863 | { "(bad)", { XX } }, | |
3864 | { "(bad)", { XX } }, | |
3865 | { "(bad)", { XX } }, | |
3866 | { "(bad)", { XX } }, | |
3867 | { "(bad)", { XX } }, | |
3868 | { "(bad)", { XX } }, | |
3869 | { "(bad)", { XX } }, | |
3870 | { "(bad)", { XX } }, | |
3871 | /* b8 */ | |
3872 | { "(bad)", { XX } }, | |
3873 | { "(bad)", { XX } }, | |
3874 | { "(bad)", { XX } }, | |
3875 | { "(bad)", { XX } }, | |
3876 | { "(bad)", { XX } }, | |
3877 | { "(bad)", { XX } }, | |
3878 | { "(bad)", { XX } }, | |
3879 | { "(bad)", { XX } }, | |
3880 | /* c0 */ | |
3881 | { "(bad)", { XX } }, | |
3882 | { "(bad)", { XX } }, | |
3883 | { "(bad)", { XX } }, | |
3884 | { "(bad)", { XX } }, | |
3885 | { "(bad)", { XX } }, | |
3886 | { "(bad)", { XX } }, | |
3887 | { "(bad)", { XX } }, | |
3888 | { "(bad)", { XX } }, | |
3889 | /* c8 */ | |
3890 | { "(bad)", { XX } }, | |
3891 | { "(bad)", { XX } }, | |
3892 | { "(bad)", { XX } }, | |
3893 | { "(bad)", { XX } }, | |
3894 | { "(bad)", { XX } }, | |
3895 | { "(bad)", { XX } }, | |
3896 | { "(bad)", { XX } }, | |
3897 | { "(bad)", { XX } }, | |
3898 | /* d0 */ | |
3899 | { "(bad)", { XX } }, | |
3900 | { "(bad)", { XX } }, | |
3901 | { "(bad)", { XX } }, | |
3902 | { "(bad)", { XX } }, | |
3903 | { "(bad)", { XX } }, | |
3904 | { "(bad)", { XX } }, | |
3905 | { "(bad)", { XX } }, | |
3906 | { "(bad)", { XX } }, | |
3907 | /* d8 */ | |
3908 | { "(bad)", { XX } }, | |
3909 | { "(bad)", { XX } }, | |
3910 | { "(bad)", { XX } }, | |
3911 | { "(bad)", { XX } }, | |
3912 | { "(bad)", { XX } }, | |
3913 | { "(bad)", { XX } }, | |
3914 | { "(bad)", { XX } }, | |
3915 | { "(bad)", { XX } }, | |
3916 | /* e0 */ | |
3917 | { "(bad)", { XX } }, | |
3918 | { "(bad)", { XX } }, | |
3919 | { "(bad)", { XX } }, | |
3920 | { "(bad)", { XX } }, | |
3921 | { "(bad)", { XX } }, | |
3922 | { "(bad)", { XX } }, | |
3923 | { "(bad)", { XX } }, | |
3924 | { "(bad)", { XX } }, | |
3925 | /* e8 */ | |
3926 | { "(bad)", { XX } }, | |
3927 | { "(bad)", { XX } }, | |
3928 | { "(bad)", { XX } }, | |
3929 | { "(bad)", { XX } }, | |
3930 | { "(bad)", { XX } }, | |
3931 | { "(bad)", { XX } }, | |
3932 | { "(bad)", { XX } }, | |
3933 | { "(bad)", { XX } }, | |
3934 | /* f0 */ | |
3935 | { "(bad)", { XX } }, | |
3936 | { "(bad)", { XX } }, | |
3937 | { "(bad)", { XX } }, | |
3938 | { "(bad)", { XX } }, | |
3939 | { "(bad)", { XX } }, | |
3940 | { "(bad)", { XX } }, | |
3941 | { "(bad)", { XX } }, | |
3942 | { "(bad)", { XX } }, | |
3943 | /* f8 */ | |
3944 | { "(bad)", { XX } }, | |
3945 | { "(bad)", { XX } }, | |
3946 | { "(bad)", { XX } }, | |
3947 | { "(bad)", { XX } }, | |
3948 | { "(bad)", { XX } }, | |
3949 | { "(bad)", { XX } }, | |
3950 | { "(bad)", { XX } }, | |
3951 | { "(bad)", { XX } }, | |
3952 | }, | |
3953 | /* THREE_BYTE_0F7A */ | |
3954 | { | |
3955 | /* 00 */ | |
3956 | { "(bad)", { XX } }, | |
3957 | { "(bad)", { XX } }, | |
3958 | { "(bad)", { XX } }, | |
3959 | { "(bad)", { XX } }, | |
3960 | { "(bad)", { XX } }, | |
3961 | { "(bad)", { XX } }, | |
3962 | { "(bad)", { XX } }, | |
3963 | { "(bad)", { XX } }, | |
3964 | /* 08 */ | |
3965 | { "(bad)", { XX } }, | |
3966 | { "(bad)", { XX } }, | |
3967 | { "(bad)", { XX } }, | |
3968 | { "(bad)", { XX } }, | |
3969 | { "(bad)", { XX } }, | |
3970 | { "(bad)", { XX } }, | |
3971 | { "(bad)", { XX } }, | |
3972 | { "(bad)", { XX } }, | |
3973 | /* 10 */ | |
3974 | { "frczps", { XM, EXq } }, | |
3975 | { "frczpd", { XM, EXq } }, | |
3976 | { "frczss", { XM, EXq } }, | |
3977 | { "frczsd", { XM, EXq } }, | |
3978 | { "(bad)", { XX } }, | |
3979 | { "(bad)", { XX } }, | |
3980 | { "(bad)", { XX } }, | |
3981 | { "(bad)", { XX } }, | |
3982 | /* 18 */ | |
3983 | { "(bad)", { XX } }, | |
3984 | { "(bad)", { XX } }, | |
3985 | { "(bad)", { XX } }, | |
3986 | { "(bad)", { XX } }, | |
3987 | { "(bad)", { XX } }, | |
3988 | { "(bad)", { XX } }, | |
3989 | { "(bad)", { XX } }, | |
3990 | { "(bad)", { XX } }, | |
3991 | /* 20 */ | |
3992 | { "ptest", { XX } }, | |
3993 | { "(bad)", { XX } }, | |
3994 | { "(bad)", { XX } }, | |
3995 | { "(bad)", { XX } }, | |
3996 | { "(bad)", { XX } }, | |
3997 | { "(bad)", { XX } }, | |
3998 | { "(bad)", { XX } }, | |
3999 | { "(bad)", { XX } }, | |
4000 | /* 28 */ | |
4001 | { "(bad)", { XX } }, | |
4002 | { "(bad)", { XX } }, | |
4003 | { "(bad)", { XX } }, | |
4004 | { "(bad)", { XX } }, | |
4005 | { "(bad)", { XX } }, | |
4006 | { "(bad)", { XX } }, | |
4007 | { "(bad)", { XX } }, | |
4008 | { "(bad)", { XX } }, | |
4009 | /* 30 */ | |
85f10a01 MM |
4010 | { "cvtph2ps", { XM, EXd } }, |
4011 | { "cvtps2ph", { EXd, XM } }, | |
d5d7db8e L |
4012 | { "(bad)", { XX } }, |
4013 | { "(bad)", { XX } }, | |
4014 | { "(bad)", { XX } }, | |
4015 | { "(bad)", { XX } }, | |
4016 | { "(bad)", { XX } }, | |
4017 | { "(bad)", { XX } }, | |
85f10a01 | 4018 | /* 38 */ |
d5d7db8e L |
4019 | { "(bad)", { XX } }, |
4020 | { "(bad)", { XX } }, | |
4021 | { "(bad)", { XX } }, | |
4022 | { "(bad)", { XX } }, | |
4023 | { "(bad)", { XX } }, | |
4024 | { "(bad)", { XX } }, | |
4025 | { "(bad)", { XX } }, | |
4026 | { "(bad)", { XX } }, | |
96fbad73 | 4027 | /* 40 */ |
d5d7db8e | 4028 | { "(bad)", { XX } }, |
85f10a01 MM |
4029 | { "phaddbw", { XM, EXq } }, |
4030 | { "phaddbd", { XM, EXq } }, | |
4031 | { "phaddbq", { XM, EXq } }, | |
d5d7db8e L |
4032 | { "(bad)", { XX } }, |
4033 | { "(bad)", { XX } }, | |
85f10a01 MM |
4034 | { "phaddwd", { XM, EXq } }, |
4035 | { "phaddwq", { XM, EXq } }, | |
96fbad73 | 4036 | /* 48 */ |
d5d7db8e L |
4037 | { "(bad)", { XX } }, |
4038 | { "(bad)", { XX } }, | |
4039 | { "(bad)", { XX } }, | |
85f10a01 | 4040 | { "phadddq", { XM, EXq } }, |
d5d7db8e L |
4041 | { "(bad)", { XX } }, |
4042 | { "(bad)", { XX } }, | |
4043 | { "(bad)", { XX } }, | |
4044 | { "(bad)", { XX } }, | |
96fbad73 | 4045 | /* 50 */ |
d5d7db8e | 4046 | { "(bad)", { XX } }, |
85f10a01 MM |
4047 | { "phaddubw", { XM, EXq } }, |
4048 | { "phaddubd", { XM, EXq } }, | |
4049 | { "phaddubq", { XM, EXq } }, | |
d5d7db8e L |
4050 | { "(bad)", { XX } }, |
4051 | { "(bad)", { XX } }, | |
85f10a01 MM |
4052 | { "phadduwd", { XM, EXq } }, |
4053 | { "phadduwq", { XM, EXq } }, | |
96fbad73 | 4054 | /* 58 */ |
d5d7db8e L |
4055 | { "(bad)", { XX } }, |
4056 | { "(bad)", { XX } }, | |
4057 | { "(bad)", { XX } }, | |
85f10a01 | 4058 | { "phaddudq", { XM, EXq } }, |
d5d7db8e L |
4059 | { "(bad)", { XX } }, |
4060 | { "(bad)", { XX } }, | |
4061 | { "(bad)", { XX } }, | |
4062 | { "(bad)", { XX } }, | |
96fbad73 | 4063 | /* 60 */ |
d5d7db8e | 4064 | { "(bad)", { XX } }, |
85f10a01 MM |
4065 | { "phsubbw", { XM, EXq } }, |
4066 | { "phsubbd", { XM, EXq } }, | |
4067 | { "phsubbq", { XM, EXq } }, | |
d5d7db8e L |
4068 | { "(bad)", { XX } }, |
4069 | { "(bad)", { XX } }, | |
4070 | { "(bad)", { XX } }, | |
4071 | { "(bad)", { XX } }, | |
96fbad73 | 4072 | /* 68 */ |
d5d7db8e L |
4073 | { "(bad)", { XX } }, |
4074 | { "(bad)", { XX } }, | |
4075 | { "(bad)", { XX } }, | |
4076 | { "(bad)", { XX } }, | |
4077 | { "(bad)", { XX } }, | |
4078 | { "(bad)", { XX } }, | |
4079 | { "(bad)", { XX } }, | |
4080 | { "(bad)", { XX } }, | |
96fbad73 | 4081 | /* 70 */ |
d5d7db8e L |
4082 | { "(bad)", { XX } }, |
4083 | { "(bad)", { XX } }, | |
4084 | { "(bad)", { XX } }, | |
4085 | { "(bad)", { XX } }, | |
4086 | { "(bad)", { XX } }, | |
4087 | { "(bad)", { XX } }, | |
4088 | { "(bad)", { XX } }, | |
4089 | { "(bad)", { XX } }, | |
96fbad73 | 4090 | /* 78 */ |
d5d7db8e L |
4091 | { "(bad)", { XX } }, |
4092 | { "(bad)", { XX } }, | |
4093 | { "(bad)", { XX } }, | |
4094 | { "(bad)", { XX } }, | |
4095 | { "(bad)", { XX } }, | |
4096 | { "(bad)", { XX } }, | |
4097 | { "(bad)", { XX } }, | |
4098 | { "(bad)", { XX } }, | |
96fbad73 | 4099 | /* 80 */ |
d5d7db8e L |
4100 | { "(bad)", { XX } }, |
4101 | { "(bad)", { XX } }, | |
4102 | { "(bad)", { XX } }, | |
4103 | { "(bad)", { XX } }, | |
4104 | { "(bad)", { XX } }, | |
4105 | { "(bad)", { XX } }, | |
4106 | { "(bad)", { XX } }, | |
4107 | { "(bad)", { XX } }, | |
96fbad73 | 4108 | /* 88 */ |
d5d7db8e L |
4109 | { "(bad)", { XX } }, |
4110 | { "(bad)", { XX } }, | |
4111 | { "(bad)", { XX } }, | |
4112 | { "(bad)", { XX } }, | |
4113 | { "(bad)", { XX } }, | |
4114 | { "(bad)", { XX } }, | |
4115 | { "(bad)", { XX } }, | |
4116 | { "(bad)", { XX } }, | |
96fbad73 | 4117 | /* 90 */ |
d5d7db8e L |
4118 | { "(bad)", { XX } }, |
4119 | { "(bad)", { XX } }, | |
4120 | { "(bad)", { XX } }, | |
4121 | { "(bad)", { XX } }, | |
4122 | { "(bad)", { XX } }, | |
4123 | { "(bad)", { XX } }, | |
4124 | { "(bad)", { XX } }, | |
4125 | { "(bad)", { XX } }, | |
96fbad73 | 4126 | /* 98 */ |
d5d7db8e L |
4127 | { "(bad)", { XX } }, |
4128 | { "(bad)", { XX } }, | |
4129 | { "(bad)", { XX } }, | |
4130 | { "(bad)", { XX } }, | |
4131 | { "(bad)", { XX } }, | |
4132 | { "(bad)", { XX } }, | |
4133 | { "(bad)", { XX } }, | |
4134 | { "(bad)", { XX } }, | |
96fbad73 | 4135 | /* a0 */ |
d5d7db8e L |
4136 | { "(bad)", { XX } }, |
4137 | { "(bad)", { XX } }, | |
4138 | { "(bad)", { XX } }, | |
4139 | { "(bad)", { XX } }, | |
4140 | { "(bad)", { XX } }, | |
4141 | { "(bad)", { XX } }, | |
4142 | { "(bad)", { XX } }, | |
4143 | { "(bad)", { XX } }, | |
96fbad73 | 4144 | /* a8 */ |
d5d7db8e L |
4145 | { "(bad)", { XX } }, |
4146 | { "(bad)", { XX } }, | |
4147 | { "(bad)", { XX } }, | |
4148 | { "(bad)", { XX } }, | |
4149 | { "(bad)", { XX } }, | |
4150 | { "(bad)", { XX } }, | |
4151 | { "(bad)", { XX } }, | |
4152 | { "(bad)", { XX } }, | |
96fbad73 | 4153 | /* b0 */ |
d5d7db8e L |
4154 | { "(bad)", { XX } }, |
4155 | { "(bad)", { XX } }, | |
4156 | { "(bad)", { XX } }, | |
4157 | { "(bad)", { XX } }, | |
4158 | { "(bad)", { XX } }, | |
4159 | { "(bad)", { XX } }, | |
4160 | { "(bad)", { XX } }, | |
4161 | { "(bad)", { XX } }, | |
96fbad73 | 4162 | /* b8 */ |
d5d7db8e L |
4163 | { "(bad)", { XX } }, |
4164 | { "(bad)", { XX } }, | |
4165 | { "(bad)", { XX } }, | |
4166 | { "(bad)", { XX } }, | |
4167 | { "(bad)", { XX } }, | |
4168 | { "(bad)", { XX } }, | |
4169 | { "(bad)", { XX } }, | |
4170 | { "(bad)", { XX } }, | |
96fbad73 | 4171 | /* c0 */ |
d5d7db8e L |
4172 | { "(bad)", { XX } }, |
4173 | { "(bad)", { XX } }, | |
4174 | { "(bad)", { XX } }, | |
4175 | { "(bad)", { XX } }, | |
4176 | { "(bad)", { XX } }, | |
4177 | { "(bad)", { XX } }, | |
4178 | { "(bad)", { XX } }, | |
4179 | { "(bad)", { XX } }, | |
96fbad73 | 4180 | /* c8 */ |
d5d7db8e L |
4181 | { "(bad)", { XX } }, |
4182 | { "(bad)", { XX } }, | |
4183 | { "(bad)", { XX } }, | |
4184 | { "(bad)", { XX } }, | |
4185 | { "(bad)", { XX } }, | |
4186 | { "(bad)", { XX } }, | |
4187 | { "(bad)", { XX } }, | |
4188 | { "(bad)", { XX } }, | |
96fbad73 | 4189 | /* d0 */ |
d5d7db8e L |
4190 | { "(bad)", { XX } }, |
4191 | { "(bad)", { XX } }, | |
4192 | { "(bad)", { XX } }, | |
4193 | { "(bad)", { XX } }, | |
4194 | { "(bad)", { XX } }, | |
4195 | { "(bad)", { XX } }, | |
4196 | { "(bad)", { XX } }, | |
4197 | { "(bad)", { XX } }, | |
96fbad73 | 4198 | /* d8 */ |
d5d7db8e L |
4199 | { "(bad)", { XX } }, |
4200 | { "(bad)", { XX } }, | |
4201 | { "(bad)", { XX } }, | |
4202 | { "(bad)", { XX } }, | |
4203 | { "(bad)", { XX } }, | |
4204 | { "(bad)", { XX } }, | |
4205 | { "(bad)", { XX } }, | |
4206 | { "(bad)", { XX } }, | |
96fbad73 | 4207 | /* e0 */ |
d5d7db8e L |
4208 | { "(bad)", { XX } }, |
4209 | { "(bad)", { XX } }, | |
4210 | { "(bad)", { XX } }, | |
4211 | { "(bad)", { XX } }, | |
4212 | { "(bad)", { XX } }, | |
4213 | { "(bad)", { XX } }, | |
4214 | { "(bad)", { XX } }, | |
4215 | { "(bad)", { XX } }, | |
96fbad73 | 4216 | /* e8 */ |
d5d7db8e L |
4217 | { "(bad)", { XX } }, |
4218 | { "(bad)", { XX } }, | |
4219 | { "(bad)", { XX } }, | |
4220 | { "(bad)", { XX } }, | |
4221 | { "(bad)", { XX } }, | |
4222 | { "(bad)", { XX } }, | |
4223 | { "(bad)", { XX } }, | |
4224 | { "(bad)", { XX } }, | |
96fbad73 | 4225 | /* f0 */ |
85f10a01 MM |
4226 | { "(bad)", { XX } }, |
4227 | { "(bad)", { XX } }, | |
d5d7db8e L |
4228 | { "(bad)", { XX } }, |
4229 | { "(bad)", { XX } }, | |
4230 | { "(bad)", { XX } }, | |
4231 | { "(bad)", { XX } }, | |
4232 | { "(bad)", { XX } }, | |
4233 | { "(bad)", { XX } }, | |
96fbad73 | 4234 | /* f8 */ |
d5d7db8e L |
4235 | { "(bad)", { XX } }, |
4236 | { "(bad)", { XX } }, | |
4237 | { "(bad)", { XX } }, | |
4238 | { "(bad)", { XX } }, | |
4239 | { "(bad)", { XX } }, | |
4240 | { "(bad)", { XX } }, | |
4241 | { "(bad)", { XX } }, | |
4242 | { "(bad)", { XX } }, | |
331d2d0d | 4243 | }, |
89b66d55 | 4244 | /* THREE_BYTE_0F7B */ |
331d2d0d | 4245 | { |
96fbad73 | 4246 | /* 00 */ |
d5d7db8e L |
4247 | { "(bad)", { XX } }, |
4248 | { "(bad)", { XX } }, | |
4249 | { "(bad)", { XX } }, | |
4250 | { "(bad)", { XX } }, | |
4251 | { "(bad)", { XX } }, | |
4252 | { "(bad)", { XX } }, | |
4253 | { "(bad)", { XX } }, | |
4254 | { "(bad)", { XX } }, | |
96fbad73 | 4255 | /* 08 */ |
d5d7db8e L |
4256 | { "(bad)", { XX } }, |
4257 | { "(bad)", { XX } }, | |
4258 | { "(bad)", { XX } }, | |
4259 | { "(bad)", { XX } }, | |
4260 | { "(bad)", { XX } }, | |
4261 | { "(bad)", { XX } }, | |
4262 | { "(bad)", { XX } }, | |
4263 | { "(bad)", { XX } }, | |
85f10a01 | 4264 | /* 10 */ |
d5d7db8e L |
4265 | { "(bad)", { XX } }, |
4266 | { "(bad)", { XX } }, | |
4267 | { "(bad)", { XX } }, | |
4268 | { "(bad)", { XX } }, | |
4269 | { "(bad)", { XX } }, | |
4270 | { "(bad)", { XX } }, | |
4271 | { "(bad)", { XX } }, | |
4272 | { "(bad)", { XX } }, | |
85f10a01 | 4273 | /* 18 */ |
d5d7db8e L |
4274 | { "(bad)", { XX } }, |
4275 | { "(bad)", { XX } }, | |
4276 | { "(bad)", { XX } }, | |
4277 | { "(bad)", { XX } }, | |
4278 | { "(bad)", { XX } }, | |
4279 | { "(bad)", { XX } }, | |
4280 | { "(bad)", { XX } }, | |
4281 | { "(bad)", { XX } }, | |
85f10a01 | 4282 | /* 20 */ |
d5d7db8e L |
4283 | { "(bad)", { XX } }, |
4284 | { "(bad)", { XX } }, | |
4285 | { "(bad)", { XX } }, | |
4286 | { "(bad)", { XX } }, | |
4287 | { "(bad)", { XX } }, | |
4288 | { "(bad)", { XX } }, | |
4289 | { "(bad)", { XX } }, | |
4290 | { "(bad)", { XX } }, | |
85f10a01 | 4291 | /* 28 */ |
d5d7db8e L |
4292 | { "(bad)", { XX } }, |
4293 | { "(bad)", { XX } }, | |
4294 | { "(bad)", { XX } }, | |
4295 | { "(bad)", { XX } }, | |
4296 | { "(bad)", { XX } }, | |
4297 | { "(bad)", { XX } }, | |
4298 | { "(bad)", { XX } }, | |
4299 | { "(bad)", { XX } }, | |
85f10a01 | 4300 | /* 30 */ |
d5d7db8e L |
4301 | { "(bad)", { XX } }, |
4302 | { "(bad)", { XX } }, | |
4303 | { "(bad)", { XX } }, | |
4304 | { "(bad)", { XX } }, | |
4305 | { "(bad)", { XX } }, | |
4306 | { "(bad)", { XX } }, | |
85f10a01 MM |
4307 | { "(bad)", { XX } }, |
4308 | { "(bad)", { XX } }, | |
4309 | /* 38 */ | |
4310 | { "(bad)", { XX } }, | |
4311 | { "(bad)", { XX } }, | |
4312 | { "(bad)", { XX } }, | |
d5d7db8e L |
4313 | { "(bad)", { XX } }, |
4314 | { "(bad)", { XX } }, | |
4315 | { "(bad)", { XX } }, | |
4316 | { "(bad)", { XX } }, | |
4317 | { "(bad)", { XX } }, | |
85f10a01 MM |
4318 | /* 40 */ |
4319 | { "protb", { XM, EXq, Ib } }, | |
4320 | { "protw", { XM, EXq, Ib } }, | |
4321 | { "protd", { XM, EXq, Ib } }, | |
4322 | { "protq", { XM, EXq, Ib } }, | |
4323 | { "pshlb", { XM, EXq, Ib } }, | |
4324 | { "pshlw", { XM, EXq, Ib } }, | |
4325 | { "pshld", { XM, EXq, Ib } }, | |
4326 | { "pshlq", { XM, EXq, Ib } }, | |
4327 | /* 48 */ | |
4328 | { "pshab", { XM, EXq, Ib } }, | |
4329 | { "pshaw", { XM, EXq, Ib } }, | |
4330 | { "pshad", { XM, EXq, Ib } }, | |
4331 | { "pshaq", { XM, EXq, Ib } }, | |
4332 | { "(bad)", { XX } }, | |
d5d7db8e L |
4333 | { "(bad)", { XX } }, |
4334 | { "(bad)", { XX } }, | |
4335 | { "(bad)", { XX } }, | |
96fbad73 | 4336 | /* 50 */ |
d5d7db8e L |
4337 | { "(bad)", { XX } }, |
4338 | { "(bad)", { XX } }, | |
4339 | { "(bad)", { XX } }, | |
4340 | { "(bad)", { XX } }, | |
4341 | { "(bad)", { XX } }, | |
4342 | { "(bad)", { XX } }, | |
4343 | { "(bad)", { XX } }, | |
4344 | { "(bad)", { XX } }, | |
96fbad73 | 4345 | /* 58 */ |
d5d7db8e L |
4346 | { "(bad)", { XX } }, |
4347 | { "(bad)", { XX } }, | |
4348 | { "(bad)", { XX } }, | |
4349 | { "(bad)", { XX } }, | |
4350 | { "(bad)", { XX } }, | |
4351 | { "(bad)", { XX } }, | |
4352 | { "(bad)", { XX } }, | |
4353 | { "(bad)", { XX } }, | |
96fbad73 | 4354 | /* 60 */ |
85f10a01 MM |
4355 | { "(bad)", { XX } }, |
4356 | { "(bad)", { XX } }, | |
4357 | { "(bad)", { XX } }, | |
4358 | { "(bad)", { XX } }, | |
d5d7db8e L |
4359 | { "(bad)", { XX } }, |
4360 | { "(bad)", { XX } }, | |
4361 | { "(bad)", { XX } }, | |
4362 | { "(bad)", { XX } }, | |
96fbad73 | 4363 | /* 68 */ |
d5d7db8e L |
4364 | { "(bad)", { XX } }, |
4365 | { "(bad)", { XX } }, | |
4366 | { "(bad)", { XX } }, | |
4367 | { "(bad)", { XX } }, | |
4368 | { "(bad)", { XX } }, | |
4369 | { "(bad)", { XX } }, | |
4370 | { "(bad)", { XX } }, | |
4371 | { "(bad)", { XX } }, | |
96fbad73 | 4372 | /* 70 */ |
d5d7db8e L |
4373 | { "(bad)", { XX } }, |
4374 | { "(bad)", { XX } }, | |
4375 | { "(bad)", { XX } }, | |
4376 | { "(bad)", { XX } }, | |
4377 | { "(bad)", { XX } }, | |
4378 | { "(bad)", { XX } }, | |
4379 | { "(bad)", { XX } }, | |
4380 | { "(bad)", { XX } }, | |
96fbad73 | 4381 | /* 78 */ |
d5d7db8e L |
4382 | { "(bad)", { XX } }, |
4383 | { "(bad)", { XX } }, | |
4384 | { "(bad)", { XX } }, | |
4385 | { "(bad)", { XX } }, | |
4386 | { "(bad)", { XX } }, | |
4387 | { "(bad)", { XX } }, | |
4388 | { "(bad)", { XX } }, | |
4389 | { "(bad)", { XX } }, | |
96fbad73 | 4390 | /* 80 */ |
d5d7db8e L |
4391 | { "(bad)", { XX } }, |
4392 | { "(bad)", { XX } }, | |
4393 | { "(bad)", { XX } }, | |
4394 | { "(bad)", { XX } }, | |
4395 | { "(bad)", { XX } }, | |
4396 | { "(bad)", { XX } }, | |
4397 | { "(bad)", { XX } }, | |
4398 | { "(bad)", { XX } }, | |
96fbad73 | 4399 | /* 88 */ |
d5d7db8e L |
4400 | { "(bad)", { XX } }, |
4401 | { "(bad)", { XX } }, | |
4402 | { "(bad)", { XX } }, | |
4403 | { "(bad)", { XX } }, | |
4404 | { "(bad)", { XX } }, | |
4405 | { "(bad)", { XX } }, | |
4406 | { "(bad)", { XX } }, | |
4407 | { "(bad)", { XX } }, | |
96fbad73 | 4408 | /* 90 */ |
d5d7db8e L |
4409 | { "(bad)", { XX } }, |
4410 | { "(bad)", { XX } }, | |
4411 | { "(bad)", { XX } }, | |
4412 | { "(bad)", { XX } }, | |
4413 | { "(bad)", { XX } }, | |
4414 | { "(bad)", { XX } }, | |
4415 | { "(bad)", { XX } }, | |
4416 | { "(bad)", { XX } }, | |
96fbad73 | 4417 | /* 98 */ |
d5d7db8e L |
4418 | { "(bad)", { XX } }, |
4419 | { "(bad)", { XX } }, | |
4420 | { "(bad)", { XX } }, | |
4421 | { "(bad)", { XX } }, | |
4422 | { "(bad)", { XX } }, | |
4423 | { "(bad)", { XX } }, | |
4424 | { "(bad)", { XX } }, | |
4425 | { "(bad)", { XX } }, | |
96fbad73 | 4426 | /* a0 */ |
d5d7db8e L |
4427 | { "(bad)", { XX } }, |
4428 | { "(bad)", { XX } }, | |
4429 | { "(bad)", { XX } }, | |
4430 | { "(bad)", { XX } }, | |
4431 | { "(bad)", { XX } }, | |
4432 | { "(bad)", { XX } }, | |
4433 | { "(bad)", { XX } }, | |
4434 | { "(bad)", { XX } }, | |
96fbad73 | 4435 | /* a8 */ |
d5d7db8e L |
4436 | { "(bad)", { XX } }, |
4437 | { "(bad)", { XX } }, | |
4438 | { "(bad)", { XX } }, | |
4439 | { "(bad)", { XX } }, | |
4440 | { "(bad)", { XX } }, | |
4441 | { "(bad)", { XX } }, | |
4442 | { "(bad)", { XX } }, | |
4443 | { "(bad)", { XX } }, | |
96fbad73 | 4444 | /* b0 */ |
d5d7db8e L |
4445 | { "(bad)", { XX } }, |
4446 | { "(bad)", { XX } }, | |
4447 | { "(bad)", { XX } }, | |
4448 | { "(bad)", { XX } }, | |
4449 | { "(bad)", { XX } }, | |
4450 | { "(bad)", { XX } }, | |
4451 | { "(bad)", { XX } }, | |
4452 | { "(bad)", { XX } }, | |
96fbad73 | 4453 | /* b8 */ |
d5d7db8e L |
4454 | { "(bad)", { XX } }, |
4455 | { "(bad)", { XX } }, | |
4456 | { "(bad)", { XX } }, | |
4457 | { "(bad)", { XX } }, | |
4458 | { "(bad)", { XX } }, | |
4459 | { "(bad)", { XX } }, | |
4460 | { "(bad)", { XX } }, | |
4461 | { "(bad)", { XX } }, | |
96fbad73 | 4462 | /* c0 */ |
d5d7db8e L |
4463 | { "(bad)", { XX } }, |
4464 | { "(bad)", { XX } }, | |
4465 | { "(bad)", { XX } }, | |
4466 | { "(bad)", { XX } }, | |
4467 | { "(bad)", { XX } }, | |
4468 | { "(bad)", { XX } }, | |
4469 | { "(bad)", { XX } }, | |
4470 | { "(bad)", { XX } }, | |
96fbad73 | 4471 | /* c8 */ |
d5d7db8e L |
4472 | { "(bad)", { XX } }, |
4473 | { "(bad)", { XX } }, | |
4474 | { "(bad)", { XX } }, | |
4475 | { "(bad)", { XX } }, | |
4476 | { "(bad)", { XX } }, | |
4477 | { "(bad)", { XX } }, | |
4478 | { "(bad)", { XX } }, | |
4479 | { "(bad)", { XX } }, | |
96fbad73 | 4480 | /* d0 */ |
d5d7db8e L |
4481 | { "(bad)", { XX } }, |
4482 | { "(bad)", { XX } }, | |
4483 | { "(bad)", { XX } }, | |
4484 | { "(bad)", { XX } }, | |
4485 | { "(bad)", { XX } }, | |
4486 | { "(bad)", { XX } }, | |
4487 | { "(bad)", { XX } }, | |
4488 | { "(bad)", { XX } }, | |
96fbad73 | 4489 | /* d8 */ |
d5d7db8e L |
4490 | { "(bad)", { XX } }, |
4491 | { "(bad)", { XX } }, | |
4492 | { "(bad)", { XX } }, | |
4493 | { "(bad)", { XX } }, | |
4494 | { "(bad)", { XX } }, | |
4495 | { "(bad)", { XX } }, | |
4496 | { "(bad)", { XX } }, | |
4497 | { "(bad)", { XX } }, | |
96fbad73 | 4498 | /* e0 */ |
d5d7db8e L |
4499 | { "(bad)", { XX } }, |
4500 | { "(bad)", { XX } }, | |
4501 | { "(bad)", { XX } }, | |
4502 | { "(bad)", { XX } }, | |
4503 | { "(bad)", { XX } }, | |
4504 | { "(bad)", { XX } }, | |
4505 | { "(bad)", { XX } }, | |
4506 | { "(bad)", { XX } }, | |
96fbad73 | 4507 | /* e8 */ |
d5d7db8e L |
4508 | { "(bad)", { XX } }, |
4509 | { "(bad)", { XX } }, | |
4510 | { "(bad)", { XX } }, | |
4511 | { "(bad)", { XX } }, | |
4512 | { "(bad)", { XX } }, | |
4513 | { "(bad)", { XX } }, | |
4514 | { "(bad)", { XX } }, | |
4515 | { "(bad)", { XX } }, | |
96fbad73 | 4516 | /* f0 */ |
d5d7db8e L |
4517 | { "(bad)", { XX } }, |
4518 | { "(bad)", { XX } }, | |
4519 | { "(bad)", { XX } }, | |
4520 | { "(bad)", { XX } }, | |
4521 | { "(bad)", { XX } }, | |
4522 | { "(bad)", { XX } }, | |
4523 | { "(bad)", { XX } }, | |
4524 | { "(bad)", { XX } }, | |
96fbad73 | 4525 | /* f8 */ |
d5d7db8e L |
4526 | { "(bad)", { XX } }, |
4527 | { "(bad)", { XX } }, | |
4528 | { "(bad)", { XX } }, | |
4529 | { "(bad)", { XX } }, | |
4530 | { "(bad)", { XX } }, | |
4531 | { "(bad)", { XX } }, | |
4532 | { "(bad)", { XX } }, | |
4533 | { "(bad)", { XX } }, | |
ce518a5f | 4534 | } |
331d2d0d L |
4535 | }; |
4536 | ||
1ceb70f8 | 4537 | static const struct dis386 mod_table[][2] = { |
b844680a | 4538 | { |
1ceb70f8 | 4539 | /* MOD_8D */ |
d8faab4e L |
4540 | { "leaS", { Gv, M } }, |
4541 | { "(bad)", { XX } }, | |
4542 | }, | |
4543 | { | |
92fddf8e L |
4544 | /* MOD_0F01_REG_0 */ |
4545 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
4546 | { RM_TABLE (RM_0F01_REG_0) }, | |
d8faab4e L |
4547 | }, |
4548 | { | |
92fddf8e L |
4549 | /* MOD_0F01_REG_1 */ |
4550 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
4551 | { RM_TABLE (RM_0F01_REG_1) }, | |
d8faab4e L |
4552 | }, |
4553 | { | |
92fddf8e L |
4554 | /* MOD_0F01_REG_2 */ |
4555 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
475a2301 | 4556 | { RM_TABLE (RM_0F01_REG_2) }, |
d8faab4e L |
4557 | }, |
4558 | { | |
92fddf8e L |
4559 | /* MOD_0F01_REG_3 */ |
4560 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
4561 | { RM_TABLE (RM_0F01_REG_3) }, | |
d8faab4e L |
4562 | }, |
4563 | { | |
92fddf8e L |
4564 | /* MOD_0F01_REG_7 */ |
4565 | { "invlpg", { Mb } }, | |
4566 | { RM_TABLE (RM_0F01_REG_7) }, | |
b844680a L |
4567 | }, |
4568 | { | |
92fddf8e L |
4569 | /* MOD_0F12_PREFIX_0 */ |
4570 | { "movlps", { XM, EXq } }, | |
4571 | { "movhlps", { XM, EXq } }, | |
b844680a L |
4572 | }, |
4573 | { | |
92fddf8e L |
4574 | /* MOD_0F13 */ |
4575 | { "movlpX", { EXq, XM } }, | |
d8faab4e L |
4576 | { "(bad)", { XX } }, |
4577 | }, | |
4578 | { | |
92fddf8e L |
4579 | /* MOD_0F16_PREFIX_0 */ |
4580 | { "movhps", { XM, EXq } }, | |
4581 | { "movlhps", { XM, EXq } }, | |
b844680a L |
4582 | }, |
4583 | { | |
92fddf8e L |
4584 | /* MOD_0F17 */ |
4585 | { "movhpX", { EXq, XM } }, | |
b844680a L |
4586 | { "(bad)", { XX } }, |
4587 | }, | |
4588 | { | |
92fddf8e L |
4589 | /* MOD_0F18_REG_0 */ |
4590 | { "prefetchnta", { Mb } }, | |
b844680a | 4591 | { "(bad)", { XX } }, |
b844680a L |
4592 | }, |
4593 | { | |
92fddf8e L |
4594 | /* MOD_0F18_REG_1 */ |
4595 | { "prefetcht0", { Mb } }, | |
4596 | { "(bad)", { XX } }, | |
b844680a L |
4597 | }, |
4598 | { | |
92fddf8e L |
4599 | /* MOD_0F18_REG_2 */ |
4600 | { "prefetcht1", { Mb } }, | |
4601 | { "(bad)", { XX } }, | |
b844680a L |
4602 | }, |
4603 | { | |
92fddf8e L |
4604 | /* MOD_0F18_REG_3 */ |
4605 | { "prefetcht2", { Mb } }, | |
b844680a | 4606 | { "(bad)", { XX } }, |
b844680a L |
4607 | }, |
4608 | { | |
92fddf8e L |
4609 | /* MOD_0F20 */ |
4610 | { "(bad)", { XX } }, | |
4611 | { "movZ", { Rm, Cm } }, | |
b844680a L |
4612 | }, |
4613 | { | |
92fddf8e L |
4614 | /* MOD_0F21 */ |
4615 | { "(bad)", { XX } }, | |
4616 | { "movZ", { Rm, Dm } }, | |
b844680a L |
4617 | }, |
4618 | { | |
92fddf8e | 4619 | /* MOD_0F22 */ |
b844680a | 4620 | { "(bad)", { XX } }, |
92fddf8e | 4621 | { "movZ", { Cm, Rm } }, |
b844680a L |
4622 | }, |
4623 | { | |
92fddf8e | 4624 | /* MOD_0F23 */ |
b844680a | 4625 | { "(bad)", { XX } }, |
92fddf8e | 4626 | { "movZ", { Dm, Rm } }, |
b844680a L |
4627 | }, |
4628 | { | |
92fddf8e L |
4629 | /* MOD_0F24 */ |
4630 | { THREE_BYTE_TABLE (THREE_BYTE_0F24) }, | |
4631 | { "movL", { Rd, Td } }, | |
b844680a L |
4632 | }, |
4633 | { | |
92fddf8e | 4634 | /* MOD_0F26 */ |
b844680a | 4635 | { "(bad)", { XX } }, |
92fddf8e | 4636 | { "movL", { Td, Rd } }, |
b844680a | 4637 | }, |
75c135a8 L |
4638 | { |
4639 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 4640 | {"movntps", { Mx, XM } }, |
75c135a8 L |
4641 | { "(bad)", { XX } }, |
4642 | }, | |
4643 | { | |
4644 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 4645 | {"movntss", { Md, XM } }, |
75c135a8 L |
4646 | { "(bad)", { XX } }, |
4647 | }, | |
4648 | { | |
4649 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 4650 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
4651 | { "(bad)", { XX } }, |
4652 | }, | |
4653 | { | |
4654 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 4655 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
4656 | { "(bad)", { XX } }, |
4657 | }, | |
4658 | { | |
4659 | /* MOD_0F51 */ | |
4660 | { "(bad)", { XX } }, | |
4661 | { "movmskpX", { Gdq, XS } }, | |
4662 | }, | |
b844680a | 4663 | { |
1ceb70f8 | 4664 | /* MOD_0F71_REG_2 */ |
b844680a | 4665 | { "(bad)", { XX } }, |
4e7d34a6 | 4666 | { "psrlw", { MS, Ib } }, |
b844680a L |
4667 | }, |
4668 | { | |
1ceb70f8 | 4669 | /* MOD_0F71_REG_4 */ |
b844680a | 4670 | { "(bad)", { XX } }, |
4e7d34a6 | 4671 | { "psraw", { MS, Ib } }, |
b844680a L |
4672 | }, |
4673 | { | |
1ceb70f8 | 4674 | /* MOD_0F71_REG_6 */ |
b844680a | 4675 | { "(bad)", { XX } }, |
4e7d34a6 | 4676 | { "psllw", { MS, Ib } }, |
b844680a L |
4677 | }, |
4678 | { | |
1ceb70f8 | 4679 | /* MOD_0F72_REG_2 */ |
b844680a | 4680 | { "(bad)", { XX } }, |
4e7d34a6 | 4681 | { "psrld", { MS, Ib } }, |
b844680a L |
4682 | }, |
4683 | { | |
1ceb70f8 | 4684 | /* MOD_0F72_REG_4 */ |
b844680a | 4685 | { "(bad)", { XX } }, |
4e7d34a6 | 4686 | { "psrad", { MS, Ib } }, |
b844680a L |
4687 | }, |
4688 | { | |
1ceb70f8 | 4689 | /* MOD_0F72_REG_6 */ |
b844680a | 4690 | { "(bad)", { XX } }, |
4e7d34a6 | 4691 | { "pslld", { MS, Ib } }, |
b844680a L |
4692 | }, |
4693 | { | |
1ceb70f8 | 4694 | /* MOD_0F73_REG_2 */ |
4e7d34a6 L |
4695 | { "(bad)", { XX } }, |
4696 | { "psrlq", { MS, Ib } }, | |
b844680a L |
4697 | }, |
4698 | { | |
1ceb70f8 | 4699 | /* MOD_0F73_REG_3 */ |
b844680a | 4700 | { "(bad)", { XX } }, |
1ceb70f8 | 4701 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
b844680a L |
4702 | }, |
4703 | { | |
1ceb70f8 | 4704 | /* MOD_0F73_REG_6 */ |
b844680a | 4705 | { "(bad)", { XX } }, |
4e7d34a6 | 4706 | { "psllq", { MS, Ib } }, |
b844680a L |
4707 | }, |
4708 | { | |
1ceb70f8 | 4709 | /* MOD_0F73_REG_7 */ |
b844680a | 4710 | { "(bad)", { XX } }, |
1ceb70f8 | 4711 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
b844680a L |
4712 | }, |
4713 | { | |
1ceb70f8 | 4714 | /* MOD_0FAE_REG_0 */ |
4e7d34a6 | 4715 | { "fxsave", { M } }, |
b844680a L |
4716 | { "(bad)", { XX } }, |
4717 | }, | |
d8faab4e | 4718 | { |
1ceb70f8 | 4719 | /* MOD_0FAE_REG_1 */ |
4e7d34a6 | 4720 | { "fxrstor", { M } }, |
d8faab4e L |
4721 | { "(bad)", { XX } }, |
4722 | }, | |
4723 | { | |
1ceb70f8 | 4724 | /* MOD_0FAE_REG_2 */ |
4e7d34a6 | 4725 | { "ldmxcsr", { Md } }, |
d8faab4e L |
4726 | { "(bad)", { XX } }, |
4727 | }, | |
876d4bfa | 4728 | { |
1ceb70f8 | 4729 | /* MOD_0FAE_REG_3 */ |
4e7d34a6 | 4730 | { "stmxcsr", { Md } }, |
876d4bfa L |
4731 | { "(bad)", { XX } }, |
4732 | }, | |
4733 | { | |
475a2301 L |
4734 | /* MOD_0FAE_REG_4 */ |
4735 | { "xsave", { M } }, | |
876d4bfa | 4736 | { "(bad)", { XX } }, |
475a2301 L |
4737 | }, |
4738 | { | |
4739 | /* MOD_0FAE_REG_5 */ | |
4740 | { "xrstor", { M } }, | |
1ceb70f8 | 4741 | { RM_TABLE (RM_0FAE_REG_5) }, |
876d4bfa L |
4742 | }, |
4743 | { | |
1ceb70f8 | 4744 | /* MOD_0FAE_REG_6 */ |
4e7d34a6 | 4745 | { "(bad)", { XX } }, |
1ceb70f8 | 4746 | { RM_TABLE (RM_0FAE_REG_6) }, |
876d4bfa L |
4747 | }, |
4748 | { | |
1ceb70f8 | 4749 | /* MOD_0FAE_REG_7 */ |
4e7d34a6 | 4750 | { "clflush", { Mb } }, |
1ceb70f8 | 4751 | { RM_TABLE (RM_0FAE_REG_7) }, |
876d4bfa | 4752 | }, |
bbedc832 | 4753 | { |
92fddf8e L |
4754 | /* MOD_0FB2 */ |
4755 | { "lssS", { Gv, Mp } }, | |
4e7d34a6 | 4756 | { "(bad)", { XX } }, |
bbedc832 | 4757 | }, |
144c41d9 | 4758 | { |
92fddf8e L |
4759 | /* MOD_0FB4 */ |
4760 | { "lfsS", { Gv, Mp } }, | |
4e7d34a6 | 4761 | { "(bad)", { XX } }, |
144c41d9 | 4762 | }, |
1afd85e3 | 4763 | { |
92fddf8e L |
4764 | /* MOD_0FB5 */ |
4765 | { "lgsS", { Gv, Mp } }, | |
4766 | { "(bad)", { XX } }, | |
1afd85e3 L |
4767 | }, |
4768 | { | |
92fddf8e L |
4769 | /* MOD_0FC7_REG_6 */ |
4770 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
4771 | { "(bad)", { XX } }, | |
4772 | }, | |
4773 | { | |
4774 | /* MOD_0FC7_REG_7 */ | |
4775 | { "vmptrst", { Mq } }, | |
4776 | { "(bad)", { XX } }, | |
1afd85e3 | 4777 | }, |
75c135a8 L |
4778 | { |
4779 | /* MOD_0FD7 */ | |
4780 | { "(bad)", { XX } }, | |
4781 | { "pmovmskb", { Gdq, MS } }, | |
4782 | }, | |
4783 | { | |
4784 | /* MOD_0FE7_PREFIX_2 */ | |
4ee52178 | 4785 | { "movntdq", { Mx, XM } }, |
75c135a8 L |
4786 | { "(bad)", { XX } }, |
4787 | }, | |
1afd85e3 | 4788 | { |
1ceb70f8 | 4789 | /* MOD_0FF0_PREFIX_3 */ |
4e7d34a6 | 4790 | { "lddqu", { XM, M } }, |
1afd85e3 | 4791 | { "(bad)", { XX } }, |
1afd85e3 | 4792 | }, |
75c135a8 L |
4793 | { |
4794 | /* MOD_0F382A_PREFIX_2 */ | |
4ee52178 | 4795 | { "movntdqa", { XM, Mx } }, |
75c135a8 L |
4796 | { "(bad)", { XX } }, |
4797 | }, | |
1afd85e3 | 4798 | { |
1ceb70f8 | 4799 | /* MOD_62_32BIT */ |
4e7d34a6 | 4800 | { "bound{S|}", { Gv, Ma } }, |
1afd85e3 | 4801 | { "(bad)", { XX } }, |
1afd85e3 L |
4802 | }, |
4803 | { | |
1ceb70f8 | 4804 | /* MOD_C4_32BIT */ |
4e7d34a6 L |
4805 | { "lesS", { Gv, Mp } }, |
4806 | { "(bad)", { XX } }, | |
1afd85e3 L |
4807 | }, |
4808 | { | |
1ceb70f8 | 4809 | /* MOD_C5_32BIT */ |
4e7d34a6 | 4810 | { "ldsS", { Gv, Mp } }, |
1afd85e3 | 4811 | { "(bad)", { XX } }, |
1afd85e3 | 4812 | }, |
b844680a L |
4813 | }; |
4814 | ||
1ceb70f8 | 4815 | static const struct dis386 rm_table[][8] = { |
b844680a | 4816 | { |
1ceb70f8 | 4817 | /* RM_0F01_REG_0 */ |
b844680a L |
4818 | { "(bad)", { XX } }, |
4819 | { "vmcall", { Skip_MODRM } }, | |
4820 | { "vmlaunch", { Skip_MODRM } }, | |
4821 | { "vmresume", { Skip_MODRM } }, | |
4822 | { "vmxoff", { Skip_MODRM } }, | |
4823 | { "(bad)", { XX } }, | |
4824 | { "(bad)", { XX } }, | |
4825 | { "(bad)", { XX } }, | |
4826 | }, | |
4827 | { | |
1ceb70f8 | 4828 | /* RM_0F01_REG_1 */ |
b844680a L |
4829 | { "monitor", { { OP_Monitor, 0 } } }, |
4830 | { "mwait", { { OP_Mwait, 0 } } }, | |
4831 | { "(bad)", { XX } }, | |
4832 | { "(bad)", { XX } }, | |
4833 | { "(bad)", { XX } }, | |
4834 | { "(bad)", { XX } }, | |
4835 | { "(bad)", { XX } }, | |
4836 | { "(bad)", { XX } }, | |
4837 | }, | |
475a2301 L |
4838 | { |
4839 | /* RM_0F01_REG_2 */ | |
4840 | { "xgetbv", { Skip_MODRM } }, | |
4841 | { "xsetbv", { Skip_MODRM } }, | |
4842 | { "(bad)", { XX } }, | |
4843 | { "(bad)", { XX } }, | |
4844 | { "(bad)", { XX } }, | |
4845 | { "(bad)", { XX } }, | |
4846 | { "(bad)", { XX } }, | |
4847 | { "(bad)", { XX } }, | |
4848 | }, | |
b844680a | 4849 | { |
1ceb70f8 | 4850 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
4851 | { "vmrun", { Skip_MODRM } }, |
4852 | { "vmmcall", { Skip_MODRM } }, | |
4853 | { "vmload", { Skip_MODRM } }, | |
4854 | { "vmsave", { Skip_MODRM } }, | |
4855 | { "stgi", { Skip_MODRM } }, | |
4856 | { "clgi", { Skip_MODRM } }, | |
4857 | { "skinit", { Skip_MODRM } }, | |
4858 | { "invlpga", { Skip_MODRM } }, | |
4859 | }, | |
4860 | { | |
1ceb70f8 | 4861 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
4862 | { "swapgs", { Skip_MODRM } }, |
4863 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
4864 | { "(bad)", { XX } }, |
4865 | { "(bad)", { XX } }, | |
4866 | { "(bad)", { XX } }, | |
4867 | { "(bad)", { XX } }, | |
4868 | { "(bad)", { XX } }, | |
4869 | { "(bad)", { XX } }, | |
4870 | }, | |
4871 | { | |
1ceb70f8 | 4872 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 4873 | { "lfence", { Skip_MODRM } }, |
b844680a L |
4874 | { "(bad)", { XX } }, |
4875 | { "(bad)", { XX } }, | |
4876 | { "(bad)", { XX } }, | |
4877 | { "(bad)", { XX } }, | |
4878 | { "(bad)", { XX } }, | |
4879 | { "(bad)", { XX } }, | |
4880 | { "(bad)", { XX } }, | |
4881 | }, | |
4882 | { | |
1ceb70f8 | 4883 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 4884 | { "mfence", { Skip_MODRM } }, |
b844680a L |
4885 | { "(bad)", { XX } }, |
4886 | { "(bad)", { XX } }, | |
4887 | { "(bad)", { XX } }, | |
4888 | { "(bad)", { XX } }, | |
4889 | { "(bad)", { XX } }, | |
4890 | { "(bad)", { XX } }, | |
4891 | { "(bad)", { XX } }, | |
4892 | }, | |
bbedc832 | 4893 | { |
1ceb70f8 | 4894 | /* RM_0FAE_REG_7 */ |
4e7d34a6 L |
4895 | { "sfence", { Skip_MODRM } }, |
4896 | { "(bad)", { XX } }, | |
bbedc832 L |
4897 | { "(bad)", { XX } }, |
4898 | { "(bad)", { XX } }, | |
4899 | { "(bad)", { XX } }, | |
4900 | { "(bad)", { XX } }, | |
4901 | { "(bad)", { XX } }, | |
4902 | { "(bad)", { XX } }, | |
144c41d9 | 4903 | }, |
b844680a L |
4904 | }; |
4905 | ||
c608c12e AM |
4906 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
4907 | ||
252b5132 | 4908 | static void |
26ca5450 | 4909 | ckprefix (void) |
252b5132 | 4910 | { |
52b15da3 JH |
4911 | int newrex; |
4912 | rex = 0; | |
252b5132 | 4913 | prefixes = 0; |
7d421014 | 4914 | used_prefixes = 0; |
52b15da3 | 4915 | rex_used = 0; |
252b5132 RH |
4916 | while (1) |
4917 | { | |
4918 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 4919 | newrex = 0; |
252b5132 RH |
4920 | switch (*codep) |
4921 | { | |
52b15da3 JH |
4922 | /* REX prefixes family. */ |
4923 | case 0x40: | |
4924 | case 0x41: | |
4925 | case 0x42: | |
4926 | case 0x43: | |
4927 | case 0x44: | |
4928 | case 0x45: | |
4929 | case 0x46: | |
4930 | case 0x47: | |
4931 | case 0x48: | |
4932 | case 0x49: | |
4933 | case 0x4a: | |
4934 | case 0x4b: | |
4935 | case 0x4c: | |
4936 | case 0x4d: | |
4937 | case 0x4e: | |
4938 | case 0x4f: | |
cb712a9e | 4939 | if (address_mode == mode_64bit) |
52b15da3 JH |
4940 | newrex = *codep; |
4941 | else | |
4942 | return; | |
4943 | break; | |
252b5132 RH |
4944 | case 0xf3: |
4945 | prefixes |= PREFIX_REPZ; | |
4946 | break; | |
4947 | case 0xf2: | |
4948 | prefixes |= PREFIX_REPNZ; | |
4949 | break; | |
4950 | case 0xf0: | |
4951 | prefixes |= PREFIX_LOCK; | |
4952 | break; | |
4953 | case 0x2e: | |
4954 | prefixes |= PREFIX_CS; | |
4955 | break; | |
4956 | case 0x36: | |
4957 | prefixes |= PREFIX_SS; | |
4958 | break; | |
4959 | case 0x3e: | |
4960 | prefixes |= PREFIX_DS; | |
4961 | break; | |
4962 | case 0x26: | |
4963 | prefixes |= PREFIX_ES; | |
4964 | break; | |
4965 | case 0x64: | |
4966 | prefixes |= PREFIX_FS; | |
4967 | break; | |
4968 | case 0x65: | |
4969 | prefixes |= PREFIX_GS; | |
4970 | break; | |
4971 | case 0x66: | |
4972 | prefixes |= PREFIX_DATA; | |
4973 | break; | |
4974 | case 0x67: | |
4975 | prefixes |= PREFIX_ADDR; | |
4976 | break; | |
5076851f | 4977 | case FWAIT_OPCODE: |
252b5132 RH |
4978 | /* fwait is really an instruction. If there are prefixes |
4979 | before the fwait, they belong to the fwait, *not* to the | |
4980 | following instruction. */ | |
3e7d61b2 | 4981 | if (prefixes || rex) |
252b5132 RH |
4982 | { |
4983 | prefixes |= PREFIX_FWAIT; | |
4984 | codep++; | |
4985 | return; | |
4986 | } | |
4987 | prefixes = PREFIX_FWAIT; | |
4988 | break; | |
4989 | default: | |
4990 | return; | |
4991 | } | |
52b15da3 JH |
4992 | /* Rex is ignored when followed by another prefix. */ |
4993 | if (rex) | |
4994 | { | |
3e7d61b2 AM |
4995 | rex_used = rex; |
4996 | return; | |
52b15da3 JH |
4997 | } |
4998 | rex = newrex; | |
252b5132 RH |
4999 | codep++; |
5000 | } | |
5001 | } | |
5002 | ||
7d421014 ILT |
5003 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
5004 | prefix byte. */ | |
5005 | ||
5006 | static const char * | |
26ca5450 | 5007 | prefix_name (int pref, int sizeflag) |
7d421014 | 5008 | { |
0003779b L |
5009 | static const char *rexes [16] = |
5010 | { | |
5011 | "rex", /* 0x40 */ | |
5012 | "rex.B", /* 0x41 */ | |
5013 | "rex.X", /* 0x42 */ | |
5014 | "rex.XB", /* 0x43 */ | |
5015 | "rex.R", /* 0x44 */ | |
5016 | "rex.RB", /* 0x45 */ | |
5017 | "rex.RX", /* 0x46 */ | |
5018 | "rex.RXB", /* 0x47 */ | |
5019 | "rex.W", /* 0x48 */ | |
5020 | "rex.WB", /* 0x49 */ | |
5021 | "rex.WX", /* 0x4a */ | |
5022 | "rex.WXB", /* 0x4b */ | |
5023 | "rex.WR", /* 0x4c */ | |
5024 | "rex.WRB", /* 0x4d */ | |
5025 | "rex.WRX", /* 0x4e */ | |
5026 | "rex.WRXB", /* 0x4f */ | |
5027 | }; | |
5028 | ||
7d421014 ILT |
5029 | switch (pref) |
5030 | { | |
52b15da3 JH |
5031 | /* REX prefixes family. */ |
5032 | case 0x40: | |
52b15da3 | 5033 | case 0x41: |
52b15da3 | 5034 | case 0x42: |
52b15da3 | 5035 | case 0x43: |
52b15da3 | 5036 | case 0x44: |
52b15da3 | 5037 | case 0x45: |
52b15da3 | 5038 | case 0x46: |
52b15da3 | 5039 | case 0x47: |
52b15da3 | 5040 | case 0x48: |
52b15da3 | 5041 | case 0x49: |
52b15da3 | 5042 | case 0x4a: |
52b15da3 | 5043 | case 0x4b: |
52b15da3 | 5044 | case 0x4c: |
52b15da3 | 5045 | case 0x4d: |
52b15da3 | 5046 | case 0x4e: |
52b15da3 | 5047 | case 0x4f: |
0003779b | 5048 | return rexes [pref - 0x40]; |
7d421014 ILT |
5049 | case 0xf3: |
5050 | return "repz"; | |
5051 | case 0xf2: | |
5052 | return "repnz"; | |
5053 | case 0xf0: | |
5054 | return "lock"; | |
5055 | case 0x2e: | |
5056 | return "cs"; | |
5057 | case 0x36: | |
5058 | return "ss"; | |
5059 | case 0x3e: | |
5060 | return "ds"; | |
5061 | case 0x26: | |
5062 | return "es"; | |
5063 | case 0x64: | |
5064 | return "fs"; | |
5065 | case 0x65: | |
5066 | return "gs"; | |
5067 | case 0x66: | |
5068 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
5069 | case 0x67: | |
cb712a9e | 5070 | if (address_mode == mode_64bit) |
db6eb5be | 5071 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 5072 | else |
2888cb7a | 5073 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
5074 | case FWAIT_OPCODE: |
5075 | return "fwait"; | |
5076 | default: | |
5077 | return NULL; | |
5078 | } | |
5079 | } | |
5080 | ||
ce518a5f L |
5081 | static char op_out[MAX_OPERANDS][100]; |
5082 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 5083 | static int two_source_ops; |
ce518a5f L |
5084 | static bfd_vma op_address[MAX_OPERANDS]; |
5085 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 5086 | static bfd_vma start_pc; |
ce518a5f | 5087 | |
252b5132 RH |
5088 | /* |
5089 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
5090 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
5091 | * section of the "Virtual 8086 Mode" chapter.) | |
5092 | * 'pc' should be the address of this instruction, it will | |
5093 | * be used to print the target address if this is a relative jump or call | |
5094 | * The function returns the length of this instruction in bytes. | |
5095 | */ | |
5096 | ||
252b5132 | 5097 | static char intel_syntax; |
9d141669 | 5098 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
5099 | static char open_char; |
5100 | static char close_char; | |
5101 | static char separator_char; | |
5102 | static char scale_char; | |
5103 | ||
e396998b AM |
5104 | /* Here for backwards compatibility. When gdb stops using |
5105 | print_insn_i386_att and print_insn_i386_intel these functions can | |
5106 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 5107 | int |
26ca5450 | 5108 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
5109 | { |
5110 | intel_syntax = 0; | |
e396998b AM |
5111 | |
5112 | return print_insn (pc, info); | |
252b5132 RH |
5113 | } |
5114 | ||
5115 | int | |
26ca5450 | 5116 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
5117 | { |
5118 | intel_syntax = 1; | |
e396998b AM |
5119 | |
5120 | return print_insn (pc, info); | |
252b5132 RH |
5121 | } |
5122 | ||
e396998b | 5123 | int |
26ca5450 | 5124 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
5125 | { |
5126 | intel_syntax = -1; | |
5127 | ||
5128 | return print_insn (pc, info); | |
5129 | } | |
5130 | ||
f59a29b9 L |
5131 | void |
5132 | print_i386_disassembler_options (FILE *stream) | |
5133 | { | |
5134 | fprintf (stream, _("\n\ | |
5135 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
5136 | with the -M switch (multiple options should be separated by commas):\n")); | |
5137 | ||
5138 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
5139 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
5140 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
5141 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
5142 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
5143 | fprintf (stream, _(" att-mnemonic\n" |
5144 | " Display instruction in AT&T mnemonic\n")); | |
5145 | fprintf (stream, _(" intel-mnemonic\n" | |
5146 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
5147 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
5148 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
5149 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
5150 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
5151 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
5152 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5153 | } | |
5154 | ||
b844680a L |
5155 | /* Get a pointer to struct dis386 with a valid name. */ |
5156 | ||
5157 | static const struct dis386 * | |
8bb15339 | 5158 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a L |
5159 | { |
5160 | int index; | |
5161 | ||
5162 | if (dp->name != NULL) | |
5163 | return dp; | |
5164 | ||
5165 | switch (dp->op[0].bytemode) | |
5166 | { | |
1ceb70f8 L |
5167 | case USE_REG_TABLE: |
5168 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
5169 | break; | |
5170 | ||
5171 | case USE_MOD_TABLE: | |
5172 | index = modrm.mod == 0x3 ? 1 : 0; | |
5173 | dp = &mod_table[dp->op[1].bytemode][index]; | |
5174 | break; | |
5175 | ||
5176 | case USE_RM_TABLE: | |
5177 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
5178 | break; |
5179 | ||
4e7d34a6 | 5180 | case USE_PREFIX_TABLE: |
b844680a L |
5181 | index = 0; |
5182 | used_prefixes |= (prefixes & PREFIX_REPZ); | |
5183 | if (prefixes & PREFIX_REPZ) | |
5184 | { | |
5185 | index = 1; | |
5186 | repz_prefix = NULL; | |
5187 | } | |
5188 | else | |
5189 | { | |
5190 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before | |
5191 | PREFIX_DATA. */ | |
5192 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
5193 | if (prefixes & PREFIX_REPNZ) | |
5194 | { | |
5195 | index = 3; | |
5196 | repnz_prefix = NULL; | |
5197 | } | |
5198 | else | |
5199 | { | |
5200 | used_prefixes |= (prefixes & PREFIX_DATA); | |
5201 | if (prefixes & PREFIX_DATA) | |
5202 | { | |
5203 | index = 2; | |
5204 | data_prefix = NULL; | |
5205 | } | |
5206 | } | |
5207 | } | |
1ceb70f8 | 5208 | dp = &prefix_table[dp->op[1].bytemode][index]; |
b844680a L |
5209 | break; |
5210 | ||
4e7d34a6 | 5211 | case USE_X86_64_TABLE: |
b844680a L |
5212 | index = address_mode == mode_64bit ? 1 : 0; |
5213 | dp = &x86_64_table[dp->op[1].bytemode][index]; | |
5214 | break; | |
5215 | ||
4e7d34a6 | 5216 | case USE_3BYTE_TABLE: |
8bb15339 L |
5217 | FETCH_DATA (info, codep + 2); |
5218 | index = *codep++; | |
5219 | dp = &three_byte_table[dp->op[1].bytemode][index]; | |
5220 | modrm.mod = (*codep >> 6) & 3; | |
5221 | modrm.reg = (*codep >> 3) & 7; | |
5222 | modrm.rm = *codep & 7; | |
5223 | break; | |
5224 | ||
b844680a L |
5225 | default: |
5226 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
5227 | return NULL; | |
5228 | } | |
5229 | ||
5230 | if (dp->name != NULL) | |
5231 | return dp; | |
5232 | else | |
8bb15339 | 5233 | return get_valid_dis386 (dp, info); |
b844680a L |
5234 | } |
5235 | ||
e396998b | 5236 | static int |
26ca5450 | 5237 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 5238 | { |
2da11e11 | 5239 | const struct dis386 *dp; |
252b5132 | 5240 | int i; |
ce518a5f | 5241 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 5242 | int needcomma; |
e396998b AM |
5243 | int sizeflag; |
5244 | const char *p; | |
252b5132 | 5245 | struct dis_private priv; |
eec0f4ca | 5246 | unsigned char op; |
b844680a L |
5247 | char prefix_obuf[32]; |
5248 | char *prefix_obufp; | |
252b5132 | 5249 | |
cb712a9e L |
5250 | if (info->mach == bfd_mach_x86_64_intel_syntax |
5251 | || info->mach == bfd_mach_x86_64) | |
5252 | address_mode = mode_64bit; | |
5253 | else | |
5254 | address_mode = mode_32bit; | |
52b15da3 | 5255 | |
8373f971 | 5256 | if (intel_syntax == (char) -1) |
e396998b AM |
5257 | intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax |
5258 | || info->mach == bfd_mach_x86_64_intel_syntax); | |
5259 | ||
2da11e11 | 5260 | if (info->mach == bfd_mach_i386_i386 |
52b15da3 JH |
5261 | || info->mach == bfd_mach_x86_64 |
5262 | || info->mach == bfd_mach_i386_i386_intel_syntax | |
5263 | || info->mach == bfd_mach_x86_64_intel_syntax) | |
e396998b | 5264 | priv.orig_sizeflag = AFLAG | DFLAG; |
2da11e11 | 5265 | else if (info->mach == bfd_mach_i386_i8086) |
e396998b | 5266 | priv.orig_sizeflag = 0; |
2da11e11 AM |
5267 | else |
5268 | abort (); | |
e396998b AM |
5269 | |
5270 | for (p = info->disassembler_options; p != NULL; ) | |
5271 | { | |
0112cd26 | 5272 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 5273 | { |
cb712a9e | 5274 | address_mode = mode_64bit; |
e396998b AM |
5275 | priv.orig_sizeflag = AFLAG | DFLAG; |
5276 | } | |
0112cd26 | 5277 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 5278 | { |
cb712a9e | 5279 | address_mode = mode_32bit; |
e396998b AM |
5280 | priv.orig_sizeflag = AFLAG | DFLAG; |
5281 | } | |
0112cd26 | 5282 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 5283 | { |
cb712a9e | 5284 | address_mode = mode_16bit; |
e396998b AM |
5285 | priv.orig_sizeflag = 0; |
5286 | } | |
0112cd26 | 5287 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
5288 | { |
5289 | intel_syntax = 1; | |
9d141669 L |
5290 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
5291 | intel_mnemonic = 1; | |
e396998b | 5292 | } |
0112cd26 | 5293 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
5294 | { |
5295 | intel_syntax = 0; | |
9d141669 L |
5296 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
5297 | intel_mnemonic = 0; | |
e396998b | 5298 | } |
0112cd26 | 5299 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 5300 | { |
f59a29b9 L |
5301 | if (address_mode == mode_64bit) |
5302 | { | |
5303 | if (p[4] == '3' && p[5] == '2') | |
5304 | priv.orig_sizeflag &= ~AFLAG; | |
5305 | else if (p[4] == '6' && p[5] == '4') | |
5306 | priv.orig_sizeflag |= AFLAG; | |
5307 | } | |
5308 | else | |
5309 | { | |
5310 | if (p[4] == '1' && p[5] == '6') | |
5311 | priv.orig_sizeflag &= ~AFLAG; | |
5312 | else if (p[4] == '3' && p[5] == '2') | |
5313 | priv.orig_sizeflag |= AFLAG; | |
5314 | } | |
e396998b | 5315 | } |
0112cd26 | 5316 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
5317 | { |
5318 | if (p[4] == '1' && p[5] == '6') | |
5319 | priv.orig_sizeflag &= ~DFLAG; | |
5320 | else if (p[4] == '3' && p[5] == '2') | |
5321 | priv.orig_sizeflag |= DFLAG; | |
5322 | } | |
0112cd26 | 5323 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
5324 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
5325 | ||
5326 | p = strchr (p, ','); | |
5327 | if (p != NULL) | |
5328 | p++; | |
5329 | } | |
5330 | ||
5331 | if (intel_syntax) | |
5332 | { | |
5333 | names64 = intel_names64; | |
5334 | names32 = intel_names32; | |
5335 | names16 = intel_names16; | |
5336 | names8 = intel_names8; | |
5337 | names8rex = intel_names8rex; | |
5338 | names_seg = intel_names_seg; | |
db51cc60 L |
5339 | index64 = intel_index64; |
5340 | index32 = intel_index32; | |
e396998b AM |
5341 | index16 = intel_index16; |
5342 | open_char = '['; | |
5343 | close_char = ']'; | |
5344 | separator_char = '+'; | |
5345 | scale_char = '*'; | |
5346 | } | |
5347 | else | |
5348 | { | |
5349 | names64 = att_names64; | |
5350 | names32 = att_names32; | |
5351 | names16 = att_names16; | |
5352 | names8 = att_names8; | |
5353 | names8rex = att_names8rex; | |
5354 | names_seg = att_names_seg; | |
db51cc60 L |
5355 | index64 = att_index64; |
5356 | index32 = att_index32; | |
e396998b AM |
5357 | index16 = att_index16; |
5358 | open_char = '('; | |
5359 | close_char = ')'; | |
5360 | separator_char = ','; | |
5361 | scale_char = ','; | |
5362 | } | |
2da11e11 | 5363 | |
4fe53c98 | 5364 | /* The output looks better if we put 7 bytes on a line, since that |
c608c12e | 5365 | puts most long word instructions on a single line. */ |
4fe53c98 | 5366 | info->bytes_per_line = 7; |
252b5132 | 5367 | |
26ca5450 | 5368 | info->private_data = &priv; |
252b5132 RH |
5369 | priv.max_fetched = priv.the_buffer; |
5370 | priv.insn_start = pc; | |
252b5132 RH |
5371 | |
5372 | obuf[0] = 0; | |
ce518a5f L |
5373 | for (i = 0; i < MAX_OPERANDS; ++i) |
5374 | { | |
5375 | op_out[i][0] = 0; | |
5376 | op_index[i] = -1; | |
5377 | } | |
252b5132 RH |
5378 | |
5379 | the_info = info; | |
5380 | start_pc = pc; | |
e396998b AM |
5381 | start_codep = priv.the_buffer; |
5382 | codep = priv.the_buffer; | |
252b5132 | 5383 | |
5076851f ILT |
5384 | if (setjmp (priv.bailout) != 0) |
5385 | { | |
7d421014 ILT |
5386 | const char *name; |
5387 | ||
5076851f | 5388 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
5389 | means we have an incomplete instruction of some sort. Just |
5390 | print the first byte as a prefix or a .byte pseudo-op. */ | |
5391 | if (codep > priv.the_buffer) | |
5076851f | 5392 | { |
e396998b | 5393 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
5394 | if (name != NULL) |
5395 | (*info->fprintf_func) (info->stream, "%s", name); | |
5396 | else | |
5076851f | 5397 | { |
7d421014 ILT |
5398 | /* Just print the first byte as a .byte instruction. */ |
5399 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 5400 | (unsigned int) priv.the_buffer[0]); |
5076851f | 5401 | } |
5076851f | 5402 | |
7d421014 | 5403 | return 1; |
5076851f ILT |
5404 | } |
5405 | ||
5406 | return -1; | |
5407 | } | |
5408 | ||
52b15da3 | 5409 | obufp = obuf; |
252b5132 RH |
5410 | ckprefix (); |
5411 | ||
5412 | insn_codep = codep; | |
e396998b | 5413 | sizeflag = priv.orig_sizeflag; |
252b5132 RH |
5414 | |
5415 | FETCH_DATA (info, codep + 1); | |
5416 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
5417 | ||
3e7d61b2 AM |
5418 | if (((prefixes & PREFIX_FWAIT) |
5419 | && ((*codep < 0xd8) || (*codep > 0xdf))) | |
5420 | || (rex && rex_used)) | |
252b5132 | 5421 | { |
7d421014 ILT |
5422 | const char *name; |
5423 | ||
3e7d61b2 AM |
5424 | /* fwait not followed by floating point instruction, or rex followed |
5425 | by other prefixes. Print the first prefix. */ | |
e396998b | 5426 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
5427 | if (name == NULL) |
5428 | name = INTERNAL_DISASSEMBLER_ERROR; | |
5429 | (*info->fprintf_func) (info->stream, "%s", name); | |
5430 | return 1; | |
252b5132 RH |
5431 | } |
5432 | ||
eec0f4ca | 5433 | op = 0; |
252b5132 RH |
5434 | if (*codep == 0x0f) |
5435 | { | |
eec0f4ca | 5436 | unsigned char threebyte; |
252b5132 | 5437 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
5438 | threebyte = *++codep; |
5439 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 5440 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 5441 | codep++; |
252b5132 RH |
5442 | } |
5443 | else | |
5444 | { | |
6439fc28 | 5445 | dp = &dis386[*codep]; |
252b5132 | 5446 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 5447 | codep++; |
252b5132 | 5448 | } |
246c51aa | 5449 | |
b844680a | 5450 | if ((prefixes & PREFIX_REPZ)) |
7d421014 | 5451 | { |
b844680a | 5452 | repz_prefix = "repz "; |
7d421014 ILT |
5453 | used_prefixes |= PREFIX_REPZ; |
5454 | } | |
b844680a L |
5455 | else |
5456 | repz_prefix = NULL; | |
5457 | ||
5458 | if ((prefixes & PREFIX_REPNZ)) | |
7d421014 | 5459 | { |
b844680a | 5460 | repnz_prefix = "repnz "; |
7d421014 ILT |
5461 | used_prefixes |= PREFIX_REPNZ; |
5462 | } | |
b844680a L |
5463 | else |
5464 | repnz_prefix = NULL; | |
050dfa73 | 5465 | |
b844680a | 5466 | if ((prefixes & PREFIX_LOCK)) |
7d421014 | 5467 | { |
b844680a | 5468 | lock_prefix = "lock "; |
7d421014 ILT |
5469 | used_prefixes |= PREFIX_LOCK; |
5470 | } | |
b844680a L |
5471 | else |
5472 | lock_prefix = NULL; | |
c608c12e | 5473 | |
b844680a | 5474 | addr_prefix = NULL; |
c608c12e AM |
5475 | if (prefixes & PREFIX_ADDR) |
5476 | { | |
5477 | sizeflag ^= AFLAG; | |
ce518a5f | 5478 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 5479 | { |
cb712a9e | 5480 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
b844680a | 5481 | addr_prefix = "addr32 "; |
3ffd33cf | 5482 | else |
b844680a | 5483 | addr_prefix = "addr16 "; |
3ffd33cf AM |
5484 | used_prefixes |= PREFIX_ADDR; |
5485 | } | |
5486 | } | |
5487 | ||
b844680a L |
5488 | data_prefix = NULL; |
5489 | if ((prefixes & PREFIX_DATA)) | |
3ffd33cf AM |
5490 | { |
5491 | sizeflag ^= DFLAG; | |
ce518a5f L |
5492 | if (dp->op[2].bytemode == cond_jump_mode |
5493 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 5494 | && !intel_syntax) |
3ffd33cf AM |
5495 | { |
5496 | if (sizeflag & DFLAG) | |
b844680a | 5497 | data_prefix = "data32 "; |
3ffd33cf | 5498 | else |
b844680a | 5499 | data_prefix = "data16 "; |
3ffd33cf AM |
5500 | used_prefixes |= PREFIX_DATA; |
5501 | } | |
5502 | } | |
5503 | ||
8bb15339 | 5504 | if (need_modrm) |
252b5132 RH |
5505 | { |
5506 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
5507 | modrm.mod = (*codep >> 6) & 3; |
5508 | modrm.reg = (*codep >> 3) & 7; | |
5509 | modrm.rm = *codep & 7; | |
252b5132 RH |
5510 | } |
5511 | ||
ce518a5f | 5512 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 RH |
5513 | { |
5514 | dofloat (sizeflag); | |
5515 | } | |
5516 | else | |
5517 | { | |
8bb15339 | 5518 | dp = get_valid_dis386 (dp, info); |
b844680a | 5519 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
ce518a5f L |
5520 | { |
5521 | for (i = 0; i < MAX_OPERANDS; ++i) | |
5522 | { | |
246c51aa | 5523 | obufp = op_out[i]; |
ce518a5f L |
5524 | op_ad = MAX_OPERANDS - 1 - i; |
5525 | if (dp->op[i].rtn) | |
5526 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
5527 | } | |
6439fc28 | 5528 | } |
252b5132 RH |
5529 | } |
5530 | ||
7d421014 ILT |
5531 | /* See if any prefixes were not used. If so, print the first one |
5532 | separately. If we don't do this, we'll wind up printing an | |
5533 | instruction stream which does not precisely correspond to the | |
5534 | bytes we are disassembling. */ | |
5535 | if ((prefixes & ~used_prefixes) != 0) | |
5536 | { | |
5537 | const char *name; | |
5538 | ||
e396998b | 5539 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
5540 | if (name == NULL) |
5541 | name = INTERNAL_DISASSEMBLER_ERROR; | |
5542 | (*info->fprintf_func) (info->stream, "%s", name); | |
5543 | return 1; | |
5544 | } | |
52b15da3 JH |
5545 | if (rex & ~rex_used) |
5546 | { | |
5547 | const char *name; | |
e396998b | 5548 | name = prefix_name (rex | 0x40, priv.orig_sizeflag); |
52b15da3 JH |
5549 | if (name == NULL) |
5550 | name = INTERNAL_DISASSEMBLER_ERROR; | |
5551 | (*info->fprintf_func) (info->stream, "%s ", name); | |
5552 | } | |
7d421014 | 5553 | |
b844680a L |
5554 | prefix_obuf[0] = 0; |
5555 | prefix_obufp = prefix_obuf; | |
5556 | if (lock_prefix) | |
5557 | prefix_obufp = stpcpy (prefix_obufp, lock_prefix); | |
5558 | if (repz_prefix) | |
5559 | prefix_obufp = stpcpy (prefix_obufp, repz_prefix); | |
5560 | if (repnz_prefix) | |
5561 | prefix_obufp = stpcpy (prefix_obufp, repnz_prefix); | |
5562 | if (addr_prefix) | |
5563 | prefix_obufp = stpcpy (prefix_obufp, addr_prefix); | |
5564 | if (data_prefix) | |
5565 | prefix_obufp = stpcpy (prefix_obufp, data_prefix); | |
5566 | ||
5567 | if (prefix_obuf[0] != 0) | |
5568 | (*info->fprintf_func) (info->stream, "%s", prefix_obuf); | |
5569 | ||
252b5132 | 5570 | obufp = obuf + strlen (obuf); |
b844680a | 5571 | for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++) |
252b5132 RH |
5572 | oappend (" "); |
5573 | oappend (" "); | |
5574 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
5575 | ||
5576 | /* The enter and bound instructions are printed with operands in the same | |
5577 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 5578 | if (intel_syntax || two_source_ops) |
252b5132 | 5579 | { |
185b1163 L |
5580 | bfd_vma riprel; |
5581 | ||
ce518a5f L |
5582 | for (i = 0; i < MAX_OPERANDS; ++i) |
5583 | op_txt[i] = op_out[i]; | |
246c51aa | 5584 | |
ce518a5f L |
5585 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
5586 | { | |
5587 | op_ad = op_index[i]; | |
5588 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
5589 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
5590 | riprel = op_riprel[i]; |
5591 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
5592 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 5593 | } |
252b5132 RH |
5594 | } |
5595 | else | |
5596 | { | |
ce518a5f L |
5597 | for (i = 0; i < MAX_OPERANDS; ++i) |
5598 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; | |
050dfa73 MM |
5599 | } |
5600 | ||
ce518a5f L |
5601 | needcomma = 0; |
5602 | for (i = 0; i < MAX_OPERANDS; ++i) | |
5603 | if (*op_txt[i]) | |
5604 | { | |
5605 | if (needcomma) | |
5606 | (*info->fprintf_func) (info->stream, ","); | |
5607 | if (op_index[i] != -1 && !op_riprel[i]) | |
5608 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
5609 | else | |
5610 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
5611 | needcomma = 1; | |
5612 | } | |
050dfa73 | 5613 | |
ce518a5f | 5614 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
5615 | if (op_index[i] != -1 && op_riprel[i]) |
5616 | { | |
5617 | (*info->fprintf_func) (info->stream, " # "); | |
5618 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
5619 | + op_address[op_index[i]]), info); | |
185b1163 | 5620 | break; |
52b15da3 | 5621 | } |
e396998b | 5622 | return codep - priv.the_buffer; |
252b5132 RH |
5623 | } |
5624 | ||
6439fc28 | 5625 | static const char *float_mem[] = { |
252b5132 | 5626 | /* d8 */ |
7c52e0e8 L |
5627 | "fadd{s|}", |
5628 | "fmul{s|}", | |
5629 | "fcom{s|}", | |
5630 | "fcomp{s|}", | |
5631 | "fsub{s|}", | |
5632 | "fsubr{s|}", | |
5633 | "fdiv{s|}", | |
5634 | "fdivr{s|}", | |
db6eb5be | 5635 | /* d9 */ |
7c52e0e8 | 5636 | "fld{s|}", |
252b5132 | 5637 | "(bad)", |
7c52e0e8 L |
5638 | "fst{s|}", |
5639 | "fstp{s|}", | |
9306ca4a | 5640 | "fldenvIC", |
252b5132 | 5641 | "fldcw", |
9306ca4a | 5642 | "fNstenvIC", |
252b5132 RH |
5643 | "fNstcw", |
5644 | /* da */ | |
7c52e0e8 L |
5645 | "fiadd{l|}", |
5646 | "fimul{l|}", | |
5647 | "ficom{l|}", | |
5648 | "ficomp{l|}", | |
5649 | "fisub{l|}", | |
5650 | "fisubr{l|}", | |
5651 | "fidiv{l|}", | |
5652 | "fidivr{l|}", | |
252b5132 | 5653 | /* db */ |
7c52e0e8 L |
5654 | "fild{l|}", |
5655 | "fisttp{l|}", | |
5656 | "fist{l|}", | |
5657 | "fistp{l|}", | |
252b5132 | 5658 | "(bad)", |
6439fc28 | 5659 | "fld{t||t|}", |
252b5132 | 5660 | "(bad)", |
6439fc28 | 5661 | "fstp{t||t|}", |
252b5132 | 5662 | /* dc */ |
7c52e0e8 L |
5663 | "fadd{l|}", |
5664 | "fmul{l|}", | |
5665 | "fcom{l|}", | |
5666 | "fcomp{l|}", | |
5667 | "fsub{l|}", | |
5668 | "fsubr{l|}", | |
5669 | "fdiv{l|}", | |
5670 | "fdivr{l|}", | |
252b5132 | 5671 | /* dd */ |
7c52e0e8 L |
5672 | "fld{l|}", |
5673 | "fisttp{ll|}", | |
5674 | "fst{l||}", | |
5675 | "fstp{l|}", | |
9306ca4a | 5676 | "frstorIC", |
252b5132 | 5677 | "(bad)", |
9306ca4a | 5678 | "fNsaveIC", |
252b5132 RH |
5679 | "fNstsw", |
5680 | /* de */ | |
5681 | "fiadd", | |
5682 | "fimul", | |
5683 | "ficom", | |
5684 | "ficomp", | |
5685 | "fisub", | |
5686 | "fisubr", | |
5687 | "fidiv", | |
5688 | "fidivr", | |
5689 | /* df */ | |
5690 | "fild", | |
ca164297 | 5691 | "fisttp", |
252b5132 RH |
5692 | "fist", |
5693 | "fistp", | |
5694 | "fbld", | |
7c52e0e8 | 5695 | "fild{ll|}", |
252b5132 | 5696 | "fbstp", |
7c52e0e8 | 5697 | "fistp{ll|}", |
1d9f512f AM |
5698 | }; |
5699 | ||
5700 | static const unsigned char float_mem_mode[] = { | |
5701 | /* d8 */ | |
5702 | d_mode, | |
5703 | d_mode, | |
5704 | d_mode, | |
5705 | d_mode, | |
5706 | d_mode, | |
5707 | d_mode, | |
5708 | d_mode, | |
5709 | d_mode, | |
5710 | /* d9 */ | |
5711 | d_mode, | |
5712 | 0, | |
5713 | d_mode, | |
5714 | d_mode, | |
5715 | 0, | |
5716 | w_mode, | |
5717 | 0, | |
5718 | w_mode, | |
5719 | /* da */ | |
5720 | d_mode, | |
5721 | d_mode, | |
5722 | d_mode, | |
5723 | d_mode, | |
5724 | d_mode, | |
5725 | d_mode, | |
5726 | d_mode, | |
5727 | d_mode, | |
5728 | /* db */ | |
5729 | d_mode, | |
5730 | d_mode, | |
5731 | d_mode, | |
5732 | d_mode, | |
5733 | 0, | |
9306ca4a | 5734 | t_mode, |
1d9f512f | 5735 | 0, |
9306ca4a | 5736 | t_mode, |
1d9f512f AM |
5737 | /* dc */ |
5738 | q_mode, | |
5739 | q_mode, | |
5740 | q_mode, | |
5741 | q_mode, | |
5742 | q_mode, | |
5743 | q_mode, | |
5744 | q_mode, | |
5745 | q_mode, | |
5746 | /* dd */ | |
5747 | q_mode, | |
5748 | q_mode, | |
5749 | q_mode, | |
5750 | q_mode, | |
5751 | 0, | |
5752 | 0, | |
5753 | 0, | |
5754 | w_mode, | |
5755 | /* de */ | |
5756 | w_mode, | |
5757 | w_mode, | |
5758 | w_mode, | |
5759 | w_mode, | |
5760 | w_mode, | |
5761 | w_mode, | |
5762 | w_mode, | |
5763 | w_mode, | |
5764 | /* df */ | |
5765 | w_mode, | |
5766 | w_mode, | |
5767 | w_mode, | |
5768 | w_mode, | |
9306ca4a | 5769 | t_mode, |
1d9f512f | 5770 | q_mode, |
9306ca4a | 5771 | t_mode, |
1d9f512f | 5772 | q_mode |
252b5132 RH |
5773 | }; |
5774 | ||
ce518a5f L |
5775 | #define ST { OP_ST, 0 } |
5776 | #define STi { OP_STi, 0 } | |
252b5132 | 5777 | |
4efba78c L |
5778 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
5779 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
5780 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
5781 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
5782 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
5783 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
5784 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
5785 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
5786 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 5787 | |
2da11e11 | 5788 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
5789 | /* d8 */ |
5790 | { | |
ce518a5f L |
5791 | { "fadd", { ST, STi } }, |
5792 | { "fmul", { ST, STi } }, | |
5793 | { "fcom", { STi } }, | |
5794 | { "fcomp", { STi } }, | |
5795 | { "fsub", { ST, STi } }, | |
5796 | { "fsubr", { ST, STi } }, | |
5797 | { "fdiv", { ST, STi } }, | |
5798 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
5799 | }, |
5800 | /* d9 */ | |
5801 | { | |
ce518a5f L |
5802 | { "fld", { STi } }, |
5803 | { "fxch", { STi } }, | |
252b5132 | 5804 | { FGRPd9_2 }, |
ce518a5f | 5805 | { "(bad)", { XX } }, |
252b5132 RH |
5806 | { FGRPd9_4 }, |
5807 | { FGRPd9_5 }, | |
5808 | { FGRPd9_6 }, | |
5809 | { FGRPd9_7 }, | |
5810 | }, | |
5811 | /* da */ | |
5812 | { | |
ce518a5f L |
5813 | { "fcmovb", { ST, STi } }, |
5814 | { "fcmove", { ST, STi } }, | |
5815 | { "fcmovbe",{ ST, STi } }, | |
5816 | { "fcmovu", { ST, STi } }, | |
5817 | { "(bad)", { XX } }, | |
252b5132 | 5818 | { FGRPda_5 }, |
ce518a5f L |
5819 | { "(bad)", { XX } }, |
5820 | { "(bad)", { XX } }, | |
252b5132 RH |
5821 | }, |
5822 | /* db */ | |
5823 | { | |
ce518a5f L |
5824 | { "fcmovnb",{ ST, STi } }, |
5825 | { "fcmovne",{ ST, STi } }, | |
5826 | { "fcmovnbe",{ ST, STi } }, | |
5827 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 5828 | { FGRPdb_4 }, |
ce518a5f L |
5829 | { "fucomi", { ST, STi } }, |
5830 | { "fcomi", { ST, STi } }, | |
5831 | { "(bad)", { XX } }, | |
252b5132 RH |
5832 | }, |
5833 | /* dc */ | |
5834 | { | |
ce518a5f L |
5835 | { "fadd", { STi, ST } }, |
5836 | { "fmul", { STi, ST } }, | |
5837 | { "(bad)", { XX } }, | |
5838 | { "(bad)", { XX } }, | |
9d141669 L |
5839 | { "fsub!M", { STi, ST } }, |
5840 | { "fsubM", { STi, ST } }, | |
5841 | { "fdiv!M", { STi, ST } }, | |
5842 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
5843 | }, |
5844 | /* dd */ | |
5845 | { | |
ce518a5f L |
5846 | { "ffree", { STi } }, |
5847 | { "(bad)", { XX } }, | |
5848 | { "fst", { STi } }, | |
5849 | { "fstp", { STi } }, | |
5850 | { "fucom", { STi } }, | |
5851 | { "fucomp", { STi } }, | |
5852 | { "(bad)", { XX } }, | |
5853 | { "(bad)", { XX } }, | |
252b5132 RH |
5854 | }, |
5855 | /* de */ | |
5856 | { | |
ce518a5f L |
5857 | { "faddp", { STi, ST } }, |
5858 | { "fmulp", { STi, ST } }, | |
5859 | { "(bad)", { XX } }, | |
252b5132 | 5860 | { FGRPde_3 }, |
9d141669 L |
5861 | { "fsub!Mp", { STi, ST } }, |
5862 | { "fsubMp", { STi, ST } }, | |
5863 | { "fdiv!Mp", { STi, ST } }, | |
5864 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
5865 | }, |
5866 | /* df */ | |
5867 | { | |
ce518a5f L |
5868 | { "ffreep", { STi } }, |
5869 | { "(bad)", { XX } }, | |
5870 | { "(bad)", { XX } }, | |
5871 | { "(bad)", { XX } }, | |
252b5132 | 5872 | { FGRPdf_4 }, |
ce518a5f L |
5873 | { "fucomip", { ST, STi } }, |
5874 | { "fcomip", { ST, STi } }, | |
5875 | { "(bad)", { XX } }, | |
252b5132 RH |
5876 | }, |
5877 | }; | |
5878 | ||
252b5132 RH |
5879 | static char *fgrps[][8] = { |
5880 | /* d9_2 0 */ | |
5881 | { | |
5882 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
5883 | }, | |
5884 | ||
5885 | /* d9_4 1 */ | |
5886 | { | |
5887 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
5888 | }, | |
5889 | ||
5890 | /* d9_5 2 */ | |
5891 | { | |
5892 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
5893 | }, | |
5894 | ||
5895 | /* d9_6 3 */ | |
5896 | { | |
5897 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
5898 | }, | |
5899 | ||
5900 | /* d9_7 4 */ | |
5901 | { | |
5902 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
5903 | }, | |
5904 | ||
5905 | /* da_5 5 */ | |
5906 | { | |
5907 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
5908 | }, | |
5909 | ||
5910 | /* db_4 6 */ | |
5911 | { | |
5912 | "feni(287 only)","fdisi(287 only)","fNclex","fNinit", | |
5913 | "fNsetpm(287 only)","(bad)","(bad)","(bad)", | |
5914 | }, | |
5915 | ||
5916 | /* de_3 7 */ | |
5917 | { | |
5918 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
5919 | }, | |
5920 | ||
5921 | /* df_4 8 */ | |
5922 | { | |
5923 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
5924 | }, | |
5925 | }; | |
5926 | ||
b844680a L |
5927 | static void |
5928 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
5929 | int sizeflag ATTRIBUTE_UNUSED) | |
5930 | { | |
5931 | /* Skip mod/rm byte. */ | |
5932 | MODRM_CHECK; | |
5933 | codep++; | |
5934 | } | |
5935 | ||
252b5132 | 5936 | static void |
26ca5450 | 5937 | dofloat (int sizeflag) |
252b5132 | 5938 | { |
2da11e11 | 5939 | const struct dis386 *dp; |
252b5132 RH |
5940 | unsigned char floatop; |
5941 | ||
5942 | floatop = codep[-1]; | |
5943 | ||
7967e09e | 5944 | if (modrm.mod != 3) |
252b5132 | 5945 | { |
7967e09e | 5946 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
5947 | |
5948 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 5949 | obufp = op_out[0]; |
6e50d963 | 5950 | op_ad = 2; |
1d9f512f | 5951 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
5952 | return; |
5953 | } | |
6608db57 | 5954 | /* Skip mod/rm byte. */ |
4bba6815 | 5955 | MODRM_CHECK; |
252b5132 RH |
5956 | codep++; |
5957 | ||
7967e09e | 5958 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
5959 | if (dp->name == NULL) |
5960 | { | |
7967e09e | 5961 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 5962 | |
6608db57 | 5963 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 5964 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 5965 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
5966 | } |
5967 | else | |
5968 | { | |
5969 | putop (dp->name, sizeflag); | |
5970 | ||
ce518a5f | 5971 | obufp = op_out[0]; |
6e50d963 | 5972 | op_ad = 2; |
ce518a5f L |
5973 | if (dp->op[0].rtn) |
5974 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 5975 | |
ce518a5f | 5976 | obufp = op_out[1]; |
6e50d963 | 5977 | op_ad = 1; |
ce518a5f L |
5978 | if (dp->op[1].rtn) |
5979 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
5980 | } |
5981 | } | |
5982 | ||
252b5132 | 5983 | static void |
26ca5450 | 5984 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 5985 | { |
422673a9 | 5986 | oappend ("%st" + intel_syntax); |
252b5132 RH |
5987 | } |
5988 | ||
252b5132 | 5989 | static void |
26ca5450 | 5990 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 5991 | { |
7967e09e | 5992 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 5993 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
5994 | } |
5995 | ||
6608db57 | 5996 | /* Capital letters in template are macros. */ |
6439fc28 | 5997 | static int |
26ca5450 | 5998 | putop (const char *template, int sizeflag) |
252b5132 | 5999 | { |
2da11e11 | 6000 | const char *p; |
9306ca4a | 6001 | int alt = 0; |
9d141669 | 6002 | int cond = 1; |
98b528ac L |
6003 | unsigned int l = 0, len = 1; |
6004 | char last[4]; | |
6005 | ||
6006 | #define SAVE_LAST(c) \ | |
6007 | if (l < len && l < sizeof (last)) \ | |
6008 | last[l++] = c; \ | |
6009 | else \ | |
6010 | abort (); | |
252b5132 RH |
6011 | |
6012 | for (p = template; *p; p++) | |
6013 | { | |
6014 | switch (*p) | |
6015 | { | |
6016 | default: | |
6017 | *obufp++ = *p; | |
6018 | break; | |
98b528ac L |
6019 | case '%': |
6020 | len++; | |
6021 | break; | |
9d141669 L |
6022 | case '!': |
6023 | cond = 0; | |
6024 | break; | |
6439fc28 AM |
6025 | case '{': |
6026 | alt = 0; | |
6027 | if (intel_syntax) | |
6439fc28 AM |
6028 | { |
6029 | while (*++p != '|') | |
7c52e0e8 L |
6030 | if (*p == '}' || *p == '\0') |
6031 | abort (); | |
6439fc28 | 6032 | } |
9306ca4a JB |
6033 | /* Fall through. */ |
6034 | case 'I': | |
6035 | alt = 1; | |
6036 | continue; | |
6439fc28 AM |
6037 | case '|': |
6038 | while (*++p != '}') | |
6039 | { | |
6040 | if (*p == '\0') | |
6041 | abort (); | |
6042 | } | |
6043 | break; | |
6044 | case '}': | |
6045 | break; | |
252b5132 | 6046 | case 'A': |
db6eb5be AM |
6047 | if (intel_syntax) |
6048 | break; | |
7967e09e | 6049 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
6050 | *obufp++ = 'b'; |
6051 | break; | |
6052 | case 'B': | |
db6eb5be AM |
6053 | if (intel_syntax) |
6054 | break; | |
252b5132 RH |
6055 | if (sizeflag & SUFFIX_ALWAYS) |
6056 | *obufp++ = 'b'; | |
252b5132 | 6057 | break; |
9306ca4a JB |
6058 | case 'C': |
6059 | if (intel_syntax && !alt) | |
6060 | break; | |
6061 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
6062 | { | |
6063 | if (sizeflag & DFLAG) | |
6064 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
6065 | else | |
6066 | *obufp++ = intel_syntax ? 'w' : 's'; | |
6067 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6068 | } | |
6069 | break; | |
ed7841b3 JB |
6070 | case 'D': |
6071 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
6072 | break; | |
161a04f6 | 6073 | USED_REX (REX_W); |
7967e09e | 6074 | if (modrm.mod == 3) |
ed7841b3 | 6075 | { |
161a04f6 | 6076 | if (rex & REX_W) |
ed7841b3 JB |
6077 | *obufp++ = 'q'; |
6078 | else if (sizeflag & DFLAG) | |
6079 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
6080 | else | |
6081 | *obufp++ = 'w'; | |
6082 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6083 | } | |
6084 | else | |
6085 | *obufp++ = 'w'; | |
6086 | break; | |
252b5132 | 6087 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 6088 | if (address_mode == mode_64bit) |
c1a64871 JH |
6089 | { |
6090 | if (sizeflag & AFLAG) | |
6091 | *obufp++ = 'r'; | |
6092 | else | |
6093 | *obufp++ = 'e'; | |
6094 | } | |
6095 | else | |
6096 | if (sizeflag & AFLAG) | |
6097 | *obufp++ = 'e'; | |
3ffd33cf AM |
6098 | used_prefixes |= (prefixes & PREFIX_ADDR); |
6099 | break; | |
6100 | case 'F': | |
db6eb5be AM |
6101 | if (intel_syntax) |
6102 | break; | |
e396998b | 6103 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
6104 | { |
6105 | if (sizeflag & AFLAG) | |
cb712a9e | 6106 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 6107 | else |
cb712a9e | 6108 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
6109 | used_prefixes |= (prefixes & PREFIX_ADDR); |
6110 | } | |
252b5132 | 6111 | break; |
52fd6d94 JB |
6112 | case 'G': |
6113 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
6114 | break; | |
161a04f6 | 6115 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
6116 | *obufp++ = 'l'; |
6117 | else | |
6118 | *obufp++ = 'w'; | |
161a04f6 | 6119 | if (!(rex & REX_W)) |
52fd6d94 JB |
6120 | used_prefixes |= (prefixes & PREFIX_DATA); |
6121 | break; | |
5dd0794d | 6122 | case 'H': |
db6eb5be AM |
6123 | if (intel_syntax) |
6124 | break; | |
5dd0794d AM |
6125 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
6126 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
6127 | { | |
6128 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
6129 | *obufp++ = ','; | |
6130 | *obufp++ = 'p'; | |
6131 | if (prefixes & PREFIX_DS) | |
6132 | *obufp++ = 't'; | |
6133 | else | |
6134 | *obufp++ = 'n'; | |
6135 | } | |
6136 | break; | |
9306ca4a JB |
6137 | case 'J': |
6138 | if (intel_syntax) | |
6139 | break; | |
6140 | *obufp++ = 'l'; | |
6141 | break; | |
42903f7f L |
6142 | case 'K': |
6143 | USED_REX (REX_W); | |
6144 | if (rex & REX_W) | |
6145 | *obufp++ = 'q'; | |
6146 | else | |
6147 | *obufp++ = 'd'; | |
6148 | break; | |
6dd5059a L |
6149 | case 'Z': |
6150 | if (intel_syntax) | |
6151 | break; | |
6152 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
6153 | { | |
6154 | *obufp++ = 'q'; | |
6155 | break; | |
6156 | } | |
6157 | /* Fall through. */ | |
98b528ac | 6158 | goto case_L; |
252b5132 | 6159 | case 'L': |
98b528ac L |
6160 | if (l != 0 || len != 1) |
6161 | { | |
6162 | SAVE_LAST (*p); | |
6163 | break; | |
6164 | } | |
6165 | case_L: | |
db6eb5be AM |
6166 | if (intel_syntax) |
6167 | break; | |
252b5132 RH |
6168 | if (sizeflag & SUFFIX_ALWAYS) |
6169 | *obufp++ = 'l'; | |
252b5132 | 6170 | break; |
9d141669 L |
6171 | case 'M': |
6172 | if (intel_mnemonic != cond) | |
6173 | *obufp++ = 'r'; | |
6174 | break; | |
252b5132 RH |
6175 | case 'N': |
6176 | if ((prefixes & PREFIX_FWAIT) == 0) | |
6177 | *obufp++ = 'n'; | |
7d421014 ILT |
6178 | else |
6179 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 6180 | break; |
52b15da3 | 6181 | case 'O': |
161a04f6 L |
6182 | USED_REX (REX_W); |
6183 | if (rex & REX_W) | |
6439fc28 | 6184 | *obufp++ = 'o'; |
a35ca55a JB |
6185 | else if (intel_syntax && (sizeflag & DFLAG)) |
6186 | *obufp++ = 'q'; | |
52b15da3 JH |
6187 | else |
6188 | *obufp++ = 'd'; | |
161a04f6 | 6189 | if (!(rex & REX_W)) |
a35ca55a | 6190 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 6191 | break; |
6439fc28 | 6192 | case 'T': |
db6eb5be AM |
6193 | if (intel_syntax) |
6194 | break; | |
cb712a9e | 6195 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
6196 | { |
6197 | *obufp++ = 'q'; | |
6198 | break; | |
6199 | } | |
6608db57 | 6200 | /* Fall through. */ |
252b5132 | 6201 | case 'P': |
db6eb5be AM |
6202 | if (intel_syntax) |
6203 | break; | |
252b5132 | 6204 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 6205 | || (rex & REX_W) |
e396998b | 6206 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 6207 | { |
161a04f6 L |
6208 | USED_REX (REX_W); |
6209 | if (rex & REX_W) | |
52b15da3 | 6210 | *obufp++ = 'q'; |
c2419411 | 6211 | else |
52b15da3 JH |
6212 | { |
6213 | if (sizeflag & DFLAG) | |
6214 | *obufp++ = 'l'; | |
6215 | else | |
6216 | *obufp++ = 'w'; | |
52b15da3 | 6217 | } |
1a114b12 | 6218 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
6219 | } |
6220 | break; | |
6439fc28 | 6221 | case 'U': |
db6eb5be AM |
6222 | if (intel_syntax) |
6223 | break; | |
cb712a9e | 6224 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 | 6225 | { |
7967e09e | 6226 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 6227 | *obufp++ = 'q'; |
6439fc28 AM |
6228 | break; |
6229 | } | |
6608db57 | 6230 | /* Fall through. */ |
98b528ac | 6231 | goto case_Q; |
252b5132 | 6232 | case 'Q': |
98b528ac | 6233 | if (l == 0 && len == 1) |
252b5132 | 6234 | { |
98b528ac L |
6235 | case_Q: |
6236 | if (intel_syntax && !alt) | |
6237 | break; | |
6238 | USED_REX (REX_W); | |
6239 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 6240 | { |
98b528ac L |
6241 | if (rex & REX_W) |
6242 | *obufp++ = 'q'; | |
52b15da3 | 6243 | else |
98b528ac L |
6244 | { |
6245 | if (sizeflag & DFLAG) | |
6246 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
6247 | else | |
6248 | *obufp++ = 'w'; | |
6249 | } | |
6250 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 6251 | } |
98b528ac L |
6252 | } |
6253 | else | |
6254 | { | |
6255 | if (l != 1 || len != 2 || last[0] != 'L') | |
6256 | { | |
6257 | SAVE_LAST (*p); | |
6258 | break; | |
6259 | } | |
6260 | if (intel_syntax | |
6261 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
6262 | break; | |
6263 | if ((rex & REX_W)) | |
6264 | { | |
6265 | USED_REX (REX_W); | |
6266 | *obufp++ = 'q'; | |
6267 | } | |
6268 | else | |
6269 | *obufp++ = 'l'; | |
252b5132 RH |
6270 | } |
6271 | break; | |
6272 | case 'R': | |
161a04f6 L |
6273 | USED_REX (REX_W); |
6274 | if (rex & REX_W) | |
a35ca55a JB |
6275 | *obufp++ = 'q'; |
6276 | else if (sizeflag & DFLAG) | |
c608c12e | 6277 | { |
a35ca55a | 6278 | if (intel_syntax) |
c608c12e | 6279 | *obufp++ = 'd'; |
c608c12e | 6280 | else |
a35ca55a | 6281 | *obufp++ = 'l'; |
c608c12e | 6282 | } |
252b5132 | 6283 | else |
a35ca55a JB |
6284 | *obufp++ = 'w'; |
6285 | if (intel_syntax && !p[1] | |
161a04f6 | 6286 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 6287 | *obufp++ = 'e'; |
161a04f6 | 6288 | if (!(rex & REX_W)) |
52b15da3 | 6289 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 6290 | break; |
1a114b12 JB |
6291 | case 'V': |
6292 | if (intel_syntax) | |
6293 | break; | |
cb712a9e | 6294 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
1a114b12 JB |
6295 | { |
6296 | if (sizeflag & SUFFIX_ALWAYS) | |
6297 | *obufp++ = 'q'; | |
6298 | break; | |
6299 | } | |
6300 | /* Fall through. */ | |
252b5132 | 6301 | case 'S': |
db6eb5be AM |
6302 | if (intel_syntax) |
6303 | break; | |
252b5132 RH |
6304 | if (sizeflag & SUFFIX_ALWAYS) |
6305 | { | |
161a04f6 | 6306 | if (rex & REX_W) |
52b15da3 | 6307 | *obufp++ = 'q'; |
252b5132 | 6308 | else |
52b15da3 JH |
6309 | { |
6310 | if (sizeflag & DFLAG) | |
6311 | *obufp++ = 'l'; | |
6312 | else | |
6313 | *obufp++ = 'w'; | |
6314 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6315 | } | |
252b5132 | 6316 | } |
252b5132 | 6317 | break; |
041bd2e0 JH |
6318 | case 'X': |
6319 | if (prefixes & PREFIX_DATA) | |
6320 | *obufp++ = 'd'; | |
6321 | else | |
6322 | *obufp++ = 's'; | |
db6eb5be | 6323 | used_prefixes |= (prefixes & PREFIX_DATA); |
041bd2e0 | 6324 | break; |
76f227a5 | 6325 | case 'Y': |
8a72226a | 6326 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
db6eb5be | 6327 | break; |
161a04f6 | 6328 | if (rex & REX_W) |
76f227a5 | 6329 | { |
161a04f6 | 6330 | USED_REX (REX_W); |
76f227a5 JH |
6331 | *obufp++ = 'q'; |
6332 | } | |
6333 | break; | |
52b15da3 | 6334 | /* implicit operand size 'l' for i386 or 'q' for x86-64 */ |
252b5132 | 6335 | case 'W': |
252b5132 | 6336 | /* operand size flag for cwtl, cbtw */ |
161a04f6 L |
6337 | USED_REX (REX_W); |
6338 | if (rex & REX_W) | |
a35ca55a JB |
6339 | { |
6340 | if (intel_syntax) | |
6341 | *obufp++ = 'd'; | |
6342 | else | |
6343 | *obufp++ = 'l'; | |
6344 | } | |
52b15da3 | 6345 | else if (sizeflag & DFLAG) |
252b5132 RH |
6346 | *obufp++ = 'w'; |
6347 | else | |
6348 | *obufp++ = 'b'; | |
161a04f6 | 6349 | if (!(rex & REX_W)) |
52b15da3 | 6350 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
6351 | break; |
6352 | } | |
9306ca4a | 6353 | alt = 0; |
252b5132 RH |
6354 | } |
6355 | *obufp = 0; | |
6439fc28 | 6356 | return 0; |
252b5132 RH |
6357 | } |
6358 | ||
6359 | static void | |
26ca5450 | 6360 | oappend (const char *s) |
252b5132 RH |
6361 | { |
6362 | strcpy (obufp, s); | |
6363 | obufp += strlen (s); | |
6364 | } | |
6365 | ||
6366 | static void | |
26ca5450 | 6367 | append_seg (void) |
252b5132 RH |
6368 | { |
6369 | if (prefixes & PREFIX_CS) | |
7d421014 | 6370 | { |
7d421014 | 6371 | used_prefixes |= PREFIX_CS; |
d708bcba | 6372 | oappend ("%cs:" + intel_syntax); |
7d421014 | 6373 | } |
252b5132 | 6374 | if (prefixes & PREFIX_DS) |
7d421014 | 6375 | { |
7d421014 | 6376 | used_prefixes |= PREFIX_DS; |
d708bcba | 6377 | oappend ("%ds:" + intel_syntax); |
7d421014 | 6378 | } |
252b5132 | 6379 | if (prefixes & PREFIX_SS) |
7d421014 | 6380 | { |
7d421014 | 6381 | used_prefixes |= PREFIX_SS; |
d708bcba | 6382 | oappend ("%ss:" + intel_syntax); |
7d421014 | 6383 | } |
252b5132 | 6384 | if (prefixes & PREFIX_ES) |
7d421014 | 6385 | { |
7d421014 | 6386 | used_prefixes |= PREFIX_ES; |
d708bcba | 6387 | oappend ("%es:" + intel_syntax); |
7d421014 | 6388 | } |
252b5132 | 6389 | if (prefixes & PREFIX_FS) |
7d421014 | 6390 | { |
7d421014 | 6391 | used_prefixes |= PREFIX_FS; |
d708bcba | 6392 | oappend ("%fs:" + intel_syntax); |
7d421014 | 6393 | } |
252b5132 | 6394 | if (prefixes & PREFIX_GS) |
7d421014 | 6395 | { |
7d421014 | 6396 | used_prefixes |= PREFIX_GS; |
d708bcba | 6397 | oappend ("%gs:" + intel_syntax); |
7d421014 | 6398 | } |
252b5132 RH |
6399 | } |
6400 | ||
6401 | static void | |
26ca5450 | 6402 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
6403 | { |
6404 | if (!intel_syntax) | |
6405 | oappend ("*"); | |
6406 | OP_E (bytemode, sizeflag); | |
6407 | } | |
6408 | ||
52b15da3 | 6409 | static void |
26ca5450 | 6410 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 6411 | { |
cb712a9e | 6412 | if (address_mode == mode_64bit) |
52b15da3 JH |
6413 | { |
6414 | if (hex) | |
6415 | { | |
6416 | char tmp[30]; | |
6417 | int i; | |
6418 | buf[0] = '0'; | |
6419 | buf[1] = 'x'; | |
6420 | sprintf_vma (tmp, disp); | |
6608db57 | 6421 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
6422 | strcpy (buf + 2, tmp + i); |
6423 | } | |
6424 | else | |
6425 | { | |
6426 | bfd_signed_vma v = disp; | |
6427 | char tmp[30]; | |
6428 | int i; | |
6429 | if (v < 0) | |
6430 | { | |
6431 | *(buf++) = '-'; | |
6432 | v = -disp; | |
6608db57 | 6433 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
6434 | if (v < 0) |
6435 | { | |
6436 | strcpy (buf, "9223372036854775808"); | |
6437 | return; | |
6438 | } | |
6439 | } | |
6440 | if (!v) | |
6441 | { | |
6442 | strcpy (buf, "0"); | |
6443 | return; | |
6444 | } | |
6445 | ||
6446 | i = 0; | |
6447 | tmp[29] = 0; | |
6448 | while (v) | |
6449 | { | |
6608db57 | 6450 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
6451 | v /= 10; |
6452 | i++; | |
6453 | } | |
6454 | strcpy (buf, tmp + 29 - i); | |
6455 | } | |
6456 | } | |
6457 | else | |
6458 | { | |
6459 | if (hex) | |
6460 | sprintf (buf, "0x%x", (unsigned int) disp); | |
6461 | else | |
6462 | sprintf (buf, "%d", (int) disp); | |
6463 | } | |
6464 | } | |
6465 | ||
5d669648 L |
6466 | /* Put DISP in BUF as signed hex number. */ |
6467 | ||
6468 | static void | |
6469 | print_displacement (char *buf, bfd_vma disp) | |
6470 | { | |
6471 | bfd_signed_vma val = disp; | |
6472 | char tmp[30]; | |
6473 | int i, j = 0; | |
6474 | ||
6475 | if (val < 0) | |
6476 | { | |
6477 | buf[j++] = '-'; | |
6478 | val = -disp; | |
6479 | ||
6480 | /* Check for possible overflow. */ | |
6481 | if (val < 0) | |
6482 | { | |
6483 | switch (address_mode) | |
6484 | { | |
6485 | case mode_64bit: | |
6486 | strcpy (buf + j, "0x8000000000000000"); | |
6487 | break; | |
6488 | case mode_32bit: | |
6489 | strcpy (buf + j, "0x80000000"); | |
6490 | break; | |
6491 | case mode_16bit: | |
6492 | strcpy (buf + j, "0x8000"); | |
6493 | break; | |
6494 | } | |
6495 | return; | |
6496 | } | |
6497 | } | |
6498 | ||
6499 | buf[j++] = '0'; | |
6500 | buf[j++] = 'x'; | |
6501 | ||
6502 | sprintf_vma (tmp, val); | |
6503 | for (i = 0; tmp[i] == '0'; i++) | |
6504 | continue; | |
6505 | if (tmp[i] == '\0') | |
6506 | i--; | |
6507 | strcpy (buf + j, tmp + i); | |
6508 | } | |
6509 | ||
3f31e633 JB |
6510 | static void |
6511 | intel_operand_size (int bytemode, int sizeflag) | |
6512 | { | |
6513 | switch (bytemode) | |
6514 | { | |
6515 | case b_mode: | |
42903f7f | 6516 | case dqb_mode: |
3f31e633 JB |
6517 | oappend ("BYTE PTR "); |
6518 | break; | |
6519 | case w_mode: | |
6520 | case dqw_mode: | |
6521 | oappend ("WORD PTR "); | |
6522 | break; | |
1a114b12 | 6523 | case stack_v_mode: |
cb712a9e | 6524 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
3f31e633 JB |
6525 | { |
6526 | oappend ("QWORD PTR "); | |
6527 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6528 | break; | |
6529 | } | |
6530 | /* FALLTHRU */ | |
6531 | case v_mode: | |
6532 | case dq_mode: | |
161a04f6 L |
6533 | USED_REX (REX_W); |
6534 | if (rex & REX_W) | |
3f31e633 JB |
6535 | oappend ("QWORD PTR "); |
6536 | else if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
6537 | oappend ("DWORD PTR "); | |
6538 | else | |
6539 | oappend ("WORD PTR "); | |
6540 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6541 | break; | |
52fd6d94 | 6542 | case z_mode: |
161a04f6 | 6543 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
6544 | *obufp++ = 'D'; |
6545 | oappend ("WORD PTR "); | |
161a04f6 | 6546 | if (!(rex & REX_W)) |
52fd6d94 JB |
6547 | used_prefixes |= (prefixes & PREFIX_DATA); |
6548 | break; | |
34b772a6 JB |
6549 | case a_mode: |
6550 | if (sizeflag & DFLAG) | |
6551 | oappend ("QWORD PTR "); | |
6552 | else | |
6553 | oappend ("DWORD PTR "); | |
6554 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6555 | break; | |
3f31e633 | 6556 | case d_mode: |
42903f7f | 6557 | case dqd_mode: |
3f31e633 JB |
6558 | oappend ("DWORD PTR "); |
6559 | break; | |
6560 | case q_mode: | |
6561 | oappend ("QWORD PTR "); | |
6562 | break; | |
6563 | case m_mode: | |
cb712a9e | 6564 | if (address_mode == mode_64bit) |
3f31e633 JB |
6565 | oappend ("QWORD PTR "); |
6566 | else | |
6567 | oappend ("DWORD PTR "); | |
6568 | break; | |
6569 | case f_mode: | |
6570 | if (sizeflag & DFLAG) | |
6571 | oappend ("FWORD PTR "); | |
6572 | else | |
6573 | oappend ("DWORD PTR "); | |
6574 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6575 | break; | |
6576 | case t_mode: | |
6577 | oappend ("TBYTE PTR "); | |
6578 | break; | |
6579 | case x_mode: | |
6580 | oappend ("XMMWORD PTR "); | |
6581 | break; | |
fb9c77c7 L |
6582 | case o_mode: |
6583 | oappend ("OWORD PTR "); | |
6584 | break; | |
3f31e633 JB |
6585 | default: |
6586 | break; | |
6587 | } | |
6588 | } | |
6589 | ||
252b5132 | 6590 | static void |
85f10a01 | 6591 | OP_E_extended (int bytemode, int sizeflag, int has_drex) |
252b5132 | 6592 | { |
52b15da3 JH |
6593 | bfd_vma disp; |
6594 | int add = 0; | |
6595 | int riprel = 0; | |
161a04f6 L |
6596 | USED_REX (REX_B); |
6597 | if (rex & REX_B) | |
52b15da3 | 6598 | add += 8; |
252b5132 | 6599 | |
6608db57 | 6600 | /* Skip mod/rm byte. */ |
4bba6815 | 6601 | MODRM_CHECK; |
252b5132 RH |
6602 | codep++; |
6603 | ||
7967e09e | 6604 | if (modrm.mod == 3) |
252b5132 RH |
6605 | { |
6606 | switch (bytemode) | |
6607 | { | |
6608 | case b_mode: | |
52b15da3 JH |
6609 | USED_REX (0); |
6610 | if (rex) | |
7967e09e | 6611 | oappend (names8rex[modrm.rm + add]); |
52b15da3 | 6612 | else |
7967e09e | 6613 | oappend (names8[modrm.rm + add]); |
252b5132 RH |
6614 | break; |
6615 | case w_mode: | |
7967e09e | 6616 | oappend (names16[modrm.rm + add]); |
252b5132 | 6617 | break; |
2da11e11 | 6618 | case d_mode: |
7967e09e | 6619 | oappend (names32[modrm.rm + add]); |
52b15da3 JH |
6620 | break; |
6621 | case q_mode: | |
7967e09e | 6622 | oappend (names64[modrm.rm + add]); |
52b15da3 JH |
6623 | break; |
6624 | case m_mode: | |
cb712a9e | 6625 | if (address_mode == mode_64bit) |
7967e09e | 6626 | oappend (names64[modrm.rm + add]); |
52b15da3 | 6627 | else |
7967e09e | 6628 | oappend (names32[modrm.rm + add]); |
2da11e11 | 6629 | break; |
1a114b12 | 6630 | case stack_v_mode: |
cb712a9e | 6631 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
003519a7 | 6632 | { |
7967e09e | 6633 | oappend (names64[modrm.rm + add]); |
003519a7 | 6634 | used_prefixes |= (prefixes & PREFIX_DATA); |
1a114b12 | 6635 | break; |
003519a7 | 6636 | } |
1a114b12 JB |
6637 | bytemode = v_mode; |
6638 | /* FALLTHRU */ | |
252b5132 | 6639 | case v_mode: |
db6eb5be | 6640 | case dq_mode: |
42903f7f L |
6641 | case dqb_mode: |
6642 | case dqd_mode: | |
9306ca4a | 6643 | case dqw_mode: |
161a04f6 L |
6644 | USED_REX (REX_W); |
6645 | if (rex & REX_W) | |
7967e09e | 6646 | oappend (names64[modrm.rm + add]); |
9306ca4a | 6647 | else if ((sizeflag & DFLAG) || bytemode != v_mode) |
7967e09e | 6648 | oappend (names32[modrm.rm + add]); |
252b5132 | 6649 | else |
7967e09e | 6650 | oappend (names16[modrm.rm + add]); |
7d421014 | 6651 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 6652 | break; |
2da11e11 | 6653 | case 0: |
c608c12e | 6654 | break; |
252b5132 | 6655 | default: |
c608c12e | 6656 | oappend (INTERNAL_DISASSEMBLER_ERROR); |
252b5132 RH |
6657 | break; |
6658 | } | |
6659 | return; | |
6660 | } | |
6661 | ||
6662 | disp = 0; | |
3f31e633 JB |
6663 | if (intel_syntax) |
6664 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
6665 | append_seg (); |
6666 | ||
5d669648 | 6667 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 6668 | { |
5d669648 L |
6669 | /* 32/64 bit address mode */ |
6670 | int havedisp; | |
252b5132 RH |
6671 | int havesib; |
6672 | int havebase; | |
0f7da397 | 6673 | int haveindex; |
20afcfb7 | 6674 | int needindex; |
82c18208 | 6675 | int base, rbase; |
252b5132 RH |
6676 | int index = 0; |
6677 | int scale = 0; | |
6678 | ||
6679 | havesib = 0; | |
6680 | havebase = 1; | |
0f7da397 | 6681 | haveindex = 0; |
7967e09e | 6682 | base = modrm.rm; |
252b5132 RH |
6683 | |
6684 | if (base == 4) | |
6685 | { | |
6686 | havesib = 1; | |
6687 | FETCH_DATA (the_info, codep + 1); | |
252b5132 | 6688 | index = (*codep >> 3) & 7; |
db51cc60 | 6689 | scale = (*codep >> 6) & 3; |
252b5132 | 6690 | base = *codep & 7; |
161a04f6 L |
6691 | USED_REX (REX_X); |
6692 | if (rex & REX_X) | |
52b15da3 | 6693 | index += 8; |
0f7da397 | 6694 | haveindex = index != 4; |
252b5132 RH |
6695 | codep++; |
6696 | } | |
82c18208 | 6697 | rbase = base + add; |
252b5132 | 6698 | |
85f10a01 MM |
6699 | /* If we have a DREX byte, skip it now |
6700 | (it has already been handled) */ | |
6701 | if (has_drex) | |
6702 | { | |
6703 | FETCH_DATA (the_info, codep + 1); | |
6704 | codep++; | |
6705 | } | |
6706 | ||
7967e09e | 6707 | switch (modrm.mod) |
252b5132 RH |
6708 | { |
6709 | case 0: | |
82c18208 | 6710 | if (base == 5) |
252b5132 RH |
6711 | { |
6712 | havebase = 0; | |
cb712a9e | 6713 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
6714 | riprel = 1; |
6715 | disp = get32s (); | |
252b5132 RH |
6716 | } |
6717 | break; | |
6718 | case 1: | |
6719 | FETCH_DATA (the_info, codep + 1); | |
6720 | disp = *codep++; | |
6721 | if ((disp & 0x80) != 0) | |
6722 | disp -= 0x100; | |
6723 | break; | |
6724 | case 2: | |
52b15da3 | 6725 | disp = get32s (); |
252b5132 RH |
6726 | break; |
6727 | } | |
6728 | ||
20afcfb7 L |
6729 | /* In 32bit mode, we need index register to tell [offset] from |
6730 | [eiz*1 + offset]. */ | |
6731 | needindex = (havesib | |
6732 | && !havebase | |
6733 | && !haveindex | |
6734 | && address_mode == mode_32bit); | |
6735 | havedisp = (havebase | |
6736 | || needindex | |
6737 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 6738 | |
252b5132 | 6739 | if (!intel_syntax) |
82c18208 | 6740 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 6741 | { |
5d669648 L |
6742 | if (havedisp || riprel) |
6743 | print_displacement (scratchbuf, disp); | |
6744 | else | |
6745 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 6746 | oappend (scratchbuf); |
52b15da3 JH |
6747 | if (riprel) |
6748 | { | |
6749 | set_op (disp, 1); | |
87767711 | 6750 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 6751 | } |
db6eb5be | 6752 | } |
2da11e11 | 6753 | |
87767711 JB |
6754 | if (havebase || haveindex || riprel) |
6755 | used_prefixes |= PREFIX_ADDR; | |
6756 | ||
5d669648 | 6757 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 6758 | { |
252b5132 | 6759 | *obufp++ = open_char; |
52b15da3 | 6760 | if (intel_syntax && riprel) |
185b1163 L |
6761 | { |
6762 | set_op (disp, 1); | |
87767711 | 6763 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 6764 | } |
db6eb5be | 6765 | *obufp = '\0'; |
252b5132 | 6766 | if (havebase) |
cb712a9e | 6767 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
82c18208 | 6768 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
6769 | if (havesib) |
6770 | { | |
db51cc60 L |
6771 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
6772 | print index to tell base + index from base. */ | |
6773 | if (scale != 0 | |
20afcfb7 | 6774 | || needindex |
db51cc60 L |
6775 | || haveindex |
6776 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 6777 | { |
9306ca4a | 6778 | if (!intel_syntax || havebase) |
db6eb5be | 6779 | { |
9306ca4a JB |
6780 | *obufp++ = separator_char; |
6781 | *obufp = '\0'; | |
db6eb5be | 6782 | } |
db51cc60 L |
6783 | if (haveindex) |
6784 | oappend (address_mode == mode_64bit | |
6785 | && (sizeflag & AFLAG) | |
6786 | ? names64[index] : names32[index]); | |
6787 | else | |
6788 | oappend (address_mode == mode_64bit | |
6789 | && (sizeflag & AFLAG) | |
6790 | ? index64 : index32); | |
6791 | ||
db6eb5be AM |
6792 | *obufp++ = scale_char; |
6793 | *obufp = '\0'; | |
6794 | sprintf (scratchbuf, "%d", 1 << scale); | |
6795 | oappend (scratchbuf); | |
6796 | } | |
252b5132 | 6797 | } |
185b1163 | 6798 | if (intel_syntax |
82c18208 | 6799 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 6800 | { |
db51cc60 | 6801 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
6802 | { |
6803 | *obufp++ = '+'; | |
6804 | *obufp = '\0'; | |
6805 | } | |
7967e09e | 6806 | else if (modrm.mod != 1) |
3d456fa1 JB |
6807 | { |
6808 | *obufp++ = '-'; | |
6809 | *obufp = '\0'; | |
6810 | disp = - (bfd_signed_vma) disp; | |
6811 | } | |
6812 | ||
db51cc60 L |
6813 | if (havedisp) |
6814 | print_displacement (scratchbuf, disp); | |
6815 | else | |
6816 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
6817 | oappend (scratchbuf); |
6818 | } | |
252b5132 RH |
6819 | |
6820 | *obufp++ = close_char; | |
db6eb5be | 6821 | *obufp = '\0'; |
252b5132 RH |
6822 | } |
6823 | else if (intel_syntax) | |
db6eb5be | 6824 | { |
82c18208 | 6825 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 6826 | { |
252b5132 RH |
6827 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
6828 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
6829 | ; | |
6830 | else | |
6831 | { | |
d708bcba | 6832 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
6833 | oappend (":"); |
6834 | } | |
52b15da3 | 6835 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
6836 | oappend (scratchbuf); |
6837 | } | |
6838 | } | |
252b5132 RH |
6839 | } |
6840 | else | |
6841 | { /* 16 bit address mode */ | |
7967e09e | 6842 | switch (modrm.mod) |
252b5132 RH |
6843 | { |
6844 | case 0: | |
7967e09e | 6845 | if (modrm.rm == 6) |
252b5132 RH |
6846 | { |
6847 | disp = get16 (); | |
6848 | if ((disp & 0x8000) != 0) | |
6849 | disp -= 0x10000; | |
6850 | } | |
6851 | break; | |
6852 | case 1: | |
6853 | FETCH_DATA (the_info, codep + 1); | |
6854 | disp = *codep++; | |
6855 | if ((disp & 0x80) != 0) | |
6856 | disp -= 0x100; | |
6857 | break; | |
6858 | case 2: | |
6859 | disp = get16 (); | |
6860 | if ((disp & 0x8000) != 0) | |
6861 | disp -= 0x10000; | |
6862 | break; | |
6863 | } | |
6864 | ||
6865 | if (!intel_syntax) | |
7967e09e | 6866 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 6867 | { |
5d669648 | 6868 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
6869 | oappend (scratchbuf); |
6870 | } | |
252b5132 | 6871 | |
7967e09e | 6872 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
6873 | { |
6874 | *obufp++ = open_char; | |
db6eb5be | 6875 | *obufp = '\0'; |
7967e09e | 6876 | oappend (index16[modrm.rm]); |
5d669648 L |
6877 | if (intel_syntax |
6878 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 6879 | { |
5d669648 | 6880 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
6881 | { |
6882 | *obufp++ = '+'; | |
6883 | *obufp = '\0'; | |
6884 | } | |
7967e09e | 6885 | else if (modrm.mod != 1) |
3d456fa1 JB |
6886 | { |
6887 | *obufp++ = '-'; | |
6888 | *obufp = '\0'; | |
6889 | disp = - (bfd_signed_vma) disp; | |
6890 | } | |
6891 | ||
5d669648 | 6892 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
6893 | oappend (scratchbuf); |
6894 | } | |
6895 | ||
db6eb5be AM |
6896 | *obufp++ = close_char; |
6897 | *obufp = '\0'; | |
252b5132 | 6898 | } |
3d456fa1 JB |
6899 | else if (intel_syntax) |
6900 | { | |
6901 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
6902 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
6903 | ; | |
6904 | else | |
6905 | { | |
6906 | oappend (names_seg[ds_reg - es_reg]); | |
6907 | oappend (":"); | |
6908 | } | |
6909 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
6910 | oappend (scratchbuf); | |
6911 | } | |
252b5132 RH |
6912 | } |
6913 | } | |
6914 | ||
85f10a01 MM |
6915 | static void |
6916 | OP_E (int bytemode, int sizeflag) | |
6917 | { | |
6918 | OP_E_extended (bytemode, sizeflag, 0); | |
6919 | } | |
6920 | ||
6921 | ||
252b5132 | 6922 | static void |
26ca5450 | 6923 | OP_G (int bytemode, int sizeflag) |
252b5132 | 6924 | { |
52b15da3 | 6925 | int add = 0; |
161a04f6 L |
6926 | USED_REX (REX_R); |
6927 | if (rex & REX_R) | |
52b15da3 | 6928 | add += 8; |
252b5132 RH |
6929 | switch (bytemode) |
6930 | { | |
6931 | case b_mode: | |
52b15da3 JH |
6932 | USED_REX (0); |
6933 | if (rex) | |
7967e09e | 6934 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 6935 | else |
7967e09e | 6936 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
6937 | break; |
6938 | case w_mode: | |
7967e09e | 6939 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
6940 | break; |
6941 | case d_mode: | |
7967e09e | 6942 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
6943 | break; |
6944 | case q_mode: | |
7967e09e | 6945 | oappend (names64[modrm.reg + add]); |
252b5132 RH |
6946 | break; |
6947 | case v_mode: | |
9306ca4a | 6948 | case dq_mode: |
42903f7f L |
6949 | case dqb_mode: |
6950 | case dqd_mode: | |
9306ca4a | 6951 | case dqw_mode: |
161a04f6 L |
6952 | USED_REX (REX_W); |
6953 | if (rex & REX_W) | |
7967e09e | 6954 | oappend (names64[modrm.reg + add]); |
9306ca4a | 6955 | else if ((sizeflag & DFLAG) || bytemode != v_mode) |
7967e09e | 6956 | oappend (names32[modrm.reg + add]); |
252b5132 | 6957 | else |
7967e09e | 6958 | oappend (names16[modrm.reg + add]); |
7d421014 | 6959 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 6960 | break; |
90700ea2 | 6961 | case m_mode: |
cb712a9e | 6962 | if (address_mode == mode_64bit) |
7967e09e | 6963 | oappend (names64[modrm.reg + add]); |
90700ea2 | 6964 | else |
7967e09e | 6965 | oappend (names32[modrm.reg + add]); |
90700ea2 | 6966 | break; |
252b5132 RH |
6967 | default: |
6968 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
6969 | break; | |
6970 | } | |
6971 | } | |
6972 | ||
52b15da3 | 6973 | static bfd_vma |
26ca5450 | 6974 | get64 (void) |
52b15da3 | 6975 | { |
5dd0794d | 6976 | bfd_vma x; |
52b15da3 | 6977 | #ifdef BFD64 |
5dd0794d AM |
6978 | unsigned int a; |
6979 | unsigned int b; | |
6980 | ||
52b15da3 JH |
6981 | FETCH_DATA (the_info, codep + 8); |
6982 | a = *codep++ & 0xff; | |
6983 | a |= (*codep++ & 0xff) << 8; | |
6984 | a |= (*codep++ & 0xff) << 16; | |
6985 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 6986 | b = *codep++ & 0xff; |
52b15da3 JH |
6987 | b |= (*codep++ & 0xff) << 8; |
6988 | b |= (*codep++ & 0xff) << 16; | |
6989 | b |= (*codep++ & 0xff) << 24; | |
6990 | x = a + ((bfd_vma) b << 32); | |
6991 | #else | |
6608db57 | 6992 | abort (); |
5dd0794d | 6993 | x = 0; |
52b15da3 JH |
6994 | #endif |
6995 | return x; | |
6996 | } | |
6997 | ||
6998 | static bfd_signed_vma | |
26ca5450 | 6999 | get32 (void) |
252b5132 | 7000 | { |
52b15da3 | 7001 | bfd_signed_vma x = 0; |
252b5132 RH |
7002 | |
7003 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
7004 | x = *codep++ & (bfd_signed_vma) 0xff; |
7005 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
7006 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
7007 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
7008 | return x; | |
7009 | } | |
7010 | ||
7011 | static bfd_signed_vma | |
26ca5450 | 7012 | get32s (void) |
52b15da3 JH |
7013 | { |
7014 | bfd_signed_vma x = 0; | |
7015 | ||
7016 | FETCH_DATA (the_info, codep + 4); | |
7017 | x = *codep++ & (bfd_signed_vma) 0xff; | |
7018 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
7019 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
7020 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
7021 | ||
7022 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
7023 | ||
252b5132 RH |
7024 | return x; |
7025 | } | |
7026 | ||
7027 | static int | |
26ca5450 | 7028 | get16 (void) |
252b5132 RH |
7029 | { |
7030 | int x = 0; | |
7031 | ||
7032 | FETCH_DATA (the_info, codep + 2); | |
7033 | x = *codep++ & 0xff; | |
7034 | x |= (*codep++ & 0xff) << 8; | |
7035 | return x; | |
7036 | } | |
7037 | ||
7038 | static void | |
26ca5450 | 7039 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
7040 | { |
7041 | op_index[op_ad] = op_ad; | |
cb712a9e | 7042 | if (address_mode == mode_64bit) |
7081ff04 AJ |
7043 | { |
7044 | op_address[op_ad] = op; | |
7045 | op_riprel[op_ad] = riprel; | |
7046 | } | |
7047 | else | |
7048 | { | |
7049 | /* Mask to get a 32-bit address. */ | |
7050 | op_address[op_ad] = op & 0xffffffff; | |
7051 | op_riprel[op_ad] = riprel & 0xffffffff; | |
7052 | } | |
252b5132 RH |
7053 | } |
7054 | ||
7055 | static void | |
26ca5450 | 7056 | OP_REG (int code, int sizeflag) |
252b5132 | 7057 | { |
2da11e11 | 7058 | const char *s; |
9b60702d | 7059 | int add; |
161a04f6 L |
7060 | USED_REX (REX_B); |
7061 | if (rex & REX_B) | |
52b15da3 | 7062 | add = 8; |
9b60702d L |
7063 | else |
7064 | add = 0; | |
52b15da3 JH |
7065 | |
7066 | switch (code) | |
7067 | { | |
52b15da3 JH |
7068 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
7069 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
7070 | s = names16[code - ax_reg + add]; | |
7071 | break; | |
7072 | case es_reg: case ss_reg: case cs_reg: | |
7073 | case ds_reg: case fs_reg: case gs_reg: | |
7074 | s = names_seg[code - es_reg + add]; | |
7075 | break; | |
7076 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
7077 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
7078 | USED_REX (0); | |
7079 | if (rex) | |
7080 | s = names8rex[code - al_reg + add]; | |
7081 | else | |
7082 | s = names8[code - al_reg]; | |
7083 | break; | |
6439fc28 AM |
7084 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
7085 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
cb712a9e | 7086 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
7087 | { |
7088 | s = names64[code - rAX_reg + add]; | |
7089 | break; | |
7090 | } | |
7091 | code += eAX_reg - rAX_reg; | |
6608db57 | 7092 | /* Fall through. */ |
52b15da3 JH |
7093 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
7094 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
7095 | USED_REX (REX_W); |
7096 | if (rex & REX_W) | |
52b15da3 JH |
7097 | s = names64[code - eAX_reg + add]; |
7098 | else if (sizeflag & DFLAG) | |
7099 | s = names32[code - eAX_reg + add]; | |
7100 | else | |
7101 | s = names16[code - eAX_reg + add]; | |
7102 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7103 | break; | |
52b15da3 JH |
7104 | default: |
7105 | s = INTERNAL_DISASSEMBLER_ERROR; | |
7106 | break; | |
7107 | } | |
7108 | oappend (s); | |
7109 | } | |
7110 | ||
7111 | static void | |
26ca5450 | 7112 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
7113 | { |
7114 | const char *s; | |
252b5132 RH |
7115 | |
7116 | switch (code) | |
7117 | { | |
7118 | case indir_dx_reg: | |
d708bcba | 7119 | if (intel_syntax) |
52fd6d94 | 7120 | s = "dx"; |
d708bcba | 7121 | else |
db6eb5be | 7122 | s = "(%dx)"; |
252b5132 RH |
7123 | break; |
7124 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
7125 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
7126 | s = names16[code - ax_reg]; | |
7127 | break; | |
7128 | case es_reg: case ss_reg: case cs_reg: | |
7129 | case ds_reg: case fs_reg: case gs_reg: | |
7130 | s = names_seg[code - es_reg]; | |
7131 | break; | |
7132 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
7133 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
7134 | USED_REX (0); |
7135 | if (rex) | |
7136 | s = names8rex[code - al_reg]; | |
7137 | else | |
7138 | s = names8[code - al_reg]; | |
252b5132 RH |
7139 | break; |
7140 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
7141 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
7142 | USED_REX (REX_W); |
7143 | if (rex & REX_W) | |
52b15da3 JH |
7144 | s = names64[code - eAX_reg]; |
7145 | else if (sizeflag & DFLAG) | |
252b5132 RH |
7146 | s = names32[code - eAX_reg]; |
7147 | else | |
7148 | s = names16[code - eAX_reg]; | |
7d421014 | 7149 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 7150 | break; |
52fd6d94 | 7151 | case z_mode_ax_reg: |
161a04f6 | 7152 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
7153 | s = *names32; |
7154 | else | |
7155 | s = *names16; | |
161a04f6 | 7156 | if (!(rex & REX_W)) |
52fd6d94 JB |
7157 | used_prefixes |= (prefixes & PREFIX_DATA); |
7158 | break; | |
252b5132 RH |
7159 | default: |
7160 | s = INTERNAL_DISASSEMBLER_ERROR; | |
7161 | break; | |
7162 | } | |
7163 | oappend (s); | |
7164 | } | |
7165 | ||
7166 | static void | |
26ca5450 | 7167 | OP_I (int bytemode, int sizeflag) |
252b5132 | 7168 | { |
52b15da3 JH |
7169 | bfd_signed_vma op; |
7170 | bfd_signed_vma mask = -1; | |
252b5132 RH |
7171 | |
7172 | switch (bytemode) | |
7173 | { | |
7174 | case b_mode: | |
7175 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
7176 | op = *codep++; |
7177 | mask = 0xff; | |
7178 | break; | |
7179 | case q_mode: | |
cb712a9e | 7180 | if (address_mode == mode_64bit) |
6439fc28 AM |
7181 | { |
7182 | op = get32s (); | |
7183 | break; | |
7184 | } | |
6608db57 | 7185 | /* Fall through. */ |
252b5132 | 7186 | case v_mode: |
161a04f6 L |
7187 | USED_REX (REX_W); |
7188 | if (rex & REX_W) | |
52b15da3 JH |
7189 | op = get32s (); |
7190 | else if (sizeflag & DFLAG) | |
7191 | { | |
7192 | op = get32 (); | |
7193 | mask = 0xffffffff; | |
7194 | } | |
252b5132 | 7195 | else |
52b15da3 JH |
7196 | { |
7197 | op = get16 (); | |
7198 | mask = 0xfffff; | |
7199 | } | |
7d421014 | 7200 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
7201 | break; |
7202 | case w_mode: | |
52b15da3 | 7203 | mask = 0xfffff; |
252b5132 RH |
7204 | op = get16 (); |
7205 | break; | |
9306ca4a JB |
7206 | case const_1_mode: |
7207 | if (intel_syntax) | |
7208 | oappend ("1"); | |
7209 | return; | |
252b5132 RH |
7210 | default: |
7211 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
7212 | return; | |
7213 | } | |
7214 | ||
52b15da3 JH |
7215 | op &= mask; |
7216 | scratchbuf[0] = '$'; | |
d708bcba AM |
7217 | print_operand_value (scratchbuf + 1, 1, op); |
7218 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
7219 | scratchbuf[0] = '\0'; |
7220 | } | |
7221 | ||
7222 | static void | |
26ca5450 | 7223 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
7224 | { |
7225 | bfd_signed_vma op; | |
7226 | bfd_signed_vma mask = -1; | |
7227 | ||
cb712a9e | 7228 | if (address_mode != mode_64bit) |
6439fc28 AM |
7229 | { |
7230 | OP_I (bytemode, sizeflag); | |
7231 | return; | |
7232 | } | |
7233 | ||
52b15da3 JH |
7234 | switch (bytemode) |
7235 | { | |
7236 | case b_mode: | |
7237 | FETCH_DATA (the_info, codep + 1); | |
7238 | op = *codep++; | |
7239 | mask = 0xff; | |
7240 | break; | |
7241 | case v_mode: | |
161a04f6 L |
7242 | USED_REX (REX_W); |
7243 | if (rex & REX_W) | |
52b15da3 JH |
7244 | op = get64 (); |
7245 | else if (sizeflag & DFLAG) | |
7246 | { | |
7247 | op = get32 (); | |
7248 | mask = 0xffffffff; | |
7249 | } | |
7250 | else | |
7251 | { | |
7252 | op = get16 (); | |
7253 | mask = 0xfffff; | |
7254 | } | |
7255 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7256 | break; | |
7257 | case w_mode: | |
7258 | mask = 0xfffff; | |
7259 | op = get16 (); | |
7260 | break; | |
7261 | default: | |
7262 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
7263 | return; | |
7264 | } | |
7265 | ||
7266 | op &= mask; | |
7267 | scratchbuf[0] = '$'; | |
d708bcba AM |
7268 | print_operand_value (scratchbuf + 1, 1, op); |
7269 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
7270 | scratchbuf[0] = '\0'; |
7271 | } | |
7272 | ||
7273 | static void | |
26ca5450 | 7274 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 7275 | { |
52b15da3 JH |
7276 | bfd_signed_vma op; |
7277 | bfd_signed_vma mask = -1; | |
252b5132 RH |
7278 | |
7279 | switch (bytemode) | |
7280 | { | |
7281 | case b_mode: | |
7282 | FETCH_DATA (the_info, codep + 1); | |
7283 | op = *codep++; | |
7284 | if ((op & 0x80) != 0) | |
7285 | op -= 0x100; | |
52b15da3 | 7286 | mask = 0xffffffff; |
252b5132 RH |
7287 | break; |
7288 | case v_mode: | |
161a04f6 L |
7289 | USED_REX (REX_W); |
7290 | if (rex & REX_W) | |
52b15da3 JH |
7291 | op = get32s (); |
7292 | else if (sizeflag & DFLAG) | |
7293 | { | |
7294 | op = get32s (); | |
7295 | mask = 0xffffffff; | |
7296 | } | |
252b5132 RH |
7297 | else |
7298 | { | |
52b15da3 | 7299 | mask = 0xffffffff; |
6608db57 | 7300 | op = get16 (); |
252b5132 RH |
7301 | if ((op & 0x8000) != 0) |
7302 | op -= 0x10000; | |
7303 | } | |
7d421014 | 7304 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
7305 | break; |
7306 | case w_mode: | |
7307 | op = get16 (); | |
52b15da3 | 7308 | mask = 0xffffffff; |
252b5132 RH |
7309 | if ((op & 0x8000) != 0) |
7310 | op -= 0x10000; | |
7311 | break; | |
7312 | default: | |
7313 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
7314 | return; | |
7315 | } | |
52b15da3 JH |
7316 | |
7317 | scratchbuf[0] = '$'; | |
7318 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 7319 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
7320 | } |
7321 | ||
7322 | static void | |
26ca5450 | 7323 | OP_J (int bytemode, int sizeflag) |
252b5132 | 7324 | { |
52b15da3 | 7325 | bfd_vma disp; |
7081ff04 | 7326 | bfd_vma mask = -1; |
65ca155d | 7327 | bfd_vma segment = 0; |
252b5132 RH |
7328 | |
7329 | switch (bytemode) | |
7330 | { | |
7331 | case b_mode: | |
7332 | FETCH_DATA (the_info, codep + 1); | |
7333 | disp = *codep++; | |
7334 | if ((disp & 0x80) != 0) | |
7335 | disp -= 0x100; | |
7336 | break; | |
7337 | case v_mode: | |
161a04f6 | 7338 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 7339 | disp = get32s (); |
252b5132 RH |
7340 | else |
7341 | { | |
7342 | disp = get16 (); | |
206717e8 L |
7343 | if ((disp & 0x8000) != 0) |
7344 | disp -= 0x10000; | |
65ca155d L |
7345 | /* In 16bit mode, address is wrapped around at 64k within |
7346 | the same segment. Otherwise, a data16 prefix on a jump | |
7347 | instruction means that the pc is masked to 16 bits after | |
7348 | the displacement is added! */ | |
7349 | mask = 0xffff; | |
7350 | if ((prefixes & PREFIX_DATA) == 0) | |
7351 | segment = ((start_pc + codep - start_codep) | |
7352 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 7353 | } |
d807a492 | 7354 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
7355 | break; |
7356 | default: | |
7357 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
7358 | return; | |
7359 | } | |
65ca155d | 7360 | disp = ((start_pc + codep - start_codep + disp) & mask) | segment; |
52b15da3 JH |
7361 | set_op (disp, 0); |
7362 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
7363 | oappend (scratchbuf); |
7364 | } | |
7365 | ||
252b5132 | 7366 | static void |
ed7841b3 | 7367 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 7368 | { |
ed7841b3 | 7369 | if (bytemode == w_mode) |
7967e09e | 7370 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 7371 | else |
7967e09e | 7372 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
7373 | } |
7374 | ||
7375 | static void | |
26ca5450 | 7376 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
7377 | { |
7378 | int seg, offset; | |
7379 | ||
c608c12e | 7380 | if (sizeflag & DFLAG) |
252b5132 | 7381 | { |
c608c12e AM |
7382 | offset = get32 (); |
7383 | seg = get16 (); | |
252b5132 | 7384 | } |
c608c12e AM |
7385 | else |
7386 | { | |
7387 | offset = get16 (); | |
7388 | seg = get16 (); | |
7389 | } | |
7d421014 | 7390 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 7391 | if (intel_syntax) |
3f31e633 | 7392 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
7393 | else |
7394 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 7395 | oappend (scratchbuf); |
252b5132 RH |
7396 | } |
7397 | ||
252b5132 | 7398 | static void |
3f31e633 | 7399 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 7400 | { |
52b15da3 | 7401 | bfd_vma off; |
252b5132 | 7402 | |
3f31e633 JB |
7403 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
7404 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
7405 | append_seg (); |
7406 | ||
cb712a9e | 7407 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
7408 | off = get32 (); |
7409 | else | |
7410 | off = get16 (); | |
7411 | ||
7412 | if (intel_syntax) | |
7413 | { | |
7414 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 7415 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 7416 | { |
d708bcba | 7417 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
7418 | oappend (":"); |
7419 | } | |
7420 | } | |
52b15da3 JH |
7421 | print_operand_value (scratchbuf, 1, off); |
7422 | oappend (scratchbuf); | |
7423 | } | |
6439fc28 | 7424 | |
52b15da3 | 7425 | static void |
3f31e633 | 7426 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
7427 | { |
7428 | bfd_vma off; | |
7429 | ||
539e75ad L |
7430 | if (address_mode != mode_64bit |
7431 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
7432 | { |
7433 | OP_OFF (bytemode, sizeflag); | |
7434 | return; | |
7435 | } | |
7436 | ||
3f31e633 JB |
7437 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
7438 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
7439 | append_seg (); |
7440 | ||
6608db57 | 7441 | off = get64 (); |
52b15da3 JH |
7442 | |
7443 | if (intel_syntax) | |
7444 | { | |
7445 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 7446 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 7447 | { |
d708bcba | 7448 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
7449 | oappend (":"); |
7450 | } | |
7451 | } | |
7452 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
7453 | oappend (scratchbuf); |
7454 | } | |
7455 | ||
7456 | static void | |
26ca5450 | 7457 | ptr_reg (int code, int sizeflag) |
252b5132 | 7458 | { |
2da11e11 | 7459 | const char *s; |
d708bcba | 7460 | |
1d9f512f | 7461 | *obufp++ = open_char; |
20f0a1fc | 7462 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 7463 | if (address_mode == mode_64bit) |
c1a64871 JH |
7464 | { |
7465 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 7466 | s = names32[code - eAX_reg]; |
c1a64871 | 7467 | else |
db6eb5be | 7468 | s = names64[code - eAX_reg]; |
c1a64871 | 7469 | } |
52b15da3 | 7470 | else if (sizeflag & AFLAG) |
252b5132 RH |
7471 | s = names32[code - eAX_reg]; |
7472 | else | |
7473 | s = names16[code - eAX_reg]; | |
7474 | oappend (s); | |
1d9f512f AM |
7475 | *obufp++ = close_char; |
7476 | *obufp = 0; | |
252b5132 RH |
7477 | } |
7478 | ||
7479 | static void | |
26ca5450 | 7480 | OP_ESreg (int code, int sizeflag) |
252b5132 | 7481 | { |
9306ca4a | 7482 | if (intel_syntax) |
52fd6d94 JB |
7483 | { |
7484 | switch (codep[-1]) | |
7485 | { | |
7486 | case 0x6d: /* insw/insl */ | |
7487 | intel_operand_size (z_mode, sizeflag); | |
7488 | break; | |
7489 | case 0xa5: /* movsw/movsl/movsq */ | |
7490 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
7491 | case 0xab: /* stosw/stosl */ | |
7492 | case 0xaf: /* scasw/scasl */ | |
7493 | intel_operand_size (v_mode, sizeflag); | |
7494 | break; | |
7495 | default: | |
7496 | intel_operand_size (b_mode, sizeflag); | |
7497 | } | |
7498 | } | |
d708bcba | 7499 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
7500 | ptr_reg (code, sizeflag); |
7501 | } | |
7502 | ||
7503 | static void | |
26ca5450 | 7504 | OP_DSreg (int code, int sizeflag) |
252b5132 | 7505 | { |
9306ca4a | 7506 | if (intel_syntax) |
52fd6d94 JB |
7507 | { |
7508 | switch (codep[-1]) | |
7509 | { | |
7510 | case 0x6f: /* outsw/outsl */ | |
7511 | intel_operand_size (z_mode, sizeflag); | |
7512 | break; | |
7513 | case 0xa5: /* movsw/movsl/movsq */ | |
7514 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
7515 | case 0xad: /* lodsw/lodsl/lodsq */ | |
7516 | intel_operand_size (v_mode, sizeflag); | |
7517 | break; | |
7518 | default: | |
7519 | intel_operand_size (b_mode, sizeflag); | |
7520 | } | |
7521 | } | |
252b5132 RH |
7522 | if ((prefixes |
7523 | & (PREFIX_CS | |
7524 | | PREFIX_DS | |
7525 | | PREFIX_SS | |
7526 | | PREFIX_ES | |
7527 | | PREFIX_FS | |
7528 | | PREFIX_GS)) == 0) | |
7529 | prefixes |= PREFIX_DS; | |
6608db57 | 7530 | append_seg (); |
252b5132 RH |
7531 | ptr_reg (code, sizeflag); |
7532 | } | |
7533 | ||
252b5132 | 7534 | static void |
26ca5450 | 7535 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 7536 | { |
9b60702d | 7537 | int add; |
161a04f6 | 7538 | if (rex & REX_R) |
c4a530c5 | 7539 | { |
161a04f6 | 7540 | USED_REX (REX_R); |
c4a530c5 JB |
7541 | add = 8; |
7542 | } | |
cb712a9e | 7543 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 7544 | { |
b844680a | 7545 | lock_prefix = NULL; |
c4a530c5 JB |
7546 | used_prefixes |= PREFIX_LOCK; |
7547 | add = 8; | |
7548 | } | |
9b60702d L |
7549 | else |
7550 | add = 0; | |
7967e09e | 7551 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 7552 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
7553 | } |
7554 | ||
252b5132 | 7555 | static void |
26ca5450 | 7556 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 7557 | { |
9b60702d | 7558 | int add; |
161a04f6 L |
7559 | USED_REX (REX_R); |
7560 | if (rex & REX_R) | |
52b15da3 | 7561 | add = 8; |
9b60702d L |
7562 | else |
7563 | add = 0; | |
d708bcba | 7564 | if (intel_syntax) |
7967e09e | 7565 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 7566 | else |
7967e09e | 7567 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
7568 | oappend (scratchbuf); |
7569 | } | |
7570 | ||
252b5132 | 7571 | static void |
26ca5450 | 7572 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 7573 | { |
7967e09e | 7574 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 7575 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
7576 | } |
7577 | ||
7578 | static void | |
6f74c397 | 7579 | OP_R (int bytemode, int sizeflag) |
252b5132 | 7580 | { |
7967e09e | 7581 | if (modrm.mod == 3) |
2da11e11 AM |
7582 | OP_E (bytemode, sizeflag); |
7583 | else | |
6608db57 | 7584 | BadOp (); |
252b5132 RH |
7585 | } |
7586 | ||
7587 | static void | |
26ca5450 | 7588 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 7589 | { |
041bd2e0 JH |
7590 | used_prefixes |= (prefixes & PREFIX_DATA); |
7591 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 7592 | { |
9b60702d | 7593 | int add; |
161a04f6 L |
7594 | USED_REX (REX_R); |
7595 | if (rex & REX_R) | |
20f0a1fc | 7596 | add = 8; |
9b60702d L |
7597 | else |
7598 | add = 0; | |
7967e09e | 7599 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); |
20f0a1fc | 7600 | } |
041bd2e0 | 7601 | else |
7967e09e | 7602 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
d708bcba | 7603 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
7604 | } |
7605 | ||
c608c12e | 7606 | static void |
26ca5450 | 7607 | OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 7608 | { |
9b60702d | 7609 | int add; |
161a04f6 L |
7610 | USED_REX (REX_R); |
7611 | if (rex & REX_R) | |
041bd2e0 | 7612 | add = 8; |
9b60702d L |
7613 | else |
7614 | add = 0; | |
7967e09e | 7615 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); |
d708bcba | 7616 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
7617 | } |
7618 | ||
252b5132 | 7619 | static void |
26ca5450 | 7620 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 7621 | { |
7967e09e | 7622 | if (modrm.mod != 3) |
252b5132 | 7623 | { |
9306ca4a JB |
7624 | if (intel_syntax && bytemode == v_mode) |
7625 | { | |
7626 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
7627 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7628 | } | |
252b5132 RH |
7629 | OP_E (bytemode, sizeflag); |
7630 | return; | |
7631 | } | |
7632 | ||
6608db57 | 7633 | /* Skip mod/rm byte. */ |
4bba6815 | 7634 | MODRM_CHECK; |
252b5132 | 7635 | codep++; |
041bd2e0 JH |
7636 | used_prefixes |= (prefixes & PREFIX_DATA); |
7637 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 7638 | { |
9b60702d | 7639 | int add; |
20f0a1fc | 7640 | |
161a04f6 L |
7641 | USED_REX (REX_B); |
7642 | if (rex & REX_B) | |
20f0a1fc | 7643 | add = 8; |
9b60702d L |
7644 | else |
7645 | add = 0; | |
7967e09e | 7646 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); |
20f0a1fc | 7647 | } |
041bd2e0 | 7648 | else |
7967e09e | 7649 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
d708bcba | 7650 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
7651 | } |
7652 | ||
246c51aa L |
7653 | /* cvt* are the only instructions in sse2 which have |
7654 | both SSE and MMX operands and also have 0x66 prefix | |
7655 | in their opcode. 0x66 was originally used to differentiate | |
7656 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
7657 | cvt* separately using OP_EMC and OP_MXC */ |
7658 | static void | |
7659 | OP_EMC (int bytemode, int sizeflag) | |
7660 | { | |
7967e09e | 7661 | if (modrm.mod != 3) |
4d9567e0 MM |
7662 | { |
7663 | if (intel_syntax && bytemode == v_mode) | |
7664 | { | |
7665 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
7666 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7667 | } | |
7668 | OP_E (bytemode, sizeflag); | |
7669 | return; | |
7670 | } | |
246c51aa | 7671 | |
4d9567e0 MM |
7672 | /* Skip mod/rm byte. */ |
7673 | MODRM_CHECK; | |
7674 | codep++; | |
7675 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 7676 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
4d9567e0 MM |
7677 | oappend (scratchbuf + intel_syntax); |
7678 | } | |
7679 | ||
7680 | static void | |
7681 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
7682 | { | |
7683 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 7684 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
4d9567e0 MM |
7685 | oappend (scratchbuf + intel_syntax); |
7686 | } | |
7687 | ||
c608c12e | 7688 | static void |
26ca5450 | 7689 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 7690 | { |
9b60702d | 7691 | int add; |
7967e09e | 7692 | if (modrm.mod != 3) |
c608c12e AM |
7693 | { |
7694 | OP_E (bytemode, sizeflag); | |
7695 | return; | |
7696 | } | |
161a04f6 L |
7697 | USED_REX (REX_B); |
7698 | if (rex & REX_B) | |
041bd2e0 | 7699 | add = 8; |
9b60702d L |
7700 | else |
7701 | add = 0; | |
c608c12e | 7702 | |
6608db57 | 7703 | /* Skip mod/rm byte. */ |
4bba6815 | 7704 | MODRM_CHECK; |
c608c12e | 7705 | codep++; |
7967e09e | 7706 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); |
d708bcba | 7707 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
7708 | } |
7709 | ||
252b5132 | 7710 | static void |
26ca5450 | 7711 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 7712 | { |
7967e09e | 7713 | if (modrm.mod == 3) |
2da11e11 AM |
7714 | OP_EM (bytemode, sizeflag); |
7715 | else | |
6608db57 | 7716 | BadOp (); |
252b5132 RH |
7717 | } |
7718 | ||
992aaec9 | 7719 | static void |
26ca5450 | 7720 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 7721 | { |
7967e09e | 7722 | if (modrm.mod == 3) |
992aaec9 AM |
7723 | OP_EX (bytemode, sizeflag); |
7724 | else | |
6608db57 | 7725 | BadOp (); |
992aaec9 AM |
7726 | } |
7727 | ||
cc0ec051 AM |
7728 | static void |
7729 | OP_M (int bytemode, int sizeflag) | |
7730 | { | |
7967e09e | 7731 | if (modrm.mod == 3) |
75413a22 L |
7732 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
7733 | BadOp (); | |
cc0ec051 AM |
7734 | else |
7735 | OP_E (bytemode, sizeflag); | |
7736 | } | |
7737 | ||
7738 | static void | |
7739 | OP_0f07 (int bytemode, int sizeflag) | |
7740 | { | |
7967e09e | 7741 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
7742 | BadOp (); |
7743 | else | |
7744 | OP_E (bytemode, sizeflag); | |
7745 | } | |
7746 | ||
46e883c5 | 7747 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 7748 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 7749 | |
cc0ec051 | 7750 | static void |
46e883c5 | 7751 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 7752 | { |
8b38ad71 L |
7753 | if ((prefixes & PREFIX_DATA) != 0 |
7754 | || (rex != 0 | |
7755 | && rex != 0x48 | |
7756 | && address_mode == mode_64bit)) | |
46e883c5 L |
7757 | OP_REG (bytemode, sizeflag); |
7758 | else | |
7759 | strcpy (obuf, "nop"); | |
7760 | } | |
7761 | ||
7762 | static void | |
7763 | NOP_Fixup2 (int bytemode, int sizeflag) | |
7764 | { | |
8b38ad71 L |
7765 | if ((prefixes & PREFIX_DATA) != 0 |
7766 | || (rex != 0 | |
7767 | && rex != 0x48 | |
7768 | && address_mode == mode_64bit)) | |
46e883c5 | 7769 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
7770 | } |
7771 | ||
84037f8c | 7772 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
7773 | /* 00 */ NULL, NULL, NULL, NULL, |
7774 | /* 04 */ NULL, NULL, NULL, NULL, | |
7775 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 7776 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
7777 | /* 10 */ NULL, NULL, NULL, NULL, |
7778 | /* 14 */ NULL, NULL, NULL, NULL, | |
7779 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 7780 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
7781 | /* 20 */ NULL, NULL, NULL, NULL, |
7782 | /* 24 */ NULL, NULL, NULL, NULL, | |
7783 | /* 28 */ NULL, NULL, NULL, NULL, | |
7784 | /* 2C */ NULL, NULL, NULL, NULL, | |
7785 | /* 30 */ NULL, NULL, NULL, NULL, | |
7786 | /* 34 */ NULL, NULL, NULL, NULL, | |
7787 | /* 38 */ NULL, NULL, NULL, NULL, | |
7788 | /* 3C */ NULL, NULL, NULL, NULL, | |
7789 | /* 40 */ NULL, NULL, NULL, NULL, | |
7790 | /* 44 */ NULL, NULL, NULL, NULL, | |
7791 | /* 48 */ NULL, NULL, NULL, NULL, | |
7792 | /* 4C */ NULL, NULL, NULL, NULL, | |
7793 | /* 50 */ NULL, NULL, NULL, NULL, | |
7794 | /* 54 */ NULL, NULL, NULL, NULL, | |
7795 | /* 58 */ NULL, NULL, NULL, NULL, | |
7796 | /* 5C */ NULL, NULL, NULL, NULL, | |
7797 | /* 60 */ NULL, NULL, NULL, NULL, | |
7798 | /* 64 */ NULL, NULL, NULL, NULL, | |
7799 | /* 68 */ NULL, NULL, NULL, NULL, | |
7800 | /* 6C */ NULL, NULL, NULL, NULL, | |
7801 | /* 70 */ NULL, NULL, NULL, NULL, | |
7802 | /* 74 */ NULL, NULL, NULL, NULL, | |
7803 | /* 78 */ NULL, NULL, NULL, NULL, | |
7804 | /* 7C */ NULL, NULL, NULL, NULL, | |
7805 | /* 80 */ NULL, NULL, NULL, NULL, | |
7806 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
7807 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
7808 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
7809 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
7810 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
7811 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
7812 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
7813 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
7814 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
7815 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
7816 | /* AC */ NULL, NULL, "pfacc", NULL, | |
7817 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 7818 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 7819 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
7820 | /* BC */ NULL, NULL, NULL, "pavgusb", |
7821 | /* C0 */ NULL, NULL, NULL, NULL, | |
7822 | /* C4 */ NULL, NULL, NULL, NULL, | |
7823 | /* C8 */ NULL, NULL, NULL, NULL, | |
7824 | /* CC */ NULL, NULL, NULL, NULL, | |
7825 | /* D0 */ NULL, NULL, NULL, NULL, | |
7826 | /* D4 */ NULL, NULL, NULL, NULL, | |
7827 | /* D8 */ NULL, NULL, NULL, NULL, | |
7828 | /* DC */ NULL, NULL, NULL, NULL, | |
7829 | /* E0 */ NULL, NULL, NULL, NULL, | |
7830 | /* E4 */ NULL, NULL, NULL, NULL, | |
7831 | /* E8 */ NULL, NULL, NULL, NULL, | |
7832 | /* EC */ NULL, NULL, NULL, NULL, | |
7833 | /* F0 */ NULL, NULL, NULL, NULL, | |
7834 | /* F4 */ NULL, NULL, NULL, NULL, | |
7835 | /* F8 */ NULL, NULL, NULL, NULL, | |
7836 | /* FC */ NULL, NULL, NULL, NULL, | |
7837 | }; | |
7838 | ||
7839 | static void | |
26ca5450 | 7840 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
7841 | { |
7842 | const char *mnemonic; | |
7843 | ||
7844 | FETCH_DATA (the_info, codep + 1); | |
7845 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
7846 | place where an 8-bit immediate would normally go. ie. the last | |
7847 | byte of the instruction. */ | |
6608db57 | 7848 | obufp = obuf + strlen (obuf); |
c608c12e | 7849 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 7850 | if (mnemonic) |
2da11e11 | 7851 | oappend (mnemonic); |
252b5132 RH |
7852 | else |
7853 | { | |
7854 | /* Since a variable sized modrm/sib chunk is between the start | |
7855 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
7856 | all the modrm processing first, and don't know until now that | |
7857 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
7858 | op_out[0][0] = '\0'; |
7859 | op_out[1][0] = '\0'; | |
6608db57 | 7860 | BadOp (); |
252b5132 RH |
7861 | } |
7862 | } | |
c608c12e | 7863 | |
6608db57 | 7864 | static const char *simd_cmp_op[] = { |
c608c12e AM |
7865 | "eq", |
7866 | "lt", | |
7867 | "le", | |
7868 | "unord", | |
7869 | "neq", | |
7870 | "nlt", | |
7871 | "nle", | |
7872 | "ord" | |
7873 | }; | |
7874 | ||
7875 | static void | |
ad19981d | 7876 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
7877 | { |
7878 | unsigned int cmp_type; | |
7879 | ||
7880 | FETCH_DATA (the_info, codep + 1); | |
7881 | cmp_type = *codep++ & 0xff; | |
7882 | if (cmp_type < 8) | |
7883 | { | |
ad19981d L |
7884 | char suffix [3]; |
7885 | char *p = obuf + strlen (obuf) - 2; | |
7886 | suffix[0] = p[0]; | |
7887 | suffix[1] = p[1]; | |
7888 | suffix[2] = '\0'; | |
7889 | sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix); | |
c608c12e AM |
7890 | } |
7891 | else | |
7892 | { | |
ad19981d L |
7893 | /* We have a reserved extension byte. Output it directly. */ |
7894 | scratchbuf[0] = '$'; | |
7895 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
7896 | oappend (scratchbuf + intel_syntax); | |
7897 | scratchbuf[0] = '\0'; | |
c608c12e AM |
7898 | } |
7899 | } | |
7900 | ||
ca164297 | 7901 | static void |
b844680a L |
7902 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
7903 | int sizeflag ATTRIBUTE_UNUSED) | |
7904 | { | |
7905 | /* mwait %eax,%ecx */ | |
7906 | if (!intel_syntax) | |
7907 | { | |
7908 | const char **names = (address_mode == mode_64bit | |
7909 | ? names64 : names32); | |
7910 | strcpy (op_out[0], names[0]); | |
7911 | strcpy (op_out[1], names[1]); | |
7912 | two_source_ops = 1; | |
7913 | } | |
7914 | /* Skip mod/rm byte. */ | |
7915 | MODRM_CHECK; | |
7916 | codep++; | |
7917 | } | |
7918 | ||
7919 | static void | |
7920 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
7921 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 7922 | { |
b844680a L |
7923 | /* monitor %eax,%ecx,%edx" */ |
7924 | if (!intel_syntax) | |
ca164297 | 7925 | { |
b844680a | 7926 | const char **op1_names; |
cb712a9e L |
7927 | const char **names = (address_mode == mode_64bit |
7928 | ? names64 : names32); | |
1d9f512f | 7929 | |
b844680a L |
7930 | if (!(prefixes & PREFIX_ADDR)) |
7931 | op1_names = (address_mode == mode_16bit | |
7932 | ? names16 : names); | |
ca164297 L |
7933 | else |
7934 | { | |
b844680a L |
7935 | /* Remove "addr16/addr32". */ |
7936 | addr_prefix = NULL; | |
7937 | op1_names = (address_mode != mode_32bit | |
7938 | ? names32 : names16); | |
7939 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 7940 | } |
b844680a L |
7941 | strcpy (op_out[0], op1_names[0]); |
7942 | strcpy (op_out[1], names[1]); | |
7943 | strcpy (op_out[2], names[2]); | |
7944 | two_source_ops = 1; | |
ca164297 | 7945 | } |
b844680a L |
7946 | /* Skip mod/rm byte. */ |
7947 | MODRM_CHECK; | |
7948 | codep++; | |
30123838 JB |
7949 | } |
7950 | ||
6608db57 KH |
7951 | static void |
7952 | BadOp (void) | |
2da11e11 | 7953 | { |
6608db57 KH |
7954 | /* Throw away prefixes and 1st. opcode byte. */ |
7955 | codep = insn_codep + 1; | |
2da11e11 AM |
7956 | oappend ("(bad)"); |
7957 | } | |
4cc91dba | 7958 | |
35c52694 L |
7959 | static void |
7960 | REP_Fixup (int bytemode, int sizeflag) | |
7961 | { | |
7962 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
7963 | lods and stos. */ | |
35c52694 | 7964 | if (prefixes & PREFIX_REPZ) |
b844680a | 7965 | repz_prefix = "rep "; |
35c52694 L |
7966 | |
7967 | switch (bytemode) | |
7968 | { | |
7969 | case al_reg: | |
7970 | case eAX_reg: | |
7971 | case indir_dx_reg: | |
7972 | OP_IMREG (bytemode, sizeflag); | |
7973 | break; | |
7974 | case eDI_reg: | |
7975 | OP_ESreg (bytemode, sizeflag); | |
7976 | break; | |
7977 | case eSI_reg: | |
7978 | OP_DSreg (bytemode, sizeflag); | |
7979 | break; | |
7980 | default: | |
7981 | abort (); | |
7982 | break; | |
7983 | } | |
7984 | } | |
f5804c90 L |
7985 | |
7986 | static void | |
7987 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
7988 | { | |
161a04f6 L |
7989 | USED_REX (REX_W); |
7990 | if (rex & REX_W) | |
f5804c90 L |
7991 | { |
7992 | /* Change cmpxchg8b to cmpxchg16b. */ | |
7993 | char *p = obuf + strlen (obuf) - 2; | |
7994 | strcpy (p, "16b"); | |
fb9c77c7 | 7995 | bytemode = o_mode; |
f5804c90 L |
7996 | } |
7997 | OP_M (bytemode, sizeflag); | |
7998 | } | |
42903f7f L |
7999 | |
8000 | static void | |
8001 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
8002 | { | |
8003 | sprintf (scratchbuf, "%%xmm%d", reg); | |
8004 | oappend (scratchbuf + intel_syntax); | |
8005 | } | |
381d071f L |
8006 | |
8007 | static void | |
8008 | CRC32_Fixup (int bytemode, int sizeflag) | |
8009 | { | |
8010 | /* Add proper suffix to "crc32". */ | |
8011 | char *p = obuf + strlen (obuf); | |
8012 | ||
8013 | switch (bytemode) | |
8014 | { | |
8015 | case b_mode: | |
20592a94 L |
8016 | if (intel_syntax) |
8017 | break; | |
8018 | ||
381d071f L |
8019 | *p++ = 'b'; |
8020 | break; | |
8021 | case v_mode: | |
20592a94 L |
8022 | if (intel_syntax) |
8023 | break; | |
8024 | ||
381d071f L |
8025 | USED_REX (REX_W); |
8026 | if (rex & REX_W) | |
8027 | *p++ = 'q'; | |
9344ff29 | 8028 | else if (sizeflag & DFLAG) |
20592a94 | 8029 | *p++ = 'l'; |
381d071f | 8030 | else |
9344ff29 L |
8031 | *p++ = 'w'; |
8032 | used_prefixes |= (prefixes & PREFIX_DATA); | |
381d071f L |
8033 | break; |
8034 | default: | |
8035 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
8036 | break; | |
8037 | } | |
8038 | *p = '\0'; | |
8039 | ||
8040 | if (modrm.mod == 3) | |
8041 | { | |
8042 | int add; | |
8043 | ||
8044 | /* Skip mod/rm byte. */ | |
8045 | MODRM_CHECK; | |
8046 | codep++; | |
8047 | ||
8048 | USED_REX (REX_B); | |
8049 | add = (rex & REX_B) ? 8 : 0; | |
8050 | if (bytemode == b_mode) | |
8051 | { | |
8052 | USED_REX (0); | |
8053 | if (rex) | |
8054 | oappend (names8rex[modrm.rm + add]); | |
8055 | else | |
8056 | oappend (names8[modrm.rm + add]); | |
8057 | } | |
8058 | else | |
8059 | { | |
8060 | USED_REX (REX_W); | |
8061 | if (rex & REX_W) | |
8062 | oappend (names64[modrm.rm + add]); | |
8063 | else if ((prefixes & PREFIX_DATA)) | |
8064 | oappend (names16[modrm.rm + add]); | |
8065 | else | |
8066 | oappend (names32[modrm.rm + add]); | |
8067 | } | |
8068 | } | |
8069 | else | |
9344ff29 | 8070 | OP_E (bytemode, sizeflag); |
381d071f | 8071 | } |
85f10a01 MM |
8072 | |
8073 | /* Print a DREX argument as either a register or memory operation. */ | |
8074 | static void | |
8075 | print_drex_arg (unsigned int reg, int bytemode, int sizeflag) | |
8076 | { | |
8077 | if (reg == DREX_REG_UNKNOWN) | |
8078 | BadOp (); | |
8079 | ||
8080 | else if (reg != DREX_REG_MEMORY) | |
8081 | { | |
8082 | sprintf (scratchbuf, "%%xmm%d", reg); | |
8083 | oappend (scratchbuf + intel_syntax); | |
8084 | } | |
8085 | ||
8086 | else | |
8087 | OP_E_extended (bytemode, sizeflag, 1); | |
8088 | } | |
8089 | ||
8090 | /* SSE5 instructions that have 4 arguments are encoded as: | |
8091 | 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>. | |
8092 | ||
8093 | The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in | |
8094 | the DREX field (0x8) to determine how the arguments are laid out. | |
8095 | The destination register must be the same register as one of the | |
8096 | inputs, and it is encoded in the DREX byte. No REX prefix is used | |
8097 | for these instructions, since the DREX field contains the 3 extension | |
8098 | bits provided by the REX prefix. | |
8099 | ||
8100 | The bytemode argument adds 2 extra bits for passing extra information: | |
8101 | DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg | |
8102 | DREX_NO_OC0 -- OC0 in DREX is invalid | |
8103 | (but pretend it is set). */ | |
8104 | ||
8105 | static void | |
8106 | OP_DREX4 (int flag_bytemode, int sizeflag) | |
8107 | { | |
8108 | unsigned int drex_byte; | |
8109 | unsigned int regs[4]; | |
8110 | unsigned int modrm_regmem; | |
8111 | unsigned int modrm_reg; | |
8112 | unsigned int drex_reg; | |
8113 | int bytemode; | |
8114 | int rex_save = rex; | |
8115 | int rex_used_save = rex_used; | |
8116 | int has_sib = 0; | |
8117 | int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0; | |
8118 | int oc0; | |
8119 | int i; | |
8120 | ||
8121 | bytemode = flag_bytemode & ~ DREX_MASK; | |
8122 | ||
8123 | for (i = 0; i < 4; i++) | |
8124 | regs[i] = DREX_REG_UNKNOWN; | |
8125 | ||
8126 | /* Determine if we have a SIB byte in addition to MODRM before the | |
8127 | DREX byte. */ | |
8128 | if (((sizeflag & AFLAG) || address_mode == mode_64bit) | |
8129 | && (modrm.mod != 3) | |
8130 | && (modrm.rm == 4)) | |
8131 | has_sib = 1; | |
8132 | ||
8133 | /* Get the DREX byte. */ | |
8134 | FETCH_DATA (the_info, codep + 2 + has_sib); | |
8135 | drex_byte = codep[has_sib+1]; | |
8136 | drex_reg = DREX_XMM (drex_byte); | |
8137 | modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0); | |
8138 | ||
8139 | /* Is OC0 legal? If not, hardwire oc0 == 1. */ | |
8140 | if (flag_bytemode & DREX_NO_OC0) | |
8141 | { | |
8142 | oc0 = 1; | |
8143 | if (DREX_OC0 (drex_byte)) | |
8144 | BadOp (); | |
8145 | } | |
8146 | else | |
8147 | oc0 = DREX_OC0 (drex_byte); | |
8148 | ||
8149 | if (modrm.mod == 3) | |
8150 | { | |
8151 | /* regmem == register */ | |
8152 | modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0); | |
8153 | rex = rex_used = 0; | |
8154 | /* skip modrm/drex since we don't call OP_E_extended */ | |
8155 | codep += 2; | |
8156 | } | |
8157 | else | |
8158 | { | |
8159 | /* regmem == memory, fill in appropriate REX bits */ | |
8160 | modrm_regmem = DREX_REG_MEMORY; | |
8161 | rex = drex_byte & (REX_B | REX_X | REX_R); | |
8162 | if (rex) | |
8163 | rex |= REX_OPCODE; | |
8164 | rex_used = rex; | |
8165 | } | |
8166 | ||
8167 | /* Based on the OC1/OC0 bits, lay out the arguments in the correct | |
8168 | order. */ | |
8169 | switch (oc0 + oc1) | |
8170 | { | |
8171 | default: | |
8172 | BadOp (); | |
8173 | return; | |
8174 | ||
8175 | case 0: | |
8176 | regs[0] = modrm_regmem; | |
8177 | regs[1] = modrm_reg; | |
8178 | regs[2] = drex_reg; | |
8179 | regs[3] = drex_reg; | |
8180 | break; | |
8181 | ||
8182 | case 1: | |
8183 | regs[0] = modrm_reg; | |
8184 | regs[1] = modrm_regmem; | |
8185 | regs[2] = drex_reg; | |
8186 | regs[3] = drex_reg; | |
8187 | break; | |
8188 | ||
8189 | case 2: | |
8190 | regs[0] = drex_reg; | |
8191 | regs[1] = modrm_regmem; | |
8192 | regs[2] = modrm_reg; | |
8193 | regs[3] = drex_reg; | |
8194 | break; | |
8195 | ||
8196 | case 3: | |
8197 | regs[0] = drex_reg; | |
8198 | regs[1] = modrm_reg; | |
8199 | regs[2] = modrm_regmem; | |
8200 | regs[3] = drex_reg; | |
8201 | break; | |
8202 | } | |
8203 | ||
8204 | /* Print out the arguments. */ | |
8205 | for (i = 0; i < 4; i++) | |
8206 | { | |
8207 | int j = (intel_syntax) ? 3 - i : i; | |
8208 | if (i > 0) | |
8209 | { | |
8210 | *obufp++ = ','; | |
8211 | *obufp = '\0'; | |
8212 | } | |
8213 | ||
8214 | print_drex_arg (regs[j], bytemode, sizeflag); | |
8215 | } | |
8216 | ||
8217 | rex = rex_save; | |
8218 | rex_used = rex_used_save; | |
8219 | } | |
8220 | ||
8221 | /* SSE5 instructions that have 3 arguments, and are encoded as: | |
8222 | 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or) | |
8223 | 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte> | |
8224 | ||
8225 | The DREX field has 1 bit (0x8) to determine how the arguments are | |
8226 | laid out. The destination register is encoded in the DREX byte. | |
8227 | No REX prefix is used for these instructions, since the DREX field | |
8228 | contains the 3 extension bits provided by the REX prefix. */ | |
8229 | ||
8230 | static void | |
8231 | OP_DREX3 (int flag_bytemode, int sizeflag) | |
8232 | { | |
8233 | unsigned int drex_byte; | |
8234 | unsigned int regs[3]; | |
8235 | unsigned int modrm_regmem; | |
8236 | unsigned int modrm_reg; | |
8237 | unsigned int drex_reg; | |
8238 | int bytemode; | |
8239 | int rex_save = rex; | |
8240 | int rex_used_save = rex_used; | |
8241 | int has_sib = 0; | |
8242 | int oc0; | |
8243 | int i; | |
8244 | ||
8245 | bytemode = flag_bytemode & ~ DREX_MASK; | |
8246 | ||
8247 | for (i = 0; i < 3; i++) | |
8248 | regs[i] = DREX_REG_UNKNOWN; | |
8249 | ||
8250 | /* Determine if we have a SIB byte in addition to MODRM before the | |
8251 | DREX byte. */ | |
8252 | if (((sizeflag & AFLAG) || address_mode == mode_64bit) | |
8253 | && (modrm.mod != 3) | |
8254 | && (modrm.rm == 4)) | |
8255 | has_sib = 1; | |
8256 | ||
8257 | /* Get the DREX byte. */ | |
8258 | FETCH_DATA (the_info, codep + 2 + has_sib); | |
8259 | drex_byte = codep[has_sib+1]; | |
8260 | drex_reg = DREX_XMM (drex_byte); | |
8261 | modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0); | |
8262 | ||
8263 | /* Is OC0 legal? If not, hardwire oc0 == 0 */ | |
8264 | oc0 = DREX_OC0 (drex_byte); | |
8265 | if ((flag_bytemode & DREX_NO_OC0) && oc0) | |
8266 | BadOp (); | |
8267 | ||
8268 | if (modrm.mod == 3) | |
8269 | { | |
8270 | /* regmem == register */ | |
8271 | modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0); | |
8272 | rex = rex_used = 0; | |
8273 | /* skip modrm/drex since we don't call OP_E_extended. */ | |
8274 | codep += 2; | |
8275 | } | |
8276 | else | |
8277 | { | |
8278 | /* regmem == memory, fill in appropriate REX bits. */ | |
8279 | modrm_regmem = DREX_REG_MEMORY; | |
8280 | rex = drex_byte & (REX_B | REX_X | REX_R); | |
8281 | if (rex) | |
8282 | rex |= REX_OPCODE; | |
8283 | rex_used = rex; | |
8284 | } | |
8285 | ||
8286 | /* Based on the OC1/OC0 bits, lay out the arguments in the correct | |
8287 | order. */ | |
8288 | switch (oc0) | |
8289 | { | |
8290 | default: | |
8291 | BadOp (); | |
8292 | return; | |
8293 | ||
8294 | case 0: | |
8295 | regs[0] = modrm_regmem; | |
8296 | regs[1] = modrm_reg; | |
8297 | regs[2] = drex_reg; | |
8298 | break; | |
8299 | ||
8300 | case 1: | |
8301 | regs[0] = modrm_reg; | |
8302 | regs[1] = modrm_regmem; | |
8303 | regs[2] = drex_reg; | |
8304 | break; | |
8305 | } | |
8306 | ||
8307 | /* Print out the arguments. */ | |
8308 | for (i = 0; i < 3; i++) | |
8309 | { | |
8310 | int j = (intel_syntax) ? 2 - i : i; | |
8311 | if (i > 0) | |
8312 | { | |
8313 | *obufp++ = ','; | |
8314 | *obufp = '\0'; | |
8315 | } | |
8316 | ||
8317 | print_drex_arg (regs[j], bytemode, sizeflag); | |
8318 | } | |
8319 | ||
8320 | rex = rex_save; | |
8321 | rex_used = rex_used_save; | |
8322 | } | |
8323 | ||
8324 | /* Emit a floating point comparison for comp<xx> instructions. */ | |
8325 | ||
8326 | static void | |
8327 | OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED, | |
8328 | int sizeflag ATTRIBUTE_UNUSED) | |
8329 | { | |
8330 | unsigned char byte; | |
8331 | ||
8332 | static const char *const cmp_test[] = { | |
8333 | "eq", | |
8334 | "lt", | |
8335 | "le", | |
8336 | "unord", | |
8337 | "ne", | |
8338 | "nlt", | |
8339 | "nle", | |
8340 | "ord", | |
8341 | "ueq", | |
8342 | "ult", | |
8343 | "ule", | |
8344 | "false", | |
8345 | "une", | |
8346 | "unlt", | |
8347 | "unle", | |
8348 | "true" | |
8349 | }; | |
8350 | ||
8351 | FETCH_DATA (the_info, codep + 1); | |
8352 | byte = *codep & 0xff; | |
8353 | ||
8354 | if (byte >= ARRAY_SIZE (cmp_test) | |
8355 | || obuf[0] != 'c' | |
8356 | || obuf[1] != 'o' | |
8357 | || obuf[2] != 'm') | |
8358 | { | |
8359 | /* The instruction isn't one we know about, so just append the | |
8360 | extension byte as a numeric value. */ | |
8361 | OP_I (b_mode, 0); | |
8362 | } | |
8363 | ||
8364 | else | |
8365 | { | |
8366 | sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3); | |
8367 | strcpy (obuf, scratchbuf); | |
8368 | codep++; | |
8369 | } | |
8370 | } | |
8371 | ||
8372 | /* Emit an integer point comparison for pcom<xx> instructions, | |
8373 | rewriting the instruction to have the test inside of it. */ | |
8374 | ||
8375 | static void | |
8376 | OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED, | |
8377 | int sizeflag ATTRIBUTE_UNUSED) | |
8378 | { | |
8379 | unsigned char byte; | |
8380 | ||
8381 | static const char *const cmp_test[] = { | |
8382 | "lt", | |
8383 | "le", | |
8384 | "gt", | |
8385 | "ge", | |
8386 | "eq", | |
8387 | "ne", | |
8388 | "false", | |
8389 | "true" | |
8390 | }; | |
8391 | ||
8392 | FETCH_DATA (the_info, codep + 1); | |
8393 | byte = *codep & 0xff; | |
8394 | ||
8395 | if (byte >= ARRAY_SIZE (cmp_test) | |
8396 | || obuf[0] != 'p' | |
8397 | || obuf[1] != 'c' | |
8398 | || obuf[2] != 'o' | |
8399 | || obuf[3] != 'm') | |
8400 | { | |
8401 | /* The instruction isn't one we know about, so just print the | |
8402 | comparison test byte as a numeric value. */ | |
8403 | OP_I (b_mode, 0); | |
8404 | } | |
8405 | ||
8406 | else | |
8407 | { | |
8408 | sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4); | |
8409 | strcpy (obuf, scratchbuf); | |
8410 | codep++; | |
8411 | } | |
8412 | } |