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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450 97static void OP_3DNowSuffix (int, int);
ad19981d 98static void CMP_Fixup (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
4ee52178 239#define Mx { OP_M, x_mode }
ce518a5f
L		 240#define Gb { OP_G, b_mode }
241#define Gv { OP_G, v_mode }
242#define Gd { OP_G, d_mode }
243#define Gdq { OP_G, dq_mode }
244#define Gm { OP_G, m_mode }
245#define Gw { OP_G, w_mode }
6f74c397
L		 246#define Rd { OP_R, d_mode }
247#define Rm { OP_R, m_mode }
ce518a5f
L		 248#define Ib { OP_I, b_mode }
249#define sIb { OP_sI, b_mode } /* sign extened byte */
250#define Iv { OP_I, v_mode }
251#define Iq { OP_I, q_mode }
252#define Iv64 { OP_I64, v_mode }
253#define Iw { OP_I, w_mode }
254#define I1 { OP_I, const_1_mode }
255#define Jb { OP_J, b_mode }
256#define Jv { OP_J, v_mode }
257#define Cm { OP_C, m_mode }
258#define Dm { OP_D, m_mode }
259#define Td { OP_T, d_mode }
b844680a 260#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 261
262#define RMeAX { OP_REG, eAX_reg }
263#define RMeBX { OP_REG, eBX_reg }
264#define RMeCX { OP_REG, eCX_reg }
265#define RMeDX { OP_REG, eDX_reg }
266#define RMeSP { OP_REG, eSP_reg }
267#define RMeBP { OP_REG, eBP_reg }
268#define RMeSI { OP_REG, eSI_reg }
269#define RMeDI { OP_REG, eDI_reg }
270#define RMrAX { OP_REG, rAX_reg }
271#define RMrBX { OP_REG, rBX_reg }
272#define RMrCX { OP_REG, rCX_reg }
273#define RMrDX { OP_REG, rDX_reg }
274#define RMrSP { OP_REG, rSP_reg }
275#define RMrBP { OP_REG, rBP_reg }
276#define RMrSI { OP_REG, rSI_reg }
277#define RMrDI { OP_REG, rDI_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMAL { OP_REG, al_reg }
280#define RMCL { OP_REG, cl_reg }
281#define RMDL { OP_REG, dl_reg }
282#define RMBL { OP_REG, bl_reg }
283#define RMAH { OP_REG, ah_reg }
284#define RMCH { OP_REG, ch_reg }
285#define RMDH { OP_REG, dh_reg }
286#define RMBH { OP_REG, bh_reg }
287#define RMAX { OP_REG, ax_reg }
288#define RMDX { OP_REG, dx_reg }
289
290#define eAX { OP_IMREG, eAX_reg }
291#define eBX { OP_IMREG, eBX_reg }
292#define eCX { OP_IMREG, eCX_reg }
293#define eDX { OP_IMREG, eDX_reg }
294#define eSP { OP_IMREG, eSP_reg }
295#define eBP { OP_IMREG, eBP_reg }
296#define eSI { OP_IMREG, eSI_reg }
297#define eDI { OP_IMREG, eDI_reg }
298#define AL { OP_IMREG, al_reg }
299#define CL { OP_IMREG, cl_reg }
300#define DL { OP_IMREG, dl_reg }
301#define BL { OP_IMREG, bl_reg }
302#define AH { OP_IMREG, ah_reg }
303#define CH { OP_IMREG, ch_reg }
304#define DH { OP_IMREG, dh_reg }
305#define BH { OP_IMREG, bh_reg }
306#define AX { OP_IMREG, ax_reg }
307#define DX { OP_IMREG, dx_reg }
308#define zAX { OP_IMREG, z_mode_ax_reg }
309#define indirDX { OP_IMREG, indir_dx_reg }
310
311#define Sw { OP_SEG, w_mode }
312#define Sv { OP_SEG, v_mode }
313#define Ap { OP_DIR, 0 }
314#define Ob { OP_OFF64, b_mode }
315#define Ov { OP_OFF64, v_mode }
316#define Xb { OP_DSreg, eSI_reg }
317#define Xv { OP_DSreg, eSI_reg }
318#define Xz { OP_DSreg, eSI_reg }
319#define Yb { OP_ESreg, eDI_reg }
320#define Yv { OP_ESreg, eDI_reg }
321#define DSBX { OP_DSreg, eBX_reg }
322
323#define es { OP_REG, es_reg }
324#define ss { OP_REG, ss_reg }
325#define cs { OP_REG, cs_reg }
326#define ds { OP_REG, ds_reg }
327#define fs { OP_REG, fs_reg }
328#define gs { OP_REG, gs_reg }
329
330#define MX { OP_MMX, 0 }
331#define XM { OP_XMM, 0 }
332#define EM { OP_EM, v_mode }
09a2c6cf 333#define EMd { OP_EM, d_mode }
14051056 334#define EMx { OP_EM, x_mode }
8976381e 335#define EXw { OP_EX, w_mode }
09a2c6cf
L		 336#define EXd { OP_EX, d_mode }
337#define EXq { OP_EX, q_mode }
338#define EXx { OP_EX, x_mode }
ce518a5f
L		 339#define MS { OP_MS, v_mode }
340#define XS { OP_XS, v_mode }
09335d05 341#define EMCq { OP_EMC, q_mode }
ce518a5f 342#define MXC { OP_MXC, 0 }
ce518a5f 343#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 344#define CMP { CMP_Fixup, 0 }
42903f7f 345#define XMM0 { XMM_Fixup, 0 }
252b5132 346
35c52694 347/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 348#define Xbr { REP_Fixup, eSI_reg }
349#define Xvr { REP_Fixup, eSI_reg }
350#define Ybr { REP_Fixup, eDI_reg }
351#define Yvr { REP_Fixup, eDI_reg }
352#define Yzr { REP_Fixup, eDI_reg }
353#define indirDXr { REP_Fixup, indir_dx_reg }
354#define ALr { REP_Fixup, al_reg }
355#define eAXr { REP_Fixup, eAX_reg }
356
357#define cond_jump_flag { NULL, cond_jump_mode }
358#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 359
252b5132 360/* bits in sizeflag */
252b5132 361#define SUFFIX_ALWAYS 4
252b5132
RH		 362#define AFLAG 2
363#define DFLAG 1
364
d55ee72f
L		 365/* byte operand */
366#define b_mode 1
367/* operand size depends on prefixes */
630c2cc5 368#define v_mode (b_mode + 1)
d55ee72f
L		 369/* word operand */
370#define w_mode (v_mode + 1)
371/* double word operand */
372#define d_mode (w_mode + 1)
373/* quad word operand */
374#define q_mode (d_mode + 1)
375/* ten-byte operand */
376#define t_mode (q_mode + 1)
377/* 16-byte XMM operand */
378#define x_mode (t_mode + 1)
379/* d_mode in 32bit, q_mode in 64bit mode. */
380#define m_mode (x_mode + 1)
381#define cond_jump_mode (m_mode + 1)
382#define loop_jcxz_mode (cond_jump_mode + 1)
383/* operand size depends on REX prefixes. */
384#define dq_mode (loop_jcxz_mode + 1)
385/* registers like dq_mode, memory like w_mode. */
386#define dqw_mode (dq_mode + 1)
387/* 4- or 6-byte pointer operand */
388#define f_mode (dqw_mode + 1)
389#define const_1_mode (f_mode + 1)
390/* v_mode for stack-related opcodes. */
391#define stack_v_mode (const_1_mode + 1)
392/* non-quad operand size depends on prefixes */
393#define z_mode (stack_v_mode + 1)
394/* 16-byte operand */
395#define o_mode (z_mode + 1)
396/* registers like dq_mode, memory like b_mode. */
397#define dqb_mode (o_mode + 1)
398/* registers like dq_mode, memory like d_mode. */
399#define dqd_mode (dqb_mode + 1)
400
401#define es_reg (dqd_mode + 1)
402#define cs_reg (es_reg + 1)
403#define ss_reg (cs_reg + 1)
404#define ds_reg (ss_reg + 1)
405#define fs_reg (ds_reg + 1)
406#define gs_reg (fs_reg + 1)
407
408#define eAX_reg (gs_reg + 1)
409#define eCX_reg (eAX_reg + 1)
410#define eDX_reg (eCX_reg + 1)
411#define eBX_reg (eDX_reg + 1)
412#define eSP_reg (eBX_reg + 1)
413#define eBP_reg (eSP_reg + 1)
414#define eSI_reg (eBP_reg + 1)
415#define eDI_reg (eSI_reg + 1)
416
417#define al_reg (eDI_reg + 1)
418#define cl_reg (al_reg + 1)
419#define dl_reg (cl_reg + 1)
420#define bl_reg (dl_reg + 1)
421#define ah_reg (bl_reg + 1)
422#define ch_reg (ah_reg + 1)
423#define dh_reg (ch_reg + 1)
424#define bh_reg (dh_reg + 1)
425
426#define ax_reg (bh_reg + 1)
427#define cx_reg (ax_reg + 1)
428#define dx_reg (cx_reg + 1)
429#define bx_reg (dx_reg + 1)
430#define sp_reg (bx_reg + 1)
431#define bp_reg (sp_reg + 1)
432#define si_reg (bp_reg + 1)
433#define di_reg (si_reg + 1)
434
435#define rAX_reg (di_reg + 1)
436#define rCX_reg (rAX_reg + 1)
437#define rDX_reg (rCX_reg + 1)
438#define rBX_reg (rDX_reg + 1)
439#define rSP_reg (rBX_reg + 1)
440#define rBP_reg (rSP_reg + 1)
441#define rSI_reg (rBP_reg + 1)
442#define rDI_reg (rSI_reg + 1)
443
444#define z_mode_ax_reg (rDI_reg + 1)
445#define indir_dx_reg (z_mode_ax_reg + 1)
446
447#define MAX_BYTEMODE indir_dx_reg
448
449/* Flags that are OR'ed into the bytemode field to pass extra
450 information. */
451#define DREX_OC1 0x10000 /* OC1 bit set */
452#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
453#define DREX_MASK 0x40000 /* mask to delete */
454
455#if MAX_BYTEMODE >= DREX_OC1
456#error MAX_BYTEMODE must be less than DREX_OC1
457#endif
252b5132 458
1b0d430b
L		 459#define FLOATCODE 1
460#define USE_REG_TABLE (FLOATCODE + 1)
461#define USE_MOD_TABLE (USE_REG_TABLE + 1)
462#define USE_RM_TABLE (USE_MOD_TABLE + 1)
463#define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
464#define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
465#define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
6439fc28 466
1ceb70f8 467#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 468
4e7d34a6 469#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 470#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
471#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
472#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
473#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 474#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
475#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 476
477#define REG_80 0
478#define REG_81 (REG_80 + 1)
479#define REG_82 (REG_81 + 1)
480#define REG_8F (REG_82 + 1)
481#define REG_C0 (REG_8F + 1)
482#define REG_C1 (REG_C0 + 1)
483#define REG_C6 (REG_C1 + 1)
484#define REG_C7 (REG_C6 + 1)
485#define REG_D0 (REG_C7 + 1)
486#define REG_D1 (REG_D0 + 1)
487#define REG_D2 (REG_D1 + 1)
488#define REG_D3 (REG_D2 + 1)
489#define REG_F6 (REG_D3 + 1)
490#define REG_F7 (REG_F6 + 1)
491#define REG_FE (REG_F7 + 1)
492#define REG_FF (REG_FE + 1)
493#define REG_0F00 (REG_FF + 1)
494#define REG_0F01 (REG_0F00 + 1)
b5b1fc4f
L		 495#define REG_0F0D (REG_0F01 + 1)
496#define REG_0F18 (REG_0F0D + 1)
1ceb70f8
L		 497#define REG_0F71 (REG_0F18 + 1)
498#define REG_0F72 (REG_0F71 + 1)
499#define REG_0F73 (REG_0F72 + 1)
500#define REG_0FA6 (REG_0F73 + 1)
501#define REG_0FA7 (REG_0FA6 + 1)
502#define REG_0FAE (REG_0FA7 + 1)
503#define REG_0FBA (REG_0FAE + 1)
504#define REG_0FC7 (REG_0FBA + 1)
505
506#define MOD_8D 0
92fddf8e 507#define MOD_0F01_REG_0 (MOD_8D + 1)
1ceb70f8
L		 508#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
509#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
510#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
511#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
92fddf8e
L		 512#define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
513#define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
514#define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
515#define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
516#define MOD_0F18_REG_0 (MOD_0F17 + 1)
1ceb70f8
L		 517#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
518#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
519#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
92fddf8e
L		 520#define MOD_0F20 (MOD_0F18_REG_3 + 1)
521#define MOD_0F21 (MOD_0F20 + 1)
522#define MOD_0F22 (MOD_0F21 + 1)
523#define MOD_0F23 (MOD_0F22 + 1)
524#define MOD_0F24 (MOD_0F23 + 1)
525#define MOD_0F26 (MOD_0F24 + 1)
75c135a8
L		 526#define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
527#define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
528#define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
529#define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
530#define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
531#define MOD_0F71_REG_2 (MOD_0F51 + 1)
1ceb70f8
L		 532#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
533#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
534#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
535#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
536#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
537#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
538#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
539#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
540#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
541#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
542#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
543#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
544#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
545#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
546#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
547#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
92fddf8e
L		 548#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
549#define MOD_0FB4 (MOD_0FB2 + 1)
550#define MOD_0FB5 (MOD_0FB4 + 1)
551#define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
1ceb70f8 552#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
75c135a8
L		 553#define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
554#define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
555#define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
556#define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
557#define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
1ceb70f8
L		 558#define MOD_C4_32BIT (MOD_62_32BIT + 1)
559#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
560
561#define RM_0F01_REG_0 0
562#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
563#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
564#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
565#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
566#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
567#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
568
569#define PREFIX_90 0
570#define PREFIX_0F10 (PREFIX_90 + 1)
571#define PREFIX_0F11 (PREFIX_0F10 + 1)
572#define PREFIX_0F12 (PREFIX_0F11 + 1)
573#define PREFIX_0F16 (PREFIX_0F12 + 1)
574#define PREFIX_0F2A (PREFIX_0F16 + 1)
575#define PREFIX_0F2B (PREFIX_0F2A + 1)
576#define PREFIX_0F2C (PREFIX_0F2B + 1)
577#define PREFIX_0F2D (PREFIX_0F2C + 1)
578#define PREFIX_0F2E (PREFIX_0F2D + 1)
579#define PREFIX_0F2F (PREFIX_0F2E + 1)
580#define PREFIX_0F51 (PREFIX_0F2F + 1)
581#define PREFIX_0F52 (PREFIX_0F51 + 1)
582#define PREFIX_0F53 (PREFIX_0F52 + 1)
583#define PREFIX_0F58 (PREFIX_0F53 + 1)
584#define PREFIX_0F59 (PREFIX_0F58 + 1)
585#define PREFIX_0F5A (PREFIX_0F59 + 1)
586#define PREFIX_0F5B (PREFIX_0F5A + 1)
587#define PREFIX_0F5C (PREFIX_0F5B + 1)
588#define PREFIX_0F5D (PREFIX_0F5C + 1)
589#define PREFIX_0F5E (PREFIX_0F5D + 1)
590#define PREFIX_0F5F (PREFIX_0F5E + 1)
591#define PREFIX_0F60 (PREFIX_0F5F + 1)
592#define PREFIX_0F61 (PREFIX_0F60 + 1)
593#define PREFIX_0F62 (PREFIX_0F61 + 1)
594#define PREFIX_0F6C (PREFIX_0F62 + 1)
595#define PREFIX_0F6D (PREFIX_0F6C + 1)
596#define PREFIX_0F6F (PREFIX_0F6D + 1)
597#define PREFIX_0F70 (PREFIX_0F6F + 1)
92fddf8e
L		 598#define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
599#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
600#define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
1ceb70f8
L		 601#define PREFIX_0F79 (PREFIX_0F78 + 1)
602#define PREFIX_0F7C (PREFIX_0F79 + 1)
603#define PREFIX_0F7D (PREFIX_0F7C + 1)
604#define PREFIX_0F7E (PREFIX_0F7D + 1)
605#define PREFIX_0F7F (PREFIX_0F7E + 1)
606#define PREFIX_0FB8 (PREFIX_0F7F + 1)
607#define PREFIX_0FBD (PREFIX_0FB8 + 1)
608#define PREFIX_0FC2 (PREFIX_0FBD + 1)
4ee52178
L		 609#define PREFIX_0FC3 (PREFIX_0FC2 + 1)
610#define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
92fddf8e 611#define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
1ceb70f8
L		 612#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
613#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
614#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
615#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
616#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
617#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
618#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
619#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
620#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
621#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
622#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
623#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
624#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
625#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
626#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
627#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
628#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
629#define PREFIX_0F382A (PREFIX_0F3829 + 1)
630#define PREFIX_0F382B (PREFIX_0F382A + 1)
631#define PREFIX_0F3830 (PREFIX_0F382B + 1)
632#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
633#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
634#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
635#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
636#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
637#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
638#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
639#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
640#define PREFIX_0F383A (PREFIX_0F3839 + 1)
641#define PREFIX_0F383B (PREFIX_0F383A + 1)
642#define PREFIX_0F383C (PREFIX_0F383B + 1)
643#define PREFIX_0F383D (PREFIX_0F383C + 1)
644#define PREFIX_0F383E (PREFIX_0F383D + 1)
645#define PREFIX_0F383F (PREFIX_0F383E + 1)
646#define PREFIX_0F3840 (PREFIX_0F383F + 1)
647#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
648#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
649#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
650#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
651#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
652#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
653#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
654#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
655#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
656#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
657#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
658#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
659#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
660#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
661#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
662#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
663#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
664#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
665#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
666#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
667#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
668#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
669#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
670#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
4e7d34a6
L		 671
672#define X86_64_06 0
673#define X86_64_07 (X86_64_06 + 1)
674#define X86_64_0D (X86_64_07 + 1)
675#define X86_64_16 (X86_64_0D + 1)
676#define X86_64_17 (X86_64_16 + 1)
677#define X86_64_1E (X86_64_17 + 1)
678#define X86_64_1F (X86_64_1E + 1)
679#define X86_64_27 (X86_64_1F + 1)
680#define X86_64_2F (X86_64_27 + 1)
681#define X86_64_37 (X86_64_2F + 1)
682#define X86_64_3F (X86_64_37 + 1)
683#define X86_64_60 (X86_64_3F + 1)
684#define X86_64_61 (X86_64_60 + 1)
685#define X86_64_62 (X86_64_61 + 1)
686#define X86_64_63 (X86_64_62 + 1)
687#define X86_64_6D (X86_64_63 + 1)
688#define X86_64_6F (X86_64_6D + 1)
689#define X86_64_9A (X86_64_6F + 1)
690#define X86_64_C4 (X86_64_9A + 1)
691#define X86_64_C5 (X86_64_C4 + 1)
692#define X86_64_CE (X86_64_C5 + 1)
693#define X86_64_D4 (X86_64_CE + 1)
694#define X86_64_D5 (X86_64_D4 + 1)
695#define X86_64_EA (X86_64_D5 + 1)
696#define X86_64_0F01_REG_0 (X86_64_EA + 1)
697#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
698#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
699#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
700
701#define THREE_BYTE_0F24 0
702#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
703#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
704#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
705#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 706#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 707
26ca5450 708typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 709
710struct dis386 {
2da11e11 711 const char *name;
ce518a5f
L		 712 struct
713 {
714 op_rtn rtn;
715 int bytemode;
716 } op[MAX_OPERANDS];
252b5132
RH		 717};
718
719/* Upper case letters in the instruction names here are macros.
720 'A' => print 'b' if no register operands or suffix_always is true
721 'B' => print 'b' if suffix_always is true
9306ca4a 722 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 723 size prefix
ed7841b3 724 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 725 suffix_always is true
252b5132 726 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 727 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 728 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 729 'H' => print ",pt" or ",pn" branch hint
9306ca4a 730 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 731 for some of the macro letters)
9306ca4a 732 'J' => print 'l'
42903f7f 733 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 734 'L' => print 'l' if suffix_always is true
9d141669 735 'M' => print 'r' if intel_mnemonic is false.
252b5132 736 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 737 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 738 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 739 or suffix_always is true. print 'q' if rex prefix is present.
740 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
741 is true
a35ca55a 742 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 743 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 744 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
745 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 746 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 747 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 748 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 749 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
750 suffix_always is true.
6dd5059a 751 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 752 '!' => change condition from true to false or from false to true.
98b528ac
L		 753 '%' => add 1 upper case letter to the macro.
754
755 2 upper case letter macros:
756 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
757 or suffix_always is true
52b15da3 758
6439fc28
AM		 759 Many of the above letters print nothing in Intel mode. See "putop"
760 for the details.
52b15da3 761
6439fc28 762 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 763 mnemonic strings for AT&T and Intel. */
252b5132 764
6439fc28 765static const struct dis386 dis386[] = {
252b5132 766 /* 00 */
ce518a5f
L		 767 { "addB", { Eb, Gb } },
768 { "addS", { Ev, Gv } },
769 { "addB", { Gb, Eb } },
770 { "addS", { Gv, Ev } },
771 { "addB", { AL, Ib } },
772 { "addS", { eAX, Iv } },
4e7d34a6
L		 773 { X86_64_TABLE (X86_64_06) },
774 { X86_64_TABLE (X86_64_07) },
252b5132 775 /* 08 */
ce518a5f
L		 776 { "orB", { Eb, Gb } },
777 { "orS", { Ev, Gv } },
778 { "orB", { Gb, Eb } },
779 { "orS", { Gv, Ev } },
780 { "orB", { AL, Ib } },
781 { "orS", { eAX, Iv } },
4e7d34a6 782 { X86_64_TABLE (X86_64_0D) },
ce518a5f 783 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 784 /* 10 */
ce518a5f
L		 785 { "adcB", { Eb, Gb } },
786 { "adcS", { Ev, Gv } },
787 { "adcB", { Gb, Eb } },
788 { "adcS", { Gv, Ev } },
789 { "adcB", { AL, Ib } },
790 { "adcS", { eAX, Iv } },
4e7d34a6
L		 791 { X86_64_TABLE (X86_64_16) },
792 { X86_64_TABLE (X86_64_17) },
252b5132 793 /* 18 */
ce518a5f
L		 794 { "sbbB", { Eb, Gb } },
795 { "sbbS", { Ev, Gv } },
796 { "sbbB", { Gb, Eb } },
797 { "sbbS", { Gv, Ev } },
798 { "sbbB", { AL, Ib } },
799 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 800 { X86_64_TABLE (X86_64_1E) },
801 { X86_64_TABLE (X86_64_1F) },
252b5132 802 /* 20 */
ce518a5f
L		 803 { "andB", { Eb, Gb } },
804 { "andS", { Ev, Gv } },
805 { "andB", { Gb, Eb } },
806 { "andS", { Gv, Ev } },
807 { "andB", { AL, Ib } },
808 { "andS", { eAX, Iv } },
809 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 810 { X86_64_TABLE (X86_64_27) },
252b5132 811 /* 28 */
ce518a5f
L		 812 { "subB", { Eb, Gb } },
813 { "subS", { Ev, Gv } },
814 { "subB", { Gb, Eb } },
815 { "subS", { Gv, Ev } },
816 { "subB", { AL, Ib } },
817 { "subS", { eAX, Iv } },
818 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 819 { X86_64_TABLE (X86_64_2F) },
252b5132 820 /* 30 */
ce518a5f
L		 821 { "xorB", { Eb, Gb } },
822 { "xorS", { Ev, Gv } },
823 { "xorB", { Gb, Eb } },
824 { "xorS", { Gv, Ev } },
825 { "xorB", { AL, Ib } },
826 { "xorS", { eAX, Iv } },
827 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 828 { X86_64_TABLE (X86_64_37) },
252b5132 829 /* 38 */
ce518a5f
L		 830 { "cmpB", { Eb, Gb } },
831 { "cmpS", { Ev, Gv } },
832 { "cmpB", { Gb, Eb } },
833 { "cmpS", { Gv, Ev } },
834 { "cmpB", { AL, Ib } },
835 { "cmpS", { eAX, Iv } },
836 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 837 { X86_64_TABLE (X86_64_3F) },
252b5132 838 /* 40 */
ce518a5f
L		 839 { "inc{S|}", { RMeAX } },
840 { "inc{S|}", { RMeCX } },
841 { "inc{S|}", { RMeDX } },
842 { "inc{S|}", { RMeBX } },
843 { "inc{S|}", { RMeSP } },
844 { "inc{S|}", { RMeBP } },
845 { "inc{S|}", { RMeSI } },
846 { "inc{S|}", { RMeDI } },
252b5132 847 /* 48 */
ce518a5f
L		 848 { "dec{S|}", { RMeAX } },
849 { "dec{S|}", { RMeCX } },
850 { "dec{S|}", { RMeDX } },
851 { "dec{S|}", { RMeBX } },
852 { "dec{S|}", { RMeSP } },
853 { "dec{S|}", { RMeBP } },
854 { "dec{S|}", { RMeSI } },
855 { "dec{S|}", { RMeDI } },
252b5132 856 /* 50 */
ce518a5f
L		 857 { "pushV", { RMrAX } },
858 { "pushV", { RMrCX } },
859 { "pushV", { RMrDX } },
860 { "pushV", { RMrBX } },
861 { "pushV", { RMrSP } },
862 { "pushV", { RMrBP } },
863 { "pushV", { RMrSI } },
864 { "pushV", { RMrDI } },
252b5132 865 /* 58 */
ce518a5f
L		 866 { "popV", { RMrAX } },
867 { "popV", { RMrCX } },
868 { "popV", { RMrDX } },
869 { "popV", { RMrBX } },
870 { "popV", { RMrSP } },
871 { "popV", { RMrBP } },
872 { "popV", { RMrSI } },
873 { "popV", { RMrDI } },
252b5132 874 /* 60 */
4e7d34a6
L		 875 { X86_64_TABLE (X86_64_60) },
876 { X86_64_TABLE (X86_64_61) },
877 { X86_64_TABLE (X86_64_62) },
878 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 879 { "(bad)", { XX } }, /* seg fs */
880 { "(bad)", { XX } }, /* seg gs */
881 { "(bad)", { XX } }, /* op size prefix */
882 { "(bad)", { XX } }, /* adr size prefix */
252b5132 883 /* 68 */
ce518a5f
L		 884 { "pushT", { Iq } },
885 { "imulS", { Gv, Ev, Iv } },
886 { "pushT", { sIb } },
887 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 888 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 889 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 890 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 891 { X86_64_TABLE (X86_64_6F) },
252b5132 892 /* 70 */
ce518a5f
L		 893 { "joH", { Jb, XX, cond_jump_flag } },
894 { "jnoH", { Jb, XX, cond_jump_flag } },
895 { "jbH", { Jb, XX, cond_jump_flag } },
896 { "jaeH", { Jb, XX, cond_jump_flag } },
897 { "jeH", { Jb, XX, cond_jump_flag } },
898 { "jneH", { Jb, XX, cond_jump_flag } },
899 { "jbeH", { Jb, XX, cond_jump_flag } },
900 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 901 /* 78 */
ce518a5f
L		 902 { "jsH", { Jb, XX, cond_jump_flag } },
903 { "jnsH", { Jb, XX, cond_jump_flag } },
904 { "jpH", { Jb, XX, cond_jump_flag } },
905 { "jnpH", { Jb, XX, cond_jump_flag } },
906 { "jlH", { Jb, XX, cond_jump_flag } },
907 { "jgeH", { Jb, XX, cond_jump_flag } },
908 { "jleH", { Jb, XX, cond_jump_flag } },
909 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 910 /* 80 */
1ceb70f8
L		 911 { REG_TABLE (REG_80) },
912 { REG_TABLE (REG_81) },
ce518a5f 913 { "(bad)", { XX } },
1ceb70f8 914 { REG_TABLE (REG_82) },
ce518a5f
L		 915 { "testB", { Eb, Gb } },
916 { "testS", { Ev, Gv } },
917 { "xchgB", { Eb, Gb } },
918 { "xchgS", { Ev, Gv } },
252b5132 919 /* 88 */
ce518a5f
L		 920 { "movB", { Eb, Gb } },
921 { "movS", { Ev, Gv } },
922 { "movB", { Gb, Eb } },
923 { "movS", { Gv, Ev } },
924 { "movD", { Sv, Sw } },
1ceb70f8 925 { MOD_TABLE (MOD_8D) },
ce518a5f 926 { "movD", { Sw, Sv } },
1ceb70f8 927 { REG_TABLE (REG_8F) },
252b5132 928 /* 90 */
1ceb70f8 929 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 930 { "xchgS", { RMeCX, eAX } },
931 { "xchgS", { RMeDX, eAX } },
932 { "xchgS", { RMeBX, eAX } },
933 { "xchgS", { RMeSP, eAX } },
934 { "xchgS", { RMeBP, eAX } },
935 { "xchgS", { RMeSI, eAX } },
936 { "xchgS", { RMeDI, eAX } },
252b5132 937 /* 98 */
7c52e0e8
L		 938 { "cW{t|}R", { XX } },
939 { "cR{t|}O", { XX } },
4e7d34a6 940 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 941 { "(bad)", { XX } }, /* fwait */
942 { "pushfT", { XX } },
943 { "popfT", { XX } },
7c52e0e8
L		 944 { "sahf", { XX } },
945 { "lahf", { XX } },
252b5132 946 /* a0 */
ce518a5f
L		 947 { "movB", { AL, Ob } },
948 { "movS", { eAX, Ov } },
949 { "movB", { Ob, AL } },
950 { "movS", { Ov, eAX } },
7c52e0e8
L		 951 { "movs{b|}", { Ybr, Xb } },
952 { "movs{R|}", { Yvr, Xv } },
953 { "cmps{b|}", { Xb, Yb } },
954 { "cmps{R|}", { Xv, Yv } },
252b5132 955 /* a8 */
ce518a5f
L		 956 { "testB", { AL, Ib } },
957 { "testS", { eAX, Iv } },
958 { "stosB", { Ybr, AL } },
959 { "stosS", { Yvr, eAX } },
960 { "lodsB", { ALr, Xb } },
961 { "lodsS", { eAXr, Xv } },
962 { "scasB", { AL, Yb } },
963 { "scasS", { eAX, Yv } },
252b5132 964 /* b0 */
ce518a5f
L		 965 { "movB", { RMAL, Ib } },
966 { "movB", { RMCL, Ib } },
967 { "movB", { RMDL, Ib } },
968 { "movB", { RMBL, Ib } },
969 { "movB", { RMAH, Ib } },
970 { "movB", { RMCH, Ib } },
971 { "movB", { RMDH, Ib } },
972 { "movB", { RMBH, Ib } },
252b5132 973 /* b8 */
ce518a5f
L		 974 { "movS", { RMeAX, Iv64 } },
975 { "movS", { RMeCX, Iv64 } },
976 { "movS", { RMeDX, Iv64 } },
977 { "movS", { RMeBX, Iv64 } },
978 { "movS", { RMeSP, Iv64 } },
979 { "movS", { RMeBP, Iv64 } },
980 { "movS", { RMeSI, Iv64 } },
981 { "movS", { RMeDI, Iv64 } },
252b5132 982 /* c0 */
1ceb70f8
L		 983 { REG_TABLE (REG_C0) },
984 { REG_TABLE (REG_C1) },
ce518a5f
L		 985 { "retT", { Iw } },
986 { "retT", { XX } },
4e7d34a6
L		 987 { X86_64_TABLE (X86_64_C4) },
988 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 989 { REG_TABLE (REG_C6) },
990 { REG_TABLE (REG_C7) },
252b5132 991 /* c8 */
ce518a5f
L		 992 { "enterT", { Iw, Ib } },
993 { "leaveT", { XX } },
994 { "lretP", { Iw } },
995 { "lretP", { XX } },
996 { "int3", { XX } },
997 { "int", { Ib } },
4e7d34a6 998 { X86_64_TABLE (X86_64_CE) },
ce518a5f 999 { "iretP", { XX } },
252b5132 1000 /* d0 */
1ceb70f8
L		 1001 { REG_TABLE (REG_D0) },
1002 { REG_TABLE (REG_D1) },
1003 { REG_TABLE (REG_D2) },
1004 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1005 { X86_64_TABLE (X86_64_D4) },
1006 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1007 { "(bad)", { XX } },
1008 { "xlat", { DSBX } },
252b5132
RH		 1009 /* d8 */
1010 { FLOAT },
1011 { FLOAT },
1012 { FLOAT },
1013 { FLOAT },
1014 { FLOAT },
1015 { FLOAT },
1016 { FLOAT },
1017 { FLOAT },
1018 /* e0 */
ce518a5f
L		 1019 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1020 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1021 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1022 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1023 { "inB", { AL, Ib } },
1024 { "inG", { zAX, Ib } },
1025 { "outB", { Ib, AL } },
1026 { "outG", { Ib, zAX } },
252b5132 1027 /* e8 */
ce518a5f
L		 1028 { "callT", { Jv } },
1029 { "jmpT", { Jv } },
4e7d34a6 1030 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1031 { "jmp", { Jb } },
1032 { "inB", { AL, indirDX } },
1033 { "inG", { zAX, indirDX } },
1034 { "outB", { indirDX, AL } },
1035 { "outG", { indirDX, zAX } },
252b5132 1036 /* f0 */
ce518a5f
L		 1037 { "(bad)", { XX } }, /* lock prefix */
1038 { "icebp", { XX } },
1039 { "(bad)", { XX } }, /* repne */
1040 { "(bad)", { XX } }, /* repz */
1041 { "hlt", { XX } },
1042 { "cmc", { XX } },
1ceb70f8
L		 1043 { REG_TABLE (REG_F6) },
1044 { REG_TABLE (REG_F7) },
252b5132 1045 /* f8 */
ce518a5f
L		 1046 { "clc", { XX } },
1047 { "stc", { XX } },
1048 { "cli", { XX } },
1049 { "sti", { XX } },
1050 { "cld", { XX } },
1051 { "std", { XX } },
1ceb70f8
L		 1052 { REG_TABLE (REG_FE) },
1053 { REG_TABLE (REG_FF) },
252b5132
RH		 1054};
1055
6439fc28 1056static const struct dis386 dis386_twobyte[] = {
252b5132 1057 /* 00 */
1ceb70f8
L		 1058 { REG_TABLE (REG_0F00 ) },
1059 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1060 { "larS", { Gv, Ew } },
1061 { "lslS", { Gv, Ew } },
1062 { "(bad)", { XX } },
1063 { "syscall", { XX } },
1064 { "clts", { XX } },
1065 { "sysretP", { XX } },
252b5132 1066 /* 08 */
ce518a5f
L		 1067 { "invd", { XX } },
1068 { "wbinvd", { XX } },
1069 { "(bad)", { XX } },
1070 { "ud2a", { XX } },
1071 { "(bad)", { XX } },
b5b1fc4f 1072 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1073 { "femms", { XX } },
1074 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1075 /* 10 */
1ceb70f8
L		 1076 { PREFIX_TABLE (PREFIX_0F10) },
1077 { PREFIX_TABLE (PREFIX_0F11) },
1078 { PREFIX_TABLE (PREFIX_0F12) },
1079 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1080 { "unpcklpX", { XM, EXx } },
1081 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1082 { PREFIX_TABLE (PREFIX_0F16) },
1083 { MOD_TABLE (MOD_0F17) },
252b5132 1084 /* 18 */
1ceb70f8 1085 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1086 { "nopQ", { Ev } },
1087 { "nopQ", { Ev } },
1088 { "nopQ", { Ev } },
1089 { "nopQ", { Ev } },
1090 { "nopQ", { Ev } },
1091 { "nopQ", { Ev } },
ce518a5f 1092 { "nopQ", { Ev } },
252b5132 1093 /* 20 */
1ceb70f8
L		 1094 { MOD_TABLE (MOD_0F20) },
1095 { MOD_TABLE (MOD_0F21) },
1096 { MOD_TABLE (MOD_0F22) },
1097 { MOD_TABLE (MOD_0F23) },
1098 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1099 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1100 { MOD_TABLE (MOD_0F26) },
ce518a5f 1101 { "(bad)", { XX } },
252b5132 1102 /* 28 */
09a2c6cf 1103 { "movapX", { XM, EXx } },
d5d7db8e 1104 { "movapX", { EXx, XM } },
1ceb70f8
L		 1105 { PREFIX_TABLE (PREFIX_0F2A) },
1106 { PREFIX_TABLE (PREFIX_0F2B) },
1107 { PREFIX_TABLE (PREFIX_0F2C) },
1108 { PREFIX_TABLE (PREFIX_0F2D) },
1109 { PREFIX_TABLE (PREFIX_0F2E) },
1110 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1111 /* 30 */
ce518a5f
L		 1112 { "wrmsr", { XX } },
1113 { "rdtsc", { XX } },
1114 { "rdmsr", { XX } },
1115 { "rdpmc", { XX } },
1116 { "sysenter", { XX } },
1117 { "sysexit", { XX } },
1118 { "(bad)", { XX } },
47dd174c 1119 { "getsec", { XX } },
252b5132 1120 /* 38 */
4e7d34a6 1121 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1122 { "(bad)", { XX } },
4e7d34a6 1123 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1124 { "(bad)", { XX } },
1125 { "(bad)", { XX } },
1126 { "(bad)", { XX } },
1127 { "(bad)", { XX } },
1128 { "(bad)", { XX } },
252b5132 1129 /* 40 */
ce518a5f
L		 1130 { "cmovo", { Gv, Ev } },
1131 { "cmovno", { Gv, Ev } },
1132 { "cmovb", { Gv, Ev } },
1133 { "cmovae", { Gv, Ev } },
1134 { "cmove", { Gv, Ev } },
1135 { "cmovne", { Gv, Ev } },
1136 { "cmovbe", { Gv, Ev } },
1137 { "cmova", { Gv, Ev } },
252b5132 1138 /* 48 */
ce518a5f
L		 1139 { "cmovs", { Gv, Ev } },
1140 { "cmovns", { Gv, Ev } },
1141 { "cmovp", { Gv, Ev } },
1142 { "cmovnp", { Gv, Ev } },
1143 { "cmovl", { Gv, Ev } },
1144 { "cmovge", { Gv, Ev } },
1145 { "cmovle", { Gv, Ev } },
1146 { "cmovg", { Gv, Ev } },
252b5132 1147 /* 50 */
75c135a8 1148 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1149 { PREFIX_TABLE (PREFIX_0F51) },
1150 { PREFIX_TABLE (PREFIX_0F52) },
1151 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1152 { "andpX", { XM, EXx } },
1153 { "andnpX", { XM, EXx } },
1154 { "orpX", { XM, EXx } },
1155 { "xorpX", { XM, EXx } },
252b5132 1156 /* 58 */
1ceb70f8
L		 1157 { PREFIX_TABLE (PREFIX_0F58) },
1158 { PREFIX_TABLE (PREFIX_0F59) },
1159 { PREFIX_TABLE (PREFIX_0F5A) },
1160 { PREFIX_TABLE (PREFIX_0F5B) },
1161 { PREFIX_TABLE (PREFIX_0F5C) },
1162 { PREFIX_TABLE (PREFIX_0F5D) },
1163 { PREFIX_TABLE (PREFIX_0F5E) },
1164 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1165 /* 60 */
1ceb70f8
L		 1166 { PREFIX_TABLE (PREFIX_0F60) },
1167 { PREFIX_TABLE (PREFIX_0F61) },
1168 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1169 { "packsswb", { MX, EM } },
1170 { "pcmpgtb", { MX, EM } },
1171 { "pcmpgtw", { MX, EM } },
1172 { "pcmpgtd", { MX, EM } },
1173 { "packuswb", { MX, EM } },
252b5132 1174 /* 68 */
ce518a5f
L		 1175 { "punpckhbw", { MX, EM } },
1176 { "punpckhwd", { MX, EM } },
1177 { "punpckhdq", { MX, EM } },
1178 { "packssdw", { MX, EM } },
1ceb70f8
L		 1179 { PREFIX_TABLE (PREFIX_0F6C) },
1180 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1181 { "movK", { MX, Edq } },
1ceb70f8 1182 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1183 /* 70 */
1ceb70f8
L		 1184 { PREFIX_TABLE (PREFIX_0F70) },
1185 { REG_TABLE (REG_0F71) },
1186 { REG_TABLE (REG_0F72) },
1187 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1188 { "pcmpeqb", { MX, EM } },
1189 { "pcmpeqw", { MX, EM } },
1190 { "pcmpeqd", { MX, EM } },
1191 { "emms", { XX } },
252b5132 1192 /* 78 */
1ceb70f8
L		 1193 { PREFIX_TABLE (PREFIX_0F78) },
1194 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1195 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1196 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1197 { PREFIX_TABLE (PREFIX_0F7C) },
1198 { PREFIX_TABLE (PREFIX_0F7D) },
1199 { PREFIX_TABLE (PREFIX_0F7E) },
1200 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1201 /* 80 */
ce518a5f
L		 1202 { "joH", { Jv, XX, cond_jump_flag } },
1203 { "jnoH", { Jv, XX, cond_jump_flag } },
1204 { "jbH", { Jv, XX, cond_jump_flag } },
1205 { "jaeH", { Jv, XX, cond_jump_flag } },
1206 { "jeH", { Jv, XX, cond_jump_flag } },
1207 { "jneH", { Jv, XX, cond_jump_flag } },
1208 { "jbeH", { Jv, XX, cond_jump_flag } },
1209 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1210 /* 88 */
ce518a5f
L		 1211 { "jsH", { Jv, XX, cond_jump_flag } },
1212 { "jnsH", { Jv, XX, cond_jump_flag } },
1213 { "jpH", { Jv, XX, cond_jump_flag } },
1214 { "jnpH", { Jv, XX, cond_jump_flag } },
1215 { "jlH", { Jv, XX, cond_jump_flag } },
1216 { "jgeH", { Jv, XX, cond_jump_flag } },
1217 { "jleH", { Jv, XX, cond_jump_flag } },
1218 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1219 /* 90 */
ce518a5f
L		 1220 { "seto", { Eb } },
1221 { "setno", { Eb } },
1222 { "setb", { Eb } },
1223 { "setae", { Eb } },
1224 { "sete", { Eb } },
1225 { "setne", { Eb } },
1226 { "setbe", { Eb } },
1227 { "seta", { Eb } },
252b5132 1228 /* 98 */
ce518a5f
L		 1229 { "sets", { Eb } },
1230 { "setns", { Eb } },
1231 { "setp", { Eb } },
1232 { "setnp", { Eb } },
1233 { "setl", { Eb } },
1234 { "setge", { Eb } },
1235 { "setle", { Eb } },
1236 { "setg", { Eb } },
252b5132 1237 /* a0 */
ce518a5f
L		 1238 { "pushT", { fs } },
1239 { "popT", { fs } },
1240 { "cpuid", { XX } },
1241 { "btS", { Ev, Gv } },
1242 { "shldS", { Ev, Gv, Ib } },
1243 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1244 { REG_TABLE (REG_0FA6) },
1245 { REG_TABLE (REG_0FA7) },
252b5132 1246 /* a8 */
ce518a5f
L		 1247 { "pushT", { gs } },
1248 { "popT", { gs } },
1249 { "rsm", { XX } },
1250 { "btsS", { Ev, Gv } },
1251 { "shrdS", { Ev, Gv, Ib } },
1252 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1253 { REG_TABLE (REG_0FAE) },
ce518a5f 1254 { "imulS", { Gv, Ev } },
252b5132 1255 /* b0 */
ce518a5f
L		 1256 { "cmpxchgB", { Eb, Gb } },
1257 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1258 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1259 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1260 { MOD_TABLE (MOD_0FB4) },
1261 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1262 { "movz{bR|x}", { Gv, Eb } },
1263 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1264 /* b8 */
1ceb70f8 1265 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1266 { "ud2b", { XX } },
1ceb70f8 1267 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1268 { "btcS", { Ev, Gv } },
1269 { "bsfS", { Gv, Ev } },
1ceb70f8 1270 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1271 { "movs{bR|x}", { Gv, Eb } },
1272 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1273 /* c0 */
ce518a5f
L		 1274 { "xaddB", { Eb, Gb } },
1275 { "xaddS", { Ev, Gv } },
1ceb70f8 1276 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 1277 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 1278 { "pinsrw", { MX, Edqw, Ib } },
1279 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1280 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1281 { REG_TABLE (REG_0FC7) },
252b5132 1282 /* c8 */
ce518a5f
L		 1283 { "bswap", { RMeAX } },
1284 { "bswap", { RMeCX } },
1285 { "bswap", { RMeDX } },
1286 { "bswap", { RMeBX } },
1287 { "bswap", { RMeSP } },
1288 { "bswap", { RMeBP } },
1289 { "bswap", { RMeSI } },
1290 { "bswap", { RMeDI } },
252b5132 1291 /* d0 */
1ceb70f8 1292 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1293 { "psrlw", { MX, EM } },
1294 { "psrld", { MX, EM } },
1295 { "psrlq", { MX, EM } },
1296 { "paddq", { MX, EM } },
1297 { "pmullw", { MX, EM } },
1ceb70f8 1298 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1299 { MOD_TABLE (MOD_0FD7) },
252b5132 1300 /* d8 */
ce518a5f
L		 1301 { "psubusb", { MX, EM } },
1302 { "psubusw", { MX, EM } },
1303 { "pminub", { MX, EM } },
1304 { "pand", { MX, EM } },
1305 { "paddusb", { MX, EM } },
1306 { "paddusw", { MX, EM } },
1307 { "pmaxub", { MX, EM } },
1308 { "pandn", { MX, EM } },
252b5132 1309 /* e0 */
ce518a5f
L		 1310 { "pavgb", { MX, EM } },
1311 { "psraw", { MX, EM } },
1312 { "psrad", { MX, EM } },
1313 { "pavgw", { MX, EM } },
1314 { "pmulhuw", { MX, EM } },
1315 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1316 { PREFIX_TABLE (PREFIX_0FE6) },
1317 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1318 /* e8 */
ce518a5f
L		 1319 { "psubsb", { MX, EM } },
1320 { "psubsw", { MX, EM } },
1321 { "pminsw", { MX, EM } },
1322 { "por", { MX, EM } },
1323 { "paddsb", { MX, EM } },
1324 { "paddsw", { MX, EM } },
1325 { "pmaxsw", { MX, EM } },
1326 { "pxor", { MX, EM } },
252b5132 1327 /* f0 */
1ceb70f8 1328 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1329 { "psllw", { MX, EM } },
1330 { "pslld", { MX, EM } },
1331 { "psllq", { MX, EM } },
1332 { "pmuludq", { MX, EM } },
1333 { "pmaddwd", { MX, EM } },
1334 { "psadbw", { MX, EM } },
1ceb70f8 1335 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1336 /* f8 */
ce518a5f
L		 1337 { "psubb", { MX, EM } },
1338 { "psubw", { MX, EM } },
1339 { "psubd", { MX, EM } },
1340 { "psubq", { MX, EM } },
1341 { "paddb", { MX, EM } },
1342 { "paddw", { MX, EM } },
1343 { "paddd", { MX, EM } },
1344 { "(bad)", { XX } },
252b5132
RH		 1345};
1346
1347static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1348 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1349 /* ------------------------------- */
1350 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1351 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1352 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1353 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1354 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1355 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1356 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1357 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1358 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1359 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1360 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1361 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1362 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1363 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1364 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1365 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1366 /* ------------------------------- */
1367 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1368};
1369
1370static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1371 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1372 /* ------------------------------- */
252b5132 1373 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1374 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1375 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1376 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1377 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1378 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1379 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1380 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1381 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1382 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1383 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1384 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1385 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1386 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1387 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1388 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1389 /* ------------------------------- */
1390 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1391};
1392
252b5132
RH		 1393static char obuf[100];
1394static char *obufp;
1395static char scratchbuf[100];
1396static unsigned char *start_codep;
1397static unsigned char *insn_codep;
1398static unsigned char *codep;
b844680a
L		 1399static const char *lock_prefix;
1400static const char *data_prefix;
1401static const char *addr_prefix;
1402static const char *repz_prefix;
1403static const char *repnz_prefix;
252b5132 1404static disassemble_info *the_info;
7967e09e
L		 1405static struct
1406 {
1407 int mod;
7967e09e 1408 int reg;
484c222e 1409 int rm;
7967e09e
L		 1410 }
1411modrm;
4bba6815 1412static unsigned char need_modrm;
252b5132 1413
4bba6815
AM		 1414/* If we are accessing mod/rm/reg without need_modrm set, then the
1415 values are stale. Hitting this abort likely indicates that you
1416 need to update onebyte_has_modrm or twobyte_has_modrm. */
1417#define MODRM_CHECK if (!need_modrm) abort ()
1418
d708bcba
AM		 1419static const char **names64;
1420static const char **names32;
1421static const char **names16;
1422static const char **names8;
1423static const char **names8rex;
1424static const char **names_seg;
db51cc60
L		 1425static const char *index64;
1426static const char *index32;
d708bcba
AM		 1427static const char **index16;
1428
1429static const char *intel_names64[] = {
1430 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1431 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1432};
1433static const char *intel_names32[] = {
1434 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1435 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1436};
1437static const char *intel_names16[] = {
1438 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1439 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1440};
1441static const char *intel_names8[] = {
1442 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1443};
1444static const char *intel_names8rex[] = {
1445 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1446 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1447};
1448static const char *intel_names_seg[] = {
1449 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1450};
db51cc60
L		 1451static const char *intel_index64 = "riz";
1452static const char *intel_index32 = "eiz";
d708bcba
AM		 1453static const char *intel_index16[] = {
1454 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1455};
1456
1457static const char *att_names64[] = {
1458 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1459 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1460};
d708bcba
AM		 1461static const char *att_names32[] = {
1462 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1463 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1464};
d708bcba
AM		 1465static const char *att_names16[] = {
1466 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1467 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1468};
d708bcba
AM		 1469static const char *att_names8[] = {
1470 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1471};
d708bcba
AM		 1472static const char *att_names8rex[] = {
1473 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1474 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1475};
d708bcba
AM		 1476static const char *att_names_seg[] = {
1477 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1478};
db51cc60
L		 1479static const char *att_index64 = "%riz";
1480static const char *att_index32 = "%eiz";
d708bcba
AM		 1481static const char *att_index16[] = {
1482 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1483};
1484
1ceb70f8
L		 1485static const struct dis386 reg_table[][8] = {
1486 /* REG_80 */
252b5132 1487 {
ce518a5f
L		 1488 { "addA", { Eb, Ib } },
1489 { "orA", { Eb, Ib } },
1490 { "adcA", { Eb, Ib } },
1491 { "sbbA", { Eb, Ib } },
1492 { "andA", { Eb, Ib } },
1493 { "subA", { Eb, Ib } },
1494 { "xorA", { Eb, Ib } },
1495 { "cmpA", { Eb, Ib } },
252b5132 1496 },
1ceb70f8 1497 /* REG_81 */
252b5132 1498 {
ce518a5f
L		 1499 { "addQ", { Ev, Iv } },
1500 { "orQ", { Ev, Iv } },
1501 { "adcQ", { Ev, Iv } },
1502 { "sbbQ", { Ev, Iv } },
1503 { "andQ", { Ev, Iv } },
1504 { "subQ", { Ev, Iv } },
1505 { "xorQ", { Ev, Iv } },
1506 { "cmpQ", { Ev, Iv } },
252b5132 1507 },
1ceb70f8 1508 /* REG_82 */
252b5132 1509 {
ce518a5f
L		 1510 { "addQ", { Ev, sIb } },
1511 { "orQ", { Ev, sIb } },
1512 { "adcQ", { Ev, sIb } },
1513 { "sbbQ", { Ev, sIb } },
1514 { "andQ", { Ev, sIb } },
1515 { "subQ", { Ev, sIb } },
1516 { "xorQ", { Ev, sIb } },
1517 { "cmpQ", { Ev, sIb } },
252b5132 1518 },
1ceb70f8 1519 /* REG_8F */
4e7d34a6
L		 1520 {
1521 { "popU", { stackEv } },
1522 { "(bad)", { XX } },
1523 { "(bad)", { XX } },
1524 { "(bad)", { XX } },
1525 { "(bad)", { XX } },
1526 { "(bad)", { XX } },
1527 { "(bad)", { XX } },
1528 { "(bad)", { XX } },
1529 },
1ceb70f8 1530 /* REG_C0 */
252b5132 1531 {
ce518a5f
L		 1532 { "rolA", { Eb, Ib } },
1533 { "rorA", { Eb, Ib } },
1534 { "rclA", { Eb, Ib } },
1535 { "rcrA", { Eb, Ib } },
1536 { "shlA", { Eb, Ib } },
1537 { "shrA", { Eb, Ib } },
1538 { "(bad)", { XX } },
1539 { "sarA", { Eb, Ib } },
252b5132 1540 },
1ceb70f8 1541 /* REG_C1 */
252b5132 1542 {
ce518a5f
L		 1543 { "rolQ", { Ev, Ib } },
1544 { "rorQ", { Ev, Ib } },
1545 { "rclQ", { Ev, Ib } },
1546 { "rcrQ", { Ev, Ib } },
1547 { "shlQ", { Ev, Ib } },
1548 { "shrQ", { Ev, Ib } },
1549 { "(bad)", { XX } },
1550 { "sarQ", { Ev, Ib } },
252b5132 1551 },
1ceb70f8 1552 /* REG_C6 */
4e7d34a6
L		 1553 {
1554 { "movA", { Eb, Ib } },
1555 { "(bad)", { XX } },
1556 { "(bad)", { XX } },
1557 { "(bad)", { XX } },
1558 { "(bad)", { XX } },
1559 { "(bad)", { XX } },
1560 { "(bad)", { XX } },
1561 { "(bad)", { XX } },
1562 },
1ceb70f8 1563 /* REG_C7 */
4e7d34a6
L		 1564 {
1565 { "movQ", { Ev, Iv } },
1566 { "(bad)", { XX } },
1567 { "(bad)", { XX } },
1568 { "(bad)", { XX } },
1569 { "(bad)", { XX } },
1570 { "(bad)", { XX } },
1571 { "(bad)", { XX } },
1572 { "(bad)", { XX } },
1573 },
1ceb70f8 1574 /* REG_D0 */
252b5132 1575 {
ce518a5f
L		 1576 { "rolA", { Eb, I1 } },
1577 { "rorA", { Eb, I1 } },
1578 { "rclA", { Eb, I1 } },
1579 { "rcrA", { Eb, I1 } },
1580 { "shlA", { Eb, I1 } },
1581 { "shrA", { Eb, I1 } },
1582 { "(bad)", { XX } },
1583 { "sarA", { Eb, I1 } },
252b5132 1584 },
1ceb70f8 1585 /* REG_D1 */
252b5132 1586 {
ce518a5f
L		 1587 { "rolQ", { Ev, I1 } },
1588 { "rorQ", { Ev, I1 } },
1589 { "rclQ", { Ev, I1 } },
1590 { "rcrQ", { Ev, I1 } },
1591 { "shlQ", { Ev, I1 } },
1592 { "shrQ", { Ev, I1 } },
1593 { "(bad)", { XX } },
1594 { "sarQ", { Ev, I1 } },
252b5132 1595 },
1ceb70f8 1596 /* REG_D2 */
252b5132 1597 {
ce518a5f
L		 1598 { "rolA", { Eb, CL } },
1599 { "rorA", { Eb, CL } },
1600 { "rclA", { Eb, CL } },
1601 { "rcrA", { Eb, CL } },
1602 { "shlA", { Eb, CL } },
1603 { "shrA", { Eb, CL } },
1604 { "(bad)", { XX } },
1605 { "sarA", { Eb, CL } },
252b5132 1606 },
1ceb70f8 1607 /* REG_D3 */
252b5132 1608 {
ce518a5f
L		 1609 { "rolQ", { Ev, CL } },
1610 { "rorQ", { Ev, CL } },
1611 { "rclQ", { Ev, CL } },
1612 { "rcrQ", { Ev, CL } },
1613 { "shlQ", { Ev, CL } },
1614 { "shrQ", { Ev, CL } },
1615 { "(bad)", { XX } },
1616 { "sarQ", { Ev, CL } },
252b5132 1617 },
1ceb70f8 1618 /* REG_F6 */
252b5132 1619 {
ce518a5f 1620 { "testA", { Eb, Ib } },
058f233b 1621 { "(bad)", { XX } },
ce518a5f
L		 1622 { "notA", { Eb } },
1623 { "negA", { Eb } },
1624 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1625 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1626 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1627 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1628 },
1ceb70f8 1629 /* REG_F7 */
252b5132 1630 {
ce518a5f
L		 1631 { "testQ", { Ev, Iv } },
1632 { "(bad)", { XX } },
1633 { "notQ", { Ev } },
1634 { "negQ", { Ev } },
1635 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1636 { "imulQ", { Ev } },
1637 { "divQ", { Ev } },
1638 { "idivQ", { Ev } },
252b5132 1639 },
1ceb70f8 1640 /* REG_FE */
252b5132 1641 {
ce518a5f
L		 1642 { "incA", { Eb } },
1643 { "decA", { Eb } },
1644 { "(bad)", { XX } },
1645 { "(bad)", { XX } },
1646 { "(bad)", { XX } },
1647 { "(bad)", { XX } },
1648 { "(bad)", { XX } },
1649 { "(bad)", { XX } },
252b5132 1650 },
1ceb70f8 1651 /* REG_FF */
252b5132 1652 {
ce518a5f
L		 1653 { "incQ", { Ev } },
1654 { "decQ", { Ev } },
1655 { "callT", { indirEv } },
1656 { "JcallT", { indirEp } },
1657 { "jmpT", { indirEv } },
1658 { "JjmpT", { indirEp } },
1659 { "pushU", { stackEv } },
1660 { "(bad)", { XX } },
252b5132 1661 },
1ceb70f8 1662 /* REG_0F00 */
252b5132 1663 {
ce518a5f
L		 1664 { "sldtD", { Sv } },
1665 { "strD", { Sv } },
1666 { "lldt", { Ew } },
1667 { "ltr", { Ew } },
1668 { "verr", { Ew } },
1669 { "verw", { Ew } },
1670 { "(bad)", { XX } },
1671 { "(bad)", { XX } },
252b5132 1672 },
1ceb70f8 1673 /* REG_0F01 */
252b5132 1674 {
1ceb70f8
L		 1675 { MOD_TABLE (MOD_0F01_REG_0) },
1676 { MOD_TABLE (MOD_0F01_REG_1) },
1677 { MOD_TABLE (MOD_0F01_REG_2) },
1678 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1679 { "smswD", { Sv } },
1680 { "(bad)", { XX } },
1681 { "lmsw", { Ew } },
1ceb70f8 1682 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1683 },
b5b1fc4f 1684 /* REG_0F0D */
252b5132 1685 {
4e7d34a6
L		 1686 { "prefetch", { Eb } },
1687 { "prefetchw", { Eb } },
1688 { "(bad)", { XX } },
1689 { "(bad)", { XX } },
1690 { "(bad)", { XX } },
1691 { "(bad)", { XX } },
1692 { "(bad)", { XX } },
1693 { "(bad)", { XX } },
252b5132 1694 },
1ceb70f8 1695 /* REG_0F18 */
252b5132 1696 {
1ceb70f8
L		 1697 { MOD_TABLE (MOD_0F18_REG_0) },
1698 { MOD_TABLE (MOD_0F18_REG_1) },
1699 { MOD_TABLE (MOD_0F18_REG_2) },
1700 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1701 { "(bad)", { XX } },
1702 { "(bad)", { XX } },
1703 { "(bad)", { XX } },
1704 { "(bad)", { XX } },
252b5132 1705 },
1ceb70f8 1706 /* REG_0F71 */
a6bd098c 1707 {
ce518a5f
L		 1708 { "(bad)", { XX } },
1709 { "(bad)", { XX } },
1ceb70f8 1710 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1711 { "(bad)", { XX } },
1ceb70f8 1712 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1713 { "(bad)", { XX } },
1ceb70f8 1714 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1715 { "(bad)", { XX } },
a6bd098c 1716 },
1ceb70f8 1717 /* REG_0F72 */
a6bd098c 1718 {
ce518a5f
L		 1719 { "(bad)", { XX } },
1720 { "(bad)", { XX } },
1ceb70f8 1721 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1722 { "(bad)", { XX } },
1ceb70f8 1723 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1724 { "(bad)", { XX } },
1ceb70f8 1725 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1726 { "(bad)", { XX } },
a6bd098c 1727 },
1ceb70f8 1728 /* REG_0F73 */
252b5132 1729 {
ce518a5f
L		 1730 { "(bad)", { XX } },
1731 { "(bad)", { XX } },
1ceb70f8
L		 1732 { MOD_TABLE (MOD_0F73_REG_2) },
1733 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1734 { "(bad)", { XX } },
ce518a5f 1735 { "(bad)", { XX } },
1ceb70f8
L		 1736 { MOD_TABLE (MOD_0F73_REG_6) },
1737 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1738 },
1ceb70f8 1739 /* REG_0FA6 */
252b5132 1740 {
4e7d34a6
L		 1741 { "montmul", { { OP_0f07, 0 } } },
1742 { "xsha1", { { OP_0f07, 0 } } },
1743 { "xsha256", { { OP_0f07, 0 } } },
1744 { "(bad)", { { OP_0f07, 0 } } },
1745 { "(bad)", { { OP_0f07, 0 } } },
1746 { "(bad)", { { OP_0f07, 0 } } },
1747 { "(bad)", { { OP_0f07, 0 } } },
1748 { "(bad)", { { OP_0f07, 0 } } },
1749 },
1ceb70f8 1750 /* REG_0FA7 */
4e7d34a6
L		 1751 {
1752 { "xstore-rng", { { OP_0f07, 0 } } },
1753 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1754 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1755 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1756 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1757 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1758 { "(bad)", { { OP_0f07, 0 } } },
1759 { "(bad)", { { OP_0f07, 0 } } },
1760 },
1ceb70f8 1761 /* REG_0FAE */
4e7d34a6 1762 {
1ceb70f8
L		 1763 { MOD_TABLE (MOD_0FAE_REG_0) },
1764 { MOD_TABLE (MOD_0FAE_REG_1) },
1765 { MOD_TABLE (MOD_0FAE_REG_2) },
1766 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1767 { "(bad)", { XX } },
1ceb70f8
L		 1768 { MOD_TABLE (MOD_0FAE_REG_5) },
1769 { MOD_TABLE (MOD_0FAE_REG_6) },
1770 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1771 },
1ceb70f8 1772 /* REG_0FBA */
252b5132 1773 {
ce518a5f
L		 1774 { "(bad)", { XX } },
1775 { "(bad)", { XX } },
d8faab4e
L		 1776 { "(bad)", { XX } },
1777 { "(bad)", { XX } },
4e7d34a6
L		 1778 { "btQ", { Ev, Ib } },
1779 { "btsQ", { Ev, Ib } },
1780 { "btrQ", { Ev, Ib } },
1781 { "btcQ", { Ev, Ib } },
c608c12e 1782 },
1ceb70f8 1783 /* REG_0FC7 */
c608c12e 1784 {
b844680a 1785 { "(bad)", { XX } },
4e7d34a6 1786 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1787 { "(bad)", { XX } },
b844680a
L		 1788 { "(bad)", { XX } },
1789 { "(bad)", { XX } },
1790 { "(bad)", { XX } },
1ceb70f8
L		 1791 { MOD_TABLE (MOD_0FC7_REG_6) },
1792 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1793 },
4e7d34a6
L		 1794};
1795
1ceb70f8
L		 1796static const struct dis386 prefix_table[][4] = {
1797 /* PREFIX_90 */
252b5132 1798 {
4e7d34a6
L		 1799 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1800 { "pause", { XX } },
1801 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1802 { "(bad)", { XX } },
0f10071e 1803 },
4e7d34a6 1804
1ceb70f8 1805 /* PREFIX_0F10 */
cc0ec051 1806 {
4e7d34a6
L		 1807 { "movups", { XM, EXx } },
1808 { "movss", { XM, EXd } },
1809 { "movupd", { XM, EXx } },
1810 { "movsd", { XM, EXq } },
30d1c836 1811 },
4e7d34a6 1812
1ceb70f8 1813 /* PREFIX_0F11 */
30d1c836 1814 {
d5d7db8e
L		 1815 { "movups", { EXx, XM } },
1816 { "movss", { EXd, XM } },
1817 { "movupd", { EXx, XM } },
1818 { "movsd", { EXq, XM } },
4e7d34a6 1819 },
252b5132 1820
1ceb70f8 1821 /* PREFIX_0F12 */
c608c12e 1822 {
1ceb70f8 1823 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1824 { "movsldup", { XM, EXx } },
1825 { "movlpd", { XM, EXq } },
1826 { "movddup", { XM, EXq } },
c608c12e 1827 },
4e7d34a6 1828
1ceb70f8 1829 /* PREFIX_0F16 */
c608c12e 1830 {
1ceb70f8 1831 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1832 { "movshdup", { XM, EXx } },
1833 { "movhpd", { XM, EXq } },
058f233b 1834 { "(bad)", { XX } },
c608c12e 1835 },
4e7d34a6 1836
1ceb70f8 1837 /* PREFIX_0F2A */
c608c12e 1838 {
09335d05 1839 { "cvtpi2ps", { XM, EMCq } },
98b528ac 1840 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 1841 { "cvtpi2pd", { XM, EMCq } },
98b528ac 1842 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 1843 },
4e7d34a6 1844
1ceb70f8 1845 /* PREFIX_0F2B */
c608c12e 1846 {
75c135a8
L		 1847 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
1848 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
1849 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
1850 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 1851 },
4e7d34a6 1852
1ceb70f8 1853 /* PREFIX_0F2C */
c608c12e 1854 {
09335d05
L		 1855 { "cvttps2pi", { MXC, EXq } },
1856 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1857 { "cvttpd2pi", { MXC, EXx } },
09335d05 1858 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1859 },
4e7d34a6 1860
1ceb70f8 1861 /* PREFIX_0F2D */
c608c12e 1862 {
4e7d34a6
L		 1863 { "cvtps2pi", { MXC, EXq } },
1864 { "cvtss2siY", { Gv, EXd } },
1865 { "cvtpd2pi", { MXC, EXx } },
1866 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1867 },
4e7d34a6 1868
1ceb70f8 1869 /* PREFIX_0F2E */
c608c12e 1870 {
4e7d34a6
L		 1871 { "ucomiss",{ XM, EXd } },
1872 { "(bad)", { XX } },
1873 { "ucomisd",{ XM, EXq } },
1874 { "(bad)", { XX } },
c608c12e 1875 },
4e7d34a6 1876
1ceb70f8 1877 /* PREFIX_0F2F */
c608c12e 1878 {
4e7d34a6
L		 1879 { "comiss", { XM, EXd } },
1880 { "(bad)", { XX } },
1881 { "comisd", { XM, EXq } },
1882 { "(bad)", { XX } },
c608c12e 1883 },
4e7d34a6 1884
1ceb70f8 1885 /* PREFIX_0F51 */
c608c12e 1886 {
4e7d34a6
L		 1887 { "sqrtps", { XM, EXx } },
1888 { "sqrtss", { XM, EXd } },
1889 { "sqrtpd", { XM, EXx } },
1890 { "sqrtsd", { XM, EXq } },
c608c12e 1891 },
4e7d34a6 1892
1ceb70f8 1893 /* PREFIX_0F52 */
c608c12e 1894 {
4e7d34a6
L		 1895 { "rsqrtps",{ XM, EXx } },
1896 { "rsqrtss",{ XM, EXd } },
058f233b
L		 1897 { "(bad)", { XX } },
1898 { "(bad)", { XX } },
c608c12e 1899 },
4e7d34a6 1900
1ceb70f8 1901 /* PREFIX_0F53 */
c608c12e 1902 {
4e7d34a6
L		 1903 { "rcpps", { XM, EXx } },
1904 { "rcpss", { XM, EXd } },
058f233b
L		 1905 { "(bad)", { XX } },
1906 { "(bad)", { XX } },
c608c12e 1907 },
4e7d34a6 1908
1ceb70f8 1909 /* PREFIX_0F58 */
c608c12e 1910 {
4e7d34a6
L		 1911 { "addps", { XM, EXx } },
1912 { "addss", { XM, EXd } },
1913 { "addpd", { XM, EXx } },
1914 { "addsd", { XM, EXq } },
c608c12e 1915 },
4e7d34a6 1916
1ceb70f8 1917 /* PREFIX_0F59 */
c608c12e 1918 {
4e7d34a6
L		 1919 { "mulps", { XM, EXx } },
1920 { "mulss", { XM, EXd } },
1921 { "mulpd", { XM, EXx } },
1922 { "mulsd", { XM, EXq } },
041bd2e0 1923 },
4e7d34a6 1924
1ceb70f8 1925 /* PREFIX_0F5A */
041bd2e0 1926 {
4e7d34a6
L		 1927 { "cvtps2pd", { XM, EXq } },
1928 { "cvtss2sd", { XM, EXd } },
1929 { "cvtpd2ps", { XM, EXx } },
1930 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1931 },
4e7d34a6 1932
1ceb70f8 1933 /* PREFIX_0F5B */
041bd2e0 1934 {
09a2c6cf
L		 1935 { "cvtdq2ps", { XM, EXx } },
1936 { "cvttps2dq", { XM, EXx } },
1937 { "cvtps2dq", { XM, EXx } },
058f233b 1938 { "(bad)", { XX } },
041bd2e0 1939 },
4e7d34a6 1940
1ceb70f8 1941 /* PREFIX_0F5C */
041bd2e0 1942 {
4e7d34a6
L		 1943 { "subps", { XM, EXx } },
1944 { "subss", { XM, EXd } },
1945 { "subpd", { XM, EXx } },
1946 { "subsd", { XM, EXq } },
041bd2e0 1947 },
4e7d34a6 1948
1ceb70f8 1949 /* PREFIX_0F5D */
041bd2e0 1950 {
4e7d34a6
L		 1951 { "minps", { XM, EXx } },
1952 { "minss", { XM, EXd } },
1953 { "minpd", { XM, EXx } },
1954 { "minsd", { XM, EXq } },
041bd2e0 1955 },
4e7d34a6 1956
1ceb70f8 1957 /* PREFIX_0F5E */
041bd2e0 1958 {
4e7d34a6
L		 1959 { "divps", { XM, EXx } },
1960 { "divss", { XM, EXd } },
1961 { "divpd", { XM, EXx } },
1962 { "divsd", { XM, EXq } },
041bd2e0 1963 },
4e7d34a6 1964
1ceb70f8 1965 /* PREFIX_0F5F */
041bd2e0 1966 {
4e7d34a6
L		 1967 { "maxps", { XM, EXx } },
1968 { "maxss", { XM, EXd } },
1969 { "maxpd", { XM, EXx } },
1970 { "maxsd", { XM, EXq } },
041bd2e0 1971 },
4e7d34a6 1972
1ceb70f8 1973 /* PREFIX_0F60 */
041bd2e0 1974 {
4e7d34a6
L		 1975 { "punpcklbw",{ MX, EMd } },
1976 { "(bad)", { XX } },
1977 { "punpcklbw",{ MX, EMx } },
1978 { "(bad)", { XX } },
041bd2e0 1979 },
4e7d34a6 1980
1ceb70f8 1981 /* PREFIX_0F61 */
041bd2e0 1982 {
4e7d34a6
L		 1983 { "punpcklwd",{ MX, EMd } },
1984 { "(bad)", { XX } },
1985 { "punpcklwd",{ MX, EMx } },
1986 { "(bad)", { XX } },
041bd2e0 1987 },
4e7d34a6 1988
1ceb70f8 1989 /* PREFIX_0F62 */
041bd2e0 1990 {
4e7d34a6
L		 1991 { "punpckldq",{ MX, EMd } },
1992 { "(bad)", { XX } },
1993 { "punpckldq",{ MX, EMx } },
1994 { "(bad)", { XX } },
041bd2e0 1995 },
4e7d34a6 1996
1ceb70f8 1997 /* PREFIX_0F6C */
041bd2e0 1998 {
058f233b
L		 1999 { "(bad)", { XX } },
2000 { "(bad)", { XX } },
4e7d34a6 2001 { "punpcklqdq", { XM, EXx } },
058f233b 2002 { "(bad)", { XX } },
0f17484f 2003 },
4e7d34a6 2004
1ceb70f8 2005 /* PREFIX_0F6D */
0f17484f 2006 {
058f233b
L		 2007 { "(bad)", { XX } },
2008 { "(bad)", { XX } },
4e7d34a6 2009 { "punpckhqdq", { XM, EXx } },
058f233b 2010 { "(bad)", { XX } },
041bd2e0 2011 },
4e7d34a6 2012
1ceb70f8 2013 /* PREFIX_0F6F */
ca164297 2014 {
4e7d34a6
L		 2015 { "movq", { MX, EM } },
2016 { "movdqu", { XM, EXx } },
2017 { "movdqa", { XM, EXx } },
058f233b 2018 { "(bad)", { XX } },
ca164297 2019 },
4e7d34a6 2020
1ceb70f8 2021 /* PREFIX_0F70 */
4e7d34a6
L		 2022 {
2023 { "pshufw", { MX, EM, Ib } },
2024 { "pshufhw",{ XM, EXx, Ib } },
2025 { "pshufd", { XM, EXx, Ib } },
2026 { "pshuflw",{ XM, EXx, Ib } },
2027 },
2028
92fddf8e
L		 2029 /* PREFIX_0F73_REG_3 */
2030 {
2031 { "(bad)", { XX } },
2032 { "(bad)", { XX } },
2033 { "psrldq", { XS, Ib } },
2034 { "(bad)", { XX } },
2035 },
2036
2037 /* PREFIX_0F73_REG_7 */
2038 {
2039 { "(bad)", { XX } },
2040 { "(bad)", { XX } },
2041 { "pslldq", { XS, Ib } },
2042 { "(bad)", { XX } },
2043 },
2044
1ceb70f8 2045 /* PREFIX_0F78 */
4e7d34a6
L		 2046 {
2047 {"vmread", { Em, Gm } },
2048 {"(bad)", { XX } },
2049 {"extrq", { XS, Ib, Ib } },
2050 {"insertq", { XM, XS, Ib, Ib } },
2051 },
2052
1ceb70f8 2053 /* PREFIX_0F79 */
4e7d34a6
L		 2054 {
2055 {"vmwrite", { Gm, Em } },
2056 {"(bad)", { XX } },
2057 {"extrq", { XM, XS } },
2058 {"insertq", { XM, XS } },
2059 },
2060
1ceb70f8 2061 /* PREFIX_0F7C */
ca164297 2062 {
058f233b
L		 2063 { "(bad)", { XX } },
2064 { "(bad)", { XX } },
09a2c6cf
L		 2065 { "haddpd", { XM, EXx } },
2066 { "haddps", { XM, EXx } },
ca164297 2067 },
4e7d34a6 2068
1ceb70f8 2069 /* PREFIX_0F7D */
ca164297 2070 {
058f233b
L		 2071 { "(bad)", { XX } },
2072 { "(bad)", { XX } },
09a2c6cf
L		 2073 { "hsubpd", { XM, EXx } },
2074 { "hsubps", { XM, EXx } },
ca164297 2075 },
4e7d34a6 2076
1ceb70f8 2077 /* PREFIX_0F7E */
ca164297 2078 {
4e7d34a6
L		 2079 { "movK", { Edq, MX } },
2080 { "movq", { XM, EXq } },
2081 { "movK", { Edq, XM } },
058f233b 2082 { "(bad)", { XX } },
ca164297 2083 },
4e7d34a6 2084
1ceb70f8 2085 /* PREFIX_0F7F */
ca164297 2086 {
4e7d34a6 2087 { "movq", { EM, MX } },
d5d7db8e
L		 2088 { "movdqu", { EXx, XM } },
2089 { "movdqa", { EXx, XM } },
058f233b 2090 { "(bad)", { XX } },
ca164297 2091 },
4e7d34a6 2092
1ceb70f8 2093 /* PREFIX_0FB8 */
ca164297 2094 {
4e7d34a6
L		 2095 { "(bad)", { XX } },
2096 { "popcntS", { Gv, Ev } },
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
ca164297 2099 },
4e7d34a6 2100
1ceb70f8 2101 /* PREFIX_0FBD */
050dfa73 2102 {
4e7d34a6
L		 2103 { "bsrS", { Gv, Ev } },
2104 { "lzcntS", { Gv, Ev } },
2105 { "bsrS", { Gv, Ev } },
2106 { "(bad)", { XX } },
050dfa73
MM		 2107 },
2108
1ceb70f8 2109 /* PREFIX_0FC2 */
050dfa73 2110 {
ad19981d
L		 2111 { "cmpps", { XM, EXx, CMP } },
2112 { "cmpss", { XM, EXd, CMP } },
2113 { "cmppd", { XM, EXx, CMP } },
2114 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2115 },
246c51aa 2116
4ee52178
L		 2117 /* PREFIX_0FC3 */
2118 {
2119 { "movntiS", { Ma, Gv } },
2120 { "(bad)", { XX } },
2121 { "(bad)", { XX } },
2122 { "(bad)", { XX } },
2123 },
2124
92fddf8e
L		 2125 /* PREFIX_0FC7_REG_6 */
2126 {
2127 { "vmptrld",{ Mq } },
2128 { "vmxon", { Mq } },
2129 { "vmclear",{ Mq } },
2130 { "(bad)", { XX } },
2131 },
2132
1ceb70f8 2133 /* PREFIX_0FD0 */
050dfa73 2134 {
058f233b
L		 2135 { "(bad)", { XX } },
2136 { "(bad)", { XX } },
4e7d34a6
L		 2137 { "addsubpd", { XM, EXx } },
2138 { "addsubps", { XM, EXx } },
246c51aa 2139 },
050dfa73 2140
1ceb70f8 2141 /* PREFIX_0FD6 */
050dfa73 2142 {
058f233b 2143 { "(bad)", { XX } },
4e7d34a6
L		 2144 { "movq2dq",{ XM, MS } },
2145 { "movq", { EXq, XM } },
2146 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2147 },
2148
1ceb70f8 2149 /* PREFIX_0FE6 */
7918206c 2150 {
058f233b 2151 { "(bad)", { XX } },
4e7d34a6
L		 2152 { "cvtdq2pd", { XM, EXq } },
2153 { "cvttpd2dq", { XM, EXx } },
2154 { "cvtpd2dq", { XM, EXx } },
7918206c 2155 },
8b38ad71 2156
1ceb70f8 2157 /* PREFIX_0FE7 */
8b38ad71 2158 {
4ee52178 2159 { "movntq", { Mq, MX } },
058f233b 2160 { "(bad)", { XX } },
75c135a8 2161 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2162 { "(bad)", { XX } },
4e7d34a6
L		 2163 },
2164
1ceb70f8 2165 /* PREFIX_0FF0 */
4e7d34a6 2166 {
058f233b
L		 2167 { "(bad)", { XX } },
2168 { "(bad)", { XX } },
2169 { "(bad)", { XX } },
1ceb70f8 2170 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2171 },
2172
1ceb70f8 2173 /* PREFIX_0FF7 */
4e7d34a6
L		 2174 {
2175 { "maskmovq", { MX, MS } },
058f233b 2176 { "(bad)", { XX } },
4e7d34a6 2177 { "maskmovdqu", { XM, XS } },
058f233b 2178 { "(bad)", { XX } },
8b38ad71 2179 },
42903f7f 2180
1ceb70f8 2181 /* PREFIX_0F3810 */
42903f7f
L		 2182 {
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
88a94849 2185 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2186 { "(bad)", { XX } },
2187 },
2188
1ceb70f8 2189 /* PREFIX_0F3814 */
42903f7f
L		 2190 {
2191 { "(bad)", { XX } },
2192 { "(bad)", { XX } },
88a94849 2193 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2194 { "(bad)", { XX } },
2195 },
2196
1ceb70f8 2197 /* PREFIX_0F3815 */
42903f7f
L		 2198 {
2199 { "(bad)", { XX } },
2200 { "(bad)", { XX } },
09a2c6cf 2201 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2202 { "(bad)", { XX } },
2203 },
2204
1ceb70f8 2205 /* PREFIX_0F3817 */
42903f7f
L		 2206 {
2207 { "(bad)", { XX } },
2208 { "(bad)", { XX } },
09a2c6cf 2209 { "ptest", { XM, EXx } },
42903f7f
L		 2210 { "(bad)", { XX } },
2211 },
2212
1ceb70f8 2213 /* PREFIX_0F3820 */
42903f7f
L		 2214 {
2215 { "(bad)", { XX } },
2216 { "(bad)", { XX } },
8976381e 2217 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2218 { "(bad)", { XX } },
2219 },
2220
1ceb70f8 2221 /* PREFIX_0F3821 */
42903f7f
L		 2222 {
2223 { "(bad)", { XX } },
2224 { "(bad)", { XX } },
8976381e 2225 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2226 { "(bad)", { XX } },
2227 },
2228
1ceb70f8 2229 /* PREFIX_0F3822 */
42903f7f
L		 2230 {
2231 { "(bad)", { XX } },
2232 { "(bad)", { XX } },
8976381e 2233 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2234 { "(bad)", { XX } },
2235 },
2236
1ceb70f8 2237 /* PREFIX_0F3823 */
42903f7f
L		 2238 {
2239 { "(bad)", { XX } },
2240 { "(bad)", { XX } },
8976381e 2241 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2242 { "(bad)", { XX } },
2243 },
2244
1ceb70f8 2245 /* PREFIX_0F3824 */
42903f7f
L		 2246 {
2247 { "(bad)", { XX } },
2248 { "(bad)", { XX } },
8976381e 2249 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2250 { "(bad)", { XX } },
2251 },
2252
1ceb70f8 2253 /* PREFIX_0F3825 */
42903f7f
L		 2254 {
2255 { "(bad)", { XX } },
2256 { "(bad)", { XX } },
8976381e 2257 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2258 { "(bad)", { XX } },
2259 },
2260
1ceb70f8 2261 /* PREFIX_0F3828 */
42903f7f
L		 2262 {
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
09a2c6cf 2265 { "pmuldq", { XM, EXx } },
42903f7f
L		 2266 { "(bad)", { XX } },
2267 },
2268
1ceb70f8 2269 /* PREFIX_0F3829 */
42903f7f
L		 2270 {
2271 { "(bad)", { XX } },
2272 { "(bad)", { XX } },
09a2c6cf 2273 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2274 { "(bad)", { XX } },
2275 },
2276
1ceb70f8 2277 /* PREFIX_0F382A */
42903f7f
L		 2278 {
2279 { "(bad)", { XX } },
2280 { "(bad)", { XX } },
75c135a8 2281 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2282 { "(bad)", { XX } },
2283 },
2284
1ceb70f8 2285 /* PREFIX_0F382B */
42903f7f
L		 2286 {
2287 { "(bad)", { XX } },
2288 { "(bad)", { XX } },
09a2c6cf 2289 { "packusdw", { XM, EXx } },
42903f7f
L		 2290 { "(bad)", { XX } },
2291 },
2292
1ceb70f8 2293 /* PREFIX_0F3830 */
42903f7f
L		 2294 {
2295 { "(bad)", { XX } },
2296 { "(bad)", { XX } },
8976381e 2297 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2298 { "(bad)", { XX } },
2299 },
2300
1ceb70f8 2301 /* PREFIX_0F3831 */
42903f7f
L		 2302 {
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
8976381e 2305 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2306 { "(bad)", { XX } },
2307 },
2308
1ceb70f8 2309 /* PREFIX_0F3832 */
42903f7f
L		 2310 {
2311 { "(bad)", { XX } },
2312 { "(bad)", { XX } },
8976381e 2313 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2314 { "(bad)", { XX } },
2315 },
2316
1ceb70f8 2317 /* PREFIX_0F3833 */
42903f7f
L		 2318 {
2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
8976381e 2321 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2322 { "(bad)", { XX } },
2323 },
2324
1ceb70f8 2325 /* PREFIX_0F3834 */
42903f7f
L		 2326 {
2327 { "(bad)", { XX } },
2328 { "(bad)", { XX } },
8976381e 2329 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2330 { "(bad)", { XX } },
2331 },
2332
1ceb70f8 2333 /* PREFIX_0F3835 */
42903f7f
L		 2334 {
2335 { "(bad)", { XX } },
2336 { "(bad)", { XX } },
8976381e 2337 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2338 { "(bad)", { XX } },
2339 },
2340
1ceb70f8 2341 /* PREFIX_0F3837 */
4e7d34a6
L		 2342 {
2343 { "(bad)", { XX } },
2344 { "(bad)", { XX } },
2345 { "pcmpgtq", { XM, EXx } },
2346 { "(bad)", { XX } },
2347 },
2348
1ceb70f8 2349 /* PREFIX_0F3838 */
42903f7f
L		 2350 {
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
09a2c6cf 2353 { "pminsb", { XM, EXx } },
42903f7f
L		 2354 { "(bad)", { XX } },
2355 },
2356
1ceb70f8 2357 /* PREFIX_0F3839 */
42903f7f
L		 2358 {
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
09a2c6cf 2361 { "pminsd", { XM, EXx } },
42903f7f
L		 2362 { "(bad)", { XX } },
2363 },
2364
1ceb70f8 2365 /* PREFIX_0F383A */
42903f7f
L		 2366 {
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
09a2c6cf 2369 { "pminuw", { XM, EXx } },
42903f7f
L		 2370 { "(bad)", { XX } },
2371 },
2372
1ceb70f8 2373 /* PREFIX_0F383B */
42903f7f
L		 2374 {
2375 { "(bad)", { XX } },
2376 { "(bad)", { XX } },
09a2c6cf 2377 { "pminud", { XM, EXx } },
42903f7f
L		 2378 { "(bad)", { XX } },
2379 },
2380
1ceb70f8 2381 /* PREFIX_0F383C */
42903f7f
L		 2382 {
2383 { "(bad)", { XX } },
2384 { "(bad)", { XX } },
09a2c6cf 2385 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2386 { "(bad)", { XX } },
2387 },
2388
1ceb70f8 2389 /* PREFIX_0F383D */
42903f7f
L		 2390 {
2391 { "(bad)", { XX } },
2392 { "(bad)", { XX } },
09a2c6cf 2393 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2394 { "(bad)", { XX } },
2395 },
2396
1ceb70f8 2397 /* PREFIX_0F383E */
42903f7f
L		 2398 {
2399 { "(bad)", { XX } },
2400 { "(bad)", { XX } },
09a2c6cf 2401 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2402 { "(bad)", { XX } },
2403 },
2404
1ceb70f8 2405 /* PREFIX_0F383F */
42903f7f
L		 2406 {
2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
09a2c6cf 2409 { "pmaxud", { XM, EXx } },
42903f7f
L		 2410 { "(bad)", { XX } },
2411 },
2412
1ceb70f8 2413 /* PREFIX_0F3840 */
42903f7f
L		 2414 {
2415 { "(bad)", { XX } },
2416 { "(bad)", { XX } },
09a2c6cf 2417 { "pmulld", { XM, EXx } },
42903f7f
L		 2418 { "(bad)", { XX } },
2419 },
2420
1ceb70f8 2421 /* PREFIX_0F3841 */
42903f7f
L		 2422 {
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
09a2c6cf 2425 { "phminposuw", { XM, EXx } },
42903f7f
L		 2426 { "(bad)", { XX } },
2427 },
2428
1ceb70f8 2429 /* PREFIX_0F38F0 */
4e7d34a6
L		 2430 {
2431 { "(bad)", { XX } },
2432 { "(bad)", { XX } },
2433 { "(bad)", { XX } },
2434 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2435 },
2436
1ceb70f8 2437 /* PREFIX_0F38F1 */
4e7d34a6
L		 2438 {
2439 { "(bad)", { XX } },
2440 { "(bad)", { XX } },
2441 { "(bad)", { XX } },
2442 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2443 },
2444
1ceb70f8 2445 /* PREFIX_0F3A08 */
42903f7f
L		 2446 {
2447 { "(bad)", { XX } },
2448 { "(bad)", { XX } },
09a2c6cf 2449 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2450 { "(bad)", { XX } },
2451 },
2452
1ceb70f8 2453 /* PREFIX_0F3A09 */
42903f7f
L		 2454 {
2455 { "(bad)", { XX } },
2456 { "(bad)", { XX } },
09a2c6cf 2457 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2458 { "(bad)", { XX } },
2459 },
2460
1ceb70f8 2461 /* PREFIX_0F3A0A */
42903f7f
L		 2462 {
2463 { "(bad)", { XX } },
2464 { "(bad)", { XX } },
09335d05 2465 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2466 { "(bad)", { XX } },
2467 },
2468
1ceb70f8 2469 /* PREFIX_0F3A0B */
42903f7f
L		 2470 {
2471 { "(bad)", { XX } },
2472 { "(bad)", { XX } },
09335d05 2473 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2474 { "(bad)", { XX } },
2475 },
2476
1ceb70f8 2477 /* PREFIX_0F3A0C */
42903f7f
L		 2478 {
2479 { "(bad)", { XX } },
2480 { "(bad)", { XX } },
09a2c6cf 2481 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2482 { "(bad)", { XX } },
2483 },
2484
1ceb70f8 2485 /* PREFIX_0F3A0D */
42903f7f
L		 2486 {
2487 { "(bad)", { XX } },
2488 { "(bad)", { XX } },
09a2c6cf 2489 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2490 { "(bad)", { XX } },
2491 },
2492
1ceb70f8 2493 /* PREFIX_0F3A0E */
42903f7f
L		 2494 {
2495 { "(bad)", { XX } },
2496 { "(bad)", { XX } },
09a2c6cf 2497 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2498 { "(bad)", { XX } },
2499 },
2500
1ceb70f8 2501 /* PREFIX_0F3A14 */
42903f7f
L		 2502 {
2503 { "(bad)", { XX } },
2504 { "(bad)", { XX } },
2505 { "pextrb", { Edqb, XM, Ib } },
2506 { "(bad)", { XX } },
2507 },
2508
1ceb70f8 2509 /* PREFIX_0F3A15 */
42903f7f
L		 2510 {
2511 { "(bad)", { XX } },
2512 { "(bad)", { XX } },
2513 { "pextrw", { Edqw, XM, Ib } },
2514 { "(bad)", { XX } },
2515 },
2516
1ceb70f8 2517 /* PREFIX_0F3A16 */
42903f7f
L		 2518 {
2519 { "(bad)", { XX } },
2520 { "(bad)", { XX } },
2521 { "pextrK", { Edq, XM, Ib } },
2522 { "(bad)", { XX } },
2523 },
2524
1ceb70f8 2525 /* PREFIX_0F3A17 */
42903f7f
L		 2526 {
2527 { "(bad)", { XX } },
2528 { "(bad)", { XX } },
2529 { "extractps", { Edqd, XM, Ib } },
2530 { "(bad)", { XX } },
2531 },
2532
1ceb70f8 2533 /* PREFIX_0F3A20 */
42903f7f
L		 2534 {
2535 { "(bad)", { XX } },
2536 { "(bad)", { XX } },
2537 { "pinsrb", { XM, Edqb, Ib } },
2538 { "(bad)", { XX } },
2539 },
2540
1ceb70f8 2541 /* PREFIX_0F3A21 */
42903f7f
L		 2542 {
2543 { "(bad)", { XX } },
2544 { "(bad)", { XX } },
8976381e 2545 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2546 { "(bad)", { XX } },
2547 },
2548
1ceb70f8 2549 /* PREFIX_0F3A22 */
42903f7f
L		 2550 {
2551 { "(bad)", { XX } },
2552 { "(bad)", { XX } },
2553 { "pinsrK", { XM, Edq, Ib } },
2554 { "(bad)", { XX } },
2555 },
2556
1ceb70f8 2557 /* PREFIX_0F3A40 */
42903f7f
L		 2558 {
2559 { "(bad)", { XX } },
2560 { "(bad)", { XX } },
09a2c6cf 2561 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2562 { "(bad)", { XX } },
2563 },
2564
1ceb70f8 2565 /* PREFIX_0F3A41 */
42903f7f
L		 2566 {
2567 { "(bad)", { XX } },
2568 { "(bad)", { XX } },
09a2c6cf 2569 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2570 { "(bad)", { XX } },
2571 },
2572
1ceb70f8 2573 /* PREFIX_0F3A42 */
42903f7f
L		 2574 {
2575 { "(bad)", { XX } },
2576 { "(bad)", { XX } },
09a2c6cf 2577 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2578 { "(bad)", { XX } },
2579 },
381d071f 2580
1ceb70f8 2581 /* PREFIX_0F3A60 */
381d071f
L		 2582 {
2583 { "(bad)", { XX } },
2584 { "(bad)", { XX } },
4e7d34a6 2585 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2586 { "(bad)", { XX } },
2587 },
2588
1ceb70f8 2589 /* PREFIX_0F3A61 */
381d071f
L		 2590 {
2591 { "(bad)", { XX } },
2592 { "(bad)", { XX } },
4e7d34a6 2593 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2594 { "(bad)", { XX } },
381d071f
L		 2595 },
2596
1ceb70f8 2597 /* PREFIX_0F3A62 */
381d071f
L		 2598 {
2599 { "(bad)", { XX } },
2600 { "(bad)", { XX } },
4e7d34a6 2601 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2602 { "(bad)", { XX } },
381d071f
L		 2603 },
2604
1ceb70f8 2605 /* PREFIX_0F3A63 */
381d071f
L		 2606 {
2607 { "(bad)", { XX } },
2608 { "(bad)", { XX } },
4e7d34a6 2609 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2610 { "(bad)", { XX } },
2611 },
4e7d34a6 2612};
09a2c6cf 2613
4e7d34a6
L		 2614static const struct dis386 x86_64_table[][2] = {
2615 /* X86_64_06 */
09a2c6cf 2616 {
4e7d34a6
L		 2617 { "push{T|}", { es } },
2618 { "(bad)", { XX } },
09a2c6cf
L		 2619 },
2620
4e7d34a6 2621 /* X86_64_07 */
09a2c6cf 2622 {
4e7d34a6
L		 2623 { "pop{T|}", { es } },
2624 { "(bad)", { XX } },
09a2c6cf
L		 2625 },
2626
4e7d34a6 2627 /* X86_64_0D */
09a2c6cf 2628 {
4e7d34a6
L		 2629 { "push{T|}", { cs } },
2630 { "(bad)", { XX } },
09a2c6cf
L		 2631 },
2632
4e7d34a6 2633 /* X86_64_16 */
09a2c6cf 2634 {
4e7d34a6
L		 2635 { "push{T|}", { ss } },
2636 { "(bad)", { XX } },
09a2c6cf
L		 2637 },
2638
4e7d34a6 2639 /* X86_64_17 */
09a2c6cf 2640 {
4e7d34a6 2641 { "pop{T|}", { ss } },
ce518a5f 2642 { "(bad)", { XX } },
5f754f58 2643 },
7c52e0e8 2644
4e7d34a6 2645 /* X86_64_1E */
5f754f58 2646 {
4e7d34a6 2647 { "push{T|}", { ds } },
ce518a5f 2648 { "(bad)", { XX } },
5f754f58 2649 },
7c52e0e8 2650
4e7d34a6 2651 /* X86_64_1F */
5f754f58 2652 {
4e7d34a6 2653 { "pop{T|}", { ds } },
ce518a5f 2654 { "(bad)", { XX } },
5f754f58 2655 },
7c52e0e8 2656
4e7d34a6 2657 /* X86_64_27 */
7c52e0e8 2658 {
4e7d34a6 2659 { "daa", { XX } },
7c52e0e8
L		 2660 { "(bad)", { XX } },
2661 },
2662
4e7d34a6 2663 /* X86_64_2F */
7c52e0e8 2664 {
4e7d34a6 2665 { "das", { XX } },
7c52e0e8
L		 2666 { "(bad)", { XX } },
2667 },
2668
4e7d34a6 2669 /* X86_64_37 */
7c52e0e8 2670 {
4e7d34a6 2671 { "aaa", { XX } },
7c52e0e8
L		 2672 { "(bad)", { XX } },
2673 },
2674
4e7d34a6 2675 /* X86_64_3F */
7c52e0e8 2676 {
4e7d34a6 2677 { "aas", { XX } },
7c52e0e8
L		 2678 { "(bad)", { XX } },
2679 },
2680
4e7d34a6 2681 /* X86_64_60 */
7c52e0e8 2682 {
4e7d34a6 2683 { "pusha{P|}", { XX } },
7c52e0e8
L		 2684 { "(bad)", { XX } },
2685 },
2686
4e7d34a6 2687 /* X86_64_61 */
7c52e0e8 2688 {
4e7d34a6 2689 { "popa{P|}", { XX } },
7c52e0e8
L		 2690 { "(bad)", { XX } },
2691 },
2692
4e7d34a6 2693 /* X86_64_62 */
7c52e0e8 2694 {
1ceb70f8 2695 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2696 { "(bad)", { XX } },
2697 },
2698
4e7d34a6 2699 /* X86_64_63 */
7c52e0e8 2700 {
4e7d34a6
L		 2701 { "arpl", { Ew, Gw } },
2702 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2703 },
2704
4e7d34a6 2705 /* X86_64_6D */
7c52e0e8 2706 {
4e7d34a6
L		 2707 { "ins{R|}", { Yzr, indirDX } },
2708 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2709 },
2710
4e7d34a6 2711 /* X86_64_6F */
7c52e0e8 2712 {
4e7d34a6
L		 2713 { "outs{R|}", { indirDXr, Xz } },
2714 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2715 },
2716
4e7d34a6 2717 /* X86_64_9A */
7c52e0e8 2718 {
4e7d34a6 2719 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2720 { "(bad)", { XX } },
2721 },
2722
4e7d34a6 2723 /* X86_64_C4 */
7c52e0e8 2724 {
1ceb70f8 2725 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2726 { "(bad)", { XX } },
7c52e0e8
L		 2727 },
2728
4e7d34a6 2729 /* X86_64_C5 */
7c52e0e8 2730 {
1ceb70f8 2731 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2732 { "(bad)", { XX } },
2733 },
2734
4e7d34a6 2735 /* X86_64_CE */
7c52e0e8
L		 2736 {
2737 { "into", { XX } },
2738 { "(bad)", { XX } },
2739 },
2740
4e7d34a6 2741 /* X86_64_D4 */
7c52e0e8
L		 2742 {
2743 { "aam", { sIb } },
2744 { "(bad)", { XX } },
2745 },
2746
4e7d34a6 2747 /* X86_64_D5 */
7c52e0e8
L		 2748 {
2749 { "aad", { sIb } },
2750 { "(bad)", { XX } },
2751 },
2752
4e7d34a6 2753 /* X86_64_EA */
7c52e0e8
L		 2754 {
2755 { "Jjmp{T|}", { Ap } },
2756 { "(bad)", { XX } },
2757 },
2758
4e7d34a6 2759 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2760 {
2761 { "sgdt{Q|IQ}", { M } },
2762 { "sgdt", { M } },
2763 },
2764
4e7d34a6 2765 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2766 {
2767 { "sidt{Q|IQ}", { M } },
2768 { "sidt", { M } },
2769 },
2770
4e7d34a6 2771 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2772 {
2773 { "lgdt{Q|Q}", { M } },
2774 { "lgdt", { M } },
2775 },
2776
4e7d34a6 2777 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2778 {
2779 { "lidt{Q|Q}", { M } },
2780 { "lidt", { M } },
2781 },
6439fc28
AM		 2782};
2783
96fbad73 2784static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2785 /* THREE_BYTE_0F24 */
331d2d0d 2786 {
96fbad73 2787 /* 00 */
4e7d34a6
L		 2788 { "fmaddps", { { OP_DREX4, q_mode } } },
2789 { "fmaddpd", { { OP_DREX4, q_mode } } },
2790 { "fmaddss", { { OP_DREX4, w_mode } } },
2791 { "fmaddsd", { { OP_DREX4, d_mode } } },
2792 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2793 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2794 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2795 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2796 /* 08 */
4e7d34a6
L		 2797 { "fmsubps", { { OP_DREX4, q_mode } } },
2798 { "fmsubpd", { { OP_DREX4, q_mode } } },
2799 { "fmsubss", { { OP_DREX4, w_mode } } },
2800 { "fmsubsd", { { OP_DREX4, d_mode } } },
2801 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2802 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2803 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2804 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2805 /* 10 */
4e7d34a6
L		 2806 { "fnmaddps", { { OP_DREX4, q_mode } } },
2807 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2808 { "fnmaddss", { { OP_DREX4, w_mode } } },
2809 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2810 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2811 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2812 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2813 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2814 /* 18 */
4e7d34a6
L		 2815 { "fnmsubps", { { OP_DREX4, q_mode } } },
2816 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2817 { "fnmsubss", { { OP_DREX4, w_mode } } },
2818 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2819 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2820 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2821 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2822 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2823 /* 20 */
4e7d34a6
L		 2824 { "permps", { { OP_DREX4, q_mode } } },
2825 { "permpd", { { OP_DREX4, q_mode } } },
2826 { "pcmov", { { OP_DREX4, q_mode } } },
2827 { "pperm", { { OP_DREX4, q_mode } } },
2828 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2829 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2830 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2831 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2832 /* 28 */
4e7d34a6
L		 2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
85f10a01 2841 /* 30 */
4e7d34a6
L		 2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
85f10a01 2850 /* 38 */
4e7d34a6
L		 2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
85f10a01 2859 /* 40 */
4e7d34a6
L		 2860 { "protb", { { OP_DREX3, q_mode } } },
2861 { "protw", { { OP_DREX3, q_mode } } },
2862 { "protd", { { OP_DREX3, q_mode } } },
2863 { "protq", { { OP_DREX3, q_mode } } },
2864 { "pshlb", { { OP_DREX3, q_mode } } },
2865 { "pshlw", { { OP_DREX3, q_mode } } },
2866 { "pshld", { { OP_DREX3, q_mode } } },
2867 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2868 /* 48 */
4e7d34a6
L		 2869 { "pshab", { { OP_DREX3, q_mode } } },
2870 { "pshaw", { { OP_DREX3, q_mode } } },
2871 { "pshad", { { OP_DREX3, q_mode } } },
2872 { "pshaq", { { OP_DREX3, q_mode } } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
85f10a01 2877 /* 50 */
4e7d34a6
L		 2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
85f10a01 2886 /* 58 */
4e7d34a6
L		 2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
85f10a01 2895 /* 60 */
4e7d34a6
L		 2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 /* 68 */
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
85f10a01 2913 /* 70 */
4e7d34a6
L		 2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
85f10a01 2922 /* 78 */
4e7d34a6
L		 2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
85f10a01 2931 /* 80 */
4e7d34a6
L		 2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2938 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2939 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2940 /* 88 */
4e7d34a6
L		 2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2948 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2949 /* 90 */
4e7d34a6
L		 2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2956 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2957 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2958 /* 98 */
4e7d34a6
L		 2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2966 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2967 /* a0 */
4e7d34a6
L		 2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2975 { "(bad)", { XX } },
85f10a01 2976 /* a8 */
4e7d34a6
L		 2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
85f10a01 2985 /* b0 */
4e7d34a6
L		 2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2993 { "(bad)", { XX } },
85f10a01 2994 /* b8 */
4e7d34a6
L		 2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
85f10a01 3003 /* c0 */
4e7d34a6
L		 3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
85f10a01 3012 /* c8 */
4e7d34a6
L		 3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
85f10a01 3021 /* d0 */
4e7d34a6
L		 3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
85f10a01 3030 /* d8 */
4e7d34a6
L		 3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
85f10a01 3039 /* e0 */
4e7d34a6
L		 3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
85f10a01 3048 /* e8 */
4e7d34a6
L		 3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
85f10a01 3057 /* f0 */
4e7d34a6
L		 3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
85f10a01 3066 /* f8 */
4e7d34a6
L		 3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
85f10a01 3075 },
4e7d34a6 3076 /* THREE_BYTE_0F25 */
85f10a01
MM		 3077 {
3078 /* 00 */
4e7d34a6
L		 3079 { "(bad)", { XX } },
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
85f10a01 3087 /* 08 */
4e7d34a6
L		 3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
85f10a01 3096 /* 10 */
4e7d34a6
L		 3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
85f10a01 3105 /* 18 */
4e7d34a6
L		 3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
85f10a01 3114 /* 20 */
4e7d34a6
L		 3115 { "(bad)", { XX } },
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
85f10a01 3123 /* 28 */
4e7d34a6
L		 3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3129 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3130 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3131 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3132 /* 30 */
4e7d34a6
L		 3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
85f10a01 3141 /* 38 */
4e7d34a6
L		 3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
85f10a01 3150 /* 40 */
4e7d34a6
L		 3151 { "(bad)", { XX } },
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
85f10a01 3159 /* 48 */
4e7d34a6
L		 3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3165 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3166 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3167 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3168 /* 50 */
4e7d34a6
L		 3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
85f10a01 3177 /* 58 */
4e7d34a6
L		 3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
85f10a01 3186 /* 60 */
4e7d34a6
L		 3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
85f10a01 3195 /* 68 */
4e7d34a6
L		 3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3201 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3202 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3203 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3204 /* 70 */
4e7d34a6
L		 3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
85f10a01 3213 /* 78 */
4e7d34a6
L		 3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
85f10a01 3222 /* 80 */
4e7d34a6
L		 3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 /* 88 */
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 /* 90 */
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 /* 98 */
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 /* a0 */
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 /* a8 */
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 /* b0 */
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 /* b8 */
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 /* c0 */
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 /* c8 */
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 /* d0 */
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 { "(bad)", { XX } },
3321 /* d8 */
3322 { "(bad)", { XX } },
3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 /* e0 */
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
3333 { "(bad)", { XX } },
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 /* e8 */
3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 { "(bad)", { XX } },
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 { "(bad)", { XX } },
3348 /* f0 */
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
3352 { "(bad)", { XX } },
3353 { "(bad)", { XX } },
3354 { "(bad)", { XX } },
3355 { "(bad)", { XX } },
3356 { "(bad)", { XX } },
3357 /* f8 */
3358 { "(bad)", { XX } },
3359 { "(bad)", { XX } },
3360 { "(bad)", { XX } },
3361 { "(bad)", { XX } },
3362 { "(bad)", { XX } },
3363 { "(bad)", { XX } },
3364 { "(bad)", { XX } },
3365 { "(bad)", { XX } },
3366 },
3367 /* THREE_BYTE_0F38 */
3368 {
3369 /* 00 */
d5d7db8e
L		 3370 { "pshufb", { MX, EM } },
3371 { "phaddw", { MX, EM } },
3372 { "phaddd", { MX, EM } },
3373 { "phaddsw", { MX, EM } },
3374 { "pmaddubsw", { MX, EM } },
3375 { "phsubw", { MX, EM } },
3376 { "phsubd", { MX, EM } },
3377 { "phsubsw", { MX, EM } },
4e7d34a6 3378 /* 08 */
d5d7db8e
L		 3379 { "psignb", { MX, EM } },
3380 { "psignw", { MX, EM } },
3381 { "psignd", { MX, EM } },
3382 { "pmulhrsw", { MX, EM } },
3383 { "(bad)", { XX } },
3384 { "(bad)", { XX } },
3385 { "(bad)", { XX } },
3386 { "(bad)", { XX } },
4e7d34a6 3387 /* 10 */
1ceb70f8 3388 { PREFIX_TABLE (PREFIX_0F3810) },
d5d7db8e
L		 3389 { "(bad)", { XX } },
3390 { "(bad)", { XX } },
3391 { "(bad)", { XX } },
1ceb70f8
L		 3392 { PREFIX_TABLE (PREFIX_0F3814) },
3393 { PREFIX_TABLE (PREFIX_0F3815) },
d5d7db8e 3394 { "(bad)", { XX } },
1ceb70f8 3395 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3396 /* 18 */
d5d7db8e
L		 3397 { "(bad)", { XX } },
3398 { "(bad)", { XX } },
3399 { "(bad)", { XX } },
3400 { "(bad)", { XX } },
3401 { "pabsb", { MX, EM } },
3402 { "pabsw", { MX, EM } },
3403 { "pabsd", { MX, EM } },
3404 { "(bad)", { XX } },
4e7d34a6 3405 /* 20 */
1ceb70f8
L		 3406 { PREFIX_TABLE (PREFIX_0F3820) },
3407 { PREFIX_TABLE (PREFIX_0F3821) },
3408 { PREFIX_TABLE (PREFIX_0F3822) },
3409 { PREFIX_TABLE (PREFIX_0F3823) },
3410 { PREFIX_TABLE (PREFIX_0F3824) },
3411 { PREFIX_TABLE (PREFIX_0F3825) },
d5d7db8e
L		 3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
4e7d34a6 3414 /* 28 */
1ceb70f8
L		 3415 { PREFIX_TABLE (PREFIX_0F3828) },
3416 { PREFIX_TABLE (PREFIX_0F3829) },
3417 { PREFIX_TABLE (PREFIX_0F382A) },
3418 { PREFIX_TABLE (PREFIX_0F382B) },
d5d7db8e
L		 3419 { "(bad)", { XX } },
3420 { "(bad)", { XX } },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
4e7d34a6 3423 /* 30 */
1ceb70f8
L		 3424 { PREFIX_TABLE (PREFIX_0F3830) },
3425 { PREFIX_TABLE (PREFIX_0F3831) },
3426 { PREFIX_TABLE (PREFIX_0F3832) },
3427 { PREFIX_TABLE (PREFIX_0F3833) },
3428 { PREFIX_TABLE (PREFIX_0F3834) },
3429 { PREFIX_TABLE (PREFIX_0F3835) },
d5d7db8e 3430 { "(bad)", { XX } },
1ceb70f8 3431 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3432 /* 38 */
1ceb70f8
L		 3433 { PREFIX_TABLE (PREFIX_0F3838) },
3434 { PREFIX_TABLE (PREFIX_0F3839) },
3435 { PREFIX_TABLE (PREFIX_0F383A) },
3436 { PREFIX_TABLE (PREFIX_0F383B) },
3437 { PREFIX_TABLE (PREFIX_0F383C) },
3438 { PREFIX_TABLE (PREFIX_0F383D) },
3439 { PREFIX_TABLE (PREFIX_0F383E) },
3440 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3441 /* 40 */
1ceb70f8
L		 3442 { PREFIX_TABLE (PREFIX_0F3840) },
3443 { PREFIX_TABLE (PREFIX_0F3841) },
d5d7db8e
L		 3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
4e7d34a6 3450 /* 48 */
d5d7db8e
L		 3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
4e7d34a6 3459 /* 50 */
d5d7db8e
L		 3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
4e7d34a6 3468 /* 58 */
d5d7db8e
L		 3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
4e7d34a6 3477 /* 60 */
d5d7db8e
L		 3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
4e7d34a6 3486 /* 68 */
d5d7db8e
L		 3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
4e7d34a6 3495 /* 70 */
d5d7db8e
L		 3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
4e7d34a6 3504 /* 78 */
d5d7db8e
L		 3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
4e7d34a6 3513 /* 80 */
d5d7db8e
L		 3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
4e7d34a6 3522 /* 88 */
d5d7db8e
L		 3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
4e7d34a6 3531 /* 90 */
d5d7db8e
L		 3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
4e7d34a6 3540 /* 98 */
d5d7db8e
L		 3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
4e7d34a6 3549 /* a0 */
d5d7db8e
L		 3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
4e7d34a6 3558 /* a8 */
d5d7db8e
L		 3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 /* b0 */
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
85f10a01 3576 /* b8 */
d5d7db8e
L		 3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
85f10a01 3585 /* c0 */
d5d7db8e
L		 3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
85f10a01 3594 /* c8 */
d5d7db8e
L		 3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
85f10a01 3603 /* d0 */
d5d7db8e
L		 3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
85f10a01 3612 /* d8 */
d5d7db8e
L		 3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
85f10a01 3621 /* e0 */
d5d7db8e
L		 3622 { "(bad)", { XX } },
3623 { "(bad)", { XX } },
3624 { "(bad)", { XX } },
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
85f10a01 3630 /* e8 */
d5d7db8e
L		 3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
85f10a01 3639 /* f0 */
1ceb70f8
L		 3640 { PREFIX_TABLE (PREFIX_0F38F0) },
3641 { PREFIX_TABLE (PREFIX_0F38F1) },
d5d7db8e
L		 3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
85f10a01 3648 /* f8 */
d5d7db8e
L		 3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
85f10a01 3657 },
4e7d34a6 3658 /* THREE_BYTE_0F3A */
85f10a01
MM		 3659 {
3660 /* 00 */
d5d7db8e
L		 3661 { "(bad)", { XX } },
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
85f10a01 3669 /* 08 */
1ceb70f8
L		 3670 { PREFIX_TABLE (PREFIX_0F3A08) },
3671 { PREFIX_TABLE (PREFIX_0F3A09) },
3672 { PREFIX_TABLE (PREFIX_0F3A0A) },
3673 { PREFIX_TABLE (PREFIX_0F3A0B) },
3674 { PREFIX_TABLE (PREFIX_0F3A0C) },
3675 { PREFIX_TABLE (PREFIX_0F3A0D) },
3676 { PREFIX_TABLE (PREFIX_0F3A0E) },
d5d7db8e 3677 { "palignr", { MX, EM, Ib } },
85f10a01 3678 /* 10 */
d5d7db8e
L		 3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
1ceb70f8
L		 3683 { PREFIX_TABLE (PREFIX_0F3A14) },
3684 { PREFIX_TABLE (PREFIX_0F3A15) },
3685 { PREFIX_TABLE (PREFIX_0F3A16) },
3686 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3687 /* 18 */
d5d7db8e
L		 3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
85f10a01 3696 /* 20 */
1ceb70f8
L		 3697 { PREFIX_TABLE (PREFIX_0F3A20) },
3698 { PREFIX_TABLE (PREFIX_0F3A21) },
3699 { PREFIX_TABLE (PREFIX_0F3A22) },
d5d7db8e
L		 3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
85f10a01 3705 /* 28 */
d5d7db8e
L		 3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
85f10a01 3714 /* 30 */
d5d7db8e
L		 3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
4e7d34a6 3723 /* 38 */
d5d7db8e
L		 3724 { "(bad)", { XX } },
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 /* 40 */
3733 { PREFIX_TABLE (PREFIX_0F3A40) },
3734 { PREFIX_TABLE (PREFIX_0F3A41) },
3735 { PREFIX_TABLE (PREFIX_0F3A42) },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
85f10a01 3741 /* 48 */
85f10a01
MM		 3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
d5d7db8e 3750 /* 50 */
85f10a01
MM		 3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
d5d7db8e 3759 /* 58 */
85f10a01
MM		 3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
85f10a01
MM		 3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
d5d7db8e
L		 3768 /* 60 */
3769 { PREFIX_TABLE (PREFIX_0F3A60) },
3770 { PREFIX_TABLE (PREFIX_0F3A61) },
3771 { PREFIX_TABLE (PREFIX_0F3A62) },
3772 { PREFIX_TABLE (PREFIX_0F3A63) },
85f10a01
MM		 3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
d5d7db8e 3777 /* 68 */
85f10a01
MM		 3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
85f10a01 3785 { "(bad)", { XX } },
d5d7db8e 3786 /* 70 */
85f10a01
MM		 3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
d5d7db8e
L		 3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 /* 78 */
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 /* 80 */
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 /* 88 */
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 /* 90 */
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 /* 98 */
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 /* a0 */
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 /* a8 */
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 /* b0 */
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 /* b8 */
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 /* c0 */
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 /* c8 */
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 /* d0 */
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 /* d8 */
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 /* e0 */
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 /* e8 */
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 /* f0 */
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 /* f8 */
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 },
3949 /* THREE_BYTE_0F7A */
3950 {
3951 /* 00 */
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 { "(bad)", { XX } },
3960 /* 08 */
3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 /* 10 */
3970 { "frczps", { XM, EXq } },
3971 { "frczpd", { XM, EXq } },
3972 { "frczss", { XM, EXq } },
3973 { "frczsd", { XM, EXq } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 /* 18 */
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 /* 20 */
3988 { "ptest", { XX } },
3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 /* 28 */
3997 { "(bad)", { XX } },
3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 /* 30 */
85f10a01
MM		 4006 { "cvtph2ps", { XM, EXd } },
4007 { "cvtps2ph", { EXd, XM } },
d5d7db8e
L		 4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { "(bad)", { XX } },
85f10a01 4014 /* 38 */
d5d7db8e
L		 4015 { "(bad)", { XX } },
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
96fbad73 4023 /* 40 */
d5d7db8e 4024 { "(bad)", { XX } },
85f10a01
MM		 4025 { "phaddbw", { XM, EXq } },
4026 { "phaddbd", { XM, EXq } },
4027 { "phaddbq", { XM, EXq } },
d5d7db8e
L		 4028 { "(bad)", { XX } },
4029 { "(bad)", { XX } },
85f10a01
MM		 4030 { "phaddwd", { XM, EXq } },
4031 { "phaddwq", { XM, EXq } },
96fbad73 4032 /* 48 */
d5d7db8e
L		 4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
85f10a01 4036 { "phadddq", { XM, EXq } },
d5d7db8e
L		 4037 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
96fbad73 4041 /* 50 */
d5d7db8e 4042 { "(bad)", { XX } },
85f10a01
MM		 4043 { "phaddubw", { XM, EXq } },
4044 { "phaddubd", { XM, EXq } },
4045 { "phaddubq", { XM, EXq } },
d5d7db8e
L		 4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
85f10a01
MM		 4048 { "phadduwd", { XM, EXq } },
4049 { "phadduwq", { XM, EXq } },
96fbad73 4050 /* 58 */
d5d7db8e
L		 4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
85f10a01 4054 { "phaddudq", { XM, EXq } },
d5d7db8e
L		 4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
96fbad73 4059 /* 60 */
d5d7db8e 4060 { "(bad)", { XX } },
85f10a01
MM		 4061 { "phsubbw", { XM, EXq } },
4062 { "phsubbd", { XM, EXq } },
4063 { "phsubbq", { XM, EXq } },
d5d7db8e
L		 4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
96fbad73 4068 /* 68 */
d5d7db8e
L		 4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
96fbad73 4077 /* 70 */
d5d7db8e
L		 4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
96fbad73 4086 /* 78 */
d5d7db8e
L		 4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
96fbad73 4095 /* 80 */
d5d7db8e
L		 4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
96fbad73 4104 /* 88 */
d5d7db8e
L		 4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
96fbad73 4113 /* 90 */
d5d7db8e
L		 4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
96fbad73 4122 /* 98 */
d5d7db8e
L		 4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
96fbad73 4131 /* a0 */
d5d7db8e
L		 4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
96fbad73 4140 /* a8 */
d5d7db8e
L		 4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
96fbad73 4149 /* b0 */
d5d7db8e
L		 4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
96fbad73 4158 /* b8 */
d5d7db8e
L		 4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
96fbad73 4167 /* c0 */
d5d7db8e
L		 4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
96fbad73 4176 /* c8 */
d5d7db8e
L		 4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
96fbad73 4185 /* d0 */
d5d7db8e
L		 4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
96fbad73 4194 /* d8 */
d5d7db8e
L		 4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
96fbad73 4203 /* e0 */
d5d7db8e
L		 4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
96fbad73 4212 /* e8 */
d5d7db8e
L		 4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
96fbad73 4221 /* f0 */
85f10a01
MM		 4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
d5d7db8e
L		 4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
96fbad73 4230 /* f8 */
d5d7db8e
L		 4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
331d2d0d 4239 },
89b66d55 4240 /* THREE_BYTE_0F7B */
331d2d0d 4241 {
96fbad73 4242 /* 00 */
d5d7db8e
L		 4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
96fbad73 4251 /* 08 */
d5d7db8e
L		 4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
85f10a01 4260 /* 10 */
d5d7db8e
L		 4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
85f10a01 4269 /* 18 */
d5d7db8e
L		 4270 { "(bad)", { XX } },
4271 { "(bad)", { XX } },
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
85f10a01 4278 /* 20 */
d5d7db8e
L		 4279 { "(bad)", { XX } },
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
85f10a01 4287 /* 28 */
d5d7db8e
L		 4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
85f10a01 4296 /* 30 */
d5d7db8e
L		 4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
4302 { "(bad)", { XX } },
85f10a01
MM		 4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 /* 38 */
4306 { "(bad)", { XX } },
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
d5d7db8e
L		 4309 { "(bad)", { XX } },
4310 { "(bad)", { XX } },
4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
85f10a01
MM		 4314 /* 40 */
4315 { "protb", { XM, EXq, Ib } },
4316 { "protw", { XM, EXq, Ib } },
4317 { "protd", { XM, EXq, Ib } },
4318 { "protq", { XM, EXq, Ib } },
4319 { "pshlb", { XM, EXq, Ib } },
4320 { "pshlw", { XM, EXq, Ib } },
4321 { "pshld", { XM, EXq, Ib } },
4322 { "pshlq", { XM, EXq, Ib } },
4323 /* 48 */
4324 { "pshab", { XM, EXq, Ib } },
4325 { "pshaw", { XM, EXq, Ib } },
4326 { "pshad", { XM, EXq, Ib } },
4327 { "pshaq", { XM, EXq, Ib } },
4328 { "(bad)", { XX } },
d5d7db8e
L		 4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
96fbad73 4332 /* 50 */
d5d7db8e
L		 4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
96fbad73 4341 /* 58 */
d5d7db8e
L		 4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
96fbad73 4350 /* 60 */
85f10a01
MM		 4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
d5d7db8e
L		 4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
96fbad73 4359 /* 68 */
d5d7db8e
L		 4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
96fbad73 4368 /* 70 */
d5d7db8e
L		 4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
96fbad73 4377 /* 78 */
d5d7db8e
L		 4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
96fbad73 4386 /* 80 */
d5d7db8e
L		 4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
96fbad73 4395 /* 88 */
d5d7db8e
L		 4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
96fbad73 4404 /* 90 */
d5d7db8e
L		 4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
96fbad73 4413 /* 98 */
d5d7db8e
L		 4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
96fbad73 4422 /* a0 */
d5d7db8e
L		 4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
96fbad73 4431 /* a8 */
d5d7db8e
L		 4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
96fbad73 4440 /* b0 */
d5d7db8e
L		 4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
96fbad73 4449 /* b8 */
d5d7db8e
L		 4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
96fbad73 4458 /* c0 */
d5d7db8e
L		 4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
96fbad73 4467 /* c8 */
d5d7db8e
L		 4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
96fbad73 4476 /* d0 */
d5d7db8e
L		 4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
96fbad73 4485 /* d8 */
d5d7db8e
L		 4486 { "(bad)", { XX } },
4487 { "(bad)", { XX } },
4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { "(bad)", { XX } },
96fbad73 4494 /* e0 */
d5d7db8e
L		 4495 { "(bad)", { XX } },
4496 { "(bad)", { XX } },
4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
4502 { "(bad)", { XX } },
96fbad73 4503 /* e8 */
d5d7db8e
L		 4504 { "(bad)", { XX } },
4505 { "(bad)", { XX } },
4506 { "(bad)", { XX } },
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { "(bad)", { XX } },
4510 { "(bad)", { XX } },
4511 { "(bad)", { XX } },
96fbad73 4512 /* f0 */
d5d7db8e
L		 4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
4515 { "(bad)", { XX } },
4516 { "(bad)", { XX } },
4517 { "(bad)", { XX } },
4518 { "(bad)", { XX } },
4519 { "(bad)", { XX } },
4520 { "(bad)", { XX } },
96fbad73 4521 /* f8 */
d5d7db8e
L		 4522 { "(bad)", { XX } },
4523 { "(bad)", { XX } },
4524 { "(bad)", { XX } },
4525 { "(bad)", { XX } },
4526 { "(bad)", { XX } },
4527 { "(bad)", { XX } },
4528 { "(bad)", { XX } },
4529 { "(bad)", { XX } },
ce518a5f 4530 }
331d2d0d
L		 4531};
4532
1ceb70f8 4533static const struct dis386 mod_table[][2] = {
b844680a 4534 {
1ceb70f8 4535 /* MOD_8D */
d8faab4e
L		 4536 { "leaS", { Gv, M } },
4537 { "(bad)", { XX } },
4538 },
4539 {
92fddf8e
L		 4540 /* MOD_0F01_REG_0 */
4541 { X86_64_TABLE (X86_64_0F01_REG_0) },
4542 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 4543 },
4544 {
92fddf8e
L		 4545 /* MOD_0F01_REG_1 */
4546 { X86_64_TABLE (X86_64_0F01_REG_1) },
4547 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 4548 },
4549 {
92fddf8e
L		 4550 /* MOD_0F01_REG_2 */
4551 { X86_64_TABLE (X86_64_0F01_REG_2) },
d8faab4e
L		 4552 { "(bad)", { XX } },
4553 },
4554 {
92fddf8e
L		 4555 /* MOD_0F01_REG_3 */
4556 { X86_64_TABLE (X86_64_0F01_REG_3) },
4557 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 4558 },
4559 {
92fddf8e
L		 4560 /* MOD_0F01_REG_7 */
4561 { "invlpg", { Mb } },
4562 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4563 },
4564 {
92fddf8e
L		 4565 /* MOD_0F12_PREFIX_0 */
4566 { "movlps", { XM, EXq } },
4567 { "movhlps", { XM, EXq } },
b844680a
L		 4568 },
4569 {
92fddf8e
L		 4570 /* MOD_0F13 */
4571 { "movlpX", { EXq, XM } },
d8faab4e
L		 4572 { "(bad)", { XX } },
4573 },
4574 {
92fddf8e
L		 4575 /* MOD_0F16_PREFIX_0 */
4576 { "movhps", { XM, EXq } },
4577 { "movlhps", { XM, EXq } },
b844680a
L		 4578 },
4579 {
92fddf8e
L		 4580 /* MOD_0F17 */
4581 { "movhpX", { EXq, XM } },
b844680a
L		 4582 { "(bad)", { XX } },
4583 },
4584 {
92fddf8e
L		 4585 /* MOD_0F18_REG_0 */
4586 { "prefetchnta", { Mb } },
b844680a 4587 { "(bad)", { XX } },
b844680a
L		 4588 },
4589 {
92fddf8e
L		 4590 /* MOD_0F18_REG_1 */
4591 { "prefetcht0", { Mb } },
4592 { "(bad)", { XX } },
b844680a
L		 4593 },
4594 {
92fddf8e
L		 4595 /* MOD_0F18_REG_2 */
4596 { "prefetcht1", { Mb } },
4597 { "(bad)", { XX } },
b844680a
L		 4598 },
4599 {
92fddf8e
L		 4600 /* MOD_0F18_REG_3 */
4601 { "prefetcht2", { Mb } },
b844680a 4602 { "(bad)", { XX } },
b844680a
L		 4603 },
4604 {
92fddf8e
L		 4605 /* MOD_0F20 */
4606 { "(bad)", { XX } },
4607 { "movZ", { Rm, Cm } },
b844680a
L		 4608 },
4609 {
92fddf8e
L		 4610 /* MOD_0F21 */
4611 { "(bad)", { XX } },
4612 { "movZ", { Rm, Dm } },
b844680a
L		 4613 },
4614 {
92fddf8e 4615 /* MOD_0F22 */
b844680a 4616 { "(bad)", { XX } },
92fddf8e 4617 { "movZ", { Cm, Rm } },
b844680a
L		 4618 },
4619 {
92fddf8e 4620 /* MOD_0F23 */
b844680a 4621 { "(bad)", { XX } },
92fddf8e 4622 { "movZ", { Dm, Rm } },
b844680a
L		 4623 },
4624 {
92fddf8e
L		 4625 /* MOD_0F24 */
4626 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4627 { "movL", { Rd, Td } },
b844680a
L		 4628 },
4629 {
92fddf8e 4630 /* MOD_0F26 */
b844680a 4631 { "(bad)", { XX } },
92fddf8e 4632 { "movL", { Td, Rd } },
b844680a 4633 },
75c135a8
L		 4634 {
4635 /* MOD_0F2B_PREFIX_0 */
4ee52178 4636 {"movntps", { Mx, XM } },
75c135a8
L		 4637 { "(bad)", { XX } },
4638 },
4639 {
4640 /* MOD_0F2B_PREFIX_1 */
4ee52178 4641 {"movntss", { Md, XM } },
75c135a8
L		 4642 { "(bad)", { XX } },
4643 },
4644 {
4645 /* MOD_0F2B_PREFIX_2 */
4ee52178 4646 {"movntpd", { Mx, XM } },
75c135a8
L		 4647 { "(bad)", { XX } },
4648 },
4649 {
4650 /* MOD_0F2B_PREFIX_3 */
4ee52178 4651 {"movntsd", { Mq, XM } },
75c135a8
L		 4652 { "(bad)", { XX } },
4653 },
4654 {
4655 /* MOD_0F51 */
4656 { "(bad)", { XX } },
4657 { "movmskpX", { Gdq, XS } },
4658 },
b844680a 4659 {
1ceb70f8 4660 /* MOD_0F71_REG_2 */
b844680a 4661 { "(bad)", { XX } },
4e7d34a6 4662 { "psrlw", { MS, Ib } },
b844680a
L		 4663 },
4664 {
1ceb70f8 4665 /* MOD_0F71_REG_4 */
b844680a 4666 { "(bad)", { XX } },
4e7d34a6 4667 { "psraw", { MS, Ib } },
b844680a
L		 4668 },
4669 {
1ceb70f8 4670 /* MOD_0F71_REG_6 */
b844680a 4671 { "(bad)", { XX } },
4e7d34a6 4672 { "psllw", { MS, Ib } },
b844680a
L		 4673 },
4674 {
1ceb70f8 4675 /* MOD_0F72_REG_2 */
b844680a 4676 { "(bad)", { XX } },
4e7d34a6 4677 { "psrld", { MS, Ib } },
b844680a
L		 4678 },
4679 {
1ceb70f8 4680 /* MOD_0F72_REG_4 */
b844680a 4681 { "(bad)", { XX } },
4e7d34a6 4682 { "psrad", { MS, Ib } },
b844680a
L		 4683 },
4684 {
1ceb70f8 4685 /* MOD_0F72_REG_6 */
b844680a 4686 { "(bad)", { XX } },
4e7d34a6 4687 { "pslld", { MS, Ib } },
b844680a
L		 4688 },
4689 {
1ceb70f8 4690 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4691 { "(bad)", { XX } },
4692 { "psrlq", { MS, Ib } },
b844680a
L		 4693 },
4694 {
1ceb70f8 4695 /* MOD_0F73_REG_3 */
b844680a 4696 { "(bad)", { XX } },
1ceb70f8 4697 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4698 },
4699 {
1ceb70f8 4700 /* MOD_0F73_REG_6 */
b844680a 4701 { "(bad)", { XX } },
4e7d34a6 4702 { "psllq", { MS, Ib } },
b844680a
L		 4703 },
4704 {
1ceb70f8 4705 /* MOD_0F73_REG_7 */
b844680a 4706 { "(bad)", { XX } },
1ceb70f8 4707 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4708 },
4709 {
1ceb70f8 4710 /* MOD_0FAE_REG_0 */
4e7d34a6 4711 { "fxsave", { M } },
b844680a
L		 4712 { "(bad)", { XX } },
4713 },
d8faab4e 4714 {
1ceb70f8 4715 /* MOD_0FAE_REG_1 */
4e7d34a6 4716 { "fxrstor", { M } },
d8faab4e
L		 4717 { "(bad)", { XX } },
4718 },
4719 {
1ceb70f8 4720 /* MOD_0FAE_REG_2 */
4e7d34a6 4721 { "ldmxcsr", { Md } },
d8faab4e
L		 4722 { "(bad)", { XX } },
4723 },
876d4bfa 4724 {
1ceb70f8 4725 /* MOD_0FAE_REG_3 */
4e7d34a6 4726 { "stmxcsr", { Md } },
876d4bfa
L		 4727 { "(bad)", { XX } },
4728 },
4729 {
1ceb70f8 4730 /* MOD_0FAE_REG_5 */
876d4bfa 4731 { "(bad)", { XX } },
1ceb70f8 4732 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4733 },
4734 {
1ceb70f8 4735 /* MOD_0FAE_REG_6 */
4e7d34a6 4736 { "(bad)", { XX } },
1ceb70f8 4737 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4738 },
4739 {
1ceb70f8 4740 /* MOD_0FAE_REG_7 */
4e7d34a6 4741 { "clflush", { Mb } },
1ceb70f8 4742 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4743 },
bbedc832 4744 {
92fddf8e
L		 4745 /* MOD_0FB2 */
4746 { "lssS", { Gv, Mp } },
4e7d34a6 4747 { "(bad)", { XX } },
bbedc832 4748 },
144c41d9 4749 {
92fddf8e
L		 4750 /* MOD_0FB4 */
4751 { "lfsS", { Gv, Mp } },
4e7d34a6 4752 { "(bad)", { XX } },
144c41d9 4753 },
1afd85e3 4754 {
92fddf8e
L		 4755 /* MOD_0FB5 */
4756 { "lgsS", { Gv, Mp } },
4757 { "(bad)", { XX } },
1afd85e3
L		 4758 },
4759 {
92fddf8e
L		 4760 /* MOD_0FC7_REG_6 */
4761 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4762 { "(bad)", { XX } },
4763 },
4764 {
4765 /* MOD_0FC7_REG_7 */
4766 { "vmptrst", { Mq } },
4767 { "(bad)", { XX } },
1afd85e3 4768 },
75c135a8
L		 4769 {
4770 /* MOD_0FD7 */
4771 { "(bad)", { XX } },
4772 { "pmovmskb", { Gdq, MS } },
4773 },
4774 {
4775 /* MOD_0FE7_PREFIX_2 */
4ee52178 4776 { "movntdq", { Mx, XM } },
75c135a8
L		 4777 { "(bad)", { XX } },
4778 },
1afd85e3 4779 {
1ceb70f8 4780 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4781 { "lddqu", { XM, M } },
1afd85e3 4782 { "(bad)", { XX } },
1afd85e3 4783 },
75c135a8
L		 4784 {
4785 /* MOD_0F382A_PREFIX_2 */
4ee52178 4786 { "movntdqa", { XM, Mx } },
75c135a8
L		 4787 { "(bad)", { XX } },
4788 },
1afd85e3 4789 {
1ceb70f8 4790 /* MOD_62_32BIT */
4e7d34a6 4791 { "bound{S|}", { Gv, Ma } },
1afd85e3 4792 { "(bad)", { XX } },
1afd85e3
L		 4793 },
4794 {
1ceb70f8 4795 /* MOD_C4_32BIT */
4e7d34a6
L		 4796 { "lesS", { Gv, Mp } },
4797 { "(bad)", { XX } },
1afd85e3
L		 4798 },
4799 {
1ceb70f8 4800 /* MOD_C5_32BIT */
4e7d34a6 4801 { "ldsS", { Gv, Mp } },
1afd85e3 4802 { "(bad)", { XX } },
1afd85e3 4803 },
b844680a
L		 4804};
4805
1ceb70f8 4806static const struct dis386 rm_table[][8] = {
b844680a 4807 {
1ceb70f8 4808 /* RM_0F01_REG_0 */
b844680a
L		 4809 { "(bad)", { XX } },
4810 { "vmcall", { Skip_MODRM } },
4811 { "vmlaunch", { Skip_MODRM } },
4812 { "vmresume", { Skip_MODRM } },
4813 { "vmxoff", { Skip_MODRM } },
4814 { "(bad)", { XX } },
4815 { "(bad)", { XX } },
4816 { "(bad)", { XX } },
4817 },
4818 {
1ceb70f8 4819 /* RM_0F01_REG_1 */
b844680a
L		 4820 { "monitor", { { OP_Monitor, 0 } } },
4821 { "mwait", { { OP_Mwait, 0 } } },
4822 { "(bad)", { XX } },
4823 { "(bad)", { XX } },
4824 { "(bad)", { XX } },
4825 { "(bad)", { XX } },
4826 { "(bad)", { XX } },
4827 { "(bad)", { XX } },
4828 },
4829 {
1ceb70f8 4830 /* RM_0F01_REG_3 */
4e7d34a6
L		 4831 { "vmrun", { Skip_MODRM } },
4832 { "vmmcall", { Skip_MODRM } },
4833 { "vmload", { Skip_MODRM } },
4834 { "vmsave", { Skip_MODRM } },
4835 { "stgi", { Skip_MODRM } },
4836 { "clgi", { Skip_MODRM } },
4837 { "skinit", { Skip_MODRM } },
4838 { "invlpga", { Skip_MODRM } },
4839 },
4840 {
1ceb70f8 4841 /* RM_0F01_REG_7 */
4e7d34a6
L		 4842 { "swapgs", { Skip_MODRM } },
4843 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4844 { "(bad)", { XX } },
4845 { "(bad)", { XX } },
4846 { "(bad)", { XX } },
4847 { "(bad)", { XX } },
4848 { "(bad)", { XX } },
4849 { "(bad)", { XX } },
4850 },
4851 {
1ceb70f8 4852 /* RM_0FAE_REG_5 */
4e7d34a6 4853 { "lfence", { Skip_MODRM } },
b844680a
L		 4854 { "(bad)", { XX } },
4855 { "(bad)", { XX } },
4856 { "(bad)", { XX } },
4857 { "(bad)", { XX } },
4858 { "(bad)", { XX } },
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
4861 },
4862 {
1ceb70f8 4863 /* RM_0FAE_REG_6 */
4e7d34a6 4864 { "mfence", { Skip_MODRM } },
b844680a
L		 4865 { "(bad)", { XX } },
4866 { "(bad)", { XX } },
4867 { "(bad)", { XX } },
4868 { "(bad)", { XX } },
4869 { "(bad)", { XX } },
4870 { "(bad)", { XX } },
4871 { "(bad)", { XX } },
4872 },
bbedc832 4873 {
1ceb70f8 4874 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4875 { "sfence", { Skip_MODRM } },
4876 { "(bad)", { XX } },
bbedc832
L		 4877 { "(bad)", { XX } },
4878 { "(bad)", { XX } },
4879 { "(bad)", { XX } },
4880 { "(bad)", { XX } },
4881 { "(bad)", { XX } },
4882 { "(bad)", { XX } },
144c41d9 4883 },
b844680a
L		 4884};
4885
c608c12e
AM		 4886#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4887
252b5132 4888static void
26ca5450 4889ckprefix (void)
252b5132 4890{
52b15da3
JH		 4891 int newrex;
4892 rex = 0;
252b5132 4893 prefixes = 0;
7d421014 4894 used_prefixes = 0;
52b15da3 4895 rex_used = 0;
252b5132
RH		 4896 while (1)
4897 {
4898 FETCH_DATA (the_info, codep + 1);
52b15da3 4899 newrex = 0;
252b5132
RH		 4900 switch (*codep)
4901 {
52b15da3
JH		 4902 /* REX prefixes family. */
4903 case 0x40:
4904 case 0x41:
4905 case 0x42:
4906 case 0x43:
4907 case 0x44:
4908 case 0x45:
4909 case 0x46:
4910 case 0x47:
4911 case 0x48:
4912 case 0x49:
4913 case 0x4a:
4914 case 0x4b:
4915 case 0x4c:
4916 case 0x4d:
4917 case 0x4e:
4918 case 0x4f:
cb712a9e 4919 if (address_mode == mode_64bit)
52b15da3
JH		 4920 newrex = *codep;
4921 else
4922 return;
4923 break;
252b5132
RH		 4924 case 0xf3:
4925 prefixes |= PREFIX_REPZ;
4926 break;
4927 case 0xf2:
4928 prefixes |= PREFIX_REPNZ;
4929 break;
4930 case 0xf0:
4931 prefixes |= PREFIX_LOCK;
4932 break;
4933 case 0x2e:
4934 prefixes |= PREFIX_CS;
4935 break;
4936 case 0x36:
4937 prefixes |= PREFIX_SS;
4938 break;
4939 case 0x3e:
4940 prefixes |= PREFIX_DS;
4941 break;
4942 case 0x26:
4943 prefixes |= PREFIX_ES;
4944 break;
4945 case 0x64:
4946 prefixes |= PREFIX_FS;
4947 break;
4948 case 0x65:
4949 prefixes |= PREFIX_GS;
4950 break;
4951 case 0x66:
4952 prefixes |= PREFIX_DATA;
4953 break;
4954 case 0x67:
4955 prefixes |= PREFIX_ADDR;
4956 break;
5076851f 4957 case FWAIT_OPCODE:
252b5132
RH		 4958 /* fwait is really an instruction. If there are prefixes
4959 before the fwait, they belong to the fwait, *not* to the
4960 following instruction. */
3e7d61b2 4961 if (prefixes || rex)
252b5132
RH		 4962 {
4963 prefixes |= PREFIX_FWAIT;
4964 codep++;
4965 return;
4966 }
4967 prefixes = PREFIX_FWAIT;
4968 break;
4969 default:
4970 return;
4971 }
52b15da3
JH		 4972 /* Rex is ignored when followed by another prefix. */
4973 if (rex)
4974 {
3e7d61b2
AM		 4975 rex_used = rex;
4976 return;
52b15da3
JH		 4977 }
4978 rex = newrex;
252b5132
RH		 4979 codep++;
4980 }
4981}
4982
7d421014
ILT		 4983/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4984 prefix byte. */
4985
4986static const char *
26ca5450 4987prefix_name (int pref, int sizeflag)
7d421014 4988{
0003779b
L		 4989 static const char *rexes [16] =
4990 {
4991 "rex", /* 0x40 */
4992 "rex.B", /* 0x41 */
4993 "rex.X", /* 0x42 */
4994 "rex.XB", /* 0x43 */
4995 "rex.R", /* 0x44 */
4996 "rex.RB", /* 0x45 */
4997 "rex.RX", /* 0x46 */
4998 "rex.RXB", /* 0x47 */
4999 "rex.W", /* 0x48 */
5000 "rex.WB", /* 0x49 */
5001 "rex.WX", /* 0x4a */
5002 "rex.WXB", /* 0x4b */
5003 "rex.WR", /* 0x4c */
5004 "rex.WRB", /* 0x4d */
5005 "rex.WRX", /* 0x4e */
5006 "rex.WRXB", /* 0x4f */
5007 };
5008
7d421014
ILT		 5009 switch (pref)
5010 {
52b15da3
JH		 5011 /* REX prefixes family. */
5012 case 0x40:
52b15da3 5013 case 0x41:
52b15da3 5014 case 0x42:
52b15da3 5015 case 0x43:
52b15da3 5016 case 0x44:
52b15da3 5017 case 0x45:
52b15da3 5018 case 0x46:
52b15da3 5019 case 0x47:
52b15da3 5020 case 0x48:
52b15da3 5021 case 0x49:
52b15da3 5022 case 0x4a:
52b15da3 5023 case 0x4b:
52b15da3 5024 case 0x4c:
52b15da3 5025 case 0x4d:
52b15da3 5026 case 0x4e:
52b15da3 5027 case 0x4f:
0003779b 5028 return rexes [pref - 0x40];
7d421014
ILT		 5029 case 0xf3:
5030 return "repz";
5031 case 0xf2:
5032 return "repnz";
5033 case 0xf0:
5034 return "lock";
5035 case 0x2e:
5036 return "cs";
5037 case 0x36:
5038 return "ss";
5039 case 0x3e:
5040 return "ds";
5041 case 0x26:
5042 return "es";
5043 case 0x64:
5044 return "fs";
5045 case 0x65:
5046 return "gs";
5047 case 0x66:
5048 return (sizeflag & DFLAG) ? "data16" : "data32";
5049 case 0x67:
cb712a9e 5050 if (address_mode == mode_64bit)
db6eb5be 5051 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 5052 else
2888cb7a 5053 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 5054 case FWAIT_OPCODE:
5055 return "fwait";
5056 default:
5057 return NULL;
5058 }
5059}
5060
ce518a5f
L		 5061static char op_out[MAX_OPERANDS][100];
5062static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 5063static int two_source_ops;
ce518a5f
L		 5064static bfd_vma op_address[MAX_OPERANDS];
5065static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 5066static bfd_vma start_pc;
ce518a5f 5067
252b5132
RH		 5068/*
5069 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
5070 * (see topic "Redundant prefixes" in the "Differences from 8086"
5071 * section of the "Virtual 8086 Mode" chapter.)
5072 * 'pc' should be the address of this instruction, it will
5073 * be used to print the target address if this is a relative jump or call
5074 * The function returns the length of this instruction in bytes.
5075 */
5076
252b5132 5077static char intel_syntax;
9d141669 5078static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 5079static char open_char;
5080static char close_char;
5081static char separator_char;
5082static char scale_char;
5083
e396998b
AM		 5084/* Here for backwards compatibility. When gdb stops using
5085 print_insn_i386_att and print_insn_i386_intel these functions can
5086 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 5087int
26ca5450 5088print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5089{
5090 intel_syntax = 0;
e396998b
AM		 5091
5092 return print_insn (pc, info);
252b5132
RH		 5093}
5094
5095int
26ca5450 5096print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5097{
5098 intel_syntax = 1;
e396998b
AM		 5099
5100 return print_insn (pc, info);
252b5132
RH		 5101}
5102
e396998b 5103int
26ca5450 5104print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5105{
5106 intel_syntax = -1;
5107
5108 return print_insn (pc, info);
5109}
5110
f59a29b9
L		 5111void
5112print_i386_disassembler_options (FILE *stream)
5113{
5114 fprintf (stream, _("\n\
5115The following i386/x86-64 specific disassembler options are supported for use\n\
5116with the -M switch (multiple options should be separated by commas):\n"));
5117
5118 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5119 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5120 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5121 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5122 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 5123 fprintf (stream, _(" att-mnemonic\n"
5124 " Display instruction in AT&T mnemonic\n"));
5125 fprintf (stream, _(" intel-mnemonic\n"
5126 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 5127 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5128 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5129 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5130 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5131 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5132 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5133}
5134
b844680a
L		 5135/* Get a pointer to struct dis386 with a valid name. */
5136
5137static const struct dis386 *
8bb15339 5138get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5139{
5140 int index;
5141
5142 if (dp->name != NULL)
5143 return dp;
5144
5145 switch (dp->op[0].bytemode)
5146 {
1ceb70f8
L		 5147 case USE_REG_TABLE:
5148 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5149 break;
5150
5151 case USE_MOD_TABLE:
5152 index = modrm.mod == 0x3 ? 1 : 0;
5153 dp = &mod_table[dp->op[1].bytemode][index];
5154 break;
5155
5156 case USE_RM_TABLE:
5157 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5158 break;
5159
4e7d34a6 5160 case USE_PREFIX_TABLE:
b844680a
L		 5161 index = 0;
5162 used_prefixes |= (prefixes & PREFIX_REPZ);
5163 if (prefixes & PREFIX_REPZ)
5164 {
5165 index = 1;
5166 repz_prefix = NULL;
5167 }
5168 else
5169 {
5170 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5171 PREFIX_DATA. */
5172 used_prefixes |= (prefixes & PREFIX_REPNZ);
5173 if (prefixes & PREFIX_REPNZ)
5174 {
5175 index = 3;
5176 repnz_prefix = NULL;
5177 }
5178 else
5179 {
5180 used_prefixes |= (prefixes & PREFIX_DATA);
5181 if (prefixes & PREFIX_DATA)
5182 {
5183 index = 2;
5184 data_prefix = NULL;
5185 }
5186 }
5187 }
1ceb70f8 5188 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5189 break;
5190
4e7d34a6 5191 case USE_X86_64_TABLE:
b844680a
L		 5192 index = address_mode == mode_64bit ? 1 : 0;
5193 dp = &x86_64_table[dp->op[1].bytemode][index];
5194 break;
5195
4e7d34a6 5196 case USE_3BYTE_TABLE:
8bb15339
L		 5197 FETCH_DATA (info, codep + 2);
5198 index = *codep++;
5199 dp = &three_byte_table[dp->op[1].bytemode][index];
5200 modrm.mod = (*codep >> 6) & 3;
5201 modrm.reg = (*codep >> 3) & 7;
5202 modrm.rm = *codep & 7;
5203 break;
5204
b844680a
L		 5205 default:
5206 oappend (INTERNAL_DISASSEMBLER_ERROR);
5207 return NULL;
5208 }
5209
5210 if (dp->name != NULL)
5211 return dp;
5212 else
8bb15339 5213 return get_valid_dis386 (dp, info);
b844680a
L		 5214}
5215
e396998b 5216static int
26ca5450 5217print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5218{
2da11e11 5219 const struct dis386 *dp;
252b5132 5220 int i;
ce518a5f 5221 char *op_txt[MAX_OPERANDS];
252b5132 5222 int needcomma;
e396998b
AM		 5223 int sizeflag;
5224 const char *p;
252b5132 5225 struct dis_private priv;
eec0f4ca 5226 unsigned char op;
b844680a
L		 5227 char prefix_obuf[32];
5228 char *prefix_obufp;
252b5132 5229
cb712a9e
L		 5230 if (info->mach == bfd_mach_x86_64_intel_syntax
5231 || info->mach == bfd_mach_x86_64)
5232 address_mode = mode_64bit;
5233 else
5234 address_mode = mode_32bit;
52b15da3 5235
8373f971 5236 if (intel_syntax == (char) -1)
e396998b
AM		 5237 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5238 || info->mach == bfd_mach_x86_64_intel_syntax);
5239
2da11e11 5240 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5241 || info->mach == bfd_mach_x86_64
5242 || info->mach == bfd_mach_i386_i386_intel_syntax
5243 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5244 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5245 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5246 priv.orig_sizeflag = 0;
2da11e11
AM		 5247 else
5248 abort ();
e396998b
AM		 5249
5250 for (p = info->disassembler_options; p != NULL; )
5251 {
0112cd26 5252 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5253 {
cb712a9e 5254 address_mode = mode_64bit;
e396998b
AM		 5255 priv.orig_sizeflag = AFLAG | DFLAG;
5256 }
0112cd26 5257 else if (CONST_STRNEQ (p, "i386"))
e396998b 5258 {
cb712a9e 5259 address_mode = mode_32bit;
e396998b
AM		 5260 priv.orig_sizeflag = AFLAG | DFLAG;
5261 }
0112cd26 5262 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5263 {
cb712a9e 5264 address_mode = mode_16bit;
e396998b
AM		 5265 priv.orig_sizeflag = 0;
5266 }
0112cd26 5267 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5268 {
5269 intel_syntax = 1;
9d141669
L		 5270 if (CONST_STRNEQ (p + 5, "-mnemonic"))
5271 intel_mnemonic = 1;
e396998b 5272 }
0112cd26 5273 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5274 {
5275 intel_syntax = 0;
9d141669
L		 5276 if (CONST_STRNEQ (p + 3, "-mnemonic"))
5277 intel_mnemonic = 0;
e396998b 5278 }
0112cd26 5279 else if (CONST_STRNEQ (p, "addr"))
e396998b 5280 {
f59a29b9
L		 5281 if (address_mode == mode_64bit)
5282 {
5283 if (p[4] == '3' && p[5] == '2')
5284 priv.orig_sizeflag &= ~AFLAG;
5285 else if (p[4] == '6' && p[5] == '4')
5286 priv.orig_sizeflag |= AFLAG;
5287 }
5288 else
5289 {
5290 if (p[4] == '1' && p[5] == '6')
5291 priv.orig_sizeflag &= ~AFLAG;
5292 else if (p[4] == '3' && p[5] == '2')
5293 priv.orig_sizeflag |= AFLAG;
5294 }
e396998b 5295 }
0112cd26 5296 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5297 {
5298 if (p[4] == '1' && p[5] == '6')
5299 priv.orig_sizeflag &= ~DFLAG;
5300 else if (p[4] == '3' && p[5] == '2')
5301 priv.orig_sizeflag |= DFLAG;
5302 }
0112cd26 5303 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5304 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5305
5306 p = strchr (p, ',');
5307 if (p != NULL)
5308 p++;
5309 }
5310
5311 if (intel_syntax)
5312 {
5313 names64 = intel_names64;
5314 names32 = intel_names32;
5315 names16 = intel_names16;
5316 names8 = intel_names8;
5317 names8rex = intel_names8rex;
5318 names_seg = intel_names_seg;
db51cc60
L		 5319 index64 = intel_index64;
5320 index32 = intel_index32;
e396998b
AM		 5321 index16 = intel_index16;
5322 open_char = '[';
5323 close_char = ']';
5324 separator_char = '+';
5325 scale_char = '*';
5326 }
5327 else
5328 {
5329 names64 = att_names64;
5330 names32 = att_names32;
5331 names16 = att_names16;
5332 names8 = att_names8;
5333 names8rex = att_names8rex;
5334 names_seg = att_names_seg;
db51cc60
L		 5335 index64 = att_index64;
5336 index32 = att_index32;
e396998b
AM		 5337 index16 = att_index16;
5338 open_char = '(';
5339 close_char = ')';
5340 separator_char = ',';
5341 scale_char = ',';
5342 }
2da11e11 5343
4fe53c98 5344 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5345 puts most long word instructions on a single line. */
4fe53c98 5346 info->bytes_per_line = 7;
252b5132 5347
26ca5450 5348 info->private_data = &priv;
252b5132
RH		 5349 priv.max_fetched = priv.the_buffer;
5350 priv.insn_start = pc;
252b5132
RH		 5351
5352 obuf[0] = 0;
ce518a5f
L		 5353 for (i = 0; i < MAX_OPERANDS; ++i)
5354 {
5355 op_out[i][0] = 0;
5356 op_index[i] = -1;
5357 }
252b5132
RH		 5358
5359 the_info = info;
5360 start_pc = pc;
e396998b
AM		 5361 start_codep = priv.the_buffer;
5362 codep = priv.the_buffer;
252b5132 5363
5076851f
ILT		 5364 if (setjmp (priv.bailout) != 0)
5365 {
7d421014
ILT		 5366 const char *name;
5367
5076851f 5368 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5369 means we have an incomplete instruction of some sort. Just
5370 print the first byte as a prefix or a .byte pseudo-op. */
5371 if (codep > priv.the_buffer)
5076851f 5372 {
e396998b 5373 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5374 if (name != NULL)
5375 (*info->fprintf_func) (info->stream, "%s", name);
5376 else
5076851f 5377 {
7d421014
ILT		 5378 /* Just print the first byte as a .byte instruction. */
5379 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5380 (unsigned int) priv.the_buffer[0]);
5076851f 5381 }
5076851f 5382
7d421014 5383 return 1;
5076851f
ILT		 5384 }
5385
5386 return -1;
5387 }
5388
52b15da3 5389 obufp = obuf;
252b5132
RH		 5390 ckprefix ();
5391
5392 insn_codep = codep;
e396998b 5393 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5394
5395 FETCH_DATA (info, codep + 1);
5396 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5397
3e7d61b2
AM		 5398 if (((prefixes & PREFIX_FWAIT)
5399 && ((*codep < 0xd8) || (*codep > 0xdf)))
5400 || (rex && rex_used))
252b5132 5401 {
7d421014
ILT		 5402 const char *name;
5403
3e7d61b2
AM		 5404 /* fwait not followed by floating point instruction, or rex followed
5405 by other prefixes. Print the first prefix. */
e396998b 5406 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5407 if (name == NULL)
5408 name = INTERNAL_DISASSEMBLER_ERROR;
5409 (*info->fprintf_func) (info->stream, "%s", name);
5410 return 1;
252b5132
RH		 5411 }
5412
eec0f4ca 5413 op = 0;
252b5132
RH		 5414 if (*codep == 0x0f)
5415 {
eec0f4ca 5416 unsigned char threebyte;
252b5132 5417 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5418 threebyte = *++codep;
5419 dp = &dis386_twobyte[threebyte];
252b5132 5420 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5421 codep++;
252b5132
RH		 5422 }
5423 else
5424 {
6439fc28 5425 dp = &dis386[*codep];
252b5132 5426 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5427 codep++;
252b5132 5428 }
246c51aa 5429
b844680a 5430 if ((prefixes & PREFIX_REPZ))
7d421014 5431 {
b844680a 5432 repz_prefix = "repz ";
7d421014
ILT		 5433 used_prefixes |= PREFIX_REPZ;
5434 }
b844680a
L		 5435 else
5436 repz_prefix = NULL;
5437
5438 if ((prefixes & PREFIX_REPNZ))
7d421014 5439 {
b844680a 5440 repnz_prefix = "repnz ";
7d421014
ILT		 5441 used_prefixes |= PREFIX_REPNZ;
5442 }
b844680a
L		 5443 else
5444 repnz_prefix = NULL;
050dfa73 5445
b844680a 5446 if ((prefixes & PREFIX_LOCK))
7d421014 5447 {
b844680a 5448 lock_prefix = "lock ";
7d421014
ILT		 5449 used_prefixes |= PREFIX_LOCK;
5450 }
b844680a
L		 5451 else
5452 lock_prefix = NULL;
c608c12e 5453
b844680a 5454 addr_prefix = NULL;
c608c12e
AM		 5455 if (prefixes & PREFIX_ADDR)
5456 {
5457 sizeflag ^= AFLAG;
ce518a5f 5458 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5459 {
cb712a9e 5460 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5461 addr_prefix = "addr32 ";
3ffd33cf 5462 else
b844680a 5463 addr_prefix = "addr16 ";
3ffd33cf
AM		 5464 used_prefixes |= PREFIX_ADDR;
5465 }
5466 }
5467
b844680a
L		 5468 data_prefix = NULL;
5469 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5470 {
5471 sizeflag ^= DFLAG;
ce518a5f
L		 5472 if (dp->op[2].bytemode == cond_jump_mode
5473 && dp->op[0].bytemode == v_mode
6439fc28 5474 && !intel_syntax)
3ffd33cf
AM		 5475 {
5476 if (sizeflag & DFLAG)
b844680a 5477 data_prefix = "data32 ";
3ffd33cf 5478 else
b844680a 5479 data_prefix = "data16 ";
3ffd33cf
AM		 5480 used_prefixes |= PREFIX_DATA;
5481 }
5482 }
5483
8bb15339 5484 if (need_modrm)
252b5132
RH		 5485 {
5486 FETCH_DATA (info, codep + 1);
7967e09e
L		 5487 modrm.mod = (*codep >> 6) & 3;
5488 modrm.reg = (*codep >> 3) & 7;
5489 modrm.rm = *codep & 7;
252b5132
RH		 5490 }
5491
ce518a5f 5492 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5493 {
5494 dofloat (sizeflag);
5495 }
5496 else
5497 {
8bb15339 5498 dp = get_valid_dis386 (dp, info);
b844680a 5499 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5500 {
5501 for (i = 0; i < MAX_OPERANDS; ++i)
5502 {
246c51aa 5503 obufp = op_out[i];
ce518a5f
L		 5504 op_ad = MAX_OPERANDS - 1 - i;
5505 if (dp->op[i].rtn)
5506 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5507 }
6439fc28 5508 }
252b5132
RH		 5509 }
5510
7d421014
ILT		 5511 /* See if any prefixes were not used. If so, print the first one
5512 separately. If we don't do this, we'll wind up printing an
5513 instruction stream which does not precisely correspond to the
5514 bytes we are disassembling. */
5515 if ((prefixes & ~used_prefixes) != 0)
5516 {
5517 const char *name;
5518
e396998b 5519 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5520 if (name == NULL)
5521 name = INTERNAL_DISASSEMBLER_ERROR;
5522 (*info->fprintf_func) (info->stream, "%s", name);
5523 return 1;
5524 }
52b15da3
JH		 5525 if (rex & ~rex_used)
5526 {
5527 const char *name;
e396998b 5528 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5529 if (name == NULL)
5530 name = INTERNAL_DISASSEMBLER_ERROR;
5531 (*info->fprintf_func) (info->stream, "%s ", name);
5532 }
7d421014 5533
b844680a
L		 5534 prefix_obuf[0] = 0;
5535 prefix_obufp = prefix_obuf;
5536 if (lock_prefix)
5537 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5538 if (repz_prefix)
5539 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5540 if (repnz_prefix)
5541 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5542 if (addr_prefix)
5543 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5544 if (data_prefix)
5545 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5546
5547 if (prefix_obuf[0] != 0)
5548 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5549
252b5132 5550 obufp = obuf + strlen (obuf);
b844680a 5551 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5552 oappend (" ");
5553 oappend (" ");
5554 (*info->fprintf_func) (info->stream, "%s", obuf);
5555
5556 /* The enter and bound instructions are printed with operands in the same
5557 order as the intel book; everything else is printed in reverse order. */
2da11e11 5558 if (intel_syntax || two_source_ops)
252b5132 5559 {
185b1163
L		 5560 bfd_vma riprel;
5561
ce518a5f
L		 5562 for (i = 0; i < MAX_OPERANDS; ++i)
5563 op_txt[i] = op_out[i];
246c51aa 5564
ce518a5f
L		 5565 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5566 {
5567 op_ad = op_index[i];
5568 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5569 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5570 riprel = op_riprel[i];
5571 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5572 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5573 }
252b5132
RH		 5574 }
5575 else
5576 {
ce518a5f
L		 5577 for (i = 0; i < MAX_OPERANDS; ++i)
5578 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5579 }
5580
ce518a5f
L		 5581 needcomma = 0;
5582 for (i = 0; i < MAX_OPERANDS; ++i)
5583 if (*op_txt[i])
5584 {
5585 if (needcomma)
5586 (*info->fprintf_func) (info->stream, ",");
5587 if (op_index[i] != -1 && !op_riprel[i])
5588 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5589 else
5590 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5591 needcomma = 1;
5592 }
050dfa73 5593
ce518a5f 5594 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5595 if (op_index[i] != -1 && op_riprel[i])
5596 {
5597 (*info->fprintf_func) (info->stream, " # ");
5598 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5599 + op_address[op_index[i]]), info);
185b1163 5600 break;
52b15da3 5601 }
e396998b 5602 return codep - priv.the_buffer;
252b5132
RH		 5603}
5604
6439fc28 5605static const char *float_mem[] = {
252b5132 5606 /* d8 */
7c52e0e8
L		 5607 "fadd{s|}",
5608 "fmul{s|}",
5609 "fcom{s|}",
5610 "fcomp{s|}",
5611 "fsub{s|}",
5612 "fsubr{s|}",
5613 "fdiv{s|}",
5614 "fdivr{s|}",
db6eb5be 5615 /* d9 */
7c52e0e8 5616 "fld{s|}",
252b5132 5617 "(bad)",
7c52e0e8
L		 5618 "fst{s|}",
5619 "fstp{s|}",
9306ca4a 5620 "fldenvIC",
252b5132 5621 "fldcw",
9306ca4a 5622 "fNstenvIC",
252b5132
RH		 5623 "fNstcw",
5624 /* da */
7c52e0e8
L		 5625 "fiadd{l|}",
5626 "fimul{l|}",
5627 "ficom{l|}",
5628 "ficomp{l|}",
5629 "fisub{l|}",
5630 "fisubr{l|}",
5631 "fidiv{l|}",
5632 "fidivr{l|}",
252b5132 5633 /* db */
7c52e0e8
L		 5634 "fild{l|}",
5635 "fisttp{l|}",
5636 "fist{l|}",
5637 "fistp{l|}",
252b5132 5638 "(bad)",
6439fc28 5639 "fld{t||t|}",
252b5132 5640 "(bad)",
6439fc28 5641 "fstp{t||t|}",
252b5132 5642 /* dc */
7c52e0e8
L		 5643 "fadd{l|}",
5644 "fmul{l|}",
5645 "fcom{l|}",
5646 "fcomp{l|}",
5647 "fsub{l|}",
5648 "fsubr{l|}",
5649 "fdiv{l|}",
5650 "fdivr{l|}",
252b5132 5651 /* dd */
7c52e0e8
L		 5652 "fld{l|}",
5653 "fisttp{ll|}",
5654 "fst{l||}",
5655 "fstp{l|}",
9306ca4a 5656 "frstorIC",
252b5132 5657 "(bad)",
9306ca4a 5658 "fNsaveIC",
252b5132
RH		 5659 "fNstsw",
5660 /* de */
5661 "fiadd",
5662 "fimul",
5663 "ficom",
5664 "ficomp",
5665 "fisub",
5666 "fisubr",
5667 "fidiv",
5668 "fidivr",
5669 /* df */
5670 "fild",
ca164297 5671 "fisttp",
252b5132
RH		 5672 "fist",
5673 "fistp",
5674 "fbld",
7c52e0e8 5675 "fild{ll|}",
252b5132 5676 "fbstp",
7c52e0e8 5677 "fistp{ll|}",
1d9f512f
AM		 5678};
5679
5680static const unsigned char float_mem_mode[] = {
5681 /* d8 */
5682 d_mode,
5683 d_mode,
5684 d_mode,
5685 d_mode,
5686 d_mode,
5687 d_mode,
5688 d_mode,
5689 d_mode,
5690 /* d9 */
5691 d_mode,
5692 0,
5693 d_mode,
5694 d_mode,
5695 0,
5696 w_mode,
5697 0,
5698 w_mode,
5699 /* da */
5700 d_mode,
5701 d_mode,
5702 d_mode,
5703 d_mode,
5704 d_mode,
5705 d_mode,
5706 d_mode,
5707 d_mode,
5708 /* db */
5709 d_mode,
5710 d_mode,
5711 d_mode,
5712 d_mode,
5713 0,
9306ca4a 5714 t_mode,
1d9f512f 5715 0,
9306ca4a 5716 t_mode,
1d9f512f
AM		 5717 /* dc */
5718 q_mode,
5719 q_mode,
5720 q_mode,
5721 q_mode,
5722 q_mode,
5723 q_mode,
5724 q_mode,
5725 q_mode,
5726 /* dd */
5727 q_mode,
5728 q_mode,
5729 q_mode,
5730 q_mode,
5731 0,
5732 0,
5733 0,
5734 w_mode,
5735 /* de */
5736 w_mode,
5737 w_mode,
5738 w_mode,
5739 w_mode,
5740 w_mode,
5741 w_mode,
5742 w_mode,
5743 w_mode,
5744 /* df */
5745 w_mode,
5746 w_mode,
5747 w_mode,
5748 w_mode,
9306ca4a 5749 t_mode,
1d9f512f 5750 q_mode,
9306ca4a 5751 t_mode,
1d9f512f 5752 q_mode
252b5132
RH		 5753};
5754
ce518a5f
L		 5755#define ST { OP_ST, 0 }
5756#define STi { OP_STi, 0 }
252b5132 5757
4efba78c
L		 5758#define FGRPd9_2 NULL, { { NULL, 0 } }
5759#define FGRPd9_4 NULL, { { NULL, 1 } }
5760#define FGRPd9_5 NULL, { { NULL, 2 } }
5761#define FGRPd9_6 NULL, { { NULL, 3 } }
5762#define FGRPd9_7 NULL, { { NULL, 4 } }
5763#define FGRPda_5 NULL, { { NULL, 5 } }
5764#define FGRPdb_4 NULL, { { NULL, 6 } }
5765#define FGRPde_3 NULL, { { NULL, 7 } }
5766#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5767
2da11e11 5768static const struct dis386 float_reg[][8] = {
252b5132
RH		 5769 /* d8 */
5770 {
ce518a5f
L		 5771 { "fadd", { ST, STi } },
5772 { "fmul", { ST, STi } },
5773 { "fcom", { STi } },
5774 { "fcomp", { STi } },
5775 { "fsub", { ST, STi } },
5776 { "fsubr", { ST, STi } },
5777 { "fdiv", { ST, STi } },
5778 { "fdivr", { ST, STi } },
252b5132
RH		 5779 },
5780 /* d9 */
5781 {
ce518a5f
L		 5782 { "fld", { STi } },
5783 { "fxch", { STi } },
252b5132 5784 { FGRPd9_2 },
ce518a5f 5785 { "(bad)", { XX } },
252b5132
RH		 5786 { FGRPd9_4 },
5787 { FGRPd9_5 },
5788 { FGRPd9_6 },
5789 { FGRPd9_7 },
5790 },
5791 /* da */
5792 {
ce518a5f
L		 5793 { "fcmovb", { ST, STi } },
5794 { "fcmove", { ST, STi } },
5795 { "fcmovbe",{ ST, STi } },
5796 { "fcmovu", { ST, STi } },
5797 { "(bad)", { XX } },
252b5132 5798 { FGRPda_5 },
ce518a5f
L		 5799 { "(bad)", { XX } },
5800 { "(bad)", { XX } },
252b5132
RH		 5801 },
5802 /* db */
5803 {
ce518a5f
L		 5804 { "fcmovnb",{ ST, STi } },
5805 { "fcmovne",{ ST, STi } },
5806 { "fcmovnbe",{ ST, STi } },
5807 { "fcmovnu",{ ST, STi } },
252b5132 5808 { FGRPdb_4 },
ce518a5f
L		 5809 { "fucomi", { ST, STi } },
5810 { "fcomi", { ST, STi } },
5811 { "(bad)", { XX } },
252b5132
RH		 5812 },
5813 /* dc */
5814 {
ce518a5f
L		 5815 { "fadd", { STi, ST } },
5816 { "fmul", { STi, ST } },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
9d141669
L		 5819 { "fsub!M", { STi, ST } },
5820 { "fsubM", { STi, ST } },
5821 { "fdiv!M", { STi, ST } },
5822 { "fdivM", { STi, ST } },
252b5132
RH		 5823 },
5824 /* dd */
5825 {
ce518a5f
L		 5826 { "ffree", { STi } },
5827 { "(bad)", { XX } },
5828 { "fst", { STi } },
5829 { "fstp", { STi } },
5830 { "fucom", { STi } },
5831 { "fucomp", { STi } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
252b5132
RH		 5834 },
5835 /* de */
5836 {
ce518a5f
L		 5837 { "faddp", { STi, ST } },
5838 { "fmulp", { STi, ST } },
5839 { "(bad)", { XX } },
252b5132 5840 { FGRPde_3 },
9d141669
L		 5841 { "fsub!Mp", { STi, ST } },
5842 { "fsubMp", { STi, ST } },
5843 { "fdiv!Mp", { STi, ST } },
5844 { "fdivMp", { STi, ST } },
252b5132
RH		 5845 },
5846 /* df */
5847 {
ce518a5f
L		 5848 { "ffreep", { STi } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
252b5132 5852 { FGRPdf_4 },
ce518a5f
L		 5853 { "fucomip", { ST, STi } },
5854 { "fcomip", { ST, STi } },
5855 { "(bad)", { XX } },
252b5132
RH		 5856 },
5857};
5858
252b5132
RH		 5859static char *fgrps[][8] = {
5860 /* d9_2 0 */
5861 {
5862 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5863 },
5864
5865 /* d9_4 1 */
5866 {
5867 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5868 },
5869
5870 /* d9_5 2 */
5871 {
5872 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5873 },
5874
5875 /* d9_6 3 */
5876 {
5877 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5878 },
5879
5880 /* d9_7 4 */
5881 {
5882 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5883 },
5884
5885 /* da_5 5 */
5886 {
5887 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5888 },
5889
5890 /* db_4 6 */
5891 {
5892 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5893 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5894 },
5895
5896 /* de_3 7 */
5897 {
5898 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5899 },
5900
5901 /* df_4 8 */
5902 {
5903 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5904 },
5905};
5906
b844680a
L		 5907static void
5908OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5909 int sizeflag ATTRIBUTE_UNUSED)
5910{
5911 /* Skip mod/rm byte. */
5912 MODRM_CHECK;
5913 codep++;
5914}
5915
252b5132 5916static void
26ca5450 5917dofloat (int sizeflag)
252b5132 5918{
2da11e11 5919 const struct dis386 *dp;
252b5132
RH		 5920 unsigned char floatop;
5921
5922 floatop = codep[-1];
5923
7967e09e 5924 if (modrm.mod != 3)
252b5132 5925 {
7967e09e 5926 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5927
5928 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5929 obufp = op_out[0];
6e50d963 5930 op_ad = 2;
1d9f512f 5931 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5932 return;
5933 }
6608db57 5934 /* Skip mod/rm byte. */
4bba6815 5935 MODRM_CHECK;
252b5132
RH		 5936 codep++;
5937
7967e09e 5938 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5939 if (dp->name == NULL)
5940 {
7967e09e 5941 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5942
6608db57 5943 /* Instruction fnstsw is only one with strange arg. */
252b5132 5944 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5945 strcpy (op_out[0], names16[0]);
252b5132
RH		 5946 }
5947 else
5948 {
5949 putop (dp->name, sizeflag);
5950
ce518a5f 5951 obufp = op_out[0];
6e50d963 5952 op_ad = 2;
ce518a5f
L		 5953 if (dp->op[0].rtn)
5954 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5955
ce518a5f 5956 obufp = op_out[1];
6e50d963 5957 op_ad = 1;
ce518a5f
L		 5958 if (dp->op[1].rtn)
5959 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5960 }
5961}
5962
252b5132 5963static void
26ca5450 5964OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5965{
422673a9 5966 oappend ("%st" + intel_syntax);
252b5132
RH		 5967}
5968
252b5132 5969static void
26ca5450 5970OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5971{
7967e09e 5972 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5973 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5974}
5975
6608db57 5976/* Capital letters in template are macros. */
6439fc28 5977static int
26ca5450 5978putop (const char *template, int sizeflag)
252b5132 5979{
2da11e11 5980 const char *p;
9306ca4a 5981 int alt = 0;
9d141669 5982 int cond = 1;
98b528ac
L		 5983 unsigned int l = 0, len = 1;
5984 char last[4];
5985
5986#define SAVE_LAST(c) \
5987 if (l < len && l < sizeof (last)) \
5988 last[l++] = c; \
5989 else \
5990 abort ();
252b5132
RH		 5991
5992 for (p = template; *p; p++)
5993 {
5994 switch (*p)
5995 {
5996 default:
5997 *obufp++ = *p;
5998 break;
98b528ac
L		 5999 case '%':
6000 len++;
6001 break;
9d141669
L		 6002 case '!':
6003 cond = 0;
6004 break;
6439fc28
AM		 6005 case '{':
6006 alt = 0;
6007 if (intel_syntax)
6439fc28
AM		 6008 {
6009 while (*++p != '|')
7c52e0e8
L		 6010 if (*p == '}' || *p == '\0')
6011 abort ();
6439fc28 6012 }
9306ca4a
JB		 6013 /* Fall through. */
6014 case 'I':
6015 alt = 1;
6016 continue;
6439fc28
AM		 6017 case '|':
6018 while (*++p != '}')
6019 {
6020 if (*p == '\0')
6021 abort ();
6022 }
6023 break;
6024 case '}':
6025 break;
252b5132 6026 case 'A':
db6eb5be
AM		 6027 if (intel_syntax)
6028 break;
7967e09e 6029 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 6030 *obufp++ = 'b';
6031 break;
6032 case 'B':
db6eb5be
AM		 6033 if (intel_syntax)
6034 break;
252b5132
RH		 6035 if (sizeflag & SUFFIX_ALWAYS)
6036 *obufp++ = 'b';
252b5132 6037 break;
9306ca4a
JB		 6038 case 'C':
6039 if (intel_syntax && !alt)
6040 break;
6041 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
6042 {
6043 if (sizeflag & DFLAG)
6044 *obufp++ = intel_syntax ? 'd' : 'l';
6045 else
6046 *obufp++ = intel_syntax ? 'w' : 's';
6047 used_prefixes |= (prefixes & PREFIX_DATA);
6048 }
6049 break;
ed7841b3
JB		 6050 case 'D':
6051 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6052 break;
161a04f6 6053 USED_REX (REX_W);
7967e09e 6054 if (modrm.mod == 3)
ed7841b3 6055 {
161a04f6 6056 if (rex & REX_W)
ed7841b3
JB		 6057 *obufp++ = 'q';
6058 else if (sizeflag & DFLAG)
6059 *obufp++ = intel_syntax ? 'd' : 'l';
6060 else
6061 *obufp++ = 'w';
6062 used_prefixes |= (prefixes & PREFIX_DATA);
6063 }
6064 else
6065 *obufp++ = 'w';
6066 break;
252b5132 6067 case 'E': /* For jcxz/jecxz */
cb712a9e 6068 if (address_mode == mode_64bit)
c1a64871
JH		 6069 {
6070 if (sizeflag & AFLAG)
6071 *obufp++ = 'r';
6072 else
6073 *obufp++ = 'e';
6074 }
6075 else
6076 if (sizeflag & AFLAG)
6077 *obufp++ = 'e';
3ffd33cf
AM		 6078 used_prefixes |= (prefixes & PREFIX_ADDR);
6079 break;
6080 case 'F':
db6eb5be
AM		 6081 if (intel_syntax)
6082 break;
e396998b 6083 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 6084 {
6085 if (sizeflag & AFLAG)
cb712a9e 6086 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 6087 else
cb712a9e 6088 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 6089 used_prefixes |= (prefixes & PREFIX_ADDR);
6090 }
252b5132 6091 break;
52fd6d94
JB		 6092 case 'G':
6093 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
6094 break;
161a04f6 6095 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6096 *obufp++ = 'l';
6097 else
6098 *obufp++ = 'w';
161a04f6 6099 if (!(rex & REX_W))
52fd6d94
JB		 6100 used_prefixes |= (prefixes & PREFIX_DATA);
6101 break;
5dd0794d 6102 case 'H':
db6eb5be
AM		 6103 if (intel_syntax)
6104 break;
5dd0794d
AM		 6105 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6106 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6107 {
6108 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6109 *obufp++ = ',';
6110 *obufp++ = 'p';
6111 if (prefixes & PREFIX_DS)
6112 *obufp++ = 't';
6113 else
6114 *obufp++ = 'n';
6115 }
6116 break;
9306ca4a
JB		 6117 case 'J':
6118 if (intel_syntax)
6119 break;
6120 *obufp++ = 'l';
6121 break;
42903f7f
L		 6122 case 'K':
6123 USED_REX (REX_W);
6124 if (rex & REX_W)
6125 *obufp++ = 'q';
6126 else
6127 *obufp++ = 'd';
6128 break;
6dd5059a
L		 6129 case 'Z':
6130 if (intel_syntax)
6131 break;
6132 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6133 {
6134 *obufp++ = 'q';
6135 break;
6136 }
6137 /* Fall through. */
98b528ac 6138 goto case_L;
252b5132 6139 case 'L':
98b528ac
L		 6140 if (l != 0 || len != 1)
6141 {
6142 SAVE_LAST (*p);
6143 break;
6144 }
6145case_L:
db6eb5be
AM		 6146 if (intel_syntax)
6147 break;
252b5132
RH		 6148 if (sizeflag & SUFFIX_ALWAYS)
6149 *obufp++ = 'l';
252b5132 6150 break;
9d141669
L		 6151 case 'M':
6152 if (intel_mnemonic != cond)
6153 *obufp++ = 'r';
6154 break;
252b5132
RH		 6155 case 'N':
6156 if ((prefixes & PREFIX_FWAIT) == 0)
6157 *obufp++ = 'n';
7d421014
ILT		 6158 else
6159 used_prefixes |= PREFIX_FWAIT;
252b5132 6160 break;
52b15da3 6161 case 'O':
161a04f6
L		 6162 USED_REX (REX_W);
6163 if (rex & REX_W)
6439fc28 6164 *obufp++ = 'o';
a35ca55a
JB		 6165 else if (intel_syntax && (sizeflag & DFLAG))
6166 *obufp++ = 'q';
52b15da3
JH		 6167 else
6168 *obufp++ = 'd';
161a04f6 6169 if (!(rex & REX_W))
a35ca55a 6170 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6171 break;
6439fc28 6172 case 'T':
db6eb5be
AM		 6173 if (intel_syntax)
6174 break;
cb712a9e 6175 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6176 {
6177 *obufp++ = 'q';
6178 break;
6179 }
6608db57 6180 /* Fall through. */
252b5132 6181 case 'P':
db6eb5be
AM		 6182 if (intel_syntax)
6183 break;
252b5132 6184 if ((prefixes & PREFIX_DATA)
161a04f6 6185 || (rex & REX_W)
e396998b 6186 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6187 {
161a04f6
L		 6188 USED_REX (REX_W);
6189 if (rex & REX_W)
52b15da3 6190 *obufp++ = 'q';
c2419411 6191 else
52b15da3
JH		 6192 {
6193 if (sizeflag & DFLAG)
6194 *obufp++ = 'l';
6195 else
6196 *obufp++ = 'w';
52b15da3 6197 }
1a114b12 6198 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6199 }
6200 break;
6439fc28 6201 case 'U':
db6eb5be
AM		 6202 if (intel_syntax)
6203 break;
cb712a9e 6204 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6205 {
7967e09e 6206 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6207 *obufp++ = 'q';
6439fc28
AM		 6208 break;
6209 }
6608db57 6210 /* Fall through. */
98b528ac 6211 goto case_Q;
252b5132 6212 case 'Q':
98b528ac 6213 if (l == 0 && len == 1)
252b5132 6214 {
98b528ac
L		 6215case_Q:
6216 if (intel_syntax && !alt)
6217 break;
6218 USED_REX (REX_W);
6219 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 6220 {
98b528ac
L		 6221 if (rex & REX_W)
6222 *obufp++ = 'q';
52b15da3 6223 else
98b528ac
L		 6224 {
6225 if (sizeflag & DFLAG)
6226 *obufp++ = intel_syntax ? 'd' : 'l';
6227 else
6228 *obufp++ = 'w';
6229 }
6230 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6231 }
98b528ac
L		 6232 }
6233 else
6234 {
6235 if (l != 1 || len != 2 || last[0] != 'L')
6236 {
6237 SAVE_LAST (*p);
6238 break;
6239 }
6240 if (intel_syntax
6241 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
6242 break;
6243 if ((rex & REX_W))
6244 {
6245 USED_REX (REX_W);
6246 *obufp++ = 'q';
6247 }
6248 else
6249 *obufp++ = 'l';
252b5132
RH		 6250 }
6251 break;
6252 case 'R':
161a04f6
L		 6253 USED_REX (REX_W);
6254 if (rex & REX_W)
a35ca55a
JB		 6255 *obufp++ = 'q';
6256 else if (sizeflag & DFLAG)
c608c12e 6257 {
a35ca55a 6258 if (intel_syntax)
c608c12e 6259 *obufp++ = 'd';
c608c12e 6260 else
a35ca55a 6261 *obufp++ = 'l';
c608c12e 6262 }
252b5132 6263 else
a35ca55a
JB		 6264 *obufp++ = 'w';
6265 if (intel_syntax && !p[1]
161a04f6 6266 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6267 *obufp++ = 'e';
161a04f6 6268 if (!(rex & REX_W))
52b15da3 6269 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6270 break;
1a114b12
JB		 6271 case 'V':
6272 if (intel_syntax)
6273 break;
cb712a9e 6274 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6275 {
6276 if (sizeflag & SUFFIX_ALWAYS)
6277 *obufp++ = 'q';
6278 break;
6279 }
6280 /* Fall through. */
252b5132 6281 case 'S':
db6eb5be
AM		 6282 if (intel_syntax)
6283 break;
252b5132
RH		 6284 if (sizeflag & SUFFIX_ALWAYS)
6285 {
161a04f6 6286 if (rex & REX_W)
52b15da3 6287 *obufp++ = 'q';
252b5132 6288 else
52b15da3
JH		 6289 {
6290 if (sizeflag & DFLAG)
6291 *obufp++ = 'l';
6292 else
6293 *obufp++ = 'w';
6294 used_prefixes |= (prefixes & PREFIX_DATA);
6295 }
252b5132 6296 }
252b5132 6297 break;
041bd2e0
JH		 6298 case 'X':
6299 if (prefixes & PREFIX_DATA)
6300 *obufp++ = 'd';
6301 else
6302 *obufp++ = 's';
db6eb5be 6303 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6304 break;
76f227a5 6305 case 'Y':
8a72226a 6306 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
db6eb5be 6307 break;
161a04f6 6308 if (rex & REX_W)
76f227a5 6309 {
161a04f6 6310 USED_REX (REX_W);
76f227a5
JH		 6311 *obufp++ = 'q';
6312 }
6313 break;
52b15da3 6314 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6315 case 'W':
252b5132 6316 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6317 USED_REX (REX_W);
6318 if (rex & REX_W)
a35ca55a
JB		 6319 {
6320 if (intel_syntax)
6321 *obufp++ = 'd';
6322 else
6323 *obufp++ = 'l';
6324 }
52b15da3 6325 else if (sizeflag & DFLAG)
252b5132
RH		 6326 *obufp++ = 'w';
6327 else
6328 *obufp++ = 'b';
161a04f6 6329 if (!(rex & REX_W))
52b15da3 6330 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6331 break;
6332 }
9306ca4a 6333 alt = 0;
252b5132
RH		 6334 }
6335 *obufp = 0;
6439fc28 6336 return 0;
252b5132
RH		 6337}
6338
6339static void
26ca5450 6340oappend (const char *s)
252b5132
RH		 6341{
6342 strcpy (obufp, s);
6343 obufp += strlen (s);
6344}
6345
6346static void
26ca5450 6347append_seg (void)
252b5132
RH		 6348{
6349 if (prefixes & PREFIX_CS)
7d421014 6350 {
7d421014 6351 used_prefixes |= PREFIX_CS;
d708bcba 6352 oappend ("%cs:" + intel_syntax);
7d421014 6353 }
252b5132 6354 if (prefixes & PREFIX_DS)
7d421014 6355 {
7d421014 6356 used_prefixes |= PREFIX_DS;
d708bcba 6357 oappend ("%ds:" + intel_syntax);
7d421014 6358 }
252b5132 6359 if (prefixes & PREFIX_SS)
7d421014 6360 {
7d421014 6361 used_prefixes |= PREFIX_SS;
d708bcba 6362 oappend ("%ss:" + intel_syntax);
7d421014 6363 }
252b5132 6364 if (prefixes & PREFIX_ES)
7d421014 6365 {
7d421014 6366 used_prefixes |= PREFIX_ES;
d708bcba 6367 oappend ("%es:" + intel_syntax);
7d421014 6368 }
252b5132 6369 if (prefixes & PREFIX_FS)
7d421014 6370 {
7d421014 6371 used_prefixes |= PREFIX_FS;
d708bcba 6372 oappend ("%fs:" + intel_syntax);
7d421014 6373 }
252b5132 6374 if (prefixes & PREFIX_GS)
7d421014 6375 {
7d421014 6376 used_prefixes |= PREFIX_GS;
d708bcba 6377 oappend ("%gs:" + intel_syntax);
7d421014 6378 }
252b5132
RH		 6379}
6380
6381static void
26ca5450 6382OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6383{
6384 if (!intel_syntax)
6385 oappend ("*");
6386 OP_E (bytemode, sizeflag);
6387}
6388
52b15da3 6389static void
26ca5450 6390print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6391{
cb712a9e 6392 if (address_mode == mode_64bit)
52b15da3
JH		 6393 {
6394 if (hex)
6395 {
6396 char tmp[30];
6397 int i;
6398 buf[0] = '0';
6399 buf[1] = 'x';
6400 sprintf_vma (tmp, disp);
6608db57 6401 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6402 strcpy (buf + 2, tmp + i);
6403 }
6404 else
6405 {
6406 bfd_signed_vma v = disp;
6407 char tmp[30];
6408 int i;
6409 if (v < 0)
6410 {
6411 *(buf++) = '-';
6412 v = -disp;
6608db57 6413 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6414 if (v < 0)
6415 {
6416 strcpy (buf, "9223372036854775808");
6417 return;
6418 }
6419 }
6420 if (!v)
6421 {
6422 strcpy (buf, "0");
6423 return;
6424 }
6425
6426 i = 0;
6427 tmp[29] = 0;
6428 while (v)
6429 {
6608db57 6430 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6431 v /= 10;
6432 i++;
6433 }
6434 strcpy (buf, tmp + 29 - i);
6435 }
6436 }
6437 else
6438 {
6439 if (hex)
6440 sprintf (buf, "0x%x", (unsigned int) disp);
6441 else
6442 sprintf (buf, "%d", (int) disp);
6443 }
6444}
6445
5d669648
L		 6446/* Put DISP in BUF as signed hex number. */
6447
6448static void
6449print_displacement (char *buf, bfd_vma disp)
6450{
6451 bfd_signed_vma val = disp;
6452 char tmp[30];
6453 int i, j = 0;
6454
6455 if (val < 0)
6456 {
6457 buf[j++] = '-';
6458 val = -disp;
6459
6460 /* Check for possible overflow. */
6461 if (val < 0)
6462 {
6463 switch (address_mode)
6464 {
6465 case mode_64bit:
6466 strcpy (buf + j, "0x8000000000000000");
6467 break;
6468 case mode_32bit:
6469 strcpy (buf + j, "0x80000000");
6470 break;
6471 case mode_16bit:
6472 strcpy (buf + j, "0x8000");
6473 break;
6474 }
6475 return;
6476 }
6477 }
6478
6479 buf[j++] = '0';
6480 buf[j++] = 'x';
6481
6482 sprintf_vma (tmp, val);
6483 for (i = 0; tmp[i] == '0'; i++)
6484 continue;
6485 if (tmp[i] == '\0')
6486 i--;
6487 strcpy (buf + j, tmp + i);
6488}
6489
3f31e633
JB		 6490static void
6491intel_operand_size (int bytemode, int sizeflag)
6492{
6493 switch (bytemode)
6494 {
6495 case b_mode:
42903f7f 6496 case dqb_mode:
3f31e633
JB		 6497 oappend ("BYTE PTR ");
6498 break;
6499 case w_mode:
6500 case dqw_mode:
6501 oappend ("WORD PTR ");
6502 break;
1a114b12 6503 case stack_v_mode:
cb712a9e 6504 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6505 {
6506 oappend ("QWORD PTR ");
6507 used_prefixes |= (prefixes & PREFIX_DATA);
6508 break;
6509 }
6510 /* FALLTHRU */
6511 case v_mode:
6512 case dq_mode:
161a04f6
L		 6513 USED_REX (REX_W);
6514 if (rex & REX_W)
3f31e633
JB		 6515 oappend ("QWORD PTR ");
6516 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6517 oappend ("DWORD PTR ");
6518 else
6519 oappend ("WORD PTR ");
6520 used_prefixes |= (prefixes & PREFIX_DATA);
6521 break;
52fd6d94 6522 case z_mode:
161a04f6 6523 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6524 *obufp++ = 'D';
6525 oappend ("WORD PTR ");
161a04f6 6526 if (!(rex & REX_W))
52fd6d94
JB		 6527 used_prefixes |= (prefixes & PREFIX_DATA);
6528 break;
3f31e633 6529 case d_mode:
42903f7f 6530 case dqd_mode:
3f31e633
JB		 6531 oappend ("DWORD PTR ");
6532 break;
6533 case q_mode:
6534 oappend ("QWORD PTR ");
6535 break;
6536 case m_mode:
cb712a9e 6537 if (address_mode == mode_64bit)
3f31e633
JB		 6538 oappend ("QWORD PTR ");
6539 else
6540 oappend ("DWORD PTR ");
6541 break;
6542 case f_mode:
6543 if (sizeflag & DFLAG)
6544 oappend ("FWORD PTR ");
6545 else
6546 oappend ("DWORD PTR ");
6547 used_prefixes |= (prefixes & PREFIX_DATA);
6548 break;
6549 case t_mode:
6550 oappend ("TBYTE PTR ");
6551 break;
6552 case x_mode:
6553 oappend ("XMMWORD PTR ");
6554 break;
fb9c77c7
L		 6555 case o_mode:
6556 oappend ("OWORD PTR ");
6557 break;
3f31e633
JB		 6558 default:
6559 break;
6560 }
6561}
6562
252b5132 6563static void
85f10a01 6564OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6565{
52b15da3
JH		 6566 bfd_vma disp;
6567 int add = 0;
6568 int riprel = 0;
161a04f6
L		 6569 USED_REX (REX_B);
6570 if (rex & REX_B)
52b15da3 6571 add += 8;
252b5132 6572
6608db57 6573 /* Skip mod/rm byte. */
4bba6815 6574 MODRM_CHECK;
252b5132
RH		 6575 codep++;
6576
7967e09e 6577 if (modrm.mod == 3)
252b5132
RH		 6578 {
6579 switch (bytemode)
6580 {
6581 case b_mode:
52b15da3
JH		 6582 USED_REX (0);
6583 if (rex)
7967e09e 6584 oappend (names8rex[modrm.rm + add]);
52b15da3 6585 else
7967e09e 6586 oappend (names8[modrm.rm + add]);
252b5132
RH		 6587 break;
6588 case w_mode:
7967e09e 6589 oappend (names16[modrm.rm + add]);
252b5132 6590 break;
2da11e11 6591 case d_mode:
7967e09e 6592 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6593 break;
6594 case q_mode:
7967e09e 6595 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6596 break;
6597 case m_mode:
cb712a9e 6598 if (address_mode == mode_64bit)
7967e09e 6599 oappend (names64[modrm.rm + add]);
52b15da3 6600 else
7967e09e 6601 oappend (names32[modrm.rm + add]);
2da11e11 6602 break;
1a114b12 6603 case stack_v_mode:
cb712a9e 6604 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6605 {
7967e09e 6606 oappend (names64[modrm.rm + add]);
003519a7 6607 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6608 break;
003519a7 6609 }
1a114b12
JB		 6610 bytemode = v_mode;
6611 /* FALLTHRU */
252b5132 6612 case v_mode:
db6eb5be 6613 case dq_mode:
42903f7f
L		 6614 case dqb_mode:
6615 case dqd_mode:
9306ca4a 6616 case dqw_mode:
161a04f6
L		 6617 USED_REX (REX_W);
6618 if (rex & REX_W)
7967e09e 6619 oappend (names64[modrm.rm + add]);
9306ca4a 6620 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6621 oappend (names32[modrm.rm + add]);
252b5132 6622 else
7967e09e 6623 oappend (names16[modrm.rm + add]);
7d421014 6624 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6625 break;
2da11e11 6626 case 0:
c608c12e 6627 break;
252b5132 6628 default:
c608c12e 6629 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6630 break;
6631 }
6632 return;
6633 }
6634
6635 disp = 0;
3f31e633
JB		 6636 if (intel_syntax)
6637 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6638 append_seg ();
6639
5d669648 6640 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6641 {
5d669648
L		 6642 /* 32/64 bit address mode */
6643 int havedisp;
252b5132
RH		 6644 int havesib;
6645 int havebase;
0f7da397 6646 int haveindex;
20afcfb7 6647 int needindex;
252b5132
RH		 6648 int base;
6649 int index = 0;
6650 int scale = 0;
6651
6652 havesib = 0;
6653 havebase = 1;
0f7da397 6654 haveindex = 0;
7967e09e 6655 base = modrm.rm;
252b5132
RH		 6656
6657 if (base == 4)
6658 {
6659 havesib = 1;
6660 FETCH_DATA (the_info, codep + 1);
252b5132 6661 index = (*codep >> 3) & 7;
db51cc60 6662 scale = (*codep >> 6) & 3;
252b5132 6663 base = *codep & 7;
161a04f6
L		 6664 USED_REX (REX_X);
6665 if (rex & REX_X)
52b15da3 6666 index += 8;
0f7da397 6667 haveindex = index != 4;
252b5132
RH		 6668 codep++;
6669 }
2888cb7a 6670 base += add;
252b5132 6671
85f10a01
MM		 6672 /* If we have a DREX byte, skip it now
6673 (it has already been handled) */
6674 if (has_drex)
6675 {
6676 FETCH_DATA (the_info, codep + 1);
6677 codep++;
6678 }
6679
7967e09e 6680 switch (modrm.mod)
252b5132
RH		 6681 {
6682 case 0:
52b15da3 6683 if ((base & 7) == 5)
252b5132
RH		 6684 {
6685 havebase = 0;
cb712a9e 6686 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6687 riprel = 1;
6688 disp = get32s ();
252b5132
RH		 6689 }
6690 break;
6691 case 1:
6692 FETCH_DATA (the_info, codep + 1);
6693 disp = *codep++;
6694 if ((disp & 0x80) != 0)
6695 disp -= 0x100;
6696 break;
6697 case 2:
52b15da3 6698 disp = get32s ();
252b5132
RH		 6699 break;
6700 }
6701
20afcfb7
L		 6702 /* In 32bit mode, we need index register to tell [offset] from
6703 [eiz*1 + offset]. */
6704 needindex = (havesib
6705 && !havebase
6706 && !haveindex
6707 && address_mode == mode_32bit);
6708 havedisp = (havebase
6709 || needindex
6710 || (havesib && (haveindex || scale != 0)));
5d669648 6711
252b5132 6712 if (!intel_syntax)
7967e09e 6713 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6714 {
5d669648
L		 6715 if (havedisp || riprel)
6716 print_displacement (scratchbuf, disp);
6717 else
6718 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6719 oappend (scratchbuf);
52b15da3
JH		 6720 if (riprel)
6721 {
6722 set_op (disp, 1);
87767711 6723 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6724 }
db6eb5be 6725 }
2da11e11 6726
87767711
JB		 6727 if (havebase || haveindex || riprel)
6728 used_prefixes |= PREFIX_ADDR;
6729
5d669648 6730 if (havedisp || (intel_syntax && riprel))
252b5132 6731 {
252b5132 6732 *obufp++ = open_char;
52b15da3 6733 if (intel_syntax && riprel)
185b1163
L		 6734 {
6735 set_op (disp, 1);
87767711 6736 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6737 }
db6eb5be 6738 *obufp = '\0';
252b5132 6739 if (havebase)
cb712a9e 6740 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6741 ? names64[base] : names32[base]);
252b5132
RH		 6742 if (havesib)
6743 {
db51cc60
L		 6744 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6745 print index to tell base + index from base. */
6746 if (scale != 0
20afcfb7 6747 || needindex
db51cc60
L		 6748 || haveindex
6749 || (havebase && base != ESP_REG_NUM))
252b5132 6750 {
9306ca4a 6751 if (!intel_syntax || havebase)
db6eb5be 6752 {
9306ca4a
JB		 6753 *obufp++ = separator_char;
6754 *obufp = '\0';
db6eb5be 6755 }
db51cc60
L		 6756 if (haveindex)
6757 oappend (address_mode == mode_64bit
6758 && (sizeflag & AFLAG)
6759 ? names64[index] : names32[index]);
6760 else
6761 oappend (address_mode == mode_64bit
6762 && (sizeflag & AFLAG)
6763 ? index64 : index32);
6764
db6eb5be
AM		 6765 *obufp++ = scale_char;
6766 *obufp = '\0';
6767 sprintf (scratchbuf, "%d", 1 << scale);
6768 oappend (scratchbuf);
6769 }
252b5132 6770 }
185b1163
L		 6771 if (intel_syntax
6772 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6773 {
db51cc60 6774 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6775 {
6776 *obufp++ = '+';
6777 *obufp = '\0';
6778 }
7967e09e 6779 else if (modrm.mod != 1)
3d456fa1
JB		 6780 {
6781 *obufp++ = '-';
6782 *obufp = '\0';
6783 disp = - (bfd_signed_vma) disp;
6784 }
6785
db51cc60
L		 6786 if (havedisp)
6787 print_displacement (scratchbuf, disp);
6788 else
6789 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6790 oappend (scratchbuf);
6791 }
252b5132
RH		 6792
6793 *obufp++ = close_char;
db6eb5be 6794 *obufp = '\0';
252b5132
RH		 6795 }
6796 else if (intel_syntax)
db6eb5be 6797 {
7967e09e 6798 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6799 {
252b5132
RH		 6800 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6801 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6802 ;
6803 else
6804 {
d708bcba 6805 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6806 oappend (":");
6807 }
52b15da3 6808 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6809 oappend (scratchbuf);
6810 }
6811 }
252b5132
RH		 6812 }
6813 else
6814 { /* 16 bit address mode */
7967e09e 6815 switch (modrm.mod)
252b5132
RH		 6816 {
6817 case 0:
7967e09e 6818 if (modrm.rm == 6)
252b5132
RH		 6819 {
6820 disp = get16 ();
6821 if ((disp & 0x8000) != 0)
6822 disp -= 0x10000;
6823 }
6824 break;
6825 case 1:
6826 FETCH_DATA (the_info, codep + 1);
6827 disp = *codep++;
6828 if ((disp & 0x80) != 0)
6829 disp -= 0x100;
6830 break;
6831 case 2:
6832 disp = get16 ();
6833 if ((disp & 0x8000) != 0)
6834 disp -= 0x10000;
6835 break;
6836 }
6837
6838 if (!intel_syntax)
7967e09e 6839 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6840 {
5d669648 6841 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6842 oappend (scratchbuf);
6843 }
252b5132 6844
7967e09e 6845 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6846 {
6847 *obufp++ = open_char;
db6eb5be 6848 *obufp = '\0';
7967e09e 6849 oappend (index16[modrm.rm]);
5d669648
L		 6850 if (intel_syntax
6851 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6852 {
5d669648 6853 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6854 {
6855 *obufp++ = '+';
6856 *obufp = '\0';
6857 }
7967e09e 6858 else if (modrm.mod != 1)
3d456fa1
JB		 6859 {
6860 *obufp++ = '-';
6861 *obufp = '\0';
6862 disp = - (bfd_signed_vma) disp;
6863 }
6864
5d669648 6865 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6866 oappend (scratchbuf);
6867 }
6868
db6eb5be
AM		 6869 *obufp++ = close_char;
6870 *obufp = '\0';
252b5132 6871 }
3d456fa1
JB		 6872 else if (intel_syntax)
6873 {
6874 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6875 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6876 ;
6877 else
6878 {
6879 oappend (names_seg[ds_reg - es_reg]);
6880 oappend (":");
6881 }
6882 print_operand_value (scratchbuf, 1, disp & 0xffff);
6883 oappend (scratchbuf);
6884 }
252b5132
RH		 6885 }
6886}
6887
85f10a01
MM		 6888static void
6889OP_E (int bytemode, int sizeflag)
6890{
6891 OP_E_extended (bytemode, sizeflag, 0);
6892}
6893
6894
252b5132 6895static void
26ca5450 6896OP_G (int bytemode, int sizeflag)
252b5132 6897{
52b15da3 6898 int add = 0;
161a04f6
L		 6899 USED_REX (REX_R);
6900 if (rex & REX_R)
52b15da3 6901 add += 8;
252b5132
RH		 6902 switch (bytemode)
6903 {
6904 case b_mode:
52b15da3
JH		 6905 USED_REX (0);
6906 if (rex)
7967e09e 6907 oappend (names8rex[modrm.reg + add]);
52b15da3 6908 else
7967e09e 6909 oappend (names8[modrm.reg + add]);
252b5132
RH		 6910 break;
6911 case w_mode:
7967e09e 6912 oappend (names16[modrm.reg + add]);
252b5132
RH		 6913 break;
6914 case d_mode:
7967e09e 6915 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6916 break;
6917 case q_mode:
7967e09e 6918 oappend (names64[modrm.reg + add]);
252b5132
RH		 6919 break;
6920 case v_mode:
9306ca4a 6921 case dq_mode:
42903f7f
L		 6922 case dqb_mode:
6923 case dqd_mode:
9306ca4a 6924 case dqw_mode:
161a04f6
L		 6925 USED_REX (REX_W);
6926 if (rex & REX_W)
7967e09e 6927 oappend (names64[modrm.reg + add]);
9306ca4a 6928 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6929 oappend (names32[modrm.reg + add]);
252b5132 6930 else
7967e09e 6931 oappend (names16[modrm.reg + add]);
7d421014 6932 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6933 break;
90700ea2 6934 case m_mode:
cb712a9e 6935 if (address_mode == mode_64bit)
7967e09e 6936 oappend (names64[modrm.reg + add]);
90700ea2 6937 else
7967e09e 6938 oappend (names32[modrm.reg + add]);
90700ea2 6939 break;
252b5132
RH		 6940 default:
6941 oappend (INTERNAL_DISASSEMBLER_ERROR);
6942 break;
6943 }
6944}
6945
52b15da3 6946static bfd_vma
26ca5450 6947get64 (void)
52b15da3 6948{
5dd0794d 6949 bfd_vma x;
52b15da3 6950#ifdef BFD64
5dd0794d
AM		 6951 unsigned int a;
6952 unsigned int b;
6953
52b15da3
JH		 6954 FETCH_DATA (the_info, codep + 8);
6955 a = *codep++ & 0xff;
6956 a |= (*codep++ & 0xff) << 8;
6957 a |= (*codep++ & 0xff) << 16;
6958 a |= (*codep++ & 0xff) << 24;
5dd0794d 6959 b = *codep++ & 0xff;
52b15da3
JH		 6960 b |= (*codep++ & 0xff) << 8;
6961 b |= (*codep++ & 0xff) << 16;
6962 b |= (*codep++ & 0xff) << 24;
6963 x = a + ((bfd_vma) b << 32);
6964#else
6608db57 6965 abort ();
5dd0794d 6966 x = 0;
52b15da3
JH		 6967#endif
6968 return x;
6969}
6970
6971static bfd_signed_vma
26ca5450 6972get32 (void)
252b5132 6973{
52b15da3 6974 bfd_signed_vma x = 0;
252b5132
RH		 6975
6976 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6977 x = *codep++ & (bfd_signed_vma) 0xff;
6978 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6979 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6980 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6981 return x;
6982}
6983
6984static bfd_signed_vma
26ca5450 6985get32s (void)
52b15da3
JH		 6986{
6987 bfd_signed_vma x = 0;
6988
6989 FETCH_DATA (the_info, codep + 4);
6990 x = *codep++ & (bfd_signed_vma) 0xff;
6991 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6992 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6993 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6994
6995 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6996
252b5132
RH		 6997 return x;
6998}
6999
7000static int
26ca5450 7001get16 (void)
252b5132
RH		 7002{
7003 int x = 0;
7004
7005 FETCH_DATA (the_info, codep + 2);
7006 x = *codep++ & 0xff;
7007 x |= (*codep++ & 0xff) << 8;
7008 return x;
7009}
7010
7011static void
26ca5450 7012set_op (bfd_vma op, int riprel)
252b5132
RH		 7013{
7014 op_index[op_ad] = op_ad;
cb712a9e 7015 if (address_mode == mode_64bit)
7081ff04
AJ		 7016 {
7017 op_address[op_ad] = op;
7018 op_riprel[op_ad] = riprel;
7019 }
7020 else
7021 {
7022 /* Mask to get a 32-bit address. */
7023 op_address[op_ad] = op & 0xffffffff;
7024 op_riprel[op_ad] = riprel & 0xffffffff;
7025 }
252b5132
RH		 7026}
7027
7028static void
26ca5450 7029OP_REG (int code, int sizeflag)
252b5132 7030{
2da11e11 7031 const char *s;
9b60702d 7032 int add;
161a04f6
L		 7033 USED_REX (REX_B);
7034 if (rex & REX_B)
52b15da3 7035 add = 8;
9b60702d
L		 7036 else
7037 add = 0;
52b15da3
JH		 7038
7039 switch (code)
7040 {
52b15da3
JH		 7041 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7042 case sp_reg: case bp_reg: case si_reg: case di_reg:
7043 s = names16[code - ax_reg + add];
7044 break;
7045 case es_reg: case ss_reg: case cs_reg:
7046 case ds_reg: case fs_reg: case gs_reg:
7047 s = names_seg[code - es_reg + add];
7048 break;
7049 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7050 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
7051 USED_REX (0);
7052 if (rex)
7053 s = names8rex[code - al_reg + add];
7054 else
7055 s = names8[code - al_reg];
7056 break;
6439fc28
AM		 7057 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
7058 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 7059 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 7060 {
7061 s = names64[code - rAX_reg + add];
7062 break;
7063 }
7064 code += eAX_reg - rAX_reg;
6608db57 7065 /* Fall through. */
52b15da3
JH		 7066 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7067 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7068 USED_REX (REX_W);
7069 if (rex & REX_W)
52b15da3
JH		 7070 s = names64[code - eAX_reg + add];
7071 else if (sizeflag & DFLAG)
7072 s = names32[code - eAX_reg + add];
7073 else
7074 s = names16[code - eAX_reg + add];
7075 used_prefixes |= (prefixes & PREFIX_DATA);
7076 break;
52b15da3
JH		 7077 default:
7078 s = INTERNAL_DISASSEMBLER_ERROR;
7079 break;
7080 }
7081 oappend (s);
7082}
7083
7084static void
26ca5450 7085OP_IMREG (int code, int sizeflag)
52b15da3
JH		 7086{
7087 const char *s;
252b5132
RH		 7088
7089 switch (code)
7090 {
7091 case indir_dx_reg:
d708bcba 7092 if (intel_syntax)
52fd6d94 7093 s = "dx";
d708bcba 7094 else
db6eb5be 7095 s = "(%dx)";
252b5132
RH		 7096 break;
7097 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7098 case sp_reg: case bp_reg: case si_reg: case di_reg:
7099 s = names16[code - ax_reg];
7100 break;
7101 case es_reg: case ss_reg: case cs_reg:
7102 case ds_reg: case fs_reg: case gs_reg:
7103 s = names_seg[code - es_reg];
7104 break;
7105 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7106 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 7107 USED_REX (0);
7108 if (rex)
7109 s = names8rex[code - al_reg];
7110 else
7111 s = names8[code - al_reg];
252b5132
RH		 7112 break;
7113 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7114 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7115 USED_REX (REX_W);
7116 if (rex & REX_W)
52b15da3
JH		 7117 s = names64[code - eAX_reg];
7118 else if (sizeflag & DFLAG)
252b5132
RH		 7119 s = names32[code - eAX_reg];
7120 else
7121 s = names16[code - eAX_reg];
7d421014 7122 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 7123 break;
52fd6d94 7124 case z_mode_ax_reg:
161a04f6 7125 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 7126 s = *names32;
7127 else
7128 s = *names16;
161a04f6 7129 if (!(rex & REX_W))
52fd6d94
JB		 7130 used_prefixes |= (prefixes & PREFIX_DATA);
7131 break;
252b5132
RH		 7132 default:
7133 s = INTERNAL_DISASSEMBLER_ERROR;
7134 break;
7135 }
7136 oappend (s);
7137}
7138
7139static void
26ca5450 7140OP_I (int bytemode, int sizeflag)
252b5132 7141{
52b15da3
JH		 7142 bfd_signed_vma op;
7143 bfd_signed_vma mask = -1;
252b5132
RH		 7144
7145 switch (bytemode)
7146 {
7147 case b_mode:
7148 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7149 op = *codep++;
7150 mask = 0xff;
7151 break;
7152 case q_mode:
cb712a9e 7153 if (address_mode == mode_64bit)
6439fc28
AM		 7154 {
7155 op = get32s ();
7156 break;
7157 }
6608db57 7158 /* Fall through. */
252b5132 7159 case v_mode:
161a04f6
L		 7160 USED_REX (REX_W);
7161 if (rex & REX_W)
52b15da3
JH		 7162 op = get32s ();
7163 else if (sizeflag & DFLAG)
7164 {
7165 op = get32 ();
7166 mask = 0xffffffff;
7167 }
252b5132 7168 else
52b15da3
JH		 7169 {
7170 op = get16 ();
7171 mask = 0xfffff;
7172 }
7d421014 7173 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7174 break;
7175 case w_mode:
52b15da3 7176 mask = 0xfffff;
252b5132
RH		 7177 op = get16 ();
7178 break;
9306ca4a
JB		 7179 case const_1_mode:
7180 if (intel_syntax)
7181 oappend ("1");
7182 return;
252b5132
RH		 7183 default:
7184 oappend (INTERNAL_DISASSEMBLER_ERROR);
7185 return;
7186 }
7187
52b15da3
JH		 7188 op &= mask;
7189 scratchbuf[0] = '$';
d708bcba
AM		 7190 print_operand_value (scratchbuf + 1, 1, op);
7191 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7192 scratchbuf[0] = '\0';
7193}
7194
7195static void
26ca5450 7196OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7197{
7198 bfd_signed_vma op;
7199 bfd_signed_vma mask = -1;
7200
cb712a9e 7201 if (address_mode != mode_64bit)
6439fc28
AM		 7202 {
7203 OP_I (bytemode, sizeflag);
7204 return;
7205 }
7206
52b15da3
JH		 7207 switch (bytemode)
7208 {
7209 case b_mode:
7210 FETCH_DATA (the_info, codep + 1);
7211 op = *codep++;
7212 mask = 0xff;
7213 break;
7214 case v_mode:
161a04f6
L		 7215 USED_REX (REX_W);
7216 if (rex & REX_W)
52b15da3
JH		 7217 op = get64 ();
7218 else if (sizeflag & DFLAG)
7219 {
7220 op = get32 ();
7221 mask = 0xffffffff;
7222 }
7223 else
7224 {
7225 op = get16 ();
7226 mask = 0xfffff;
7227 }
7228 used_prefixes |= (prefixes & PREFIX_DATA);
7229 break;
7230 case w_mode:
7231 mask = 0xfffff;
7232 op = get16 ();
7233 break;
7234 default:
7235 oappend (INTERNAL_DISASSEMBLER_ERROR);
7236 return;
7237 }
7238
7239 op &= mask;
7240 scratchbuf[0] = '$';
d708bcba
AM		 7241 print_operand_value (scratchbuf + 1, 1, op);
7242 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7243 scratchbuf[0] = '\0';
7244}
7245
7246static void
26ca5450 7247OP_sI (int bytemode, int sizeflag)
252b5132 7248{
52b15da3
JH		 7249 bfd_signed_vma op;
7250 bfd_signed_vma mask = -1;
252b5132
RH		 7251
7252 switch (bytemode)
7253 {
7254 case b_mode:
7255 FETCH_DATA (the_info, codep + 1);
7256 op = *codep++;
7257 if ((op & 0x80) != 0)
7258 op -= 0x100;
52b15da3 7259 mask = 0xffffffff;
252b5132
RH		 7260 break;
7261 case v_mode:
161a04f6
L		 7262 USED_REX (REX_W);
7263 if (rex & REX_W)
52b15da3
JH		 7264 op = get32s ();
7265 else if (sizeflag & DFLAG)
7266 {
7267 op = get32s ();
7268 mask = 0xffffffff;
7269 }
252b5132
RH		 7270 else
7271 {
52b15da3 7272 mask = 0xffffffff;
6608db57 7273 op = get16 ();
252b5132
RH		 7274 if ((op & 0x8000) != 0)
7275 op -= 0x10000;
7276 }
7d421014 7277 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7278 break;
7279 case w_mode:
7280 op = get16 ();
52b15da3 7281 mask = 0xffffffff;
252b5132
RH		 7282 if ((op & 0x8000) != 0)
7283 op -= 0x10000;
7284 break;
7285 default:
7286 oappend (INTERNAL_DISASSEMBLER_ERROR);
7287 return;
7288 }
52b15da3
JH		 7289
7290 scratchbuf[0] = '$';
7291 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7292 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7293}
7294
7295static void
26ca5450 7296OP_J (int bytemode, int sizeflag)
252b5132 7297{
52b15da3 7298 bfd_vma disp;
7081ff04 7299 bfd_vma mask = -1;
65ca155d 7300 bfd_vma segment = 0;
252b5132
RH		 7301
7302 switch (bytemode)
7303 {
7304 case b_mode:
7305 FETCH_DATA (the_info, codep + 1);
7306 disp = *codep++;
7307 if ((disp & 0x80) != 0)
7308 disp -= 0x100;
7309 break;
7310 case v_mode:
161a04f6 7311 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7312 disp = get32s ();
252b5132
RH		 7313 else
7314 {
7315 disp = get16 ();
206717e8
L		 7316 if ((disp & 0x8000) != 0)
7317 disp -= 0x10000;
65ca155d
L		 7318 /* In 16bit mode, address is wrapped around at 64k within
7319 the same segment. Otherwise, a data16 prefix on a jump
7320 instruction means that the pc is masked to 16 bits after
7321 the displacement is added! */
7322 mask = 0xffff;
7323 if ((prefixes & PREFIX_DATA) == 0)
7324 segment = ((start_pc + codep - start_codep)
7325 & ~((bfd_vma) 0xffff));
252b5132 7326 }
d807a492 7327 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7328 break;
7329 default:
7330 oappend (INTERNAL_DISASSEMBLER_ERROR);
7331 return;
7332 }
65ca155d 7333 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7334 set_op (disp, 0);
7335 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7336 oappend (scratchbuf);
7337}
7338
252b5132 7339static void
ed7841b3 7340OP_SEG (int bytemode, int sizeflag)
252b5132 7341{
ed7841b3 7342 if (bytemode == w_mode)
7967e09e 7343 oappend (names_seg[modrm.reg]);
ed7841b3 7344 else
7967e09e 7345 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7346}
7347
7348static void
26ca5450 7349OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7350{
7351 int seg, offset;
7352
c608c12e 7353 if (sizeflag & DFLAG)
252b5132 7354 {
c608c12e
AM		 7355 offset = get32 ();
7356 seg = get16 ();
252b5132 7357 }
c608c12e
AM		 7358 else
7359 {
7360 offset = get16 ();
7361 seg = get16 ();
7362 }
7d421014 7363 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7364 if (intel_syntax)
3f31e633 7365 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7366 else
7367 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7368 oappend (scratchbuf);
252b5132
RH		 7369}
7370
252b5132 7371static void
3f31e633 7372OP_OFF (int bytemode, int sizeflag)
252b5132 7373{
52b15da3 7374 bfd_vma off;
252b5132 7375
3f31e633
JB		 7376 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7377 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7378 append_seg ();
7379
cb712a9e 7380 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7381 off = get32 ();
7382 else
7383 off = get16 ();
7384
7385 if (intel_syntax)
7386 {
7387 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7388 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7389 {
d708bcba 7390 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7391 oappend (":");
7392 }
7393 }
52b15da3
JH		 7394 print_operand_value (scratchbuf, 1, off);
7395 oappend (scratchbuf);
7396}
6439fc28 7397
52b15da3 7398static void
3f31e633 7399OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7400{
7401 bfd_vma off;
7402
539e75ad
L		 7403 if (address_mode != mode_64bit
7404 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7405 {
7406 OP_OFF (bytemode, sizeflag);
7407 return;
7408 }
7409
3f31e633
JB		 7410 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7411 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7412 append_seg ();
7413
6608db57 7414 off = get64 ();
52b15da3
JH		 7415
7416 if (intel_syntax)
7417 {
7418 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7419 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7420 {
d708bcba 7421 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7422 oappend (":");
7423 }
7424 }
7425 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7426 oappend (scratchbuf);
7427}
7428
7429static void
26ca5450 7430ptr_reg (int code, int sizeflag)
252b5132 7431{
2da11e11 7432 const char *s;
d708bcba 7433
1d9f512f 7434 *obufp++ = open_char;
20f0a1fc 7435 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7436 if (address_mode == mode_64bit)
c1a64871
JH		 7437 {
7438 if (!(sizeflag & AFLAG))
db6eb5be 7439 s = names32[code - eAX_reg];
c1a64871 7440 else
db6eb5be 7441 s = names64[code - eAX_reg];
c1a64871 7442 }
52b15da3 7443 else if (sizeflag & AFLAG)
252b5132
RH		 7444 s = names32[code - eAX_reg];
7445 else
7446 s = names16[code - eAX_reg];
7447 oappend (s);
1d9f512f
AM		 7448 *obufp++ = close_char;
7449 *obufp = 0;
252b5132
RH		 7450}
7451
7452static void
26ca5450 7453OP_ESreg (int code, int sizeflag)
252b5132 7454{
9306ca4a 7455 if (intel_syntax)
52fd6d94
JB		 7456 {
7457 switch (codep[-1])
7458 {
7459 case 0x6d: /* insw/insl */
7460 intel_operand_size (z_mode, sizeflag);
7461 break;
7462 case 0xa5: /* movsw/movsl/movsq */
7463 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7464 case 0xab: /* stosw/stosl */
7465 case 0xaf: /* scasw/scasl */
7466 intel_operand_size (v_mode, sizeflag);
7467 break;
7468 default:
7469 intel_operand_size (b_mode, sizeflag);
7470 }
7471 }
d708bcba 7472 oappend ("%es:" + intel_syntax);
252b5132
RH		 7473 ptr_reg (code, sizeflag);
7474}
7475
7476static void
26ca5450 7477OP_DSreg (int code, int sizeflag)
252b5132 7478{
9306ca4a 7479 if (intel_syntax)
52fd6d94
JB		 7480 {
7481 switch (codep[-1])
7482 {
7483 case 0x6f: /* outsw/outsl */
7484 intel_operand_size (z_mode, sizeflag);
7485 break;
7486 case 0xa5: /* movsw/movsl/movsq */
7487 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7488 case 0xad: /* lodsw/lodsl/lodsq */
7489 intel_operand_size (v_mode, sizeflag);
7490 break;
7491 default:
7492 intel_operand_size (b_mode, sizeflag);
7493 }
7494 }
252b5132
RH		 7495 if ((prefixes
7496 & (PREFIX_CS
7497 | PREFIX_DS
7498 | PREFIX_SS
7499 | PREFIX_ES
7500 | PREFIX_FS
7501 | PREFIX_GS)) == 0)
7502 prefixes |= PREFIX_DS;
6608db57 7503 append_seg ();
252b5132
RH		 7504 ptr_reg (code, sizeflag);
7505}
7506
252b5132 7507static void
26ca5450 7508OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7509{
9b60702d 7510 int add;
161a04f6 7511 if (rex & REX_R)
c4a530c5 7512 {
161a04f6 7513 USED_REX (REX_R);
c4a530c5
JB		 7514 add = 8;
7515 }
cb712a9e 7516 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7517 {
b844680a 7518 lock_prefix = NULL;
c4a530c5
JB		 7519 used_prefixes |= PREFIX_LOCK;
7520 add = 8;
7521 }
9b60702d
L		 7522 else
7523 add = 0;
7967e09e 7524 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7525 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7526}
7527
252b5132 7528static void
26ca5450 7529OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7530{
9b60702d 7531 int add;
161a04f6
L		 7532 USED_REX (REX_R);
7533 if (rex & REX_R)
52b15da3 7534 add = 8;
9b60702d
L		 7535 else
7536 add = 0;
d708bcba 7537 if (intel_syntax)
7967e09e 7538 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7539 else
7967e09e 7540 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7541 oappend (scratchbuf);
7542}
7543
252b5132 7544static void
26ca5450 7545OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7546{
7967e09e 7547 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7548 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7549}
7550
7551static void
6f74c397 7552OP_R (int bytemode, int sizeflag)
252b5132 7553{
7967e09e 7554 if (modrm.mod == 3)
2da11e11
AM		 7555 OP_E (bytemode, sizeflag);
7556 else
6608db57 7557 BadOp ();
252b5132
RH		 7558}
7559
7560static void
26ca5450 7561OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7562{
041bd2e0
JH		 7563 used_prefixes |= (prefixes & PREFIX_DATA);
7564 if (prefixes & PREFIX_DATA)
20f0a1fc 7565 {
9b60702d 7566 int add;
161a04f6
L		 7567 USED_REX (REX_R);
7568 if (rex & REX_R)
20f0a1fc 7569 add = 8;
9b60702d
L		 7570 else
7571 add = 0;
7967e09e 7572 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7573 }
041bd2e0 7574 else
7967e09e 7575 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7576 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7577}
7578
c608c12e 7579static void
26ca5450 7580OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7581{
9b60702d 7582 int add;
161a04f6
L		 7583 USED_REX (REX_R);
7584 if (rex & REX_R)
041bd2e0 7585 add = 8;
9b60702d
L		 7586 else
7587 add = 0;
7967e09e 7588 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7589 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7590}
7591
252b5132 7592static void
26ca5450 7593OP_EM (int bytemode, int sizeflag)
252b5132 7594{
7967e09e 7595 if (modrm.mod != 3)
252b5132 7596 {
9306ca4a
JB		 7597 if (intel_syntax && bytemode == v_mode)
7598 {
7599 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7600 used_prefixes |= (prefixes & PREFIX_DATA);
7601 }
252b5132
RH		 7602 OP_E (bytemode, sizeflag);
7603 return;
7604 }
7605
6608db57 7606 /* Skip mod/rm byte. */
4bba6815 7607 MODRM_CHECK;
252b5132 7608 codep++;
041bd2e0
JH		 7609 used_prefixes |= (prefixes & PREFIX_DATA);
7610 if (prefixes & PREFIX_DATA)
20f0a1fc 7611 {
9b60702d 7612 int add;
20f0a1fc 7613
161a04f6
L		 7614 USED_REX (REX_B);
7615 if (rex & REX_B)
20f0a1fc 7616 add = 8;
9b60702d
L		 7617 else
7618 add = 0;
7967e09e 7619 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7620 }
041bd2e0 7621 else
7967e09e 7622 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7623 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7624}
7625
246c51aa
L		 7626/* cvt* are the only instructions in sse2 which have
7627 both SSE and MMX operands and also have 0x66 prefix
7628 in their opcode. 0x66 was originally used to differentiate
7629 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7630 cvt* separately using OP_EMC and OP_MXC */
7631static void
7632OP_EMC (int bytemode, int sizeflag)
7633{
7967e09e 7634 if (modrm.mod != 3)
4d9567e0
MM		 7635 {
7636 if (intel_syntax && bytemode == v_mode)
7637 {
7638 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7639 used_prefixes |= (prefixes & PREFIX_DATA);
7640 }
7641 OP_E (bytemode, sizeflag);
7642 return;
7643 }
246c51aa 7644
4d9567e0
MM		 7645 /* Skip mod/rm byte. */
7646 MODRM_CHECK;
7647 codep++;
7648 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7649 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7650 oappend (scratchbuf + intel_syntax);
7651}
7652
7653static void
7654OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7655{
7656 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7657 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7658 oappend (scratchbuf + intel_syntax);
7659}
7660
c608c12e 7661static void
26ca5450 7662OP_EX (int bytemode, int sizeflag)
c608c12e 7663{
9b60702d 7664 int add;
7967e09e 7665 if (modrm.mod != 3)
c608c12e
AM		 7666 {
7667 OP_E (bytemode, sizeflag);
7668 return;
7669 }
161a04f6
L		 7670 USED_REX (REX_B);
7671 if (rex & REX_B)
041bd2e0 7672 add = 8;
9b60702d
L		 7673 else
7674 add = 0;
c608c12e 7675
6608db57 7676 /* Skip mod/rm byte. */
4bba6815 7677 MODRM_CHECK;
c608c12e 7678 codep++;
7967e09e 7679 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7680 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7681}
7682
252b5132 7683static void
26ca5450 7684OP_MS (int bytemode, int sizeflag)
252b5132 7685{
7967e09e 7686 if (modrm.mod == 3)
2da11e11
AM		 7687 OP_EM (bytemode, sizeflag);
7688 else
6608db57 7689 BadOp ();
252b5132
RH		 7690}
7691
992aaec9 7692static void
26ca5450 7693OP_XS (int bytemode, int sizeflag)
992aaec9 7694{
7967e09e 7695 if (modrm.mod == 3)
992aaec9
AM		 7696 OP_EX (bytemode, sizeflag);
7697 else
6608db57 7698 BadOp ();
992aaec9
AM		 7699}
7700
cc0ec051
AM		 7701static void
7702OP_M (int bytemode, int sizeflag)
7703{
7967e09e 7704 if (modrm.mod == 3)
75413a22
L		 7705 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7706 BadOp ();
cc0ec051
AM		 7707 else
7708 OP_E (bytemode, sizeflag);
7709}
7710
7711static void
7712OP_0f07 (int bytemode, int sizeflag)
7713{
7967e09e 7714 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7715 BadOp ();
7716 else
7717 OP_E (bytemode, sizeflag);
7718}
7719
46e883c5 7720/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7721 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7722
cc0ec051 7723static void
46e883c5 7724NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7725{
8b38ad71
L		 7726 if ((prefixes & PREFIX_DATA) != 0
7727 || (rex != 0
7728 && rex != 0x48
7729 && address_mode == mode_64bit))
46e883c5
L		 7730 OP_REG (bytemode, sizeflag);
7731 else
7732 strcpy (obuf, "nop");
7733}
7734
7735static void
7736NOP_Fixup2 (int bytemode, int sizeflag)
7737{
8b38ad71
L		 7738 if ((prefixes & PREFIX_DATA) != 0
7739 || (rex != 0
7740 && rex != 0x48
7741 && address_mode == mode_64bit))
46e883c5 7742 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7743}
7744
84037f8c 7745static const char *const Suffix3DNow[] = {
252b5132
RH		 7746/* 00 */ NULL, NULL, NULL, NULL,
7747/* 04 */ NULL, NULL, NULL, NULL,
7748/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7749/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7750/* 10 */ NULL, NULL, NULL, NULL,
7751/* 14 */ NULL, NULL, NULL, NULL,
7752/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7753/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7754/* 20 */ NULL, NULL, NULL, NULL,
7755/* 24 */ NULL, NULL, NULL, NULL,
7756/* 28 */ NULL, NULL, NULL, NULL,
7757/* 2C */ NULL, NULL, NULL, NULL,
7758/* 30 */ NULL, NULL, NULL, NULL,
7759/* 34 */ NULL, NULL, NULL, NULL,
7760/* 38 */ NULL, NULL, NULL, NULL,
7761/* 3C */ NULL, NULL, NULL, NULL,
7762/* 40 */ NULL, NULL, NULL, NULL,
7763/* 44 */ NULL, NULL, NULL, NULL,
7764/* 48 */ NULL, NULL, NULL, NULL,
7765/* 4C */ NULL, NULL, NULL, NULL,
7766/* 50 */ NULL, NULL, NULL, NULL,
7767/* 54 */ NULL, NULL, NULL, NULL,
7768/* 58 */ NULL, NULL, NULL, NULL,
7769/* 5C */ NULL, NULL, NULL, NULL,
7770/* 60 */ NULL, NULL, NULL, NULL,
7771/* 64 */ NULL, NULL, NULL, NULL,
7772/* 68 */ NULL, NULL, NULL, NULL,
7773/* 6C */ NULL, NULL, NULL, NULL,
7774/* 70 */ NULL, NULL, NULL, NULL,
7775/* 74 */ NULL, NULL, NULL, NULL,
7776/* 78 */ NULL, NULL, NULL, NULL,
7777/* 7C */ NULL, NULL, NULL, NULL,
7778/* 80 */ NULL, NULL, NULL, NULL,
7779/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7780/* 88 */ NULL, NULL, "pfnacc", NULL,
7781/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7782/* 90 */ "pfcmpge", NULL, NULL, NULL,
7783/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7784/* 98 */ NULL, NULL, "pfsub", NULL,
7785/* 9C */ NULL, NULL, "pfadd", NULL,
7786/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7787/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7788/* A8 */ NULL, NULL, "pfsubr", NULL,
7789/* AC */ NULL, NULL, "pfacc", NULL,
7790/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7791/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7792/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7793/* BC */ NULL, NULL, NULL, "pavgusb",
7794/* C0 */ NULL, NULL, NULL, NULL,
7795/* C4 */ NULL, NULL, NULL, NULL,
7796/* C8 */ NULL, NULL, NULL, NULL,
7797/* CC */ NULL, NULL, NULL, NULL,
7798/* D0 */ NULL, NULL, NULL, NULL,
7799/* D4 */ NULL, NULL, NULL, NULL,
7800/* D8 */ NULL, NULL, NULL, NULL,
7801/* DC */ NULL, NULL, NULL, NULL,
7802/* E0 */ NULL, NULL, NULL, NULL,
7803/* E4 */ NULL, NULL, NULL, NULL,
7804/* E8 */ NULL, NULL, NULL, NULL,
7805/* EC */ NULL, NULL, NULL, NULL,
7806/* F0 */ NULL, NULL, NULL, NULL,
7807/* F4 */ NULL, NULL, NULL, NULL,
7808/* F8 */ NULL, NULL, NULL, NULL,
7809/* FC */ NULL, NULL, NULL, NULL,
7810};
7811
7812static void
26ca5450 7813OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7814{
7815 const char *mnemonic;
7816
7817 FETCH_DATA (the_info, codep + 1);
7818 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7819 place where an 8-bit immediate would normally go. ie. the last
7820 byte of the instruction. */
6608db57 7821 obufp = obuf + strlen (obuf);
c608c12e 7822 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7823 if (mnemonic)
2da11e11 7824 oappend (mnemonic);
252b5132
RH		 7825 else
7826 {
7827 /* Since a variable sized modrm/sib chunk is between the start
7828 of the opcode (0x0f0f) and the opcode suffix, we need to do
7829 all the modrm processing first, and don't know until now that
7830 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7831 op_out[0][0] = '\0';
7832 op_out[1][0] = '\0';
6608db57 7833 BadOp ();
252b5132
RH		 7834 }
7835}
c608c12e 7836
6608db57 7837static const char *simd_cmp_op[] = {
c608c12e
AM		 7838 "eq",
7839 "lt",
7840 "le",
7841 "unord",
7842 "neq",
7843 "nlt",
7844 "nle",
7845 "ord"
7846};
7847
7848static void
ad19981d 7849CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7850{
7851 unsigned int cmp_type;
7852
7853 FETCH_DATA (the_info, codep + 1);
7854 cmp_type = *codep++ & 0xff;
7855 if (cmp_type < 8)
7856 {
ad19981d
L		 7857 char suffix [3];
7858 char *p = obuf + strlen (obuf) - 2;
7859 suffix[0] = p[0];
7860 suffix[1] = p[1];
7861 suffix[2] = '\0';
7862 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
c608c12e
AM		 7863 }
7864 else
7865 {
ad19981d
L		 7866 /* We have a reserved extension byte. Output it directly. */
7867 scratchbuf[0] = '$';
7868 print_operand_value (scratchbuf + 1, 1, cmp_type);
7869 oappend (scratchbuf + intel_syntax);
7870 scratchbuf[0] = '\0';
c608c12e
AM		 7871 }
7872}
7873
ca164297 7874static void
b844680a
L		 7875OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7876 int sizeflag ATTRIBUTE_UNUSED)
7877{
7878 /* mwait %eax,%ecx */
7879 if (!intel_syntax)
7880 {
7881 const char **names = (address_mode == mode_64bit
7882 ? names64 : names32);
7883 strcpy (op_out[0], names[0]);
7884 strcpy (op_out[1], names[1]);
7885 two_source_ops = 1;
7886 }
7887 /* Skip mod/rm byte. */
7888 MODRM_CHECK;
7889 codep++;
7890}
7891
7892static void
7893OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7894 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7895{
b844680a
L		 7896 /* monitor %eax,%ecx,%edx" */
7897 if (!intel_syntax)
ca164297 7898 {
b844680a 7899 const char **op1_names;
cb712a9e
L		 7900 const char **names = (address_mode == mode_64bit
7901 ? names64 : names32);
1d9f512f 7902
b844680a
L		 7903 if (!(prefixes & PREFIX_ADDR))
7904 op1_names = (address_mode == mode_16bit
7905 ? names16 : names);
ca164297
L		 7906 else
7907 {
b844680a
L		 7908 /* Remove "addr16/addr32". */
7909 addr_prefix = NULL;
7910 op1_names = (address_mode != mode_32bit
7911 ? names32 : names16);
7912 used_prefixes |= PREFIX_ADDR;
ca164297 7913 }
b844680a
L		 7914 strcpy (op_out[0], op1_names[0]);
7915 strcpy (op_out[1], names[1]);
7916 strcpy (op_out[2], names[2]);
7917 two_source_ops = 1;
ca164297 7918 }
b844680a
L		 7919 /* Skip mod/rm byte. */
7920 MODRM_CHECK;
7921 codep++;
30123838
JB		 7922}
7923
6608db57
KH		 7924static void
7925BadOp (void)
2da11e11 7926{
6608db57
KH		 7927 /* Throw away prefixes and 1st. opcode byte. */
7928 codep = insn_codep + 1;
2da11e11
AM		 7929 oappend ("(bad)");
7930}
4cc91dba 7931
35c52694
L		 7932static void
7933REP_Fixup (int bytemode, int sizeflag)
7934{
7935 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7936 lods and stos. */
35c52694 7937 if (prefixes & PREFIX_REPZ)
b844680a 7938 repz_prefix = "rep ";
35c52694
L		 7939
7940 switch (bytemode)
7941 {
7942 case al_reg:
7943 case eAX_reg:
7944 case indir_dx_reg:
7945 OP_IMREG (bytemode, sizeflag);
7946 break;
7947 case eDI_reg:
7948 OP_ESreg (bytemode, sizeflag);
7949 break;
7950 case eSI_reg:
7951 OP_DSreg (bytemode, sizeflag);
7952 break;
7953 default:
7954 abort ();
7955 break;
7956 }
7957}
f5804c90
L		 7958
7959static void
7960CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7961{
161a04f6
L		 7962 USED_REX (REX_W);
7963 if (rex & REX_W)
f5804c90
L		 7964 {
7965 /* Change cmpxchg8b to cmpxchg16b. */
7966 char *p = obuf + strlen (obuf) - 2;
7967 strcpy (p, "16b");
fb9c77c7 7968 bytemode = o_mode;
f5804c90
L		 7969 }
7970 OP_M (bytemode, sizeflag);
7971}
42903f7f
L		 7972
7973static void
7974XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7975{
7976 sprintf (scratchbuf, "%%xmm%d", reg);
7977 oappend (scratchbuf + intel_syntax);
7978}
381d071f
L		 7979
7980static void
7981CRC32_Fixup (int bytemode, int sizeflag)
7982{
7983 /* Add proper suffix to "crc32". */
7984 char *p = obuf + strlen (obuf);
7985
7986 switch (bytemode)
7987 {
7988 case b_mode:
20592a94
L		 7989 if (intel_syntax)
7990 break;
7991
381d071f
L		 7992 *p++ = 'b';
7993 break;
7994 case v_mode:
20592a94
L		 7995 if (intel_syntax)
7996 break;
7997
381d071f
L		 7998 USED_REX (REX_W);
7999 if (rex & REX_W)
8000 *p++ = 'q';
9344ff29 8001 else if (sizeflag & DFLAG)
20592a94 8002 *p++ = 'l';
381d071f 8003 else
9344ff29
L		 8004 *p++ = 'w';
8005 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 8006 break;
8007 default:
8008 oappend (INTERNAL_DISASSEMBLER_ERROR);
8009 break;
8010 }
8011 *p = '\0';
8012
8013 if (modrm.mod == 3)
8014 {
8015 int add;
8016
8017 /* Skip mod/rm byte. */
8018 MODRM_CHECK;
8019 codep++;
8020
8021 USED_REX (REX_B);
8022 add = (rex & REX_B) ? 8 : 0;
8023 if (bytemode == b_mode)
8024 {
8025 USED_REX (0);
8026 if (rex)
8027 oappend (names8rex[modrm.rm + add]);
8028 else
8029 oappend (names8[modrm.rm + add]);
8030 }
8031 else
8032 {
8033 USED_REX (REX_W);
8034 if (rex & REX_W)
8035 oappend (names64[modrm.rm + add]);
8036 else if ((prefixes & PREFIX_DATA))
8037 oappend (names16[modrm.rm + add]);
8038 else
8039 oappend (names32[modrm.rm + add]);
8040 }
8041 }
8042 else
9344ff29 8043 OP_E (bytemode, sizeflag);
381d071f 8044}
85f10a01
MM		 8045
8046/* Print a DREX argument as either a register or memory operation. */
8047static void
8048print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
8049{
8050 if (reg == DREX_REG_UNKNOWN)
8051 BadOp ();
8052
8053 else if (reg != DREX_REG_MEMORY)
8054 {
8055 sprintf (scratchbuf, "%%xmm%d", reg);
8056 oappend (scratchbuf + intel_syntax);
8057 }
8058
8059 else
8060 OP_E_extended (bytemode, sizeflag, 1);
8061}
8062
8063/* SSE5 instructions that have 4 arguments are encoded as:
8064 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
8065
8066 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
8067 the DREX field (0x8) to determine how the arguments are laid out.
8068 The destination register must be the same register as one of the
8069 inputs, and it is encoded in the DREX byte. No REX prefix is used
8070 for these instructions, since the DREX field contains the 3 extension
8071 bits provided by the REX prefix.
8072
8073 The bytemode argument adds 2 extra bits for passing extra information:
8074 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
8075 DREX_NO_OC0 -- OC0 in DREX is invalid
8076 (but pretend it is set). */
8077
8078static void
8079OP_DREX4 (int flag_bytemode, int sizeflag)
8080{
8081 unsigned int drex_byte;
8082 unsigned int regs[4];
8083 unsigned int modrm_regmem;
8084 unsigned int modrm_reg;
8085 unsigned int drex_reg;
8086 int bytemode;
8087 int rex_save = rex;
8088 int rex_used_save = rex_used;
8089 int has_sib = 0;
8090 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
8091 int oc0;
8092 int i;
8093
8094 bytemode = flag_bytemode & ~ DREX_MASK;
8095
8096 for (i = 0; i < 4; i++)
8097 regs[i] = DREX_REG_UNKNOWN;
8098
8099 /* Determine if we have a SIB byte in addition to MODRM before the
8100 DREX byte. */
8101 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8102 && (modrm.mod != 3)
8103 && (modrm.rm == 4))
8104 has_sib = 1;
8105
8106 /* Get the DREX byte. */
8107 FETCH_DATA (the_info, codep + 2 + has_sib);
8108 drex_byte = codep[has_sib+1];
8109 drex_reg = DREX_XMM (drex_byte);
8110 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8111
8112 /* Is OC0 legal? If not, hardwire oc0 == 1. */
8113 if (flag_bytemode & DREX_NO_OC0)
8114 {
8115 oc0 = 1;
8116 if (DREX_OC0 (drex_byte))
8117 BadOp ();
8118 }
8119 else
8120 oc0 = DREX_OC0 (drex_byte);
8121
8122 if (modrm.mod == 3)
8123 {
8124 /* regmem == register */
8125 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8126 rex = rex_used = 0;
8127 /* skip modrm/drex since we don't call OP_E_extended */
8128 codep += 2;
8129 }
8130 else
8131 {
8132 /* regmem == memory, fill in appropriate REX bits */
8133 modrm_regmem = DREX_REG_MEMORY;
8134 rex = drex_byte & (REX_B | REX_X | REX_R);
8135 if (rex)
8136 rex |= REX_OPCODE;
8137 rex_used = rex;
8138 }
8139
8140 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8141 order. */
8142 switch (oc0 + oc1)
8143 {
8144 default:
8145 BadOp ();
8146 return;
8147
8148 case 0:
8149 regs[0] = modrm_regmem;
8150 regs[1] = modrm_reg;
8151 regs[2] = drex_reg;
8152 regs[3] = drex_reg;
8153 break;
8154
8155 case 1:
8156 regs[0] = modrm_reg;
8157 regs[1] = modrm_regmem;
8158 regs[2] = drex_reg;
8159 regs[3] = drex_reg;
8160 break;
8161
8162 case 2:
8163 regs[0] = drex_reg;
8164 regs[1] = modrm_regmem;
8165 regs[2] = modrm_reg;
8166 regs[3] = drex_reg;
8167 break;
8168
8169 case 3:
8170 regs[0] = drex_reg;
8171 regs[1] = modrm_reg;
8172 regs[2] = modrm_regmem;
8173 regs[3] = drex_reg;
8174 break;
8175 }
8176
8177 /* Print out the arguments. */
8178 for (i = 0; i < 4; i++)
8179 {
8180 int j = (intel_syntax) ? 3 - i : i;
8181 if (i > 0)
8182 {
8183 *obufp++ = ',';
8184 *obufp = '\0';
8185 }
8186
8187 print_drex_arg (regs[j], bytemode, sizeflag);
8188 }
8189
8190 rex = rex_save;
8191 rex_used = rex_used_save;
8192}
8193
8194/* SSE5 instructions that have 3 arguments, and are encoded as:
8195 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8196 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8197
8198 The DREX field has 1 bit (0x8) to determine how the arguments are
8199 laid out. The destination register is encoded in the DREX byte.
8200 No REX prefix is used for these instructions, since the DREX field
8201 contains the 3 extension bits provided by the REX prefix. */
8202
8203static void
8204OP_DREX3 (int flag_bytemode, int sizeflag)
8205{
8206 unsigned int drex_byte;
8207 unsigned int regs[3];
8208 unsigned int modrm_regmem;
8209 unsigned int modrm_reg;
8210 unsigned int drex_reg;
8211 int bytemode;
8212 int rex_save = rex;
8213 int rex_used_save = rex_used;
8214 int has_sib = 0;
8215 int oc0;
8216 int i;
8217
8218 bytemode = flag_bytemode & ~ DREX_MASK;
8219
8220 for (i = 0; i < 3; i++)
8221 regs[i] = DREX_REG_UNKNOWN;
8222
8223 /* Determine if we have a SIB byte in addition to MODRM before the
8224 DREX byte. */
8225 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8226 && (modrm.mod != 3)
8227 && (modrm.rm == 4))
8228 has_sib = 1;
8229
8230 /* Get the DREX byte. */
8231 FETCH_DATA (the_info, codep + 2 + has_sib);
8232 drex_byte = codep[has_sib+1];
8233 drex_reg = DREX_XMM (drex_byte);
8234 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8235
8236 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8237 oc0 = DREX_OC0 (drex_byte);
8238 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8239 BadOp ();
8240
8241 if (modrm.mod == 3)
8242 {
8243 /* regmem == register */
8244 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8245 rex = rex_used = 0;
8246 /* skip modrm/drex since we don't call OP_E_extended. */
8247 codep += 2;
8248 }
8249 else
8250 {
8251 /* regmem == memory, fill in appropriate REX bits. */
8252 modrm_regmem = DREX_REG_MEMORY;
8253 rex = drex_byte & (REX_B | REX_X | REX_R);
8254 if (rex)
8255 rex |= REX_OPCODE;
8256 rex_used = rex;
8257 }
8258
8259 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8260 order. */
8261 switch (oc0)
8262 {
8263 default:
8264 BadOp ();
8265 return;
8266
8267 case 0:
8268 regs[0] = modrm_regmem;
8269 regs[1] = modrm_reg;
8270 regs[2] = drex_reg;
8271 break;
8272
8273 case 1:
8274 regs[0] = modrm_reg;
8275 regs[1] = modrm_regmem;
8276 regs[2] = drex_reg;
8277 break;
8278 }
8279
8280 /* Print out the arguments. */
8281 for (i = 0; i < 3; i++)
8282 {
8283 int j = (intel_syntax) ? 2 - i : i;
8284 if (i > 0)
8285 {
8286 *obufp++ = ',';
8287 *obufp = '\0';
8288 }
8289
8290 print_drex_arg (regs[j], bytemode, sizeflag);
8291 }
8292
8293 rex = rex_save;
8294 rex_used = rex_used_save;
8295}
8296
8297/* Emit a floating point comparison for comp<xx> instructions. */
8298
8299static void
8300OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8301 int sizeflag ATTRIBUTE_UNUSED)
8302{
8303 unsigned char byte;
8304
8305 static const char *const cmp_test[] = {
8306 "eq",
8307 "lt",
8308 "le",
8309 "unord",
8310 "ne",
8311 "nlt",
8312 "nle",
8313 "ord",
8314 "ueq",
8315 "ult",
8316 "ule",
8317 "false",
8318 "une",
8319 "unlt",
8320 "unle",
8321 "true"
8322 };
8323
8324 FETCH_DATA (the_info, codep + 1);
8325 byte = *codep & 0xff;
8326
8327 if (byte >= ARRAY_SIZE (cmp_test)
8328 || obuf[0] != 'c'
8329 || obuf[1] != 'o'
8330 || obuf[2] != 'm')
8331 {
8332 /* The instruction isn't one we know about, so just append the
8333 extension byte as a numeric value. */
8334 OP_I (b_mode, 0);
8335 }
8336
8337 else
8338 {
8339 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8340 strcpy (obuf, scratchbuf);
8341 codep++;
8342 }
8343}
8344
8345/* Emit an integer point comparison for pcom<xx> instructions,
8346 rewriting the instruction to have the test inside of it. */
8347
8348static void
8349OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8350 int sizeflag ATTRIBUTE_UNUSED)
8351{
8352 unsigned char byte;
8353
8354 static const char *const cmp_test[] = {
8355 "lt",
8356 "le",
8357 "gt",
8358 "ge",
8359 "eq",
8360 "ne",
8361 "false",
8362 "true"
8363 };
8364
8365 FETCH_DATA (the_info, codep + 1);
8366 byte = *codep & 0xff;
8367
8368 if (byte >= ARRAY_SIZE (cmp_test)
8369 || obuf[0] != 'p'
8370 || obuf[1] != 'c'
8371 || obuf[2] != 'o'
8372 || obuf[3] != 'm')
8373 {
8374 /* The instruction isn't one we know about, so just print the
8375 comparison test byte as a numeric value. */
8376 OP_I (b_mode, 0);
8377 }
8378
8379 else
8380 {
8381 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8382 strcpy (obuf, scratchbuf);
8383 codep++;
8384 }
8385}
GDB Binutils - Deliverables
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