Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0bfee649 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int fetch_data (struct disassemble_info *, bfd_byte *); |
46 | static void ckprefix (void); | |
47 | static const char *prefix_name (int, int); | |
48 | static int print_insn (bfd_vma, disassemble_info *); | |
49 | static void dofloat (int); | |
50 | static void OP_ST (int, int); | |
51 | static void OP_STi (int, int); | |
52 | static int putop (const char *, int); | |
53 | static void oappend (const char *); | |
54 | static void append_seg (void); | |
55 | static void OP_indirE (int, int); | |
56 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 57 | static void OP_E_register (int, int); |
c1e679ec DR |
58 | static void OP_E_memory (int, int); |
59 | static void OP_E_extended (int, int); | |
5d669648 | 60 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
61 | static void OP_E (int, int); |
62 | static void OP_G (int, int); | |
63 | static bfd_vma get64 (void); | |
64 | static bfd_signed_vma get32 (void); | |
65 | static bfd_signed_vma get32s (void); | |
66 | static int get16 (void); | |
67 | static void set_op (bfd_vma, int); | |
b844680a | 68 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
69 | static void OP_REG (int, int); |
70 | static void OP_IMREG (int, int); | |
71 | static void OP_I (int, int); | |
72 | static void OP_I64 (int, int); | |
73 | static void OP_sI (int, int); | |
74 | static void OP_J (int, int); | |
75 | static void OP_SEG (int, int); | |
76 | static void OP_DIR (int, int); | |
77 | static void OP_OFF (int, int); | |
78 | static void OP_OFF64 (int, int); | |
79 | static void ptr_reg (int, int); | |
80 | static void OP_ESreg (int, int); | |
81 | static void OP_DSreg (int, int); | |
82 | static void OP_C (int, int); | |
83 | static void OP_D (int, int); | |
84 | static void OP_T (int, int); | |
6f74c397 | 85 | static void OP_R (int, int); |
26ca5450 AJ |
86 | static void OP_MMX (int, int); |
87 | static void OP_XMM (int, int); | |
88 | static void OP_EM (int, int); | |
89 | static void OP_EX (int, int); | |
4d9567e0 MM |
90 | static void OP_EMC (int,int); |
91 | static void OP_MXC (int,int); | |
26ca5450 AJ |
92 | static void OP_MS (int, int); |
93 | static void OP_XS (int, int); | |
cc0ec051 | 94 | static void OP_M (int, int); |
c0f3af97 L |
95 | static void OP_VEX (int, int); |
96 | static void OP_EX_Vex (int, int); | |
c0f3af97 | 97 | static void OP_XMM_Vex (int, int); |
c0f3af97 L |
98 | static void OP_REG_VexI4 (int, int); |
99 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 L |
100 | static void VZERO_Fixup (int, int); |
101 | static void VCMP_Fixup (int, int); | |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
f5804c90 | 111 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 112 | static void XMM_Fixup (int, int); |
381d071f | 113 | static void CRC32_Fixup (int, int); |
c1e679ec | 114 | |
f1f8f695 | 115 | static void MOVBE_Fixup (int, int); |
252b5132 | 116 | |
6608db57 | 117 | struct dis_private { |
252b5132 RH |
118 | /* Points to first byte not fetched. */ |
119 | bfd_byte *max_fetched; | |
0b1cf022 | 120 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 121 | bfd_vma insn_start; |
e396998b | 122 | int orig_sizeflag; |
252b5132 RH |
123 | jmp_buf bailout; |
124 | }; | |
125 | ||
cb712a9e L |
126 | enum address_mode |
127 | { | |
128 | mode_16bit, | |
129 | mode_32bit, | |
130 | mode_64bit | |
131 | }; | |
132 | ||
133 | enum address_mode address_mode; | |
52b15da3 | 134 | |
5076851f ILT |
135 | /* Flags for the prefixes for the current instruction. See below. */ |
136 | static int prefixes; | |
137 | ||
52b15da3 JH |
138 | /* REX prefix the current instruction. See below. */ |
139 | static int rex; | |
140 | /* Bits of REX we've already used. */ | |
141 | static int rex_used; | |
c0f3af97 L |
142 | /* Original REX prefix. */ |
143 | static int rex_original; | |
144 | /* REX bits in original REX prefix ignored. It may not be the same | |
145 | as rex_original since some bits may not be ignored. */ | |
146 | static int rex_ignored; | |
52b15da3 JH |
147 | /* Mark parts used in the REX prefix. When we are testing for |
148 | empty prefix (for 8bit register REX extension), just mask it | |
149 | out. Otherwise test for REX bit is excuse for existence of REX | |
150 | only in case value is nonzero. */ | |
151 | #define USED_REX(value) \ | |
152 | { \ | |
153 | if (value) \ | |
161a04f6 L |
154 | { \ |
155 | if ((rex & value)) \ | |
156 | rex_used |= (value) | REX_OPCODE; \ | |
157 | } \ | |
52b15da3 | 158 | else \ |
161a04f6 | 159 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
160 | } |
161 | ||
7d421014 ILT |
162 | /* Flags for prefixes which we somehow handled when printing the |
163 | current instruction. */ | |
164 | static int used_prefixes; | |
165 | ||
5076851f ILT |
166 | /* Flags stored in PREFIXES. */ |
167 | #define PREFIX_REPZ 1 | |
168 | #define PREFIX_REPNZ 2 | |
169 | #define PREFIX_LOCK 4 | |
170 | #define PREFIX_CS 8 | |
171 | #define PREFIX_SS 0x10 | |
172 | #define PREFIX_DS 0x20 | |
173 | #define PREFIX_ES 0x40 | |
174 | #define PREFIX_FS 0x80 | |
175 | #define PREFIX_GS 0x100 | |
176 | #define PREFIX_DATA 0x200 | |
177 | #define PREFIX_ADDR 0x400 | |
178 | #define PREFIX_FWAIT 0x800 | |
179 | ||
252b5132 RH |
180 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
181 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
182 | on error. */ | |
183 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 184 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
185 | ? 1 : fetch_data ((info), (addr))) |
186 | ||
187 | static int | |
26ca5450 | 188 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
189 | { |
190 | int status; | |
6608db57 | 191 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
192 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
193 | ||
0b1cf022 | 194 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
195 | status = (*info->read_memory_func) (start, |
196 | priv->max_fetched, | |
197 | addr - priv->max_fetched, | |
198 | info); | |
199 | else | |
200 | status = -1; | |
252b5132 RH |
201 | if (status != 0) |
202 | { | |
7d421014 | 203 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
204 | print_insn_i386 will do something sensible. Otherwise, print |
205 | an error. We do that here because this is where we know | |
206 | STATUS. */ | |
7d421014 | 207 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 208 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
209 | longjmp (priv->bailout, 1); |
210 | } | |
211 | else | |
212 | priv->max_fetched = addr; | |
213 | return 1; | |
214 | } | |
215 | ||
ce518a5f L |
216 | #define XX { NULL, 0 } |
217 | ||
218 | #define Eb { OP_E, b_mode } | |
b6169b20 | 219 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 220 | #define Ev { OP_E, v_mode } |
b6169b20 | 221 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
222 | #define Ed { OP_E, d_mode } |
223 | #define Edq { OP_E, dq_mode } | |
224 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
225 | #define Edqb { OP_E, dqb_mode } |
226 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 227 | #define Eq { OP_E, q_mode } |
ce518a5f L |
228 | #define indirEv { OP_indirE, stack_v_mode } |
229 | #define indirEp { OP_indirE, f_mode } | |
230 | #define stackEv { OP_E, stack_v_mode } | |
231 | #define Em { OP_E, m_mode } | |
232 | #define Ew { OP_E, w_mode } | |
233 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 234 | #define Ma { OP_M, a_mode } |
b844680a | 235 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 236 | #define Md { OP_M, d_mode } |
f1f8f695 | 237 | #define Mo { OP_M, o_mode } |
ce518a5f L |
238 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
239 | #define Mq { OP_M, q_mode } | |
4ee52178 | 240 | #define Mx { OP_M, x_mode } |
c0f3af97 | 241 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f L |
242 | #define Gb { OP_G, b_mode } |
243 | #define Gv { OP_G, v_mode } | |
244 | #define Gd { OP_G, d_mode } | |
245 | #define Gdq { OP_G, dq_mode } | |
246 | #define Gm { OP_G, m_mode } | |
247 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
248 | #define Rd { OP_R, d_mode } |
249 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
250 | #define Ib { OP_I, b_mode } |
251 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
252 | #define Iv { OP_I, v_mode } | |
253 | #define Iq { OP_I, q_mode } | |
254 | #define Iv64 { OP_I64, v_mode } | |
255 | #define Iw { OP_I, w_mode } | |
256 | #define I1 { OP_I, const_1_mode } | |
257 | #define Jb { OP_J, b_mode } | |
258 | #define Jv { OP_J, v_mode } | |
259 | #define Cm { OP_C, m_mode } | |
260 | #define Dm { OP_D, m_mode } | |
261 | #define Td { OP_T, d_mode } | |
b844680a | 262 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
263 | |
264 | #define RMeAX { OP_REG, eAX_reg } | |
265 | #define RMeBX { OP_REG, eBX_reg } | |
266 | #define RMeCX { OP_REG, eCX_reg } | |
267 | #define RMeDX { OP_REG, eDX_reg } | |
268 | #define RMeSP { OP_REG, eSP_reg } | |
269 | #define RMeBP { OP_REG, eBP_reg } | |
270 | #define RMeSI { OP_REG, eSI_reg } | |
271 | #define RMeDI { OP_REG, eDI_reg } | |
272 | #define RMrAX { OP_REG, rAX_reg } | |
273 | #define RMrBX { OP_REG, rBX_reg } | |
274 | #define RMrCX { OP_REG, rCX_reg } | |
275 | #define RMrDX { OP_REG, rDX_reg } | |
276 | #define RMrSP { OP_REG, rSP_reg } | |
277 | #define RMrBP { OP_REG, rBP_reg } | |
278 | #define RMrSI { OP_REG, rSI_reg } | |
279 | #define RMrDI { OP_REG, rDI_reg } | |
280 | #define RMAL { OP_REG, al_reg } | |
281 | #define RMAL { OP_REG, al_reg } | |
282 | #define RMCL { OP_REG, cl_reg } | |
283 | #define RMDL { OP_REG, dl_reg } | |
284 | #define RMBL { OP_REG, bl_reg } | |
285 | #define RMAH { OP_REG, ah_reg } | |
286 | #define RMCH { OP_REG, ch_reg } | |
287 | #define RMDH { OP_REG, dh_reg } | |
288 | #define RMBH { OP_REG, bh_reg } | |
289 | #define RMAX { OP_REG, ax_reg } | |
290 | #define RMDX { OP_REG, dx_reg } | |
291 | ||
292 | #define eAX { OP_IMREG, eAX_reg } | |
293 | #define eBX { OP_IMREG, eBX_reg } | |
294 | #define eCX { OP_IMREG, eCX_reg } | |
295 | #define eDX { OP_IMREG, eDX_reg } | |
296 | #define eSP { OP_IMREG, eSP_reg } | |
297 | #define eBP { OP_IMREG, eBP_reg } | |
298 | #define eSI { OP_IMREG, eSI_reg } | |
299 | #define eDI { OP_IMREG, eDI_reg } | |
300 | #define AL { OP_IMREG, al_reg } | |
301 | #define CL { OP_IMREG, cl_reg } | |
302 | #define DL { OP_IMREG, dl_reg } | |
303 | #define BL { OP_IMREG, bl_reg } | |
304 | #define AH { OP_IMREG, ah_reg } | |
305 | #define CH { OP_IMREG, ch_reg } | |
306 | #define DH { OP_IMREG, dh_reg } | |
307 | #define BH { OP_IMREG, bh_reg } | |
308 | #define AX { OP_IMREG, ax_reg } | |
309 | #define DX { OP_IMREG, dx_reg } | |
310 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
311 | #define indirDX { OP_IMREG, indir_dx_reg } | |
312 | ||
313 | #define Sw { OP_SEG, w_mode } | |
314 | #define Sv { OP_SEG, v_mode } | |
315 | #define Ap { OP_DIR, 0 } | |
316 | #define Ob { OP_OFF64, b_mode } | |
317 | #define Ov { OP_OFF64, v_mode } | |
318 | #define Xb { OP_DSreg, eSI_reg } | |
319 | #define Xv { OP_DSreg, eSI_reg } | |
320 | #define Xz { OP_DSreg, eSI_reg } | |
321 | #define Yb { OP_ESreg, eDI_reg } | |
322 | #define Yv { OP_ESreg, eDI_reg } | |
323 | #define DSBX { OP_DSreg, eBX_reg } | |
324 | ||
325 | #define es { OP_REG, es_reg } | |
326 | #define ss { OP_REG, ss_reg } | |
327 | #define cs { OP_REG, cs_reg } | |
328 | #define ds { OP_REG, ds_reg } | |
329 | #define fs { OP_REG, fs_reg } | |
330 | #define gs { OP_REG, gs_reg } | |
331 | ||
332 | #define MX { OP_MMX, 0 } | |
333 | #define XM { OP_XMM, 0 } | |
c0f3af97 | 334 | #define XMM { OP_XMM, xmm_mode } |
ce518a5f | 335 | #define EM { OP_EM, v_mode } |
b6169b20 | 336 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 337 | #define EMd { OP_EM, d_mode } |
14051056 | 338 | #define EMx { OP_EM, x_mode } |
8976381e | 339 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 340 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 341 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 342 | #define EXq { OP_EX, q_mode } |
b6169b20 | 343 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 344 | #define EXx { OP_EX, x_mode } |
b6169b20 | 345 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 L |
346 | #define EXxmm { OP_EX, xmm_mode } |
347 | #define EXxmmq { OP_EX, xmmq_mode } | |
348 | #define EXymmq { OP_EX, ymmq_mode } | |
0bfee649 | 349 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
ce518a5f L |
350 | #define MS { OP_MS, v_mode } |
351 | #define XS { OP_XS, v_mode } | |
09335d05 | 352 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 353 | #define MXC { OP_MXC, 0 } |
ce518a5f | 354 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 355 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 356 | #define XMM0 { XMM_Fixup, 0 } |
252b5132 | 357 | |
c0f3af97 L |
358 | #define Vex { OP_VEX, vex_mode } |
359 | #define Vex128 { OP_VEX, vex128_mode } | |
360 | #define Vex256 { OP_VEX, vex256_mode } | |
c0f3af97 | 361 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 362 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
c0f3af97 | 363 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 364 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
c0f3af97 | 365 | #define XMVex { OP_XMM_Vex, 0 } |
c0f3af97 L |
366 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
367 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
368 | #define VZERO { VZERO_Fixup, 0 } | |
369 | #define VCMP { VCMP_Fixup, 0 } | |
c0f3af97 | 370 | |
35c52694 | 371 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
372 | #define Xbr { REP_Fixup, eSI_reg } |
373 | #define Xvr { REP_Fixup, eSI_reg } | |
374 | #define Ybr { REP_Fixup, eDI_reg } | |
375 | #define Yvr { REP_Fixup, eDI_reg } | |
376 | #define Yzr { REP_Fixup, eDI_reg } | |
377 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
378 | #define ALr { REP_Fixup, al_reg } | |
379 | #define eAXr { REP_Fixup, eAX_reg } | |
380 | ||
381 | #define cond_jump_flag { NULL, cond_jump_mode } | |
382 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 383 | |
252b5132 | 384 | /* bits in sizeflag */ |
252b5132 | 385 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
386 | #define AFLAG 2 |
387 | #define DFLAG 1 | |
388 | ||
d55ee72f L |
389 | /* byte operand */ |
390 | #define b_mode 1 | |
b6169b20 L |
391 | /* byte operand with operand swapped */ |
392 | #define b_swap_mode (b_mode + 1) | |
d55ee72f | 393 | /* operand size depends on prefixes */ |
b6169b20 L |
394 | #define v_mode (b_swap_mode + 1) |
395 | /* operand size depends on prefixes with operand swapped */ | |
396 | #define v_swap_mode (v_mode + 1) | |
d55ee72f | 397 | /* word operand */ |
b6169b20 | 398 | #define w_mode (v_swap_mode + 1) |
d55ee72f L |
399 | /* double word operand */ |
400 | #define d_mode (w_mode + 1) | |
fa99fab2 L |
401 | /* double word operand with operand swapped */ |
402 | #define d_swap_mode (d_mode + 1) | |
d55ee72f | 403 | /* quad word operand */ |
fa99fab2 | 404 | #define q_mode (d_swap_mode + 1) |
b6169b20 L |
405 | /* quad word operand with operand swapped */ |
406 | #define q_swap_mode (q_mode + 1) | |
d55ee72f | 407 | /* ten-byte operand */ |
b6169b20 | 408 | #define t_mode (q_swap_mode + 1) |
c0f3af97 | 409 | /* 16-byte XMM or 32-byte YMM operand */ |
d55ee72f | 410 | #define x_mode (t_mode + 1) |
b6169b20 L |
411 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
412 | #define x_swap_mode (x_mode + 1) | |
c0f3af97 | 413 | /* 16-byte XMM operand */ |
b6169b20 | 414 | #define xmm_mode (x_swap_mode + 1) |
c0f3af97 L |
415 | /* 16-byte XMM or quad word operand */ |
416 | #define xmmq_mode (xmm_mode + 1) | |
417 | /* 32-byte YMM or quad word operand */ | |
418 | #define ymmq_mode (xmmq_mode + 1) | |
d55ee72f | 419 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
c0f3af97 | 420 | #define m_mode (ymmq_mode + 1) |
34b772a6 JB |
421 | /* pair of v_mode operands */ |
422 | #define a_mode (m_mode + 1) | |
423 | #define cond_jump_mode (a_mode + 1) | |
d55ee72f L |
424 | #define loop_jcxz_mode (cond_jump_mode + 1) |
425 | /* operand size depends on REX prefixes. */ | |
426 | #define dq_mode (loop_jcxz_mode + 1) | |
427 | /* registers like dq_mode, memory like w_mode. */ | |
428 | #define dqw_mode (dq_mode + 1) | |
429 | /* 4- or 6-byte pointer operand */ | |
430 | #define f_mode (dqw_mode + 1) | |
431 | #define const_1_mode (f_mode + 1) | |
432 | /* v_mode for stack-related opcodes. */ | |
433 | #define stack_v_mode (const_1_mode + 1) | |
434 | /* non-quad operand size depends on prefixes */ | |
435 | #define z_mode (stack_v_mode + 1) | |
436 | /* 16-byte operand */ | |
437 | #define o_mode (z_mode + 1) | |
438 | /* registers like dq_mode, memory like b_mode. */ | |
439 | #define dqb_mode (o_mode + 1) | |
440 | /* registers like dq_mode, memory like d_mode. */ | |
441 | #define dqd_mode (dqb_mode + 1) | |
c0f3af97 L |
442 | /* normal vex mode */ |
443 | #define vex_mode (dqd_mode + 1) | |
444 | /* 128bit vex mode */ | |
445 | #define vex128_mode (vex_mode + 1) | |
446 | /* 256bit vex mode */ | |
447 | #define vex256_mode (vex128_mode + 1) | |
0bfee649 L |
448 | /* operand size depends on the VEX.W bit. */ |
449 | #define vex_w_dq_mode (vex256_mode + 1) | |
c0f3af97 | 450 | |
0bfee649 | 451 | #define es_reg (vex_w_dq_mode + 1) |
d55ee72f L |
452 | #define cs_reg (es_reg + 1) |
453 | #define ss_reg (cs_reg + 1) | |
454 | #define ds_reg (ss_reg + 1) | |
455 | #define fs_reg (ds_reg + 1) | |
456 | #define gs_reg (fs_reg + 1) | |
457 | ||
458 | #define eAX_reg (gs_reg + 1) | |
459 | #define eCX_reg (eAX_reg + 1) | |
460 | #define eDX_reg (eCX_reg + 1) | |
461 | #define eBX_reg (eDX_reg + 1) | |
462 | #define eSP_reg (eBX_reg + 1) | |
463 | #define eBP_reg (eSP_reg + 1) | |
464 | #define eSI_reg (eBP_reg + 1) | |
465 | #define eDI_reg (eSI_reg + 1) | |
466 | ||
467 | #define al_reg (eDI_reg + 1) | |
468 | #define cl_reg (al_reg + 1) | |
469 | #define dl_reg (cl_reg + 1) | |
470 | #define bl_reg (dl_reg + 1) | |
471 | #define ah_reg (bl_reg + 1) | |
472 | #define ch_reg (ah_reg + 1) | |
473 | #define dh_reg (ch_reg + 1) | |
474 | #define bh_reg (dh_reg + 1) | |
475 | ||
476 | #define ax_reg (bh_reg + 1) | |
477 | #define cx_reg (ax_reg + 1) | |
478 | #define dx_reg (cx_reg + 1) | |
479 | #define bx_reg (dx_reg + 1) | |
480 | #define sp_reg (bx_reg + 1) | |
481 | #define bp_reg (sp_reg + 1) | |
482 | #define si_reg (bp_reg + 1) | |
483 | #define di_reg (si_reg + 1) | |
484 | ||
485 | #define rAX_reg (di_reg + 1) | |
486 | #define rCX_reg (rAX_reg + 1) | |
487 | #define rDX_reg (rCX_reg + 1) | |
488 | #define rBX_reg (rDX_reg + 1) | |
489 | #define rSP_reg (rBX_reg + 1) | |
490 | #define rBP_reg (rSP_reg + 1) | |
491 | #define rSI_reg (rBP_reg + 1) | |
492 | #define rDI_reg (rSI_reg + 1) | |
493 | ||
494 | #define z_mode_ax_reg (rDI_reg + 1) | |
495 | #define indir_dx_reg (z_mode_ax_reg + 1) | |
496 | ||
497 | #define MAX_BYTEMODE indir_dx_reg | |
498 | ||
252b5132 | 499 | |
1b0d430b L |
500 | #define FLOATCODE 1 |
501 | #define USE_REG_TABLE (FLOATCODE + 1) | |
502 | #define USE_MOD_TABLE (USE_REG_TABLE + 1) | |
503 | #define USE_RM_TABLE (USE_MOD_TABLE + 1) | |
504 | #define USE_PREFIX_TABLE (USE_RM_TABLE + 1) | |
505 | #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1) | |
506 | #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1) | |
c0f3af97 L |
507 | #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1) |
508 | #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1) | |
509 | #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1) | |
6439fc28 | 510 | |
1ceb70f8 | 511 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 512 | |
4e7d34a6 | 513 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
514 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
515 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
516 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
517 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
518 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
519 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
c0f3af97 L |
520 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
521 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
522 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
1ceb70f8 L |
523 | |
524 | #define REG_80 0 | |
525 | #define REG_81 (REG_80 + 1) | |
526 | #define REG_82 (REG_81 + 1) | |
527 | #define REG_8F (REG_82 + 1) | |
528 | #define REG_C0 (REG_8F + 1) | |
529 | #define REG_C1 (REG_C0 + 1) | |
530 | #define REG_C6 (REG_C1 + 1) | |
531 | #define REG_C7 (REG_C6 + 1) | |
532 | #define REG_D0 (REG_C7 + 1) | |
533 | #define REG_D1 (REG_D0 + 1) | |
534 | #define REG_D2 (REG_D1 + 1) | |
535 | #define REG_D3 (REG_D2 + 1) | |
536 | #define REG_F6 (REG_D3 + 1) | |
537 | #define REG_F7 (REG_F6 + 1) | |
538 | #define REG_FE (REG_F7 + 1) | |
539 | #define REG_FF (REG_FE + 1) | |
540 | #define REG_0F00 (REG_FF + 1) | |
541 | #define REG_0F01 (REG_0F00 + 1) | |
b5b1fc4f L |
542 | #define REG_0F0D (REG_0F01 + 1) |
543 | #define REG_0F18 (REG_0F0D + 1) | |
1ceb70f8 L |
544 | #define REG_0F71 (REG_0F18 + 1) |
545 | #define REG_0F72 (REG_0F71 + 1) | |
546 | #define REG_0F73 (REG_0F72 + 1) | |
547 | #define REG_0FA6 (REG_0F73 + 1) | |
548 | #define REG_0FA7 (REG_0FA6 + 1) | |
549 | #define REG_0FAE (REG_0FA7 + 1) | |
550 | #define REG_0FBA (REG_0FAE + 1) | |
551 | #define REG_0FC7 (REG_0FBA + 1) | |
c0f3af97 L |
552 | #define REG_VEX_71 (REG_0FC7 + 1) |
553 | #define REG_VEX_72 (REG_VEX_71 + 1) | |
554 | #define REG_VEX_73 (REG_VEX_72 + 1) | |
555 | #define REG_VEX_AE (REG_VEX_73 + 1) | |
1ceb70f8 L |
556 | |
557 | #define MOD_8D 0 | |
92fddf8e | 558 | #define MOD_0F01_REG_0 (MOD_8D + 1) |
1ceb70f8 L |
559 | #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1) |
560 | #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1) | |
561 | #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1) | |
562 | #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1) | |
92fddf8e L |
563 | #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1) |
564 | #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1) | |
565 | #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1) | |
566 | #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1) | |
567 | #define MOD_0F18_REG_0 (MOD_0F17 + 1) | |
1ceb70f8 L |
568 | #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1) |
569 | #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1) | |
570 | #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1) | |
92fddf8e L |
571 | #define MOD_0F20 (MOD_0F18_REG_3 + 1) |
572 | #define MOD_0F21 (MOD_0F20 + 1) | |
573 | #define MOD_0F22 (MOD_0F21 + 1) | |
574 | #define MOD_0F23 (MOD_0F22 + 1) | |
575 | #define MOD_0F24 (MOD_0F23 + 1) | |
576 | #define MOD_0F26 (MOD_0F24 + 1) | |
75c135a8 L |
577 | #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1) |
578 | #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1) | |
579 | #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1) | |
580 | #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1) | |
581 | #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1) | |
582 | #define MOD_0F71_REG_2 (MOD_0F51 + 1) | |
1ceb70f8 L |
583 | #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1) |
584 | #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1) | |
585 | #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1) | |
586 | #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1) | |
587 | #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1) | |
588 | #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1) | |
589 | #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1) | |
590 | #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1) | |
591 | #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1) | |
592 | #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1) | |
593 | #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1) | |
594 | #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1) | |
595 | #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1) | |
475a2301 L |
596 | #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1) |
597 | #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1) | |
1ceb70f8 L |
598 | #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1) |
599 | #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1) | |
92fddf8e L |
600 | #define MOD_0FB2 (MOD_0FAE_REG_7 + 1) |
601 | #define MOD_0FB4 (MOD_0FB2 + 1) | |
602 | #define MOD_0FB5 (MOD_0FB4 + 1) | |
603 | #define MOD_0FC7_REG_6 (MOD_0FB5 + 1) | |
1ceb70f8 | 604 | #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1) |
75c135a8 L |
605 | #define MOD_0FD7 (MOD_0FC7_REG_7 + 1) |
606 | #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1) | |
607 | #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1) | |
608 | #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1) | |
609 | #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1) | |
1ceb70f8 L |
610 | #define MOD_C4_32BIT (MOD_62_32BIT + 1) |
611 | #define MOD_C5_32BIT (MOD_C4_32BIT + 1) | |
c0f3af97 L |
612 | #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1) |
613 | #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1) | |
614 | #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1) | |
615 | #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1) | |
616 | #define MOD_VEX_2B (MOD_VEX_17 + 1) | |
617 | #define MOD_VEX_51 (MOD_VEX_2B + 1) | |
618 | #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1) | |
619 | #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1) | |
620 | #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1) | |
621 | #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1) | |
622 | #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1) | |
623 | #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1) | |
624 | #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1) | |
625 | #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1) | |
626 | #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1) | |
627 | #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1) | |
628 | #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1) | |
629 | #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1) | |
630 | #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1) | |
631 | #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1) | |
632 | #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1) | |
633 | #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1) | |
634 | #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1) | |
635 | #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1) | |
636 | #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1) | |
637 | #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1) | |
638 | #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1) | |
639 | #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1) | |
640 | #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1) | |
1ceb70f8 L |
641 | |
642 | #define RM_0F01_REG_0 0 | |
643 | #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1) | |
475a2301 L |
644 | #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1) |
645 | #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1) | |
1ceb70f8 L |
646 | #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1) |
647 | #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1) | |
648 | #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1) | |
649 | #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1) | |
650 | ||
651 | #define PREFIX_90 0 | |
652 | #define PREFIX_0F10 (PREFIX_90 + 1) | |
653 | #define PREFIX_0F11 (PREFIX_0F10 + 1) | |
654 | #define PREFIX_0F12 (PREFIX_0F11 + 1) | |
655 | #define PREFIX_0F16 (PREFIX_0F12 + 1) | |
656 | #define PREFIX_0F2A (PREFIX_0F16 + 1) | |
657 | #define PREFIX_0F2B (PREFIX_0F2A + 1) | |
658 | #define PREFIX_0F2C (PREFIX_0F2B + 1) | |
659 | #define PREFIX_0F2D (PREFIX_0F2C + 1) | |
660 | #define PREFIX_0F2E (PREFIX_0F2D + 1) | |
661 | #define PREFIX_0F2F (PREFIX_0F2E + 1) | |
662 | #define PREFIX_0F51 (PREFIX_0F2F + 1) | |
663 | #define PREFIX_0F52 (PREFIX_0F51 + 1) | |
664 | #define PREFIX_0F53 (PREFIX_0F52 + 1) | |
665 | #define PREFIX_0F58 (PREFIX_0F53 + 1) | |
666 | #define PREFIX_0F59 (PREFIX_0F58 + 1) | |
667 | #define PREFIX_0F5A (PREFIX_0F59 + 1) | |
668 | #define PREFIX_0F5B (PREFIX_0F5A + 1) | |
669 | #define PREFIX_0F5C (PREFIX_0F5B + 1) | |
670 | #define PREFIX_0F5D (PREFIX_0F5C + 1) | |
671 | #define PREFIX_0F5E (PREFIX_0F5D + 1) | |
672 | #define PREFIX_0F5F (PREFIX_0F5E + 1) | |
673 | #define PREFIX_0F60 (PREFIX_0F5F + 1) | |
674 | #define PREFIX_0F61 (PREFIX_0F60 + 1) | |
675 | #define PREFIX_0F62 (PREFIX_0F61 + 1) | |
676 | #define PREFIX_0F6C (PREFIX_0F62 + 1) | |
677 | #define PREFIX_0F6D (PREFIX_0F6C + 1) | |
678 | #define PREFIX_0F6F (PREFIX_0F6D + 1) | |
679 | #define PREFIX_0F70 (PREFIX_0F6F + 1) | |
92fddf8e L |
680 | #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1) |
681 | #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1) | |
682 | #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1) | |
1ceb70f8 L |
683 | #define PREFIX_0F79 (PREFIX_0F78 + 1) |
684 | #define PREFIX_0F7C (PREFIX_0F79 + 1) | |
685 | #define PREFIX_0F7D (PREFIX_0F7C + 1) | |
686 | #define PREFIX_0F7E (PREFIX_0F7D + 1) | |
687 | #define PREFIX_0F7F (PREFIX_0F7E + 1) | |
688 | #define PREFIX_0FB8 (PREFIX_0F7F + 1) | |
689 | #define PREFIX_0FBD (PREFIX_0FB8 + 1) | |
690 | #define PREFIX_0FC2 (PREFIX_0FBD + 1) | |
4ee52178 L |
691 | #define PREFIX_0FC3 (PREFIX_0FC2 + 1) |
692 | #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1) | |
92fddf8e | 693 | #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1) |
1ceb70f8 L |
694 | #define PREFIX_0FD6 (PREFIX_0FD0 + 1) |
695 | #define PREFIX_0FE6 (PREFIX_0FD6 + 1) | |
696 | #define PREFIX_0FE7 (PREFIX_0FE6 + 1) | |
697 | #define PREFIX_0FF0 (PREFIX_0FE7 + 1) | |
698 | #define PREFIX_0FF7 (PREFIX_0FF0 + 1) | |
699 | #define PREFIX_0F3810 (PREFIX_0FF7 + 1) | |
700 | #define PREFIX_0F3814 (PREFIX_0F3810 + 1) | |
701 | #define PREFIX_0F3815 (PREFIX_0F3814 + 1) | |
702 | #define PREFIX_0F3817 (PREFIX_0F3815 + 1) | |
703 | #define PREFIX_0F3820 (PREFIX_0F3817 + 1) | |
704 | #define PREFIX_0F3821 (PREFIX_0F3820 + 1) | |
705 | #define PREFIX_0F3822 (PREFIX_0F3821 + 1) | |
706 | #define PREFIX_0F3823 (PREFIX_0F3822 + 1) | |
707 | #define PREFIX_0F3824 (PREFIX_0F3823 + 1) | |
708 | #define PREFIX_0F3825 (PREFIX_0F3824 + 1) | |
709 | #define PREFIX_0F3828 (PREFIX_0F3825 + 1) | |
710 | #define PREFIX_0F3829 (PREFIX_0F3828 + 1) | |
711 | #define PREFIX_0F382A (PREFIX_0F3829 + 1) | |
712 | #define PREFIX_0F382B (PREFIX_0F382A + 1) | |
713 | #define PREFIX_0F3830 (PREFIX_0F382B + 1) | |
714 | #define PREFIX_0F3831 (PREFIX_0F3830 + 1) | |
715 | #define PREFIX_0F3832 (PREFIX_0F3831 + 1) | |
716 | #define PREFIX_0F3833 (PREFIX_0F3832 + 1) | |
717 | #define PREFIX_0F3834 (PREFIX_0F3833 + 1) | |
718 | #define PREFIX_0F3835 (PREFIX_0F3834 + 1) | |
719 | #define PREFIX_0F3837 (PREFIX_0F3835 + 1) | |
720 | #define PREFIX_0F3838 (PREFIX_0F3837 + 1) | |
721 | #define PREFIX_0F3839 (PREFIX_0F3838 + 1) | |
722 | #define PREFIX_0F383A (PREFIX_0F3839 + 1) | |
723 | #define PREFIX_0F383B (PREFIX_0F383A + 1) | |
724 | #define PREFIX_0F383C (PREFIX_0F383B + 1) | |
725 | #define PREFIX_0F383D (PREFIX_0F383C + 1) | |
726 | #define PREFIX_0F383E (PREFIX_0F383D + 1) | |
727 | #define PREFIX_0F383F (PREFIX_0F383E + 1) | |
728 | #define PREFIX_0F3840 (PREFIX_0F383F + 1) | |
729 | #define PREFIX_0F3841 (PREFIX_0F3840 + 1) | |
f1f8f695 L |
730 | #define PREFIX_0F3880 (PREFIX_0F3841 + 1) |
731 | #define PREFIX_0F3881 (PREFIX_0F3880 + 1) | |
732 | #define PREFIX_0F38DB (PREFIX_0F3881 + 1) | |
c0f3af97 L |
733 | #define PREFIX_0F38DC (PREFIX_0F38DB + 1) |
734 | #define PREFIX_0F38DD (PREFIX_0F38DC + 1) | |
735 | #define PREFIX_0F38DE (PREFIX_0F38DD + 1) | |
736 | #define PREFIX_0F38DF (PREFIX_0F38DE + 1) | |
737 | #define PREFIX_0F38F0 (PREFIX_0F38DF + 1) | |
1ceb70f8 L |
738 | #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1) |
739 | #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1) | |
740 | #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1) | |
741 | #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1) | |
742 | #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1) | |
743 | #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1) | |
744 | #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1) | |
745 | #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1) | |
746 | #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1) | |
747 | #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1) | |
748 | #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1) | |
749 | #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1) | |
750 | #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1) | |
751 | #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1) | |
752 | #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1) | |
753 | #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1) | |
754 | #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1) | |
755 | #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1) | |
c0f3af97 L |
756 | #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1) |
757 | #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1) | |
1ceb70f8 L |
758 | #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1) |
759 | #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1) | |
760 | #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1) | |
c0f3af97 L |
761 | #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1) |
762 | #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1) | |
763 | #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1) | |
764 | #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1) | |
765 | #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1) | |
766 | #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1) | |
767 | #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1) | |
768 | #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1) | |
769 | #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1) | |
770 | #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1) | |
771 | #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1) | |
772 | #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1) | |
773 | #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1) | |
774 | #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1) | |
775 | #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1) | |
776 | #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1) | |
777 | #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1) | |
778 | #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1) | |
779 | #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1) | |
780 | #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1) | |
781 | #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1) | |
782 | #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1) | |
783 | #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1) | |
784 | #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1) | |
785 | #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1) | |
786 | #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1) | |
787 | #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1) | |
788 | #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1) | |
789 | #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1) | |
790 | #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1) | |
791 | #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1) | |
792 | #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1) | |
793 | #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1) | |
794 | #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1) | |
795 | #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1) | |
796 | #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1) | |
797 | #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1) | |
798 | #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1) | |
799 | #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1) | |
800 | #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1) | |
801 | #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1) | |
802 | #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1) | |
803 | #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1) | |
804 | #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1) | |
805 | #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1) | |
806 | #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1) | |
807 | #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1) | |
808 | #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1) | |
809 | #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1) | |
810 | #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1) | |
811 | #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1) | |
812 | #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1) | |
813 | #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1) | |
814 | #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1) | |
815 | #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1) | |
816 | #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1) | |
817 | #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1) | |
818 | #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1) | |
819 | #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1) | |
820 | #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1) | |
821 | #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1) | |
822 | #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1) | |
823 | #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1) | |
824 | #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1) | |
825 | #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1) | |
826 | #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1) | |
827 | #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1) | |
828 | #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1) | |
829 | #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1) | |
830 | #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1) | |
831 | #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1) | |
832 | #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1) | |
833 | #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1) | |
834 | #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1) | |
835 | #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1) | |
836 | #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1) | |
837 | #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1) | |
838 | #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1) | |
839 | #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1) | |
840 | #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1) | |
841 | #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1) | |
842 | #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1) | |
843 | #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1) | |
844 | #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1) | |
845 | #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1) | |
846 | #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1) | |
847 | #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1) | |
848 | #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1) | |
849 | #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1) | |
850 | #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1) | |
851 | #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1) | |
852 | #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1) | |
853 | #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1) | |
854 | #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1) | |
855 | #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1) | |
856 | #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1) | |
857 | #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1) | |
858 | #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1) | |
859 | #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1) | |
860 | #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1) | |
861 | #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1) | |
862 | #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1) | |
863 | #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1) | |
864 | #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1) | |
865 | #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1) | |
866 | #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1) | |
06c8514a L |
867 | #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1) |
868 | #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1) | |
869 | #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1) | |
870 | #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1) | |
871 | #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1) | |
872 | #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1) | |
873 | #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1) | |
874 | #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1) | |
875 | #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1) | |
876 | #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1) | |
877 | #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1) | |
878 | #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1) | |
879 | #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1) | |
880 | #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1) | |
881 | #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1) | |
882 | #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1) | |
883 | #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1) | |
884 | #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1) | |
885 | #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1) | |
886 | #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1) | |
887 | #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1) | |
888 | #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1) | |
889 | #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1) | |
890 | #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1) | |
891 | #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1) | |
892 | #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1) | |
893 | #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1) | |
894 | #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1) | |
895 | #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1) | |
896 | #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1) | |
897 | #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1) | |
898 | #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1) | |
899 | #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1) | |
900 | #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1) | |
901 | #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1) | |
902 | #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1) | |
903 | #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1) | |
904 | #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1) | |
905 | #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1) | |
906 | #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1) | |
907 | #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1) | |
908 | #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1) | |
909 | #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1) | |
910 | #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1) | |
911 | #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1) | |
912 | #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1) | |
913 | #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1) | |
914 | #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1) | |
915 | #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1) | |
916 | #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1) | |
917 | #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1) | |
918 | #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1) | |
919 | #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1) | |
920 | #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1) | |
0bfee649 L |
921 | #define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1) |
922 | #define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1) | |
923 | #define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1) | |
924 | #define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1) | |
925 | #define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1) | |
926 | #define PREFIX_VEX_389B (PREFIX_VEX_389A + 1) | |
927 | #define PREFIX_VEX_389C (PREFIX_VEX_389B + 1) | |
928 | #define PREFIX_VEX_389D (PREFIX_VEX_389C + 1) | |
929 | #define PREFIX_VEX_389E (PREFIX_VEX_389D + 1) | |
930 | #define PREFIX_VEX_389F (PREFIX_VEX_389E + 1) | |
931 | #define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1) | |
932 | #define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1) | |
933 | #define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1) | |
934 | #define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1) | |
935 | #define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1) | |
936 | #define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1) | |
937 | #define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1) | |
938 | #define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1) | |
939 | #define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1) | |
940 | #define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1) | |
941 | #define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1) | |
942 | #define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1) | |
943 | #define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1) | |
944 | #define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1) | |
945 | #define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1) | |
946 | #define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1) | |
947 | #define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1) | |
948 | #define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1) | |
949 | #define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1) | |
950 | #define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1) | |
951 | #define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1) | |
a5ff0eb2 L |
952 | #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1) |
953 | #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1) | |
954 | #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1) | |
955 | #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1) | |
956 | #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1) | |
06c8514a L |
957 | #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1) |
958 | #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1) | |
959 | #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1) | |
960 | #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1) | |
961 | #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1) | |
962 | #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1) | |
963 | #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1) | |
964 | #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1) | |
965 | #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1) | |
966 | #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1) | |
967 | #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1) | |
968 | #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1) | |
969 | #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1) | |
970 | #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1) | |
971 | #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1) | |
972 | #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1) | |
973 | #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1) | |
974 | #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1) | |
975 | #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1) | |
976 | #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1) | |
977 | #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1) | |
978 | #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1) | |
ce2f5b3c L |
979 | #define PREFIX_VEX_3A44 (PREFIX_VEX_3A42 + 1) |
980 | #define PREFIX_VEX_3A4A (PREFIX_VEX_3A44 + 1) | |
06c8514a L |
981 | #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1) |
982 | #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1) | |
0bfee649 | 983 | #define PREFIX_VEX_3A60 (PREFIX_VEX_3A4C + 1) |
06c8514a L |
984 | #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1) |
985 | #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1) | |
986 | #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1) | |
0bfee649 | 987 | #define PREFIX_VEX_3ADF (PREFIX_VEX_3A63 + 1) |
4e7d34a6 L |
988 | |
989 | #define X86_64_06 0 | |
990 | #define X86_64_07 (X86_64_06 + 1) | |
991 | #define X86_64_0D (X86_64_07 + 1) | |
992 | #define X86_64_16 (X86_64_0D + 1) | |
993 | #define X86_64_17 (X86_64_16 + 1) | |
994 | #define X86_64_1E (X86_64_17 + 1) | |
995 | #define X86_64_1F (X86_64_1E + 1) | |
996 | #define X86_64_27 (X86_64_1F + 1) | |
997 | #define X86_64_2F (X86_64_27 + 1) | |
998 | #define X86_64_37 (X86_64_2F + 1) | |
999 | #define X86_64_3F (X86_64_37 + 1) | |
1000 | #define X86_64_60 (X86_64_3F + 1) | |
1001 | #define X86_64_61 (X86_64_60 + 1) | |
1002 | #define X86_64_62 (X86_64_61 + 1) | |
1003 | #define X86_64_63 (X86_64_62 + 1) | |
1004 | #define X86_64_6D (X86_64_63 + 1) | |
1005 | #define X86_64_6F (X86_64_6D + 1) | |
1006 | #define X86_64_9A (X86_64_6F + 1) | |
1007 | #define X86_64_C4 (X86_64_9A + 1) | |
1008 | #define X86_64_C5 (X86_64_C4 + 1) | |
1009 | #define X86_64_CE (X86_64_C5 + 1) | |
1010 | #define X86_64_D4 (X86_64_CE + 1) | |
1011 | #define X86_64_D5 (X86_64_D4 + 1) | |
1012 | #define X86_64_EA (X86_64_D5 + 1) | |
1013 | #define X86_64_0F01_REG_0 (X86_64_EA + 1) | |
1014 | #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1) | |
1015 | #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1) | |
1016 | #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1) | |
1017 | ||
c1e679ec | 1018 | #define THREE_BYTE_0F38 0 |
4e7d34a6 L |
1019 | #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1) |
1020 | #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1) | |
4e7d34a6 | 1021 | |
c0f3af97 L |
1022 | #define VEX_0F 0 |
1023 | #define VEX_0F38 (VEX_0F + 1) | |
1024 | #define VEX_0F3A (VEX_0F38 + 1) | |
1025 | ||
1026 | #define VEX_LEN_10_P_1 0 | |
1027 | #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1) | |
1028 | #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1) | |
1029 | #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1) | |
1030 | #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1) | |
1031 | #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1) | |
1032 | #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1) | |
1033 | #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1) | |
1034 | #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1) | |
1035 | #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1) | |
1036 | #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1) | |
1037 | #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1) | |
1038 | #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1) | |
1039 | #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1) | |
168e3097 | 1040 | #define VEX_LEN_2C_P_1 (VEX_LEN_2A_P_3 + 1) |
c0f3af97 L |
1041 | #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1) |
1042 | #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1) | |
1043 | #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1) | |
1044 | #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1) | |
1045 | #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1) | |
1046 | #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1) | |
1047 | #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1) | |
1048 | #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1) | |
1049 | #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1) | |
1050 | #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1) | |
1051 | #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1) | |
1052 | #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1) | |
1053 | #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1) | |
1054 | #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1) | |
1055 | #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1) | |
1056 | #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1) | |
1057 | #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1) | |
1058 | #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1) | |
1059 | #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1) | |
1060 | #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1) | |
1061 | #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1) | |
1062 | #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1) | |
1063 | #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1) | |
1064 | #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1) | |
1065 | #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1) | |
1066 | #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1) | |
1067 | #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1) | |
1068 | #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1) | |
1069 | #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1) | |
1070 | #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1) | |
1071 | #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1) | |
1072 | #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1) | |
1073 | #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1) | |
1074 | #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1) | |
1075 | #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1) | |
1076 | #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1) | |
1077 | #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1) | |
1078 | #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1) | |
1079 | #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1) | |
1080 | #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1) | |
1081 | #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1) | |
1082 | #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1) | |
1083 | #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1) | |
1084 | #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1) | |
1085 | #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1) | |
1086 | #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1) | |
1087 | #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1) | |
1088 | #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1) | |
1089 | #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1) | |
1090 | #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1) | |
1091 | #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1) | |
1092 | #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1) | |
1093 | #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1) | |
1094 | #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1) | |
1095 | #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1) | |
1096 | #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1) | |
1097 | #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1) | |
1098 | #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1) | |
1099 | #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1) | |
1100 | #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1) | |
1101 | #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1) | |
1102 | #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1) | |
1103 | #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1) | |
1104 | #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1) | |
1105 | #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1) | |
1106 | #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1) | |
1107 | #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1) | |
1108 | #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1) | |
1109 | #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1) | |
1110 | #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1) | |
1111 | #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1) | |
1112 | #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1) | |
1113 | #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1) | |
1114 | #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1) | |
1115 | #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1) | |
1116 | #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1) | |
1117 | #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1) | |
1118 | #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1) | |
1119 | #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1) | |
1120 | #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1) | |
1121 | #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1) | |
1122 | #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1) | |
1123 | #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1) | |
1124 | #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1) | |
1125 | #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1) | |
168e3097 | 1126 | #define VEX_LEN_E8_P_2 (VEX_LEN_E5_P_2 + 1) |
c0f3af97 L |
1127 | #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1) |
1128 | #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1) | |
1129 | #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1) | |
1130 | #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1) | |
1131 | #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1) | |
1132 | #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1) | |
1133 | #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1) | |
1134 | #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1) | |
1135 | #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1) | |
1136 | #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1) | |
1137 | #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1) | |
1138 | #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1) | |
1139 | #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1) | |
1140 | #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1) | |
1141 | #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1) | |
1142 | #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1) | |
1143 | #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1) | |
1144 | #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1) | |
1145 | #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1) | |
1146 | #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1) | |
1147 | #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1) | |
1148 | #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1) | |
1149 | #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1) | |
1150 | #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1) | |
1151 | #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1) | |
1152 | #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1) | |
1153 | #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1) | |
1154 | #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1) | |
1155 | #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1) | |
1156 | #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1) | |
1157 | #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1) | |
1158 | #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1) | |
1159 | #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1) | |
1160 | #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1) | |
1161 | #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1) | |
1162 | #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1) | |
1163 | #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1) | |
1164 | #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1) | |
1165 | #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1) | |
1166 | #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1) | |
1167 | #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1) | |
1168 | #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1) | |
1169 | #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1) | |
1170 | #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1) | |
1171 | #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1) | |
1172 | #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1) | |
1173 | #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1) | |
1174 | #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1) | |
1175 | #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1) | |
1176 | #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1) | |
1177 | #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1) | |
1178 | #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1) | |
1179 | #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1) | |
1180 | #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1) | |
1181 | #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1) | |
1182 | #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1) | |
1183 | #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1) | |
1184 | #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1) | |
1185 | #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1) | |
1186 | #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1) | |
1187 | #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1) | |
1188 | #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1) | |
1189 | #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1) | |
1190 | #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1) | |
1191 | #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1) | |
a5ff0eb2 L |
1192 | #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1) |
1193 | #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1) | |
1194 | #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1) | |
1195 | #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1) | |
1196 | #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1) | |
1197 | #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1) | |
c0f3af97 L |
1198 | #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1) |
1199 | #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1) | |
1200 | #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1) | |
1201 | #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1) | |
1202 | #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1) | |
1203 | #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1) | |
1204 | #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1) | |
1205 | #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1) | |
1206 | #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1) | |
1207 | #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1) | |
1208 | #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1) | |
1209 | #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1) | |
1210 | #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1) | |
1211 | #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1) | |
1212 | #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1) | |
ce2f5b3c L |
1213 | #define VEX_LEN_3A44_P_2 (VEX_LEN_3A42_P_2 + 1) |
1214 | #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A44_P_2 + 1) | |
c0f3af97 L |
1215 | #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1) |
1216 | #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1) | |
1217 | #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1) | |
1218 | #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1) | |
0bfee649 | 1219 | #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A63_P_2 + 1) |
c0f3af97 | 1220 | |
26ca5450 | 1221 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1222 | |
1223 | struct dis386 { | |
2da11e11 | 1224 | const char *name; |
ce518a5f L |
1225 | struct |
1226 | { | |
1227 | op_rtn rtn; | |
1228 | int bytemode; | |
1229 | } op[MAX_OPERANDS]; | |
252b5132 RH |
1230 | }; |
1231 | ||
1232 | /* Upper case letters in the instruction names here are macros. | |
1233 | 'A' => print 'b' if no register operands or suffix_always is true | |
1234 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1235 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1236 | size prefix |
ed7841b3 | 1237 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1238 | suffix_always is true |
252b5132 | 1239 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1240 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1241 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1242 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 1243 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 1244 | for some of the macro letters) |
9306ca4a | 1245 | 'J' => print 'l' |
42903f7f | 1246 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 1247 | 'L' => print 'l' if suffix_always is true |
9d141669 | 1248 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1249 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1250 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 1251 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
1252 | or suffix_always is true. print 'q' if rex prefix is present. |
1253 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
1254 | is true | |
a35ca55a | 1255 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1256 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
1257 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
1258 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 1259 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 1260 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1261 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
1262 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
1263 | suffix_always is true. | |
6dd5059a | 1264 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 1265 | '!' => change condition from true to false or from false to true. |
98b528ac L |
1266 | '%' => add 1 upper case letter to the macro. |
1267 | ||
1268 | 2 upper case letter macros: | |
c0f3af97 L |
1269 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
1270 | is true. | |
0bfee649 | 1271 | 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA) |
98b528ac L |
1272 | 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand |
1273 | or suffix_always is true | |
52b15da3 | 1274 | |
6439fc28 AM |
1275 | Many of the above letters print nothing in Intel mode. See "putop" |
1276 | for the details. | |
52b15da3 | 1277 | |
6439fc28 | 1278 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1279 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1280 | |
6439fc28 | 1281 | static const struct dis386 dis386[] = { |
252b5132 | 1282 | /* 00 */ |
ce518a5f L |
1283 | { "addB", { Eb, Gb } }, |
1284 | { "addS", { Ev, Gv } }, | |
c7532693 L |
1285 | { "addB", { Gb, EbS } }, |
1286 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
1287 | { "addB", { AL, Ib } }, |
1288 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
1289 | { X86_64_TABLE (X86_64_06) }, |
1290 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1291 | /* 08 */ |
ce518a5f L |
1292 | { "orB", { Eb, Gb } }, |
1293 | { "orS", { Ev, Gv } }, | |
c7532693 L |
1294 | { "orB", { Gb, EbS } }, |
1295 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
1296 | { "orB", { AL, Ib } }, |
1297 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 1298 | { X86_64_TABLE (X86_64_0D) }, |
ce518a5f | 1299 | { "(bad)", { XX } }, /* 0x0f extended opcode escape */ |
252b5132 | 1300 | /* 10 */ |
ce518a5f L |
1301 | { "adcB", { Eb, Gb } }, |
1302 | { "adcS", { Ev, Gv } }, | |
c7532693 L |
1303 | { "adcB", { Gb, EbS } }, |
1304 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
1305 | { "adcB", { AL, Ib } }, |
1306 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
1307 | { X86_64_TABLE (X86_64_16) }, |
1308 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1309 | /* 18 */ |
ce518a5f L |
1310 | { "sbbB", { Eb, Gb } }, |
1311 | { "sbbS", { Ev, Gv } }, | |
c7532693 L |
1312 | { "sbbB", { Gb, EbS } }, |
1313 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
1314 | { "sbbB", { AL, Ib } }, |
1315 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
1316 | { X86_64_TABLE (X86_64_1E) }, |
1317 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1318 | /* 20 */ |
ce518a5f L |
1319 | { "andB", { Eb, Gb } }, |
1320 | { "andS", { Ev, Gv } }, | |
c7532693 L |
1321 | { "andB", { Gb, EbS } }, |
1322 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
1323 | { "andB", { AL, Ib } }, |
1324 | { "andS", { eAX, Iv } }, | |
1325 | { "(bad)", { XX } }, /* SEG ES prefix */ | |
4e7d34a6 | 1326 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1327 | /* 28 */ |
ce518a5f L |
1328 | { "subB", { Eb, Gb } }, |
1329 | { "subS", { Ev, Gv } }, | |
c7532693 L |
1330 | { "subB", { Gb, EbS } }, |
1331 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
1332 | { "subB", { AL, Ib } }, |
1333 | { "subS", { eAX, Iv } }, | |
1334 | { "(bad)", { XX } }, /* SEG CS prefix */ | |
4e7d34a6 | 1335 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1336 | /* 30 */ |
ce518a5f L |
1337 | { "xorB", { Eb, Gb } }, |
1338 | { "xorS", { Ev, Gv } }, | |
c7532693 L |
1339 | { "xorB", { Gb, EbS } }, |
1340 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
1341 | { "xorB", { AL, Ib } }, |
1342 | { "xorS", { eAX, Iv } }, | |
1343 | { "(bad)", { XX } }, /* SEG SS prefix */ | |
4e7d34a6 | 1344 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1345 | /* 38 */ |
ce518a5f L |
1346 | { "cmpB", { Eb, Gb } }, |
1347 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
1348 | { "cmpB", { Gb, EbS } }, |
1349 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
1350 | { "cmpB", { AL, Ib } }, |
1351 | { "cmpS", { eAX, Iv } }, | |
1352 | { "(bad)", { XX } }, /* SEG DS prefix */ | |
4e7d34a6 | 1353 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1354 | /* 40 */ |
ce518a5f L |
1355 | { "inc{S|}", { RMeAX } }, |
1356 | { "inc{S|}", { RMeCX } }, | |
1357 | { "inc{S|}", { RMeDX } }, | |
1358 | { "inc{S|}", { RMeBX } }, | |
1359 | { "inc{S|}", { RMeSP } }, | |
1360 | { "inc{S|}", { RMeBP } }, | |
1361 | { "inc{S|}", { RMeSI } }, | |
1362 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 1363 | /* 48 */ |
ce518a5f L |
1364 | { "dec{S|}", { RMeAX } }, |
1365 | { "dec{S|}", { RMeCX } }, | |
1366 | { "dec{S|}", { RMeDX } }, | |
1367 | { "dec{S|}", { RMeBX } }, | |
1368 | { "dec{S|}", { RMeSP } }, | |
1369 | { "dec{S|}", { RMeBP } }, | |
1370 | { "dec{S|}", { RMeSI } }, | |
1371 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 1372 | /* 50 */ |
ce518a5f L |
1373 | { "pushV", { RMrAX } }, |
1374 | { "pushV", { RMrCX } }, | |
1375 | { "pushV", { RMrDX } }, | |
1376 | { "pushV", { RMrBX } }, | |
1377 | { "pushV", { RMrSP } }, | |
1378 | { "pushV", { RMrBP } }, | |
1379 | { "pushV", { RMrSI } }, | |
1380 | { "pushV", { RMrDI } }, | |
252b5132 | 1381 | /* 58 */ |
ce518a5f L |
1382 | { "popV", { RMrAX } }, |
1383 | { "popV", { RMrCX } }, | |
1384 | { "popV", { RMrDX } }, | |
1385 | { "popV", { RMrBX } }, | |
1386 | { "popV", { RMrSP } }, | |
1387 | { "popV", { RMrBP } }, | |
1388 | { "popV", { RMrSI } }, | |
1389 | { "popV", { RMrDI } }, | |
252b5132 | 1390 | /* 60 */ |
4e7d34a6 L |
1391 | { X86_64_TABLE (X86_64_60) }, |
1392 | { X86_64_TABLE (X86_64_61) }, | |
1393 | { X86_64_TABLE (X86_64_62) }, | |
1394 | { X86_64_TABLE (X86_64_63) }, | |
ce518a5f L |
1395 | { "(bad)", { XX } }, /* seg fs */ |
1396 | { "(bad)", { XX } }, /* seg gs */ | |
1397 | { "(bad)", { XX } }, /* op size prefix */ | |
1398 | { "(bad)", { XX } }, /* adr size prefix */ | |
252b5132 | 1399 | /* 68 */ |
ce518a5f L |
1400 | { "pushT", { Iq } }, |
1401 | { "imulS", { Gv, Ev, Iv } }, | |
1402 | { "pushT", { sIb } }, | |
1403 | { "imulS", { Gv, Ev, sIb } }, | |
7c52e0e8 | 1404 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 1405 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 1406 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 1407 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1408 | /* 70 */ |
ce518a5f L |
1409 | { "joH", { Jb, XX, cond_jump_flag } }, |
1410 | { "jnoH", { Jb, XX, cond_jump_flag } }, | |
1411 | { "jbH", { Jb, XX, cond_jump_flag } }, | |
1412 | { "jaeH", { Jb, XX, cond_jump_flag } }, | |
1413 | { "jeH", { Jb, XX, cond_jump_flag } }, | |
1414 | { "jneH", { Jb, XX, cond_jump_flag } }, | |
1415 | { "jbeH", { Jb, XX, cond_jump_flag } }, | |
1416 | { "jaH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1417 | /* 78 */ |
ce518a5f L |
1418 | { "jsH", { Jb, XX, cond_jump_flag } }, |
1419 | { "jnsH", { Jb, XX, cond_jump_flag } }, | |
1420 | { "jpH", { Jb, XX, cond_jump_flag } }, | |
1421 | { "jnpH", { Jb, XX, cond_jump_flag } }, | |
1422 | { "jlH", { Jb, XX, cond_jump_flag } }, | |
1423 | { "jgeH", { Jb, XX, cond_jump_flag } }, | |
1424 | { "jleH", { Jb, XX, cond_jump_flag } }, | |
1425 | { "jgH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1426 | /* 80 */ |
1ceb70f8 L |
1427 | { REG_TABLE (REG_80) }, |
1428 | { REG_TABLE (REG_81) }, | |
ce518a5f | 1429 | { "(bad)", { XX } }, |
1ceb70f8 | 1430 | { REG_TABLE (REG_82) }, |
ce518a5f L |
1431 | { "testB", { Eb, Gb } }, |
1432 | { "testS", { Ev, Gv } }, | |
1433 | { "xchgB", { Eb, Gb } }, | |
1434 | { "xchgS", { Ev, Gv } }, | |
252b5132 | 1435 | /* 88 */ |
ce518a5f L |
1436 | { "movB", { Eb, Gb } }, |
1437 | { "movS", { Ev, Gv } }, | |
b6169b20 L |
1438 | { "movB", { Gb, EbS } }, |
1439 | { "movS", { Gv, EvS } }, | |
ce518a5f | 1440 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 1441 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 1442 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 1443 | { REG_TABLE (REG_8F) }, |
252b5132 | 1444 | /* 90 */ |
1ceb70f8 | 1445 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
1446 | { "xchgS", { RMeCX, eAX } }, |
1447 | { "xchgS", { RMeDX, eAX } }, | |
1448 | { "xchgS", { RMeBX, eAX } }, | |
1449 | { "xchgS", { RMeSP, eAX } }, | |
1450 | { "xchgS", { RMeBP, eAX } }, | |
1451 | { "xchgS", { RMeSI, eAX } }, | |
1452 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 1453 | /* 98 */ |
7c52e0e8 L |
1454 | { "cW{t|}R", { XX } }, |
1455 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 1456 | { X86_64_TABLE (X86_64_9A) }, |
ce518a5f L |
1457 | { "(bad)", { XX } }, /* fwait */ |
1458 | { "pushfT", { XX } }, | |
1459 | { "popfT", { XX } }, | |
7c52e0e8 L |
1460 | { "sahf", { XX } }, |
1461 | { "lahf", { XX } }, | |
252b5132 | 1462 | /* a0 */ |
ce518a5f L |
1463 | { "movB", { AL, Ob } }, |
1464 | { "movS", { eAX, Ov } }, | |
1465 | { "movB", { Ob, AL } }, | |
1466 | { "movS", { Ov, eAX } }, | |
7c52e0e8 L |
1467 | { "movs{b|}", { Ybr, Xb } }, |
1468 | { "movs{R|}", { Yvr, Xv } }, | |
1469 | { "cmps{b|}", { Xb, Yb } }, | |
1470 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 1471 | /* a8 */ |
ce518a5f L |
1472 | { "testB", { AL, Ib } }, |
1473 | { "testS", { eAX, Iv } }, | |
1474 | { "stosB", { Ybr, AL } }, | |
1475 | { "stosS", { Yvr, eAX } }, | |
1476 | { "lodsB", { ALr, Xb } }, | |
1477 | { "lodsS", { eAXr, Xv } }, | |
1478 | { "scasB", { AL, Yb } }, | |
1479 | { "scasS", { eAX, Yv } }, | |
252b5132 | 1480 | /* b0 */ |
ce518a5f L |
1481 | { "movB", { RMAL, Ib } }, |
1482 | { "movB", { RMCL, Ib } }, | |
1483 | { "movB", { RMDL, Ib } }, | |
1484 | { "movB", { RMBL, Ib } }, | |
1485 | { "movB", { RMAH, Ib } }, | |
1486 | { "movB", { RMCH, Ib } }, | |
1487 | { "movB", { RMDH, Ib } }, | |
1488 | { "movB", { RMBH, Ib } }, | |
252b5132 | 1489 | /* b8 */ |
ce518a5f L |
1490 | { "movS", { RMeAX, Iv64 } }, |
1491 | { "movS", { RMeCX, Iv64 } }, | |
1492 | { "movS", { RMeDX, Iv64 } }, | |
1493 | { "movS", { RMeBX, Iv64 } }, | |
1494 | { "movS", { RMeSP, Iv64 } }, | |
1495 | { "movS", { RMeBP, Iv64 } }, | |
1496 | { "movS", { RMeSI, Iv64 } }, | |
1497 | { "movS", { RMeDI, Iv64 } }, | |
252b5132 | 1498 | /* c0 */ |
1ceb70f8 L |
1499 | { REG_TABLE (REG_C0) }, |
1500 | { REG_TABLE (REG_C1) }, | |
ce518a5f L |
1501 | { "retT", { Iw } }, |
1502 | { "retT", { XX } }, | |
4e7d34a6 L |
1503 | { X86_64_TABLE (X86_64_C4) }, |
1504 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1505 | { REG_TABLE (REG_C6) }, |
1506 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1507 | /* c8 */ |
ce518a5f L |
1508 | { "enterT", { Iw, Ib } }, |
1509 | { "leaveT", { XX } }, | |
ddab3d59 JB |
1510 | { "Jret{|f}P", { Iw } }, |
1511 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
1512 | { "int3", { XX } }, |
1513 | { "int", { Ib } }, | |
4e7d34a6 | 1514 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1515 | { "iretP", { XX } }, |
252b5132 | 1516 | /* d0 */ |
1ceb70f8 L |
1517 | { REG_TABLE (REG_D0) }, |
1518 | { REG_TABLE (REG_D1) }, | |
1519 | { REG_TABLE (REG_D2) }, | |
1520 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1521 | { X86_64_TABLE (X86_64_D4) }, |
1522 | { X86_64_TABLE (X86_64_D5) }, | |
ce518a5f L |
1523 | { "(bad)", { XX } }, |
1524 | { "xlat", { DSBX } }, | |
252b5132 RH |
1525 | /* d8 */ |
1526 | { FLOAT }, | |
1527 | { FLOAT }, | |
1528 | { FLOAT }, | |
1529 | { FLOAT }, | |
1530 | { FLOAT }, | |
1531 | { FLOAT }, | |
1532 | { FLOAT }, | |
1533 | { FLOAT }, | |
1534 | /* e0 */ | |
ce518a5f L |
1535 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1536 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1537 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1538 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1539 | { "inB", { AL, Ib } }, | |
1540 | { "inG", { zAX, Ib } }, | |
1541 | { "outB", { Ib, AL } }, | |
1542 | { "outG", { Ib, zAX } }, | |
252b5132 | 1543 | /* e8 */ |
ce518a5f L |
1544 | { "callT", { Jv } }, |
1545 | { "jmpT", { Jv } }, | |
4e7d34a6 | 1546 | { X86_64_TABLE (X86_64_EA) }, |
ce518a5f L |
1547 | { "jmp", { Jb } }, |
1548 | { "inB", { AL, indirDX } }, | |
1549 | { "inG", { zAX, indirDX } }, | |
1550 | { "outB", { indirDX, AL } }, | |
1551 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1552 | /* f0 */ |
ce518a5f L |
1553 | { "(bad)", { XX } }, /* lock prefix */ |
1554 | { "icebp", { XX } }, | |
1555 | { "(bad)", { XX } }, /* repne */ | |
1556 | { "(bad)", { XX } }, /* repz */ | |
1557 | { "hlt", { XX } }, | |
1558 | { "cmc", { XX } }, | |
1ceb70f8 L |
1559 | { REG_TABLE (REG_F6) }, |
1560 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1561 | /* f8 */ |
ce518a5f L |
1562 | { "clc", { XX } }, |
1563 | { "stc", { XX } }, | |
1564 | { "cli", { XX } }, | |
1565 | { "sti", { XX } }, | |
1566 | { "cld", { XX } }, | |
1567 | { "std", { XX } }, | |
1ceb70f8 L |
1568 | { REG_TABLE (REG_FE) }, |
1569 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1570 | }; |
1571 | ||
6439fc28 | 1572 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1573 | /* 00 */ |
1ceb70f8 L |
1574 | { REG_TABLE (REG_0F00 ) }, |
1575 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1576 | { "larS", { Gv, Ew } }, |
1577 | { "lslS", { Gv, Ew } }, | |
1578 | { "(bad)", { XX } }, | |
1579 | { "syscall", { XX } }, | |
1580 | { "clts", { XX } }, | |
1581 | { "sysretP", { XX } }, | |
252b5132 | 1582 | /* 08 */ |
ce518a5f L |
1583 | { "invd", { XX } }, |
1584 | { "wbinvd", { XX } }, | |
1585 | { "(bad)", { XX } }, | |
1586 | { "ud2a", { XX } }, | |
1587 | { "(bad)", { XX } }, | |
b5b1fc4f | 1588 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1589 | { "femms", { XX } }, |
1590 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1591 | /* 10 */ |
1ceb70f8 L |
1592 | { PREFIX_TABLE (PREFIX_0F10) }, |
1593 | { PREFIX_TABLE (PREFIX_0F11) }, | |
1594 | { PREFIX_TABLE (PREFIX_0F12) }, | |
1595 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
1596 | { "unpcklpX", { XM, EXx } }, |
1597 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
1598 | { PREFIX_TABLE (PREFIX_0F16) }, |
1599 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 1600 | /* 18 */ |
1ceb70f8 | 1601 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f L |
1602 | { "nopQ", { Ev } }, |
1603 | { "nopQ", { Ev } }, | |
1604 | { "nopQ", { Ev } }, | |
1605 | { "nopQ", { Ev } }, | |
1606 | { "nopQ", { Ev } }, | |
1607 | { "nopQ", { Ev } }, | |
ce518a5f | 1608 | { "nopQ", { Ev } }, |
252b5132 | 1609 | /* 20 */ |
1ceb70f8 L |
1610 | { MOD_TABLE (MOD_0F20) }, |
1611 | { MOD_TABLE (MOD_0F21) }, | |
1612 | { MOD_TABLE (MOD_0F22) }, | |
1613 | { MOD_TABLE (MOD_0F23) }, | |
1614 | { MOD_TABLE (MOD_0F24) }, | |
c1e679ec | 1615 | { "(bad)", { XX } }, |
1ceb70f8 | 1616 | { MOD_TABLE (MOD_0F26) }, |
ce518a5f | 1617 | { "(bad)", { XX } }, |
252b5132 | 1618 | /* 28 */ |
09a2c6cf | 1619 | { "movapX", { XM, EXx } }, |
b6169b20 | 1620 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
1621 | { PREFIX_TABLE (PREFIX_0F2A) }, |
1622 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
1623 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
1624 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
1625 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
1626 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 1627 | /* 30 */ |
ce518a5f L |
1628 | { "wrmsr", { XX } }, |
1629 | { "rdtsc", { XX } }, | |
1630 | { "rdmsr", { XX } }, | |
1631 | { "rdpmc", { XX } }, | |
1632 | { "sysenter", { XX } }, | |
1633 | { "sysexit", { XX } }, | |
1634 | { "(bad)", { XX } }, | |
47dd174c | 1635 | { "getsec", { XX } }, |
252b5132 | 1636 | /* 38 */ |
4e7d34a6 | 1637 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
ce518a5f | 1638 | { "(bad)", { XX } }, |
4e7d34a6 | 1639 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
ce518a5f L |
1640 | { "(bad)", { XX } }, |
1641 | { "(bad)", { XX } }, | |
1642 | { "(bad)", { XX } }, | |
1643 | { "(bad)", { XX } }, | |
1644 | { "(bad)", { XX } }, | |
252b5132 | 1645 | /* 40 */ |
b19d5385 JB |
1646 | { "cmovoS", { Gv, Ev } }, |
1647 | { "cmovnoS", { Gv, Ev } }, | |
1648 | { "cmovbS", { Gv, Ev } }, | |
1649 | { "cmovaeS", { Gv, Ev } }, | |
1650 | { "cmoveS", { Gv, Ev } }, | |
1651 | { "cmovneS", { Gv, Ev } }, | |
1652 | { "cmovbeS", { Gv, Ev } }, | |
1653 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 1654 | /* 48 */ |
b19d5385 JB |
1655 | { "cmovsS", { Gv, Ev } }, |
1656 | { "cmovnsS", { Gv, Ev } }, | |
1657 | { "cmovpS", { Gv, Ev } }, | |
1658 | { "cmovnpS", { Gv, Ev } }, | |
1659 | { "cmovlS", { Gv, Ev } }, | |
1660 | { "cmovgeS", { Gv, Ev } }, | |
1661 | { "cmovleS", { Gv, Ev } }, | |
1662 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 1663 | /* 50 */ |
75c135a8 | 1664 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
1665 | { PREFIX_TABLE (PREFIX_0F51) }, |
1666 | { PREFIX_TABLE (PREFIX_0F52) }, | |
1667 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
1668 | { "andpX", { XM, EXx } }, |
1669 | { "andnpX", { XM, EXx } }, | |
1670 | { "orpX", { XM, EXx } }, | |
1671 | { "xorpX", { XM, EXx } }, | |
252b5132 | 1672 | /* 58 */ |
1ceb70f8 L |
1673 | { PREFIX_TABLE (PREFIX_0F58) }, |
1674 | { PREFIX_TABLE (PREFIX_0F59) }, | |
1675 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
1676 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
1677 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
1678 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
1679 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
1680 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 1681 | /* 60 */ |
1ceb70f8 L |
1682 | { PREFIX_TABLE (PREFIX_0F60) }, |
1683 | { PREFIX_TABLE (PREFIX_0F61) }, | |
1684 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
1685 | { "packsswb", { MX, EM } }, |
1686 | { "pcmpgtb", { MX, EM } }, | |
1687 | { "pcmpgtw", { MX, EM } }, | |
1688 | { "pcmpgtd", { MX, EM } }, | |
1689 | { "packuswb", { MX, EM } }, | |
252b5132 | 1690 | /* 68 */ |
ce518a5f L |
1691 | { "punpckhbw", { MX, EM } }, |
1692 | { "punpckhwd", { MX, EM } }, | |
1693 | { "punpckhdq", { MX, EM } }, | |
1694 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
1695 | { PREFIX_TABLE (PREFIX_0F6C) }, |
1696 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 1697 | { "movK", { MX, Edq } }, |
1ceb70f8 | 1698 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 1699 | /* 70 */ |
1ceb70f8 L |
1700 | { PREFIX_TABLE (PREFIX_0F70) }, |
1701 | { REG_TABLE (REG_0F71) }, | |
1702 | { REG_TABLE (REG_0F72) }, | |
1703 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
1704 | { "pcmpeqb", { MX, EM } }, |
1705 | { "pcmpeqw", { MX, EM } }, | |
1706 | { "pcmpeqd", { MX, EM } }, | |
1707 | { "emms", { XX } }, | |
252b5132 | 1708 | /* 78 */ |
1ceb70f8 L |
1709 | { PREFIX_TABLE (PREFIX_0F78) }, |
1710 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 1711 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
c1e679ec | 1712 | { "(bad)", { XX } }, |
1ceb70f8 L |
1713 | { PREFIX_TABLE (PREFIX_0F7C) }, |
1714 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
1715 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
1716 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 1717 | /* 80 */ |
ce518a5f L |
1718 | { "joH", { Jv, XX, cond_jump_flag } }, |
1719 | { "jnoH", { Jv, XX, cond_jump_flag } }, | |
1720 | { "jbH", { Jv, XX, cond_jump_flag } }, | |
1721 | { "jaeH", { Jv, XX, cond_jump_flag } }, | |
1722 | { "jeH", { Jv, XX, cond_jump_flag } }, | |
1723 | { "jneH", { Jv, XX, cond_jump_flag } }, | |
1724 | { "jbeH", { Jv, XX, cond_jump_flag } }, | |
1725 | { "jaH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1726 | /* 88 */ |
ce518a5f L |
1727 | { "jsH", { Jv, XX, cond_jump_flag } }, |
1728 | { "jnsH", { Jv, XX, cond_jump_flag } }, | |
1729 | { "jpH", { Jv, XX, cond_jump_flag } }, | |
1730 | { "jnpH", { Jv, XX, cond_jump_flag } }, | |
1731 | { "jlH", { Jv, XX, cond_jump_flag } }, | |
1732 | { "jgeH", { Jv, XX, cond_jump_flag } }, | |
1733 | { "jleH", { Jv, XX, cond_jump_flag } }, | |
1734 | { "jgH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1735 | /* 90 */ |
ce518a5f L |
1736 | { "seto", { Eb } }, |
1737 | { "setno", { Eb } }, | |
1738 | { "setb", { Eb } }, | |
1739 | { "setae", { Eb } }, | |
1740 | { "sete", { Eb } }, | |
1741 | { "setne", { Eb } }, | |
1742 | { "setbe", { Eb } }, | |
1743 | { "seta", { Eb } }, | |
252b5132 | 1744 | /* 98 */ |
ce518a5f L |
1745 | { "sets", { Eb } }, |
1746 | { "setns", { Eb } }, | |
1747 | { "setp", { Eb } }, | |
1748 | { "setnp", { Eb } }, | |
1749 | { "setl", { Eb } }, | |
1750 | { "setge", { Eb } }, | |
1751 | { "setle", { Eb } }, | |
1752 | { "setg", { Eb } }, | |
252b5132 | 1753 | /* a0 */ |
ce518a5f L |
1754 | { "pushT", { fs } }, |
1755 | { "popT", { fs } }, | |
1756 | { "cpuid", { XX } }, | |
1757 | { "btS", { Ev, Gv } }, | |
1758 | { "shldS", { Ev, Gv, Ib } }, | |
1759 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
1760 | { REG_TABLE (REG_0FA6) }, |
1761 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 1762 | /* a8 */ |
ce518a5f L |
1763 | { "pushT", { gs } }, |
1764 | { "popT", { gs } }, | |
1765 | { "rsm", { XX } }, | |
1766 | { "btsS", { Ev, Gv } }, | |
1767 | { "shrdS", { Ev, Gv, Ib } }, | |
1768 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 1769 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 1770 | { "imulS", { Gv, Ev } }, |
252b5132 | 1771 | /* b0 */ |
ce518a5f L |
1772 | { "cmpxchgB", { Eb, Gb } }, |
1773 | { "cmpxchgS", { Ev, Gv } }, | |
1ceb70f8 | 1774 | { MOD_TABLE (MOD_0FB2) }, |
ce518a5f | 1775 | { "btrS", { Ev, Gv } }, |
1ceb70f8 L |
1776 | { MOD_TABLE (MOD_0FB4) }, |
1777 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
1778 | { "movz{bR|x}", { Gv, Eb } }, |
1779 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 1780 | /* b8 */ |
1ceb70f8 | 1781 | { PREFIX_TABLE (PREFIX_0FB8) }, |
ce518a5f | 1782 | { "ud2b", { XX } }, |
1ceb70f8 | 1783 | { REG_TABLE (REG_0FBA) }, |
ce518a5f L |
1784 | { "btcS", { Ev, Gv } }, |
1785 | { "bsfS", { Gv, Ev } }, | |
1ceb70f8 | 1786 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
1787 | { "movs{bR|x}", { Gv, Eb } }, |
1788 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 1789 | /* c0 */ |
ce518a5f L |
1790 | { "xaddB", { Eb, Gb } }, |
1791 | { "xaddS", { Ev, Gv } }, | |
1ceb70f8 | 1792 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 1793 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
1794 | { "pinsrw", { MX, Edqw, Ib } }, |
1795 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 1796 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 1797 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 1798 | /* c8 */ |
ce518a5f L |
1799 | { "bswap", { RMeAX } }, |
1800 | { "bswap", { RMeCX } }, | |
1801 | { "bswap", { RMeDX } }, | |
1802 | { "bswap", { RMeBX } }, | |
1803 | { "bswap", { RMeSP } }, | |
1804 | { "bswap", { RMeBP } }, | |
1805 | { "bswap", { RMeSI } }, | |
1806 | { "bswap", { RMeDI } }, | |
252b5132 | 1807 | /* d0 */ |
1ceb70f8 | 1808 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
1809 | { "psrlw", { MX, EM } }, |
1810 | { "psrld", { MX, EM } }, | |
1811 | { "psrlq", { MX, EM } }, | |
1812 | { "paddq", { MX, EM } }, | |
1813 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 1814 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 1815 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 1816 | /* d8 */ |
ce518a5f L |
1817 | { "psubusb", { MX, EM } }, |
1818 | { "psubusw", { MX, EM } }, | |
1819 | { "pminub", { MX, EM } }, | |
1820 | { "pand", { MX, EM } }, | |
1821 | { "paddusb", { MX, EM } }, | |
1822 | { "paddusw", { MX, EM } }, | |
1823 | { "pmaxub", { MX, EM } }, | |
1824 | { "pandn", { MX, EM } }, | |
252b5132 | 1825 | /* e0 */ |
ce518a5f L |
1826 | { "pavgb", { MX, EM } }, |
1827 | { "psraw", { MX, EM } }, | |
1828 | { "psrad", { MX, EM } }, | |
1829 | { "pavgw", { MX, EM } }, | |
1830 | { "pmulhuw", { MX, EM } }, | |
1831 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
1832 | { PREFIX_TABLE (PREFIX_0FE6) }, |
1833 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 1834 | /* e8 */ |
ce518a5f L |
1835 | { "psubsb", { MX, EM } }, |
1836 | { "psubsw", { MX, EM } }, | |
1837 | { "pminsw", { MX, EM } }, | |
1838 | { "por", { MX, EM } }, | |
1839 | { "paddsb", { MX, EM } }, | |
1840 | { "paddsw", { MX, EM } }, | |
1841 | { "pmaxsw", { MX, EM } }, | |
1842 | { "pxor", { MX, EM } }, | |
252b5132 | 1843 | /* f0 */ |
1ceb70f8 | 1844 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
1845 | { "psllw", { MX, EM } }, |
1846 | { "pslld", { MX, EM } }, | |
1847 | { "psllq", { MX, EM } }, | |
1848 | { "pmuludq", { MX, EM } }, | |
1849 | { "pmaddwd", { MX, EM } }, | |
1850 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 1851 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 1852 | /* f8 */ |
ce518a5f L |
1853 | { "psubb", { MX, EM } }, |
1854 | { "psubw", { MX, EM } }, | |
1855 | { "psubd", { MX, EM } }, | |
1856 | { "psubq", { MX, EM } }, | |
1857 | { "paddb", { MX, EM } }, | |
1858 | { "paddw", { MX, EM } }, | |
1859 | { "paddd", { MX, EM } }, | |
1860 | { "(bad)", { XX } }, | |
252b5132 RH |
1861 | }; |
1862 | ||
1863 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
1864 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1865 | /* ------------------------------- */ | |
1866 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
1867 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
1868 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
1869 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
1870 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
1871 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
1872 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
1873 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
1874 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
1875 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
1876 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
1877 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
1878 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
1879 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
1880 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
1881 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
1882 | /* ------------------------------- */ | |
1883 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
1884 | }; |
1885 | ||
1886 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
1887 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1888 | /* ------------------------------- */ | |
252b5132 | 1889 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 1890 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 1891 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 1892 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 1893 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
1894 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
1895 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 1896 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
1897 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
1898 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 1899 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 1900 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 1901 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 1902 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 1903 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 1904 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
1905 | /* ------------------------------- */ |
1906 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1907 | }; | |
1908 | ||
252b5132 RH |
1909 | static char obuf[100]; |
1910 | static char *obufp; | |
ea397f5b | 1911 | static char *mnemonicendp; |
252b5132 RH |
1912 | static char scratchbuf[100]; |
1913 | static unsigned char *start_codep; | |
1914 | static unsigned char *insn_codep; | |
1915 | static unsigned char *codep; | |
b844680a L |
1916 | static const char *lock_prefix; |
1917 | static const char *data_prefix; | |
1918 | static const char *addr_prefix; | |
1919 | static const char *repz_prefix; | |
1920 | static const char *repnz_prefix; | |
252b5132 | 1921 | static disassemble_info *the_info; |
7967e09e L |
1922 | static struct |
1923 | { | |
1924 | int mod; | |
7967e09e | 1925 | int reg; |
484c222e | 1926 | int rm; |
7967e09e L |
1927 | } |
1928 | modrm; | |
4bba6815 | 1929 | static unsigned char need_modrm; |
c0f3af97 L |
1930 | static struct |
1931 | { | |
1932 | int register_specifier; | |
1933 | int length; | |
1934 | int prefix; | |
1935 | int w; | |
1936 | } | |
1937 | vex; | |
1938 | static unsigned char need_vex; | |
1939 | static unsigned char need_vex_reg; | |
dae39acc | 1940 | static unsigned char vex_w_done; |
252b5132 | 1941 | |
ea397f5b L |
1942 | struct op |
1943 | { | |
1944 | const char *name; | |
1945 | unsigned int len; | |
1946 | }; | |
1947 | ||
4bba6815 AM |
1948 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
1949 | values are stale. Hitting this abort likely indicates that you | |
1950 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
1951 | #define MODRM_CHECK if (!need_modrm) abort () | |
1952 | ||
d708bcba AM |
1953 | static const char **names64; |
1954 | static const char **names32; | |
1955 | static const char **names16; | |
1956 | static const char **names8; | |
1957 | static const char **names8rex; | |
1958 | static const char **names_seg; | |
db51cc60 L |
1959 | static const char *index64; |
1960 | static const char *index32; | |
d708bcba AM |
1961 | static const char **index16; |
1962 | ||
1963 | static const char *intel_names64[] = { | |
1964 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
1965 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
1966 | }; | |
1967 | static const char *intel_names32[] = { | |
1968 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
1969 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
1970 | }; | |
1971 | static const char *intel_names16[] = { | |
1972 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
1973 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
1974 | }; | |
1975 | static const char *intel_names8[] = { | |
1976 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
1977 | }; | |
1978 | static const char *intel_names8rex[] = { | |
1979 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
1980 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
1981 | }; | |
1982 | static const char *intel_names_seg[] = { | |
1983 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
1984 | }; | |
db51cc60 L |
1985 | static const char *intel_index64 = "riz"; |
1986 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
1987 | static const char *intel_index16[] = { |
1988 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
1989 | }; | |
1990 | ||
1991 | static const char *att_names64[] = { | |
1992 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
1993 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
1994 | }; | |
d708bcba AM |
1995 | static const char *att_names32[] = { |
1996 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 1997 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 1998 | }; |
d708bcba AM |
1999 | static const char *att_names16[] = { |
2000 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2001 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2002 | }; |
d708bcba AM |
2003 | static const char *att_names8[] = { |
2004 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2005 | }; |
d708bcba AM |
2006 | static const char *att_names8rex[] = { |
2007 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2008 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2009 | }; | |
d708bcba AM |
2010 | static const char *att_names_seg[] = { |
2011 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2012 | }; |
db51cc60 L |
2013 | static const char *att_index64 = "%riz"; |
2014 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2015 | static const char *att_index16[] = { |
2016 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2017 | }; |
2018 | ||
1ceb70f8 L |
2019 | static const struct dis386 reg_table[][8] = { |
2020 | /* REG_80 */ | |
252b5132 | 2021 | { |
ce518a5f L |
2022 | { "addA", { Eb, Ib } }, |
2023 | { "orA", { Eb, Ib } }, | |
2024 | { "adcA", { Eb, Ib } }, | |
2025 | { "sbbA", { Eb, Ib } }, | |
2026 | { "andA", { Eb, Ib } }, | |
2027 | { "subA", { Eb, Ib } }, | |
2028 | { "xorA", { Eb, Ib } }, | |
2029 | { "cmpA", { Eb, Ib } }, | |
252b5132 | 2030 | }, |
1ceb70f8 | 2031 | /* REG_81 */ |
252b5132 | 2032 | { |
ce518a5f L |
2033 | { "addQ", { Ev, Iv } }, |
2034 | { "orQ", { Ev, Iv } }, | |
2035 | { "adcQ", { Ev, Iv } }, | |
2036 | { "sbbQ", { Ev, Iv } }, | |
2037 | { "andQ", { Ev, Iv } }, | |
2038 | { "subQ", { Ev, Iv } }, | |
2039 | { "xorQ", { Ev, Iv } }, | |
2040 | { "cmpQ", { Ev, Iv } }, | |
252b5132 | 2041 | }, |
1ceb70f8 | 2042 | /* REG_82 */ |
252b5132 | 2043 | { |
ce518a5f L |
2044 | { "addQ", { Ev, sIb } }, |
2045 | { "orQ", { Ev, sIb } }, | |
2046 | { "adcQ", { Ev, sIb } }, | |
2047 | { "sbbQ", { Ev, sIb } }, | |
2048 | { "andQ", { Ev, sIb } }, | |
2049 | { "subQ", { Ev, sIb } }, | |
2050 | { "xorQ", { Ev, sIb } }, | |
2051 | { "cmpQ", { Ev, sIb } }, | |
252b5132 | 2052 | }, |
1ceb70f8 | 2053 | /* REG_8F */ |
4e7d34a6 L |
2054 | { |
2055 | { "popU", { stackEv } }, | |
2056 | { "(bad)", { XX } }, | |
2057 | { "(bad)", { XX } }, | |
2058 | { "(bad)", { XX } }, | |
2059 | { "(bad)", { XX } }, | |
2060 | { "(bad)", { XX } }, | |
2061 | { "(bad)", { XX } }, | |
2062 | { "(bad)", { XX } }, | |
2063 | }, | |
1ceb70f8 | 2064 | /* REG_C0 */ |
252b5132 | 2065 | { |
ce518a5f L |
2066 | { "rolA", { Eb, Ib } }, |
2067 | { "rorA", { Eb, Ib } }, | |
2068 | { "rclA", { Eb, Ib } }, | |
2069 | { "rcrA", { Eb, Ib } }, | |
2070 | { "shlA", { Eb, Ib } }, | |
2071 | { "shrA", { Eb, Ib } }, | |
2072 | { "(bad)", { XX } }, | |
2073 | { "sarA", { Eb, Ib } }, | |
252b5132 | 2074 | }, |
1ceb70f8 | 2075 | /* REG_C1 */ |
252b5132 | 2076 | { |
ce518a5f L |
2077 | { "rolQ", { Ev, Ib } }, |
2078 | { "rorQ", { Ev, Ib } }, | |
2079 | { "rclQ", { Ev, Ib } }, | |
2080 | { "rcrQ", { Ev, Ib } }, | |
2081 | { "shlQ", { Ev, Ib } }, | |
2082 | { "shrQ", { Ev, Ib } }, | |
2083 | { "(bad)", { XX } }, | |
2084 | { "sarQ", { Ev, Ib } }, | |
252b5132 | 2085 | }, |
1ceb70f8 | 2086 | /* REG_C6 */ |
4e7d34a6 L |
2087 | { |
2088 | { "movA", { Eb, Ib } }, | |
2089 | { "(bad)", { XX } }, | |
2090 | { "(bad)", { XX } }, | |
2091 | { "(bad)", { XX } }, | |
2092 | { "(bad)", { XX } }, | |
2093 | { "(bad)", { XX } }, | |
2094 | { "(bad)", { XX } }, | |
2095 | { "(bad)", { XX } }, | |
2096 | }, | |
1ceb70f8 | 2097 | /* REG_C7 */ |
4e7d34a6 L |
2098 | { |
2099 | { "movQ", { Ev, Iv } }, | |
2100 | { "(bad)", { XX } }, | |
2101 | { "(bad)", { XX } }, | |
2102 | { "(bad)", { XX } }, | |
2103 | { "(bad)", { XX } }, | |
2104 | { "(bad)", { XX } }, | |
2105 | { "(bad)", { XX } }, | |
2106 | { "(bad)", { XX } }, | |
2107 | }, | |
1ceb70f8 | 2108 | /* REG_D0 */ |
252b5132 | 2109 | { |
ce518a5f L |
2110 | { "rolA", { Eb, I1 } }, |
2111 | { "rorA", { Eb, I1 } }, | |
2112 | { "rclA", { Eb, I1 } }, | |
2113 | { "rcrA", { Eb, I1 } }, | |
2114 | { "shlA", { Eb, I1 } }, | |
2115 | { "shrA", { Eb, I1 } }, | |
2116 | { "(bad)", { XX } }, | |
2117 | { "sarA", { Eb, I1 } }, | |
252b5132 | 2118 | }, |
1ceb70f8 | 2119 | /* REG_D1 */ |
252b5132 | 2120 | { |
ce518a5f L |
2121 | { "rolQ", { Ev, I1 } }, |
2122 | { "rorQ", { Ev, I1 } }, | |
2123 | { "rclQ", { Ev, I1 } }, | |
2124 | { "rcrQ", { Ev, I1 } }, | |
2125 | { "shlQ", { Ev, I1 } }, | |
2126 | { "shrQ", { Ev, I1 } }, | |
2127 | { "(bad)", { XX } }, | |
2128 | { "sarQ", { Ev, I1 } }, | |
252b5132 | 2129 | }, |
1ceb70f8 | 2130 | /* REG_D2 */ |
252b5132 | 2131 | { |
ce518a5f L |
2132 | { "rolA", { Eb, CL } }, |
2133 | { "rorA", { Eb, CL } }, | |
2134 | { "rclA", { Eb, CL } }, | |
2135 | { "rcrA", { Eb, CL } }, | |
2136 | { "shlA", { Eb, CL } }, | |
2137 | { "shrA", { Eb, CL } }, | |
2138 | { "(bad)", { XX } }, | |
2139 | { "sarA", { Eb, CL } }, | |
252b5132 | 2140 | }, |
1ceb70f8 | 2141 | /* REG_D3 */ |
252b5132 | 2142 | { |
ce518a5f L |
2143 | { "rolQ", { Ev, CL } }, |
2144 | { "rorQ", { Ev, CL } }, | |
2145 | { "rclQ", { Ev, CL } }, | |
2146 | { "rcrQ", { Ev, CL } }, | |
2147 | { "shlQ", { Ev, CL } }, | |
2148 | { "shrQ", { Ev, CL } }, | |
2149 | { "(bad)", { XX } }, | |
2150 | { "sarQ", { Ev, CL } }, | |
252b5132 | 2151 | }, |
1ceb70f8 | 2152 | /* REG_F6 */ |
252b5132 | 2153 | { |
ce518a5f | 2154 | { "testA", { Eb, Ib } }, |
058f233b | 2155 | { "(bad)", { XX } }, |
ce518a5f L |
2156 | { "notA", { Eb } }, |
2157 | { "negA", { Eb } }, | |
2158 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ | |
2159 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
2160 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
2161 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 2162 | }, |
1ceb70f8 | 2163 | /* REG_F7 */ |
252b5132 | 2164 | { |
ce518a5f L |
2165 | { "testQ", { Ev, Iv } }, |
2166 | { "(bad)", { XX } }, | |
2167 | { "notQ", { Ev } }, | |
2168 | { "negQ", { Ev } }, | |
2169 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ | |
2170 | { "imulQ", { Ev } }, | |
2171 | { "divQ", { Ev } }, | |
2172 | { "idivQ", { Ev } }, | |
252b5132 | 2173 | }, |
1ceb70f8 | 2174 | /* REG_FE */ |
252b5132 | 2175 | { |
ce518a5f L |
2176 | { "incA", { Eb } }, |
2177 | { "decA", { Eb } }, | |
2178 | { "(bad)", { XX } }, | |
2179 | { "(bad)", { XX } }, | |
2180 | { "(bad)", { XX } }, | |
2181 | { "(bad)", { XX } }, | |
2182 | { "(bad)", { XX } }, | |
2183 | { "(bad)", { XX } }, | |
252b5132 | 2184 | }, |
1ceb70f8 | 2185 | /* REG_FF */ |
252b5132 | 2186 | { |
ce518a5f L |
2187 | { "incQ", { Ev } }, |
2188 | { "decQ", { Ev } }, | |
2189 | { "callT", { indirEv } }, | |
2190 | { "JcallT", { indirEp } }, | |
2191 | { "jmpT", { indirEv } }, | |
2192 | { "JjmpT", { indirEp } }, | |
2193 | { "pushU", { stackEv } }, | |
2194 | { "(bad)", { XX } }, | |
252b5132 | 2195 | }, |
1ceb70f8 | 2196 | /* REG_0F00 */ |
252b5132 | 2197 | { |
ce518a5f L |
2198 | { "sldtD", { Sv } }, |
2199 | { "strD", { Sv } }, | |
2200 | { "lldt", { Ew } }, | |
2201 | { "ltr", { Ew } }, | |
2202 | { "verr", { Ew } }, | |
2203 | { "verw", { Ew } }, | |
2204 | { "(bad)", { XX } }, | |
2205 | { "(bad)", { XX } }, | |
252b5132 | 2206 | }, |
1ceb70f8 | 2207 | /* REG_0F01 */ |
252b5132 | 2208 | { |
1ceb70f8 L |
2209 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2210 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2211 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2212 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f L |
2213 | { "smswD", { Sv } }, |
2214 | { "(bad)", { XX } }, | |
2215 | { "lmsw", { Ew } }, | |
1ceb70f8 | 2216 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2217 | }, |
b5b1fc4f | 2218 | /* REG_0F0D */ |
252b5132 | 2219 | { |
4e7d34a6 L |
2220 | { "prefetch", { Eb } }, |
2221 | { "prefetchw", { Eb } }, | |
2222 | { "(bad)", { XX } }, | |
2223 | { "(bad)", { XX } }, | |
2224 | { "(bad)", { XX } }, | |
2225 | { "(bad)", { XX } }, | |
2226 | { "(bad)", { XX } }, | |
2227 | { "(bad)", { XX } }, | |
252b5132 | 2228 | }, |
1ceb70f8 | 2229 | /* REG_0F18 */ |
252b5132 | 2230 | { |
1ceb70f8 L |
2231 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2232 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2233 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2234 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
ce518a5f L |
2235 | { "(bad)", { XX } }, |
2236 | { "(bad)", { XX } }, | |
2237 | { "(bad)", { XX } }, | |
2238 | { "(bad)", { XX } }, | |
252b5132 | 2239 | }, |
1ceb70f8 | 2240 | /* REG_0F71 */ |
a6bd098c | 2241 | { |
ce518a5f L |
2242 | { "(bad)", { XX } }, |
2243 | { "(bad)", { XX } }, | |
1ceb70f8 | 2244 | { MOD_TABLE (MOD_0F71_REG_2) }, |
ce518a5f | 2245 | { "(bad)", { XX } }, |
1ceb70f8 | 2246 | { MOD_TABLE (MOD_0F71_REG_4) }, |
ce518a5f | 2247 | { "(bad)", { XX } }, |
1ceb70f8 | 2248 | { MOD_TABLE (MOD_0F71_REG_6) }, |
ce518a5f | 2249 | { "(bad)", { XX } }, |
a6bd098c | 2250 | }, |
1ceb70f8 | 2251 | /* REG_0F72 */ |
a6bd098c | 2252 | { |
ce518a5f L |
2253 | { "(bad)", { XX } }, |
2254 | { "(bad)", { XX } }, | |
1ceb70f8 | 2255 | { MOD_TABLE (MOD_0F72_REG_2) }, |
ce518a5f | 2256 | { "(bad)", { XX } }, |
1ceb70f8 | 2257 | { MOD_TABLE (MOD_0F72_REG_4) }, |
ce518a5f | 2258 | { "(bad)", { XX } }, |
1ceb70f8 | 2259 | { MOD_TABLE (MOD_0F72_REG_6) }, |
ce518a5f | 2260 | { "(bad)", { XX } }, |
a6bd098c | 2261 | }, |
1ceb70f8 | 2262 | /* REG_0F73 */ |
252b5132 | 2263 | { |
ce518a5f L |
2264 | { "(bad)", { XX } }, |
2265 | { "(bad)", { XX } }, | |
1ceb70f8 L |
2266 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2267 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
ce518a5f | 2268 | { "(bad)", { XX } }, |
ce518a5f | 2269 | { "(bad)", { XX } }, |
1ceb70f8 L |
2270 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2271 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2272 | }, |
1ceb70f8 | 2273 | /* REG_0FA6 */ |
252b5132 | 2274 | { |
4e7d34a6 L |
2275 | { "montmul", { { OP_0f07, 0 } } }, |
2276 | { "xsha1", { { OP_0f07, 0 } } }, | |
2277 | { "xsha256", { { OP_0f07, 0 } } }, | |
2278 | { "(bad)", { { OP_0f07, 0 } } }, | |
2279 | { "(bad)", { { OP_0f07, 0 } } }, | |
2280 | { "(bad)", { { OP_0f07, 0 } } }, | |
2281 | { "(bad)", { { OP_0f07, 0 } } }, | |
2282 | { "(bad)", { { OP_0f07, 0 } } }, | |
2283 | }, | |
1ceb70f8 | 2284 | /* REG_0FA7 */ |
4e7d34a6 L |
2285 | { |
2286 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
2287 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
2288 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
2289 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
2290 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
2291 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
2292 | { "(bad)", { { OP_0f07, 0 } } }, | |
2293 | { "(bad)", { { OP_0f07, 0 } } }, | |
2294 | }, | |
1ceb70f8 | 2295 | /* REG_0FAE */ |
4e7d34a6 | 2296 | { |
1ceb70f8 L |
2297 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2298 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2299 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2300 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2301 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2302 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2303 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2304 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2305 | }, |
1ceb70f8 | 2306 | /* REG_0FBA */ |
252b5132 | 2307 | { |
ce518a5f L |
2308 | { "(bad)", { XX } }, |
2309 | { "(bad)", { XX } }, | |
d8faab4e L |
2310 | { "(bad)", { XX } }, |
2311 | { "(bad)", { XX } }, | |
4e7d34a6 L |
2312 | { "btQ", { Ev, Ib } }, |
2313 | { "btsQ", { Ev, Ib } }, | |
2314 | { "btrQ", { Ev, Ib } }, | |
2315 | { "btcQ", { Ev, Ib } }, | |
c608c12e | 2316 | }, |
1ceb70f8 | 2317 | /* REG_0FC7 */ |
c608c12e | 2318 | { |
b844680a | 2319 | { "(bad)", { XX } }, |
4e7d34a6 | 2320 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
d8faab4e | 2321 | { "(bad)", { XX } }, |
b844680a L |
2322 | { "(bad)", { XX } }, |
2323 | { "(bad)", { XX } }, | |
2324 | { "(bad)", { XX } }, | |
1ceb70f8 L |
2325 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2326 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2327 | }, |
c0f3af97 L |
2328 | /* REG_VEX_71 */ |
2329 | { | |
2330 | { "(bad)", { XX } }, | |
2331 | { "(bad)", { XX } }, | |
2332 | { MOD_TABLE (MOD_VEX_71_REG_2) }, | |
2333 | { "(bad)", { XX } }, | |
2334 | { MOD_TABLE (MOD_VEX_71_REG_4) }, | |
2335 | { "(bad)", { XX } }, | |
2336 | { MOD_TABLE (MOD_VEX_71_REG_6) }, | |
2337 | { "(bad)", { XX } }, | |
2338 | }, | |
2339 | /* REG_VEX_72 */ | |
2340 | { | |
2341 | { "(bad)", { XX } }, | |
2342 | { "(bad)", { XX } }, | |
2343 | { MOD_TABLE (MOD_VEX_72_REG_2) }, | |
2344 | { "(bad)", { XX } }, | |
2345 | { MOD_TABLE (MOD_VEX_72_REG_4) }, | |
2346 | { "(bad)", { XX } }, | |
2347 | { MOD_TABLE (MOD_VEX_72_REG_6) }, | |
2348 | { "(bad)", { XX } }, | |
2349 | }, | |
2350 | /* REG_VEX_73 */ | |
2351 | { | |
2352 | { "(bad)", { XX } }, | |
2353 | { "(bad)", { XX } }, | |
2354 | { MOD_TABLE (MOD_VEX_73_REG_2) }, | |
2355 | { MOD_TABLE (MOD_VEX_73_REG_3) }, | |
2356 | { "(bad)", { XX } }, | |
2357 | { "(bad)", { XX } }, | |
2358 | { MOD_TABLE (MOD_VEX_73_REG_6) }, | |
2359 | { MOD_TABLE (MOD_VEX_73_REG_7) }, | |
2360 | }, | |
2361 | /* REG_VEX_AE */ | |
2362 | { | |
2363 | { "(bad)", { XX } }, | |
2364 | { "(bad)", { XX } }, | |
2365 | { MOD_TABLE (MOD_VEX_AE_REG_2) }, | |
2366 | { MOD_TABLE (MOD_VEX_AE_REG_3) }, | |
2367 | { "(bad)", { XX } }, | |
2368 | { "(bad)", { XX } }, | |
2369 | { "(bad)", { XX } }, | |
2370 | { "(bad)", { XX } }, | |
2371 | }, | |
4e7d34a6 L |
2372 | }; |
2373 | ||
1ceb70f8 L |
2374 | static const struct dis386 prefix_table[][4] = { |
2375 | /* PREFIX_90 */ | |
252b5132 | 2376 | { |
4e7d34a6 L |
2377 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
2378 | { "pause", { XX } }, | |
2379 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
2380 | { "(bad)", { XX } }, | |
0f10071e | 2381 | }, |
4e7d34a6 | 2382 | |
1ceb70f8 | 2383 | /* PREFIX_0F10 */ |
cc0ec051 | 2384 | { |
4e7d34a6 L |
2385 | { "movups", { XM, EXx } }, |
2386 | { "movss", { XM, EXd } }, | |
2387 | { "movupd", { XM, EXx } }, | |
2388 | { "movsd", { XM, EXq } }, | |
30d1c836 | 2389 | }, |
4e7d34a6 | 2390 | |
1ceb70f8 | 2391 | /* PREFIX_0F11 */ |
30d1c836 | 2392 | { |
b6169b20 | 2393 | { "movups", { EXxS, XM } }, |
fa99fab2 | 2394 | { "movss", { EXdS, XM } }, |
b6169b20 | 2395 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 2396 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 2397 | }, |
252b5132 | 2398 | |
1ceb70f8 | 2399 | /* PREFIX_0F12 */ |
c608c12e | 2400 | { |
1ceb70f8 | 2401 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
2402 | { "movsldup", { XM, EXx } }, |
2403 | { "movlpd", { XM, EXq } }, | |
2404 | { "movddup", { XM, EXq } }, | |
c608c12e | 2405 | }, |
4e7d34a6 | 2406 | |
1ceb70f8 | 2407 | /* PREFIX_0F16 */ |
c608c12e | 2408 | { |
1ceb70f8 | 2409 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
2410 | { "movshdup", { XM, EXx } }, |
2411 | { "movhpd", { XM, EXq } }, | |
058f233b | 2412 | { "(bad)", { XX } }, |
c608c12e | 2413 | }, |
4e7d34a6 | 2414 | |
1ceb70f8 | 2415 | /* PREFIX_0F2A */ |
c608c12e | 2416 | { |
09335d05 | 2417 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 2418 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 2419 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 2420 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 2421 | }, |
4e7d34a6 | 2422 | |
1ceb70f8 | 2423 | /* PREFIX_0F2B */ |
c608c12e | 2424 | { |
75c135a8 L |
2425 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
2426 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
2427 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
2428 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 2429 | }, |
4e7d34a6 | 2430 | |
1ceb70f8 | 2431 | /* PREFIX_0F2C */ |
c608c12e | 2432 | { |
09335d05 L |
2433 | { "cvttps2pi", { MXC, EXq } }, |
2434 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 2435 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 2436 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 2437 | }, |
4e7d34a6 | 2438 | |
1ceb70f8 | 2439 | /* PREFIX_0F2D */ |
c608c12e | 2440 | { |
4e7d34a6 L |
2441 | { "cvtps2pi", { MXC, EXq } }, |
2442 | { "cvtss2siY", { Gv, EXd } }, | |
2443 | { "cvtpd2pi", { MXC, EXx } }, | |
2444 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 2445 | }, |
4e7d34a6 | 2446 | |
1ceb70f8 | 2447 | /* PREFIX_0F2E */ |
c608c12e | 2448 | { |
4e7d34a6 L |
2449 | { "ucomiss",{ XM, EXd } }, |
2450 | { "(bad)", { XX } }, | |
2451 | { "ucomisd",{ XM, EXq } }, | |
2452 | { "(bad)", { XX } }, | |
c608c12e | 2453 | }, |
4e7d34a6 | 2454 | |
1ceb70f8 | 2455 | /* PREFIX_0F2F */ |
c608c12e | 2456 | { |
4e7d34a6 L |
2457 | { "comiss", { XM, EXd } }, |
2458 | { "(bad)", { XX } }, | |
2459 | { "comisd", { XM, EXq } }, | |
2460 | { "(bad)", { XX } }, | |
c608c12e | 2461 | }, |
4e7d34a6 | 2462 | |
1ceb70f8 | 2463 | /* PREFIX_0F51 */ |
c608c12e | 2464 | { |
4e7d34a6 L |
2465 | { "sqrtps", { XM, EXx } }, |
2466 | { "sqrtss", { XM, EXd } }, | |
2467 | { "sqrtpd", { XM, EXx } }, | |
2468 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 2469 | }, |
4e7d34a6 | 2470 | |
1ceb70f8 | 2471 | /* PREFIX_0F52 */ |
c608c12e | 2472 | { |
4e7d34a6 L |
2473 | { "rsqrtps",{ XM, EXx } }, |
2474 | { "rsqrtss",{ XM, EXd } }, | |
058f233b L |
2475 | { "(bad)", { XX } }, |
2476 | { "(bad)", { XX } }, | |
c608c12e | 2477 | }, |
4e7d34a6 | 2478 | |
1ceb70f8 | 2479 | /* PREFIX_0F53 */ |
c608c12e | 2480 | { |
4e7d34a6 L |
2481 | { "rcpps", { XM, EXx } }, |
2482 | { "rcpss", { XM, EXd } }, | |
058f233b L |
2483 | { "(bad)", { XX } }, |
2484 | { "(bad)", { XX } }, | |
c608c12e | 2485 | }, |
4e7d34a6 | 2486 | |
1ceb70f8 | 2487 | /* PREFIX_0F58 */ |
c608c12e | 2488 | { |
4e7d34a6 L |
2489 | { "addps", { XM, EXx } }, |
2490 | { "addss", { XM, EXd } }, | |
2491 | { "addpd", { XM, EXx } }, | |
2492 | { "addsd", { XM, EXq } }, | |
c608c12e | 2493 | }, |
4e7d34a6 | 2494 | |
1ceb70f8 | 2495 | /* PREFIX_0F59 */ |
c608c12e | 2496 | { |
4e7d34a6 L |
2497 | { "mulps", { XM, EXx } }, |
2498 | { "mulss", { XM, EXd } }, | |
2499 | { "mulpd", { XM, EXx } }, | |
2500 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 2501 | }, |
4e7d34a6 | 2502 | |
1ceb70f8 | 2503 | /* PREFIX_0F5A */ |
041bd2e0 | 2504 | { |
4e7d34a6 L |
2505 | { "cvtps2pd", { XM, EXq } }, |
2506 | { "cvtss2sd", { XM, EXd } }, | |
2507 | { "cvtpd2ps", { XM, EXx } }, | |
2508 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 2509 | }, |
4e7d34a6 | 2510 | |
1ceb70f8 | 2511 | /* PREFIX_0F5B */ |
041bd2e0 | 2512 | { |
09a2c6cf L |
2513 | { "cvtdq2ps", { XM, EXx } }, |
2514 | { "cvttps2dq", { XM, EXx } }, | |
2515 | { "cvtps2dq", { XM, EXx } }, | |
058f233b | 2516 | { "(bad)", { XX } }, |
041bd2e0 | 2517 | }, |
4e7d34a6 | 2518 | |
1ceb70f8 | 2519 | /* PREFIX_0F5C */ |
041bd2e0 | 2520 | { |
4e7d34a6 L |
2521 | { "subps", { XM, EXx } }, |
2522 | { "subss", { XM, EXd } }, | |
2523 | { "subpd", { XM, EXx } }, | |
2524 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 2525 | }, |
4e7d34a6 | 2526 | |
1ceb70f8 | 2527 | /* PREFIX_0F5D */ |
041bd2e0 | 2528 | { |
4e7d34a6 L |
2529 | { "minps", { XM, EXx } }, |
2530 | { "minss", { XM, EXd } }, | |
2531 | { "minpd", { XM, EXx } }, | |
2532 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 2533 | }, |
4e7d34a6 | 2534 | |
1ceb70f8 | 2535 | /* PREFIX_0F5E */ |
041bd2e0 | 2536 | { |
4e7d34a6 L |
2537 | { "divps", { XM, EXx } }, |
2538 | { "divss", { XM, EXd } }, | |
2539 | { "divpd", { XM, EXx } }, | |
2540 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 2541 | }, |
4e7d34a6 | 2542 | |
1ceb70f8 | 2543 | /* PREFIX_0F5F */ |
041bd2e0 | 2544 | { |
4e7d34a6 L |
2545 | { "maxps", { XM, EXx } }, |
2546 | { "maxss", { XM, EXd } }, | |
2547 | { "maxpd", { XM, EXx } }, | |
2548 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 2549 | }, |
4e7d34a6 | 2550 | |
1ceb70f8 | 2551 | /* PREFIX_0F60 */ |
041bd2e0 | 2552 | { |
4e7d34a6 L |
2553 | { "punpcklbw",{ MX, EMd } }, |
2554 | { "(bad)", { XX } }, | |
2555 | { "punpcklbw",{ MX, EMx } }, | |
2556 | { "(bad)", { XX } }, | |
041bd2e0 | 2557 | }, |
4e7d34a6 | 2558 | |
1ceb70f8 | 2559 | /* PREFIX_0F61 */ |
041bd2e0 | 2560 | { |
4e7d34a6 L |
2561 | { "punpcklwd",{ MX, EMd } }, |
2562 | { "(bad)", { XX } }, | |
2563 | { "punpcklwd",{ MX, EMx } }, | |
2564 | { "(bad)", { XX } }, | |
041bd2e0 | 2565 | }, |
4e7d34a6 | 2566 | |
1ceb70f8 | 2567 | /* PREFIX_0F62 */ |
041bd2e0 | 2568 | { |
4e7d34a6 L |
2569 | { "punpckldq",{ MX, EMd } }, |
2570 | { "(bad)", { XX } }, | |
2571 | { "punpckldq",{ MX, EMx } }, | |
2572 | { "(bad)", { XX } }, | |
041bd2e0 | 2573 | }, |
4e7d34a6 | 2574 | |
1ceb70f8 | 2575 | /* PREFIX_0F6C */ |
041bd2e0 | 2576 | { |
058f233b L |
2577 | { "(bad)", { XX } }, |
2578 | { "(bad)", { XX } }, | |
4e7d34a6 | 2579 | { "punpcklqdq", { XM, EXx } }, |
058f233b | 2580 | { "(bad)", { XX } }, |
0f17484f | 2581 | }, |
4e7d34a6 | 2582 | |
1ceb70f8 | 2583 | /* PREFIX_0F6D */ |
0f17484f | 2584 | { |
058f233b L |
2585 | { "(bad)", { XX } }, |
2586 | { "(bad)", { XX } }, | |
4e7d34a6 | 2587 | { "punpckhqdq", { XM, EXx } }, |
058f233b | 2588 | { "(bad)", { XX } }, |
041bd2e0 | 2589 | }, |
4e7d34a6 | 2590 | |
1ceb70f8 | 2591 | /* PREFIX_0F6F */ |
ca164297 | 2592 | { |
4e7d34a6 L |
2593 | { "movq", { MX, EM } }, |
2594 | { "movdqu", { XM, EXx } }, | |
2595 | { "movdqa", { XM, EXx } }, | |
058f233b | 2596 | { "(bad)", { XX } }, |
ca164297 | 2597 | }, |
4e7d34a6 | 2598 | |
1ceb70f8 | 2599 | /* PREFIX_0F70 */ |
4e7d34a6 L |
2600 | { |
2601 | { "pshufw", { MX, EM, Ib } }, | |
2602 | { "pshufhw",{ XM, EXx, Ib } }, | |
2603 | { "pshufd", { XM, EXx, Ib } }, | |
2604 | { "pshuflw",{ XM, EXx, Ib } }, | |
2605 | }, | |
2606 | ||
92fddf8e L |
2607 | /* PREFIX_0F73_REG_3 */ |
2608 | { | |
2609 | { "(bad)", { XX } }, | |
2610 | { "(bad)", { XX } }, | |
2611 | { "psrldq", { XS, Ib } }, | |
2612 | { "(bad)", { XX } }, | |
2613 | }, | |
2614 | ||
2615 | /* PREFIX_0F73_REG_7 */ | |
2616 | { | |
2617 | { "(bad)", { XX } }, | |
2618 | { "(bad)", { XX } }, | |
2619 | { "pslldq", { XS, Ib } }, | |
2620 | { "(bad)", { XX } }, | |
2621 | }, | |
2622 | ||
1ceb70f8 | 2623 | /* PREFIX_0F78 */ |
4e7d34a6 L |
2624 | { |
2625 | {"vmread", { Em, Gm } }, | |
2626 | {"(bad)", { XX } }, | |
2627 | {"extrq", { XS, Ib, Ib } }, | |
2628 | {"insertq", { XM, XS, Ib, Ib } }, | |
2629 | }, | |
2630 | ||
1ceb70f8 | 2631 | /* PREFIX_0F79 */ |
4e7d34a6 L |
2632 | { |
2633 | {"vmwrite", { Gm, Em } }, | |
2634 | {"(bad)", { XX } }, | |
2635 | {"extrq", { XM, XS } }, | |
2636 | {"insertq", { XM, XS } }, | |
2637 | }, | |
2638 | ||
1ceb70f8 | 2639 | /* PREFIX_0F7C */ |
ca164297 | 2640 | { |
058f233b L |
2641 | { "(bad)", { XX } }, |
2642 | { "(bad)", { XX } }, | |
09a2c6cf L |
2643 | { "haddpd", { XM, EXx } }, |
2644 | { "haddps", { XM, EXx } }, | |
ca164297 | 2645 | }, |
4e7d34a6 | 2646 | |
1ceb70f8 | 2647 | /* PREFIX_0F7D */ |
ca164297 | 2648 | { |
058f233b L |
2649 | { "(bad)", { XX } }, |
2650 | { "(bad)", { XX } }, | |
09a2c6cf L |
2651 | { "hsubpd", { XM, EXx } }, |
2652 | { "hsubps", { XM, EXx } }, | |
ca164297 | 2653 | }, |
4e7d34a6 | 2654 | |
1ceb70f8 | 2655 | /* PREFIX_0F7E */ |
ca164297 | 2656 | { |
4e7d34a6 L |
2657 | { "movK", { Edq, MX } }, |
2658 | { "movq", { XM, EXq } }, | |
2659 | { "movK", { Edq, XM } }, | |
058f233b | 2660 | { "(bad)", { XX } }, |
ca164297 | 2661 | }, |
4e7d34a6 | 2662 | |
1ceb70f8 | 2663 | /* PREFIX_0F7F */ |
ca164297 | 2664 | { |
b6169b20 L |
2665 | { "movq", { EMS, MX } }, |
2666 | { "movdqu", { EXxS, XM } }, | |
2667 | { "movdqa", { EXxS, XM } }, | |
058f233b | 2668 | { "(bad)", { XX } }, |
ca164297 | 2669 | }, |
4e7d34a6 | 2670 | |
1ceb70f8 | 2671 | /* PREFIX_0FB8 */ |
ca164297 | 2672 | { |
4e7d34a6 L |
2673 | { "(bad)", { XX } }, |
2674 | { "popcntS", { Gv, Ev } }, | |
2675 | { "(bad)", { XX } }, | |
2676 | { "(bad)", { XX } }, | |
ca164297 | 2677 | }, |
4e7d34a6 | 2678 | |
1ceb70f8 | 2679 | /* PREFIX_0FBD */ |
050dfa73 | 2680 | { |
4e7d34a6 L |
2681 | { "bsrS", { Gv, Ev } }, |
2682 | { "lzcntS", { Gv, Ev } }, | |
2683 | { "bsrS", { Gv, Ev } }, | |
2684 | { "(bad)", { XX } }, | |
050dfa73 MM |
2685 | }, |
2686 | ||
1ceb70f8 | 2687 | /* PREFIX_0FC2 */ |
050dfa73 | 2688 | { |
ad19981d L |
2689 | { "cmpps", { XM, EXx, CMP } }, |
2690 | { "cmpss", { XM, EXd, CMP } }, | |
2691 | { "cmppd", { XM, EXx, CMP } }, | |
2692 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 2693 | }, |
246c51aa | 2694 | |
4ee52178 L |
2695 | /* PREFIX_0FC3 */ |
2696 | { | |
2697 | { "movntiS", { Ma, Gv } }, | |
2698 | { "(bad)", { XX } }, | |
2699 | { "(bad)", { XX } }, | |
2700 | { "(bad)", { XX } }, | |
2701 | }, | |
2702 | ||
92fddf8e L |
2703 | /* PREFIX_0FC7_REG_6 */ |
2704 | { | |
2705 | { "vmptrld",{ Mq } }, | |
2706 | { "vmxon", { Mq } }, | |
2707 | { "vmclear",{ Mq } }, | |
2708 | { "(bad)", { XX } }, | |
2709 | }, | |
2710 | ||
1ceb70f8 | 2711 | /* PREFIX_0FD0 */ |
050dfa73 | 2712 | { |
058f233b L |
2713 | { "(bad)", { XX } }, |
2714 | { "(bad)", { XX } }, | |
4e7d34a6 L |
2715 | { "addsubpd", { XM, EXx } }, |
2716 | { "addsubps", { XM, EXx } }, | |
246c51aa | 2717 | }, |
050dfa73 | 2718 | |
1ceb70f8 | 2719 | /* PREFIX_0FD6 */ |
050dfa73 | 2720 | { |
058f233b | 2721 | { "(bad)", { XX } }, |
4e7d34a6 | 2722 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 2723 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 2724 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
2725 | }, |
2726 | ||
1ceb70f8 | 2727 | /* PREFIX_0FE6 */ |
7918206c | 2728 | { |
058f233b | 2729 | { "(bad)", { XX } }, |
4e7d34a6 L |
2730 | { "cvtdq2pd", { XM, EXq } }, |
2731 | { "cvttpd2dq", { XM, EXx } }, | |
2732 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 2733 | }, |
8b38ad71 | 2734 | |
1ceb70f8 | 2735 | /* PREFIX_0FE7 */ |
8b38ad71 | 2736 | { |
4ee52178 | 2737 | { "movntq", { Mq, MX } }, |
058f233b | 2738 | { "(bad)", { XX } }, |
75c135a8 | 2739 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
058f233b | 2740 | { "(bad)", { XX } }, |
4e7d34a6 L |
2741 | }, |
2742 | ||
1ceb70f8 | 2743 | /* PREFIX_0FF0 */ |
4e7d34a6 | 2744 | { |
058f233b L |
2745 | { "(bad)", { XX } }, |
2746 | { "(bad)", { XX } }, | |
2747 | { "(bad)", { XX } }, | |
1ceb70f8 | 2748 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
2749 | }, |
2750 | ||
1ceb70f8 | 2751 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
2752 | { |
2753 | { "maskmovq", { MX, MS } }, | |
058f233b | 2754 | { "(bad)", { XX } }, |
4e7d34a6 | 2755 | { "maskmovdqu", { XM, XS } }, |
058f233b | 2756 | { "(bad)", { XX } }, |
8b38ad71 | 2757 | }, |
42903f7f | 2758 | |
1ceb70f8 | 2759 | /* PREFIX_0F3810 */ |
42903f7f L |
2760 | { |
2761 | { "(bad)", { XX } }, | |
2762 | { "(bad)", { XX } }, | |
88a94849 | 2763 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
2764 | { "(bad)", { XX } }, |
2765 | }, | |
2766 | ||
1ceb70f8 | 2767 | /* PREFIX_0F3814 */ |
42903f7f L |
2768 | { |
2769 | { "(bad)", { XX } }, | |
2770 | { "(bad)", { XX } }, | |
88a94849 | 2771 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
2772 | { "(bad)", { XX } }, |
2773 | }, | |
2774 | ||
1ceb70f8 | 2775 | /* PREFIX_0F3815 */ |
42903f7f L |
2776 | { |
2777 | { "(bad)", { XX } }, | |
2778 | { "(bad)", { XX } }, | |
09a2c6cf | 2779 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
2780 | { "(bad)", { XX } }, |
2781 | }, | |
2782 | ||
1ceb70f8 | 2783 | /* PREFIX_0F3817 */ |
42903f7f L |
2784 | { |
2785 | { "(bad)", { XX } }, | |
2786 | { "(bad)", { XX } }, | |
09a2c6cf | 2787 | { "ptest", { XM, EXx } }, |
42903f7f L |
2788 | { "(bad)", { XX } }, |
2789 | }, | |
2790 | ||
1ceb70f8 | 2791 | /* PREFIX_0F3820 */ |
42903f7f L |
2792 | { |
2793 | { "(bad)", { XX } }, | |
2794 | { "(bad)", { XX } }, | |
8976381e | 2795 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
2796 | { "(bad)", { XX } }, |
2797 | }, | |
2798 | ||
1ceb70f8 | 2799 | /* PREFIX_0F3821 */ |
42903f7f L |
2800 | { |
2801 | { "(bad)", { XX } }, | |
2802 | { "(bad)", { XX } }, | |
8976381e | 2803 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
2804 | { "(bad)", { XX } }, |
2805 | }, | |
2806 | ||
1ceb70f8 | 2807 | /* PREFIX_0F3822 */ |
42903f7f L |
2808 | { |
2809 | { "(bad)", { XX } }, | |
2810 | { "(bad)", { XX } }, | |
8976381e | 2811 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
2812 | { "(bad)", { XX } }, |
2813 | }, | |
2814 | ||
1ceb70f8 | 2815 | /* PREFIX_0F3823 */ |
42903f7f L |
2816 | { |
2817 | { "(bad)", { XX } }, | |
2818 | { "(bad)", { XX } }, | |
8976381e | 2819 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
2820 | { "(bad)", { XX } }, |
2821 | }, | |
2822 | ||
1ceb70f8 | 2823 | /* PREFIX_0F3824 */ |
42903f7f L |
2824 | { |
2825 | { "(bad)", { XX } }, | |
2826 | { "(bad)", { XX } }, | |
8976381e | 2827 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
2828 | { "(bad)", { XX } }, |
2829 | }, | |
2830 | ||
1ceb70f8 | 2831 | /* PREFIX_0F3825 */ |
42903f7f L |
2832 | { |
2833 | { "(bad)", { XX } }, | |
2834 | { "(bad)", { XX } }, | |
8976381e | 2835 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
2836 | { "(bad)", { XX } }, |
2837 | }, | |
2838 | ||
1ceb70f8 | 2839 | /* PREFIX_0F3828 */ |
42903f7f L |
2840 | { |
2841 | { "(bad)", { XX } }, | |
2842 | { "(bad)", { XX } }, | |
09a2c6cf | 2843 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
2844 | { "(bad)", { XX } }, |
2845 | }, | |
2846 | ||
1ceb70f8 | 2847 | /* PREFIX_0F3829 */ |
42903f7f L |
2848 | { |
2849 | { "(bad)", { XX } }, | |
2850 | { "(bad)", { XX } }, | |
09a2c6cf | 2851 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
2852 | { "(bad)", { XX } }, |
2853 | }, | |
2854 | ||
1ceb70f8 | 2855 | /* PREFIX_0F382A */ |
42903f7f L |
2856 | { |
2857 | { "(bad)", { XX } }, | |
2858 | { "(bad)", { XX } }, | |
75c135a8 | 2859 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
2860 | { "(bad)", { XX } }, |
2861 | }, | |
2862 | ||
1ceb70f8 | 2863 | /* PREFIX_0F382B */ |
42903f7f L |
2864 | { |
2865 | { "(bad)", { XX } }, | |
2866 | { "(bad)", { XX } }, | |
09a2c6cf | 2867 | { "packusdw", { XM, EXx } }, |
42903f7f L |
2868 | { "(bad)", { XX } }, |
2869 | }, | |
2870 | ||
1ceb70f8 | 2871 | /* PREFIX_0F3830 */ |
42903f7f L |
2872 | { |
2873 | { "(bad)", { XX } }, | |
2874 | { "(bad)", { XX } }, | |
8976381e | 2875 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
2876 | { "(bad)", { XX } }, |
2877 | }, | |
2878 | ||
1ceb70f8 | 2879 | /* PREFIX_0F3831 */ |
42903f7f L |
2880 | { |
2881 | { "(bad)", { XX } }, | |
2882 | { "(bad)", { XX } }, | |
8976381e | 2883 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
2884 | { "(bad)", { XX } }, |
2885 | }, | |
2886 | ||
1ceb70f8 | 2887 | /* PREFIX_0F3832 */ |
42903f7f L |
2888 | { |
2889 | { "(bad)", { XX } }, | |
2890 | { "(bad)", { XX } }, | |
8976381e | 2891 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
2892 | { "(bad)", { XX } }, |
2893 | }, | |
2894 | ||
1ceb70f8 | 2895 | /* PREFIX_0F3833 */ |
42903f7f L |
2896 | { |
2897 | { "(bad)", { XX } }, | |
2898 | { "(bad)", { XX } }, | |
8976381e | 2899 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
2900 | { "(bad)", { XX } }, |
2901 | }, | |
2902 | ||
1ceb70f8 | 2903 | /* PREFIX_0F3834 */ |
42903f7f L |
2904 | { |
2905 | { "(bad)", { XX } }, | |
2906 | { "(bad)", { XX } }, | |
8976381e | 2907 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
2908 | { "(bad)", { XX } }, |
2909 | }, | |
2910 | ||
1ceb70f8 | 2911 | /* PREFIX_0F3835 */ |
42903f7f L |
2912 | { |
2913 | { "(bad)", { XX } }, | |
2914 | { "(bad)", { XX } }, | |
8976381e | 2915 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
2916 | { "(bad)", { XX } }, |
2917 | }, | |
2918 | ||
1ceb70f8 | 2919 | /* PREFIX_0F3837 */ |
4e7d34a6 L |
2920 | { |
2921 | { "(bad)", { XX } }, | |
2922 | { "(bad)", { XX } }, | |
2923 | { "pcmpgtq", { XM, EXx } }, | |
2924 | { "(bad)", { XX } }, | |
2925 | }, | |
2926 | ||
1ceb70f8 | 2927 | /* PREFIX_0F3838 */ |
42903f7f L |
2928 | { |
2929 | { "(bad)", { XX } }, | |
2930 | { "(bad)", { XX } }, | |
09a2c6cf | 2931 | { "pminsb", { XM, EXx } }, |
42903f7f L |
2932 | { "(bad)", { XX } }, |
2933 | }, | |
2934 | ||
1ceb70f8 | 2935 | /* PREFIX_0F3839 */ |
42903f7f L |
2936 | { |
2937 | { "(bad)", { XX } }, | |
2938 | { "(bad)", { XX } }, | |
09a2c6cf | 2939 | { "pminsd", { XM, EXx } }, |
42903f7f L |
2940 | { "(bad)", { XX } }, |
2941 | }, | |
2942 | ||
1ceb70f8 | 2943 | /* PREFIX_0F383A */ |
42903f7f L |
2944 | { |
2945 | { "(bad)", { XX } }, | |
2946 | { "(bad)", { XX } }, | |
09a2c6cf | 2947 | { "pminuw", { XM, EXx } }, |
42903f7f L |
2948 | { "(bad)", { XX } }, |
2949 | }, | |
2950 | ||
1ceb70f8 | 2951 | /* PREFIX_0F383B */ |
42903f7f L |
2952 | { |
2953 | { "(bad)", { XX } }, | |
2954 | { "(bad)", { XX } }, | |
09a2c6cf | 2955 | { "pminud", { XM, EXx } }, |
42903f7f L |
2956 | { "(bad)", { XX } }, |
2957 | }, | |
2958 | ||
1ceb70f8 | 2959 | /* PREFIX_0F383C */ |
42903f7f L |
2960 | { |
2961 | { "(bad)", { XX } }, | |
2962 | { "(bad)", { XX } }, | |
09a2c6cf | 2963 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
2964 | { "(bad)", { XX } }, |
2965 | }, | |
2966 | ||
1ceb70f8 | 2967 | /* PREFIX_0F383D */ |
42903f7f L |
2968 | { |
2969 | { "(bad)", { XX } }, | |
2970 | { "(bad)", { XX } }, | |
09a2c6cf | 2971 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
2972 | { "(bad)", { XX } }, |
2973 | }, | |
2974 | ||
1ceb70f8 | 2975 | /* PREFIX_0F383E */ |
42903f7f L |
2976 | { |
2977 | { "(bad)", { XX } }, | |
2978 | { "(bad)", { XX } }, | |
09a2c6cf | 2979 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
2980 | { "(bad)", { XX } }, |
2981 | }, | |
2982 | ||
1ceb70f8 | 2983 | /* PREFIX_0F383F */ |
42903f7f L |
2984 | { |
2985 | { "(bad)", { XX } }, | |
2986 | { "(bad)", { XX } }, | |
09a2c6cf | 2987 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
2988 | { "(bad)", { XX } }, |
2989 | }, | |
2990 | ||
1ceb70f8 | 2991 | /* PREFIX_0F3840 */ |
42903f7f L |
2992 | { |
2993 | { "(bad)", { XX } }, | |
2994 | { "(bad)", { XX } }, | |
09a2c6cf | 2995 | { "pmulld", { XM, EXx } }, |
42903f7f L |
2996 | { "(bad)", { XX } }, |
2997 | }, | |
2998 | ||
1ceb70f8 | 2999 | /* PREFIX_0F3841 */ |
42903f7f L |
3000 | { |
3001 | { "(bad)", { XX } }, | |
3002 | { "(bad)", { XX } }, | |
09a2c6cf | 3003 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
3004 | { "(bad)", { XX } }, |
3005 | }, | |
3006 | ||
f1f8f695 L |
3007 | /* PREFIX_0F3880 */ |
3008 | { | |
3009 | { "(bad)", { XX } }, | |
3010 | { "(bad)", { XX } }, | |
3011 | { "invept", { Gm, Mo } }, | |
3012 | { "(bad)", { XX } }, | |
3013 | }, | |
3014 | ||
3015 | /* PREFIX_0F3881 */ | |
3016 | { | |
3017 | { "(bad)", { XX } }, | |
3018 | { "(bad)", { XX } }, | |
3019 | { "invvpid", { Gm, Mo } }, | |
3020 | { "(bad)", { XX } }, | |
3021 | }, | |
3022 | ||
c0f3af97 L |
3023 | /* PREFIX_0F38DB */ |
3024 | { | |
3025 | { "(bad)", { XX } }, | |
3026 | { "(bad)", { XX } }, | |
3027 | { "aesimc", { XM, EXx } }, | |
3028 | { "(bad)", { XX } }, | |
3029 | }, | |
3030 | ||
3031 | /* PREFIX_0F38DC */ | |
3032 | { | |
3033 | { "(bad)", { XX } }, | |
3034 | { "(bad)", { XX } }, | |
3035 | { "aesenc", { XM, EXx } }, | |
3036 | { "(bad)", { XX } }, | |
3037 | }, | |
3038 | ||
3039 | /* PREFIX_0F38DD */ | |
3040 | { | |
3041 | { "(bad)", { XX } }, | |
3042 | { "(bad)", { XX } }, | |
3043 | { "aesenclast", { XM, EXx } }, | |
3044 | { "(bad)", { XX } }, | |
3045 | }, | |
3046 | ||
3047 | /* PREFIX_0F38DE */ | |
3048 | { | |
3049 | { "(bad)", { XX } }, | |
3050 | { "(bad)", { XX } }, | |
3051 | { "aesdec", { XM, EXx } }, | |
3052 | { "(bad)", { XX } }, | |
3053 | }, | |
3054 | ||
3055 | /* PREFIX_0F38DF */ | |
3056 | { | |
3057 | { "(bad)", { XX } }, | |
3058 | { "(bad)", { XX } }, | |
3059 | { "aesdeclast", { XM, EXx } }, | |
3060 | { "(bad)", { XX } }, | |
3061 | }, | |
3062 | ||
1ceb70f8 | 3063 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3064 | { |
f1f8f695 | 3065 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4e7d34a6 | 3066 | { "(bad)", { XX } }, |
f1f8f695 | 3067 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4e7d34a6 L |
3068 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
3069 | }, | |
3070 | ||
1ceb70f8 | 3071 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3072 | { |
f1f8f695 | 3073 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4e7d34a6 | 3074 | { "(bad)", { XX } }, |
f1f8f695 | 3075 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4e7d34a6 L |
3076 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
3077 | }, | |
3078 | ||
1ceb70f8 | 3079 | /* PREFIX_0F3A08 */ |
42903f7f L |
3080 | { |
3081 | { "(bad)", { XX } }, | |
3082 | { "(bad)", { XX } }, | |
09a2c6cf | 3083 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
3084 | { "(bad)", { XX } }, |
3085 | }, | |
3086 | ||
1ceb70f8 | 3087 | /* PREFIX_0F3A09 */ |
42903f7f L |
3088 | { |
3089 | { "(bad)", { XX } }, | |
3090 | { "(bad)", { XX } }, | |
09a2c6cf | 3091 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
3092 | { "(bad)", { XX } }, |
3093 | }, | |
3094 | ||
1ceb70f8 | 3095 | /* PREFIX_0F3A0A */ |
42903f7f L |
3096 | { |
3097 | { "(bad)", { XX } }, | |
3098 | { "(bad)", { XX } }, | |
09335d05 | 3099 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
3100 | { "(bad)", { XX } }, |
3101 | }, | |
3102 | ||
1ceb70f8 | 3103 | /* PREFIX_0F3A0B */ |
42903f7f L |
3104 | { |
3105 | { "(bad)", { XX } }, | |
3106 | { "(bad)", { XX } }, | |
09335d05 | 3107 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
3108 | { "(bad)", { XX } }, |
3109 | }, | |
3110 | ||
1ceb70f8 | 3111 | /* PREFIX_0F3A0C */ |
42903f7f L |
3112 | { |
3113 | { "(bad)", { XX } }, | |
3114 | { "(bad)", { XX } }, | |
09a2c6cf | 3115 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
3116 | { "(bad)", { XX } }, |
3117 | }, | |
3118 | ||
1ceb70f8 | 3119 | /* PREFIX_0F3A0D */ |
42903f7f L |
3120 | { |
3121 | { "(bad)", { XX } }, | |
3122 | { "(bad)", { XX } }, | |
09a2c6cf | 3123 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
3124 | { "(bad)", { XX } }, |
3125 | }, | |
3126 | ||
1ceb70f8 | 3127 | /* PREFIX_0F3A0E */ |
42903f7f L |
3128 | { |
3129 | { "(bad)", { XX } }, | |
3130 | { "(bad)", { XX } }, | |
09a2c6cf | 3131 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
3132 | { "(bad)", { XX } }, |
3133 | }, | |
3134 | ||
1ceb70f8 | 3135 | /* PREFIX_0F3A14 */ |
42903f7f L |
3136 | { |
3137 | { "(bad)", { XX } }, | |
3138 | { "(bad)", { XX } }, | |
3139 | { "pextrb", { Edqb, XM, Ib } }, | |
3140 | { "(bad)", { XX } }, | |
3141 | }, | |
3142 | ||
1ceb70f8 | 3143 | /* PREFIX_0F3A15 */ |
42903f7f L |
3144 | { |
3145 | { "(bad)", { XX } }, | |
3146 | { "(bad)", { XX } }, | |
3147 | { "pextrw", { Edqw, XM, Ib } }, | |
3148 | { "(bad)", { XX } }, | |
3149 | }, | |
3150 | ||
1ceb70f8 | 3151 | /* PREFIX_0F3A16 */ |
42903f7f L |
3152 | { |
3153 | { "(bad)", { XX } }, | |
3154 | { "(bad)", { XX } }, | |
3155 | { "pextrK", { Edq, XM, Ib } }, | |
3156 | { "(bad)", { XX } }, | |
3157 | }, | |
3158 | ||
1ceb70f8 | 3159 | /* PREFIX_0F3A17 */ |
42903f7f L |
3160 | { |
3161 | { "(bad)", { XX } }, | |
3162 | { "(bad)", { XX } }, | |
3163 | { "extractps", { Edqd, XM, Ib } }, | |
3164 | { "(bad)", { XX } }, | |
3165 | }, | |
3166 | ||
1ceb70f8 | 3167 | /* PREFIX_0F3A20 */ |
42903f7f L |
3168 | { |
3169 | { "(bad)", { XX } }, | |
3170 | { "(bad)", { XX } }, | |
3171 | { "pinsrb", { XM, Edqb, Ib } }, | |
3172 | { "(bad)", { XX } }, | |
3173 | }, | |
3174 | ||
1ceb70f8 | 3175 | /* PREFIX_0F3A21 */ |
42903f7f L |
3176 | { |
3177 | { "(bad)", { XX } }, | |
3178 | { "(bad)", { XX } }, | |
8976381e | 3179 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
3180 | { "(bad)", { XX } }, |
3181 | }, | |
3182 | ||
1ceb70f8 | 3183 | /* PREFIX_0F3A22 */ |
42903f7f L |
3184 | { |
3185 | { "(bad)", { XX } }, | |
3186 | { "(bad)", { XX } }, | |
3187 | { "pinsrK", { XM, Edq, Ib } }, | |
3188 | { "(bad)", { XX } }, | |
3189 | }, | |
3190 | ||
1ceb70f8 | 3191 | /* PREFIX_0F3A40 */ |
42903f7f L |
3192 | { |
3193 | { "(bad)", { XX } }, | |
3194 | { "(bad)", { XX } }, | |
09a2c6cf | 3195 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
3196 | { "(bad)", { XX } }, |
3197 | }, | |
3198 | ||
1ceb70f8 | 3199 | /* PREFIX_0F3A41 */ |
42903f7f L |
3200 | { |
3201 | { "(bad)", { XX } }, | |
3202 | { "(bad)", { XX } }, | |
09a2c6cf | 3203 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
3204 | { "(bad)", { XX } }, |
3205 | }, | |
3206 | ||
1ceb70f8 | 3207 | /* PREFIX_0F3A42 */ |
42903f7f L |
3208 | { |
3209 | { "(bad)", { XX } }, | |
3210 | { "(bad)", { XX } }, | |
09a2c6cf | 3211 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f L |
3212 | { "(bad)", { XX } }, |
3213 | }, | |
381d071f | 3214 | |
c0f3af97 L |
3215 | /* PREFIX_0F3A44 */ |
3216 | { | |
3217 | { "(bad)", { XX } }, | |
3218 | { "(bad)", { XX } }, | |
3219 | { "pclmulqdq", { XM, EXx, PCLMUL } }, | |
3220 | { "(bad)", { XX } }, | |
3221 | }, | |
3222 | ||
1ceb70f8 | 3223 | /* PREFIX_0F3A60 */ |
381d071f L |
3224 | { |
3225 | { "(bad)", { XX } }, | |
3226 | { "(bad)", { XX } }, | |
4e7d34a6 | 3227 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
3228 | { "(bad)", { XX } }, |
3229 | }, | |
3230 | ||
1ceb70f8 | 3231 | /* PREFIX_0F3A61 */ |
381d071f L |
3232 | { |
3233 | { "(bad)", { XX } }, | |
3234 | { "(bad)", { XX } }, | |
4e7d34a6 | 3235 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f | 3236 | { "(bad)", { XX } }, |
381d071f L |
3237 | }, |
3238 | ||
1ceb70f8 | 3239 | /* PREFIX_0F3A62 */ |
381d071f L |
3240 | { |
3241 | { "(bad)", { XX } }, | |
3242 | { "(bad)", { XX } }, | |
4e7d34a6 | 3243 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f | 3244 | { "(bad)", { XX } }, |
381d071f L |
3245 | }, |
3246 | ||
1ceb70f8 | 3247 | /* PREFIX_0F3A63 */ |
381d071f L |
3248 | { |
3249 | { "(bad)", { XX } }, | |
3250 | { "(bad)", { XX } }, | |
4e7d34a6 | 3251 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f L |
3252 | { "(bad)", { XX } }, |
3253 | }, | |
09a2c6cf | 3254 | |
c0f3af97 | 3255 | /* PREFIX_0F3ADF */ |
09a2c6cf | 3256 | { |
c0f3af97 L |
3257 | { "(bad)", { XX } }, |
3258 | { "(bad)", { XX } }, | |
3259 | { "aeskeygenassist", { XM, EXx, Ib } }, | |
3260 | { "(bad)", { XX } }, | |
09a2c6cf L |
3261 | }, |
3262 | ||
c0f3af97 | 3263 | /* PREFIX_VEX_10 */ |
09a2c6cf | 3264 | { |
c0f3af97 L |
3265 | { "vmovups", { XM, EXx } }, |
3266 | { VEX_LEN_TABLE (VEX_LEN_10_P_1) }, | |
3267 | { "vmovupd", { XM, EXx } }, | |
3268 | { VEX_LEN_TABLE (VEX_LEN_10_P_3) }, | |
09a2c6cf L |
3269 | }, |
3270 | ||
c0f3af97 | 3271 | /* PREFIX_VEX_11 */ |
09a2c6cf | 3272 | { |
b6169b20 | 3273 | { "vmovups", { EXxS, XM } }, |
c0f3af97 | 3274 | { VEX_LEN_TABLE (VEX_LEN_11_P_1) }, |
b6169b20 | 3275 | { "vmovupd", { EXxS, XM } }, |
c0f3af97 | 3276 | { VEX_LEN_TABLE (VEX_LEN_11_P_3) }, |
09a2c6cf L |
3277 | }, |
3278 | ||
c0f3af97 | 3279 | /* PREFIX_VEX_12 */ |
09a2c6cf | 3280 | { |
c0f3af97 L |
3281 | { MOD_TABLE (MOD_VEX_12_PREFIX_0) }, |
3282 | { "vmovsldup", { XM, EXx } }, | |
3283 | { VEX_LEN_TABLE (VEX_LEN_12_P_2) }, | |
3284 | { "vmovddup", { XM, EXymmq } }, | |
09a2c6cf L |
3285 | }, |
3286 | ||
c0f3af97 | 3287 | /* PREFIX_VEX_16 */ |
09a2c6cf | 3288 | { |
c0f3af97 L |
3289 | { MOD_TABLE (MOD_VEX_16_PREFIX_0) }, |
3290 | { "vmovshdup", { XM, EXx } }, | |
3291 | { VEX_LEN_TABLE (VEX_LEN_16_P_2) }, | |
3292 | { "(bad)", { XX } }, | |
5f754f58 | 3293 | }, |
7c52e0e8 | 3294 | |
c0f3af97 | 3295 | /* PREFIX_VEX_2A */ |
5f754f58 | 3296 | { |
c0f3af97 L |
3297 | { "(bad)", { XX } }, |
3298 | { VEX_LEN_TABLE (VEX_LEN_2A_P_1) }, | |
3299 | { "(bad)", { XX } }, | |
3300 | { VEX_LEN_TABLE (VEX_LEN_2A_P_3) }, | |
5f754f58 | 3301 | }, |
7c52e0e8 | 3302 | |
c0f3af97 | 3303 | /* PREFIX_VEX_2C */ |
5f754f58 | 3304 | { |
c0f3af97 L |
3305 | { "(bad)", { XX } }, |
3306 | { VEX_LEN_TABLE (VEX_LEN_2C_P_1) }, | |
3307 | { "(bad)", { XX } }, | |
3308 | { VEX_LEN_TABLE (VEX_LEN_2C_P_3) }, | |
5f754f58 | 3309 | }, |
7c52e0e8 | 3310 | |
c0f3af97 | 3311 | /* PREFIX_VEX_2D */ |
7c52e0e8 | 3312 | { |
c0f3af97 L |
3313 | { "(bad)", { XX } }, |
3314 | { VEX_LEN_TABLE (VEX_LEN_2D_P_1) }, | |
3315 | { "(bad)", { XX } }, | |
3316 | { VEX_LEN_TABLE (VEX_LEN_2D_P_3) }, | |
7c52e0e8 L |
3317 | }, |
3318 | ||
c0f3af97 | 3319 | /* PREFIX_VEX_2E */ |
7c52e0e8 | 3320 | { |
c0f3af97 L |
3321 | { VEX_LEN_TABLE (VEX_LEN_2E_P_0) }, |
3322 | { "(bad)", { XX } }, | |
3323 | { VEX_LEN_TABLE (VEX_LEN_2E_P_2) }, | |
3324 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3325 | }, |
3326 | ||
c0f3af97 | 3327 | /* PREFIX_VEX_2F */ |
7c52e0e8 | 3328 | { |
c0f3af97 L |
3329 | { VEX_LEN_TABLE (VEX_LEN_2F_P_0) }, |
3330 | { "(bad)", { XX } }, | |
3331 | { VEX_LEN_TABLE (VEX_LEN_2F_P_2) }, | |
3332 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3333 | }, |
3334 | ||
c0f3af97 | 3335 | /* PREFIX_VEX_51 */ |
7c52e0e8 | 3336 | { |
c0f3af97 L |
3337 | { "vsqrtps", { XM, EXx } }, |
3338 | { VEX_LEN_TABLE (VEX_LEN_51_P_1) }, | |
3339 | { "vsqrtpd", { XM, EXx } }, | |
3340 | { VEX_LEN_TABLE (VEX_LEN_51_P_3) }, | |
7c52e0e8 L |
3341 | }, |
3342 | ||
c0f3af97 | 3343 | /* PREFIX_VEX_52 */ |
7c52e0e8 | 3344 | { |
c0f3af97 L |
3345 | { "vrsqrtps", { XM, EXx } }, |
3346 | { VEX_LEN_TABLE (VEX_LEN_52_P_1) }, | |
3347 | { "(bad)", { XX } }, | |
3348 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3349 | }, |
3350 | ||
c0f3af97 | 3351 | /* PREFIX_VEX_53 */ |
7c52e0e8 | 3352 | { |
c0f3af97 L |
3353 | { "vrcpps", { XM, EXx } }, |
3354 | { VEX_LEN_TABLE (VEX_LEN_53_P_1) }, | |
3355 | { "(bad)", { XX } }, | |
3356 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3357 | }, |
3358 | ||
c0f3af97 | 3359 | /* PREFIX_VEX_58 */ |
7c52e0e8 | 3360 | { |
c0f3af97 L |
3361 | { "vaddps", { XM, Vex, EXx } }, |
3362 | { VEX_LEN_TABLE (VEX_LEN_58_P_1) }, | |
3363 | { "vaddpd", { XM, Vex, EXx } }, | |
3364 | { VEX_LEN_TABLE (VEX_LEN_58_P_3) }, | |
7c52e0e8 L |
3365 | }, |
3366 | ||
c0f3af97 | 3367 | /* PREFIX_VEX_59 */ |
7c52e0e8 | 3368 | { |
c0f3af97 L |
3369 | { "vmulps", { XM, Vex, EXx } }, |
3370 | { VEX_LEN_TABLE (VEX_LEN_59_P_1) }, | |
3371 | { "vmulpd", { XM, Vex, EXx } }, | |
3372 | { VEX_LEN_TABLE (VEX_LEN_59_P_3) }, | |
7c52e0e8 L |
3373 | }, |
3374 | ||
c0f3af97 | 3375 | /* PREFIX_VEX_5A */ |
7c52e0e8 | 3376 | { |
c0f3af97 L |
3377 | { "vcvtps2pd", { XM, EXxmmq } }, |
3378 | { VEX_LEN_TABLE (VEX_LEN_5A_P_1) }, | |
3379 | { "vcvtpd2ps%XY", { XMM, EXx } }, | |
3380 | { VEX_LEN_TABLE (VEX_LEN_5A_P_3) }, | |
7c52e0e8 L |
3381 | }, |
3382 | ||
c0f3af97 | 3383 | /* PREFIX_VEX_5B */ |
7c52e0e8 | 3384 | { |
c0f3af97 L |
3385 | { "vcvtdq2ps", { XM, EXx } }, |
3386 | { "vcvttps2dq", { XM, EXx } }, | |
3387 | { "vcvtps2dq", { XM, EXx } }, | |
3388 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3389 | }, |
3390 | ||
c0f3af97 | 3391 | /* PREFIX_VEX_5C */ |
7c52e0e8 | 3392 | { |
c0f3af97 L |
3393 | { "vsubps", { XM, Vex, EXx } }, |
3394 | { VEX_LEN_TABLE (VEX_LEN_5C_P_1) }, | |
3395 | { "vsubpd", { XM, Vex, EXx } }, | |
3396 | { VEX_LEN_TABLE (VEX_LEN_5C_P_3) }, | |
7c52e0e8 L |
3397 | }, |
3398 | ||
c0f3af97 | 3399 | /* PREFIX_VEX_5D */ |
7c52e0e8 | 3400 | { |
c0f3af97 L |
3401 | { "vminps", { XM, Vex, EXx } }, |
3402 | { VEX_LEN_TABLE (VEX_LEN_5D_P_1) }, | |
3403 | { "vminpd", { XM, Vex, EXx } }, | |
3404 | { VEX_LEN_TABLE (VEX_LEN_5D_P_3) }, | |
7c52e0e8 L |
3405 | }, |
3406 | ||
c0f3af97 | 3407 | /* PREFIX_VEX_5E */ |
7c52e0e8 | 3408 | { |
c0f3af97 L |
3409 | { "vdivps", { XM, Vex, EXx } }, |
3410 | { VEX_LEN_TABLE (VEX_LEN_5E_P_1) }, | |
3411 | { "vdivpd", { XM, Vex, EXx } }, | |
3412 | { VEX_LEN_TABLE (VEX_LEN_5E_P_3) }, | |
7c52e0e8 L |
3413 | }, |
3414 | ||
c0f3af97 | 3415 | /* PREFIX_VEX_5F */ |
7c52e0e8 | 3416 | { |
c0f3af97 L |
3417 | { "vmaxps", { XM, Vex, EXx } }, |
3418 | { VEX_LEN_TABLE (VEX_LEN_5F_P_1) }, | |
3419 | { "vmaxpd", { XM, Vex, EXx } }, | |
3420 | { VEX_LEN_TABLE (VEX_LEN_5F_P_3) }, | |
7c52e0e8 L |
3421 | }, |
3422 | ||
c0f3af97 | 3423 | /* PREFIX_VEX_60 */ |
7c52e0e8 | 3424 | { |
c0f3af97 L |
3425 | { "(bad)", { XX } }, |
3426 | { "(bad)", { XX } }, | |
3427 | { VEX_LEN_TABLE (VEX_LEN_60_P_2) }, | |
3428 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3429 | }, |
3430 | ||
c0f3af97 | 3431 | /* PREFIX_VEX_61 */ |
7c52e0e8 | 3432 | { |
c0f3af97 L |
3433 | { "(bad)", { XX } }, |
3434 | { "(bad)", { XX } }, | |
3435 | { VEX_LEN_TABLE (VEX_LEN_61_P_2) }, | |
3436 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3437 | }, |
3438 | ||
c0f3af97 | 3439 | /* PREFIX_VEX_62 */ |
7c52e0e8 | 3440 | { |
c0f3af97 L |
3441 | { "(bad)", { XX } }, |
3442 | { "(bad)", { XX } }, | |
3443 | { VEX_LEN_TABLE (VEX_LEN_62_P_2) }, | |
3444 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3445 | }, |
3446 | ||
c0f3af97 | 3447 | /* PREFIX_VEX_63 */ |
7c52e0e8 | 3448 | { |
c0f3af97 L |
3449 | { "(bad)", { XX } }, |
3450 | { "(bad)", { XX } }, | |
3451 | { VEX_LEN_TABLE (VEX_LEN_63_P_2) }, | |
3452 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3453 | }, |
3454 | ||
c0f3af97 | 3455 | /* PREFIX_VEX_64 */ |
7c52e0e8 | 3456 | { |
c0f3af97 L |
3457 | { "(bad)", { XX } }, |
3458 | { "(bad)", { XX } }, | |
3459 | { VEX_LEN_TABLE (VEX_LEN_64_P_2) }, | |
3460 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3461 | }, |
3462 | ||
c0f3af97 | 3463 | /* PREFIX_VEX_65 */ |
7c52e0e8 | 3464 | { |
c0f3af97 L |
3465 | { "(bad)", { XX } }, |
3466 | { "(bad)", { XX } }, | |
3467 | { VEX_LEN_TABLE (VEX_LEN_65_P_2) }, | |
3468 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3469 | }, |
3470 | ||
c0f3af97 | 3471 | /* PREFIX_VEX_66 */ |
7c52e0e8 | 3472 | { |
c0f3af97 L |
3473 | { "(bad)", { XX } }, |
3474 | { "(bad)", { XX } }, | |
3475 | { VEX_LEN_TABLE (VEX_LEN_66_P_2) }, | |
3476 | { "(bad)", { XX } }, | |
7c52e0e8 | 3477 | }, |
6439fc28 | 3478 | |
c0f3af97 | 3479 | /* PREFIX_VEX_67 */ |
331d2d0d | 3480 | { |
c0f3af97 L |
3481 | { "(bad)", { XX } }, |
3482 | { "(bad)", { XX } }, | |
3483 | { VEX_LEN_TABLE (VEX_LEN_67_P_2) }, | |
3484 | { "(bad)", { XX } }, | |
3485 | }, | |
3486 | ||
3487 | /* PREFIX_VEX_68 */ | |
3488 | { | |
3489 | { "(bad)", { XX } }, | |
3490 | { "(bad)", { XX } }, | |
3491 | { VEX_LEN_TABLE (VEX_LEN_68_P_2) }, | |
3492 | { "(bad)", { XX } }, | |
3493 | }, | |
3494 | ||
3495 | /* PREFIX_VEX_69 */ | |
3496 | { | |
3497 | { "(bad)", { XX } }, | |
3498 | { "(bad)", { XX } }, | |
3499 | { VEX_LEN_TABLE (VEX_LEN_69_P_2) }, | |
3500 | { "(bad)", { XX } }, | |
3501 | }, | |
3502 | ||
3503 | /* PREFIX_VEX_6A */ | |
3504 | { | |
3505 | { "(bad)", { XX } }, | |
3506 | { "(bad)", { XX } }, | |
3507 | { VEX_LEN_TABLE (VEX_LEN_6A_P_2) }, | |
3508 | { "(bad)", { XX } }, | |
3509 | }, | |
3510 | ||
3511 | /* PREFIX_VEX_6B */ | |
3512 | { | |
3513 | { "(bad)", { XX } }, | |
3514 | { "(bad)", { XX } }, | |
3515 | { VEX_LEN_TABLE (VEX_LEN_6B_P_2) }, | |
3516 | { "(bad)", { XX } }, | |
3517 | }, | |
3518 | ||
3519 | /* PREFIX_VEX_6C */ | |
3520 | { | |
3521 | { "(bad)", { XX } }, | |
3522 | { "(bad)", { XX } }, | |
3523 | { VEX_LEN_TABLE (VEX_LEN_6C_P_2) }, | |
3524 | { "(bad)", { XX } }, | |
3525 | }, | |
3526 | ||
3527 | /* PREFIX_VEX_6D */ | |
3528 | { | |
3529 | { "(bad)", { XX } }, | |
3530 | { "(bad)", { XX } }, | |
3531 | { VEX_LEN_TABLE (VEX_LEN_6D_P_2) }, | |
3532 | { "(bad)", { XX } }, | |
3533 | }, | |
3534 | ||
3535 | /* PREFIX_VEX_6E */ | |
3536 | { | |
3537 | { "(bad)", { XX } }, | |
3538 | { "(bad)", { XX } }, | |
3539 | { VEX_LEN_TABLE (VEX_LEN_6E_P_2) }, | |
3540 | { "(bad)", { XX } }, | |
3541 | }, | |
3542 | ||
3543 | /* PREFIX_VEX_6F */ | |
3544 | { | |
3545 | { "(bad)", { XX } }, | |
3546 | { "vmovdqu", { XM, EXx } }, | |
3547 | { "vmovdqa", { XM, EXx } }, | |
3548 | { "(bad)", { XX } }, | |
3549 | }, | |
3550 | ||
3551 | /* PREFIX_VEX_70 */ | |
3552 | { | |
3553 | { "(bad)", { XX } }, | |
3554 | { VEX_LEN_TABLE (VEX_LEN_70_P_1) }, | |
3555 | { VEX_LEN_TABLE (VEX_LEN_70_P_2) }, | |
3556 | { VEX_LEN_TABLE (VEX_LEN_70_P_3) }, | |
3557 | }, | |
3558 | ||
3559 | /* PREFIX_VEX_71_REG_2 */ | |
3560 | { | |
3561 | { "(bad)", { XX } }, | |
3562 | { "(bad)", { XX } }, | |
3563 | { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) }, | |
3564 | { "(bad)", { XX } }, | |
3565 | }, | |
3566 | ||
3567 | /* PREFIX_VEX_71_REG_4 */ | |
3568 | { | |
3569 | { "(bad)", { XX } }, | |
3570 | { "(bad)", { XX } }, | |
3571 | { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) }, | |
3572 | { "(bad)", { XX } }, | |
3573 | }, | |
3574 | ||
3575 | /* PREFIX_VEX_71_REG_6 */ | |
3576 | { | |
3577 | { "(bad)", { XX } }, | |
3578 | { "(bad)", { XX } }, | |
3579 | { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) }, | |
3580 | { "(bad)", { XX } }, | |
3581 | }, | |
3582 | ||
3583 | /* PREFIX_VEX_72_REG_2 */ | |
3584 | { | |
3585 | { "(bad)", { XX } }, | |
3586 | { "(bad)", { XX } }, | |
3587 | { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) }, | |
3588 | { "(bad)", { XX } }, | |
3589 | }, | |
3590 | ||
3591 | /* PREFIX_VEX_72_REG_4 */ | |
3592 | { | |
3593 | { "(bad)", { XX } }, | |
3594 | { "(bad)", { XX } }, | |
3595 | { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) }, | |
3596 | { "(bad)", { XX } }, | |
3597 | }, | |
3598 | ||
3599 | /* PREFIX_VEX_72_REG_6 */ | |
3600 | { | |
3601 | { "(bad)", { XX } }, | |
3602 | { "(bad)", { XX } }, | |
3603 | { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) }, | |
3604 | { "(bad)", { XX } }, | |
3605 | }, | |
3606 | ||
3607 | /* PREFIX_VEX_73_REG_2 */ | |
3608 | { | |
3609 | { "(bad)", { XX } }, | |
3610 | { "(bad)", { XX } }, | |
3611 | { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) }, | |
3612 | { "(bad)", { XX } }, | |
3613 | }, | |
3614 | ||
3615 | /* PREFIX_VEX_73_REG_3 */ | |
3616 | { | |
3617 | { "(bad)", { XX } }, | |
3618 | { "(bad)", { XX } }, | |
3619 | { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) }, | |
3620 | { "(bad)", { XX } }, | |
3621 | }, | |
3622 | ||
3623 | /* PREFIX_VEX_73_REG_6 */ | |
3624 | { | |
3625 | { "(bad)", { XX } }, | |
3626 | { "(bad)", { XX } }, | |
3627 | { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) }, | |
3628 | { "(bad)", { XX } }, | |
3629 | }, | |
3630 | ||
3631 | /* PREFIX_VEX_73_REG_7 */ | |
3632 | { | |
3633 | { "(bad)", { XX } }, | |
3634 | { "(bad)", { XX } }, | |
3635 | { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) }, | |
3636 | { "(bad)", { XX } }, | |
3637 | }, | |
3638 | ||
3639 | /* PREFIX_VEX_74 */ | |
3640 | { | |
3641 | { "(bad)", { XX } }, | |
3642 | { "(bad)", { XX } }, | |
3643 | { VEX_LEN_TABLE (VEX_LEN_74_P_2) }, | |
3644 | { "(bad)", { XX } }, | |
3645 | }, | |
3646 | ||
3647 | /* PREFIX_VEX_75 */ | |
3648 | { | |
3649 | { "(bad)", { XX } }, | |
3650 | { "(bad)", { XX } }, | |
3651 | { VEX_LEN_TABLE (VEX_LEN_75_P_2) }, | |
3652 | { "(bad)", { XX } }, | |
3653 | }, | |
3654 | ||
3655 | /* PREFIX_VEX_76 */ | |
3656 | { | |
3657 | { "(bad)", { XX } }, | |
3658 | { "(bad)", { XX } }, | |
3659 | { VEX_LEN_TABLE (VEX_LEN_76_P_2) }, | |
3660 | { "(bad)", { XX } }, | |
3661 | }, | |
3662 | ||
3663 | /* PREFIX_VEX_77 */ | |
3664 | { | |
3665 | { "", { VZERO } }, | |
3666 | { "(bad)", { XX } }, | |
3667 | { "(bad)", { XX } }, | |
3668 | { "(bad)", { XX } }, | |
3669 | }, | |
3670 | ||
3671 | /* PREFIX_VEX_7C */ | |
3672 | { | |
3673 | { "(bad)", { XX } }, | |
3674 | { "(bad)", { XX } }, | |
3675 | { "vhaddpd", { XM, Vex, EXx } }, | |
3676 | { "vhaddps", { XM, Vex, EXx } }, | |
3677 | }, | |
3678 | ||
3679 | /* PREFIX_VEX_7D */ | |
3680 | { | |
3681 | { "(bad)", { XX } }, | |
3682 | { "(bad)", { XX } }, | |
3683 | { "vhsubpd", { XM, Vex, EXx } }, | |
3684 | { "vhsubps", { XM, Vex, EXx } }, | |
3685 | }, | |
3686 | ||
3687 | /* PREFIX_VEX_7E */ | |
3688 | { | |
3689 | { "(bad)", { XX } }, | |
3690 | { VEX_LEN_TABLE (VEX_LEN_7E_P_1) }, | |
3691 | { VEX_LEN_TABLE (VEX_LEN_7E_P_2) }, | |
3692 | { "(bad)", { XX } }, | |
3693 | }, | |
3694 | ||
3695 | /* PREFIX_VEX_7F */ | |
3696 | { | |
3697 | { "(bad)", { XX } }, | |
b6169b20 L |
3698 | { "vmovdqu", { EXxS, XM } }, |
3699 | { "vmovdqa", { EXxS, XM } }, | |
c0f3af97 L |
3700 | { "(bad)", { XX } }, |
3701 | }, | |
3702 | ||
3703 | /* PREFIX_VEX_C2 */ | |
3704 | { | |
3705 | { "vcmpps", { XM, Vex, EXx, VCMP } }, | |
3706 | { VEX_LEN_TABLE (VEX_LEN_C2_P_1) }, | |
3707 | { "vcmppd", { XM, Vex, EXx, VCMP } }, | |
3708 | { VEX_LEN_TABLE (VEX_LEN_C2_P_3) }, | |
3709 | }, | |
3710 | ||
3711 | /* PREFIX_VEX_C4 */ | |
3712 | { | |
3713 | { "(bad)", { XX } }, | |
3714 | { "(bad)", { XX } }, | |
3715 | { VEX_LEN_TABLE (VEX_LEN_C4_P_2) }, | |
3716 | { "(bad)", { XX } }, | |
3717 | }, | |
3718 | ||
3719 | /* PREFIX_VEX_C5 */ | |
3720 | { | |
3721 | { "(bad)", { XX } }, | |
3722 | { "(bad)", { XX } }, | |
3723 | { VEX_LEN_TABLE (VEX_LEN_C5_P_2) }, | |
3724 | { "(bad)", { XX } }, | |
3725 | }, | |
3726 | ||
3727 | /* PREFIX_VEX_D0 */ | |
3728 | { | |
3729 | { "(bad)", { XX } }, | |
3730 | { "(bad)", { XX } }, | |
3731 | { "vaddsubpd", { XM, Vex, EXx } }, | |
3732 | { "vaddsubps", { XM, Vex, EXx } }, | |
3733 | }, | |
3734 | ||
3735 | /* PREFIX_VEX_D1 */ | |
3736 | { | |
3737 | { "(bad)", { XX } }, | |
3738 | { "(bad)", { XX } }, | |
3739 | { VEX_LEN_TABLE (VEX_LEN_D1_P_2) }, | |
3740 | { "(bad)", { XX } }, | |
3741 | }, | |
3742 | ||
3743 | /* PREFIX_VEX_D2 */ | |
3744 | { | |
3745 | { "(bad)", { XX } }, | |
3746 | { "(bad)", { XX } }, | |
3747 | { VEX_LEN_TABLE (VEX_LEN_D2_P_2) }, | |
3748 | { "(bad)", { XX } }, | |
3749 | }, | |
3750 | ||
3751 | /* PREFIX_VEX_D3 */ | |
3752 | { | |
3753 | { "(bad)", { XX } }, | |
3754 | { "(bad)", { XX } }, | |
3755 | { VEX_LEN_TABLE (VEX_LEN_D3_P_2) }, | |
3756 | { "(bad)", { XX } }, | |
3757 | }, | |
3758 | ||
3759 | /* PREFIX_VEX_D4 */ | |
3760 | { | |
3761 | { "(bad)", { XX } }, | |
3762 | { "(bad)", { XX } }, | |
3763 | { VEX_LEN_TABLE (VEX_LEN_D4_P_2) }, | |
3764 | { "(bad)", { XX } }, | |
3765 | }, | |
3766 | ||
3767 | /* PREFIX_VEX_D5 */ | |
3768 | { | |
3769 | { "(bad)", { XX } }, | |
3770 | { "(bad)", { XX } }, | |
3771 | { VEX_LEN_TABLE (VEX_LEN_D5_P_2) }, | |
3772 | { "(bad)", { XX } }, | |
3773 | }, | |
3774 | ||
3775 | /* PREFIX_VEX_D6 */ | |
3776 | { | |
3777 | { "(bad)", { XX } }, | |
3778 | { "(bad)", { XX } }, | |
3779 | { VEX_LEN_TABLE (VEX_LEN_D6_P_2) }, | |
3780 | { "(bad)", { XX } }, | |
3781 | }, | |
3782 | ||
3783 | /* PREFIX_VEX_D7 */ | |
3784 | { | |
3785 | { "(bad)", { XX } }, | |
3786 | { "(bad)", { XX } }, | |
3787 | { MOD_TABLE (MOD_VEX_D7_PREFIX_2) }, | |
3788 | { "(bad)", { XX } }, | |
3789 | }, | |
3790 | ||
3791 | /* PREFIX_VEX_D8 */ | |
3792 | { | |
3793 | { "(bad)", { XX } }, | |
3794 | { "(bad)", { XX } }, | |
3795 | { VEX_LEN_TABLE (VEX_LEN_D8_P_2) }, | |
3796 | { "(bad)", { XX } }, | |
3797 | }, | |
3798 | ||
3799 | /* PREFIX_VEX_D9 */ | |
3800 | { | |
3801 | { "(bad)", { XX } }, | |
3802 | { "(bad)", { XX } }, | |
3803 | { VEX_LEN_TABLE (VEX_LEN_D9_P_2) }, | |
3804 | { "(bad)", { XX } }, | |
3805 | }, | |
3806 | ||
3807 | /* PREFIX_VEX_DA */ | |
3808 | { | |
3809 | { "(bad)", { XX } }, | |
3810 | { "(bad)", { XX } }, | |
3811 | { VEX_LEN_TABLE (VEX_LEN_DA_P_2) }, | |
3812 | { "(bad)", { XX } }, | |
3813 | }, | |
3814 | ||
3815 | /* PREFIX_VEX_DB */ | |
3816 | { | |
3817 | { "(bad)", { XX } }, | |
3818 | { "(bad)", { XX } }, | |
3819 | { VEX_LEN_TABLE (VEX_LEN_DB_P_2) }, | |
3820 | { "(bad)", { XX } }, | |
3821 | }, | |
3822 | ||
3823 | /* PREFIX_VEX_DC */ | |
3824 | { | |
3825 | { "(bad)", { XX } }, | |
3826 | { "(bad)", { XX } }, | |
3827 | { VEX_LEN_TABLE (VEX_LEN_DC_P_2) }, | |
3828 | { "(bad)", { XX } }, | |
3829 | }, | |
3830 | ||
3831 | /* PREFIX_VEX_DD */ | |
3832 | { | |
3833 | { "(bad)", { XX } }, | |
3834 | { "(bad)", { XX } }, | |
3835 | { VEX_LEN_TABLE (VEX_LEN_DD_P_2) }, | |
3836 | { "(bad)", { XX } }, | |
3837 | }, | |
3838 | ||
3839 | /* PREFIX_VEX_DE */ | |
3840 | { | |
3841 | { "(bad)", { XX } }, | |
3842 | { "(bad)", { XX } }, | |
3843 | { VEX_LEN_TABLE (VEX_LEN_DE_P_2) }, | |
3844 | { "(bad)", { XX } }, | |
3845 | }, | |
3846 | ||
3847 | /* PREFIX_VEX_DF */ | |
3848 | { | |
3849 | { "(bad)", { XX } }, | |
3850 | { "(bad)", { XX } }, | |
3851 | { VEX_LEN_TABLE (VEX_LEN_DF_P_2) }, | |
3852 | { "(bad)", { XX } }, | |
3853 | }, | |
3854 | ||
3855 | /* PREFIX_VEX_E0 */ | |
3856 | { | |
3857 | { "(bad)", { XX } }, | |
3858 | { "(bad)", { XX } }, | |
3859 | { VEX_LEN_TABLE (VEX_LEN_E0_P_2) }, | |
3860 | { "(bad)", { XX } }, | |
3861 | }, | |
3862 | ||
3863 | /* PREFIX_VEX_E1 */ | |
3864 | { | |
3865 | { "(bad)", { XX } }, | |
3866 | { "(bad)", { XX } }, | |
3867 | { VEX_LEN_TABLE (VEX_LEN_E1_P_2) }, | |
3868 | { "(bad)", { XX } }, | |
3869 | }, | |
3870 | ||
3871 | /* PREFIX_VEX_E2 */ | |
3872 | { | |
3873 | { "(bad)", { XX } }, | |
3874 | { "(bad)", { XX } }, | |
3875 | { VEX_LEN_TABLE (VEX_LEN_E2_P_2) }, | |
3876 | { "(bad)", { XX } }, | |
3877 | }, | |
3878 | ||
3879 | /* PREFIX_VEX_E3 */ | |
3880 | { | |
3881 | { "(bad)", { XX } }, | |
3882 | { "(bad)", { XX } }, | |
3883 | { VEX_LEN_TABLE (VEX_LEN_E3_P_2) }, | |
3884 | { "(bad)", { XX } }, | |
3885 | }, | |
3886 | ||
3887 | /* PREFIX_VEX_E4 */ | |
3888 | { | |
3889 | { "(bad)", { XX } }, | |
3890 | { "(bad)", { XX } }, | |
3891 | { VEX_LEN_TABLE (VEX_LEN_E4_P_2) }, | |
3892 | { "(bad)", { XX } }, | |
3893 | }, | |
3894 | ||
3895 | /* PREFIX_VEX_E5 */ | |
3896 | { | |
3897 | { "(bad)", { XX } }, | |
3898 | { "(bad)", { XX } }, | |
3899 | { VEX_LEN_TABLE (VEX_LEN_E5_P_2) }, | |
3900 | { "(bad)", { XX } }, | |
3901 | }, | |
3902 | ||
3903 | /* PREFIX_VEX_E6 */ | |
3904 | { | |
3905 | { "(bad)", { XX } }, | |
3906 | { "vcvtdq2pd", { XM, EXxmmq } }, | |
3907 | { "vcvttpd2dq%XY", { XMM, EXx } }, | |
3908 | { "vcvtpd2dq%XY", { XMM, EXx } }, | |
3909 | }, | |
3910 | ||
3911 | /* PREFIX_VEX_E7 */ | |
3912 | { | |
3913 | { "(bad)", { XX } }, | |
3914 | { "(bad)", { XX } }, | |
3915 | { MOD_TABLE (MOD_VEX_E7_PREFIX_2) }, | |
3916 | { "(bad)", { XX } }, | |
3917 | }, | |
3918 | ||
3919 | /* PREFIX_VEX_E8 */ | |
3920 | { | |
3921 | { "(bad)", { XX } }, | |
3922 | { "(bad)", { XX } }, | |
3923 | { VEX_LEN_TABLE (VEX_LEN_E8_P_2) }, | |
3924 | { "(bad)", { XX } }, | |
3925 | }, | |
3926 | ||
3927 | /* PREFIX_VEX_E9 */ | |
3928 | { | |
3929 | { "(bad)", { XX } }, | |
3930 | { "(bad)", { XX } }, | |
3931 | { VEX_LEN_TABLE (VEX_LEN_E9_P_2) }, | |
3932 | { "(bad)", { XX } }, | |
3933 | }, | |
3934 | ||
3935 | /* PREFIX_VEX_EA */ | |
3936 | { | |
3937 | { "(bad)", { XX } }, | |
3938 | { "(bad)", { XX } }, | |
3939 | { VEX_LEN_TABLE (VEX_LEN_EA_P_2) }, | |
3940 | { "(bad)", { XX } }, | |
3941 | }, | |
3942 | ||
3943 | /* PREFIX_VEX_EB */ | |
3944 | { | |
3945 | { "(bad)", { XX } }, | |
3946 | { "(bad)", { XX } }, | |
3947 | { VEX_LEN_TABLE (VEX_LEN_EB_P_2) }, | |
3948 | { "(bad)", { XX } }, | |
3949 | }, | |
3950 | ||
3951 | /* PREFIX_VEX_EC */ | |
3952 | { | |
3953 | { "(bad)", { XX } }, | |
3954 | { "(bad)", { XX } }, | |
3955 | { VEX_LEN_TABLE (VEX_LEN_EC_P_2) }, | |
3956 | { "(bad)", { XX } }, | |
3957 | }, | |
3958 | ||
3959 | /* PREFIX_VEX_ED */ | |
3960 | { | |
3961 | { "(bad)", { XX } }, | |
3962 | { "(bad)", { XX } }, | |
3963 | { VEX_LEN_TABLE (VEX_LEN_ED_P_2) }, | |
3964 | { "(bad)", { XX } }, | |
3965 | }, | |
3966 | ||
3967 | /* PREFIX_VEX_EE */ | |
3968 | { | |
3969 | { "(bad)", { XX } }, | |
3970 | { "(bad)", { XX } }, | |
3971 | { VEX_LEN_TABLE (VEX_LEN_EE_P_2) }, | |
3972 | { "(bad)", { XX } }, | |
3973 | }, | |
3974 | ||
3975 | /* PREFIX_VEX_EF */ | |
3976 | { | |
3977 | { "(bad)", { XX } }, | |
3978 | { "(bad)", { XX } }, | |
3979 | { VEX_LEN_TABLE (VEX_LEN_EF_P_2) }, | |
3980 | { "(bad)", { XX } }, | |
3981 | }, | |
3982 | ||
3983 | /* PREFIX_VEX_F0 */ | |
3984 | { | |
3985 | { "(bad)", { XX } }, | |
3986 | { "(bad)", { XX } }, | |
3987 | { "(bad)", { XX } }, | |
3988 | { MOD_TABLE (MOD_VEX_F0_PREFIX_3) }, | |
3989 | }, | |
3990 | ||
3991 | /* PREFIX_VEX_F1 */ | |
3992 | { | |
3993 | { "(bad)", { XX } }, | |
3994 | { "(bad)", { XX } }, | |
3995 | { VEX_LEN_TABLE (VEX_LEN_F1_P_2) }, | |
3996 | { "(bad)", { XX } }, | |
3997 | }, | |
3998 | ||
3999 | /* PREFIX_VEX_F2 */ | |
4000 | { | |
4001 | { "(bad)", { XX } }, | |
4002 | { "(bad)", { XX } }, | |
4003 | { VEX_LEN_TABLE (VEX_LEN_F2_P_2) }, | |
4004 | { "(bad)", { XX } }, | |
4005 | }, | |
4006 | ||
4007 | /* PREFIX_VEX_F3 */ | |
4008 | { | |
4009 | { "(bad)", { XX } }, | |
4010 | { "(bad)", { XX } }, | |
4011 | { VEX_LEN_TABLE (VEX_LEN_F3_P_2) }, | |
4012 | { "(bad)", { XX } }, | |
4013 | }, | |
4014 | ||
4015 | /* PREFIX_VEX_F4 */ | |
4016 | { | |
4017 | { "(bad)", { XX } }, | |
4018 | { "(bad)", { XX } }, | |
4019 | { VEX_LEN_TABLE (VEX_LEN_F4_P_2) }, | |
4020 | { "(bad)", { XX } }, | |
4021 | }, | |
4022 | ||
4023 | /* PREFIX_VEX_F5 */ | |
4024 | { | |
4025 | { "(bad)", { XX } }, | |
4026 | { "(bad)", { XX } }, | |
4027 | { VEX_LEN_TABLE (VEX_LEN_F5_P_2) }, | |
4028 | { "(bad)", { XX } }, | |
4029 | }, | |
4030 | ||
4031 | /* PREFIX_VEX_F6 */ | |
4032 | { | |
4033 | { "(bad)", { XX } }, | |
4034 | { "(bad)", { XX } }, | |
4035 | { VEX_LEN_TABLE (VEX_LEN_F6_P_2) }, | |
4036 | { "(bad)", { XX } }, | |
4037 | }, | |
4038 | ||
4039 | /* PREFIX_VEX_F7 */ | |
4040 | { | |
4041 | { "(bad)", { XX } }, | |
4042 | { "(bad)", { XX } }, | |
4043 | { VEX_LEN_TABLE (VEX_LEN_F7_P_2) }, | |
4044 | { "(bad)", { XX } }, | |
4045 | }, | |
4046 | ||
4047 | /* PREFIX_VEX_F8 */ | |
4048 | { | |
4049 | { "(bad)", { XX } }, | |
4050 | { "(bad)", { XX } }, | |
4051 | { VEX_LEN_TABLE (VEX_LEN_F8_P_2) }, | |
4052 | { "(bad)", { XX } }, | |
4053 | }, | |
4054 | ||
4055 | /* PREFIX_VEX_F9 */ | |
4056 | { | |
4057 | { "(bad)", { XX } }, | |
4058 | { "(bad)", { XX } }, | |
4059 | { VEX_LEN_TABLE (VEX_LEN_F9_P_2) }, | |
4060 | { "(bad)", { XX } }, | |
4061 | }, | |
4062 | ||
4063 | /* PREFIX_VEX_FA */ | |
4064 | { | |
4065 | { "(bad)", { XX } }, | |
4066 | { "(bad)", { XX } }, | |
4067 | { VEX_LEN_TABLE (VEX_LEN_FA_P_2) }, | |
4068 | { "(bad)", { XX } }, | |
4069 | }, | |
4070 | ||
4071 | /* PREFIX_VEX_FB */ | |
4072 | { | |
4073 | { "(bad)", { XX } }, | |
4074 | { "(bad)", { XX } }, | |
4075 | { VEX_LEN_TABLE (VEX_LEN_FB_P_2) }, | |
4076 | { "(bad)", { XX } }, | |
4077 | }, | |
4078 | ||
4079 | /* PREFIX_VEX_FC */ | |
4080 | { | |
4081 | { "(bad)", { XX } }, | |
4082 | { "(bad)", { XX } }, | |
4083 | { VEX_LEN_TABLE (VEX_LEN_FC_P_2) }, | |
4084 | { "(bad)", { XX } }, | |
4085 | }, | |
4086 | ||
4087 | /* PREFIX_VEX_FD */ | |
4088 | { | |
4089 | { "(bad)", { XX } }, | |
4090 | { "(bad)", { XX } }, | |
4091 | { VEX_LEN_TABLE (VEX_LEN_FD_P_2) }, | |
4092 | { "(bad)", { XX } }, | |
4093 | }, | |
4094 | ||
4095 | /* PREFIX_VEX_FE */ | |
4096 | { | |
4097 | { "(bad)", { XX } }, | |
4098 | { "(bad)", { XX } }, | |
4099 | { VEX_LEN_TABLE (VEX_LEN_FE_P_2) }, | |
4100 | { "(bad)", { XX } }, | |
4101 | }, | |
4102 | ||
4103 | /* PREFIX_VEX_3800 */ | |
4104 | { | |
4105 | { "(bad)", { XX } }, | |
4106 | { "(bad)", { XX } }, | |
4107 | { VEX_LEN_TABLE (VEX_LEN_3800_P_2) }, | |
4108 | { "(bad)", { XX } }, | |
4109 | }, | |
4110 | ||
4111 | /* PREFIX_VEX_3801 */ | |
4112 | { | |
4113 | { "(bad)", { XX } }, | |
4114 | { "(bad)", { XX } }, | |
4115 | { VEX_LEN_TABLE (VEX_LEN_3801_P_2) }, | |
4116 | { "(bad)", { XX } }, | |
4117 | }, | |
4118 | ||
4119 | /* PREFIX_VEX_3802 */ | |
4120 | { | |
4121 | { "(bad)", { XX } }, | |
4122 | { "(bad)", { XX } }, | |
4123 | { VEX_LEN_TABLE (VEX_LEN_3802_P_2) }, | |
4124 | { "(bad)", { XX } }, | |
4125 | }, | |
4126 | ||
4127 | /* PREFIX_VEX_3803 */ | |
4128 | { | |
4129 | { "(bad)", { XX } }, | |
4130 | { "(bad)", { XX } }, | |
4131 | { VEX_LEN_TABLE (VEX_LEN_3803_P_2) }, | |
4132 | { "(bad)", { XX } }, | |
4133 | }, | |
4134 | ||
4135 | /* PREFIX_VEX_3804 */ | |
4136 | { | |
4137 | { "(bad)", { XX } }, | |
4138 | { "(bad)", { XX } }, | |
4139 | { VEX_LEN_TABLE (VEX_LEN_3804_P_2) }, | |
4140 | { "(bad)", { XX } }, | |
4141 | }, | |
4142 | ||
4143 | /* PREFIX_VEX_3805 */ | |
4144 | { | |
4145 | { "(bad)", { XX } }, | |
4146 | { "(bad)", { XX } }, | |
4147 | { VEX_LEN_TABLE (VEX_LEN_3805_P_2) }, | |
4148 | { "(bad)", { XX } }, | |
4149 | }, | |
4150 | ||
4151 | /* PREFIX_VEX_3806 */ | |
4152 | { | |
4153 | { "(bad)", { XX } }, | |
4154 | { "(bad)", { XX } }, | |
4155 | { VEX_LEN_TABLE (VEX_LEN_3806_P_2) }, | |
4156 | { "(bad)", { XX } }, | |
4157 | }, | |
4158 | ||
4159 | /* PREFIX_VEX_3807 */ | |
4160 | { | |
4161 | { "(bad)", { XX } }, | |
4162 | { "(bad)", { XX } }, | |
4163 | { VEX_LEN_TABLE (VEX_LEN_3807_P_2) }, | |
4164 | { "(bad)", { XX } }, | |
4165 | }, | |
4166 | ||
4167 | /* PREFIX_VEX_3808 */ | |
4168 | { | |
4169 | { "(bad)", { XX } }, | |
4170 | { "(bad)", { XX } }, | |
4171 | { VEX_LEN_TABLE (VEX_LEN_3808_P_2) }, | |
4172 | { "(bad)", { XX } }, | |
4173 | }, | |
4174 | ||
4175 | /* PREFIX_VEX_3809 */ | |
4176 | { | |
4177 | { "(bad)", { XX } }, | |
4178 | { "(bad)", { XX } }, | |
4179 | { VEX_LEN_TABLE (VEX_LEN_3809_P_2) }, | |
4180 | { "(bad)", { XX } }, | |
4181 | }, | |
4182 | ||
4183 | /* PREFIX_VEX_380A */ | |
4184 | { | |
4185 | { "(bad)", { XX } }, | |
4186 | { "(bad)", { XX } }, | |
4187 | { VEX_LEN_TABLE (VEX_LEN_380A_P_2) }, | |
4188 | { "(bad)", { XX } }, | |
4189 | }, | |
4190 | ||
4191 | /* PREFIX_VEX_380B */ | |
4192 | { | |
4193 | { "(bad)", { XX } }, | |
4194 | { "(bad)", { XX } }, | |
4195 | { VEX_LEN_TABLE (VEX_LEN_380B_P_2) }, | |
4196 | { "(bad)", { XX } }, | |
4197 | }, | |
4198 | ||
4199 | /* PREFIX_VEX_380C */ | |
4200 | { | |
4201 | { "(bad)", { XX } }, | |
4202 | { "(bad)", { XX } }, | |
4203 | { "vpermilps", { XM, Vex, EXx } }, | |
4204 | { "(bad)", { XX } }, | |
4205 | }, | |
4206 | ||
4207 | /* PREFIX_VEX_380D */ | |
4208 | { | |
4209 | { "(bad)", { XX } }, | |
4210 | { "(bad)", { XX } }, | |
4211 | { "vpermilpd", { XM, Vex, EXx } }, | |
4212 | { "(bad)", { XX } }, | |
4213 | }, | |
4214 | ||
4215 | /* PREFIX_VEX_380E */ | |
4216 | { | |
4217 | { "(bad)", { XX } }, | |
4218 | { "(bad)", { XX } }, | |
4219 | { "vtestps", { XM, EXx } }, | |
4220 | { "(bad)", { XX } }, | |
4221 | }, | |
4222 | ||
4223 | /* PREFIX_VEX_380F */ | |
4224 | { | |
4225 | { "(bad)", { XX } }, | |
4226 | { "(bad)", { XX } }, | |
4227 | { "vtestpd", { XM, EXx } }, | |
4228 | { "(bad)", { XX } }, | |
4229 | }, | |
4230 | ||
4231 | /* PREFIX_VEX_3817 */ | |
4232 | { | |
4233 | { "(bad)", { XX } }, | |
4234 | { "(bad)", { XX } }, | |
4235 | { "vptest", { XM, EXx } }, | |
4236 | { "(bad)", { XX } }, | |
4237 | }, | |
4238 | ||
4239 | /* PREFIX_VEX_3818 */ | |
4240 | { | |
4241 | { "(bad)", { XX } }, | |
4242 | { "(bad)", { XX } }, | |
4243 | { MOD_TABLE (MOD_VEX_3818_PREFIX_2) }, | |
4244 | { "(bad)", { XX } }, | |
4245 | }, | |
4246 | ||
4247 | /* PREFIX_VEX_3819 */ | |
4248 | { | |
4249 | { "(bad)", { XX } }, | |
4250 | { "(bad)", { XX } }, | |
4251 | { MOD_TABLE (MOD_VEX_3819_PREFIX_2) }, | |
4252 | { "(bad)", { XX } }, | |
4253 | }, | |
4254 | ||
4255 | /* PREFIX_VEX_381A */ | |
4256 | { | |
4257 | { "(bad)", { XX } }, | |
4258 | { "(bad)", { XX } }, | |
4259 | { MOD_TABLE (MOD_VEX_381A_PREFIX_2) }, | |
4260 | { "(bad)", { XX } }, | |
4261 | }, | |
4262 | ||
4263 | /* PREFIX_VEX_381C */ | |
4264 | { | |
4265 | { "(bad)", { XX } }, | |
4266 | { "(bad)", { XX } }, | |
4267 | { VEX_LEN_TABLE (VEX_LEN_381C_P_2) }, | |
4268 | { "(bad)", { XX } }, | |
4269 | }, | |
4270 | ||
4271 | /* PREFIX_VEX_381D */ | |
4272 | { | |
4273 | { "(bad)", { XX } }, | |
4274 | { "(bad)", { XX } }, | |
4275 | { VEX_LEN_TABLE (VEX_LEN_381D_P_2) }, | |
4276 | { "(bad)", { XX } }, | |
4277 | }, | |
4278 | ||
4279 | /* PREFIX_VEX_381E */ | |
4280 | { | |
4281 | { "(bad)", { XX } }, | |
4282 | { "(bad)", { XX } }, | |
4283 | { VEX_LEN_TABLE (VEX_LEN_381E_P_2) }, | |
4284 | { "(bad)", { XX } }, | |
4285 | }, | |
4286 | ||
4287 | /* PREFIX_VEX_3820 */ | |
4288 | { | |
4289 | { "(bad)", { XX } }, | |
4290 | { "(bad)", { XX } }, | |
4291 | { VEX_LEN_TABLE (VEX_LEN_3820_P_2) }, | |
4292 | { "(bad)", { XX } }, | |
4293 | }, | |
4294 | ||
4295 | /* PREFIX_VEX_3821 */ | |
4296 | { | |
4297 | { "(bad)", { XX } }, | |
4298 | { "(bad)", { XX } }, | |
4299 | { VEX_LEN_TABLE (VEX_LEN_3821_P_2) }, | |
4300 | { "(bad)", { XX } }, | |
4301 | }, | |
4302 | ||
4303 | /* PREFIX_VEX_3822 */ | |
4304 | { | |
4305 | { "(bad)", { XX } }, | |
4306 | { "(bad)", { XX } }, | |
4307 | { VEX_LEN_TABLE (VEX_LEN_3822_P_2) }, | |
4308 | { "(bad)", { XX } }, | |
4309 | }, | |
4310 | ||
4311 | /* PREFIX_VEX_3823 */ | |
4312 | { | |
4313 | { "(bad)", { XX } }, | |
4314 | { "(bad)", { XX } }, | |
4315 | { VEX_LEN_TABLE (VEX_LEN_3823_P_2) }, | |
4316 | { "(bad)", { XX } }, | |
4317 | }, | |
4318 | ||
4319 | /* PREFIX_VEX_3824 */ | |
4320 | { | |
4321 | { "(bad)", { XX } }, | |
4322 | { "(bad)", { XX } }, | |
4323 | { VEX_LEN_TABLE (VEX_LEN_3824_P_2) }, | |
4324 | { "(bad)", { XX } }, | |
4325 | }, | |
4326 | ||
4327 | /* PREFIX_VEX_3825 */ | |
4328 | { | |
4329 | { "(bad)", { XX } }, | |
4330 | { "(bad)", { XX } }, | |
4331 | { VEX_LEN_TABLE (VEX_LEN_3825_P_2) }, | |
4332 | { "(bad)", { XX } }, | |
4333 | }, | |
4334 | ||
4335 | /* PREFIX_VEX_3828 */ | |
4336 | { | |
4337 | { "(bad)", { XX } }, | |
4338 | { "(bad)", { XX } }, | |
4339 | { VEX_LEN_TABLE (VEX_LEN_3828_P_2) }, | |
4340 | { "(bad)", { XX } }, | |
4341 | }, | |
4342 | ||
4343 | /* PREFIX_VEX_3829 */ | |
4344 | { | |
4345 | { "(bad)", { XX } }, | |
4346 | { "(bad)", { XX } }, | |
4347 | { VEX_LEN_TABLE (VEX_LEN_3829_P_2) }, | |
4348 | { "(bad)", { XX } }, | |
4349 | }, | |
4350 | ||
4351 | /* PREFIX_VEX_382A */ | |
4352 | { | |
4353 | { "(bad)", { XX } }, | |
4354 | { "(bad)", { XX } }, | |
4355 | { MOD_TABLE (MOD_VEX_382A_PREFIX_2) }, | |
4356 | { "(bad)", { XX } }, | |
4357 | }, | |
4358 | ||
4359 | /* PREFIX_VEX_382B */ | |
4360 | { | |
4361 | { "(bad)", { XX } }, | |
4362 | { "(bad)", { XX } }, | |
4363 | { VEX_LEN_TABLE (VEX_LEN_382B_P_2) }, | |
4364 | { "(bad)", { XX } }, | |
4365 | }, | |
4366 | ||
4367 | /* PREFIX_VEX_382C */ | |
4368 | { | |
4369 | { "(bad)", { XX } }, | |
4370 | { "(bad)", { XX } }, | |
4371 | { MOD_TABLE (MOD_VEX_382C_PREFIX_2) }, | |
4372 | { "(bad)", { XX } }, | |
4373 | }, | |
4374 | ||
4375 | /* PREFIX_VEX_382D */ | |
4376 | { | |
4377 | { "(bad)", { XX } }, | |
4378 | { "(bad)", { XX } }, | |
4379 | { MOD_TABLE (MOD_VEX_382D_PREFIX_2) }, | |
4380 | { "(bad)", { XX } }, | |
4381 | }, | |
4382 | ||
4383 | /* PREFIX_VEX_382E */ | |
4384 | { | |
4385 | { "(bad)", { XX } }, | |
4386 | { "(bad)", { XX } }, | |
4387 | { MOD_TABLE (MOD_VEX_382E_PREFIX_2) }, | |
4388 | { "(bad)", { XX } }, | |
4389 | }, | |
4390 | ||
4391 | /* PREFIX_VEX_382F */ | |
4392 | { | |
4393 | { "(bad)", { XX } }, | |
4394 | { "(bad)", { XX } }, | |
4395 | { MOD_TABLE (MOD_VEX_382F_PREFIX_2) }, | |
4396 | { "(bad)", { XX } }, | |
4397 | }, | |
4398 | ||
4399 | /* PREFIX_VEX_3830 */ | |
4400 | { | |
4401 | { "(bad)", { XX } }, | |
4402 | { "(bad)", { XX } }, | |
4403 | { VEX_LEN_TABLE (VEX_LEN_3830_P_2) }, | |
4404 | { "(bad)", { XX } }, | |
4405 | }, | |
4406 | ||
4407 | /* PREFIX_VEX_3831 */ | |
4408 | { | |
4409 | { "(bad)", { XX } }, | |
4410 | { "(bad)", { XX } }, | |
4411 | { VEX_LEN_TABLE (VEX_LEN_3831_P_2) }, | |
4412 | { "(bad)", { XX } }, | |
4413 | }, | |
4414 | ||
4415 | /* PREFIX_VEX_3832 */ | |
4416 | { | |
4417 | { "(bad)", { XX } }, | |
4418 | { "(bad)", { XX } }, | |
4419 | { VEX_LEN_TABLE (VEX_LEN_3832_P_2) }, | |
4420 | { "(bad)", { XX } }, | |
4421 | }, | |
4422 | ||
4423 | /* PREFIX_VEX_3833 */ | |
4424 | { | |
4425 | { "(bad)", { XX } }, | |
4426 | { "(bad)", { XX } }, | |
4427 | { VEX_LEN_TABLE (VEX_LEN_3833_P_2) }, | |
4428 | { "(bad)", { XX } }, | |
4429 | }, | |
4430 | ||
4431 | /* PREFIX_VEX_3834 */ | |
4432 | { | |
4433 | { "(bad)", { XX } }, | |
4434 | { "(bad)", { XX } }, | |
4435 | { VEX_LEN_TABLE (VEX_LEN_3834_P_2) }, | |
4436 | { "(bad)", { XX } }, | |
4437 | }, | |
4438 | ||
4439 | /* PREFIX_VEX_3835 */ | |
4440 | { | |
4441 | { "(bad)", { XX } }, | |
4442 | { "(bad)", { XX } }, | |
4443 | { VEX_LEN_TABLE (VEX_LEN_3835_P_2) }, | |
4444 | { "(bad)", { XX } }, | |
4445 | }, | |
4446 | ||
4447 | /* PREFIX_VEX_3837 */ | |
4448 | { | |
4449 | { "(bad)", { XX } }, | |
4450 | { "(bad)", { XX } }, | |
4451 | { VEX_LEN_TABLE (VEX_LEN_3837_P_2) }, | |
4452 | { "(bad)", { XX } }, | |
4453 | }, | |
4454 | ||
4455 | /* PREFIX_VEX_3838 */ | |
4456 | { | |
4457 | { "(bad)", { XX } }, | |
4458 | { "(bad)", { XX } }, | |
4459 | { VEX_LEN_TABLE (VEX_LEN_3838_P_2) }, | |
4460 | { "(bad)", { XX } }, | |
4461 | }, | |
4462 | ||
4463 | /* PREFIX_VEX_3839 */ | |
4464 | { | |
4465 | { "(bad)", { XX } }, | |
4466 | { "(bad)", { XX } }, | |
4467 | { VEX_LEN_TABLE (VEX_LEN_3839_P_2) }, | |
4468 | { "(bad)", { XX } }, | |
4469 | }, | |
4470 | ||
4471 | /* PREFIX_VEX_383A */ | |
4472 | { | |
4473 | { "(bad)", { XX } }, | |
4474 | { "(bad)", { XX } }, | |
4475 | { VEX_LEN_TABLE (VEX_LEN_383A_P_2) }, | |
4476 | { "(bad)", { XX } }, | |
4477 | }, | |
4478 | ||
4479 | /* PREFIX_VEX_383B */ | |
4480 | { | |
4481 | { "(bad)", { XX } }, | |
4482 | { "(bad)", { XX } }, | |
4483 | { VEX_LEN_TABLE (VEX_LEN_383B_P_2) }, | |
4484 | { "(bad)", { XX } }, | |
4485 | }, | |
4486 | ||
4487 | /* PREFIX_VEX_383C */ | |
4488 | { | |
4489 | { "(bad)", { XX } }, | |
4490 | { "(bad)", { XX } }, | |
4491 | { VEX_LEN_TABLE (VEX_LEN_383C_P_2) }, | |
4492 | { "(bad)", { XX } }, | |
4493 | }, | |
4494 | ||
4495 | /* PREFIX_VEX_383D */ | |
4496 | { | |
4497 | { "(bad)", { XX } }, | |
4498 | { "(bad)", { XX } }, | |
4499 | { VEX_LEN_TABLE (VEX_LEN_383D_P_2) }, | |
4500 | { "(bad)", { XX } }, | |
4501 | }, | |
4502 | ||
4503 | /* PREFIX_VEX_383E */ | |
4504 | { | |
4505 | { "(bad)", { XX } }, | |
4506 | { "(bad)", { XX } }, | |
4507 | { VEX_LEN_TABLE (VEX_LEN_383E_P_2) }, | |
4508 | { "(bad)", { XX } }, | |
4509 | }, | |
4510 | ||
4511 | /* PREFIX_VEX_383F */ | |
4512 | { | |
4513 | { "(bad)", { XX } }, | |
4514 | { "(bad)", { XX } }, | |
4515 | { VEX_LEN_TABLE (VEX_LEN_383F_P_2) }, | |
4516 | { "(bad)", { XX } }, | |
4517 | }, | |
4518 | ||
4519 | /* PREFIX_VEX_3840 */ | |
4520 | { | |
4521 | { "(bad)", { XX } }, | |
4522 | { "(bad)", { XX } }, | |
4523 | { VEX_LEN_TABLE (VEX_LEN_3840_P_2) }, | |
4524 | { "(bad)", { XX } }, | |
4525 | }, | |
4526 | ||
4527 | /* PREFIX_VEX_3841 */ | |
4528 | { | |
4529 | { "(bad)", { XX } }, | |
4530 | { "(bad)", { XX } }, | |
4531 | { VEX_LEN_TABLE (VEX_LEN_3841_P_2) }, | |
4532 | { "(bad)", { XX } }, | |
4533 | }, | |
4534 | ||
0bfee649 | 4535 | /* PREFIX_VEX_3896 */ |
a5ff0eb2 L |
4536 | { |
4537 | { "(bad)", { XX } }, | |
4538 | { "(bad)", { XX } }, | |
0bfee649 | 4539 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4540 | { "(bad)", { XX } }, |
4541 | }, | |
4542 | ||
0bfee649 | 4543 | /* PREFIX_VEX_3897 */ |
a5ff0eb2 L |
4544 | { |
4545 | { "(bad)", { XX } }, | |
4546 | { "(bad)", { XX } }, | |
0bfee649 | 4547 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4548 | { "(bad)", { XX } }, |
4549 | }, | |
4550 | ||
0bfee649 | 4551 | /* PREFIX_VEX_3898 */ |
a5ff0eb2 L |
4552 | { |
4553 | { "(bad)", { XX } }, | |
4554 | { "(bad)", { XX } }, | |
0bfee649 | 4555 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4556 | { "(bad)", { XX } }, |
4557 | }, | |
4558 | ||
0bfee649 | 4559 | /* PREFIX_VEX_3899 */ |
a5ff0eb2 L |
4560 | { |
4561 | { "(bad)", { XX } }, | |
4562 | { "(bad)", { XX } }, | |
0bfee649 | 4563 | { "vfmadd132s%XW", { XM, Vex, EXVexWdq } }, |
a5ff0eb2 L |
4564 | { "(bad)", { XX } }, |
4565 | }, | |
4566 | ||
0bfee649 | 4567 | /* PREFIX_VEX_389A */ |
a5ff0eb2 L |
4568 | { |
4569 | { "(bad)", { XX } }, | |
4570 | { "(bad)", { XX } }, | |
0bfee649 | 4571 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4572 | { "(bad)", { XX } }, |
4573 | }, | |
4574 | ||
0bfee649 | 4575 | /* PREFIX_VEX_389B */ |
c0f3af97 L |
4576 | { |
4577 | { "(bad)", { XX } }, | |
4578 | { "(bad)", { XX } }, | |
0bfee649 | 4579 | { "vfmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4580 | { "(bad)", { XX } }, |
4581 | }, | |
4582 | ||
0bfee649 | 4583 | /* PREFIX_VEX_389C */ |
c0f3af97 L |
4584 | { |
4585 | { "(bad)", { XX } }, | |
4586 | { "(bad)", { XX } }, | |
0bfee649 | 4587 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4588 | { "(bad)", { XX } }, |
4589 | }, | |
4590 | ||
0bfee649 | 4591 | /* PREFIX_VEX_389D */ |
c0f3af97 L |
4592 | { |
4593 | { "(bad)", { XX } }, | |
4594 | { "(bad)", { XX } }, | |
0bfee649 | 4595 | { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4596 | { "(bad)", { XX } }, |
4597 | }, | |
4598 | ||
0bfee649 | 4599 | /* PREFIX_VEX_389E */ |
c0f3af97 L |
4600 | { |
4601 | { "(bad)", { XX } }, | |
4602 | { "(bad)", { XX } }, | |
0bfee649 | 4603 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4604 | { "(bad)", { XX } }, |
4605 | }, | |
4606 | ||
0bfee649 | 4607 | /* PREFIX_VEX_389F */ |
c0f3af97 L |
4608 | { |
4609 | { "(bad)", { XX } }, | |
4610 | { "(bad)", { XX } }, | |
0bfee649 | 4611 | { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4612 | { "(bad)", { XX } }, |
4613 | }, | |
4614 | ||
0bfee649 | 4615 | /* PREFIX_VEX_38A6 */ |
c0f3af97 L |
4616 | { |
4617 | { "(bad)", { XX } }, | |
4618 | { "(bad)", { XX } }, | |
0bfee649 | 4619 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4620 | { "(bad)", { XX } }, |
4621 | }, | |
4622 | ||
0bfee649 | 4623 | /* PREFIX_VEX_38A7 */ |
c0f3af97 L |
4624 | { |
4625 | { "(bad)", { XX } }, | |
4626 | { "(bad)", { XX } }, | |
0bfee649 | 4627 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4628 | { "(bad)", { XX } }, |
4629 | }, | |
4630 | ||
0bfee649 | 4631 | /* PREFIX_VEX_38A8 */ |
c0f3af97 L |
4632 | { |
4633 | { "(bad)", { XX } }, | |
4634 | { "(bad)", { XX } }, | |
0bfee649 | 4635 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4636 | { "(bad)", { XX } }, |
4637 | }, | |
4638 | ||
0bfee649 | 4639 | /* PREFIX_VEX_38A9 */ |
c0f3af97 L |
4640 | { |
4641 | { "(bad)", { XX } }, | |
4642 | { "(bad)", { XX } }, | |
0bfee649 | 4643 | { "vfmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4644 | { "(bad)", { XX } }, |
4645 | }, | |
4646 | ||
0bfee649 | 4647 | /* PREFIX_VEX_38AA */ |
c0f3af97 L |
4648 | { |
4649 | { "(bad)", { XX } }, | |
4650 | { "(bad)", { XX } }, | |
0bfee649 | 4651 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4652 | { "(bad)", { XX } }, |
4653 | }, | |
4654 | ||
0bfee649 | 4655 | /* PREFIX_VEX_38AB */ |
c0f3af97 L |
4656 | { |
4657 | { "(bad)", { XX } }, | |
4658 | { "(bad)", { XX } }, | |
0bfee649 | 4659 | { "vfmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4660 | { "(bad)", { XX } }, |
4661 | }, | |
4662 | ||
0bfee649 | 4663 | /* PREFIX_VEX_38AC */ |
c0f3af97 L |
4664 | { |
4665 | { "(bad)", { XX } }, | |
4666 | { "(bad)", { XX } }, | |
0bfee649 | 4667 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4668 | { "(bad)", { XX } }, |
4669 | }, | |
4670 | ||
0bfee649 | 4671 | /* PREFIX_VEX_38AD */ |
c0f3af97 L |
4672 | { |
4673 | { "(bad)", { XX } }, | |
4674 | { "(bad)", { XX } }, | |
0bfee649 | 4675 | { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4676 | { "(bad)", { XX } }, |
4677 | }, | |
4678 | ||
0bfee649 | 4679 | /* PREFIX_VEX_38AE */ |
c0f3af97 L |
4680 | { |
4681 | { "(bad)", { XX } }, | |
4682 | { "(bad)", { XX } }, | |
0bfee649 | 4683 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4684 | { "(bad)", { XX } }, |
4685 | }, | |
4686 | ||
0bfee649 | 4687 | /* PREFIX_VEX_38AF */ |
c0f3af97 L |
4688 | { |
4689 | { "(bad)", { XX } }, | |
4690 | { "(bad)", { XX } }, | |
0bfee649 | 4691 | { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4692 | { "(bad)", { XX } }, |
4693 | }, | |
4694 | ||
0bfee649 | 4695 | /* PREFIX_VEX_38B6 */ |
c0f3af97 L |
4696 | { |
4697 | { "(bad)", { XX } }, | |
4698 | { "(bad)", { XX } }, | |
0bfee649 | 4699 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4700 | { "(bad)", { XX } }, |
4701 | }, | |
4702 | ||
0bfee649 | 4703 | /* PREFIX_VEX_38B7 */ |
c0f3af97 L |
4704 | { |
4705 | { "(bad)", { XX } }, | |
4706 | { "(bad)", { XX } }, | |
0bfee649 | 4707 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4708 | { "(bad)", { XX } }, |
4709 | }, | |
4710 | ||
0bfee649 | 4711 | /* PREFIX_VEX_38B8 */ |
c0f3af97 L |
4712 | { |
4713 | { "(bad)", { XX } }, | |
4714 | { "(bad)", { XX } }, | |
0bfee649 | 4715 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4716 | { "(bad)", { XX } }, |
4717 | }, | |
4718 | ||
0bfee649 | 4719 | /* PREFIX_VEX_38B9 */ |
c0f3af97 L |
4720 | { |
4721 | { "(bad)", { XX } }, | |
4722 | { "(bad)", { XX } }, | |
0bfee649 | 4723 | { "vfmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4724 | { "(bad)", { XX } }, |
4725 | }, | |
4726 | ||
0bfee649 | 4727 | /* PREFIX_VEX_38BA */ |
c0f3af97 L |
4728 | { |
4729 | { "(bad)", { XX } }, | |
4730 | { "(bad)", { XX } }, | |
0bfee649 | 4731 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4732 | { "(bad)", { XX } }, |
4733 | }, | |
4734 | ||
0bfee649 | 4735 | /* PREFIX_VEX_38BB */ |
c0f3af97 L |
4736 | { |
4737 | { "(bad)", { XX } }, | |
4738 | { "(bad)", { XX } }, | |
0bfee649 | 4739 | { "vfmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4740 | { "(bad)", { XX } }, |
4741 | }, | |
4742 | ||
0bfee649 | 4743 | /* PREFIX_VEX_38BC */ |
c0f3af97 L |
4744 | { |
4745 | { "(bad)", { XX } }, | |
4746 | { "(bad)", { XX } }, | |
0bfee649 | 4747 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4748 | { "(bad)", { XX } }, |
4749 | }, | |
4750 | ||
0bfee649 | 4751 | /* PREFIX_VEX_38BD */ |
c0f3af97 L |
4752 | { |
4753 | { "(bad)", { XX } }, | |
4754 | { "(bad)", { XX } }, | |
0bfee649 | 4755 | { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4756 | { "(bad)", { XX } }, |
4757 | }, | |
4758 | ||
0bfee649 | 4759 | /* PREFIX_VEX_38BE */ |
c0f3af97 L |
4760 | { |
4761 | { "(bad)", { XX } }, | |
4762 | { "(bad)", { XX } }, | |
0bfee649 | 4763 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4764 | { "(bad)", { XX } }, |
4765 | }, | |
4766 | ||
0bfee649 | 4767 | /* PREFIX_VEX_38BF */ |
c0f3af97 L |
4768 | { |
4769 | { "(bad)", { XX } }, | |
4770 | { "(bad)", { XX } }, | |
0bfee649 | 4771 | { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4772 | { "(bad)", { XX } }, |
4773 | }, | |
4774 | ||
0bfee649 | 4775 | /* PREFIX_VEX_38DB */ |
c0f3af97 L |
4776 | { |
4777 | { "(bad)", { XX } }, | |
4778 | { "(bad)", { XX } }, | |
0bfee649 | 4779 | { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, |
c0f3af97 L |
4780 | { "(bad)", { XX } }, |
4781 | }, | |
4782 | ||
0bfee649 | 4783 | /* PREFIX_VEX_38DC */ |
c0f3af97 L |
4784 | { |
4785 | { "(bad)", { XX } }, | |
4786 | { "(bad)", { XX } }, | |
0bfee649 | 4787 | { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, |
c0f3af97 L |
4788 | { "(bad)", { XX } }, |
4789 | }, | |
4790 | ||
0bfee649 | 4791 | /* PREFIX_VEX_38DD */ |
c0f3af97 L |
4792 | { |
4793 | { "(bad)", { XX } }, | |
4794 | { "(bad)", { XX } }, | |
0bfee649 | 4795 | { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, |
c0f3af97 L |
4796 | { "(bad)", { XX } }, |
4797 | }, | |
4798 | ||
0bfee649 | 4799 | /* PREFIX_VEX_38DE */ |
c0f3af97 L |
4800 | { |
4801 | { "(bad)", { XX } }, | |
4802 | { "(bad)", { XX } }, | |
0bfee649 | 4803 | { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, |
c0f3af97 L |
4804 | { "(bad)", { XX } }, |
4805 | }, | |
4806 | ||
0bfee649 | 4807 | /* PREFIX_VEX_38DF */ |
c0f3af97 L |
4808 | { |
4809 | { "(bad)", { XX } }, | |
4810 | { "(bad)", { XX } }, | |
0bfee649 | 4811 | { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, |
c0f3af97 L |
4812 | { "(bad)", { XX } }, |
4813 | }, | |
4814 | ||
0bfee649 | 4815 | /* PREFIX_VEX_3A04 */ |
c0f3af97 L |
4816 | { |
4817 | { "(bad)", { XX } }, | |
4818 | { "(bad)", { XX } }, | |
0bfee649 | 4819 | { "vpermilps", { XM, EXx, Ib } }, |
c0f3af97 L |
4820 | { "(bad)", { XX } }, |
4821 | }, | |
4822 | ||
0bfee649 | 4823 | /* PREFIX_VEX_3A05 */ |
c0f3af97 L |
4824 | { |
4825 | { "(bad)", { XX } }, | |
4826 | { "(bad)", { XX } }, | |
0bfee649 | 4827 | { "vpermilpd", { XM, EXx, Ib } }, |
c0f3af97 L |
4828 | { "(bad)", { XX } }, |
4829 | }, | |
4830 | ||
0bfee649 | 4831 | /* PREFIX_VEX_3A06 */ |
c0f3af97 L |
4832 | { |
4833 | { "(bad)", { XX } }, | |
4834 | { "(bad)", { XX } }, | |
0bfee649 | 4835 | { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, |
c0f3af97 L |
4836 | { "(bad)", { XX } }, |
4837 | }, | |
4838 | ||
0bfee649 | 4839 | /* PREFIX_VEX_3A08 */ |
c0f3af97 L |
4840 | { |
4841 | { "(bad)", { XX } }, | |
4842 | { "(bad)", { XX } }, | |
0bfee649 | 4843 | { "vroundps", { XM, EXx, Ib } }, |
c0f3af97 L |
4844 | { "(bad)", { XX } }, |
4845 | }, | |
4846 | ||
0bfee649 | 4847 | /* PREFIX_VEX_3A09 */ |
c0f3af97 L |
4848 | { |
4849 | { "(bad)", { XX } }, | |
4850 | { "(bad)", { XX } }, | |
0bfee649 | 4851 | { "vroundpd", { XM, EXx, Ib } }, |
c0f3af97 L |
4852 | { "(bad)", { XX } }, |
4853 | }, | |
4854 | ||
0bfee649 | 4855 | /* PREFIX_VEX_3A0A */ |
c0f3af97 L |
4856 | { |
4857 | { "(bad)", { XX } }, | |
4858 | { "(bad)", { XX } }, | |
0bfee649 L |
4859 | { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, |
4860 | { "(bad)", { XX } }, | |
4861 | }, | |
4862 | ||
4863 | /* PREFIX_VEX_3A0B */ | |
4864 | { | |
4865 | { "(bad)", { XX } }, | |
4866 | { "(bad)", { XX } }, | |
4867 | { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, | |
4868 | { "(bad)", { XX } }, | |
4869 | }, | |
4870 | ||
4871 | /* PREFIX_VEX_3A0C */ | |
4872 | { | |
4873 | { "(bad)", { XX } }, | |
4874 | { "(bad)", { XX } }, | |
4875 | { "vblendps", { XM, Vex, EXx, Ib } }, | |
4876 | { "(bad)", { XX } }, | |
4877 | }, | |
4878 | ||
4879 | /* PREFIX_VEX_3A0D */ | |
4880 | { | |
4881 | { "(bad)", { XX } }, | |
4882 | { "(bad)", { XX } }, | |
4883 | { "vblendpd", { XM, Vex, EXx, Ib } }, | |
c0f3af97 L |
4884 | { "(bad)", { XX } }, |
4885 | }, | |
4886 | ||
0bfee649 L |
4887 | /* PREFIX_VEX_3A0E */ |
4888 | { | |
4889 | { "(bad)", { XX } }, | |
4890 | { "(bad)", { XX } }, | |
4891 | { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, | |
4892 | { "(bad)", { XX } }, | |
4893 | }, | |
4894 | ||
4895 | /* PREFIX_VEX_3A0F */ | |
4896 | { | |
4897 | { "(bad)", { XX } }, | |
4898 | { "(bad)", { XX } }, | |
4899 | { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, | |
4900 | { "(bad)", { XX } }, | |
4901 | }, | |
4902 | ||
4903 | /* PREFIX_VEX_3A14 */ | |
4904 | { | |
4905 | { "(bad)", { XX } }, | |
4906 | { "(bad)", { XX } }, | |
4907 | { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, | |
4908 | { "(bad)", { XX } }, | |
4909 | }, | |
4910 | ||
4911 | /* PREFIX_VEX_3A15 */ | |
4912 | { | |
4913 | { "(bad)", { XX } }, | |
4914 | { "(bad)", { XX } }, | |
4915 | { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, | |
4916 | { "(bad)", { XX } }, | |
4917 | }, | |
4918 | ||
4919 | /* PREFIX_VEX_3A16 */ | |
c0f3af97 L |
4920 | { |
4921 | { "(bad)", { XX } }, | |
4922 | { "(bad)", { XX } }, | |
0bfee649 | 4923 | { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, |
c0f3af97 L |
4924 | { "(bad)", { XX } }, |
4925 | }, | |
4926 | ||
0bfee649 | 4927 | /* PREFIX_VEX_3A17 */ |
c0f3af97 L |
4928 | { |
4929 | { "(bad)", { XX } }, | |
4930 | { "(bad)", { XX } }, | |
0bfee649 | 4931 | { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, |
c0f3af97 L |
4932 | { "(bad)", { XX } }, |
4933 | }, | |
4934 | ||
0bfee649 | 4935 | /* PREFIX_VEX_3A18 */ |
c0f3af97 L |
4936 | { |
4937 | { "(bad)", { XX } }, | |
4938 | { "(bad)", { XX } }, | |
0bfee649 | 4939 | { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, |
c0f3af97 L |
4940 | { "(bad)", { XX } }, |
4941 | }, | |
4942 | ||
0bfee649 | 4943 | /* PREFIX_VEX_3A19 */ |
c0f3af97 L |
4944 | { |
4945 | { "(bad)", { XX } }, | |
4946 | { "(bad)", { XX } }, | |
0bfee649 | 4947 | { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, |
c0f3af97 L |
4948 | { "(bad)", { XX } }, |
4949 | }, | |
4950 | ||
0bfee649 | 4951 | /* PREFIX_VEX_3A20 */ |
c0f3af97 L |
4952 | { |
4953 | { "(bad)", { XX } }, | |
4954 | { "(bad)", { XX } }, | |
0bfee649 | 4955 | { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, |
c0f3af97 L |
4956 | { "(bad)", { XX } }, |
4957 | }, | |
4958 | ||
0bfee649 | 4959 | /* PREFIX_VEX_3A21 */ |
c0f3af97 L |
4960 | { |
4961 | { "(bad)", { XX } }, | |
4962 | { "(bad)", { XX } }, | |
0bfee649 | 4963 | { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, |
c0f3af97 L |
4964 | { "(bad)", { XX } }, |
4965 | }, | |
4966 | ||
0bfee649 L |
4967 | /* PREFIX_VEX_3A22 */ |
4968 | { | |
4969 | { "(bad)", { XX } }, | |
4970 | { "(bad)", { XX } }, | |
4971 | { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, | |
4972 | { "(bad)", { XX } }, | |
4973 | }, | |
4974 | ||
4975 | /* PREFIX_VEX_3A40 */ | |
c0f3af97 L |
4976 | { |
4977 | { "(bad)", { XX } }, | |
4978 | { "(bad)", { XX } }, | |
0bfee649 | 4979 | { "vdpps", { XM, Vex, EXx, Ib } }, |
c0f3af97 L |
4980 | { "(bad)", { XX } }, |
4981 | }, | |
4982 | ||
0bfee649 | 4983 | /* PREFIX_VEX_3A41 */ |
c0f3af97 L |
4984 | { |
4985 | { "(bad)", { XX } }, | |
4986 | { "(bad)", { XX } }, | |
0bfee649 | 4987 | { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, |
c0f3af97 L |
4988 | { "(bad)", { XX } }, |
4989 | }, | |
4990 | ||
0bfee649 | 4991 | /* PREFIX_VEX_3A42 */ |
c0f3af97 L |
4992 | { |
4993 | { "(bad)", { XX } }, | |
4994 | { "(bad)", { XX } }, | |
0bfee649 | 4995 | { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, |
c0f3af97 L |
4996 | { "(bad)", { XX } }, |
4997 | }, | |
4998 | ||
ce2f5b3c L |
4999 | /* PREFIX_VEX_3A44 */ |
5000 | { | |
5001 | { "(bad)", { XX } }, | |
5002 | { "(bad)", { XX } }, | |
5003 | { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) }, | |
5004 | { "(bad)", { XX } }, | |
5005 | }, | |
5006 | ||
0bfee649 | 5007 | /* PREFIX_VEX_3A4A */ |
c0f3af97 L |
5008 | { |
5009 | { "(bad)", { XX } }, | |
5010 | { "(bad)", { XX } }, | |
0bfee649 | 5011 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
c0f3af97 L |
5012 | { "(bad)", { XX } }, |
5013 | }, | |
5014 | ||
0bfee649 | 5015 | /* PREFIX_VEX_3A4B */ |
c0f3af97 L |
5016 | { |
5017 | { "(bad)", { XX } }, | |
5018 | { "(bad)", { XX } }, | |
0bfee649 | 5019 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
c0f3af97 L |
5020 | { "(bad)", { XX } }, |
5021 | }, | |
5022 | ||
0bfee649 | 5023 | /* PREFIX_VEX_3A4C */ |
c0f3af97 L |
5024 | { |
5025 | { "(bad)", { XX } }, | |
5026 | { "(bad)", { XX } }, | |
0bfee649 | 5027 | { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, |
c0f3af97 L |
5028 | { "(bad)", { XX } }, |
5029 | }, | |
5030 | ||
0bfee649 | 5031 | /* PREFIX_VEX_3A60 */ |
c0f3af97 L |
5032 | { |
5033 | { "(bad)", { XX } }, | |
5034 | { "(bad)", { XX } }, | |
0bfee649 | 5035 | { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, |
c0f3af97 L |
5036 | { "(bad)", { XX } }, |
5037 | }, | |
5038 | ||
0bfee649 | 5039 | /* PREFIX_VEX_3A61 */ |
c0f3af97 L |
5040 | { |
5041 | { "(bad)", { XX } }, | |
5042 | { "(bad)", { XX } }, | |
0bfee649 | 5043 | { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, |
c0f3af97 L |
5044 | { "(bad)", { XX } }, |
5045 | }, | |
5046 | ||
0bfee649 | 5047 | /* PREFIX_VEX_3A62 */ |
c0f3af97 L |
5048 | { |
5049 | { "(bad)", { XX } }, | |
5050 | { "(bad)", { XX } }, | |
0bfee649 | 5051 | { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, |
c0f3af97 L |
5052 | { "(bad)", { XX } }, |
5053 | }, | |
5054 | ||
0bfee649 | 5055 | /* PREFIX_VEX_3A63 */ |
c0f3af97 L |
5056 | { |
5057 | { "(bad)", { XX } }, | |
5058 | { "(bad)", { XX } }, | |
0bfee649 | 5059 | { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, |
c0f3af97 L |
5060 | { "(bad)", { XX } }, |
5061 | }, | |
a5ff0eb2 L |
5062 | |
5063 | /* PREFIX_VEX_3ADF */ | |
5064 | { | |
5065 | { "(bad)", { XX } }, | |
5066 | { "(bad)", { XX } }, | |
5067 | { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) }, | |
5068 | { "(bad)", { XX } }, | |
5069 | }, | |
c0f3af97 L |
5070 | }; |
5071 | ||
5072 | static const struct dis386 x86_64_table[][2] = { | |
5073 | /* X86_64_06 */ | |
5074 | { | |
5075 | { "push{T|}", { es } }, | |
5076 | { "(bad)", { XX } }, | |
5077 | }, | |
5078 | ||
5079 | /* X86_64_07 */ | |
5080 | { | |
5081 | { "pop{T|}", { es } }, | |
5082 | { "(bad)", { XX } }, | |
5083 | }, | |
5084 | ||
5085 | /* X86_64_0D */ | |
5086 | { | |
5087 | { "push{T|}", { cs } }, | |
5088 | { "(bad)", { XX } }, | |
5089 | }, | |
5090 | ||
5091 | /* X86_64_16 */ | |
5092 | { | |
5093 | { "push{T|}", { ss } }, | |
5094 | { "(bad)", { XX } }, | |
5095 | }, | |
5096 | ||
5097 | /* X86_64_17 */ | |
5098 | { | |
5099 | { "pop{T|}", { ss } }, | |
5100 | { "(bad)", { XX } }, | |
5101 | }, | |
5102 | ||
5103 | /* X86_64_1E */ | |
5104 | { | |
5105 | { "push{T|}", { ds } }, | |
5106 | { "(bad)", { XX } }, | |
5107 | }, | |
5108 | ||
5109 | /* X86_64_1F */ | |
5110 | { | |
5111 | { "pop{T|}", { ds } }, | |
5112 | { "(bad)", { XX } }, | |
5113 | }, | |
5114 | ||
5115 | /* X86_64_27 */ | |
5116 | { | |
5117 | { "daa", { XX } }, | |
5118 | { "(bad)", { XX } }, | |
5119 | }, | |
5120 | ||
5121 | /* X86_64_2F */ | |
5122 | { | |
5123 | { "das", { XX } }, | |
5124 | { "(bad)", { XX } }, | |
5125 | }, | |
5126 | ||
5127 | /* X86_64_37 */ | |
5128 | { | |
5129 | { "aaa", { XX } }, | |
5130 | { "(bad)", { XX } }, | |
5131 | }, | |
5132 | ||
5133 | /* X86_64_3F */ | |
5134 | { | |
5135 | { "aas", { XX } }, | |
5136 | { "(bad)", { XX } }, | |
5137 | }, | |
5138 | ||
5139 | /* X86_64_60 */ | |
5140 | { | |
5141 | { "pusha{P|}", { XX } }, | |
5142 | { "(bad)", { XX } }, | |
5143 | }, | |
5144 | ||
5145 | /* X86_64_61 */ | |
5146 | { | |
5147 | { "popa{P|}", { XX } }, | |
5148 | { "(bad)", { XX } }, | |
5149 | }, | |
5150 | ||
5151 | /* X86_64_62 */ | |
5152 | { | |
5153 | { MOD_TABLE (MOD_62_32BIT) }, | |
5154 | { "(bad)", { XX } }, | |
5155 | }, | |
5156 | ||
5157 | /* X86_64_63 */ | |
5158 | { | |
5159 | { "arpl", { Ew, Gw } }, | |
5160 | { "movs{lq|xd}", { Gv, Ed } }, | |
5161 | }, | |
5162 | ||
5163 | /* X86_64_6D */ | |
5164 | { | |
5165 | { "ins{R|}", { Yzr, indirDX } }, | |
5166 | { "ins{G|}", { Yzr, indirDX } }, | |
5167 | }, | |
5168 | ||
5169 | /* X86_64_6F */ | |
5170 | { | |
5171 | { "outs{R|}", { indirDXr, Xz } }, | |
5172 | { "outs{G|}", { indirDXr, Xz } }, | |
5173 | }, | |
5174 | ||
5175 | /* X86_64_9A */ | |
5176 | { | |
5177 | { "Jcall{T|}", { Ap } }, | |
5178 | { "(bad)", { XX } }, | |
5179 | }, | |
5180 | ||
5181 | /* X86_64_C4 */ | |
5182 | { | |
5183 | { MOD_TABLE (MOD_C4_32BIT) }, | |
5184 | { VEX_C4_TABLE (VEX_0F) }, | |
5185 | }, | |
5186 | ||
5187 | /* X86_64_C5 */ | |
5188 | { | |
5189 | { MOD_TABLE (MOD_C5_32BIT) }, | |
5190 | { VEX_C5_TABLE (VEX_0F) }, | |
5191 | }, | |
5192 | ||
5193 | /* X86_64_CE */ | |
5194 | { | |
5195 | { "into", { XX } }, | |
5196 | { "(bad)", { XX } }, | |
5197 | }, | |
5198 | ||
5199 | /* X86_64_D4 */ | |
5200 | { | |
5201 | { "aam", { sIb } }, | |
5202 | { "(bad)", { XX } }, | |
5203 | }, | |
5204 | ||
5205 | /* X86_64_D5 */ | |
5206 | { | |
5207 | { "aad", { sIb } }, | |
5208 | { "(bad)", { XX } }, | |
5209 | }, | |
5210 | ||
5211 | /* X86_64_EA */ | |
5212 | { | |
5213 | { "Jjmp{T|}", { Ap } }, | |
5214 | { "(bad)", { XX } }, | |
5215 | }, | |
5216 | ||
5217 | /* X86_64_0F01_REG_0 */ | |
5218 | { | |
5219 | { "sgdt{Q|IQ}", { M } }, | |
5220 | { "sgdt", { M } }, | |
5221 | }, | |
5222 | ||
5223 | /* X86_64_0F01_REG_1 */ | |
5224 | { | |
5225 | { "sidt{Q|IQ}", { M } }, | |
5226 | { "sidt", { M } }, | |
5227 | }, | |
5228 | ||
5229 | /* X86_64_0F01_REG_2 */ | |
5230 | { | |
5231 | { "lgdt{Q|Q}", { M } }, | |
5232 | { "lgdt", { M } }, | |
5233 | }, | |
5234 | ||
5235 | /* X86_64_0F01_REG_3 */ | |
5236 | { | |
5237 | { "lidt{Q|Q}", { M } }, | |
5238 | { "lidt", { M } }, | |
5239 | }, | |
5240 | }; | |
5241 | ||
5242 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
5243 | |
5244 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
5245 | { |
5246 | /* 00 */ | |
c1e679ec DR |
5247 | { "pshufb", { MX, EM } }, |
5248 | { "phaddw", { MX, EM } }, | |
5249 | { "phaddd", { MX, EM } }, | |
5250 | { "phaddsw", { MX, EM } }, | |
5251 | { "pmaddubsw", { MX, EM } }, | |
5252 | { "phsubw", { MX, EM } }, | |
5253 | { "phsubd", { MX, EM } }, | |
5254 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 5255 | /* 08 */ |
c1e679ec DR |
5256 | { "psignb", { MX, EM } }, |
5257 | { "psignw", { MX, EM } }, | |
5258 | { "psignd", { MX, EM } }, | |
5259 | { "pmulhrsw", { MX, EM } }, | |
c0f3af97 L |
5260 | { "(bad)", { XX } }, |
5261 | { "(bad)", { XX } }, | |
5262 | { "(bad)", { XX } }, | |
5263 | { "(bad)", { XX } }, | |
c1e679ec DR |
5264 | /* 10 */ |
5265 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
c0f3af97 L |
5266 | { "(bad)", { XX } }, |
5267 | { "(bad)", { XX } }, | |
5268 | { "(bad)", { XX } }, | |
c1e679ec DR |
5269 | { PREFIX_TABLE (PREFIX_0F3814) }, |
5270 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
c0f3af97 | 5271 | { "(bad)", { XX } }, |
c1e679ec DR |
5272 | { PREFIX_TABLE (PREFIX_0F3817) }, |
5273 | /* 18 */ | |
c0f3af97 L |
5274 | { "(bad)", { XX } }, |
5275 | { "(bad)", { XX } }, | |
5276 | { "(bad)", { XX } }, | |
5277 | { "(bad)", { XX } }, | |
c1e679ec DR |
5278 | { "pabsb", { MX, EM } }, |
5279 | { "pabsw", { MX, EM } }, | |
5280 | { "pabsd", { MX, EM } }, | |
c0f3af97 | 5281 | { "(bad)", { XX } }, |
c1e679ec DR |
5282 | /* 20 */ |
5283 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
5284 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
5285 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
5286 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
5287 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
5288 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
c0f3af97 L |
5289 | { "(bad)", { XX } }, |
5290 | { "(bad)", { XX } }, | |
c1e679ec DR |
5291 | /* 28 */ |
5292 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
5293 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
5294 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
5295 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
c0f3af97 L |
5296 | { "(bad)", { XX } }, |
5297 | { "(bad)", { XX } }, | |
5298 | { "(bad)", { XX } }, | |
5299 | { "(bad)", { XX } }, | |
c1e679ec DR |
5300 | /* 30 */ |
5301 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
5302 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
5303 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
5304 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
5305 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
5306 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
c0f3af97 | 5307 | { "(bad)", { XX } }, |
c1e679ec DR |
5308 | { PREFIX_TABLE (PREFIX_0F3837) }, |
5309 | /* 38 */ | |
5310 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
5311 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
5312 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
5313 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
5314 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
5315 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
5316 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
5317 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
c0f3af97 | 5318 | /* 40 */ |
c1e679ec DR |
5319 | { PREFIX_TABLE (PREFIX_0F3840) }, |
5320 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
4e7d34a6 L |
5321 | { "(bad)", { XX } }, |
5322 | { "(bad)", { XX } }, | |
c0f3af97 | 5323 | { "(bad)", { XX } }, |
c0f3af97 L |
5324 | { "(bad)", { XX } }, |
5325 | { "(bad)", { XX } }, | |
5326 | { "(bad)", { XX } }, | |
85f10a01 | 5327 | /* 48 */ |
4e7d34a6 L |
5328 | { "(bad)", { XX } }, |
5329 | { "(bad)", { XX } }, | |
5330 | { "(bad)", { XX } }, | |
5331 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5332 | { "(bad)", { XX } }, |
5333 | { "(bad)", { XX } }, | |
5334 | { "(bad)", { XX } }, | |
5335 | { "(bad)", { XX } }, | |
c0f3af97 | 5336 | /* 50 */ |
4e7d34a6 L |
5337 | { "(bad)", { XX } }, |
5338 | { "(bad)", { XX } }, | |
5339 | { "(bad)", { XX } }, | |
5340 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5341 | { "(bad)", { XX } }, |
5342 | { "(bad)", { XX } }, | |
5343 | { "(bad)", { XX } }, | |
5344 | { "(bad)", { XX } }, | |
c0f3af97 | 5345 | /* 58 */ |
4e7d34a6 L |
5346 | { "(bad)", { XX } }, |
5347 | { "(bad)", { XX } }, | |
5348 | { "(bad)", { XX } }, | |
5349 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5350 | { "(bad)", { XX } }, |
5351 | { "(bad)", { XX } }, | |
5352 | { "(bad)", { XX } }, | |
5353 | { "(bad)", { XX } }, | |
c0f3af97 | 5354 | /* 60 */ |
c1e679ec DR |
5355 | { "(bad)", { XX } }, |
5356 | { "(bad)", { XX } }, | |
5357 | { "(bad)", { XX } }, | |
5358 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5359 | { "(bad)", { XX } }, |
5360 | { "(bad)", { XX } }, | |
5361 | { "(bad)", { XX } }, | |
5362 | { "(bad)", { XX } }, | |
5363 | /* 68 */ | |
5364 | { "(bad)", { XX } }, | |
5365 | { "(bad)", { XX } }, | |
5366 | { "(bad)", { XX } }, | |
5367 | { "(bad)", { XX } }, | |
5368 | { "(bad)", { XX } }, | |
5369 | { "(bad)", { XX } }, | |
5370 | { "(bad)", { XX } }, | |
5371 | { "(bad)", { XX } }, | |
85f10a01 | 5372 | /* 70 */ |
4e7d34a6 L |
5373 | { "(bad)", { XX } }, |
5374 | { "(bad)", { XX } }, | |
5375 | { "(bad)", { XX } }, | |
5376 | { "(bad)", { XX } }, | |
5377 | { "(bad)", { XX } }, | |
5378 | { "(bad)", { XX } }, | |
5379 | { "(bad)", { XX } }, | |
5380 | { "(bad)", { XX } }, | |
85f10a01 | 5381 | /* 78 */ |
4e7d34a6 L |
5382 | { "(bad)", { XX } }, |
5383 | { "(bad)", { XX } }, | |
5384 | { "(bad)", { XX } }, | |
5385 | { "(bad)", { XX } }, | |
5386 | { "(bad)", { XX } }, | |
5387 | { "(bad)", { XX } }, | |
5388 | { "(bad)", { XX } }, | |
5389 | { "(bad)", { XX } }, | |
85f10a01 | 5390 | /* 80 */ |
c1e679ec DR |
5391 | { PREFIX_TABLE (PREFIX_0F3880) }, |
5392 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
4e7d34a6 L |
5393 | { "(bad)", { XX } }, |
5394 | { "(bad)", { XX } }, | |
5395 | { "(bad)", { XX } }, | |
c0f3af97 L |
5396 | { "(bad)", { XX } }, |
5397 | { "(bad)", { XX } }, | |
5398 | { "(bad)", { XX } }, | |
85f10a01 | 5399 | /* 88 */ |
4e7d34a6 L |
5400 | { "(bad)", { XX } }, |
5401 | { "(bad)", { XX } }, | |
5402 | { "(bad)", { XX } }, | |
5403 | { "(bad)", { XX } }, | |
5404 | { "(bad)", { XX } }, | |
5405 | { "(bad)", { XX } }, | |
c0f3af97 L |
5406 | { "(bad)", { XX } }, |
5407 | { "(bad)", { XX } }, | |
85f10a01 | 5408 | /* 90 */ |
4e7d34a6 L |
5409 | { "(bad)", { XX } }, |
5410 | { "(bad)", { XX } }, | |
5411 | { "(bad)", { XX } }, | |
5412 | { "(bad)", { XX } }, | |
5413 | { "(bad)", { XX } }, | |
c0f3af97 L |
5414 | { "(bad)", { XX } }, |
5415 | { "(bad)", { XX } }, | |
5416 | { "(bad)", { XX } }, | |
85f10a01 | 5417 | /* 98 */ |
4e7d34a6 L |
5418 | { "(bad)", { XX } }, |
5419 | { "(bad)", { XX } }, | |
5420 | { "(bad)", { XX } }, | |
5421 | { "(bad)", { XX } }, | |
5422 | { "(bad)", { XX } }, | |
5423 | { "(bad)", { XX } }, | |
c0f3af97 L |
5424 | { "(bad)", { XX } }, |
5425 | { "(bad)", { XX } }, | |
85f10a01 | 5426 | /* a0 */ |
4e7d34a6 L |
5427 | { "(bad)", { XX } }, |
5428 | { "(bad)", { XX } }, | |
5429 | { "(bad)", { XX } }, | |
5430 | { "(bad)", { XX } }, | |
5431 | { "(bad)", { XX } }, | |
5432 | { "(bad)", { XX } }, | |
c0f3af97 | 5433 | { "(bad)", { XX } }, |
4e7d34a6 | 5434 | { "(bad)", { XX } }, |
85f10a01 | 5435 | /* a8 */ |
4e7d34a6 L |
5436 | { "(bad)", { XX } }, |
5437 | { "(bad)", { XX } }, | |
5438 | { "(bad)", { XX } }, | |
5439 | { "(bad)", { XX } }, | |
5440 | { "(bad)", { XX } }, | |
5441 | { "(bad)", { XX } }, | |
5442 | { "(bad)", { XX } }, | |
5443 | { "(bad)", { XX } }, | |
85f10a01 | 5444 | /* b0 */ |
4e7d34a6 L |
5445 | { "(bad)", { XX } }, |
5446 | { "(bad)", { XX } }, | |
5447 | { "(bad)", { XX } }, | |
5448 | { "(bad)", { XX } }, | |
5449 | { "(bad)", { XX } }, | |
5450 | { "(bad)", { XX } }, | |
c0f3af97 | 5451 | { "(bad)", { XX } }, |
4e7d34a6 | 5452 | { "(bad)", { XX } }, |
85f10a01 | 5453 | /* b8 */ |
4e7d34a6 L |
5454 | { "(bad)", { XX } }, |
5455 | { "(bad)", { XX } }, | |
5456 | { "(bad)", { XX } }, | |
5457 | { "(bad)", { XX } }, | |
5458 | { "(bad)", { XX } }, | |
5459 | { "(bad)", { XX } }, | |
5460 | { "(bad)", { XX } }, | |
5461 | { "(bad)", { XX } }, | |
85f10a01 | 5462 | /* c0 */ |
4e7d34a6 L |
5463 | { "(bad)", { XX } }, |
5464 | { "(bad)", { XX } }, | |
5465 | { "(bad)", { XX } }, | |
5466 | { "(bad)", { XX } }, | |
5467 | { "(bad)", { XX } }, | |
5468 | { "(bad)", { XX } }, | |
5469 | { "(bad)", { XX } }, | |
5470 | { "(bad)", { XX } }, | |
85f10a01 | 5471 | /* c8 */ |
4e7d34a6 L |
5472 | { "(bad)", { XX } }, |
5473 | { "(bad)", { XX } }, | |
5474 | { "(bad)", { XX } }, | |
5475 | { "(bad)", { XX } }, | |
5476 | { "(bad)", { XX } }, | |
5477 | { "(bad)", { XX } }, | |
5478 | { "(bad)", { XX } }, | |
5479 | { "(bad)", { XX } }, | |
85f10a01 | 5480 | /* d0 */ |
4e7d34a6 L |
5481 | { "(bad)", { XX } }, |
5482 | { "(bad)", { XX } }, | |
5483 | { "(bad)", { XX } }, | |
5484 | { "(bad)", { XX } }, | |
5485 | { "(bad)", { XX } }, | |
5486 | { "(bad)", { XX } }, | |
5487 | { "(bad)", { XX } }, | |
5488 | { "(bad)", { XX } }, | |
85f10a01 | 5489 | /* d8 */ |
4e7d34a6 L |
5490 | { "(bad)", { XX } }, |
5491 | { "(bad)", { XX } }, | |
5492 | { "(bad)", { XX } }, | |
c1e679ec DR |
5493 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
5494 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
5495 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
5496 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
5497 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
85f10a01 | 5498 | /* e0 */ |
4e7d34a6 L |
5499 | { "(bad)", { XX } }, |
5500 | { "(bad)", { XX } }, | |
5501 | { "(bad)", { XX } }, | |
5502 | { "(bad)", { XX } }, | |
5503 | { "(bad)", { XX } }, | |
5504 | { "(bad)", { XX } }, | |
5505 | { "(bad)", { XX } }, | |
5506 | { "(bad)", { XX } }, | |
85f10a01 | 5507 | /* e8 */ |
4e7d34a6 L |
5508 | { "(bad)", { XX } }, |
5509 | { "(bad)", { XX } }, | |
5510 | { "(bad)", { XX } }, | |
5511 | { "(bad)", { XX } }, | |
5512 | { "(bad)", { XX } }, | |
5513 | { "(bad)", { XX } }, | |
5514 | { "(bad)", { XX } }, | |
5515 | { "(bad)", { XX } }, | |
85f10a01 | 5516 | /* f0 */ |
c1e679ec DR |
5517 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
5518 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
4e7d34a6 L |
5519 | { "(bad)", { XX } }, |
5520 | { "(bad)", { XX } }, | |
5521 | { "(bad)", { XX } }, | |
5522 | { "(bad)", { XX } }, | |
5523 | { "(bad)", { XX } }, | |
5524 | { "(bad)", { XX } }, | |
85f10a01 | 5525 | /* f8 */ |
4e7d34a6 L |
5526 | { "(bad)", { XX } }, |
5527 | { "(bad)", { XX } }, | |
5528 | { "(bad)", { XX } }, | |
5529 | { "(bad)", { XX } }, | |
5530 | { "(bad)", { XX } }, | |
5531 | { "(bad)", { XX } }, | |
5532 | { "(bad)", { XX } }, | |
5533 | { "(bad)", { XX } }, | |
85f10a01 | 5534 | }, |
c1e679ec | 5535 | /* THREE_BYTE_0F3A */ |
85f10a01 MM |
5536 | { |
5537 | /* 00 */ | |
4e7d34a6 L |
5538 | { "(bad)", { XX } }, |
5539 | { "(bad)", { XX } }, | |
5540 | { "(bad)", { XX } }, | |
5541 | { "(bad)", { XX } }, | |
5542 | { "(bad)", { XX } }, | |
5543 | { "(bad)", { XX } }, | |
5544 | { "(bad)", { XX } }, | |
5545 | { "(bad)", { XX } }, | |
85f10a01 | 5546 | /* 08 */ |
c1e679ec DR |
5547 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
5548 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
5549 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
5550 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
5551 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
5552 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
5553 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
5554 | { "palignr", { MX, EM, Ib } }, | |
85f10a01 | 5555 | /* 10 */ |
4e7d34a6 L |
5556 | { "(bad)", { XX } }, |
5557 | { "(bad)", { XX } }, | |
5558 | { "(bad)", { XX } }, | |
5559 | { "(bad)", { XX } }, | |
c1e679ec DR |
5560 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
5561 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
5562 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
5563 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
85f10a01 | 5564 | /* 18 */ |
4e7d34a6 L |
5565 | { "(bad)", { XX } }, |
5566 | { "(bad)", { XX } }, | |
5567 | { "(bad)", { XX } }, | |
5568 | { "(bad)", { XX } }, | |
5569 | { "(bad)", { XX } }, | |
5570 | { "(bad)", { XX } }, | |
5571 | { "(bad)", { XX } }, | |
5572 | { "(bad)", { XX } }, | |
85f10a01 | 5573 | /* 20 */ |
c1e679ec DR |
5574 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
5575 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
5576 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
4e7d34a6 L |
5577 | { "(bad)", { XX } }, |
5578 | { "(bad)", { XX } }, | |
5579 | { "(bad)", { XX } }, | |
5580 | { "(bad)", { XX } }, | |
5581 | { "(bad)", { XX } }, | |
85f10a01 | 5582 | /* 28 */ |
4e7d34a6 L |
5583 | { "(bad)", { XX } }, |
5584 | { "(bad)", { XX } }, | |
5585 | { "(bad)", { XX } }, | |
5586 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5587 | { "(bad)", { XX } }, |
5588 | { "(bad)", { XX } }, | |
5589 | { "(bad)", { XX } }, | |
5590 | { "(bad)", { XX } }, | |
c0f3af97 | 5591 | /* 30 */ |
c1e679ec DR |
5592 | { "(bad)", { XX } }, |
5593 | { "(bad)", { XX } }, | |
4e7d34a6 | 5594 | { "(bad)", { XX } }, |
4e7d34a6 L |
5595 | { "(bad)", { XX } }, |
5596 | { "(bad)", { XX } }, | |
5597 | { "(bad)", { XX } }, | |
5598 | { "(bad)", { XX } }, | |
5599 | { "(bad)", { XX } }, | |
c0f3af97 | 5600 | /* 38 */ |
4e7d34a6 L |
5601 | { "(bad)", { XX } }, |
5602 | { "(bad)", { XX } }, | |
5603 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5604 | { "(bad)", { XX } }, |
5605 | { "(bad)", { XX } }, | |
5606 | { "(bad)", { XX } }, | |
5607 | { "(bad)", { XX } }, | |
5608 | { "(bad)", { XX } }, | |
c0f3af97 | 5609 | /* 40 */ |
c1e679ec DR |
5610 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
5611 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
5612 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
5613 | { "(bad)", { XX } }, | |
5614 | { PREFIX_TABLE (PREFIX_0F3A44) }, | |
4e7d34a6 L |
5615 | { "(bad)", { XX } }, |
5616 | { "(bad)", { XX } }, | |
5617 | { "(bad)", { XX } }, | |
85f10a01 | 5618 | /* 48 */ |
4e7d34a6 L |
5619 | { "(bad)", { XX } }, |
5620 | { "(bad)", { XX } }, | |
5621 | { "(bad)", { XX } }, | |
c1e679ec | 5622 | { "(bad)", { XX } }, |
4e7d34a6 L |
5623 | { "(bad)", { XX } }, |
5624 | { "(bad)", { XX } }, | |
5625 | { "(bad)", { XX } }, | |
5626 | { "(bad)", { XX } }, | |
c0f3af97 | 5627 | /* 50 */ |
4e7d34a6 L |
5628 | { "(bad)", { XX } }, |
5629 | { "(bad)", { XX } }, | |
5630 | { "(bad)", { XX } }, | |
c1e679ec DR |
5631 | { "(bad)", { XX } }, |
5632 | { "(bad)", { XX } }, | |
5633 | { "(bad)", { XX } }, | |
5634 | { "(bad)", { XX } }, | |
5635 | { "(bad)", { XX } }, | |
85f10a01 | 5636 | /* 58 */ |
4e7d34a6 L |
5637 | { "(bad)", { XX } }, |
5638 | { "(bad)", { XX } }, | |
5639 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5640 | { "(bad)", { XX } }, |
5641 | { "(bad)", { XX } }, | |
5642 | { "(bad)", { XX } }, | |
5643 | { "(bad)", { XX } }, | |
4e7d34a6 | 5644 | { "(bad)", { XX } }, |
c1e679ec DR |
5645 | /* 60 */ |
5646 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
5647 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
5648 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
5649 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
4e7d34a6 L |
5650 | { "(bad)", { XX } }, |
5651 | { "(bad)", { XX } }, | |
5652 | { "(bad)", { XX } }, | |
5653 | { "(bad)", { XX } }, | |
c0f3af97 L |
5654 | /* 68 */ |
5655 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5656 | { "(bad)", { XX } }, |
5657 | { "(bad)", { XX } }, | |
5658 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5659 | { "(bad)", { XX } }, |
5660 | { "(bad)", { XX } }, | |
5661 | { "(bad)", { XX } }, | |
5662 | { "(bad)", { XX } }, | |
85f10a01 | 5663 | /* 70 */ |
4e7d34a6 L |
5664 | { "(bad)", { XX } }, |
5665 | { "(bad)", { XX } }, | |
5666 | { "(bad)", { XX } }, | |
5667 | { "(bad)", { XX } }, | |
5668 | { "(bad)", { XX } }, | |
5669 | { "(bad)", { XX } }, | |
5670 | { "(bad)", { XX } }, | |
5671 | { "(bad)", { XX } }, | |
85f10a01 | 5672 | /* 78 */ |
4e7d34a6 L |
5673 | { "(bad)", { XX } }, |
5674 | { "(bad)", { XX } }, | |
5675 | { "(bad)", { XX } }, | |
5676 | { "(bad)", { XX } }, | |
5677 | { "(bad)", { XX } }, | |
5678 | { "(bad)", { XX } }, | |
5679 | { "(bad)", { XX } }, | |
5680 | { "(bad)", { XX } }, | |
85f10a01 | 5681 | /* 80 */ |
4e7d34a6 L |
5682 | { "(bad)", { XX } }, |
5683 | { "(bad)", { XX } }, | |
5684 | { "(bad)", { XX } }, | |
5685 | { "(bad)", { XX } }, | |
5686 | { "(bad)", { XX } }, | |
5687 | { "(bad)", { XX } }, | |
5688 | { "(bad)", { XX } }, | |
5689 | { "(bad)", { XX } }, | |
5690 | /* 88 */ | |
5691 | { "(bad)", { XX } }, | |
5692 | { "(bad)", { XX } }, | |
5693 | { "(bad)", { XX } }, | |
5694 | { "(bad)", { XX } }, | |
5695 | { "(bad)", { XX } }, | |
5696 | { "(bad)", { XX } }, | |
5697 | { "(bad)", { XX } }, | |
5698 | { "(bad)", { XX } }, | |
5699 | /* 90 */ | |
5700 | { "(bad)", { XX } }, | |
5701 | { "(bad)", { XX } }, | |
5702 | { "(bad)", { XX } }, | |
5703 | { "(bad)", { XX } }, | |
5704 | { "(bad)", { XX } }, | |
5705 | { "(bad)", { XX } }, | |
5706 | { "(bad)", { XX } }, | |
5707 | { "(bad)", { XX } }, | |
5708 | /* 98 */ | |
5709 | { "(bad)", { XX } }, | |
5710 | { "(bad)", { XX } }, | |
5711 | { "(bad)", { XX } }, | |
5712 | { "(bad)", { XX } }, | |
5713 | { "(bad)", { XX } }, | |
5714 | { "(bad)", { XX } }, | |
5715 | { "(bad)", { XX } }, | |
5716 | { "(bad)", { XX } }, | |
5717 | /* a0 */ | |
5718 | { "(bad)", { XX } }, | |
5719 | { "(bad)", { XX } }, | |
5720 | { "(bad)", { XX } }, | |
5721 | { "(bad)", { XX } }, | |
5722 | { "(bad)", { XX } }, | |
5723 | { "(bad)", { XX } }, | |
5724 | { "(bad)", { XX } }, | |
5725 | { "(bad)", { XX } }, | |
5726 | /* a8 */ | |
5727 | { "(bad)", { XX } }, | |
5728 | { "(bad)", { XX } }, | |
5729 | { "(bad)", { XX } }, | |
5730 | { "(bad)", { XX } }, | |
5731 | { "(bad)", { XX } }, | |
5732 | { "(bad)", { XX } }, | |
5733 | { "(bad)", { XX } }, | |
5734 | { "(bad)", { XX } }, | |
5735 | /* b0 */ | |
5736 | { "(bad)", { XX } }, | |
5737 | { "(bad)", { XX } }, | |
5738 | { "(bad)", { XX } }, | |
5739 | { "(bad)", { XX } }, | |
5740 | { "(bad)", { XX } }, | |
5741 | { "(bad)", { XX } }, | |
5742 | { "(bad)", { XX } }, | |
5743 | { "(bad)", { XX } }, | |
5744 | /* b8 */ | |
5745 | { "(bad)", { XX } }, | |
5746 | { "(bad)", { XX } }, | |
5747 | { "(bad)", { XX } }, | |
5748 | { "(bad)", { XX } }, | |
5749 | { "(bad)", { XX } }, | |
5750 | { "(bad)", { XX } }, | |
5751 | { "(bad)", { XX } }, | |
5752 | { "(bad)", { XX } }, | |
5753 | /* c0 */ | |
5754 | { "(bad)", { XX } }, | |
5755 | { "(bad)", { XX } }, | |
5756 | { "(bad)", { XX } }, | |
5757 | { "(bad)", { XX } }, | |
5758 | { "(bad)", { XX } }, | |
5759 | { "(bad)", { XX } }, | |
5760 | { "(bad)", { XX } }, | |
5761 | { "(bad)", { XX } }, | |
5762 | /* c8 */ | |
5763 | { "(bad)", { XX } }, | |
5764 | { "(bad)", { XX } }, | |
5765 | { "(bad)", { XX } }, | |
5766 | { "(bad)", { XX } }, | |
5767 | { "(bad)", { XX } }, | |
5768 | { "(bad)", { XX } }, | |
5769 | { "(bad)", { XX } }, | |
5770 | { "(bad)", { XX } }, | |
5771 | /* d0 */ | |
5772 | { "(bad)", { XX } }, | |
5773 | { "(bad)", { XX } }, | |
5774 | { "(bad)", { XX } }, | |
5775 | { "(bad)", { XX } }, | |
5776 | { "(bad)", { XX } }, | |
5777 | { "(bad)", { XX } }, | |
5778 | { "(bad)", { XX } }, | |
5779 | { "(bad)", { XX } }, | |
5780 | /* d8 */ | |
5781 | { "(bad)", { XX } }, | |
5782 | { "(bad)", { XX } }, | |
5783 | { "(bad)", { XX } }, | |
5784 | { "(bad)", { XX } }, | |
5785 | { "(bad)", { XX } }, | |
5786 | { "(bad)", { XX } }, | |
5787 | { "(bad)", { XX } }, | |
c1e679ec | 5788 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
4e7d34a6 L |
5789 | /* e0 */ |
5790 | { "(bad)", { XX } }, | |
5791 | { "(bad)", { XX } }, | |
5792 | { "(bad)", { XX } }, | |
5793 | { "(bad)", { XX } }, | |
5794 | { "(bad)", { XX } }, | |
5795 | { "(bad)", { XX } }, | |
5796 | { "(bad)", { XX } }, | |
5797 | { "(bad)", { XX } }, | |
5798 | /* e8 */ | |
5799 | { "(bad)", { XX } }, | |
5800 | { "(bad)", { XX } }, | |
5801 | { "(bad)", { XX } }, | |
5802 | { "(bad)", { XX } }, | |
5803 | { "(bad)", { XX } }, | |
5804 | { "(bad)", { XX } }, | |
5805 | { "(bad)", { XX } }, | |
5806 | { "(bad)", { XX } }, | |
5807 | /* f0 */ | |
5808 | { "(bad)", { XX } }, | |
5809 | { "(bad)", { XX } }, | |
5810 | { "(bad)", { XX } }, | |
5811 | { "(bad)", { XX } }, | |
5812 | { "(bad)", { XX } }, | |
5813 | { "(bad)", { XX } }, | |
5814 | { "(bad)", { XX } }, | |
5815 | { "(bad)", { XX } }, | |
5816 | /* f8 */ | |
5817 | { "(bad)", { XX } }, | |
5818 | { "(bad)", { XX } }, | |
5819 | { "(bad)", { XX } }, | |
5820 | { "(bad)", { XX } }, | |
5821 | { "(bad)", { XX } }, | |
5822 | { "(bad)", { XX } }, | |
5823 | { "(bad)", { XX } }, | |
5824 | { "(bad)", { XX } }, | |
5825 | }, | |
c1e679ec DR |
5826 | |
5827 | /* THREE_BYTE_0F7A */ | |
4e7d34a6 L |
5828 | { |
5829 | /* 00 */ | |
c0f3af97 L |
5830 | { "(bad)", { XX } }, |
5831 | { "(bad)", { XX } }, | |
5832 | { "(bad)", { XX } }, | |
5833 | { "(bad)", { XX } }, | |
5834 | { "(bad)", { XX } }, | |
5835 | { "(bad)", { XX } }, | |
5836 | { "(bad)", { XX } }, | |
5837 | { "(bad)", { XX } }, | |
4e7d34a6 | 5838 | /* 08 */ |
c0f3af97 L |
5839 | { "(bad)", { XX } }, |
5840 | { "(bad)", { XX } }, | |
5841 | { "(bad)", { XX } }, | |
5842 | { "(bad)", { XX } }, | |
d5d7db8e L |
5843 | { "(bad)", { XX } }, |
5844 | { "(bad)", { XX } }, | |
5845 | { "(bad)", { XX } }, | |
5846 | { "(bad)", { XX } }, | |
4e7d34a6 | 5847 | /* 10 */ |
d5d7db8e L |
5848 | { "(bad)", { XX } }, |
5849 | { "(bad)", { XX } }, | |
5850 | { "(bad)", { XX } }, | |
d5d7db8e | 5851 | { "(bad)", { XX } }, |
c0f3af97 L |
5852 | { "(bad)", { XX } }, |
5853 | { "(bad)", { XX } }, | |
5854 | { "(bad)", { XX } }, | |
5855 | { "(bad)", { XX } }, | |
4e7d34a6 | 5856 | /* 18 */ |
d5d7db8e L |
5857 | { "(bad)", { XX } }, |
5858 | { "(bad)", { XX } }, | |
5859 | { "(bad)", { XX } }, | |
5860 | { "(bad)", { XX } }, | |
c0f3af97 L |
5861 | { "(bad)", { XX } }, |
5862 | { "(bad)", { XX } }, | |
5863 | { "(bad)", { XX } }, | |
d5d7db8e | 5864 | { "(bad)", { XX } }, |
4e7d34a6 | 5865 | /* 20 */ |
c1e679ec | 5866 | { "ptest", { XX } }, |
c0f3af97 L |
5867 | { "(bad)", { XX } }, |
5868 | { "(bad)", { XX } }, | |
5869 | { "(bad)", { XX } }, | |
5870 | { "(bad)", { XX } }, | |
5871 | { "(bad)", { XX } }, | |
d5d7db8e L |
5872 | { "(bad)", { XX } }, |
5873 | { "(bad)", { XX } }, | |
4e7d34a6 | 5874 | /* 28 */ |
c0f3af97 L |
5875 | { "(bad)", { XX } }, |
5876 | { "(bad)", { XX } }, | |
5877 | { "(bad)", { XX } }, | |
5878 | { "(bad)", { XX } }, | |
d5d7db8e L |
5879 | { "(bad)", { XX } }, |
5880 | { "(bad)", { XX } }, | |
5881 | { "(bad)", { XX } }, | |
5882 | { "(bad)", { XX } }, | |
4e7d34a6 | 5883 | /* 30 */ |
d5d7db8e | 5884 | { "(bad)", { XX } }, |
d5d7db8e L |
5885 | { "(bad)", { XX } }, |
5886 | { "(bad)", { XX } }, | |
5887 | { "(bad)", { XX } }, | |
5888 | { "(bad)", { XX } }, | |
5889 | { "(bad)", { XX } }, | |
5890 | { "(bad)", { XX } }, | |
c0f3af97 L |
5891 | { "(bad)", { XX } }, |
5892 | /* 38 */ | |
5893 | { "(bad)", { XX } }, | |
5894 | { "(bad)", { XX } }, | |
5895 | { "(bad)", { XX } }, | |
5896 | { "(bad)", { XX } }, | |
d5d7db8e L |
5897 | { "(bad)", { XX } }, |
5898 | { "(bad)", { XX } }, | |
5899 | { "(bad)", { XX } }, | |
5900 | { "(bad)", { XX } }, | |
c0f3af97 | 5901 | /* 40 */ |
c1e679ec DR |
5902 | { "(bad)", { XX } }, |
5903 | { "phaddbw", { XM, EXq } }, | |
5904 | { "phaddbd", { XM, EXq } }, | |
5905 | { "phaddbq", { XM, EXq } }, | |
d5d7db8e L |
5906 | { "(bad)", { XX } }, |
5907 | { "(bad)", { XX } }, | |
c1e679ec DR |
5908 | { "phaddwd", { XM, EXq } }, |
5909 | { "phaddwq", { XM, EXq } }, | |
5910 | /* 48 */ | |
d5d7db8e L |
5911 | { "(bad)", { XX } }, |
5912 | { "(bad)", { XX } }, | |
d5d7db8e | 5913 | { "(bad)", { XX } }, |
c1e679ec | 5914 | { "phadddq", { XM, EXq } }, |
d5d7db8e L |
5915 | { "(bad)", { XX } }, |
5916 | { "(bad)", { XX } }, | |
5917 | { "(bad)", { XX } }, | |
5918 | { "(bad)", { XX } }, | |
c1e679ec | 5919 | /* 50 */ |
d5d7db8e | 5920 | { "(bad)", { XX } }, |
c1e679ec DR |
5921 | { "phaddubw", { XM, EXq } }, |
5922 | { "phaddubd", { XM, EXq } }, | |
5923 | { "phaddubq", { XM, EXq } }, | |
d5d7db8e L |
5924 | { "(bad)", { XX } }, |
5925 | { "(bad)", { XX } }, | |
c1e679ec DR |
5926 | { "phadduwd", { XM, EXq } }, |
5927 | { "phadduwq", { XM, EXq } }, | |
4e7d34a6 | 5928 | /* 58 */ |
d5d7db8e L |
5929 | { "(bad)", { XX } }, |
5930 | { "(bad)", { XX } }, | |
5931 | { "(bad)", { XX } }, | |
c1e679ec | 5932 | { "phaddudq", { XM, EXq } }, |
d5d7db8e L |
5933 | { "(bad)", { XX } }, |
5934 | { "(bad)", { XX } }, | |
5935 | { "(bad)", { XX } }, | |
5936 | { "(bad)", { XX } }, | |
4e7d34a6 | 5937 | /* 60 */ |
d5d7db8e | 5938 | { "(bad)", { XX } }, |
c1e679ec DR |
5939 | { "phsubbw", { XM, EXq } }, |
5940 | { "phsubbd", { XM, EXq } }, | |
5941 | { "phsubbq", { XM, EXq } }, | |
d5d7db8e L |
5942 | { "(bad)", { XX } }, |
5943 | { "(bad)", { XX } }, | |
5944 | { "(bad)", { XX } }, | |
5945 | { "(bad)", { XX } }, | |
4e7d34a6 | 5946 | /* 68 */ |
d5d7db8e L |
5947 | { "(bad)", { XX } }, |
5948 | { "(bad)", { XX } }, | |
5949 | { "(bad)", { XX } }, | |
5950 | { "(bad)", { XX } }, | |
5951 | { "(bad)", { XX } }, | |
5952 | { "(bad)", { XX } }, | |
5953 | { "(bad)", { XX } }, | |
5954 | { "(bad)", { XX } }, | |
4e7d34a6 | 5955 | /* 70 */ |
d5d7db8e L |
5956 | { "(bad)", { XX } }, |
5957 | { "(bad)", { XX } }, | |
5958 | { "(bad)", { XX } }, | |
5959 | { "(bad)", { XX } }, | |
5960 | { "(bad)", { XX } }, | |
5961 | { "(bad)", { XX } }, | |
5962 | { "(bad)", { XX } }, | |
5963 | { "(bad)", { XX } }, | |
4e7d34a6 | 5964 | /* 78 */ |
d5d7db8e L |
5965 | { "(bad)", { XX } }, |
5966 | { "(bad)", { XX } }, | |
5967 | { "(bad)", { XX } }, | |
5968 | { "(bad)", { XX } }, | |
5969 | { "(bad)", { XX } }, | |
5970 | { "(bad)", { XX } }, | |
5971 | { "(bad)", { XX } }, | |
5972 | { "(bad)", { XX } }, | |
4e7d34a6 | 5973 | /* 80 */ |
d5d7db8e L |
5974 | { "(bad)", { XX } }, |
5975 | { "(bad)", { XX } }, | |
5976 | { "(bad)", { XX } }, | |
5977 | { "(bad)", { XX } }, | |
5978 | { "(bad)", { XX } }, | |
5979 | { "(bad)", { XX } }, | |
5980 | { "(bad)", { XX } }, | |
5981 | { "(bad)", { XX } }, | |
4e7d34a6 | 5982 | /* 88 */ |
d5d7db8e L |
5983 | { "(bad)", { XX } }, |
5984 | { "(bad)", { XX } }, | |
5985 | { "(bad)", { XX } }, | |
5986 | { "(bad)", { XX } }, | |
5987 | { "(bad)", { XX } }, | |
5988 | { "(bad)", { XX } }, | |
5989 | { "(bad)", { XX } }, | |
5990 | { "(bad)", { XX } }, | |
4e7d34a6 | 5991 | /* 90 */ |
d5d7db8e L |
5992 | { "(bad)", { XX } }, |
5993 | { "(bad)", { XX } }, | |
5994 | { "(bad)", { XX } }, | |
5995 | { "(bad)", { XX } }, | |
5996 | { "(bad)", { XX } }, | |
5997 | { "(bad)", { XX } }, | |
5998 | { "(bad)", { XX } }, | |
5999 | { "(bad)", { XX } }, | |
4e7d34a6 | 6000 | /* 98 */ |
d5d7db8e L |
6001 | { "(bad)", { XX } }, |
6002 | { "(bad)", { XX } }, | |
6003 | { "(bad)", { XX } }, | |
6004 | { "(bad)", { XX } }, | |
6005 | { "(bad)", { XX } }, | |
6006 | { "(bad)", { XX } }, | |
6007 | { "(bad)", { XX } }, | |
6008 | { "(bad)", { XX } }, | |
4e7d34a6 | 6009 | /* a0 */ |
d5d7db8e L |
6010 | { "(bad)", { XX } }, |
6011 | { "(bad)", { XX } }, | |
6012 | { "(bad)", { XX } }, | |
6013 | { "(bad)", { XX } }, | |
6014 | { "(bad)", { XX } }, | |
6015 | { "(bad)", { XX } }, | |
6016 | { "(bad)", { XX } }, | |
6017 | { "(bad)", { XX } }, | |
4e7d34a6 | 6018 | /* a8 */ |
d5d7db8e L |
6019 | { "(bad)", { XX } }, |
6020 | { "(bad)", { XX } }, | |
6021 | { "(bad)", { XX } }, | |
6022 | { "(bad)", { XX } }, | |
6023 | { "(bad)", { XX } }, | |
6024 | { "(bad)", { XX } }, | |
6025 | { "(bad)", { XX } }, | |
6026 | { "(bad)", { XX } }, | |
6027 | /* b0 */ | |
6028 | { "(bad)", { XX } }, | |
6029 | { "(bad)", { XX } }, | |
6030 | { "(bad)", { XX } }, | |
6031 | { "(bad)", { XX } }, | |
6032 | { "(bad)", { XX } }, | |
6033 | { "(bad)", { XX } }, | |
6034 | { "(bad)", { XX } }, | |
6035 | { "(bad)", { XX } }, | |
85f10a01 | 6036 | /* b8 */ |
d5d7db8e L |
6037 | { "(bad)", { XX } }, |
6038 | { "(bad)", { XX } }, | |
6039 | { "(bad)", { XX } }, | |
6040 | { "(bad)", { XX } }, | |
6041 | { "(bad)", { XX } }, | |
6042 | { "(bad)", { XX } }, | |
6043 | { "(bad)", { XX } }, | |
6044 | { "(bad)", { XX } }, | |
85f10a01 | 6045 | /* c0 */ |
d5d7db8e L |
6046 | { "(bad)", { XX } }, |
6047 | { "(bad)", { XX } }, | |
6048 | { "(bad)", { XX } }, | |
6049 | { "(bad)", { XX } }, | |
6050 | { "(bad)", { XX } }, | |
6051 | { "(bad)", { XX } }, | |
6052 | { "(bad)", { XX } }, | |
6053 | { "(bad)", { XX } }, | |
85f10a01 | 6054 | /* c8 */ |
d5d7db8e L |
6055 | { "(bad)", { XX } }, |
6056 | { "(bad)", { XX } }, | |
6057 | { "(bad)", { XX } }, | |
6058 | { "(bad)", { XX } }, | |
6059 | { "(bad)", { XX } }, | |
6060 | { "(bad)", { XX } }, | |
6061 | { "(bad)", { XX } }, | |
6062 | { "(bad)", { XX } }, | |
85f10a01 | 6063 | /* d0 */ |
d5d7db8e L |
6064 | { "(bad)", { XX } }, |
6065 | { "(bad)", { XX } }, | |
6066 | { "(bad)", { XX } }, | |
6067 | { "(bad)", { XX } }, | |
6068 | { "(bad)", { XX } }, | |
6069 | { "(bad)", { XX } }, | |
6070 | { "(bad)", { XX } }, | |
6071 | { "(bad)", { XX } }, | |
85f10a01 | 6072 | /* d8 */ |
d5d7db8e L |
6073 | { "(bad)", { XX } }, |
6074 | { "(bad)", { XX } }, | |
6075 | { "(bad)", { XX } }, | |
6076 | { "(bad)", { XX } }, | |
6077 | { "(bad)", { XX } }, | |
6078 | { "(bad)", { XX } }, | |
6079 | { "(bad)", { XX } }, | |
6080 | { "(bad)", { XX } }, | |
85f10a01 | 6081 | /* e0 */ |
d5d7db8e L |
6082 | { "(bad)", { XX } }, |
6083 | { "(bad)", { XX } }, | |
6084 | { "(bad)", { XX } }, | |
6085 | { "(bad)", { XX } }, | |
6086 | { "(bad)", { XX } }, | |
6087 | { "(bad)", { XX } }, | |
6088 | { "(bad)", { XX } }, | |
6089 | { "(bad)", { XX } }, | |
85f10a01 | 6090 | /* e8 */ |
d5d7db8e L |
6091 | { "(bad)", { XX } }, |
6092 | { "(bad)", { XX } }, | |
6093 | { "(bad)", { XX } }, | |
6094 | { "(bad)", { XX } }, | |
6095 | { "(bad)", { XX } }, | |
6096 | { "(bad)", { XX } }, | |
6097 | { "(bad)", { XX } }, | |
6098 | { "(bad)", { XX } }, | |
85f10a01 | 6099 | /* f0 */ |
c0f3af97 L |
6100 | { "(bad)", { XX } }, |
6101 | { "(bad)", { XX } }, | |
d5d7db8e L |
6102 | { "(bad)", { XX } }, |
6103 | { "(bad)", { XX } }, | |
6104 | { "(bad)", { XX } }, | |
6105 | { "(bad)", { XX } }, | |
6106 | { "(bad)", { XX } }, | |
6107 | { "(bad)", { XX } }, | |
85f10a01 | 6108 | /* f8 */ |
d5d7db8e L |
6109 | { "(bad)", { XX } }, |
6110 | { "(bad)", { XX } }, | |
6111 | { "(bad)", { XX } }, | |
6112 | { "(bad)", { XX } }, | |
6113 | { "(bad)", { XX } }, | |
6114 | { "(bad)", { XX } }, | |
6115 | { "(bad)", { XX } }, | |
6116 | { "(bad)", { XX } }, | |
85f10a01 | 6117 | }, |
c0f3af97 L |
6118 | }; |
6119 | ||
c1e679ec | 6120 | |
c0f3af97 L |
6121 | static const struct dis386 vex_table[][256] = { |
6122 | /* VEX_0F */ | |
85f10a01 MM |
6123 | { |
6124 | /* 00 */ | |
d5d7db8e L |
6125 | { "(bad)", { XX } }, |
6126 | { "(bad)", { XX } }, | |
6127 | { "(bad)", { XX } }, | |
6128 | { "(bad)", { XX } }, | |
6129 | { "(bad)", { XX } }, | |
6130 | { "(bad)", { XX } }, | |
6131 | { "(bad)", { XX } }, | |
6132 | { "(bad)", { XX } }, | |
85f10a01 | 6133 | /* 08 */ |
d5d7db8e L |
6134 | { "(bad)", { XX } }, |
6135 | { "(bad)", { XX } }, | |
6136 | { "(bad)", { XX } }, | |
6137 | { "(bad)", { XX } }, | |
d5d7db8e L |
6138 | { "(bad)", { XX } }, |
6139 | { "(bad)", { XX } }, | |
6140 | { "(bad)", { XX } }, | |
6141 | { "(bad)", { XX } }, | |
c0f3af97 L |
6142 | /* 10 */ |
6143 | { PREFIX_TABLE (PREFIX_VEX_10) }, | |
6144 | { PREFIX_TABLE (PREFIX_VEX_11) }, | |
6145 | { PREFIX_TABLE (PREFIX_VEX_12) }, | |
6146 | { MOD_TABLE (MOD_VEX_13) }, | |
6147 | { "vunpcklpX", { XM, Vex, EXx } }, | |
6148 | { "vunpckhpX", { XM, Vex, EXx } }, | |
6149 | { PREFIX_TABLE (PREFIX_VEX_16) }, | |
6150 | { MOD_TABLE (MOD_VEX_17) }, | |
6151 | /* 18 */ | |
d5d7db8e L |
6152 | { "(bad)", { XX } }, |
6153 | { "(bad)", { XX } }, | |
6154 | { "(bad)", { XX } }, | |
d5d7db8e L |
6155 | { "(bad)", { XX } }, |
6156 | { "(bad)", { XX } }, | |
6157 | { "(bad)", { XX } }, | |
6158 | { "(bad)", { XX } }, | |
6159 | { "(bad)", { XX } }, | |
c0f3af97 | 6160 | /* 20 */ |
d5d7db8e L |
6161 | { "(bad)", { XX } }, |
6162 | { "(bad)", { XX } }, | |
6163 | { "(bad)", { XX } }, | |
6164 | { "(bad)", { XX } }, | |
6165 | { "(bad)", { XX } }, | |
6166 | { "(bad)", { XX } }, | |
6167 | { "(bad)", { XX } }, | |
6168 | { "(bad)", { XX } }, | |
c0f3af97 L |
6169 | /* 28 */ |
6170 | { "vmovapX", { XM, EXx } }, | |
b6169b20 | 6171 | { "vmovapX", { EXxS, XM } }, |
c0f3af97 L |
6172 | { PREFIX_TABLE (PREFIX_VEX_2A) }, |
6173 | { MOD_TABLE (MOD_VEX_2B) }, | |
6174 | { PREFIX_TABLE (PREFIX_VEX_2C) }, | |
6175 | { PREFIX_TABLE (PREFIX_VEX_2D) }, | |
6176 | { PREFIX_TABLE (PREFIX_VEX_2E) }, | |
6177 | { PREFIX_TABLE (PREFIX_VEX_2F) }, | |
85f10a01 | 6178 | /* 30 */ |
d5d7db8e L |
6179 | { "(bad)", { XX } }, |
6180 | { "(bad)", { XX } }, | |
6181 | { "(bad)", { XX } }, | |
6182 | { "(bad)", { XX } }, | |
6183 | { "(bad)", { XX } }, | |
6184 | { "(bad)", { XX } }, | |
6185 | { "(bad)", { XX } }, | |
6186 | { "(bad)", { XX } }, | |
4e7d34a6 | 6187 | /* 38 */ |
d5d7db8e L |
6188 | { "(bad)", { XX } }, |
6189 | { "(bad)", { XX } }, | |
6190 | { "(bad)", { XX } }, | |
6191 | { "(bad)", { XX } }, | |
6192 | { "(bad)", { XX } }, | |
6193 | { "(bad)", { XX } }, | |
6194 | { "(bad)", { XX } }, | |
6195 | { "(bad)", { XX } }, | |
6196 | /* 40 */ | |
c0f3af97 L |
6197 | { "(bad)", { XX } }, |
6198 | { "(bad)", { XX } }, | |
6199 | { "(bad)", { XX } }, | |
d5d7db8e L |
6200 | { "(bad)", { XX } }, |
6201 | { "(bad)", { XX } }, | |
6202 | { "(bad)", { XX } }, | |
6203 | { "(bad)", { XX } }, | |
6204 | { "(bad)", { XX } }, | |
85f10a01 | 6205 | /* 48 */ |
85f10a01 MM |
6206 | { "(bad)", { XX } }, |
6207 | { "(bad)", { XX } }, | |
6208 | { "(bad)", { XX } }, | |
6209 | { "(bad)", { XX } }, | |
6210 | { "(bad)", { XX } }, | |
6211 | { "(bad)", { XX } }, | |
6212 | { "(bad)", { XX } }, | |
6213 | { "(bad)", { XX } }, | |
d5d7db8e | 6214 | /* 50 */ |
c0f3af97 L |
6215 | { MOD_TABLE (MOD_VEX_51) }, |
6216 | { PREFIX_TABLE (PREFIX_VEX_51) }, | |
6217 | { PREFIX_TABLE (PREFIX_VEX_52) }, | |
6218 | { PREFIX_TABLE (PREFIX_VEX_53) }, | |
6219 | { "vandpX", { XM, Vex, EXx } }, | |
6220 | { "vandnpX", { XM, Vex, EXx } }, | |
6221 | { "vorpX", { XM, Vex, EXx } }, | |
6222 | { "vxorpX", { XM, Vex, EXx } }, | |
6223 | /* 58 */ | |
6224 | { PREFIX_TABLE (PREFIX_VEX_58) }, | |
6225 | { PREFIX_TABLE (PREFIX_VEX_59) }, | |
6226 | { PREFIX_TABLE (PREFIX_VEX_5A) }, | |
6227 | { PREFIX_TABLE (PREFIX_VEX_5B) }, | |
6228 | { PREFIX_TABLE (PREFIX_VEX_5C) }, | |
6229 | { PREFIX_TABLE (PREFIX_VEX_5D) }, | |
6230 | { PREFIX_TABLE (PREFIX_VEX_5E) }, | |
6231 | { PREFIX_TABLE (PREFIX_VEX_5F) }, | |
6232 | /* 60 */ | |
6233 | { PREFIX_TABLE (PREFIX_VEX_60) }, | |
6234 | { PREFIX_TABLE (PREFIX_VEX_61) }, | |
6235 | { PREFIX_TABLE (PREFIX_VEX_62) }, | |
6236 | { PREFIX_TABLE (PREFIX_VEX_63) }, | |
6237 | { PREFIX_TABLE (PREFIX_VEX_64) }, | |
6238 | { PREFIX_TABLE (PREFIX_VEX_65) }, | |
6239 | { PREFIX_TABLE (PREFIX_VEX_66) }, | |
6240 | { PREFIX_TABLE (PREFIX_VEX_67) }, | |
6241 | /* 68 */ | |
6242 | { PREFIX_TABLE (PREFIX_VEX_68) }, | |
6243 | { PREFIX_TABLE (PREFIX_VEX_69) }, | |
6244 | { PREFIX_TABLE (PREFIX_VEX_6A) }, | |
6245 | { PREFIX_TABLE (PREFIX_VEX_6B) }, | |
6246 | { PREFIX_TABLE (PREFIX_VEX_6C) }, | |
6247 | { PREFIX_TABLE (PREFIX_VEX_6D) }, | |
6248 | { PREFIX_TABLE (PREFIX_VEX_6E) }, | |
6249 | { PREFIX_TABLE (PREFIX_VEX_6F) }, | |
6250 | /* 70 */ | |
6251 | { PREFIX_TABLE (PREFIX_VEX_70) }, | |
6252 | { REG_TABLE (REG_VEX_71) }, | |
6253 | { REG_TABLE (REG_VEX_72) }, | |
6254 | { REG_TABLE (REG_VEX_73) }, | |
6255 | { PREFIX_TABLE (PREFIX_VEX_74) }, | |
6256 | { PREFIX_TABLE (PREFIX_VEX_75) }, | |
6257 | { PREFIX_TABLE (PREFIX_VEX_76) }, | |
6258 | { PREFIX_TABLE (PREFIX_VEX_77) }, | |
6259 | /* 78 */ | |
85f10a01 MM |
6260 | { "(bad)", { XX } }, |
6261 | { "(bad)", { XX } }, | |
6262 | { "(bad)", { XX } }, | |
6263 | { "(bad)", { XX } }, | |
c0f3af97 L |
6264 | { PREFIX_TABLE (PREFIX_VEX_7C) }, |
6265 | { PREFIX_TABLE (PREFIX_VEX_7D) }, | |
6266 | { PREFIX_TABLE (PREFIX_VEX_7E) }, | |
6267 | { PREFIX_TABLE (PREFIX_VEX_7F) }, | |
6268 | /* 80 */ | |
85f10a01 MM |
6269 | { "(bad)", { XX } }, |
6270 | { "(bad)", { XX } }, | |
6271 | { "(bad)", { XX } }, | |
6272 | { "(bad)", { XX } }, | |
85f10a01 MM |
6273 | { "(bad)", { XX } }, |
6274 | { "(bad)", { XX } }, | |
6275 | { "(bad)", { XX } }, | |
6276 | { "(bad)", { XX } }, | |
c0f3af97 | 6277 | /* 88 */ |
85f10a01 MM |
6278 | { "(bad)", { XX } }, |
6279 | { "(bad)", { XX } }, | |
6280 | { "(bad)", { XX } }, | |
6281 | { "(bad)", { XX } }, | |
6282 | { "(bad)", { XX } }, | |
6283 | { "(bad)", { XX } }, | |
6284 | { "(bad)", { XX } }, | |
6285 | { "(bad)", { XX } }, | |
c0f3af97 | 6286 | /* 90 */ |
85f10a01 MM |
6287 | { "(bad)", { XX } }, |
6288 | { "(bad)", { XX } }, | |
6289 | { "(bad)", { XX } }, | |
6290 | { "(bad)", { XX } }, | |
6291 | { "(bad)", { XX } }, | |
6292 | { "(bad)", { XX } }, | |
6293 | { "(bad)", { XX } }, | |
85f10a01 | 6294 | { "(bad)", { XX } }, |
c0f3af97 | 6295 | /* 98 */ |
85f10a01 MM |
6296 | { "(bad)", { XX } }, |
6297 | { "(bad)", { XX } }, | |
6298 | { "(bad)", { XX } }, | |
d5d7db8e L |
6299 | { "(bad)", { XX } }, |
6300 | { "(bad)", { XX } }, | |
6301 | { "(bad)", { XX } }, | |
6302 | { "(bad)", { XX } }, | |
6303 | { "(bad)", { XX } }, | |
c0f3af97 | 6304 | /* a0 */ |
d5d7db8e L |
6305 | { "(bad)", { XX } }, |
6306 | { "(bad)", { XX } }, | |
6307 | { "(bad)", { XX } }, | |
6308 | { "(bad)", { XX } }, | |
6309 | { "(bad)", { XX } }, | |
6310 | { "(bad)", { XX } }, | |
6311 | { "(bad)", { XX } }, | |
6312 | { "(bad)", { XX } }, | |
c0f3af97 | 6313 | /* a8 */ |
d5d7db8e L |
6314 | { "(bad)", { XX } }, |
6315 | { "(bad)", { XX } }, | |
6316 | { "(bad)", { XX } }, | |
6317 | { "(bad)", { XX } }, | |
6318 | { "(bad)", { XX } }, | |
6319 | { "(bad)", { XX } }, | |
c0f3af97 | 6320 | { REG_TABLE (REG_VEX_AE) }, |
d5d7db8e | 6321 | { "(bad)", { XX } }, |
c0f3af97 | 6322 | /* b0 */ |
d5d7db8e | 6323 | { "(bad)", { XX } }, |
d5d7db8e L |
6324 | { "(bad)", { XX } }, |
6325 | { "(bad)", { XX } }, | |
6326 | { "(bad)", { XX } }, | |
6327 | { "(bad)", { XX } }, | |
6328 | { "(bad)", { XX } }, | |
6329 | { "(bad)", { XX } }, | |
6330 | { "(bad)", { XX } }, | |
c0f3af97 | 6331 | /* b8 */ |
d5d7db8e | 6332 | { "(bad)", { XX } }, |
d5d7db8e L |
6333 | { "(bad)", { XX } }, |
6334 | { "(bad)", { XX } }, | |
6335 | { "(bad)", { XX } }, | |
6336 | { "(bad)", { XX } }, | |
6337 | { "(bad)", { XX } }, | |
6338 | { "(bad)", { XX } }, | |
6339 | { "(bad)", { XX } }, | |
c0f3af97 | 6340 | /* c0 */ |
d5d7db8e | 6341 | { "(bad)", { XX } }, |
d5d7db8e | 6342 | { "(bad)", { XX } }, |
c0f3af97 | 6343 | { PREFIX_TABLE (PREFIX_VEX_C2) }, |
d5d7db8e | 6344 | { "(bad)", { XX } }, |
c0f3af97 L |
6345 | { PREFIX_TABLE (PREFIX_VEX_C4) }, |
6346 | { PREFIX_TABLE (PREFIX_VEX_C5) }, | |
6347 | { "vshufpX", { XM, Vex, EXx, Ib } }, | |
d5d7db8e | 6348 | { "(bad)", { XX } }, |
c0f3af97 | 6349 | /* c8 */ |
d5d7db8e L |
6350 | { "(bad)", { XX } }, |
6351 | { "(bad)", { XX } }, | |
6352 | { "(bad)", { XX } }, | |
6353 | { "(bad)", { XX } }, | |
6354 | { "(bad)", { XX } }, | |
d5d7db8e L |
6355 | { "(bad)", { XX } }, |
6356 | { "(bad)", { XX } }, | |
6357 | { "(bad)", { XX } }, | |
c0f3af97 L |
6358 | /* d0 */ |
6359 | { PREFIX_TABLE (PREFIX_VEX_D0) }, | |
6360 | { PREFIX_TABLE (PREFIX_VEX_D1) }, | |
6361 | { PREFIX_TABLE (PREFIX_VEX_D2) }, | |
6362 | { PREFIX_TABLE (PREFIX_VEX_D3) }, | |
6363 | { PREFIX_TABLE (PREFIX_VEX_D4) }, | |
6364 | { PREFIX_TABLE (PREFIX_VEX_D5) }, | |
6365 | { PREFIX_TABLE (PREFIX_VEX_D6) }, | |
6366 | { PREFIX_TABLE (PREFIX_VEX_D7) }, | |
6367 | /* d8 */ | |
6368 | { PREFIX_TABLE (PREFIX_VEX_D8) }, | |
6369 | { PREFIX_TABLE (PREFIX_VEX_D9) }, | |
6370 | { PREFIX_TABLE (PREFIX_VEX_DA) }, | |
6371 | { PREFIX_TABLE (PREFIX_VEX_DB) }, | |
6372 | { PREFIX_TABLE (PREFIX_VEX_DC) }, | |
6373 | { PREFIX_TABLE (PREFIX_VEX_DD) }, | |
6374 | { PREFIX_TABLE (PREFIX_VEX_DE) }, | |
6375 | { PREFIX_TABLE (PREFIX_VEX_DF) }, | |
6376 | /* e0 */ | |
6377 | { PREFIX_TABLE (PREFIX_VEX_E0) }, | |
6378 | { PREFIX_TABLE (PREFIX_VEX_E1) }, | |
6379 | { PREFIX_TABLE (PREFIX_VEX_E2) }, | |
6380 | { PREFIX_TABLE (PREFIX_VEX_E3) }, | |
6381 | { PREFIX_TABLE (PREFIX_VEX_E4) }, | |
6382 | { PREFIX_TABLE (PREFIX_VEX_E5) }, | |
6383 | { PREFIX_TABLE (PREFIX_VEX_E6) }, | |
6384 | { PREFIX_TABLE (PREFIX_VEX_E7) }, | |
6385 | /* e8 */ | |
6386 | { PREFIX_TABLE (PREFIX_VEX_E8) }, | |
6387 | { PREFIX_TABLE (PREFIX_VEX_E9) }, | |
6388 | { PREFIX_TABLE (PREFIX_VEX_EA) }, | |
6389 | { PREFIX_TABLE (PREFIX_VEX_EB) }, | |
6390 | { PREFIX_TABLE (PREFIX_VEX_EC) }, | |
6391 | { PREFIX_TABLE (PREFIX_VEX_ED) }, | |
6392 | { PREFIX_TABLE (PREFIX_VEX_EE) }, | |
6393 | { PREFIX_TABLE (PREFIX_VEX_EF) }, | |
6394 | /* f0 */ | |
6395 | { PREFIX_TABLE (PREFIX_VEX_F0) }, | |
6396 | { PREFIX_TABLE (PREFIX_VEX_F1) }, | |
6397 | { PREFIX_TABLE (PREFIX_VEX_F2) }, | |
6398 | { PREFIX_TABLE (PREFIX_VEX_F3) }, | |
6399 | { PREFIX_TABLE (PREFIX_VEX_F4) }, | |
6400 | { PREFIX_TABLE (PREFIX_VEX_F5) }, | |
6401 | { PREFIX_TABLE (PREFIX_VEX_F6) }, | |
6402 | { PREFIX_TABLE (PREFIX_VEX_F7) }, | |
6403 | /* f8 */ | |
6404 | { PREFIX_TABLE (PREFIX_VEX_F8) }, | |
6405 | { PREFIX_TABLE (PREFIX_VEX_F9) }, | |
6406 | { PREFIX_TABLE (PREFIX_VEX_FA) }, | |
6407 | { PREFIX_TABLE (PREFIX_VEX_FB) }, | |
6408 | { PREFIX_TABLE (PREFIX_VEX_FC) }, | |
6409 | { PREFIX_TABLE (PREFIX_VEX_FD) }, | |
6410 | { PREFIX_TABLE (PREFIX_VEX_FE) }, | |
d5d7db8e | 6411 | { "(bad)", { XX } }, |
c0f3af97 L |
6412 | }, |
6413 | /* VEX_0F38 */ | |
6414 | { | |
6415 | /* 00 */ | |
6416 | { PREFIX_TABLE (PREFIX_VEX_3800) }, | |
6417 | { PREFIX_TABLE (PREFIX_VEX_3801) }, | |
6418 | { PREFIX_TABLE (PREFIX_VEX_3802) }, | |
6419 | { PREFIX_TABLE (PREFIX_VEX_3803) }, | |
6420 | { PREFIX_TABLE (PREFIX_VEX_3804) }, | |
6421 | { PREFIX_TABLE (PREFIX_VEX_3805) }, | |
6422 | { PREFIX_TABLE (PREFIX_VEX_3806) }, | |
6423 | { PREFIX_TABLE (PREFIX_VEX_3807) }, | |
6424 | /* 08 */ | |
6425 | { PREFIX_TABLE (PREFIX_VEX_3808) }, | |
6426 | { PREFIX_TABLE (PREFIX_VEX_3809) }, | |
6427 | { PREFIX_TABLE (PREFIX_VEX_380A) }, | |
6428 | { PREFIX_TABLE (PREFIX_VEX_380B) }, | |
6429 | { PREFIX_TABLE (PREFIX_VEX_380C) }, | |
6430 | { PREFIX_TABLE (PREFIX_VEX_380D) }, | |
6431 | { PREFIX_TABLE (PREFIX_VEX_380E) }, | |
6432 | { PREFIX_TABLE (PREFIX_VEX_380F) }, | |
6433 | /* 10 */ | |
d5d7db8e L |
6434 | { "(bad)", { XX } }, |
6435 | { "(bad)", { XX } }, | |
6436 | { "(bad)", { XX } }, | |
6437 | { "(bad)", { XX } }, | |
d5d7db8e L |
6438 | { "(bad)", { XX } }, |
6439 | { "(bad)", { XX } }, | |
6440 | { "(bad)", { XX } }, | |
c0f3af97 L |
6441 | { PREFIX_TABLE (PREFIX_VEX_3817) }, |
6442 | /* 18 */ | |
6443 | { PREFIX_TABLE (PREFIX_VEX_3818) }, | |
6444 | { PREFIX_TABLE (PREFIX_VEX_3819) }, | |
6445 | { PREFIX_TABLE (PREFIX_VEX_381A) }, | |
d5d7db8e | 6446 | { "(bad)", { XX } }, |
c0f3af97 L |
6447 | { PREFIX_TABLE (PREFIX_VEX_381C) }, |
6448 | { PREFIX_TABLE (PREFIX_VEX_381D) }, | |
6449 | { PREFIX_TABLE (PREFIX_VEX_381E) }, | |
d5d7db8e | 6450 | { "(bad)", { XX } }, |
c0f3af97 L |
6451 | /* 20 */ |
6452 | { PREFIX_TABLE (PREFIX_VEX_3820) }, | |
6453 | { PREFIX_TABLE (PREFIX_VEX_3821) }, | |
6454 | { PREFIX_TABLE (PREFIX_VEX_3822) }, | |
6455 | { PREFIX_TABLE (PREFIX_VEX_3823) }, | |
6456 | { PREFIX_TABLE (PREFIX_VEX_3824) }, | |
6457 | { PREFIX_TABLE (PREFIX_VEX_3825) }, | |
d5d7db8e L |
6458 | { "(bad)", { XX } }, |
6459 | { "(bad)", { XX } }, | |
c0f3af97 L |
6460 | /* 28 */ |
6461 | { PREFIX_TABLE (PREFIX_VEX_3828) }, | |
6462 | { PREFIX_TABLE (PREFIX_VEX_3829) }, | |
6463 | { PREFIX_TABLE (PREFIX_VEX_382A) }, | |
6464 | { PREFIX_TABLE (PREFIX_VEX_382B) }, | |
6465 | { PREFIX_TABLE (PREFIX_VEX_382C) }, | |
6466 | { PREFIX_TABLE (PREFIX_VEX_382D) }, | |
6467 | { PREFIX_TABLE (PREFIX_VEX_382E) }, | |
6468 | { PREFIX_TABLE (PREFIX_VEX_382F) }, | |
6469 | /* 30 */ | |
6470 | { PREFIX_TABLE (PREFIX_VEX_3830) }, | |
6471 | { PREFIX_TABLE (PREFIX_VEX_3831) }, | |
6472 | { PREFIX_TABLE (PREFIX_VEX_3832) }, | |
6473 | { PREFIX_TABLE (PREFIX_VEX_3833) }, | |
6474 | { PREFIX_TABLE (PREFIX_VEX_3834) }, | |
6475 | { PREFIX_TABLE (PREFIX_VEX_3835) }, | |
6476 | { "(bad)", { XX } }, | |
6477 | { PREFIX_TABLE (PREFIX_VEX_3837) }, | |
6478 | /* 38 */ | |
6479 | { PREFIX_TABLE (PREFIX_VEX_3838) }, | |
6480 | { PREFIX_TABLE (PREFIX_VEX_3839) }, | |
6481 | { PREFIX_TABLE (PREFIX_VEX_383A) }, | |
6482 | { PREFIX_TABLE (PREFIX_VEX_383B) }, | |
6483 | { PREFIX_TABLE (PREFIX_VEX_383C) }, | |
6484 | { PREFIX_TABLE (PREFIX_VEX_383D) }, | |
6485 | { PREFIX_TABLE (PREFIX_VEX_383E) }, | |
6486 | { PREFIX_TABLE (PREFIX_VEX_383F) }, | |
6487 | /* 40 */ | |
6488 | { PREFIX_TABLE (PREFIX_VEX_3840) }, | |
6489 | { PREFIX_TABLE (PREFIX_VEX_3841) }, | |
d5d7db8e | 6490 | { "(bad)", { XX } }, |
d5d7db8e L |
6491 | { "(bad)", { XX } }, |
6492 | { "(bad)", { XX } }, | |
6493 | { "(bad)", { XX } }, | |
6494 | { "(bad)", { XX } }, | |
6495 | { "(bad)", { XX } }, | |
c0f3af97 | 6496 | /* 48 */ |
d5d7db8e L |
6497 | { "(bad)", { XX } }, |
6498 | { "(bad)", { XX } }, | |
6499 | { "(bad)", { XX } }, | |
d5d7db8e L |
6500 | { "(bad)", { XX } }, |
6501 | { "(bad)", { XX } }, | |
6502 | { "(bad)", { XX } }, | |
6503 | { "(bad)", { XX } }, | |
6504 | { "(bad)", { XX } }, | |
c0f3af97 | 6505 | /* 50 */ |
d5d7db8e L |
6506 | { "(bad)", { XX } }, |
6507 | { "(bad)", { XX } }, | |
6508 | { "(bad)", { XX } }, | |
d5d7db8e L |
6509 | { "(bad)", { XX } }, |
6510 | { "(bad)", { XX } }, | |
6511 | { "(bad)", { XX } }, | |
6512 | { "(bad)", { XX } }, | |
6513 | { "(bad)", { XX } }, | |
c0f3af97 | 6514 | /* 58 */ |
d5d7db8e L |
6515 | { "(bad)", { XX } }, |
6516 | { "(bad)", { XX } }, | |
6517 | { "(bad)", { XX } }, | |
d5d7db8e L |
6518 | { "(bad)", { XX } }, |
6519 | { "(bad)", { XX } }, | |
6520 | { "(bad)", { XX } }, | |
6521 | { "(bad)", { XX } }, | |
6522 | { "(bad)", { XX } }, | |
c0f3af97 | 6523 | /* 60 */ |
d5d7db8e L |
6524 | { "(bad)", { XX } }, |
6525 | { "(bad)", { XX } }, | |
6526 | { "(bad)", { XX } }, | |
d5d7db8e L |
6527 | { "(bad)", { XX } }, |
6528 | { "(bad)", { XX } }, | |
6529 | { "(bad)", { XX } }, | |
6530 | { "(bad)", { XX } }, | |
6531 | { "(bad)", { XX } }, | |
c0f3af97 | 6532 | /* 68 */ |
d5d7db8e L |
6533 | { "(bad)", { XX } }, |
6534 | { "(bad)", { XX } }, | |
6535 | { "(bad)", { XX } }, | |
d5d7db8e L |
6536 | { "(bad)", { XX } }, |
6537 | { "(bad)", { XX } }, | |
6538 | { "(bad)", { XX } }, | |
6539 | { "(bad)", { XX } }, | |
6540 | { "(bad)", { XX } }, | |
c0f3af97 | 6541 | /* 70 */ |
d5d7db8e L |
6542 | { "(bad)", { XX } }, |
6543 | { "(bad)", { XX } }, | |
6544 | { "(bad)", { XX } }, | |
d5d7db8e L |
6545 | { "(bad)", { XX } }, |
6546 | { "(bad)", { XX } }, | |
6547 | { "(bad)", { XX } }, | |
6548 | { "(bad)", { XX } }, | |
6549 | { "(bad)", { XX } }, | |
c0f3af97 | 6550 | /* 78 */ |
d5d7db8e L |
6551 | { "(bad)", { XX } }, |
6552 | { "(bad)", { XX } }, | |
6553 | { "(bad)", { XX } }, | |
d5d7db8e L |
6554 | { "(bad)", { XX } }, |
6555 | { "(bad)", { XX } }, | |
6556 | { "(bad)", { XX } }, | |
6557 | { "(bad)", { XX } }, | |
6558 | { "(bad)", { XX } }, | |
c0f3af97 | 6559 | /* 80 */ |
d5d7db8e L |
6560 | { "(bad)", { XX } }, |
6561 | { "(bad)", { XX } }, | |
6562 | { "(bad)", { XX } }, | |
d5d7db8e L |
6563 | { "(bad)", { XX } }, |
6564 | { "(bad)", { XX } }, | |
6565 | { "(bad)", { XX } }, | |
6566 | { "(bad)", { XX } }, | |
6567 | { "(bad)", { XX } }, | |
c0f3af97 | 6568 | /* 88 */ |
d5d7db8e L |
6569 | { "(bad)", { XX } }, |
6570 | { "(bad)", { XX } }, | |
6571 | { "(bad)", { XX } }, | |
d5d7db8e L |
6572 | { "(bad)", { XX } }, |
6573 | { "(bad)", { XX } }, | |
6574 | { "(bad)", { XX } }, | |
6575 | { "(bad)", { XX } }, | |
6576 | { "(bad)", { XX } }, | |
c0f3af97 | 6577 | /* 90 */ |
d5d7db8e L |
6578 | { "(bad)", { XX } }, |
6579 | { "(bad)", { XX } }, | |
6580 | { "(bad)", { XX } }, | |
d5d7db8e L |
6581 | { "(bad)", { XX } }, |
6582 | { "(bad)", { XX } }, | |
6583 | { "(bad)", { XX } }, | |
0bfee649 L |
6584 | { PREFIX_TABLE (PREFIX_VEX_3896) }, |
6585 | { PREFIX_TABLE (PREFIX_VEX_3897) }, | |
c0f3af97 | 6586 | /* 98 */ |
0bfee649 L |
6587 | { PREFIX_TABLE (PREFIX_VEX_3898) }, |
6588 | { PREFIX_TABLE (PREFIX_VEX_3899) }, | |
6589 | { PREFIX_TABLE (PREFIX_VEX_389A) }, | |
6590 | { PREFIX_TABLE (PREFIX_VEX_389B) }, | |
6591 | { PREFIX_TABLE (PREFIX_VEX_389C) }, | |
6592 | { PREFIX_TABLE (PREFIX_VEX_389D) }, | |
6593 | { PREFIX_TABLE (PREFIX_VEX_389E) }, | |
6594 | { PREFIX_TABLE (PREFIX_VEX_389F) }, | |
c0f3af97 | 6595 | /* a0 */ |
d5d7db8e L |
6596 | { "(bad)", { XX } }, |
6597 | { "(bad)", { XX } }, | |
6598 | { "(bad)", { XX } }, | |
d5d7db8e L |
6599 | { "(bad)", { XX } }, |
6600 | { "(bad)", { XX } }, | |
6601 | { "(bad)", { XX } }, | |
0bfee649 L |
6602 | { PREFIX_TABLE (PREFIX_VEX_38A6) }, |
6603 | { PREFIX_TABLE (PREFIX_VEX_38A7) }, | |
c0f3af97 | 6604 | /* a8 */ |
0bfee649 L |
6605 | { PREFIX_TABLE (PREFIX_VEX_38A8) }, |
6606 | { PREFIX_TABLE (PREFIX_VEX_38A9) }, | |
6607 | { PREFIX_TABLE (PREFIX_VEX_38AA) }, | |
6608 | { PREFIX_TABLE (PREFIX_VEX_38AB) }, | |
6609 | { PREFIX_TABLE (PREFIX_VEX_38AC) }, | |
6610 | { PREFIX_TABLE (PREFIX_VEX_38AD) }, | |
6611 | { PREFIX_TABLE (PREFIX_VEX_38AE) }, | |
6612 | { PREFIX_TABLE (PREFIX_VEX_38AF) }, | |
c0f3af97 | 6613 | /* b0 */ |
d5d7db8e L |
6614 | { "(bad)", { XX } }, |
6615 | { "(bad)", { XX } }, | |
6616 | { "(bad)", { XX } }, | |
6617 | { "(bad)", { XX } }, | |
6618 | { "(bad)", { XX } }, | |
6619 | { "(bad)", { XX } }, | |
0bfee649 L |
6620 | { PREFIX_TABLE (PREFIX_VEX_38B6) }, |
6621 | { PREFIX_TABLE (PREFIX_VEX_38B7) }, | |
c0f3af97 | 6622 | /* b8 */ |
0bfee649 L |
6623 | { PREFIX_TABLE (PREFIX_VEX_38B8) }, |
6624 | { PREFIX_TABLE (PREFIX_VEX_38B9) }, | |
6625 | { PREFIX_TABLE (PREFIX_VEX_38BA) }, | |
6626 | { PREFIX_TABLE (PREFIX_VEX_38BB) }, | |
6627 | { PREFIX_TABLE (PREFIX_VEX_38BC) }, | |
6628 | { PREFIX_TABLE (PREFIX_VEX_38BD) }, | |
6629 | { PREFIX_TABLE (PREFIX_VEX_38BE) }, | |
6630 | { PREFIX_TABLE (PREFIX_VEX_38BF) }, | |
c0f3af97 | 6631 | /* c0 */ |
d5d7db8e L |
6632 | { "(bad)", { XX } }, |
6633 | { "(bad)", { XX } }, | |
6634 | { "(bad)", { XX } }, | |
6635 | { "(bad)", { XX } }, | |
d5d7db8e L |
6636 | { "(bad)", { XX } }, |
6637 | { "(bad)", { XX } }, | |
6638 | { "(bad)", { XX } }, | |
6639 | { "(bad)", { XX } }, | |
c0f3af97 | 6640 | /* c8 */ |
d5d7db8e L |
6641 | { "(bad)", { XX } }, |
6642 | { "(bad)", { XX } }, | |
6643 | { "(bad)", { XX } }, | |
6644 | { "(bad)", { XX } }, | |
d5d7db8e | 6645 | { "(bad)", { XX } }, |
d5d7db8e L |
6646 | { "(bad)", { XX } }, |
6647 | { "(bad)", { XX } }, | |
d5d7db8e | 6648 | { "(bad)", { XX } }, |
c0f3af97 | 6649 | /* d0 */ |
d5d7db8e L |
6650 | { "(bad)", { XX } }, |
6651 | { "(bad)", { XX } }, | |
d5d7db8e L |
6652 | { "(bad)", { XX } }, |
6653 | { "(bad)", { XX } }, | |
6654 | { "(bad)", { XX } }, | |
6655 | { "(bad)", { XX } }, | |
d5d7db8e | 6656 | { "(bad)", { XX } }, |
d5d7db8e | 6657 | { "(bad)", { XX } }, |
c0f3af97 | 6658 | /* d8 */ |
d5d7db8e | 6659 | { "(bad)", { XX } }, |
d5d7db8e L |
6660 | { "(bad)", { XX } }, |
6661 | { "(bad)", { XX } }, | |
a5ff0eb2 L |
6662 | { PREFIX_TABLE (PREFIX_VEX_38DB) }, |
6663 | { PREFIX_TABLE (PREFIX_VEX_38DC) }, | |
6664 | { PREFIX_TABLE (PREFIX_VEX_38DD) }, | |
6665 | { PREFIX_TABLE (PREFIX_VEX_38DE) }, | |
6666 | { PREFIX_TABLE (PREFIX_VEX_38DF) }, | |
c0f3af97 | 6667 | /* e0 */ |
d5d7db8e | 6668 | { "(bad)", { XX } }, |
d5d7db8e L |
6669 | { "(bad)", { XX } }, |
6670 | { "(bad)", { XX } }, | |
6671 | { "(bad)", { XX } }, | |
6672 | { "(bad)", { XX } }, | |
d5d7db8e L |
6673 | { "(bad)", { XX } }, |
6674 | { "(bad)", { XX } }, | |
6675 | { "(bad)", { XX } }, | |
c0f3af97 | 6676 | /* e8 */ |
d5d7db8e L |
6677 | { "(bad)", { XX } }, |
6678 | { "(bad)", { XX } }, | |
6679 | { "(bad)", { XX } }, | |
6680 | { "(bad)", { XX } }, | |
6681 | { "(bad)", { XX } }, | |
d5d7db8e L |
6682 | { "(bad)", { XX } }, |
6683 | { "(bad)", { XX } }, | |
6684 | { "(bad)", { XX } }, | |
c0f3af97 | 6685 | /* f0 */ |
d5d7db8e L |
6686 | { "(bad)", { XX } }, |
6687 | { "(bad)", { XX } }, | |
6688 | { "(bad)", { XX } }, | |
6689 | { "(bad)", { XX } }, | |
6690 | { "(bad)", { XX } }, | |
d5d7db8e L |
6691 | { "(bad)", { XX } }, |
6692 | { "(bad)", { XX } }, | |
6693 | { "(bad)", { XX } }, | |
c0f3af97 | 6694 | /* f8 */ |
d5d7db8e L |
6695 | { "(bad)", { XX } }, |
6696 | { "(bad)", { XX } }, | |
6697 | { "(bad)", { XX } }, | |
6698 | { "(bad)", { XX } }, | |
6699 | { "(bad)", { XX } }, | |
d5d7db8e L |
6700 | { "(bad)", { XX } }, |
6701 | { "(bad)", { XX } }, | |
6702 | { "(bad)", { XX } }, | |
c0f3af97 L |
6703 | }, |
6704 | /* VEX_0F3A */ | |
6705 | { | |
6706 | /* 00 */ | |
d5d7db8e L |
6707 | { "(bad)", { XX } }, |
6708 | { "(bad)", { XX } }, | |
6709 | { "(bad)", { XX } }, | |
6710 | { "(bad)", { XX } }, | |
c0f3af97 L |
6711 | { PREFIX_TABLE (PREFIX_VEX_3A04) }, |
6712 | { PREFIX_TABLE (PREFIX_VEX_3A05) }, | |
6713 | { PREFIX_TABLE (PREFIX_VEX_3A06) }, | |
d5d7db8e | 6714 | { "(bad)", { XX } }, |
c0f3af97 L |
6715 | /* 08 */ |
6716 | { PREFIX_TABLE (PREFIX_VEX_3A08) }, | |
6717 | { PREFIX_TABLE (PREFIX_VEX_3A09) }, | |
6718 | { PREFIX_TABLE (PREFIX_VEX_3A0A) }, | |
6719 | { PREFIX_TABLE (PREFIX_VEX_3A0B) }, | |
6720 | { PREFIX_TABLE (PREFIX_VEX_3A0C) }, | |
6721 | { PREFIX_TABLE (PREFIX_VEX_3A0D) }, | |
6722 | { PREFIX_TABLE (PREFIX_VEX_3A0E) }, | |
6723 | { PREFIX_TABLE (PREFIX_VEX_3A0F) }, | |
6724 | /* 10 */ | |
d5d7db8e L |
6725 | { "(bad)", { XX } }, |
6726 | { "(bad)", { XX } }, | |
6727 | { "(bad)", { XX } }, | |
6728 | { "(bad)", { XX } }, | |
c0f3af97 L |
6729 | { PREFIX_TABLE (PREFIX_VEX_3A14) }, |
6730 | { PREFIX_TABLE (PREFIX_VEX_3A15) }, | |
6731 | { PREFIX_TABLE (PREFIX_VEX_3A16) }, | |
6732 | { PREFIX_TABLE (PREFIX_VEX_3A17) }, | |
6733 | /* 18 */ | |
6734 | { PREFIX_TABLE (PREFIX_VEX_3A18) }, | |
6735 | { PREFIX_TABLE (PREFIX_VEX_3A19) }, | |
d5d7db8e L |
6736 | { "(bad)", { XX } }, |
6737 | { "(bad)", { XX } }, | |
6738 | { "(bad)", { XX } }, | |
6739 | { "(bad)", { XX } }, | |
d5d7db8e L |
6740 | { "(bad)", { XX } }, |
6741 | { "(bad)", { XX } }, | |
c0f3af97 L |
6742 | /* 20 */ |
6743 | { PREFIX_TABLE (PREFIX_VEX_3A20) }, | |
6744 | { PREFIX_TABLE (PREFIX_VEX_3A21) }, | |
6745 | { PREFIX_TABLE (PREFIX_VEX_3A22) }, | |
d5d7db8e L |
6746 | { "(bad)", { XX } }, |
6747 | { "(bad)", { XX } }, | |
6748 | { "(bad)", { XX } }, | |
6749 | { "(bad)", { XX } }, | |
6750 | { "(bad)", { XX } }, | |
c0f3af97 | 6751 | /* 28 */ |
d5d7db8e | 6752 | { "(bad)", { XX } }, |
d5d7db8e L |
6753 | { "(bad)", { XX } }, |
6754 | { "(bad)", { XX } }, | |
6755 | { "(bad)", { XX } }, | |
6756 | { "(bad)", { XX } }, | |
6757 | { "(bad)", { XX } }, | |
6758 | { "(bad)", { XX } }, | |
6759 | { "(bad)", { XX } }, | |
c0f3af97 | 6760 | /* 30 */ |
d5d7db8e | 6761 | { "(bad)", { XX } }, |
d5d7db8e L |
6762 | { "(bad)", { XX } }, |
6763 | { "(bad)", { XX } }, | |
6764 | { "(bad)", { XX } }, | |
6765 | { "(bad)", { XX } }, | |
6766 | { "(bad)", { XX } }, | |
6767 | { "(bad)", { XX } }, | |
6768 | { "(bad)", { XX } }, | |
c0f3af97 | 6769 | /* 38 */ |
d5d7db8e | 6770 | { "(bad)", { XX } }, |
d5d7db8e L |
6771 | { "(bad)", { XX } }, |
6772 | { "(bad)", { XX } }, | |
6773 | { "(bad)", { XX } }, | |
6774 | { "(bad)", { XX } }, | |
6775 | { "(bad)", { XX } }, | |
6776 | { "(bad)", { XX } }, | |
6777 | { "(bad)", { XX } }, | |
c0f3af97 L |
6778 | /* 40 */ |
6779 | { PREFIX_TABLE (PREFIX_VEX_3A40) }, | |
6780 | { PREFIX_TABLE (PREFIX_VEX_3A41) }, | |
6781 | { PREFIX_TABLE (PREFIX_VEX_3A42) }, | |
d5d7db8e | 6782 | { "(bad)", { XX } }, |
ce2f5b3c | 6783 | { PREFIX_TABLE (PREFIX_VEX_3A44) }, |
d5d7db8e L |
6784 | { "(bad)", { XX } }, |
6785 | { "(bad)", { XX } }, | |
6786 | { "(bad)", { XX } }, | |
c0f3af97 | 6787 | /* 48 */ |
0bfee649 L |
6788 | { "(bad)", { XX } }, |
6789 | { "(bad)", { XX } }, | |
c0f3af97 L |
6790 | { PREFIX_TABLE (PREFIX_VEX_3A4A) }, |
6791 | { PREFIX_TABLE (PREFIX_VEX_3A4B) }, | |
6792 | { PREFIX_TABLE (PREFIX_VEX_3A4C) }, | |
d5d7db8e L |
6793 | { "(bad)", { XX } }, |
6794 | { "(bad)", { XX } }, | |
6795 | { "(bad)", { XX } }, | |
c0f3af97 | 6796 | /* 50 */ |
d5d7db8e | 6797 | { "(bad)", { XX } }, |
d5d7db8e L |
6798 | { "(bad)", { XX } }, |
6799 | { "(bad)", { XX } }, | |
6800 | { "(bad)", { XX } }, | |
6801 | { "(bad)", { XX } }, | |
6802 | { "(bad)", { XX } }, | |
6803 | { "(bad)", { XX } }, | |
6804 | { "(bad)", { XX } }, | |
c0f3af97 | 6805 | /* 58 */ |
d5d7db8e | 6806 | { "(bad)", { XX } }, |
d5d7db8e L |
6807 | { "(bad)", { XX } }, |
6808 | { "(bad)", { XX } }, | |
6809 | { "(bad)", { XX } }, | |
0bfee649 L |
6810 | { "(bad)", { XX } }, |
6811 | { "(bad)", { XX } }, | |
6812 | { "(bad)", { XX } }, | |
6813 | { "(bad)", { XX } }, | |
c0f3af97 L |
6814 | /* 60 */ |
6815 | { PREFIX_TABLE (PREFIX_VEX_3A60) }, | |
6816 | { PREFIX_TABLE (PREFIX_VEX_3A61) }, | |
6817 | { PREFIX_TABLE (PREFIX_VEX_3A62) }, | |
6818 | { PREFIX_TABLE (PREFIX_VEX_3A63) }, | |
d5d7db8e L |
6819 | { "(bad)", { XX } }, |
6820 | { "(bad)", { XX } }, | |
6821 | { "(bad)", { XX } }, | |
6822 | { "(bad)", { XX } }, | |
c0f3af97 | 6823 | /* 68 */ |
0bfee649 L |
6824 | { "(bad)", { XX } }, |
6825 | { "(bad)", { XX } }, | |
6826 | { "(bad)", { XX } }, | |
6827 | { "(bad)", { XX } }, | |
6828 | { "(bad)", { XX } }, | |
6829 | { "(bad)", { XX } }, | |
6830 | { "(bad)", { XX } }, | |
6831 | { "(bad)", { XX } }, | |
c0f3af97 | 6832 | /* 70 */ |
d5d7db8e | 6833 | { "(bad)", { XX } }, |
d5d7db8e L |
6834 | { "(bad)", { XX } }, |
6835 | { "(bad)", { XX } }, | |
6836 | { "(bad)", { XX } }, | |
6837 | { "(bad)", { XX } }, | |
6838 | { "(bad)", { XX } }, | |
6839 | { "(bad)", { XX } }, | |
6840 | { "(bad)", { XX } }, | |
c0f3af97 | 6841 | /* 78 */ |
0bfee649 L |
6842 | { "(bad)", { XX } }, |
6843 | { "(bad)", { XX } }, | |
6844 | { "(bad)", { XX } }, | |
6845 | { "(bad)", { XX } }, | |
6846 | { "(bad)", { XX } }, | |
6847 | { "(bad)", { XX } }, | |
6848 | { "(bad)", { XX } }, | |
6849 | { "(bad)", { XX } }, | |
c0f3af97 | 6850 | /* 80 */ |
d5d7db8e | 6851 | { "(bad)", { XX } }, |
d5d7db8e L |
6852 | { "(bad)", { XX } }, |
6853 | { "(bad)", { XX } }, | |
6854 | { "(bad)", { XX } }, | |
6855 | { "(bad)", { XX } }, | |
6856 | { "(bad)", { XX } }, | |
6857 | { "(bad)", { XX } }, | |
6858 | { "(bad)", { XX } }, | |
c0f3af97 | 6859 | /* 88 */ |
d5d7db8e | 6860 | { "(bad)", { XX } }, |
d5d7db8e L |
6861 | { "(bad)", { XX } }, |
6862 | { "(bad)", { XX } }, | |
6863 | { "(bad)", { XX } }, | |
6864 | { "(bad)", { XX } }, | |
6865 | { "(bad)", { XX } }, | |
6866 | { "(bad)", { XX } }, | |
6867 | { "(bad)", { XX } }, | |
c0f3af97 | 6868 | /* 90 */ |
d5d7db8e | 6869 | { "(bad)", { XX } }, |
d5d7db8e L |
6870 | { "(bad)", { XX } }, |
6871 | { "(bad)", { XX } }, | |
6872 | { "(bad)", { XX } }, | |
6873 | { "(bad)", { XX } }, | |
6874 | { "(bad)", { XX } }, | |
6875 | { "(bad)", { XX } }, | |
6876 | { "(bad)", { XX } }, | |
c0f3af97 | 6877 | /* 98 */ |
d5d7db8e | 6878 | { "(bad)", { XX } }, |
d5d7db8e L |
6879 | { "(bad)", { XX } }, |
6880 | { "(bad)", { XX } }, | |
6881 | { "(bad)", { XX } }, | |
6882 | { "(bad)", { XX } }, | |
6883 | { "(bad)", { XX } }, | |
6884 | { "(bad)", { XX } }, | |
6885 | { "(bad)", { XX } }, | |
c0f3af97 | 6886 | /* a0 */ |
d5d7db8e | 6887 | { "(bad)", { XX } }, |
85f10a01 MM |
6888 | { "(bad)", { XX } }, |
6889 | { "(bad)", { XX } }, | |
d5d7db8e L |
6890 | { "(bad)", { XX } }, |
6891 | { "(bad)", { XX } }, | |
6892 | { "(bad)", { XX } }, | |
6893 | { "(bad)", { XX } }, | |
6894 | { "(bad)", { XX } }, | |
c0f3af97 | 6895 | /* a8 */ |
d5d7db8e | 6896 | { "(bad)", { XX } }, |
d5d7db8e L |
6897 | { "(bad)", { XX } }, |
6898 | { "(bad)", { XX } }, | |
6899 | { "(bad)", { XX } }, | |
6900 | { "(bad)", { XX } }, | |
6901 | { "(bad)", { XX } }, | |
6902 | { "(bad)", { XX } }, | |
6903 | { "(bad)", { XX } }, | |
c0f3af97 L |
6904 | /* b0 */ |
6905 | { "(bad)", { XX } }, | |
6906 | { "(bad)", { XX } }, | |
6907 | { "(bad)", { XX } }, | |
6908 | { "(bad)", { XX } }, | |
6909 | { "(bad)", { XX } }, | |
6910 | { "(bad)", { XX } }, | |
6911 | { "(bad)", { XX } }, | |
6912 | { "(bad)", { XX } }, | |
6913 | /* b8 */ | |
6914 | { "(bad)", { XX } }, | |
6915 | { "(bad)", { XX } }, | |
6916 | { "(bad)", { XX } }, | |
6917 | { "(bad)", { XX } }, | |
6918 | { "(bad)", { XX } }, | |
6919 | { "(bad)", { XX } }, | |
6920 | { "(bad)", { XX } }, | |
6921 | { "(bad)", { XX } }, | |
6922 | /* c0 */ | |
6923 | { "(bad)", { XX } }, | |
6924 | { "(bad)", { XX } }, | |
6925 | { "(bad)", { XX } }, | |
6926 | { "(bad)", { XX } }, | |
6927 | { "(bad)", { XX } }, | |
6928 | { "(bad)", { XX } }, | |
6929 | { "(bad)", { XX } }, | |
6930 | { "(bad)", { XX } }, | |
6931 | /* c8 */ | |
6932 | { "(bad)", { XX } }, | |
6933 | { "(bad)", { XX } }, | |
d5d7db8e | 6934 | { "(bad)", { XX } }, |
d5d7db8e L |
6935 | { "(bad)", { XX } }, |
6936 | { "(bad)", { XX } }, | |
6937 | { "(bad)", { XX } }, | |
6938 | { "(bad)", { XX } }, | |
6939 | { "(bad)", { XX } }, | |
c0f3af97 L |
6940 | /* d0 */ |
6941 | { "(bad)", { XX } }, | |
6942 | { "(bad)", { XX } }, | |
6943 | { "(bad)", { XX } }, | |
d5d7db8e L |
6944 | { "(bad)", { XX } }, |
6945 | { "(bad)", { XX } }, | |
6946 | { "(bad)", { XX } }, | |
c0f3af97 L |
6947 | { "(bad)", { XX } }, |
6948 | { "(bad)", { XX } }, | |
6949 | /* d8 */ | |
6950 | { "(bad)", { XX } }, | |
d5d7db8e L |
6951 | { "(bad)", { XX } }, |
6952 | { "(bad)", { XX } }, | |
6953 | { "(bad)", { XX } }, | |
6954 | { "(bad)", { XX } }, | |
6955 | { "(bad)", { XX } }, | |
6956 | { "(bad)", { XX } }, | |
a5ff0eb2 | 6957 | { PREFIX_TABLE (PREFIX_VEX_3ADF) }, |
c0f3af97 | 6958 | /* e0 */ |
d5d7db8e | 6959 | { "(bad)", { XX } }, |
d5d7db8e L |
6960 | { "(bad)", { XX } }, |
6961 | { "(bad)", { XX } }, | |
6962 | { "(bad)", { XX } }, | |
6963 | { "(bad)", { XX } }, | |
6964 | { "(bad)", { XX } }, | |
6965 | { "(bad)", { XX } }, | |
6966 | { "(bad)", { XX } }, | |
c0f3af97 | 6967 | /* e8 */ |
d5d7db8e | 6968 | { "(bad)", { XX } }, |
d5d7db8e L |
6969 | { "(bad)", { XX } }, |
6970 | { "(bad)", { XX } }, | |
6971 | { "(bad)", { XX } }, | |
6972 | { "(bad)", { XX } }, | |
6973 | { "(bad)", { XX } }, | |
6974 | { "(bad)", { XX } }, | |
6975 | { "(bad)", { XX } }, | |
c0f3af97 | 6976 | /* f0 */ |
d5d7db8e | 6977 | { "(bad)", { XX } }, |
d5d7db8e L |
6978 | { "(bad)", { XX } }, |
6979 | { "(bad)", { XX } }, | |
6980 | { "(bad)", { XX } }, | |
6981 | { "(bad)", { XX } }, | |
6982 | { "(bad)", { XX } }, | |
6983 | { "(bad)", { XX } }, | |
6984 | { "(bad)", { XX } }, | |
c0f3af97 | 6985 | /* f8 */ |
d5d7db8e | 6986 | { "(bad)", { XX } }, |
d5d7db8e L |
6987 | { "(bad)", { XX } }, |
6988 | { "(bad)", { XX } }, | |
6989 | { "(bad)", { XX } }, | |
6990 | { "(bad)", { XX } }, | |
6991 | { "(bad)", { XX } }, | |
6992 | { "(bad)", { XX } }, | |
6993 | { "(bad)", { XX } }, | |
c0f3af97 L |
6994 | }, |
6995 | }; | |
6996 | ||
6997 | static const struct dis386 vex_len_table[][2] = { | |
6998 | /* VEX_LEN_10_P_1 */ | |
6999 | { | |
7000 | { "vmovss", { XMVex, Vex128, EXd } }, | |
d5d7db8e | 7001 | { "(bad)", { XX } }, |
c0f3af97 L |
7002 | }, |
7003 | ||
7004 | /* VEX_LEN_10_P_3 */ | |
7005 | { | |
7006 | { "vmovsd", { XMVex, Vex128, EXq } }, | |
d5d7db8e | 7007 | { "(bad)", { XX } }, |
c0f3af97 L |
7008 | }, |
7009 | ||
7010 | /* VEX_LEN_11_P_1 */ | |
7011 | { | |
fa99fab2 | 7012 | { "vmovss", { EXdVexS, Vex128, XM } }, |
d5d7db8e | 7013 | { "(bad)", { XX } }, |
c0f3af97 L |
7014 | }, |
7015 | ||
7016 | /* VEX_LEN_11_P_3 */ | |
7017 | { | |
fa99fab2 | 7018 | { "vmovsd", { EXqVexS, Vex128, XM } }, |
d5d7db8e | 7019 | { "(bad)", { XX } }, |
c0f3af97 L |
7020 | }, |
7021 | ||
7022 | /* VEX_LEN_12_P_0_M_0 */ | |
7023 | { | |
7024 | { "vmovlps", { XM, Vex128, EXq } }, | |
d5d7db8e | 7025 | { "(bad)", { XX } }, |
c0f3af97 L |
7026 | }, |
7027 | ||
7028 | /* VEX_LEN_12_P_0_M_1 */ | |
7029 | { | |
7030 | { "vmovhlps", { XM, Vex128, EXq } }, | |
d5d7db8e | 7031 | { "(bad)", { XX } }, |
c0f3af97 L |
7032 | }, |
7033 | ||
7034 | /* VEX_LEN_12_P_2 */ | |
7035 | { | |
7036 | { "vmovlpd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7037 | { "(bad)", { XX } }, |
c0f3af97 L |
7038 | }, |
7039 | ||
7040 | /* VEX_LEN_13_M_0 */ | |
7041 | { | |
7042 | { "vmovlpX", { EXq, XM } }, | |
85f10a01 | 7043 | { "(bad)", { XX } }, |
c0f3af97 L |
7044 | }, |
7045 | ||
7046 | /* VEX_LEN_16_P_0_M_0 */ | |
7047 | { | |
7048 | { "vmovhps", { XM, Vex128, EXq } }, | |
85f10a01 | 7049 | { "(bad)", { XX } }, |
c0f3af97 L |
7050 | }, |
7051 | ||
7052 | /* VEX_LEN_16_P_0_M_1 */ | |
7053 | { | |
7054 | { "vmovlhps", { XM, Vex128, EXq } }, | |
85f10a01 | 7055 | { "(bad)", { XX } }, |
c0f3af97 L |
7056 | }, |
7057 | ||
7058 | /* VEX_LEN_16_P_2 */ | |
7059 | { | |
7060 | { "vmovhpd", { XM, Vex128, EXq } }, | |
85f10a01 | 7061 | { "(bad)", { XX } }, |
c0f3af97 L |
7062 | }, |
7063 | ||
7064 | /* VEX_LEN_17_M_0 */ | |
7065 | { | |
7066 | { "vmovhpX", { EXq, XM } }, | |
85f10a01 | 7067 | { "(bad)", { XX } }, |
c0f3af97 L |
7068 | }, |
7069 | ||
7070 | /* VEX_LEN_2A_P_1 */ | |
7071 | { | |
7072 | { "vcvtsi2ss%LQ", { XM, Vex128, Ev } }, | |
d5d7db8e | 7073 | { "(bad)", { XX } }, |
c0f3af97 L |
7074 | }, |
7075 | ||
7076 | /* VEX_LEN_2A_P_3 */ | |
7077 | { | |
7078 | { "vcvtsi2sd%LQ", { XM, Vex128, Ev } }, | |
d5d7db8e | 7079 | { "(bad)", { XX } }, |
c0f3af97 L |
7080 | }, |
7081 | ||
c0f3af97 L |
7082 | /* VEX_LEN_2C_P_1 */ |
7083 | { | |
7084 | { "vcvttss2siY", { Gv, EXd } }, | |
d5d7db8e | 7085 | { "(bad)", { XX } }, |
c0f3af97 L |
7086 | }, |
7087 | ||
7088 | /* VEX_LEN_2C_P_3 */ | |
7089 | { | |
7090 | { "vcvttsd2siY", { Gv, EXq } }, | |
d5d7db8e | 7091 | { "(bad)", { XX } }, |
c0f3af97 L |
7092 | }, |
7093 | ||
7094 | /* VEX_LEN_2D_P_1 */ | |
7095 | { | |
7096 | { "vcvtss2siY", { Gv, EXd } }, | |
85f10a01 | 7097 | { "(bad)", { XX } }, |
c0f3af97 L |
7098 | }, |
7099 | ||
7100 | /* VEX_LEN_2D_P_3 */ | |
7101 | { | |
7102 | { "vcvtsd2siY", { Gv, EXq } }, | |
d5d7db8e | 7103 | { "(bad)", { XX } }, |
c0f3af97 L |
7104 | }, |
7105 | ||
7106 | /* VEX_LEN_2E_P_0 */ | |
7107 | { | |
7108 | { "vucomiss", { XM, EXd } }, | |
d5d7db8e | 7109 | { "(bad)", { XX } }, |
c0f3af97 L |
7110 | }, |
7111 | ||
7112 | /* VEX_LEN_2E_P_2 */ | |
7113 | { | |
7114 | { "vucomisd", { XM, EXq } }, | |
d5d7db8e | 7115 | { "(bad)", { XX } }, |
c0f3af97 L |
7116 | }, |
7117 | ||
7118 | /* VEX_LEN_2F_P_0 */ | |
7119 | { | |
7120 | { "vcomiss", { XM, EXd } }, | |
d5d7db8e | 7121 | { "(bad)", { XX } }, |
c0f3af97 L |
7122 | }, |
7123 | ||
7124 | /* VEX_LEN_2F_P_2 */ | |
7125 | { | |
7126 | { "vcomisd", { XM, EXq } }, | |
d5d7db8e | 7127 | { "(bad)", { XX } }, |
c0f3af97 L |
7128 | }, |
7129 | ||
7130 | /* VEX_LEN_51_P_1 */ | |
7131 | { | |
7132 | { "vsqrtss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7133 | { "(bad)", { XX } }, |
c0f3af97 L |
7134 | }, |
7135 | ||
7136 | /* VEX_LEN_51_P_3 */ | |
7137 | { | |
7138 | { "vsqrtsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7139 | { "(bad)", { XX } }, |
c0f3af97 L |
7140 | }, |
7141 | ||
7142 | /* VEX_LEN_52_P_1 */ | |
7143 | { | |
7144 | { "vrsqrtss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7145 | { "(bad)", { XX } }, |
c0f3af97 L |
7146 | }, |
7147 | ||
7148 | /* VEX_LEN_53_P_1 */ | |
7149 | { | |
7150 | { "vrcpss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7151 | { "(bad)", { XX } }, |
c0f3af97 L |
7152 | }, |
7153 | ||
7154 | /* VEX_LEN_58_P_1 */ | |
7155 | { | |
7156 | { "vaddss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7157 | { "(bad)", { XX } }, |
c0f3af97 L |
7158 | }, |
7159 | ||
7160 | /* VEX_LEN_58_P_3 */ | |
7161 | { | |
7162 | { "vaddsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7163 | { "(bad)", { XX } }, |
c0f3af97 L |
7164 | }, |
7165 | ||
7166 | /* VEX_LEN_59_P_1 */ | |
7167 | { | |
7168 | { "vmulss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7169 | { "(bad)", { XX } }, |
c0f3af97 L |
7170 | }, |
7171 | ||
7172 | /* VEX_LEN_59_P_3 */ | |
7173 | { | |
7174 | { "vmulsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7175 | { "(bad)", { XX } }, |
c0f3af97 L |
7176 | }, |
7177 | ||
7178 | /* VEX_LEN_5A_P_1 */ | |
7179 | { | |
7180 | { "vcvtss2sd", { XM, Vex128, EXd } }, | |
d5d7db8e | 7181 | { "(bad)", { XX } }, |
c0f3af97 L |
7182 | }, |
7183 | ||
7184 | /* VEX_LEN_5A_P_3 */ | |
7185 | { | |
7186 | { "vcvtsd2ss", { XM, Vex128, EXq } }, | |
d5d7db8e | 7187 | { "(bad)", { XX } }, |
c0f3af97 L |
7188 | }, |
7189 | ||
7190 | /* VEX_LEN_5C_P_1 */ | |
7191 | { | |
7192 | { "vsubss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7193 | { "(bad)", { XX } }, |
c0f3af97 L |
7194 | }, |
7195 | ||
7196 | /* VEX_LEN_5C_P_3 */ | |
7197 | { | |
7198 | { "vsubsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7199 | { "(bad)", { XX } }, |
c0f3af97 L |
7200 | }, |
7201 | ||
7202 | /* VEX_LEN_5D_P_1 */ | |
7203 | { | |
7204 | { "vminss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7205 | { "(bad)", { XX } }, |
c0f3af97 L |
7206 | }, |
7207 | ||
7208 | /* VEX_LEN_5D_P_3 */ | |
7209 | { | |
7210 | { "vminsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7211 | { "(bad)", { XX } }, |
c0f3af97 L |
7212 | }, |
7213 | ||
7214 | /* VEX_LEN_5E_P_1 */ | |
7215 | { | |
7216 | { "vdivss", { XM, Vex128, EXd } }, | |
85f10a01 | 7217 | { "(bad)", { XX } }, |
c0f3af97 L |
7218 | }, |
7219 | ||
7220 | /* VEX_LEN_5E_P_3 */ | |
7221 | { | |
7222 | { "vdivsd", { XM, Vex128, EXq } }, | |
85f10a01 | 7223 | { "(bad)", { XX } }, |
c0f3af97 L |
7224 | }, |
7225 | ||
7226 | /* VEX_LEN_5F_P_1 */ | |
7227 | { | |
7228 | { "vmaxss", { XM, Vex128, EXd } }, | |
85f10a01 | 7229 | { "(bad)", { XX } }, |
c0f3af97 L |
7230 | }, |
7231 | ||
7232 | /* VEX_LEN_5F_P_3 */ | |
7233 | { | |
7234 | { "vmaxsd", { XM, Vex128, EXq } }, | |
85f10a01 | 7235 | { "(bad)", { XX } }, |
c0f3af97 L |
7236 | }, |
7237 | ||
7238 | /* VEX_LEN_60_P_2 */ | |
7239 | { | |
7240 | { "vpunpcklbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7241 | { "(bad)", { XX } }, |
c0f3af97 L |
7242 | }, |
7243 | ||
7244 | /* VEX_LEN_61_P_2 */ | |
7245 | { | |
7246 | { "vpunpcklwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7247 | { "(bad)", { XX } }, |
c0f3af97 L |
7248 | }, |
7249 | ||
7250 | /* VEX_LEN_62_P_2 */ | |
7251 | { | |
7252 | { "vpunpckldq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7253 | { "(bad)", { XX } }, |
c0f3af97 L |
7254 | }, |
7255 | ||
7256 | /* VEX_LEN_63_P_2 */ | |
7257 | { | |
7258 | { "vpacksswb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7259 | { "(bad)", { XX } }, |
c0f3af97 L |
7260 | }, |
7261 | ||
7262 | /* VEX_LEN_64_P_2 */ | |
7263 | { | |
7264 | { "vpcmpgtb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7265 | { "(bad)", { XX } }, |
c0f3af97 L |
7266 | }, |
7267 | ||
7268 | /* VEX_LEN_65_P_2 */ | |
7269 | { | |
7270 | { "vpcmpgtw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7271 | { "(bad)", { XX } }, |
c0f3af97 L |
7272 | }, |
7273 | ||
7274 | /* VEX_LEN_66_P_2 */ | |
7275 | { | |
7276 | { "vpcmpgtd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7277 | { "(bad)", { XX } }, |
c0f3af97 L |
7278 | }, |
7279 | ||
7280 | /* VEX_LEN_67_P_2 */ | |
7281 | { | |
7282 | { "vpackuswb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7283 | { "(bad)", { XX } }, |
c0f3af97 L |
7284 | }, |
7285 | ||
7286 | /* VEX_LEN_68_P_2 */ | |
7287 | { | |
7288 | { "vpunpckhbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7289 | { "(bad)", { XX } }, |
c0f3af97 L |
7290 | }, |
7291 | ||
7292 | /* VEX_LEN_69_P_2 */ | |
7293 | { | |
7294 | { "vpunpckhwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7295 | { "(bad)", { XX } }, |
c0f3af97 L |
7296 | }, |
7297 | ||
7298 | /* VEX_LEN_6A_P_2 */ | |
7299 | { | |
7300 | { "vpunpckhdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7301 | { "(bad)", { XX } }, |
c0f3af97 L |
7302 | }, |
7303 | ||
7304 | /* VEX_LEN_6B_P_2 */ | |
7305 | { | |
7306 | { "vpackssdw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7307 | { "(bad)", { XX } }, |
c0f3af97 L |
7308 | }, |
7309 | ||
7310 | /* VEX_LEN_6C_P_2 */ | |
7311 | { | |
7312 | { "vpunpcklqdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7313 | { "(bad)", { XX } }, |
c0f3af97 L |
7314 | }, |
7315 | ||
7316 | /* VEX_LEN_6D_P_2 */ | |
7317 | { | |
7318 | { "vpunpckhqdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7319 | { "(bad)", { XX } }, |
c0f3af97 L |
7320 | }, |
7321 | ||
7322 | /* VEX_LEN_6E_P_2 */ | |
7323 | { | |
7324 | { "vmovK", { XM, Edq } }, | |
d5d7db8e | 7325 | { "(bad)", { XX } }, |
c0f3af97 L |
7326 | }, |
7327 | ||
7328 | /* VEX_LEN_70_P_1 */ | |
7329 | { | |
7330 | { "vpshufhw", { XM, EXx, Ib } }, | |
d5d7db8e | 7331 | { "(bad)", { XX } }, |
c0f3af97 L |
7332 | }, |
7333 | ||
7334 | /* VEX_LEN_70_P_2 */ | |
7335 | { | |
7336 | { "vpshufd", { XM, EXx, Ib } }, | |
d5d7db8e | 7337 | { "(bad)", { XX } }, |
c0f3af97 L |
7338 | }, |
7339 | ||
7340 | /* VEX_LEN_70_P_3 */ | |
7341 | { | |
7342 | { "vpshuflw", { XM, EXx, Ib } }, | |
d5d7db8e | 7343 | { "(bad)", { XX } }, |
c0f3af97 L |
7344 | }, |
7345 | ||
7346 | /* VEX_LEN_71_R_2_P_2 */ | |
7347 | { | |
7348 | { "vpsrlw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7349 | { "(bad)", { XX } }, |
c0f3af97 L |
7350 | }, |
7351 | ||
7352 | /* VEX_LEN_71_R_4_P_2 */ | |
7353 | { | |
7354 | { "vpsraw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7355 | { "(bad)", { XX } }, |
c0f3af97 L |
7356 | }, |
7357 | ||
7358 | /* VEX_LEN_71_R_6_P_2 */ | |
7359 | { | |
7360 | { "vpsllw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7361 | { "(bad)", { XX } }, |
c0f3af97 L |
7362 | }, |
7363 | ||
7364 | /* VEX_LEN_72_R_2_P_2 */ | |
7365 | { | |
7366 | { "vpsrld", { Vex128, XS, Ib } }, | |
d5d7db8e | 7367 | { "(bad)", { XX } }, |
c0f3af97 L |
7368 | }, |
7369 | ||
7370 | /* VEX_LEN_72_R_4_P_2 */ | |
7371 | { | |
7372 | { "vpsrad", { Vex128, XS, Ib } }, | |
d5d7db8e | 7373 | { "(bad)", { XX } }, |
c0f3af97 L |
7374 | }, |
7375 | ||
7376 | /* VEX_LEN_72_R_6_P_2 */ | |
7377 | { | |
7378 | { "vpslld", { Vex128, XS, Ib } }, | |
d5d7db8e | 7379 | { "(bad)", { XX } }, |
c0f3af97 L |
7380 | }, |
7381 | ||
7382 | /* VEX_LEN_73_R_2_P_2 */ | |
7383 | { | |
7384 | { "vpsrlq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7385 | { "(bad)", { XX } }, |
c0f3af97 L |
7386 | }, |
7387 | ||
7388 | /* VEX_LEN_73_R_3_P_2 */ | |
7389 | { | |
7390 | { "vpsrldq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7391 | { "(bad)", { XX } }, |
c0f3af97 L |
7392 | }, |
7393 | ||
7394 | /* VEX_LEN_73_R_6_P_2 */ | |
7395 | { | |
7396 | { "vpsllq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7397 | { "(bad)", { XX } }, |
c0f3af97 L |
7398 | }, |
7399 | ||
7400 | /* VEX_LEN_73_R_7_P_2 */ | |
7401 | { | |
7402 | { "vpslldq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7403 | { "(bad)", { XX } }, |
c0f3af97 L |
7404 | }, |
7405 | ||
7406 | /* VEX_LEN_74_P_2 */ | |
7407 | { | |
7408 | { "vpcmpeqb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7409 | { "(bad)", { XX } }, |
c0f3af97 L |
7410 | }, |
7411 | ||
7412 | /* VEX_LEN_75_P_2 */ | |
7413 | { | |
7414 | { "vpcmpeqw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7415 | { "(bad)", { XX } }, |
c0f3af97 L |
7416 | }, |
7417 | ||
7418 | /* VEX_LEN_76_P_2 */ | |
7419 | { | |
7420 | { "vpcmpeqd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7421 | { "(bad)", { XX } }, |
c0f3af97 L |
7422 | }, |
7423 | ||
7424 | /* VEX_LEN_7E_P_1 */ | |
7425 | { | |
7426 | { "vmovq", { XM, EXq } }, | |
d5d7db8e | 7427 | { "(bad)", { XX } }, |
c0f3af97 L |
7428 | }, |
7429 | ||
7430 | /* VEX_LEN_7E_P_2 */ | |
7431 | { | |
7432 | { "vmovK", { Edq, XM } }, | |
d5d7db8e | 7433 | { "(bad)", { XX } }, |
c0f3af97 L |
7434 | }, |
7435 | ||
7436 | /* VEX_LEN_AE_R_2_M0 */ | |
7437 | { | |
7438 | { "vldmxcsr", { Md } }, | |
d5d7db8e | 7439 | { "(bad)", { XX } }, |
c0f3af97 L |
7440 | }, |
7441 | ||
7442 | /* VEX_LEN_AE_R_3_M0 */ | |
7443 | { | |
7444 | { "vstmxcsr", { Md } }, | |
d5d7db8e | 7445 | { "(bad)", { XX } }, |
c0f3af97 L |
7446 | }, |
7447 | ||
7448 | /* VEX_LEN_C2_P_1 */ | |
7449 | { | |
7450 | { "vcmpss", { XM, Vex128, EXd, VCMP } }, | |
d5d7db8e | 7451 | { "(bad)", { XX } }, |
c0f3af97 L |
7452 | }, |
7453 | ||
7454 | /* VEX_LEN_C2_P_3 */ | |
7455 | { | |
7456 | { "vcmpsd", { XM, Vex128, EXq, VCMP } }, | |
d5d7db8e | 7457 | { "(bad)", { XX } }, |
c0f3af97 L |
7458 | }, |
7459 | ||
7460 | /* VEX_LEN_C4_P_2 */ | |
7461 | { | |
7462 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, | |
d5d7db8e | 7463 | { "(bad)", { XX } }, |
c0f3af97 L |
7464 | }, |
7465 | ||
7466 | /* VEX_LEN_C5_P_2 */ | |
7467 | { | |
7468 | { "vpextrw", { Gdq, XS, Ib } }, | |
d5d7db8e | 7469 | { "(bad)", { XX } }, |
c0f3af97 L |
7470 | }, |
7471 | ||
7472 | /* VEX_LEN_D1_P_2 */ | |
7473 | { | |
7474 | { "vpsrlw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7475 | { "(bad)", { XX } }, |
c0f3af97 L |
7476 | }, |
7477 | ||
7478 | /* VEX_LEN_D2_P_2 */ | |
7479 | { | |
7480 | { "vpsrld", { XM, Vex128, EXx } }, | |
d5d7db8e | 7481 | { "(bad)", { XX } }, |
c0f3af97 L |
7482 | }, |
7483 | ||
7484 | /* VEX_LEN_D3_P_2 */ | |
7485 | { | |
7486 | { "vpsrlq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7487 | { "(bad)", { XX } }, |
c0f3af97 L |
7488 | }, |
7489 | ||
7490 | /* VEX_LEN_D4_P_2 */ | |
7491 | { | |
7492 | { "vpaddq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7493 | { "(bad)", { XX } }, |
c0f3af97 L |
7494 | }, |
7495 | ||
7496 | /* VEX_LEN_D5_P_2 */ | |
7497 | { | |
7498 | { "vpmullw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7499 | { "(bad)", { XX } }, |
c0f3af97 L |
7500 | }, |
7501 | ||
7502 | /* VEX_LEN_D6_P_2 */ | |
7503 | { | |
b6169b20 | 7504 | { "vmovq", { EXqS, XM } }, |
d5d7db8e | 7505 | { "(bad)", { XX } }, |
c0f3af97 L |
7506 | }, |
7507 | ||
7508 | /* VEX_LEN_D7_P_2_M_1 */ | |
7509 | { | |
7510 | { "vpmovmskb", { Gdq, XS } }, | |
d5d7db8e | 7511 | { "(bad)", { XX } }, |
c0f3af97 L |
7512 | }, |
7513 | ||
7514 | /* VEX_LEN_D8_P_2 */ | |
7515 | { | |
7516 | { "vpsubusb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7517 | { "(bad)", { XX } }, |
c0f3af97 L |
7518 | }, |
7519 | ||
7520 | /* VEX_LEN_D9_P_2 */ | |
7521 | { | |
7522 | { "vpsubusw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7523 | { "(bad)", { XX } }, |
c0f3af97 L |
7524 | }, |
7525 | ||
7526 | /* VEX_LEN_DA_P_2 */ | |
7527 | { | |
7528 | { "vpminub", { XM, Vex128, EXx } }, | |
d5d7db8e | 7529 | { "(bad)", { XX } }, |
c0f3af97 L |
7530 | }, |
7531 | ||
7532 | /* VEX_LEN_DB_P_2 */ | |
7533 | { | |
7534 | { "vpand", { XM, Vex128, EXx } }, | |
d5d7db8e | 7535 | { "(bad)", { XX } }, |
c0f3af97 L |
7536 | }, |
7537 | ||
7538 | /* VEX_LEN_DC_P_2 */ | |
7539 | { | |
7540 | { "vpaddusb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7541 | { "(bad)", { XX } }, |
c0f3af97 L |
7542 | }, |
7543 | ||
7544 | /* VEX_LEN_DD_P_2 */ | |
7545 | { | |
7546 | { "vpaddusw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7547 | { "(bad)", { XX } }, |
c0f3af97 L |
7548 | }, |
7549 | ||
7550 | /* VEX_LEN_DE_P_2 */ | |
7551 | { | |
7552 | { "vpmaxub", { XM, Vex128, EXx } }, | |
d5d7db8e | 7553 | { "(bad)", { XX } }, |
c0f3af97 L |
7554 | }, |
7555 | ||
7556 | /* VEX_LEN_DF_P_2 */ | |
7557 | { | |
7558 | { "vpandn", { XM, Vex128, EXx } }, | |
d5d7db8e | 7559 | { "(bad)", { XX } }, |
c0f3af97 L |
7560 | }, |
7561 | ||
7562 | /* VEX_LEN_E0_P_2 */ | |
7563 | { | |
7564 | { "vpavgb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7565 | { "(bad)", { XX } }, |
c0f3af97 L |
7566 | }, |
7567 | ||
7568 | /* VEX_LEN_E1_P_2 */ | |
7569 | { | |
7570 | { "vpsraw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7571 | { "(bad)", { XX } }, |
c0f3af97 L |
7572 | }, |
7573 | ||
7574 | /* VEX_LEN_E2_P_2 */ | |
7575 | { | |
7576 | { "vpsrad", { XM, Vex128, EXx } }, | |
d5d7db8e | 7577 | { "(bad)", { XX } }, |
c0f3af97 L |
7578 | }, |
7579 | ||
7580 | /* VEX_LEN_E3_P_2 */ | |
7581 | { | |
7582 | { "vpavgw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7583 | { "(bad)", { XX } }, |
c0f3af97 L |
7584 | }, |
7585 | ||
7586 | /* VEX_LEN_E4_P_2 */ | |
7587 | { | |
7588 | { "vpmulhuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7589 | { "(bad)", { XX } }, |
c0f3af97 L |
7590 | }, |
7591 | ||
7592 | /* VEX_LEN_E5_P_2 */ | |
7593 | { | |
7594 | { "vpmulhw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7595 | { "(bad)", { XX } }, |
c0f3af97 L |
7596 | }, |
7597 | ||
c0f3af97 L |
7598 | /* VEX_LEN_E8_P_2 */ |
7599 | { | |
7600 | { "vpsubsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7601 | { "(bad)", { XX } }, |
c0f3af97 L |
7602 | }, |
7603 | ||
7604 | /* VEX_LEN_E9_P_2 */ | |
7605 | { | |
7606 | { "vpsubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7607 | { "(bad)", { XX } }, |
c0f3af97 L |
7608 | }, |
7609 | ||
7610 | /* VEX_LEN_EA_P_2 */ | |
7611 | { | |
7612 | { "vpminsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7613 | { "(bad)", { XX } }, |
c0f3af97 L |
7614 | }, |
7615 | ||
7616 | /* VEX_LEN_EB_P_2 */ | |
7617 | { | |
7618 | { "vpor", { XM, Vex128, EXx } }, | |
d5d7db8e | 7619 | { "(bad)", { XX } }, |
c0f3af97 L |
7620 | }, |
7621 | ||
7622 | /* VEX_LEN_EC_P_2 */ | |
7623 | { | |
7624 | { "vpaddsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7625 | { "(bad)", { XX } }, |
c0f3af97 L |
7626 | }, |
7627 | ||
7628 | /* VEX_LEN_ED_P_2 */ | |
7629 | { | |
7630 | { "vpaddsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7631 | { "(bad)", { XX } }, |
c0f3af97 L |
7632 | }, |
7633 | ||
7634 | /* VEX_LEN_EE_P_2 */ | |
7635 | { | |
7636 | { "vpmaxsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7637 | { "(bad)", { XX } }, |
c0f3af97 L |
7638 | }, |
7639 | ||
7640 | /* VEX_LEN_EF_P_2 */ | |
7641 | { | |
7642 | { "vpxor", { XM, Vex128, EXx } }, | |
d5d7db8e | 7643 | { "(bad)", { XX } }, |
c0f3af97 L |
7644 | }, |
7645 | ||
7646 | /* VEX_LEN_F1_P_2 */ | |
7647 | { | |
7648 | { "vpsllw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7649 | { "(bad)", { XX } }, |
c0f3af97 L |
7650 | }, |
7651 | ||
7652 | /* VEX_LEN_F2_P_2 */ | |
7653 | { | |
7654 | { "vpslld", { XM, Vex128, EXx } }, | |
d5d7db8e | 7655 | { "(bad)", { XX } }, |
c0f3af97 L |
7656 | }, |
7657 | ||
7658 | /* VEX_LEN_F3_P_2 */ | |
7659 | { | |
7660 | { "vpsllq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7661 | { "(bad)", { XX } }, |
c0f3af97 L |
7662 | }, |
7663 | ||
7664 | /* VEX_LEN_F4_P_2 */ | |
7665 | { | |
7666 | { "vpmuludq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7667 | { "(bad)", { XX } }, |
c0f3af97 L |
7668 | }, |
7669 | ||
7670 | /* VEX_LEN_F5_P_2 */ | |
7671 | { | |
7672 | { "vpmaddwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7673 | { "(bad)", { XX } }, |
c0f3af97 L |
7674 | }, |
7675 | ||
7676 | /* VEX_LEN_F6_P_2 */ | |
7677 | { | |
7678 | { "vpsadbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7679 | { "(bad)", { XX } }, |
c0f3af97 L |
7680 | }, |
7681 | ||
7682 | /* VEX_LEN_F7_P_2 */ | |
7683 | { | |
7684 | { "vmaskmovdqu", { XM, XS } }, | |
d5d7db8e | 7685 | { "(bad)", { XX } }, |
c0f3af97 L |
7686 | }, |
7687 | ||
7688 | /* VEX_LEN_F8_P_2 */ | |
7689 | { | |
7690 | { "vpsubb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7691 | { "(bad)", { XX } }, |
c0f3af97 L |
7692 | }, |
7693 | ||
7694 | /* VEX_LEN_F9_P_2 */ | |
7695 | { | |
7696 | { "vpsubw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7697 | { "(bad)", { XX } }, |
c0f3af97 L |
7698 | }, |
7699 | ||
7700 | /* VEX_LEN_FA_P_2 */ | |
7701 | { | |
7702 | { "vpsubd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7703 | { "(bad)", { XX } }, |
c0f3af97 L |
7704 | }, |
7705 | ||
7706 | /* VEX_LEN_FB_P_2 */ | |
7707 | { | |
7708 | { "vpsubq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7709 | { "(bad)", { XX } }, |
c0f3af97 L |
7710 | }, |
7711 | ||
7712 | /* VEX_LEN_FC_P_2 */ | |
7713 | { | |
7714 | { "vpaddb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7715 | { "(bad)", { XX } }, |
c0f3af97 L |
7716 | }, |
7717 | ||
7718 | /* VEX_LEN_FD_P_2 */ | |
7719 | { | |
7720 | { "vpaddw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7721 | { "(bad)", { XX } }, |
c0f3af97 L |
7722 | }, |
7723 | ||
7724 | /* VEX_LEN_FE_P_2 */ | |
7725 | { | |
7726 | { "vpaddd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7727 | { "(bad)", { XX } }, |
c0f3af97 L |
7728 | }, |
7729 | ||
7730 | /* VEX_LEN_3800_P_2 */ | |
7731 | { | |
7732 | { "vpshufb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7733 | { "(bad)", { XX } }, |
c0f3af97 L |
7734 | }, |
7735 | ||
7736 | /* VEX_LEN_3801_P_2 */ | |
7737 | { | |
7738 | { "vphaddw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7739 | { "(bad)", { XX } }, |
c0f3af97 L |
7740 | }, |
7741 | ||
7742 | /* VEX_LEN_3802_P_2 */ | |
7743 | { | |
7744 | { "vphaddd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7745 | { "(bad)", { XX } }, |
c0f3af97 L |
7746 | }, |
7747 | ||
7748 | /* VEX_LEN_3803_P_2 */ | |
7749 | { | |
7750 | { "vphaddsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7751 | { "(bad)", { XX } }, |
c0f3af97 L |
7752 | }, |
7753 | ||
7754 | /* VEX_LEN_3804_P_2 */ | |
7755 | { | |
7756 | { "vpmaddubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7757 | { "(bad)", { XX } }, |
c0f3af97 L |
7758 | }, |
7759 | ||
7760 | /* VEX_LEN_3805_P_2 */ | |
7761 | { | |
7762 | { "vphsubw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7763 | { "(bad)", { XX } }, |
c0f3af97 L |
7764 | }, |
7765 | ||
7766 | /* VEX_LEN_3806_P_2 */ | |
7767 | { | |
7768 | { "vphsubd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7769 | { "(bad)", { XX } }, |
c0f3af97 L |
7770 | }, |
7771 | ||
7772 | /* VEX_LEN_3807_P_2 */ | |
7773 | { | |
7774 | { "vphsubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7775 | { "(bad)", { XX } }, |
c0f3af97 L |
7776 | }, |
7777 | ||
7778 | /* VEX_LEN_3808_P_2 */ | |
7779 | { | |
7780 | { "vpsignb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7781 | { "(bad)", { XX } }, |
c0f3af97 L |
7782 | }, |
7783 | ||
7784 | /* VEX_LEN_3809_P_2 */ | |
7785 | { | |
7786 | { "vpsignw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7787 | { "(bad)", { XX } }, |
c0f3af97 L |
7788 | }, |
7789 | ||
7790 | /* VEX_LEN_380A_P_2 */ | |
7791 | { | |
7792 | { "vpsignd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7793 | { "(bad)", { XX } }, |
c0f3af97 L |
7794 | }, |
7795 | ||
7796 | /* VEX_LEN_380B_P_2 */ | |
7797 | { | |
7798 | { "vpmulhrsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7799 | { "(bad)", { XX } }, |
c0f3af97 L |
7800 | }, |
7801 | ||
7802 | /* VEX_LEN_3819_P_2_M_0 */ | |
7803 | { | |
d5d7db8e | 7804 | { "(bad)", { XX } }, |
c0f3af97 L |
7805 | { "vbroadcastsd", { XM, Mq } }, |
7806 | }, | |
7807 | ||
7808 | /* VEX_LEN_381A_P_2_M_0 */ | |
7809 | { | |
d5d7db8e | 7810 | { "(bad)", { XX } }, |
c0f3af97 L |
7811 | { "vbroadcastf128", { XM, Mxmm } }, |
7812 | }, | |
7813 | ||
7814 | /* VEX_LEN_381C_P_2 */ | |
7815 | { | |
7816 | { "vpabsb", { XM, EXx } }, | |
d5d7db8e | 7817 | { "(bad)", { XX } }, |
c0f3af97 L |
7818 | }, |
7819 | ||
7820 | /* VEX_LEN_381D_P_2 */ | |
7821 | { | |
7822 | { "vpabsw", { XM, EXx } }, | |
d5d7db8e | 7823 | { "(bad)", { XX } }, |
c0f3af97 L |
7824 | }, |
7825 | ||
7826 | /* VEX_LEN_381E_P_2 */ | |
7827 | { | |
7828 | { "vpabsd", { XM, EXx } }, | |
d5d7db8e | 7829 | { "(bad)", { XX } }, |
c0f3af97 L |
7830 | }, |
7831 | ||
7832 | /* VEX_LEN_3820_P_2 */ | |
7833 | { | |
7834 | { "vpmovsxbw", { XM, EXq } }, | |
d5d7db8e | 7835 | { "(bad)", { XX } }, |
c0f3af97 L |
7836 | }, |
7837 | ||
7838 | /* VEX_LEN_3821_P_2 */ | |
7839 | { | |
7840 | { "vpmovsxbd", { XM, EXd } }, | |
d5d7db8e | 7841 | { "(bad)", { XX } }, |
c0f3af97 L |
7842 | }, |
7843 | ||
7844 | /* VEX_LEN_3822_P_2 */ | |
7845 | { | |
7846 | { "vpmovsxbq", { XM, EXw } }, | |
d5d7db8e | 7847 | { "(bad)", { XX } }, |
c0f3af97 L |
7848 | }, |
7849 | ||
7850 | /* VEX_LEN_3823_P_2 */ | |
7851 | { | |
7852 | { "vpmovsxwd", { XM, EXq } }, | |
d5d7db8e | 7853 | { "(bad)", { XX } }, |
c0f3af97 L |
7854 | }, |
7855 | ||
7856 | /* VEX_LEN_3824_P_2 */ | |
7857 | { | |
7858 | { "vpmovsxwq", { XM, EXd } }, | |
d5d7db8e | 7859 | { "(bad)", { XX } }, |
c0f3af97 L |
7860 | }, |
7861 | ||
7862 | /* VEX_LEN_3825_P_2 */ | |
7863 | { | |
7864 | { "vpmovsxdq", { XM, EXq } }, | |
d5d7db8e | 7865 | { "(bad)", { XX } }, |
c0f3af97 L |
7866 | }, |
7867 | ||
7868 | /* VEX_LEN_3828_P_2 */ | |
7869 | { | |
7870 | { "vpmuldq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7871 | { "(bad)", { XX } }, |
c0f3af97 L |
7872 | }, |
7873 | ||
7874 | /* VEX_LEN_3829_P_2 */ | |
7875 | { | |
7876 | { "vpcmpeqq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7877 | { "(bad)", { XX } }, |
c0f3af97 L |
7878 | }, |
7879 | ||
7880 | /* VEX_LEN_382A_P_2_M_0 */ | |
7881 | { | |
7882 | { "vmovntdqa", { XM, Mx } }, | |
d5d7db8e | 7883 | { "(bad)", { XX } }, |
c0f3af97 L |
7884 | }, |
7885 | ||
7886 | /* VEX_LEN_382B_P_2 */ | |
7887 | { | |
7888 | { "vpackusdw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7889 | { "(bad)", { XX } }, |
c0f3af97 L |
7890 | }, |
7891 | ||
7892 | /* VEX_LEN_3830_P_2 */ | |
7893 | { | |
7894 | { "vpmovzxbw", { XM, EXq } }, | |
d5d7db8e | 7895 | { "(bad)", { XX } }, |
c0f3af97 L |
7896 | }, |
7897 | ||
7898 | /* VEX_LEN_3831_P_2 */ | |
7899 | { | |
7900 | { "vpmovzxbd", { XM, EXd } }, | |
d5d7db8e | 7901 | { "(bad)", { XX } }, |
c0f3af97 L |
7902 | }, |
7903 | ||
7904 | /* VEX_LEN_3832_P_2 */ | |
7905 | { | |
7906 | { "vpmovzxbq", { XM, EXw } }, | |
d5d7db8e | 7907 | { "(bad)", { XX } }, |
c0f3af97 L |
7908 | }, |
7909 | ||
7910 | /* VEX_LEN_3833_P_2 */ | |
7911 | { | |
7912 | { "vpmovzxwd", { XM, EXq } }, | |
d5d7db8e | 7913 | { "(bad)", { XX } }, |
c0f3af97 L |
7914 | }, |
7915 | ||
7916 | /* VEX_LEN_3834_P_2 */ | |
7917 | { | |
7918 | { "vpmovzxwq", { XM, EXd } }, | |
d5d7db8e | 7919 | { "(bad)", { XX } }, |
c0f3af97 L |
7920 | }, |
7921 | ||
7922 | /* VEX_LEN_3835_P_2 */ | |
7923 | { | |
7924 | { "vpmovzxdq", { XM, EXq } }, | |
d5d7db8e | 7925 | { "(bad)", { XX } }, |
c0f3af97 L |
7926 | }, |
7927 | ||
7928 | /* VEX_LEN_3837_P_2 */ | |
7929 | { | |
7930 | { "vpcmpgtq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7931 | { "(bad)", { XX } }, |
c0f3af97 L |
7932 | }, |
7933 | ||
7934 | /* VEX_LEN_3838_P_2 */ | |
7935 | { | |
7936 | { "vpminsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7937 | { "(bad)", { XX } }, |
c0f3af97 L |
7938 | }, |
7939 | ||
7940 | /* VEX_LEN_3839_P_2 */ | |
7941 | { | |
7942 | { "vpminsd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7943 | { "(bad)", { XX } }, |
c0f3af97 L |
7944 | }, |
7945 | ||
7946 | /* VEX_LEN_383A_P_2 */ | |
7947 | { | |
7948 | { "vpminuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7949 | { "(bad)", { XX } }, |
c0f3af97 L |
7950 | }, |
7951 | ||
7952 | /* VEX_LEN_383B_P_2 */ | |
7953 | { | |
7954 | { "vpminud", { XM, Vex128, EXx } }, | |
d5d7db8e | 7955 | { "(bad)", { XX } }, |
c0f3af97 L |
7956 | }, |
7957 | ||
7958 | /* VEX_LEN_383C_P_2 */ | |
7959 | { | |
7960 | { "vpmaxsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7961 | { "(bad)", { XX } }, |
c0f3af97 L |
7962 | }, |
7963 | ||
7964 | /* VEX_LEN_383D_P_2 */ | |
7965 | { | |
7966 | { "vpmaxsd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7967 | { "(bad)", { XX } }, |
c0f3af97 L |
7968 | }, |
7969 | ||
7970 | /* VEX_LEN_383E_P_2 */ | |
7971 | { | |
7972 | { "vpmaxuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7973 | { "(bad)", { XX } }, |
c0f3af97 L |
7974 | }, |
7975 | ||
7976 | /* VEX_LEN_383F_P_2 */ | |
7977 | { | |
7978 | { "vpmaxud", { XM, Vex128, EXx } }, | |
d5d7db8e | 7979 | { "(bad)", { XX } }, |
c0f3af97 L |
7980 | }, |
7981 | ||
7982 | /* VEX_LEN_3840_P_2 */ | |
7983 | { | |
7984 | { "vpmulld", { XM, Vex128, EXx } }, | |
d5d7db8e | 7985 | { "(bad)", { XX } }, |
c0f3af97 L |
7986 | }, |
7987 | ||
7988 | /* VEX_LEN_3841_P_2 */ | |
7989 | { | |
7990 | { "vphminposuw", { XM, EXx } }, | |
d5d7db8e | 7991 | { "(bad)", { XX } }, |
c0f3af97 L |
7992 | }, |
7993 | ||
a5ff0eb2 L |
7994 | /* VEX_LEN_38DB_P_2 */ |
7995 | { | |
7996 | { "vaesimc", { XM, EXx } }, | |
7997 | { "(bad)", { XX } }, | |
7998 | }, | |
7999 | ||
8000 | /* VEX_LEN_38DC_P_2 */ | |
8001 | { | |
8002 | { "vaesenc", { XM, Vex128, EXx } }, | |
8003 | { "(bad)", { XX } }, | |
8004 | }, | |
8005 | ||
8006 | /* VEX_LEN_38DD_P_2 */ | |
8007 | { | |
8008 | { "vaesenclast", { XM, Vex128, EXx } }, | |
8009 | { "(bad)", { XX } }, | |
8010 | }, | |
8011 | ||
8012 | /* VEX_LEN_38DE_P_2 */ | |
8013 | { | |
8014 | { "vaesdec", { XM, Vex128, EXx } }, | |
8015 | { "(bad)", { XX } }, | |
8016 | }, | |
8017 | ||
8018 | /* VEX_LEN_38DF_P_2 */ | |
8019 | { | |
8020 | { "vaesdeclast", { XM, Vex128, EXx } }, | |
8021 | { "(bad)", { XX } }, | |
8022 | }, | |
8023 | ||
c0f3af97 L |
8024 | /* VEX_LEN_3A06_P_2 */ |
8025 | { | |
d5d7db8e | 8026 | { "(bad)", { XX } }, |
c0f3af97 L |
8027 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
8028 | }, | |
8029 | ||
8030 | /* VEX_LEN_3A0A_P_2 */ | |
8031 | { | |
8032 | { "vroundss", { XM, Vex128, EXd, Ib } }, | |
d5d7db8e | 8033 | { "(bad)", { XX } }, |
c0f3af97 L |
8034 | }, |
8035 | ||
8036 | /* VEX_LEN_3A0B_P_2 */ | |
8037 | { | |
8038 | { "vroundsd", { XM, Vex128, EXq, Ib } }, | |
d5d7db8e | 8039 | { "(bad)", { XX } }, |
c0f3af97 L |
8040 | }, |
8041 | ||
8042 | /* VEX_LEN_3A0E_P_2 */ | |
8043 | { | |
8044 | { "vpblendw", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8045 | { "(bad)", { XX } }, |
c0f3af97 L |
8046 | }, |
8047 | ||
8048 | /* VEX_LEN_3A0F_P_2 */ | |
8049 | { | |
8050 | { "vpalignr", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8051 | { "(bad)", { XX } }, |
c0f3af97 L |
8052 | }, |
8053 | ||
8054 | /* VEX_LEN_3A14_P_2 */ | |
8055 | { | |
8056 | { "vpextrb", { Edqb, XM, Ib } }, | |
d5d7db8e | 8057 | { "(bad)", { XX } }, |
c0f3af97 L |
8058 | }, |
8059 | ||
8060 | /* VEX_LEN_3A15_P_2 */ | |
8061 | { | |
8062 | { "vpextrw", { Edqw, XM, Ib } }, | |
d5d7db8e | 8063 | { "(bad)", { XX } }, |
c0f3af97 L |
8064 | }, |
8065 | ||
8066 | /* VEX_LEN_3A16_P_2 */ | |
8067 | { | |
8068 | { "vpextrK", { Edq, XM, Ib } }, | |
d5d7db8e | 8069 | { "(bad)", { XX } }, |
c0f3af97 L |
8070 | }, |
8071 | ||
8072 | /* VEX_LEN_3A17_P_2 */ | |
8073 | { | |
8074 | { "vextractps", { Edqd, XM, Ib } }, | |
d5d7db8e | 8075 | { "(bad)", { XX } }, |
c0f3af97 L |
8076 | }, |
8077 | ||
8078 | /* VEX_LEN_3A18_P_2 */ | |
8079 | { | |
d5d7db8e | 8080 | { "(bad)", { XX } }, |
c0f3af97 L |
8081 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
8082 | }, | |
8083 | ||
8084 | /* VEX_LEN_3A19_P_2 */ | |
8085 | { | |
d5d7db8e | 8086 | { "(bad)", { XX } }, |
c0f3af97 L |
8087 | { "vextractf128", { EXxmm, XM, Ib } }, |
8088 | }, | |
8089 | ||
8090 | /* VEX_LEN_3A20_P_2 */ | |
8091 | { | |
8092 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, | |
d5d7db8e | 8093 | { "(bad)", { XX } }, |
c0f3af97 L |
8094 | }, |
8095 | ||
8096 | /* VEX_LEN_3A21_P_2 */ | |
8097 | { | |
8098 | { "vinsertps", { XM, Vex128, EXd, Ib } }, | |
d5d7db8e | 8099 | { "(bad)", { XX } }, |
c0f3af97 L |
8100 | }, |
8101 | ||
8102 | /* VEX_LEN_3A22_P_2 */ | |
8103 | { | |
8104 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
d5d7db8e | 8105 | { "(bad)", { XX } }, |
c0f3af97 L |
8106 | }, |
8107 | ||
8108 | /* VEX_LEN_3A41_P_2 */ | |
8109 | { | |
8110 | { "vdppd", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8111 | { "(bad)", { XX } }, |
c0f3af97 L |
8112 | }, |
8113 | ||
8114 | /* VEX_LEN_3A42_P_2 */ | |
8115 | { | |
8116 | { "vmpsadbw", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8117 | { "(bad)", { XX } }, |
c0f3af97 L |
8118 | }, |
8119 | ||
ce2f5b3c L |
8120 | /* VEX_LEN_3A44_P_2 */ |
8121 | { | |
8122 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, | |
8123 | { "(bad)", { XX } }, | |
8124 | }, | |
8125 | ||
c0f3af97 L |
8126 | /* VEX_LEN_3A4C_P_2 */ |
8127 | { | |
8128 | { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, | |
d5d7db8e | 8129 | { "(bad)", { XX } }, |
c0f3af97 L |
8130 | }, |
8131 | ||
8132 | /* VEX_LEN_3A60_P_2 */ | |
8133 | { | |
8134 | { "vpcmpestrm", { XM, EXx, Ib } }, | |
d5d7db8e | 8135 | { "(bad)", { XX } }, |
c0f3af97 L |
8136 | }, |
8137 | ||
8138 | /* VEX_LEN_3A61_P_2 */ | |
8139 | { | |
8140 | { "vpcmpestri", { XM, EXx, Ib } }, | |
d5d7db8e | 8141 | { "(bad)", { XX } }, |
c0f3af97 L |
8142 | }, |
8143 | ||
8144 | /* VEX_LEN_3A62_P_2 */ | |
8145 | { | |
8146 | { "vpcmpistrm", { XM, EXx, Ib } }, | |
d5d7db8e | 8147 | { "(bad)", { XX } }, |
c0f3af97 L |
8148 | }, |
8149 | ||
8150 | /* VEX_LEN_3A63_P_2 */ | |
8151 | { | |
8152 | { "vpcmpistri", { XM, EXx, Ib } }, | |
d5d7db8e | 8153 | { "(bad)", { XX } }, |
c0f3af97 L |
8154 | }, |
8155 | ||
a5ff0eb2 L |
8156 | /* VEX_LEN_3ADF_P_2 */ |
8157 | { | |
8158 | { "vaeskeygenassist", { XM, EXx, Ib } }, | |
8159 | { "(bad)", { XX } }, | |
8160 | }, | |
331d2d0d L |
8161 | }; |
8162 | ||
1ceb70f8 | 8163 | static const struct dis386 mod_table[][2] = { |
b844680a | 8164 | { |
1ceb70f8 | 8165 | /* MOD_8D */ |
d8faab4e L |
8166 | { "leaS", { Gv, M } }, |
8167 | { "(bad)", { XX } }, | |
8168 | }, | |
8169 | { | |
92fddf8e L |
8170 | /* MOD_0F01_REG_0 */ |
8171 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
8172 | { RM_TABLE (RM_0F01_REG_0) }, | |
d8faab4e L |
8173 | }, |
8174 | { | |
92fddf8e L |
8175 | /* MOD_0F01_REG_1 */ |
8176 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
8177 | { RM_TABLE (RM_0F01_REG_1) }, | |
d8faab4e L |
8178 | }, |
8179 | { | |
92fddf8e L |
8180 | /* MOD_0F01_REG_2 */ |
8181 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
475a2301 | 8182 | { RM_TABLE (RM_0F01_REG_2) }, |
d8faab4e L |
8183 | }, |
8184 | { | |
92fddf8e L |
8185 | /* MOD_0F01_REG_3 */ |
8186 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
8187 | { RM_TABLE (RM_0F01_REG_3) }, | |
d8faab4e L |
8188 | }, |
8189 | { | |
92fddf8e L |
8190 | /* MOD_0F01_REG_7 */ |
8191 | { "invlpg", { Mb } }, | |
8192 | { RM_TABLE (RM_0F01_REG_7) }, | |
b844680a L |
8193 | }, |
8194 | { | |
92fddf8e L |
8195 | /* MOD_0F12_PREFIX_0 */ |
8196 | { "movlps", { XM, EXq } }, | |
8197 | { "movhlps", { XM, EXq } }, | |
b844680a L |
8198 | }, |
8199 | { | |
92fddf8e L |
8200 | /* MOD_0F13 */ |
8201 | { "movlpX", { EXq, XM } }, | |
d8faab4e L |
8202 | { "(bad)", { XX } }, |
8203 | }, | |
8204 | { | |
92fddf8e L |
8205 | /* MOD_0F16_PREFIX_0 */ |
8206 | { "movhps", { XM, EXq } }, | |
8207 | { "movlhps", { XM, EXq } }, | |
b844680a L |
8208 | }, |
8209 | { | |
92fddf8e L |
8210 | /* MOD_0F17 */ |
8211 | { "movhpX", { EXq, XM } }, | |
b844680a L |
8212 | { "(bad)", { XX } }, |
8213 | }, | |
8214 | { | |
92fddf8e L |
8215 | /* MOD_0F18_REG_0 */ |
8216 | { "prefetchnta", { Mb } }, | |
b844680a | 8217 | { "(bad)", { XX } }, |
b844680a L |
8218 | }, |
8219 | { | |
92fddf8e L |
8220 | /* MOD_0F18_REG_1 */ |
8221 | { "prefetcht0", { Mb } }, | |
8222 | { "(bad)", { XX } }, | |
b844680a L |
8223 | }, |
8224 | { | |
92fddf8e L |
8225 | /* MOD_0F18_REG_2 */ |
8226 | { "prefetcht1", { Mb } }, | |
8227 | { "(bad)", { XX } }, | |
b844680a L |
8228 | }, |
8229 | { | |
92fddf8e L |
8230 | /* MOD_0F18_REG_3 */ |
8231 | { "prefetcht2", { Mb } }, | |
b844680a | 8232 | { "(bad)", { XX } }, |
b844680a L |
8233 | }, |
8234 | { | |
92fddf8e L |
8235 | /* MOD_0F20 */ |
8236 | { "(bad)", { XX } }, | |
8237 | { "movZ", { Rm, Cm } }, | |
b844680a L |
8238 | }, |
8239 | { | |
92fddf8e L |
8240 | /* MOD_0F21 */ |
8241 | { "(bad)", { XX } }, | |
8242 | { "movZ", { Rm, Dm } }, | |
b844680a L |
8243 | }, |
8244 | { | |
92fddf8e | 8245 | /* MOD_0F22 */ |
b844680a | 8246 | { "(bad)", { XX } }, |
92fddf8e | 8247 | { "movZ", { Cm, Rm } }, |
b844680a L |
8248 | }, |
8249 | { | |
92fddf8e | 8250 | /* MOD_0F23 */ |
b844680a | 8251 | { "(bad)", { XX } }, |
92fddf8e | 8252 | { "movZ", { Dm, Rm } }, |
b844680a L |
8253 | }, |
8254 | { | |
92fddf8e | 8255 | /* MOD_0F24 */ |
c1e679ec | 8256 | { "(bad)", { XX } }, |
92fddf8e | 8257 | { "movL", { Rd, Td } }, |
b844680a L |
8258 | }, |
8259 | { | |
92fddf8e | 8260 | /* MOD_0F26 */ |
b844680a | 8261 | { "(bad)", { XX } }, |
92fddf8e | 8262 | { "movL", { Td, Rd } }, |
b844680a | 8263 | }, |
75c135a8 L |
8264 | { |
8265 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 8266 | {"movntps", { Mx, XM } }, |
75c135a8 L |
8267 | { "(bad)", { XX } }, |
8268 | }, | |
8269 | { | |
8270 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 8271 | {"movntss", { Md, XM } }, |
75c135a8 L |
8272 | { "(bad)", { XX } }, |
8273 | }, | |
8274 | { | |
8275 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 8276 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
8277 | { "(bad)", { XX } }, |
8278 | }, | |
8279 | { | |
8280 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 8281 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
8282 | { "(bad)", { XX } }, |
8283 | }, | |
8284 | { | |
8285 | /* MOD_0F51 */ | |
8286 | { "(bad)", { XX } }, | |
8287 | { "movmskpX", { Gdq, XS } }, | |
8288 | }, | |
b844680a | 8289 | { |
1ceb70f8 | 8290 | /* MOD_0F71_REG_2 */ |
b844680a | 8291 | { "(bad)", { XX } }, |
4e7d34a6 | 8292 | { "psrlw", { MS, Ib } }, |
b844680a L |
8293 | }, |
8294 | { | |
1ceb70f8 | 8295 | /* MOD_0F71_REG_4 */ |
b844680a | 8296 | { "(bad)", { XX } }, |
4e7d34a6 | 8297 | { "psraw", { MS, Ib } }, |
b844680a L |
8298 | }, |
8299 | { | |
1ceb70f8 | 8300 | /* MOD_0F71_REG_6 */ |
b844680a | 8301 | { "(bad)", { XX } }, |
4e7d34a6 | 8302 | { "psllw", { MS, Ib } }, |
b844680a L |
8303 | }, |
8304 | { | |
1ceb70f8 | 8305 | /* MOD_0F72_REG_2 */ |
b844680a | 8306 | { "(bad)", { XX } }, |
4e7d34a6 | 8307 | { "psrld", { MS, Ib } }, |
b844680a L |
8308 | }, |
8309 | { | |
1ceb70f8 | 8310 | /* MOD_0F72_REG_4 */ |
b844680a | 8311 | { "(bad)", { XX } }, |
4e7d34a6 | 8312 | { "psrad", { MS, Ib } }, |
b844680a L |
8313 | }, |
8314 | { | |
1ceb70f8 | 8315 | /* MOD_0F72_REG_6 */ |
b844680a | 8316 | { "(bad)", { XX } }, |
4e7d34a6 | 8317 | { "pslld", { MS, Ib } }, |
b844680a L |
8318 | }, |
8319 | { | |
1ceb70f8 | 8320 | /* MOD_0F73_REG_2 */ |
4e7d34a6 L |
8321 | { "(bad)", { XX } }, |
8322 | { "psrlq", { MS, Ib } }, | |
b844680a L |
8323 | }, |
8324 | { | |
1ceb70f8 | 8325 | /* MOD_0F73_REG_3 */ |
b844680a | 8326 | { "(bad)", { XX } }, |
c0f3af97 L |
8327 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
8328 | }, | |
8329 | { | |
8330 | /* MOD_0F73_REG_6 */ | |
8331 | { "(bad)", { XX } }, | |
8332 | { "psllq", { MS, Ib } }, | |
8333 | }, | |
8334 | { | |
8335 | /* MOD_0F73_REG_7 */ | |
8336 | { "(bad)", { XX } }, | |
8337 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, | |
8338 | }, | |
8339 | { | |
8340 | /* MOD_0FAE_REG_0 */ | |
8341 | { "fxsave", { M } }, | |
8342 | { "(bad)", { XX } }, | |
8343 | }, | |
8344 | { | |
8345 | /* MOD_0FAE_REG_1 */ | |
8346 | { "fxrstor", { M } }, | |
8347 | { "(bad)", { XX } }, | |
8348 | }, | |
8349 | { | |
8350 | /* MOD_0FAE_REG_2 */ | |
8351 | { "ldmxcsr", { Md } }, | |
8352 | { "(bad)", { XX } }, | |
8353 | }, | |
8354 | { | |
8355 | /* MOD_0FAE_REG_3 */ | |
8356 | { "stmxcsr", { Md } }, | |
8357 | { "(bad)", { XX } }, | |
8358 | }, | |
8359 | { | |
8360 | /* MOD_0FAE_REG_4 */ | |
8361 | { "xsave", { M } }, | |
8362 | { "(bad)", { XX } }, | |
8363 | }, | |
8364 | { | |
8365 | /* MOD_0FAE_REG_5 */ | |
8366 | { "xrstor", { M } }, | |
8367 | { RM_TABLE (RM_0FAE_REG_5) }, | |
8368 | }, | |
8369 | { | |
8370 | /* MOD_0FAE_REG_6 */ | |
8371 | { "xsaveopt", { M } }, | |
8372 | { RM_TABLE (RM_0FAE_REG_6) }, | |
8373 | }, | |
8374 | { | |
8375 | /* MOD_0FAE_REG_7 */ | |
8376 | { "clflush", { Mb } }, | |
8377 | { RM_TABLE (RM_0FAE_REG_7) }, | |
8378 | }, | |
8379 | { | |
8380 | /* MOD_0FB2 */ | |
8381 | { "lssS", { Gv, Mp } }, | |
8382 | { "(bad)", { XX } }, | |
8383 | }, | |
8384 | { | |
8385 | /* MOD_0FB4 */ | |
8386 | { "lfsS", { Gv, Mp } }, | |
8387 | { "(bad)", { XX } }, | |
8388 | }, | |
8389 | { | |
8390 | /* MOD_0FB5 */ | |
8391 | { "lgsS", { Gv, Mp } }, | |
8392 | { "(bad)", { XX } }, | |
8393 | }, | |
8394 | { | |
8395 | /* MOD_0FC7_REG_6 */ | |
8396 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
8397 | { "(bad)", { XX } }, | |
8398 | }, | |
8399 | { | |
8400 | /* MOD_0FC7_REG_7 */ | |
8401 | { "vmptrst", { Mq } }, | |
8402 | { "(bad)", { XX } }, | |
8403 | }, | |
8404 | { | |
8405 | /* MOD_0FD7 */ | |
8406 | { "(bad)", { XX } }, | |
8407 | { "pmovmskb", { Gdq, MS } }, | |
8408 | }, | |
8409 | { | |
8410 | /* MOD_0FE7_PREFIX_2 */ | |
8411 | { "movntdq", { Mx, XM } }, | |
8412 | { "(bad)", { XX } }, | |
8413 | }, | |
8414 | { | |
8415 | /* MOD_0FF0_PREFIX_3 */ | |
8416 | { "lddqu", { XM, M } }, | |
8417 | { "(bad)", { XX } }, | |
8418 | }, | |
8419 | { | |
8420 | /* MOD_0F382A_PREFIX_2 */ | |
8421 | { "movntdqa", { XM, Mx } }, | |
8422 | { "(bad)", { XX } }, | |
8423 | }, | |
8424 | { | |
8425 | /* MOD_62_32BIT */ | |
8426 | { "bound{S|}", { Gv, Ma } }, | |
8427 | { "(bad)", { XX } }, | |
8428 | }, | |
8429 | { | |
8430 | /* MOD_C4_32BIT */ | |
8431 | { "lesS", { Gv, Mp } }, | |
8432 | { VEX_C4_TABLE (VEX_0F) }, | |
8433 | }, | |
8434 | { | |
8435 | /* MOD_C5_32BIT */ | |
8436 | { "ldsS", { Gv, Mp } }, | |
8437 | { VEX_C5_TABLE (VEX_0F) }, | |
8438 | }, | |
8439 | { | |
8440 | /* MOD_VEX_12_PREFIX_0 */ | |
8441 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) }, | |
8442 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) }, | |
8443 | }, | |
8444 | { | |
8445 | /* MOD_VEX_13 */ | |
8446 | { VEX_LEN_TABLE (VEX_LEN_13_M_0) }, | |
8447 | { "(bad)", { XX } }, | |
8448 | }, | |
8449 | { | |
8450 | /* MOD_VEX_16_PREFIX_0 */ | |
8451 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) }, | |
8452 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) }, | |
8453 | }, | |
8454 | { | |
8455 | /* MOD_VEX_17 */ | |
8456 | { VEX_LEN_TABLE (VEX_LEN_17_M_0) }, | |
8457 | { "(bad)", { XX } }, | |
8458 | }, | |
8459 | { | |
8460 | /* MOD_VEX_2B */ | |
168e3097 | 8461 | { "vmovntpX", { Mx, XM } }, |
c0f3af97 L |
8462 | { "(bad)", { XX } }, |
8463 | }, | |
8464 | { | |
8465 | /* MOD_VEX_51 */ | |
8466 | { "(bad)", { XX } }, | |
8467 | { "vmovmskpX", { Gdq, XS } }, | |
8468 | }, | |
8469 | { | |
8470 | /* MOD_VEX_71_REG_2 */ | |
8471 | { "(bad)", { XX } }, | |
8472 | { PREFIX_TABLE (PREFIX_VEX_71_REG_2) }, | |
b844680a L |
8473 | }, |
8474 | { | |
c0f3af97 | 8475 | /* MOD_VEX_71_REG_4 */ |
b844680a | 8476 | { "(bad)", { XX } }, |
c0f3af97 | 8477 | { PREFIX_TABLE (PREFIX_VEX_71_REG_4) }, |
b844680a L |
8478 | }, |
8479 | { | |
c0f3af97 | 8480 | /* MOD_VEX_71_REG_6 */ |
b844680a | 8481 | { "(bad)", { XX } }, |
c0f3af97 | 8482 | { PREFIX_TABLE (PREFIX_VEX_71_REG_6) }, |
b844680a L |
8483 | }, |
8484 | { | |
c0f3af97 | 8485 | /* MOD_VEX_72_REG_2 */ |
b844680a | 8486 | { "(bad)", { XX } }, |
c0f3af97 | 8487 | { PREFIX_TABLE (PREFIX_VEX_72_REG_2) }, |
b844680a | 8488 | }, |
d8faab4e | 8489 | { |
c0f3af97 | 8490 | /* MOD_VEX_72_REG_4 */ |
d8faab4e | 8491 | { "(bad)", { XX } }, |
c0f3af97 | 8492 | { PREFIX_TABLE (PREFIX_VEX_72_REG_4) }, |
d8faab4e L |
8493 | }, |
8494 | { | |
c0f3af97 | 8495 | /* MOD_VEX_72_REG_6 */ |
d8faab4e | 8496 | { "(bad)", { XX } }, |
c0f3af97 | 8497 | { PREFIX_TABLE (PREFIX_VEX_72_REG_6) }, |
d8faab4e | 8498 | }, |
876d4bfa | 8499 | { |
c0f3af97 | 8500 | /* MOD_VEX_73_REG_2 */ |
876d4bfa | 8501 | { "(bad)", { XX } }, |
c0f3af97 | 8502 | { PREFIX_TABLE (PREFIX_VEX_73_REG_2) }, |
876d4bfa L |
8503 | }, |
8504 | { | |
c0f3af97 | 8505 | /* MOD_VEX_73_REG_3 */ |
876d4bfa | 8506 | { "(bad)", { XX } }, |
c0f3af97 | 8507 | { PREFIX_TABLE (PREFIX_VEX_73_REG_3) }, |
475a2301 L |
8508 | }, |
8509 | { | |
c0f3af97 L |
8510 | /* MOD_VEX_73_REG_6 */ |
8511 | { "(bad)", { XX } }, | |
8512 | { PREFIX_TABLE (PREFIX_VEX_73_REG_6) }, | |
876d4bfa L |
8513 | }, |
8514 | { | |
c0f3af97 | 8515 | /* MOD_VEX_73_REG_7 */ |
4e7d34a6 | 8516 | { "(bad)", { XX } }, |
c0f3af97 | 8517 | { PREFIX_TABLE (PREFIX_VEX_73_REG_7) }, |
876d4bfa L |
8518 | }, |
8519 | { | |
c0f3af97 L |
8520 | /* MOD_VEX_AE_REG_2 */ |
8521 | { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) }, | |
8522 | { "(bad)", { XX } }, | |
876d4bfa | 8523 | }, |
bbedc832 | 8524 | { |
c0f3af97 L |
8525 | /* MOD_VEX_AE_REG_3 */ |
8526 | { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) }, | |
4e7d34a6 | 8527 | { "(bad)", { XX } }, |
bbedc832 | 8528 | }, |
144c41d9 | 8529 | { |
c0f3af97 | 8530 | /* MOD_VEX_D7_PREFIX_2 */ |
4e7d34a6 | 8531 | { "(bad)", { XX } }, |
c0f3af97 | 8532 | { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) }, |
144c41d9 | 8533 | }, |
1afd85e3 | 8534 | { |
c0f3af97 | 8535 | /* MOD_VEX_E7_PREFIX_2 */ |
168e3097 | 8536 | { "vmovntdq", { Mx, XM } }, |
92fddf8e | 8537 | { "(bad)", { XX } }, |
1afd85e3 L |
8538 | }, |
8539 | { | |
c0f3af97 L |
8540 | /* MOD_VEX_F0_PREFIX_3 */ |
8541 | { "vlddqu", { XM, M } }, | |
92fddf8e L |
8542 | { "(bad)", { XX } }, |
8543 | }, | |
8544 | { | |
c0f3af97 L |
8545 | /* MOD_VEX_3818_PREFIX_2 */ |
8546 | { "vbroadcastss", { XM, Md } }, | |
92fddf8e | 8547 | { "(bad)", { XX } }, |
1afd85e3 | 8548 | }, |
75c135a8 | 8549 | { |
c0f3af97 L |
8550 | /* MOD_VEX_3819_PREFIX_2 */ |
8551 | { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) }, | |
75c135a8 | 8552 | { "(bad)", { XX } }, |
75c135a8 L |
8553 | }, |
8554 | { | |
c0f3af97 L |
8555 | /* MOD_VEX_381A_PREFIX_2 */ |
8556 | { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) }, | |
75c135a8 L |
8557 | { "(bad)", { XX } }, |
8558 | }, | |
1afd85e3 | 8559 | { |
c0f3af97 L |
8560 | /* MOD_VEX_382A_PREFIX_2 */ |
8561 | { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) }, | |
1afd85e3 | 8562 | { "(bad)", { XX } }, |
1afd85e3 | 8563 | }, |
75c135a8 | 8564 | { |
c0f3af97 L |
8565 | /* MOD_VEX_382C_PREFIX_2 */ |
8566 | { "vmaskmovps", { XM, Vex, Mx } }, | |
75c135a8 L |
8567 | { "(bad)", { XX } }, |
8568 | }, | |
1afd85e3 | 8569 | { |
c0f3af97 L |
8570 | /* MOD_VEX_382D_PREFIX_2 */ |
8571 | { "vmaskmovpd", { XM, Vex, Mx } }, | |
1afd85e3 | 8572 | { "(bad)", { XX } }, |
1afd85e3 L |
8573 | }, |
8574 | { | |
c0f3af97 L |
8575 | /* MOD_VEX_382E_PREFIX_2 */ |
8576 | { "vmaskmovps", { Mx, Vex, XM } }, | |
4e7d34a6 | 8577 | { "(bad)", { XX } }, |
1afd85e3 L |
8578 | }, |
8579 | { | |
c0f3af97 L |
8580 | /* MOD_VEX_382F_PREFIX_2 */ |
8581 | { "vmaskmovpd", { Mx, Vex, XM } }, | |
1afd85e3 | 8582 | { "(bad)", { XX } }, |
1afd85e3 | 8583 | }, |
b844680a L |
8584 | }; |
8585 | ||
1ceb70f8 | 8586 | static const struct dis386 rm_table[][8] = { |
b844680a | 8587 | { |
1ceb70f8 | 8588 | /* RM_0F01_REG_0 */ |
b844680a L |
8589 | { "(bad)", { XX } }, |
8590 | { "vmcall", { Skip_MODRM } }, | |
8591 | { "vmlaunch", { Skip_MODRM } }, | |
8592 | { "vmresume", { Skip_MODRM } }, | |
8593 | { "vmxoff", { Skip_MODRM } }, | |
8594 | { "(bad)", { XX } }, | |
8595 | { "(bad)", { XX } }, | |
8596 | { "(bad)", { XX } }, | |
8597 | }, | |
8598 | { | |
1ceb70f8 | 8599 | /* RM_0F01_REG_1 */ |
b844680a L |
8600 | { "monitor", { { OP_Monitor, 0 } } }, |
8601 | { "mwait", { { OP_Mwait, 0 } } }, | |
8602 | { "(bad)", { XX } }, | |
8603 | { "(bad)", { XX } }, | |
8604 | { "(bad)", { XX } }, | |
8605 | { "(bad)", { XX } }, | |
8606 | { "(bad)", { XX } }, | |
8607 | { "(bad)", { XX } }, | |
8608 | }, | |
475a2301 L |
8609 | { |
8610 | /* RM_0F01_REG_2 */ | |
8611 | { "xgetbv", { Skip_MODRM } }, | |
8612 | { "xsetbv", { Skip_MODRM } }, | |
8613 | { "(bad)", { XX } }, | |
8614 | { "(bad)", { XX } }, | |
8615 | { "(bad)", { XX } }, | |
8616 | { "(bad)", { XX } }, | |
8617 | { "(bad)", { XX } }, | |
8618 | { "(bad)", { XX } }, | |
8619 | }, | |
b844680a | 8620 | { |
1ceb70f8 | 8621 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
8622 | { "vmrun", { Skip_MODRM } }, |
8623 | { "vmmcall", { Skip_MODRM } }, | |
8624 | { "vmload", { Skip_MODRM } }, | |
8625 | { "vmsave", { Skip_MODRM } }, | |
8626 | { "stgi", { Skip_MODRM } }, | |
8627 | { "clgi", { Skip_MODRM } }, | |
8628 | { "skinit", { Skip_MODRM } }, | |
8629 | { "invlpga", { Skip_MODRM } }, | |
8630 | }, | |
8631 | { | |
1ceb70f8 | 8632 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
8633 | { "swapgs", { Skip_MODRM } }, |
8634 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
8635 | { "(bad)", { XX } }, |
8636 | { "(bad)", { XX } }, | |
8637 | { "(bad)", { XX } }, | |
8638 | { "(bad)", { XX } }, | |
8639 | { "(bad)", { XX } }, | |
8640 | { "(bad)", { XX } }, | |
8641 | }, | |
8642 | { | |
1ceb70f8 | 8643 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 8644 | { "lfence", { Skip_MODRM } }, |
b844680a L |
8645 | { "(bad)", { XX } }, |
8646 | { "(bad)", { XX } }, | |
8647 | { "(bad)", { XX } }, | |
8648 | { "(bad)", { XX } }, | |
8649 | { "(bad)", { XX } }, | |
8650 | { "(bad)", { XX } }, | |
8651 | { "(bad)", { XX } }, | |
8652 | }, | |
8653 | { | |
1ceb70f8 | 8654 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 8655 | { "mfence", { Skip_MODRM } }, |
b844680a L |
8656 | { "(bad)", { XX } }, |
8657 | { "(bad)", { XX } }, | |
8658 | { "(bad)", { XX } }, | |
8659 | { "(bad)", { XX } }, | |
8660 | { "(bad)", { XX } }, | |
8661 | { "(bad)", { XX } }, | |
8662 | { "(bad)", { XX } }, | |
8663 | }, | |
bbedc832 | 8664 | { |
1ceb70f8 | 8665 | /* RM_0FAE_REG_7 */ |
4e7d34a6 L |
8666 | { "sfence", { Skip_MODRM } }, |
8667 | { "(bad)", { XX } }, | |
bbedc832 L |
8668 | { "(bad)", { XX } }, |
8669 | { "(bad)", { XX } }, | |
8670 | { "(bad)", { XX } }, | |
8671 | { "(bad)", { XX } }, | |
8672 | { "(bad)", { XX } }, | |
8673 | { "(bad)", { XX } }, | |
144c41d9 | 8674 | }, |
b844680a L |
8675 | }; |
8676 | ||
c608c12e AM |
8677 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
8678 | ||
252b5132 | 8679 | static void |
26ca5450 | 8680 | ckprefix (void) |
252b5132 | 8681 | { |
52b15da3 JH |
8682 | int newrex; |
8683 | rex = 0; | |
c0f3af97 L |
8684 | rex_original = 0; |
8685 | rex_ignored = 0; | |
252b5132 | 8686 | prefixes = 0; |
7d421014 | 8687 | used_prefixes = 0; |
52b15da3 | 8688 | rex_used = 0; |
252b5132 RH |
8689 | while (1) |
8690 | { | |
8691 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 8692 | newrex = 0; |
252b5132 RH |
8693 | switch (*codep) |
8694 | { | |
52b15da3 JH |
8695 | /* REX prefixes family. */ |
8696 | case 0x40: | |
8697 | case 0x41: | |
8698 | case 0x42: | |
8699 | case 0x43: | |
8700 | case 0x44: | |
8701 | case 0x45: | |
8702 | case 0x46: | |
8703 | case 0x47: | |
8704 | case 0x48: | |
8705 | case 0x49: | |
8706 | case 0x4a: | |
8707 | case 0x4b: | |
8708 | case 0x4c: | |
8709 | case 0x4d: | |
8710 | case 0x4e: | |
8711 | case 0x4f: | |
cb712a9e | 8712 | if (address_mode == mode_64bit) |
52b15da3 JH |
8713 | newrex = *codep; |
8714 | else | |
8715 | return; | |
8716 | break; | |
252b5132 RH |
8717 | case 0xf3: |
8718 | prefixes |= PREFIX_REPZ; | |
8719 | break; | |
8720 | case 0xf2: | |
8721 | prefixes |= PREFIX_REPNZ; | |
8722 | break; | |
8723 | case 0xf0: | |
8724 | prefixes |= PREFIX_LOCK; | |
8725 | break; | |
8726 | case 0x2e: | |
8727 | prefixes |= PREFIX_CS; | |
8728 | break; | |
8729 | case 0x36: | |
8730 | prefixes |= PREFIX_SS; | |
8731 | break; | |
8732 | case 0x3e: | |
8733 | prefixes |= PREFIX_DS; | |
8734 | break; | |
8735 | case 0x26: | |
8736 | prefixes |= PREFIX_ES; | |
8737 | break; | |
8738 | case 0x64: | |
8739 | prefixes |= PREFIX_FS; | |
8740 | break; | |
8741 | case 0x65: | |
8742 | prefixes |= PREFIX_GS; | |
8743 | break; | |
8744 | case 0x66: | |
8745 | prefixes |= PREFIX_DATA; | |
8746 | break; | |
8747 | case 0x67: | |
8748 | prefixes |= PREFIX_ADDR; | |
8749 | break; | |
5076851f | 8750 | case FWAIT_OPCODE: |
252b5132 RH |
8751 | /* fwait is really an instruction. If there are prefixes |
8752 | before the fwait, they belong to the fwait, *not* to the | |
8753 | following instruction. */ | |
3e7d61b2 | 8754 | if (prefixes || rex) |
252b5132 RH |
8755 | { |
8756 | prefixes |= PREFIX_FWAIT; | |
8757 | codep++; | |
8758 | return; | |
8759 | } | |
8760 | prefixes = PREFIX_FWAIT; | |
8761 | break; | |
8762 | default: | |
8763 | return; | |
8764 | } | |
52b15da3 JH |
8765 | /* Rex is ignored when followed by another prefix. */ |
8766 | if (rex) | |
8767 | { | |
3e7d61b2 AM |
8768 | rex_used = rex; |
8769 | return; | |
52b15da3 JH |
8770 | } |
8771 | rex = newrex; | |
c0f3af97 | 8772 | rex_original = rex; |
252b5132 RH |
8773 | codep++; |
8774 | } | |
8775 | } | |
8776 | ||
7d421014 ILT |
8777 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
8778 | prefix byte. */ | |
8779 | ||
8780 | static const char * | |
26ca5450 | 8781 | prefix_name (int pref, int sizeflag) |
7d421014 | 8782 | { |
0003779b L |
8783 | static const char *rexes [16] = |
8784 | { | |
8785 | "rex", /* 0x40 */ | |
8786 | "rex.B", /* 0x41 */ | |
8787 | "rex.X", /* 0x42 */ | |
8788 | "rex.XB", /* 0x43 */ | |
8789 | "rex.R", /* 0x44 */ | |
8790 | "rex.RB", /* 0x45 */ | |
8791 | "rex.RX", /* 0x46 */ | |
8792 | "rex.RXB", /* 0x47 */ | |
8793 | "rex.W", /* 0x48 */ | |
8794 | "rex.WB", /* 0x49 */ | |
8795 | "rex.WX", /* 0x4a */ | |
8796 | "rex.WXB", /* 0x4b */ | |
8797 | "rex.WR", /* 0x4c */ | |
8798 | "rex.WRB", /* 0x4d */ | |
8799 | "rex.WRX", /* 0x4e */ | |
8800 | "rex.WRXB", /* 0x4f */ | |
8801 | }; | |
8802 | ||
7d421014 ILT |
8803 | switch (pref) |
8804 | { | |
52b15da3 JH |
8805 | /* REX prefixes family. */ |
8806 | case 0x40: | |
52b15da3 | 8807 | case 0x41: |
52b15da3 | 8808 | case 0x42: |
52b15da3 | 8809 | case 0x43: |
52b15da3 | 8810 | case 0x44: |
52b15da3 | 8811 | case 0x45: |
52b15da3 | 8812 | case 0x46: |
52b15da3 | 8813 | case 0x47: |
52b15da3 | 8814 | case 0x48: |
52b15da3 | 8815 | case 0x49: |
52b15da3 | 8816 | case 0x4a: |
52b15da3 | 8817 | case 0x4b: |
52b15da3 | 8818 | case 0x4c: |
52b15da3 | 8819 | case 0x4d: |
52b15da3 | 8820 | case 0x4e: |
52b15da3 | 8821 | case 0x4f: |
0003779b | 8822 | return rexes [pref - 0x40]; |
7d421014 ILT |
8823 | case 0xf3: |
8824 | return "repz"; | |
8825 | case 0xf2: | |
8826 | return "repnz"; | |
8827 | case 0xf0: | |
8828 | return "lock"; | |
8829 | case 0x2e: | |
8830 | return "cs"; | |
8831 | case 0x36: | |
8832 | return "ss"; | |
8833 | case 0x3e: | |
8834 | return "ds"; | |
8835 | case 0x26: | |
8836 | return "es"; | |
8837 | case 0x64: | |
8838 | return "fs"; | |
8839 | case 0x65: | |
8840 | return "gs"; | |
8841 | case 0x66: | |
8842 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
8843 | case 0x67: | |
cb712a9e | 8844 | if (address_mode == mode_64bit) |
db6eb5be | 8845 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 8846 | else |
2888cb7a | 8847 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
8848 | case FWAIT_OPCODE: |
8849 | return "fwait"; | |
8850 | default: | |
8851 | return NULL; | |
8852 | } | |
8853 | } | |
8854 | ||
ce518a5f L |
8855 | static char op_out[MAX_OPERANDS][100]; |
8856 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 8857 | static int two_source_ops; |
ce518a5f L |
8858 | static bfd_vma op_address[MAX_OPERANDS]; |
8859 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 8860 | static bfd_vma start_pc; |
ce518a5f | 8861 | |
252b5132 RH |
8862 | /* |
8863 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
8864 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
8865 | * section of the "Virtual 8086 Mode" chapter.) | |
8866 | * 'pc' should be the address of this instruction, it will | |
8867 | * be used to print the target address if this is a relative jump or call | |
8868 | * The function returns the length of this instruction in bytes. | |
8869 | */ | |
8870 | ||
252b5132 | 8871 | static char intel_syntax; |
9d141669 | 8872 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
8873 | static char open_char; |
8874 | static char close_char; | |
8875 | static char separator_char; | |
8876 | static char scale_char; | |
8877 | ||
e396998b AM |
8878 | /* Here for backwards compatibility. When gdb stops using |
8879 | print_insn_i386_att and print_insn_i386_intel these functions can | |
8880 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 8881 | int |
26ca5450 | 8882 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
8883 | { |
8884 | intel_syntax = 0; | |
e396998b AM |
8885 | |
8886 | return print_insn (pc, info); | |
252b5132 RH |
8887 | } |
8888 | ||
8889 | int | |
26ca5450 | 8890 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
8891 | { |
8892 | intel_syntax = 1; | |
e396998b AM |
8893 | |
8894 | return print_insn (pc, info); | |
252b5132 RH |
8895 | } |
8896 | ||
e396998b | 8897 | int |
26ca5450 | 8898 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
8899 | { |
8900 | intel_syntax = -1; | |
8901 | ||
8902 | return print_insn (pc, info); | |
8903 | } | |
8904 | ||
f59a29b9 L |
8905 | void |
8906 | print_i386_disassembler_options (FILE *stream) | |
8907 | { | |
8908 | fprintf (stream, _("\n\ | |
8909 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
8910 | with the -M switch (multiple options should be separated by commas):\n")); | |
8911 | ||
8912 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
8913 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
8914 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
8915 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
8916 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
8917 | fprintf (stream, _(" att-mnemonic\n" |
8918 | " Display instruction in AT&T mnemonic\n")); | |
8919 | fprintf (stream, _(" intel-mnemonic\n" | |
8920 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
8921 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
8922 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
8923 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
8924 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
8925 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
8926 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
8927 | } | |
8928 | ||
b844680a L |
8929 | /* Get a pointer to struct dis386 with a valid name. */ |
8930 | ||
8931 | static const struct dis386 * | |
8bb15339 | 8932 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 8933 | { |
c0f3af97 | 8934 | int index, vex_table_index; |
b844680a L |
8935 | |
8936 | if (dp->name != NULL) | |
8937 | return dp; | |
8938 | ||
8939 | switch (dp->op[0].bytemode) | |
8940 | { | |
1ceb70f8 L |
8941 | case USE_REG_TABLE: |
8942 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
8943 | break; | |
8944 | ||
8945 | case USE_MOD_TABLE: | |
8946 | index = modrm.mod == 0x3 ? 1 : 0; | |
8947 | dp = &mod_table[dp->op[1].bytemode][index]; | |
8948 | break; | |
8949 | ||
8950 | case USE_RM_TABLE: | |
8951 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
8952 | break; |
8953 | ||
4e7d34a6 | 8954 | case USE_PREFIX_TABLE: |
c0f3af97 | 8955 | if (need_vex) |
b844680a | 8956 | { |
c0f3af97 L |
8957 | /* The prefix in VEX is implicit. */ |
8958 | switch (vex.prefix) | |
8959 | { | |
8960 | case 0: | |
8961 | index = 0; | |
8962 | break; | |
8963 | case REPE_PREFIX_OPCODE: | |
8964 | index = 1; | |
8965 | break; | |
8966 | case DATA_PREFIX_OPCODE: | |
8967 | index = 2; | |
8968 | break; | |
8969 | case REPNE_PREFIX_OPCODE: | |
8970 | index = 3; | |
8971 | break; | |
8972 | default: | |
8973 | abort (); | |
8974 | break; | |
8975 | } | |
b844680a | 8976 | } |
c0f3af97 | 8977 | else |
b844680a | 8978 | { |
c0f3af97 L |
8979 | index = 0; |
8980 | used_prefixes |= (prefixes & PREFIX_REPZ); | |
8981 | if (prefixes & PREFIX_REPZ) | |
b844680a | 8982 | { |
c0f3af97 L |
8983 | index = 1; |
8984 | repz_prefix = NULL; | |
b844680a L |
8985 | } |
8986 | else | |
8987 | { | |
c0f3af97 L |
8988 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
8989 | PREFIX_DATA. */ | |
8990 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
8991 | if (prefixes & PREFIX_REPNZ) | |
8992 | { | |
8993 | index = 3; | |
8994 | repnz_prefix = NULL; | |
8995 | } | |
8996 | else | |
b844680a | 8997 | { |
c0f3af97 L |
8998 | used_prefixes |= (prefixes & PREFIX_DATA); |
8999 | if (prefixes & PREFIX_DATA) | |
9000 | { | |
9001 | index = 2; | |
9002 | data_prefix = NULL; | |
9003 | } | |
b844680a L |
9004 | } |
9005 | } | |
9006 | } | |
1ceb70f8 | 9007 | dp = &prefix_table[dp->op[1].bytemode][index]; |
b844680a L |
9008 | break; |
9009 | ||
4e7d34a6 | 9010 | case USE_X86_64_TABLE: |
b844680a L |
9011 | index = address_mode == mode_64bit ? 1 : 0; |
9012 | dp = &x86_64_table[dp->op[1].bytemode][index]; | |
9013 | break; | |
9014 | ||
4e7d34a6 | 9015 | case USE_3BYTE_TABLE: |
8bb15339 L |
9016 | FETCH_DATA (info, codep + 2); |
9017 | index = *codep++; | |
9018 | dp = &three_byte_table[dp->op[1].bytemode][index]; | |
9019 | modrm.mod = (*codep >> 6) & 3; | |
9020 | modrm.reg = (*codep >> 3) & 7; | |
9021 | modrm.rm = *codep & 7; | |
9022 | break; | |
9023 | ||
c0f3af97 L |
9024 | case USE_VEX_LEN_TABLE: |
9025 | if (!need_vex) | |
9026 | abort (); | |
9027 | ||
9028 | switch (vex.length) | |
9029 | { | |
9030 | case 128: | |
9031 | index = 0; | |
9032 | break; | |
9033 | case 256: | |
9034 | index = 1; | |
9035 | break; | |
9036 | default: | |
9037 | abort (); | |
9038 | break; | |
9039 | } | |
9040 | ||
9041 | dp = &vex_len_table[dp->op[1].bytemode][index]; | |
9042 | break; | |
9043 | ||
9044 | case USE_VEX_C4_TABLE: | |
9045 | FETCH_DATA (info, codep + 3); | |
9046 | /* All bits in the REX prefix are ignored. */ | |
9047 | rex_ignored = rex; | |
9048 | rex = ~(*codep >> 5) & 0x7; | |
9049 | switch ((*codep & 0x1f)) | |
9050 | { | |
9051 | default: | |
9052 | BadOp (); | |
9053 | case 0x1: | |
9054 | vex_table_index = 0; | |
9055 | break; | |
9056 | case 0x2: | |
9057 | vex_table_index = 1; | |
9058 | break; | |
9059 | case 0x3: | |
9060 | vex_table_index = 2; | |
9061 | break; | |
9062 | } | |
9063 | codep++; | |
9064 | vex.w = *codep & 0x80; | |
9065 | if (vex.w && address_mode == mode_64bit) | |
9066 | rex |= REX_W; | |
9067 | ||
9068 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
9069 | if (address_mode != mode_64bit | |
9070 | && vex.register_specifier > 0x7) | |
9071 | BadOp (); | |
9072 | ||
9073 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9074 | switch ((*codep & 0x3)) | |
9075 | { | |
9076 | case 0: | |
9077 | vex.prefix = 0; | |
9078 | break; | |
9079 | case 1: | |
9080 | vex.prefix = DATA_PREFIX_OPCODE; | |
9081 | break; | |
9082 | case 2: | |
9083 | vex.prefix = REPE_PREFIX_OPCODE; | |
9084 | break; | |
9085 | case 3: | |
9086 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9087 | break; | |
9088 | } | |
9089 | need_vex = 1; | |
9090 | need_vex_reg = 1; | |
9091 | codep++; | |
9092 | index = *codep++; | |
9093 | dp = &vex_table[vex_table_index][index]; | |
9094 | /* There is no MODRM byte for VEX [82|77]. */ | |
9095 | if (index != 0x77 && index != 0x82) | |
9096 | { | |
9097 | FETCH_DATA (info, codep + 1); | |
9098 | modrm.mod = (*codep >> 6) & 3; | |
9099 | modrm.reg = (*codep >> 3) & 7; | |
9100 | modrm.rm = *codep & 7; | |
9101 | } | |
9102 | break; | |
9103 | ||
9104 | case USE_VEX_C5_TABLE: | |
9105 | FETCH_DATA (info, codep + 2); | |
9106 | /* All bits in the REX prefix are ignored. */ | |
9107 | rex_ignored = rex; | |
9108 | rex = (*codep & 0x80) ? 0 : REX_R; | |
9109 | ||
9110 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
9111 | if (address_mode != mode_64bit | |
9112 | && vex.register_specifier > 0x7) | |
9113 | BadOp (); | |
9114 | ||
9115 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9116 | switch ((*codep & 0x3)) | |
9117 | { | |
9118 | case 0: | |
9119 | vex.prefix = 0; | |
9120 | break; | |
9121 | case 1: | |
9122 | vex.prefix = DATA_PREFIX_OPCODE; | |
9123 | break; | |
9124 | case 2: | |
9125 | vex.prefix = REPE_PREFIX_OPCODE; | |
9126 | break; | |
9127 | case 3: | |
9128 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9129 | break; | |
9130 | } | |
9131 | need_vex = 1; | |
9132 | need_vex_reg = 1; | |
9133 | codep++; | |
9134 | index = *codep++; | |
9135 | dp = &vex_table[dp->op[1].bytemode][index]; | |
9136 | /* There is no MODRM byte for VEX [82|77]. */ | |
9137 | if (index != 0x77 && index != 0x82) | |
9138 | { | |
9139 | FETCH_DATA (info, codep + 1); | |
9140 | modrm.mod = (*codep >> 6) & 3; | |
9141 | modrm.reg = (*codep >> 3) & 7; | |
9142 | modrm.rm = *codep & 7; | |
9143 | } | |
9144 | break; | |
9145 | ||
b844680a | 9146 | default: |
d34b5006 | 9147 | abort (); |
b844680a L |
9148 | } |
9149 | ||
9150 | if (dp->name != NULL) | |
9151 | return dp; | |
9152 | else | |
8bb15339 | 9153 | return get_valid_dis386 (dp, info); |
b844680a L |
9154 | } |
9155 | ||
e396998b | 9156 | static int |
26ca5450 | 9157 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 9158 | { |
2da11e11 | 9159 | const struct dis386 *dp; |
252b5132 | 9160 | int i; |
ce518a5f | 9161 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9162 | int needcomma; |
e396998b AM |
9163 | int sizeflag; |
9164 | const char *p; | |
252b5132 | 9165 | struct dis_private priv; |
eec0f4ca | 9166 | unsigned char op; |
b844680a L |
9167 | char prefix_obuf[32]; |
9168 | char *prefix_obufp; | |
252b5132 | 9169 | |
cb712a9e L |
9170 | if (info->mach == bfd_mach_x86_64_intel_syntax |
9171 | || info->mach == bfd_mach_x86_64) | |
9172 | address_mode = mode_64bit; | |
9173 | else | |
9174 | address_mode = mode_32bit; | |
52b15da3 | 9175 | |
8373f971 | 9176 | if (intel_syntax == (char) -1) |
e396998b AM |
9177 | intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax |
9178 | || info->mach == bfd_mach_x86_64_intel_syntax); | |
9179 | ||
2da11e11 | 9180 | if (info->mach == bfd_mach_i386_i386 |
52b15da3 JH |
9181 | || info->mach == bfd_mach_x86_64 |
9182 | || info->mach == bfd_mach_i386_i386_intel_syntax | |
9183 | || info->mach == bfd_mach_x86_64_intel_syntax) | |
e396998b | 9184 | priv.orig_sizeflag = AFLAG | DFLAG; |
2da11e11 | 9185 | else if (info->mach == bfd_mach_i386_i8086) |
e396998b | 9186 | priv.orig_sizeflag = 0; |
2da11e11 AM |
9187 | else |
9188 | abort (); | |
e396998b AM |
9189 | |
9190 | for (p = info->disassembler_options; p != NULL; ) | |
9191 | { | |
0112cd26 | 9192 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 9193 | { |
cb712a9e | 9194 | address_mode = mode_64bit; |
e396998b AM |
9195 | priv.orig_sizeflag = AFLAG | DFLAG; |
9196 | } | |
0112cd26 | 9197 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 9198 | { |
cb712a9e | 9199 | address_mode = mode_32bit; |
e396998b AM |
9200 | priv.orig_sizeflag = AFLAG | DFLAG; |
9201 | } | |
0112cd26 | 9202 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 9203 | { |
cb712a9e | 9204 | address_mode = mode_16bit; |
e396998b AM |
9205 | priv.orig_sizeflag = 0; |
9206 | } | |
0112cd26 | 9207 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
9208 | { |
9209 | intel_syntax = 1; | |
9d141669 L |
9210 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
9211 | intel_mnemonic = 1; | |
e396998b | 9212 | } |
0112cd26 | 9213 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
9214 | { |
9215 | intel_syntax = 0; | |
9d141669 L |
9216 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
9217 | intel_mnemonic = 0; | |
e396998b | 9218 | } |
0112cd26 | 9219 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 9220 | { |
f59a29b9 L |
9221 | if (address_mode == mode_64bit) |
9222 | { | |
9223 | if (p[4] == '3' && p[5] == '2') | |
9224 | priv.orig_sizeflag &= ~AFLAG; | |
9225 | else if (p[4] == '6' && p[5] == '4') | |
9226 | priv.orig_sizeflag |= AFLAG; | |
9227 | } | |
9228 | else | |
9229 | { | |
9230 | if (p[4] == '1' && p[5] == '6') | |
9231 | priv.orig_sizeflag &= ~AFLAG; | |
9232 | else if (p[4] == '3' && p[5] == '2') | |
9233 | priv.orig_sizeflag |= AFLAG; | |
9234 | } | |
e396998b | 9235 | } |
0112cd26 | 9236 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
9237 | { |
9238 | if (p[4] == '1' && p[5] == '6') | |
9239 | priv.orig_sizeflag &= ~DFLAG; | |
9240 | else if (p[4] == '3' && p[5] == '2') | |
9241 | priv.orig_sizeflag |= DFLAG; | |
9242 | } | |
0112cd26 | 9243 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
9244 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9245 | ||
9246 | p = strchr (p, ','); | |
9247 | if (p != NULL) | |
9248 | p++; | |
9249 | } | |
9250 | ||
9251 | if (intel_syntax) | |
9252 | { | |
9253 | names64 = intel_names64; | |
9254 | names32 = intel_names32; | |
9255 | names16 = intel_names16; | |
9256 | names8 = intel_names8; | |
9257 | names8rex = intel_names8rex; | |
9258 | names_seg = intel_names_seg; | |
db51cc60 L |
9259 | index64 = intel_index64; |
9260 | index32 = intel_index32; | |
e396998b AM |
9261 | index16 = intel_index16; |
9262 | open_char = '['; | |
9263 | close_char = ']'; | |
9264 | separator_char = '+'; | |
9265 | scale_char = '*'; | |
9266 | } | |
9267 | else | |
9268 | { | |
9269 | names64 = att_names64; | |
9270 | names32 = att_names32; | |
9271 | names16 = att_names16; | |
9272 | names8 = att_names8; | |
9273 | names8rex = att_names8rex; | |
9274 | names_seg = att_names_seg; | |
db51cc60 L |
9275 | index64 = att_index64; |
9276 | index32 = att_index32; | |
e396998b AM |
9277 | index16 = att_index16; |
9278 | open_char = '('; | |
9279 | close_char = ')'; | |
9280 | separator_char = ','; | |
9281 | scale_char = ','; | |
9282 | } | |
2da11e11 | 9283 | |
4fe53c98 | 9284 | /* The output looks better if we put 7 bytes on a line, since that |
c608c12e | 9285 | puts most long word instructions on a single line. */ |
4fe53c98 | 9286 | info->bytes_per_line = 7; |
252b5132 | 9287 | |
26ca5450 | 9288 | info->private_data = &priv; |
252b5132 RH |
9289 | priv.max_fetched = priv.the_buffer; |
9290 | priv.insn_start = pc; | |
252b5132 RH |
9291 | |
9292 | obuf[0] = 0; | |
ce518a5f L |
9293 | for (i = 0; i < MAX_OPERANDS; ++i) |
9294 | { | |
9295 | op_out[i][0] = 0; | |
9296 | op_index[i] = -1; | |
9297 | } | |
252b5132 RH |
9298 | |
9299 | the_info = info; | |
9300 | start_pc = pc; | |
e396998b AM |
9301 | start_codep = priv.the_buffer; |
9302 | codep = priv.the_buffer; | |
252b5132 | 9303 | |
5076851f ILT |
9304 | if (setjmp (priv.bailout) != 0) |
9305 | { | |
7d421014 ILT |
9306 | const char *name; |
9307 | ||
5076851f | 9308 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
9309 | means we have an incomplete instruction of some sort. Just |
9310 | print the first byte as a prefix or a .byte pseudo-op. */ | |
9311 | if (codep > priv.the_buffer) | |
5076851f | 9312 | { |
e396998b | 9313 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9314 | if (name != NULL) |
9315 | (*info->fprintf_func) (info->stream, "%s", name); | |
9316 | else | |
5076851f | 9317 | { |
7d421014 ILT |
9318 | /* Just print the first byte as a .byte instruction. */ |
9319 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 9320 | (unsigned int) priv.the_buffer[0]); |
5076851f | 9321 | } |
5076851f | 9322 | |
7d421014 | 9323 | return 1; |
5076851f ILT |
9324 | } |
9325 | ||
9326 | return -1; | |
9327 | } | |
9328 | ||
52b15da3 | 9329 | obufp = obuf; |
252b5132 RH |
9330 | ckprefix (); |
9331 | ||
9332 | insn_codep = codep; | |
e396998b | 9333 | sizeflag = priv.orig_sizeflag; |
252b5132 RH |
9334 | |
9335 | FETCH_DATA (info, codep + 1); | |
9336 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
9337 | ||
3e7d61b2 AM |
9338 | if (((prefixes & PREFIX_FWAIT) |
9339 | && ((*codep < 0xd8) || (*codep > 0xdf))) | |
9340 | || (rex && rex_used)) | |
252b5132 | 9341 | { |
7d421014 ILT |
9342 | const char *name; |
9343 | ||
3e7d61b2 AM |
9344 | /* fwait not followed by floating point instruction, or rex followed |
9345 | by other prefixes. Print the first prefix. */ | |
e396998b | 9346 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9347 | if (name == NULL) |
9348 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9349 | (*info->fprintf_func) (info->stream, "%s", name); | |
9350 | return 1; | |
252b5132 RH |
9351 | } |
9352 | ||
eec0f4ca | 9353 | op = 0; |
c1e679ec | 9354 | |
252b5132 RH |
9355 | if (*codep == 0x0f) |
9356 | { | |
eec0f4ca | 9357 | unsigned char threebyte; |
252b5132 | 9358 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
9359 | threebyte = *++codep; |
9360 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 9361 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 9362 | codep++; |
252b5132 RH |
9363 | } |
9364 | else | |
9365 | { | |
6439fc28 | 9366 | dp = &dis386[*codep]; |
252b5132 | 9367 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 9368 | codep++; |
252b5132 | 9369 | } |
246c51aa | 9370 | |
b844680a | 9371 | if ((prefixes & PREFIX_REPZ)) |
7d421014 | 9372 | { |
b844680a | 9373 | repz_prefix = "repz "; |
7d421014 ILT |
9374 | used_prefixes |= PREFIX_REPZ; |
9375 | } | |
b844680a L |
9376 | else |
9377 | repz_prefix = NULL; | |
9378 | ||
9379 | if ((prefixes & PREFIX_REPNZ)) | |
7d421014 | 9380 | { |
b844680a | 9381 | repnz_prefix = "repnz "; |
7d421014 ILT |
9382 | used_prefixes |= PREFIX_REPNZ; |
9383 | } | |
b844680a L |
9384 | else |
9385 | repnz_prefix = NULL; | |
050dfa73 | 9386 | |
b844680a | 9387 | if ((prefixes & PREFIX_LOCK)) |
7d421014 | 9388 | { |
b844680a | 9389 | lock_prefix = "lock "; |
7d421014 ILT |
9390 | used_prefixes |= PREFIX_LOCK; |
9391 | } | |
b844680a L |
9392 | else |
9393 | lock_prefix = NULL; | |
c608c12e | 9394 | |
b844680a | 9395 | addr_prefix = NULL; |
c608c12e AM |
9396 | if (prefixes & PREFIX_ADDR) |
9397 | { | |
9398 | sizeflag ^= AFLAG; | |
ce518a5f | 9399 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 9400 | { |
cb712a9e | 9401 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
b844680a | 9402 | addr_prefix = "addr32 "; |
3ffd33cf | 9403 | else |
b844680a | 9404 | addr_prefix = "addr16 "; |
3ffd33cf AM |
9405 | used_prefixes |= PREFIX_ADDR; |
9406 | } | |
9407 | } | |
9408 | ||
b844680a L |
9409 | data_prefix = NULL; |
9410 | if ((prefixes & PREFIX_DATA)) | |
3ffd33cf AM |
9411 | { |
9412 | sizeflag ^= DFLAG; | |
ce518a5f L |
9413 | if (dp->op[2].bytemode == cond_jump_mode |
9414 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 9415 | && !intel_syntax) |
3ffd33cf AM |
9416 | { |
9417 | if (sizeflag & DFLAG) | |
b844680a | 9418 | data_prefix = "data32 "; |
3ffd33cf | 9419 | else |
b844680a | 9420 | data_prefix = "data16 "; |
3ffd33cf AM |
9421 | used_prefixes |= PREFIX_DATA; |
9422 | } | |
9423 | } | |
9424 | ||
8bb15339 | 9425 | if (need_modrm) |
252b5132 RH |
9426 | { |
9427 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
9428 | modrm.mod = (*codep >> 6) & 3; |
9429 | modrm.reg = (*codep >> 3) & 7; | |
9430 | modrm.rm = *codep & 7; | |
252b5132 RH |
9431 | } |
9432 | ||
ce518a5f | 9433 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 RH |
9434 | { |
9435 | dofloat (sizeflag); | |
9436 | } | |
9437 | else | |
9438 | { | |
c0f3af97 L |
9439 | need_vex = 0; |
9440 | need_vex_reg = 0; | |
dae39acc | 9441 | vex_w_done = 0; |
8bb15339 | 9442 | dp = get_valid_dis386 (dp, info); |
b844680a | 9443 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
ce518a5f L |
9444 | { |
9445 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9446 | { | |
246c51aa | 9447 | obufp = op_out[i]; |
ce518a5f L |
9448 | op_ad = MAX_OPERANDS - 1 - i; |
9449 | if (dp->op[i].rtn) | |
9450 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
9451 | } | |
6439fc28 | 9452 | } |
252b5132 RH |
9453 | } |
9454 | ||
7d421014 ILT |
9455 | /* See if any prefixes were not used. If so, print the first one |
9456 | separately. If we don't do this, we'll wind up printing an | |
9457 | instruction stream which does not precisely correspond to the | |
9458 | bytes we are disassembling. */ | |
9459 | if ((prefixes & ~used_prefixes) != 0) | |
9460 | { | |
9461 | const char *name; | |
9462 | ||
e396998b | 9463 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9464 | if (name == NULL) |
9465 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9466 | (*info->fprintf_func) (info->stream, "%s", name); | |
9467 | return 1; | |
9468 | } | |
c0f3af97 | 9469 | if ((rex_original & ~rex_used) || rex_ignored) |
52b15da3 JH |
9470 | { |
9471 | const char *name; | |
c0f3af97 | 9472 | name = prefix_name (rex_original, priv.orig_sizeflag); |
52b15da3 JH |
9473 | if (name == NULL) |
9474 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9475 | (*info->fprintf_func) (info->stream, "%s ", name); | |
9476 | } | |
7d421014 | 9477 | |
b844680a L |
9478 | prefix_obuf[0] = 0; |
9479 | prefix_obufp = prefix_obuf; | |
9480 | if (lock_prefix) | |
9481 | prefix_obufp = stpcpy (prefix_obufp, lock_prefix); | |
9482 | if (repz_prefix) | |
9483 | prefix_obufp = stpcpy (prefix_obufp, repz_prefix); | |
9484 | if (repnz_prefix) | |
9485 | prefix_obufp = stpcpy (prefix_obufp, repnz_prefix); | |
9486 | if (addr_prefix) | |
9487 | prefix_obufp = stpcpy (prefix_obufp, addr_prefix); | |
9488 | if (data_prefix) | |
9489 | prefix_obufp = stpcpy (prefix_obufp, data_prefix); | |
9490 | ||
9491 | if (prefix_obuf[0] != 0) | |
9492 | (*info->fprintf_func) (info->stream, "%s", prefix_obuf); | |
9493 | ||
ea397f5b | 9494 | obufp = mnemonicendp; |
b844680a | 9495 | for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++) |
252b5132 RH |
9496 | oappend (" "); |
9497 | oappend (" "); | |
9498 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
9499 | ||
9500 | /* The enter and bound instructions are printed with operands in the same | |
9501 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 9502 | if (intel_syntax || two_source_ops) |
252b5132 | 9503 | { |
185b1163 L |
9504 | bfd_vma riprel; |
9505 | ||
ce518a5f L |
9506 | for (i = 0; i < MAX_OPERANDS; ++i) |
9507 | op_txt[i] = op_out[i]; | |
246c51aa | 9508 | |
ce518a5f L |
9509 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
9510 | { | |
9511 | op_ad = op_index[i]; | |
9512 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
9513 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
9514 | riprel = op_riprel[i]; |
9515 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
9516 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 9517 | } |
252b5132 RH |
9518 | } |
9519 | else | |
9520 | { | |
ce518a5f L |
9521 | for (i = 0; i < MAX_OPERANDS; ++i) |
9522 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; | |
050dfa73 MM |
9523 | } |
9524 | ||
ce518a5f L |
9525 | needcomma = 0; |
9526 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9527 | if (*op_txt[i]) | |
9528 | { | |
9529 | if (needcomma) | |
9530 | (*info->fprintf_func) (info->stream, ","); | |
9531 | if (op_index[i] != -1 && !op_riprel[i]) | |
9532 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
9533 | else | |
9534 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
9535 | needcomma = 1; | |
9536 | } | |
050dfa73 | 9537 | |
ce518a5f | 9538 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
9539 | if (op_index[i] != -1 && op_riprel[i]) |
9540 | { | |
9541 | (*info->fprintf_func) (info->stream, " # "); | |
9542 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
9543 | + op_address[op_index[i]]), info); | |
185b1163 | 9544 | break; |
52b15da3 | 9545 | } |
e396998b | 9546 | return codep - priv.the_buffer; |
252b5132 RH |
9547 | } |
9548 | ||
6439fc28 | 9549 | static const char *float_mem[] = { |
252b5132 | 9550 | /* d8 */ |
7c52e0e8 L |
9551 | "fadd{s|}", |
9552 | "fmul{s|}", | |
9553 | "fcom{s|}", | |
9554 | "fcomp{s|}", | |
9555 | "fsub{s|}", | |
9556 | "fsubr{s|}", | |
9557 | "fdiv{s|}", | |
9558 | "fdivr{s|}", | |
db6eb5be | 9559 | /* d9 */ |
7c52e0e8 | 9560 | "fld{s|}", |
252b5132 | 9561 | "(bad)", |
7c52e0e8 L |
9562 | "fst{s|}", |
9563 | "fstp{s|}", | |
9306ca4a | 9564 | "fldenvIC", |
252b5132 | 9565 | "fldcw", |
9306ca4a | 9566 | "fNstenvIC", |
252b5132 RH |
9567 | "fNstcw", |
9568 | /* da */ | |
7c52e0e8 L |
9569 | "fiadd{l|}", |
9570 | "fimul{l|}", | |
9571 | "ficom{l|}", | |
9572 | "ficomp{l|}", | |
9573 | "fisub{l|}", | |
9574 | "fisubr{l|}", | |
9575 | "fidiv{l|}", | |
9576 | "fidivr{l|}", | |
252b5132 | 9577 | /* db */ |
7c52e0e8 L |
9578 | "fild{l|}", |
9579 | "fisttp{l|}", | |
9580 | "fist{l|}", | |
9581 | "fistp{l|}", | |
252b5132 | 9582 | "(bad)", |
6439fc28 | 9583 | "fld{t||t|}", |
252b5132 | 9584 | "(bad)", |
6439fc28 | 9585 | "fstp{t||t|}", |
252b5132 | 9586 | /* dc */ |
7c52e0e8 L |
9587 | "fadd{l|}", |
9588 | "fmul{l|}", | |
9589 | "fcom{l|}", | |
9590 | "fcomp{l|}", | |
9591 | "fsub{l|}", | |
9592 | "fsubr{l|}", | |
9593 | "fdiv{l|}", | |
9594 | "fdivr{l|}", | |
252b5132 | 9595 | /* dd */ |
7c52e0e8 L |
9596 | "fld{l|}", |
9597 | "fisttp{ll|}", | |
9598 | "fst{l||}", | |
9599 | "fstp{l|}", | |
9306ca4a | 9600 | "frstorIC", |
252b5132 | 9601 | "(bad)", |
9306ca4a | 9602 | "fNsaveIC", |
252b5132 RH |
9603 | "fNstsw", |
9604 | /* de */ | |
9605 | "fiadd", | |
9606 | "fimul", | |
9607 | "ficom", | |
9608 | "ficomp", | |
9609 | "fisub", | |
9610 | "fisubr", | |
9611 | "fidiv", | |
9612 | "fidivr", | |
9613 | /* df */ | |
9614 | "fild", | |
ca164297 | 9615 | "fisttp", |
252b5132 RH |
9616 | "fist", |
9617 | "fistp", | |
9618 | "fbld", | |
7c52e0e8 | 9619 | "fild{ll|}", |
252b5132 | 9620 | "fbstp", |
7c52e0e8 | 9621 | "fistp{ll|}", |
1d9f512f AM |
9622 | }; |
9623 | ||
9624 | static const unsigned char float_mem_mode[] = { | |
9625 | /* d8 */ | |
9626 | d_mode, | |
9627 | d_mode, | |
9628 | d_mode, | |
9629 | d_mode, | |
9630 | d_mode, | |
9631 | d_mode, | |
9632 | d_mode, | |
9633 | d_mode, | |
9634 | /* d9 */ | |
9635 | d_mode, | |
9636 | 0, | |
9637 | d_mode, | |
9638 | d_mode, | |
9639 | 0, | |
9640 | w_mode, | |
9641 | 0, | |
9642 | w_mode, | |
9643 | /* da */ | |
9644 | d_mode, | |
9645 | d_mode, | |
9646 | d_mode, | |
9647 | d_mode, | |
9648 | d_mode, | |
9649 | d_mode, | |
9650 | d_mode, | |
9651 | d_mode, | |
9652 | /* db */ | |
9653 | d_mode, | |
9654 | d_mode, | |
9655 | d_mode, | |
9656 | d_mode, | |
9657 | 0, | |
9306ca4a | 9658 | t_mode, |
1d9f512f | 9659 | 0, |
9306ca4a | 9660 | t_mode, |
1d9f512f AM |
9661 | /* dc */ |
9662 | q_mode, | |
9663 | q_mode, | |
9664 | q_mode, | |
9665 | q_mode, | |
9666 | q_mode, | |
9667 | q_mode, | |
9668 | q_mode, | |
9669 | q_mode, | |
9670 | /* dd */ | |
9671 | q_mode, | |
9672 | q_mode, | |
9673 | q_mode, | |
9674 | q_mode, | |
9675 | 0, | |
9676 | 0, | |
9677 | 0, | |
9678 | w_mode, | |
9679 | /* de */ | |
9680 | w_mode, | |
9681 | w_mode, | |
9682 | w_mode, | |
9683 | w_mode, | |
9684 | w_mode, | |
9685 | w_mode, | |
9686 | w_mode, | |
9687 | w_mode, | |
9688 | /* df */ | |
9689 | w_mode, | |
9690 | w_mode, | |
9691 | w_mode, | |
9692 | w_mode, | |
9306ca4a | 9693 | t_mode, |
1d9f512f | 9694 | q_mode, |
9306ca4a | 9695 | t_mode, |
1d9f512f | 9696 | q_mode |
252b5132 RH |
9697 | }; |
9698 | ||
ce518a5f L |
9699 | #define ST { OP_ST, 0 } |
9700 | #define STi { OP_STi, 0 } | |
252b5132 | 9701 | |
4efba78c L |
9702 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
9703 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
9704 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
9705 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
9706 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
9707 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
9708 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
9709 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
9710 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 9711 | |
2da11e11 | 9712 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
9713 | /* d8 */ |
9714 | { | |
ce518a5f L |
9715 | { "fadd", { ST, STi } }, |
9716 | { "fmul", { ST, STi } }, | |
9717 | { "fcom", { STi } }, | |
9718 | { "fcomp", { STi } }, | |
9719 | { "fsub", { ST, STi } }, | |
9720 | { "fsubr", { ST, STi } }, | |
9721 | { "fdiv", { ST, STi } }, | |
9722 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
9723 | }, |
9724 | /* d9 */ | |
9725 | { | |
ce518a5f L |
9726 | { "fld", { STi } }, |
9727 | { "fxch", { STi } }, | |
252b5132 | 9728 | { FGRPd9_2 }, |
ce518a5f | 9729 | { "(bad)", { XX } }, |
252b5132 RH |
9730 | { FGRPd9_4 }, |
9731 | { FGRPd9_5 }, | |
9732 | { FGRPd9_6 }, | |
9733 | { FGRPd9_7 }, | |
9734 | }, | |
9735 | /* da */ | |
9736 | { | |
ce518a5f L |
9737 | { "fcmovb", { ST, STi } }, |
9738 | { "fcmove", { ST, STi } }, | |
9739 | { "fcmovbe",{ ST, STi } }, | |
9740 | { "fcmovu", { ST, STi } }, | |
9741 | { "(bad)", { XX } }, | |
252b5132 | 9742 | { FGRPda_5 }, |
ce518a5f L |
9743 | { "(bad)", { XX } }, |
9744 | { "(bad)", { XX } }, | |
252b5132 RH |
9745 | }, |
9746 | /* db */ | |
9747 | { | |
ce518a5f L |
9748 | { "fcmovnb",{ ST, STi } }, |
9749 | { "fcmovne",{ ST, STi } }, | |
9750 | { "fcmovnbe",{ ST, STi } }, | |
9751 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 9752 | { FGRPdb_4 }, |
ce518a5f L |
9753 | { "fucomi", { ST, STi } }, |
9754 | { "fcomi", { ST, STi } }, | |
9755 | { "(bad)", { XX } }, | |
252b5132 RH |
9756 | }, |
9757 | /* dc */ | |
9758 | { | |
ce518a5f L |
9759 | { "fadd", { STi, ST } }, |
9760 | { "fmul", { STi, ST } }, | |
9761 | { "(bad)", { XX } }, | |
9762 | { "(bad)", { XX } }, | |
9d141669 L |
9763 | { "fsub!M", { STi, ST } }, |
9764 | { "fsubM", { STi, ST } }, | |
9765 | { "fdiv!M", { STi, ST } }, | |
9766 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
9767 | }, |
9768 | /* dd */ | |
9769 | { | |
ce518a5f L |
9770 | { "ffree", { STi } }, |
9771 | { "(bad)", { XX } }, | |
9772 | { "fst", { STi } }, | |
9773 | { "fstp", { STi } }, | |
9774 | { "fucom", { STi } }, | |
9775 | { "fucomp", { STi } }, | |
9776 | { "(bad)", { XX } }, | |
9777 | { "(bad)", { XX } }, | |
252b5132 RH |
9778 | }, |
9779 | /* de */ | |
9780 | { | |
ce518a5f L |
9781 | { "faddp", { STi, ST } }, |
9782 | { "fmulp", { STi, ST } }, | |
9783 | { "(bad)", { XX } }, | |
252b5132 | 9784 | { FGRPde_3 }, |
9d141669 L |
9785 | { "fsub!Mp", { STi, ST } }, |
9786 | { "fsubMp", { STi, ST } }, | |
9787 | { "fdiv!Mp", { STi, ST } }, | |
9788 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
9789 | }, |
9790 | /* df */ | |
9791 | { | |
ce518a5f L |
9792 | { "ffreep", { STi } }, |
9793 | { "(bad)", { XX } }, | |
9794 | { "(bad)", { XX } }, | |
9795 | { "(bad)", { XX } }, | |
252b5132 | 9796 | { FGRPdf_4 }, |
ce518a5f L |
9797 | { "fucomip", { ST, STi } }, |
9798 | { "fcomip", { ST, STi } }, | |
9799 | { "(bad)", { XX } }, | |
252b5132 RH |
9800 | }, |
9801 | }; | |
9802 | ||
252b5132 RH |
9803 | static char *fgrps[][8] = { |
9804 | /* d9_2 0 */ | |
9805 | { | |
9806 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9807 | }, | |
9808 | ||
9809 | /* d9_4 1 */ | |
9810 | { | |
9811 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
9812 | }, | |
9813 | ||
9814 | /* d9_5 2 */ | |
9815 | { | |
9816 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
9817 | }, | |
9818 | ||
9819 | /* d9_6 3 */ | |
9820 | { | |
9821 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
9822 | }, | |
9823 | ||
9824 | /* d9_7 4 */ | |
9825 | { | |
9826 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
9827 | }, | |
9828 | ||
9829 | /* da_5 5 */ | |
9830 | { | |
9831 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9832 | }, | |
9833 | ||
9834 | /* db_4 6 */ | |
9835 | { | |
9836 | "feni(287 only)","fdisi(287 only)","fNclex","fNinit", | |
9837 | "fNsetpm(287 only)","(bad)","(bad)","(bad)", | |
9838 | }, | |
9839 | ||
9840 | /* de_3 7 */ | |
9841 | { | |
9842 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9843 | }, | |
9844 | ||
9845 | /* df_4 8 */ | |
9846 | { | |
9847 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9848 | }, | |
9849 | }; | |
9850 | ||
b6169b20 L |
9851 | static void |
9852 | swap_operand (void) | |
9853 | { | |
9854 | mnemonicendp[0] = '.'; | |
9855 | mnemonicendp[1] = 's'; | |
9856 | mnemonicendp += 2; | |
9857 | } | |
9858 | ||
b844680a L |
9859 | static void |
9860 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
9861 | int sizeflag ATTRIBUTE_UNUSED) | |
9862 | { | |
9863 | /* Skip mod/rm byte. */ | |
9864 | MODRM_CHECK; | |
9865 | codep++; | |
9866 | } | |
9867 | ||
252b5132 | 9868 | static void |
26ca5450 | 9869 | dofloat (int sizeflag) |
252b5132 | 9870 | { |
2da11e11 | 9871 | const struct dis386 *dp; |
252b5132 RH |
9872 | unsigned char floatop; |
9873 | ||
9874 | floatop = codep[-1]; | |
9875 | ||
7967e09e | 9876 | if (modrm.mod != 3) |
252b5132 | 9877 | { |
7967e09e | 9878 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
9879 | |
9880 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 9881 | obufp = op_out[0]; |
6e50d963 | 9882 | op_ad = 2; |
1d9f512f | 9883 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
9884 | return; |
9885 | } | |
6608db57 | 9886 | /* Skip mod/rm byte. */ |
4bba6815 | 9887 | MODRM_CHECK; |
252b5132 RH |
9888 | codep++; |
9889 | ||
7967e09e | 9890 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
9891 | if (dp->name == NULL) |
9892 | { | |
7967e09e | 9893 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 9894 | |
6608db57 | 9895 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 9896 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 9897 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
9898 | } |
9899 | else | |
9900 | { | |
9901 | putop (dp->name, sizeflag); | |
9902 | ||
ce518a5f | 9903 | obufp = op_out[0]; |
6e50d963 | 9904 | op_ad = 2; |
ce518a5f L |
9905 | if (dp->op[0].rtn) |
9906 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 9907 | |
ce518a5f | 9908 | obufp = op_out[1]; |
6e50d963 | 9909 | op_ad = 1; |
ce518a5f L |
9910 | if (dp->op[1].rtn) |
9911 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
9912 | } |
9913 | } | |
9914 | ||
252b5132 | 9915 | static void |
26ca5450 | 9916 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 9917 | { |
422673a9 | 9918 | oappend ("%st" + intel_syntax); |
252b5132 RH |
9919 | } |
9920 | ||
252b5132 | 9921 | static void |
26ca5450 | 9922 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 9923 | { |
7967e09e | 9924 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 9925 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
9926 | } |
9927 | ||
6608db57 | 9928 | /* Capital letters in template are macros. */ |
6439fc28 | 9929 | static int |
26ca5450 | 9930 | putop (const char *template, int sizeflag) |
252b5132 | 9931 | { |
2da11e11 | 9932 | const char *p; |
9306ca4a | 9933 | int alt = 0; |
9d141669 | 9934 | int cond = 1; |
98b528ac L |
9935 | unsigned int l = 0, len = 1; |
9936 | char last[4]; | |
9937 | ||
9938 | #define SAVE_LAST(c) \ | |
9939 | if (l < len && l < sizeof (last)) \ | |
9940 | last[l++] = c; \ | |
9941 | else \ | |
9942 | abort (); | |
252b5132 RH |
9943 | |
9944 | for (p = template; *p; p++) | |
9945 | { | |
9946 | switch (*p) | |
9947 | { | |
9948 | default: | |
9949 | *obufp++ = *p; | |
9950 | break; | |
98b528ac L |
9951 | case '%': |
9952 | len++; | |
9953 | break; | |
9d141669 L |
9954 | case '!': |
9955 | cond = 0; | |
9956 | break; | |
6439fc28 AM |
9957 | case '{': |
9958 | alt = 0; | |
9959 | if (intel_syntax) | |
6439fc28 AM |
9960 | { |
9961 | while (*++p != '|') | |
7c52e0e8 L |
9962 | if (*p == '}' || *p == '\0') |
9963 | abort (); | |
6439fc28 | 9964 | } |
9306ca4a JB |
9965 | /* Fall through. */ |
9966 | case 'I': | |
9967 | alt = 1; | |
9968 | continue; | |
6439fc28 AM |
9969 | case '|': |
9970 | while (*++p != '}') | |
9971 | { | |
9972 | if (*p == '\0') | |
9973 | abort (); | |
9974 | } | |
9975 | break; | |
9976 | case '}': | |
9977 | break; | |
252b5132 | 9978 | case 'A': |
db6eb5be AM |
9979 | if (intel_syntax) |
9980 | break; | |
7967e09e | 9981 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
9982 | *obufp++ = 'b'; |
9983 | break; | |
9984 | case 'B': | |
db6eb5be AM |
9985 | if (intel_syntax) |
9986 | break; | |
252b5132 RH |
9987 | if (sizeflag & SUFFIX_ALWAYS) |
9988 | *obufp++ = 'b'; | |
252b5132 | 9989 | break; |
9306ca4a JB |
9990 | case 'C': |
9991 | if (intel_syntax && !alt) | |
9992 | break; | |
9993 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
9994 | { | |
9995 | if (sizeflag & DFLAG) | |
9996 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
9997 | else | |
9998 | *obufp++ = intel_syntax ? 'w' : 's'; | |
9999 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10000 | } | |
10001 | break; | |
ed7841b3 JB |
10002 | case 'D': |
10003 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
10004 | break; | |
161a04f6 | 10005 | USED_REX (REX_W); |
7967e09e | 10006 | if (modrm.mod == 3) |
ed7841b3 | 10007 | { |
161a04f6 | 10008 | if (rex & REX_W) |
ed7841b3 JB |
10009 | *obufp++ = 'q'; |
10010 | else if (sizeflag & DFLAG) | |
10011 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10012 | else | |
10013 | *obufp++ = 'w'; | |
10014 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10015 | } | |
10016 | else | |
10017 | *obufp++ = 'w'; | |
10018 | break; | |
252b5132 | 10019 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 10020 | if (address_mode == mode_64bit) |
c1a64871 JH |
10021 | { |
10022 | if (sizeflag & AFLAG) | |
10023 | *obufp++ = 'r'; | |
10024 | else | |
10025 | *obufp++ = 'e'; | |
10026 | } | |
10027 | else | |
10028 | if (sizeflag & AFLAG) | |
10029 | *obufp++ = 'e'; | |
3ffd33cf AM |
10030 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10031 | break; | |
10032 | case 'F': | |
db6eb5be AM |
10033 | if (intel_syntax) |
10034 | break; | |
e396998b | 10035 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10036 | { |
10037 | if (sizeflag & AFLAG) | |
cb712a9e | 10038 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10039 | else |
cb712a9e | 10040 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
10041 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10042 | } | |
252b5132 | 10043 | break; |
52fd6d94 JB |
10044 | case 'G': |
10045 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
10046 | break; | |
161a04f6 | 10047 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10048 | *obufp++ = 'l'; |
10049 | else | |
10050 | *obufp++ = 'w'; | |
161a04f6 | 10051 | if (!(rex & REX_W)) |
52fd6d94 JB |
10052 | used_prefixes |= (prefixes & PREFIX_DATA); |
10053 | break; | |
5dd0794d | 10054 | case 'H': |
db6eb5be AM |
10055 | if (intel_syntax) |
10056 | break; | |
5dd0794d AM |
10057 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10058 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
10059 | { | |
10060 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
10061 | *obufp++ = ','; | |
10062 | *obufp++ = 'p'; | |
10063 | if (prefixes & PREFIX_DS) | |
10064 | *obufp++ = 't'; | |
10065 | else | |
10066 | *obufp++ = 'n'; | |
10067 | } | |
10068 | break; | |
9306ca4a JB |
10069 | case 'J': |
10070 | if (intel_syntax) | |
10071 | break; | |
10072 | *obufp++ = 'l'; | |
10073 | break; | |
42903f7f L |
10074 | case 'K': |
10075 | USED_REX (REX_W); | |
10076 | if (rex & REX_W) | |
10077 | *obufp++ = 'q'; | |
10078 | else | |
10079 | *obufp++ = 'd'; | |
10080 | break; | |
6dd5059a L |
10081 | case 'Z': |
10082 | if (intel_syntax) | |
10083 | break; | |
10084 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
10085 | { | |
10086 | *obufp++ = 'q'; | |
10087 | break; | |
10088 | } | |
10089 | /* Fall through. */ | |
98b528ac | 10090 | goto case_L; |
252b5132 | 10091 | case 'L': |
98b528ac L |
10092 | if (l != 0 || len != 1) |
10093 | { | |
10094 | SAVE_LAST (*p); | |
10095 | break; | |
10096 | } | |
10097 | case_L: | |
db6eb5be AM |
10098 | if (intel_syntax) |
10099 | break; | |
252b5132 RH |
10100 | if (sizeflag & SUFFIX_ALWAYS) |
10101 | *obufp++ = 'l'; | |
252b5132 | 10102 | break; |
9d141669 L |
10103 | case 'M': |
10104 | if (intel_mnemonic != cond) | |
10105 | *obufp++ = 'r'; | |
10106 | break; | |
252b5132 RH |
10107 | case 'N': |
10108 | if ((prefixes & PREFIX_FWAIT) == 0) | |
10109 | *obufp++ = 'n'; | |
7d421014 ILT |
10110 | else |
10111 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 10112 | break; |
52b15da3 | 10113 | case 'O': |
161a04f6 L |
10114 | USED_REX (REX_W); |
10115 | if (rex & REX_W) | |
6439fc28 | 10116 | *obufp++ = 'o'; |
a35ca55a JB |
10117 | else if (intel_syntax && (sizeflag & DFLAG)) |
10118 | *obufp++ = 'q'; | |
52b15da3 JH |
10119 | else |
10120 | *obufp++ = 'd'; | |
161a04f6 | 10121 | if (!(rex & REX_W)) |
a35ca55a | 10122 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 10123 | break; |
6439fc28 | 10124 | case 'T': |
db6eb5be AM |
10125 | if (intel_syntax) |
10126 | break; | |
cb712a9e | 10127 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
10128 | { |
10129 | *obufp++ = 'q'; | |
10130 | break; | |
10131 | } | |
6608db57 | 10132 | /* Fall through. */ |
252b5132 | 10133 | case 'P': |
db6eb5be AM |
10134 | if (intel_syntax) |
10135 | break; | |
252b5132 | 10136 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 10137 | || (rex & REX_W) |
e396998b | 10138 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 10139 | { |
161a04f6 L |
10140 | USED_REX (REX_W); |
10141 | if (rex & REX_W) | |
52b15da3 | 10142 | *obufp++ = 'q'; |
c2419411 | 10143 | else |
52b15da3 JH |
10144 | { |
10145 | if (sizeflag & DFLAG) | |
10146 | *obufp++ = 'l'; | |
10147 | else | |
10148 | *obufp++ = 'w'; | |
52b15da3 | 10149 | } |
1a114b12 | 10150 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
10151 | } |
10152 | break; | |
6439fc28 | 10153 | case 'U': |
db6eb5be AM |
10154 | if (intel_syntax) |
10155 | break; | |
cb712a9e | 10156 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 | 10157 | { |
7967e09e | 10158 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 10159 | *obufp++ = 'q'; |
6439fc28 AM |
10160 | break; |
10161 | } | |
6608db57 | 10162 | /* Fall through. */ |
98b528ac | 10163 | goto case_Q; |
252b5132 | 10164 | case 'Q': |
98b528ac | 10165 | if (l == 0 && len == 1) |
252b5132 | 10166 | { |
98b528ac L |
10167 | case_Q: |
10168 | if (intel_syntax && !alt) | |
10169 | break; | |
10170 | USED_REX (REX_W); | |
10171 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10172 | { |
98b528ac L |
10173 | if (rex & REX_W) |
10174 | *obufp++ = 'q'; | |
52b15da3 | 10175 | else |
98b528ac L |
10176 | { |
10177 | if (sizeflag & DFLAG) | |
10178 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10179 | else | |
10180 | *obufp++ = 'w'; | |
10181 | } | |
10182 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 10183 | } |
98b528ac L |
10184 | } |
10185 | else | |
10186 | { | |
10187 | if (l != 1 || len != 2 || last[0] != 'L') | |
10188 | { | |
10189 | SAVE_LAST (*p); | |
10190 | break; | |
10191 | } | |
10192 | if (intel_syntax | |
10193 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
10194 | break; | |
10195 | if ((rex & REX_W)) | |
10196 | { | |
10197 | USED_REX (REX_W); | |
10198 | *obufp++ = 'q'; | |
10199 | } | |
10200 | else | |
10201 | *obufp++ = 'l'; | |
252b5132 RH |
10202 | } |
10203 | break; | |
10204 | case 'R': | |
161a04f6 L |
10205 | USED_REX (REX_W); |
10206 | if (rex & REX_W) | |
a35ca55a JB |
10207 | *obufp++ = 'q'; |
10208 | else if (sizeflag & DFLAG) | |
c608c12e | 10209 | { |
a35ca55a | 10210 | if (intel_syntax) |
c608c12e | 10211 | *obufp++ = 'd'; |
c608c12e | 10212 | else |
a35ca55a | 10213 | *obufp++ = 'l'; |
c608c12e | 10214 | } |
252b5132 | 10215 | else |
a35ca55a JB |
10216 | *obufp++ = 'w'; |
10217 | if (intel_syntax && !p[1] | |
161a04f6 | 10218 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 10219 | *obufp++ = 'e'; |
161a04f6 | 10220 | if (!(rex & REX_W)) |
52b15da3 | 10221 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 10222 | break; |
1a114b12 JB |
10223 | case 'V': |
10224 | if (intel_syntax) | |
10225 | break; | |
cb712a9e | 10226 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
1a114b12 JB |
10227 | { |
10228 | if (sizeflag & SUFFIX_ALWAYS) | |
10229 | *obufp++ = 'q'; | |
10230 | break; | |
10231 | } | |
10232 | /* Fall through. */ | |
252b5132 | 10233 | case 'S': |
db6eb5be AM |
10234 | if (intel_syntax) |
10235 | break; | |
252b5132 RH |
10236 | if (sizeflag & SUFFIX_ALWAYS) |
10237 | { | |
161a04f6 | 10238 | if (rex & REX_W) |
52b15da3 | 10239 | *obufp++ = 'q'; |
252b5132 | 10240 | else |
52b15da3 JH |
10241 | { |
10242 | if (sizeflag & DFLAG) | |
10243 | *obufp++ = 'l'; | |
10244 | else | |
10245 | *obufp++ = 'w'; | |
10246 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10247 | } | |
252b5132 | 10248 | } |
252b5132 | 10249 | break; |
041bd2e0 | 10250 | case 'X': |
c0f3af97 L |
10251 | if (l != 0 || len != 1) |
10252 | { | |
10253 | SAVE_LAST (*p); | |
10254 | break; | |
10255 | } | |
10256 | if (need_vex && vex.prefix) | |
10257 | { | |
10258 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
10259 | *obufp++ = 'd'; | |
10260 | else | |
10261 | *obufp++ = 's'; | |
10262 | } | |
10263 | else if (prefixes & PREFIX_DATA) | |
041bd2e0 JH |
10264 | *obufp++ = 'd'; |
10265 | else | |
10266 | *obufp++ = 's'; | |
db6eb5be | 10267 | used_prefixes |= (prefixes & PREFIX_DATA); |
041bd2e0 | 10268 | break; |
76f227a5 | 10269 | case 'Y': |
c0f3af97 | 10270 | if (l == 0 && len == 1) |
76f227a5 | 10271 | { |
c0f3af97 L |
10272 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
10273 | break; | |
10274 | if (rex & REX_W) | |
10275 | { | |
10276 | USED_REX (REX_W); | |
10277 | *obufp++ = 'q'; | |
10278 | } | |
10279 | break; | |
10280 | } | |
10281 | else | |
10282 | { | |
10283 | if (l != 1 || len != 2 || last[0] != 'X') | |
10284 | { | |
10285 | SAVE_LAST (*p); | |
10286 | break; | |
10287 | } | |
10288 | if (!need_vex) | |
10289 | abort (); | |
10290 | if (intel_syntax | |
10291 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
10292 | break; | |
10293 | switch (vex.length) | |
10294 | { | |
10295 | case 128: | |
10296 | *obufp++ = 'x'; | |
10297 | break; | |
10298 | case 256: | |
10299 | *obufp++ = 'y'; | |
10300 | break; | |
10301 | default: | |
10302 | abort (); | |
10303 | } | |
76f227a5 JH |
10304 | } |
10305 | break; | |
252b5132 | 10306 | case 'W': |
0bfee649 | 10307 | if (l == 0 && len == 1) |
a35ca55a | 10308 | { |
0bfee649 L |
10309 | /* operand size flag for cwtl, cbtw */ |
10310 | USED_REX (REX_W); | |
10311 | if (rex & REX_W) | |
10312 | { | |
10313 | if (intel_syntax) | |
10314 | *obufp++ = 'd'; | |
10315 | else | |
10316 | *obufp++ = 'l'; | |
10317 | } | |
10318 | else if (sizeflag & DFLAG) | |
10319 | *obufp++ = 'w'; | |
a35ca55a | 10320 | else |
0bfee649 L |
10321 | *obufp++ = 'b'; |
10322 | if (!(rex & REX_W)) | |
10323 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 10324 | } |
252b5132 | 10325 | else |
0bfee649 L |
10326 | { |
10327 | if (l != 1 || len != 2 || last[0] != 'X') | |
10328 | { | |
10329 | SAVE_LAST (*p); | |
10330 | break; | |
10331 | } | |
10332 | if (!need_vex) | |
10333 | abort (); | |
10334 | *obufp++ = vex.w ? 'd': 's'; | |
10335 | } | |
252b5132 RH |
10336 | break; |
10337 | } | |
9306ca4a | 10338 | alt = 0; |
252b5132 RH |
10339 | } |
10340 | *obufp = 0; | |
ea397f5b | 10341 | mnemonicendp = obufp; |
6439fc28 | 10342 | return 0; |
252b5132 RH |
10343 | } |
10344 | ||
10345 | static void | |
26ca5450 | 10346 | oappend (const char *s) |
252b5132 | 10347 | { |
ea397f5b | 10348 | obufp = stpcpy (obufp, s); |
252b5132 RH |
10349 | } |
10350 | ||
10351 | static void | |
26ca5450 | 10352 | append_seg (void) |
252b5132 RH |
10353 | { |
10354 | if (prefixes & PREFIX_CS) | |
7d421014 | 10355 | { |
7d421014 | 10356 | used_prefixes |= PREFIX_CS; |
d708bcba | 10357 | oappend ("%cs:" + intel_syntax); |
7d421014 | 10358 | } |
252b5132 | 10359 | if (prefixes & PREFIX_DS) |
7d421014 | 10360 | { |
7d421014 | 10361 | used_prefixes |= PREFIX_DS; |
d708bcba | 10362 | oappend ("%ds:" + intel_syntax); |
7d421014 | 10363 | } |
252b5132 | 10364 | if (prefixes & PREFIX_SS) |
7d421014 | 10365 | { |
7d421014 | 10366 | used_prefixes |= PREFIX_SS; |
d708bcba | 10367 | oappend ("%ss:" + intel_syntax); |
7d421014 | 10368 | } |
252b5132 | 10369 | if (prefixes & PREFIX_ES) |
7d421014 | 10370 | { |
7d421014 | 10371 | used_prefixes |= PREFIX_ES; |
d708bcba | 10372 | oappend ("%es:" + intel_syntax); |
7d421014 | 10373 | } |
252b5132 | 10374 | if (prefixes & PREFIX_FS) |
7d421014 | 10375 | { |
7d421014 | 10376 | used_prefixes |= PREFIX_FS; |
d708bcba | 10377 | oappend ("%fs:" + intel_syntax); |
7d421014 | 10378 | } |
252b5132 | 10379 | if (prefixes & PREFIX_GS) |
7d421014 | 10380 | { |
7d421014 | 10381 | used_prefixes |= PREFIX_GS; |
d708bcba | 10382 | oappend ("%gs:" + intel_syntax); |
7d421014 | 10383 | } |
252b5132 RH |
10384 | } |
10385 | ||
10386 | static void | |
26ca5450 | 10387 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
10388 | { |
10389 | if (!intel_syntax) | |
10390 | oappend ("*"); | |
10391 | OP_E (bytemode, sizeflag); | |
10392 | } | |
10393 | ||
52b15da3 | 10394 | static void |
26ca5450 | 10395 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 10396 | { |
cb712a9e | 10397 | if (address_mode == mode_64bit) |
52b15da3 JH |
10398 | { |
10399 | if (hex) | |
10400 | { | |
10401 | char tmp[30]; | |
10402 | int i; | |
10403 | buf[0] = '0'; | |
10404 | buf[1] = 'x'; | |
10405 | sprintf_vma (tmp, disp); | |
6608db57 | 10406 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
10407 | strcpy (buf + 2, tmp + i); |
10408 | } | |
10409 | else | |
10410 | { | |
10411 | bfd_signed_vma v = disp; | |
10412 | char tmp[30]; | |
10413 | int i; | |
10414 | if (v < 0) | |
10415 | { | |
10416 | *(buf++) = '-'; | |
10417 | v = -disp; | |
6608db57 | 10418 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
10419 | if (v < 0) |
10420 | { | |
10421 | strcpy (buf, "9223372036854775808"); | |
10422 | return; | |
10423 | } | |
10424 | } | |
10425 | if (!v) | |
10426 | { | |
10427 | strcpy (buf, "0"); | |
10428 | return; | |
10429 | } | |
10430 | ||
10431 | i = 0; | |
10432 | tmp[29] = 0; | |
10433 | while (v) | |
10434 | { | |
6608db57 | 10435 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
10436 | v /= 10; |
10437 | i++; | |
10438 | } | |
10439 | strcpy (buf, tmp + 29 - i); | |
10440 | } | |
10441 | } | |
10442 | else | |
10443 | { | |
10444 | if (hex) | |
10445 | sprintf (buf, "0x%x", (unsigned int) disp); | |
10446 | else | |
10447 | sprintf (buf, "%d", (int) disp); | |
10448 | } | |
10449 | } | |
10450 | ||
5d669648 L |
10451 | /* Put DISP in BUF as signed hex number. */ |
10452 | ||
10453 | static void | |
10454 | print_displacement (char *buf, bfd_vma disp) | |
10455 | { | |
10456 | bfd_signed_vma val = disp; | |
10457 | char tmp[30]; | |
10458 | int i, j = 0; | |
10459 | ||
10460 | if (val < 0) | |
10461 | { | |
10462 | buf[j++] = '-'; | |
10463 | val = -disp; | |
10464 | ||
10465 | /* Check for possible overflow. */ | |
10466 | if (val < 0) | |
10467 | { | |
10468 | switch (address_mode) | |
10469 | { | |
10470 | case mode_64bit: | |
10471 | strcpy (buf + j, "0x8000000000000000"); | |
10472 | break; | |
10473 | case mode_32bit: | |
10474 | strcpy (buf + j, "0x80000000"); | |
10475 | break; | |
10476 | case mode_16bit: | |
10477 | strcpy (buf + j, "0x8000"); | |
10478 | break; | |
10479 | } | |
10480 | return; | |
10481 | } | |
10482 | } | |
10483 | ||
10484 | buf[j++] = '0'; | |
10485 | buf[j++] = 'x'; | |
10486 | ||
0af1713e | 10487 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
10488 | for (i = 0; tmp[i] == '0'; i++) |
10489 | continue; | |
10490 | if (tmp[i] == '\0') | |
10491 | i--; | |
10492 | strcpy (buf + j, tmp + i); | |
10493 | } | |
10494 | ||
3f31e633 JB |
10495 | static void |
10496 | intel_operand_size (int bytemode, int sizeflag) | |
10497 | { | |
10498 | switch (bytemode) | |
10499 | { | |
10500 | case b_mode: | |
b6169b20 | 10501 | case b_swap_mode: |
42903f7f | 10502 | case dqb_mode: |
3f31e633 JB |
10503 | oappend ("BYTE PTR "); |
10504 | break; | |
10505 | case w_mode: | |
10506 | case dqw_mode: | |
10507 | oappend ("WORD PTR "); | |
10508 | break; | |
1a114b12 | 10509 | case stack_v_mode: |
cb712a9e | 10510 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
3f31e633 JB |
10511 | { |
10512 | oappend ("QWORD PTR "); | |
10513 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10514 | break; | |
10515 | } | |
10516 | /* FALLTHRU */ | |
10517 | case v_mode: | |
b6169b20 | 10518 | case v_swap_mode: |
3f31e633 | 10519 | case dq_mode: |
161a04f6 L |
10520 | USED_REX (REX_W); |
10521 | if (rex & REX_W) | |
3f31e633 JB |
10522 | oappend ("QWORD PTR "); |
10523 | else if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
10524 | oappend ("DWORD PTR "); | |
10525 | else | |
10526 | oappend ("WORD PTR "); | |
10527 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10528 | break; | |
52fd6d94 | 10529 | case z_mode: |
161a04f6 | 10530 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10531 | *obufp++ = 'D'; |
10532 | oappend ("WORD PTR "); | |
161a04f6 | 10533 | if (!(rex & REX_W)) |
52fd6d94 JB |
10534 | used_prefixes |= (prefixes & PREFIX_DATA); |
10535 | break; | |
34b772a6 JB |
10536 | case a_mode: |
10537 | if (sizeflag & DFLAG) | |
10538 | oappend ("QWORD PTR "); | |
10539 | else | |
10540 | oappend ("DWORD PTR "); | |
10541 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10542 | break; | |
3f31e633 | 10543 | case d_mode: |
fa99fab2 | 10544 | case d_swap_mode: |
42903f7f | 10545 | case dqd_mode: |
3f31e633 JB |
10546 | oappend ("DWORD PTR "); |
10547 | break; | |
10548 | case q_mode: | |
b6169b20 | 10549 | case q_swap_mode: |
3f31e633 JB |
10550 | oappend ("QWORD PTR "); |
10551 | break; | |
10552 | case m_mode: | |
cb712a9e | 10553 | if (address_mode == mode_64bit) |
3f31e633 JB |
10554 | oappend ("QWORD PTR "); |
10555 | else | |
10556 | oappend ("DWORD PTR "); | |
10557 | break; | |
10558 | case f_mode: | |
10559 | if (sizeflag & DFLAG) | |
10560 | oappend ("FWORD PTR "); | |
10561 | else | |
10562 | oappend ("DWORD PTR "); | |
10563 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10564 | break; | |
10565 | case t_mode: | |
10566 | oappend ("TBYTE PTR "); | |
10567 | break; | |
10568 | case x_mode: | |
b6169b20 | 10569 | case x_swap_mode: |
c0f3af97 L |
10570 | if (need_vex) |
10571 | { | |
10572 | switch (vex.length) | |
10573 | { | |
10574 | case 128: | |
10575 | oappend ("XMMWORD PTR "); | |
10576 | break; | |
10577 | case 256: | |
10578 | oappend ("YMMWORD PTR "); | |
10579 | break; | |
10580 | default: | |
10581 | abort (); | |
10582 | } | |
10583 | } | |
10584 | else | |
10585 | oappend ("XMMWORD PTR "); | |
10586 | break; | |
10587 | case xmm_mode: | |
3f31e633 JB |
10588 | oappend ("XMMWORD PTR "); |
10589 | break; | |
c0f3af97 L |
10590 | case xmmq_mode: |
10591 | if (!need_vex) | |
10592 | abort (); | |
10593 | ||
10594 | switch (vex.length) | |
10595 | { | |
10596 | case 128: | |
10597 | oappend ("QWORD PTR "); | |
10598 | break; | |
10599 | case 256: | |
10600 | oappend ("XMMWORD PTR "); | |
10601 | break; | |
10602 | default: | |
10603 | abort (); | |
10604 | } | |
10605 | break; | |
10606 | case ymmq_mode: | |
10607 | if (!need_vex) | |
10608 | abort (); | |
10609 | ||
10610 | switch (vex.length) | |
10611 | { | |
10612 | case 128: | |
10613 | oappend ("QWORD PTR "); | |
10614 | break; | |
10615 | case 256: | |
10616 | oappend ("YMMWORD PTR "); | |
10617 | break; | |
10618 | default: | |
10619 | abort (); | |
10620 | } | |
10621 | break; | |
fb9c77c7 L |
10622 | case o_mode: |
10623 | oappend ("OWORD PTR "); | |
10624 | break; | |
0bfee649 L |
10625 | case vex_w_dq_mode: |
10626 | if (!need_vex) | |
10627 | abort (); | |
10628 | ||
10629 | if (vex.w) | |
10630 | oappend ("QWORD PTR "); | |
10631 | else | |
10632 | oappend ("DWORD PTR "); | |
10633 | break; | |
3f31e633 JB |
10634 | default: |
10635 | break; | |
10636 | } | |
10637 | } | |
10638 | ||
252b5132 | 10639 | static void |
c0f3af97 | 10640 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 10641 | { |
c0f3af97 L |
10642 | int reg = modrm.rm; |
10643 | const char **names; | |
252b5132 | 10644 | |
c0f3af97 L |
10645 | USED_REX (REX_B); |
10646 | if ((rex & REX_B)) | |
10647 | reg += 8; | |
252b5132 | 10648 | |
b6169b20 L |
10649 | if ((sizeflag & SUFFIX_ALWAYS) |
10650 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
10651 | swap_operand (); | |
10652 | ||
c0f3af97 | 10653 | switch (bytemode) |
252b5132 | 10654 | { |
c0f3af97 | 10655 | case b_mode: |
b6169b20 | 10656 | case b_swap_mode: |
c0f3af97 L |
10657 | USED_REX (0); |
10658 | if (rex) | |
10659 | names = names8rex; | |
10660 | else | |
10661 | names = names8; | |
10662 | break; | |
10663 | case w_mode: | |
10664 | names = names16; | |
10665 | break; | |
10666 | case d_mode: | |
10667 | names = names32; | |
10668 | break; | |
10669 | case q_mode: | |
10670 | names = names64; | |
10671 | break; | |
10672 | case m_mode: | |
10673 | names = address_mode == mode_64bit ? names64 : names32; | |
10674 | break; | |
10675 | case stack_v_mode: | |
10676 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) | |
252b5132 | 10677 | { |
c0f3af97 | 10678 | names = names64; |
7d421014 | 10679 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 10680 | break; |
252b5132 | 10681 | } |
c0f3af97 L |
10682 | bytemode = v_mode; |
10683 | /* FALLTHRU */ | |
10684 | case v_mode: | |
b6169b20 | 10685 | case v_swap_mode: |
c0f3af97 L |
10686 | case dq_mode: |
10687 | case dqb_mode: | |
10688 | case dqd_mode: | |
10689 | case dqw_mode: | |
10690 | USED_REX (REX_W); | |
10691 | if (rex & REX_W) | |
10692 | names = names64; | |
b6169b20 L |
10693 | else if ((sizeflag & DFLAG) |
10694 | || (bytemode != v_mode | |
10695 | && bytemode != v_swap_mode)) | |
c0f3af97 L |
10696 | names = names32; |
10697 | else | |
10698 | names = names16; | |
10699 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10700 | break; | |
10701 | case 0: | |
10702 | return; | |
10703 | default: | |
10704 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
10705 | return; |
10706 | } | |
c0f3af97 L |
10707 | oappend (names[reg]); |
10708 | } | |
10709 | ||
10710 | static void | |
c1e679ec | 10711 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
10712 | { |
10713 | bfd_vma disp = 0; | |
10714 | int add = (rex & REX_B) ? 8 : 0; | |
10715 | int riprel = 0; | |
252b5132 | 10716 | |
c0f3af97 | 10717 | USED_REX (REX_B); |
3f31e633 JB |
10718 | if (intel_syntax) |
10719 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
10720 | append_seg (); |
10721 | ||
5d669648 | 10722 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 10723 | { |
5d669648 L |
10724 | /* 32/64 bit address mode */ |
10725 | int havedisp; | |
252b5132 RH |
10726 | int havesib; |
10727 | int havebase; | |
0f7da397 | 10728 | int haveindex; |
20afcfb7 | 10729 | int needindex; |
82c18208 | 10730 | int base, rbase; |
252b5132 RH |
10731 | int index = 0; |
10732 | int scale = 0; | |
10733 | ||
10734 | havesib = 0; | |
10735 | havebase = 1; | |
0f7da397 | 10736 | haveindex = 0; |
7967e09e | 10737 | base = modrm.rm; |
252b5132 RH |
10738 | |
10739 | if (base == 4) | |
10740 | { | |
10741 | havesib = 1; | |
10742 | FETCH_DATA (the_info, codep + 1); | |
252b5132 | 10743 | index = (*codep >> 3) & 7; |
db51cc60 | 10744 | scale = (*codep >> 6) & 3; |
252b5132 | 10745 | base = *codep & 7; |
161a04f6 L |
10746 | USED_REX (REX_X); |
10747 | if (rex & REX_X) | |
52b15da3 | 10748 | index += 8; |
0f7da397 | 10749 | haveindex = index != 4; |
252b5132 RH |
10750 | codep++; |
10751 | } | |
82c18208 | 10752 | rbase = base + add; |
252b5132 | 10753 | |
7967e09e | 10754 | switch (modrm.mod) |
252b5132 RH |
10755 | { |
10756 | case 0: | |
82c18208 | 10757 | if (base == 5) |
252b5132 RH |
10758 | { |
10759 | havebase = 0; | |
cb712a9e | 10760 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
10761 | riprel = 1; |
10762 | disp = get32s (); | |
252b5132 RH |
10763 | } |
10764 | break; | |
10765 | case 1: | |
10766 | FETCH_DATA (the_info, codep + 1); | |
10767 | disp = *codep++; | |
10768 | if ((disp & 0x80) != 0) | |
10769 | disp -= 0x100; | |
10770 | break; | |
10771 | case 2: | |
52b15da3 | 10772 | disp = get32s (); |
252b5132 RH |
10773 | break; |
10774 | } | |
10775 | ||
20afcfb7 L |
10776 | /* In 32bit mode, we need index register to tell [offset] from |
10777 | [eiz*1 + offset]. */ | |
10778 | needindex = (havesib | |
10779 | && !havebase | |
10780 | && !haveindex | |
10781 | && address_mode == mode_32bit); | |
10782 | havedisp = (havebase | |
10783 | || needindex | |
10784 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 10785 | |
252b5132 | 10786 | if (!intel_syntax) |
82c18208 | 10787 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 10788 | { |
5d669648 L |
10789 | if (havedisp || riprel) |
10790 | print_displacement (scratchbuf, disp); | |
10791 | else | |
10792 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 10793 | oappend (scratchbuf); |
52b15da3 JH |
10794 | if (riprel) |
10795 | { | |
10796 | set_op (disp, 1); | |
87767711 | 10797 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 10798 | } |
db6eb5be | 10799 | } |
2da11e11 | 10800 | |
87767711 JB |
10801 | if (havebase || haveindex || riprel) |
10802 | used_prefixes |= PREFIX_ADDR; | |
10803 | ||
5d669648 | 10804 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 10805 | { |
252b5132 | 10806 | *obufp++ = open_char; |
52b15da3 | 10807 | if (intel_syntax && riprel) |
185b1163 L |
10808 | { |
10809 | set_op (disp, 1); | |
87767711 | 10810 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 10811 | } |
db6eb5be | 10812 | *obufp = '\0'; |
252b5132 | 10813 | if (havebase) |
cb712a9e | 10814 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
82c18208 | 10815 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
10816 | if (havesib) |
10817 | { | |
db51cc60 L |
10818 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
10819 | print index to tell base + index from base. */ | |
10820 | if (scale != 0 | |
20afcfb7 | 10821 | || needindex |
db51cc60 L |
10822 | || haveindex |
10823 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 10824 | { |
9306ca4a | 10825 | if (!intel_syntax || havebase) |
db6eb5be | 10826 | { |
9306ca4a JB |
10827 | *obufp++ = separator_char; |
10828 | *obufp = '\0'; | |
db6eb5be | 10829 | } |
db51cc60 L |
10830 | if (haveindex) |
10831 | oappend (address_mode == mode_64bit | |
10832 | && (sizeflag & AFLAG) | |
10833 | ? names64[index] : names32[index]); | |
10834 | else | |
10835 | oappend (address_mode == mode_64bit | |
10836 | && (sizeflag & AFLAG) | |
10837 | ? index64 : index32); | |
10838 | ||
db6eb5be AM |
10839 | *obufp++ = scale_char; |
10840 | *obufp = '\0'; | |
10841 | sprintf (scratchbuf, "%d", 1 << scale); | |
10842 | oappend (scratchbuf); | |
10843 | } | |
252b5132 | 10844 | } |
185b1163 | 10845 | if (intel_syntax |
82c18208 | 10846 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 10847 | { |
db51cc60 | 10848 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
10849 | { |
10850 | *obufp++ = '+'; | |
10851 | *obufp = '\0'; | |
10852 | } | |
7967e09e | 10853 | else if (modrm.mod != 1) |
3d456fa1 JB |
10854 | { |
10855 | *obufp++ = '-'; | |
10856 | *obufp = '\0'; | |
10857 | disp = - (bfd_signed_vma) disp; | |
10858 | } | |
10859 | ||
db51cc60 L |
10860 | if (havedisp) |
10861 | print_displacement (scratchbuf, disp); | |
10862 | else | |
10863 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
10864 | oappend (scratchbuf); |
10865 | } | |
252b5132 RH |
10866 | |
10867 | *obufp++ = close_char; | |
db6eb5be | 10868 | *obufp = '\0'; |
252b5132 RH |
10869 | } |
10870 | else if (intel_syntax) | |
db6eb5be | 10871 | { |
82c18208 | 10872 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 10873 | { |
252b5132 RH |
10874 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
10875 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
10876 | ; | |
10877 | else | |
10878 | { | |
d708bcba | 10879 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
10880 | oappend (":"); |
10881 | } | |
52b15da3 | 10882 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
10883 | oappend (scratchbuf); |
10884 | } | |
10885 | } | |
252b5132 RH |
10886 | } |
10887 | else | |
10888 | { /* 16 bit address mode */ | |
7967e09e | 10889 | switch (modrm.mod) |
252b5132 RH |
10890 | { |
10891 | case 0: | |
7967e09e | 10892 | if (modrm.rm == 6) |
252b5132 RH |
10893 | { |
10894 | disp = get16 (); | |
10895 | if ((disp & 0x8000) != 0) | |
10896 | disp -= 0x10000; | |
10897 | } | |
10898 | break; | |
10899 | case 1: | |
10900 | FETCH_DATA (the_info, codep + 1); | |
10901 | disp = *codep++; | |
10902 | if ((disp & 0x80) != 0) | |
10903 | disp -= 0x100; | |
10904 | break; | |
10905 | case 2: | |
10906 | disp = get16 (); | |
10907 | if ((disp & 0x8000) != 0) | |
10908 | disp -= 0x10000; | |
10909 | break; | |
10910 | } | |
10911 | ||
10912 | if (!intel_syntax) | |
7967e09e | 10913 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 10914 | { |
5d669648 | 10915 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
10916 | oappend (scratchbuf); |
10917 | } | |
252b5132 | 10918 | |
7967e09e | 10919 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
10920 | { |
10921 | *obufp++ = open_char; | |
db6eb5be | 10922 | *obufp = '\0'; |
7967e09e | 10923 | oappend (index16[modrm.rm]); |
5d669648 L |
10924 | if (intel_syntax |
10925 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 10926 | { |
5d669648 | 10927 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
10928 | { |
10929 | *obufp++ = '+'; | |
10930 | *obufp = '\0'; | |
10931 | } | |
7967e09e | 10932 | else if (modrm.mod != 1) |
3d456fa1 JB |
10933 | { |
10934 | *obufp++ = '-'; | |
10935 | *obufp = '\0'; | |
10936 | disp = - (bfd_signed_vma) disp; | |
10937 | } | |
10938 | ||
5d669648 | 10939 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
10940 | oappend (scratchbuf); |
10941 | } | |
10942 | ||
db6eb5be AM |
10943 | *obufp++ = close_char; |
10944 | *obufp = '\0'; | |
252b5132 | 10945 | } |
3d456fa1 JB |
10946 | else if (intel_syntax) |
10947 | { | |
10948 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
10949 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
10950 | ; | |
10951 | else | |
10952 | { | |
10953 | oappend (names_seg[ds_reg - es_reg]); | |
10954 | oappend (":"); | |
10955 | } | |
10956 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
10957 | oappend (scratchbuf); | |
10958 | } | |
252b5132 RH |
10959 | } |
10960 | } | |
10961 | ||
c0f3af97 | 10962 | static void |
c1e679ec | 10963 | OP_E_extended (int bytemode, int sizeflag) |
c0f3af97 L |
10964 | { |
10965 | /* Skip mod/rm byte. */ | |
10966 | MODRM_CHECK; | |
10967 | codep++; | |
10968 | ||
10969 | if (modrm.mod == 3) | |
10970 | OP_E_register (bytemode, sizeflag); | |
10971 | else | |
c1e679ec | 10972 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
10973 | } |
10974 | ||
85f10a01 MM |
10975 | static void |
10976 | OP_E (int bytemode, int sizeflag) | |
10977 | { | |
c1e679ec | 10978 | OP_E_extended (bytemode, sizeflag); |
85f10a01 MM |
10979 | } |
10980 | ||
10981 | ||
252b5132 | 10982 | static void |
26ca5450 | 10983 | OP_G (int bytemode, int sizeflag) |
252b5132 | 10984 | { |
52b15da3 | 10985 | int add = 0; |
161a04f6 L |
10986 | USED_REX (REX_R); |
10987 | if (rex & REX_R) | |
52b15da3 | 10988 | add += 8; |
252b5132 RH |
10989 | switch (bytemode) |
10990 | { | |
10991 | case b_mode: | |
52b15da3 JH |
10992 | USED_REX (0); |
10993 | if (rex) | |
7967e09e | 10994 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 10995 | else |
7967e09e | 10996 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
10997 | break; |
10998 | case w_mode: | |
7967e09e | 10999 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
11000 | break; |
11001 | case d_mode: | |
7967e09e | 11002 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
11003 | break; |
11004 | case q_mode: | |
7967e09e | 11005 | oappend (names64[modrm.reg + add]); |
252b5132 RH |
11006 | break; |
11007 | case v_mode: | |
9306ca4a | 11008 | case dq_mode: |
42903f7f L |
11009 | case dqb_mode: |
11010 | case dqd_mode: | |
9306ca4a | 11011 | case dqw_mode: |
161a04f6 L |
11012 | USED_REX (REX_W); |
11013 | if (rex & REX_W) | |
7967e09e | 11014 | oappend (names64[modrm.reg + add]); |
9306ca4a | 11015 | else if ((sizeflag & DFLAG) || bytemode != v_mode) |
7967e09e | 11016 | oappend (names32[modrm.reg + add]); |
252b5132 | 11017 | else |
7967e09e | 11018 | oappend (names16[modrm.reg + add]); |
7d421014 | 11019 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 11020 | break; |
90700ea2 | 11021 | case m_mode: |
cb712a9e | 11022 | if (address_mode == mode_64bit) |
7967e09e | 11023 | oappend (names64[modrm.reg + add]); |
90700ea2 | 11024 | else |
7967e09e | 11025 | oappend (names32[modrm.reg + add]); |
90700ea2 | 11026 | break; |
252b5132 RH |
11027 | default: |
11028 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11029 | break; | |
11030 | } | |
11031 | } | |
11032 | ||
52b15da3 | 11033 | static bfd_vma |
26ca5450 | 11034 | get64 (void) |
52b15da3 | 11035 | { |
5dd0794d | 11036 | bfd_vma x; |
52b15da3 | 11037 | #ifdef BFD64 |
5dd0794d AM |
11038 | unsigned int a; |
11039 | unsigned int b; | |
11040 | ||
52b15da3 JH |
11041 | FETCH_DATA (the_info, codep + 8); |
11042 | a = *codep++ & 0xff; | |
11043 | a |= (*codep++ & 0xff) << 8; | |
11044 | a |= (*codep++ & 0xff) << 16; | |
11045 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 11046 | b = *codep++ & 0xff; |
52b15da3 JH |
11047 | b |= (*codep++ & 0xff) << 8; |
11048 | b |= (*codep++ & 0xff) << 16; | |
11049 | b |= (*codep++ & 0xff) << 24; | |
11050 | x = a + ((bfd_vma) b << 32); | |
11051 | #else | |
6608db57 | 11052 | abort (); |
5dd0794d | 11053 | x = 0; |
52b15da3 JH |
11054 | #endif |
11055 | return x; | |
11056 | } | |
11057 | ||
11058 | static bfd_signed_vma | |
26ca5450 | 11059 | get32 (void) |
252b5132 | 11060 | { |
52b15da3 | 11061 | bfd_signed_vma x = 0; |
252b5132 RH |
11062 | |
11063 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
11064 | x = *codep++ & (bfd_signed_vma) 0xff; |
11065 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
11066 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
11067 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
11068 | return x; | |
11069 | } | |
11070 | ||
11071 | static bfd_signed_vma | |
26ca5450 | 11072 | get32s (void) |
52b15da3 JH |
11073 | { |
11074 | bfd_signed_vma x = 0; | |
11075 | ||
11076 | FETCH_DATA (the_info, codep + 4); | |
11077 | x = *codep++ & (bfd_signed_vma) 0xff; | |
11078 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
11079 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
11080 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
11081 | ||
11082 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
11083 | ||
252b5132 RH |
11084 | return x; |
11085 | } | |
11086 | ||
11087 | static int | |
26ca5450 | 11088 | get16 (void) |
252b5132 RH |
11089 | { |
11090 | int x = 0; | |
11091 | ||
11092 | FETCH_DATA (the_info, codep + 2); | |
11093 | x = *codep++ & 0xff; | |
11094 | x |= (*codep++ & 0xff) << 8; | |
11095 | return x; | |
11096 | } | |
11097 | ||
11098 | static void | |
26ca5450 | 11099 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
11100 | { |
11101 | op_index[op_ad] = op_ad; | |
cb712a9e | 11102 | if (address_mode == mode_64bit) |
7081ff04 AJ |
11103 | { |
11104 | op_address[op_ad] = op; | |
11105 | op_riprel[op_ad] = riprel; | |
11106 | } | |
11107 | else | |
11108 | { | |
11109 | /* Mask to get a 32-bit address. */ | |
11110 | op_address[op_ad] = op & 0xffffffff; | |
11111 | op_riprel[op_ad] = riprel & 0xffffffff; | |
11112 | } | |
252b5132 RH |
11113 | } |
11114 | ||
11115 | static void | |
26ca5450 | 11116 | OP_REG (int code, int sizeflag) |
252b5132 | 11117 | { |
2da11e11 | 11118 | const char *s; |
9b60702d | 11119 | int add; |
161a04f6 L |
11120 | USED_REX (REX_B); |
11121 | if (rex & REX_B) | |
52b15da3 | 11122 | add = 8; |
9b60702d L |
11123 | else |
11124 | add = 0; | |
52b15da3 JH |
11125 | |
11126 | switch (code) | |
11127 | { | |
52b15da3 JH |
11128 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
11129 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
11130 | s = names16[code - ax_reg + add]; | |
11131 | break; | |
11132 | case es_reg: case ss_reg: case cs_reg: | |
11133 | case ds_reg: case fs_reg: case gs_reg: | |
11134 | s = names_seg[code - es_reg + add]; | |
11135 | break; | |
11136 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
11137 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
11138 | USED_REX (0); | |
11139 | if (rex) | |
11140 | s = names8rex[code - al_reg + add]; | |
11141 | else | |
11142 | s = names8[code - al_reg]; | |
11143 | break; | |
6439fc28 AM |
11144 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
11145 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
cb712a9e | 11146 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
11147 | { |
11148 | s = names64[code - rAX_reg + add]; | |
11149 | break; | |
11150 | } | |
11151 | code += eAX_reg - rAX_reg; | |
6608db57 | 11152 | /* Fall through. */ |
52b15da3 JH |
11153 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
11154 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
11155 | USED_REX (REX_W); |
11156 | if (rex & REX_W) | |
52b15da3 JH |
11157 | s = names64[code - eAX_reg + add]; |
11158 | else if (sizeflag & DFLAG) | |
11159 | s = names32[code - eAX_reg + add]; | |
11160 | else | |
11161 | s = names16[code - eAX_reg + add]; | |
11162 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11163 | break; | |
52b15da3 JH |
11164 | default: |
11165 | s = INTERNAL_DISASSEMBLER_ERROR; | |
11166 | break; | |
11167 | } | |
11168 | oappend (s); | |
11169 | } | |
11170 | ||
11171 | static void | |
26ca5450 | 11172 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
11173 | { |
11174 | const char *s; | |
252b5132 RH |
11175 | |
11176 | switch (code) | |
11177 | { | |
11178 | case indir_dx_reg: | |
d708bcba | 11179 | if (intel_syntax) |
52fd6d94 | 11180 | s = "dx"; |
d708bcba | 11181 | else |
db6eb5be | 11182 | s = "(%dx)"; |
252b5132 RH |
11183 | break; |
11184 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
11185 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
11186 | s = names16[code - ax_reg]; | |
11187 | break; | |
11188 | case es_reg: case ss_reg: case cs_reg: | |
11189 | case ds_reg: case fs_reg: case gs_reg: | |
11190 | s = names_seg[code - es_reg]; | |
11191 | break; | |
11192 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
11193 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
11194 | USED_REX (0); |
11195 | if (rex) | |
11196 | s = names8rex[code - al_reg]; | |
11197 | else | |
11198 | s = names8[code - al_reg]; | |
252b5132 RH |
11199 | break; |
11200 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
11201 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
11202 | USED_REX (REX_W); |
11203 | if (rex & REX_W) | |
52b15da3 JH |
11204 | s = names64[code - eAX_reg]; |
11205 | else if (sizeflag & DFLAG) | |
252b5132 RH |
11206 | s = names32[code - eAX_reg]; |
11207 | else | |
11208 | s = names16[code - eAX_reg]; | |
7d421014 | 11209 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 11210 | break; |
52fd6d94 | 11211 | case z_mode_ax_reg: |
161a04f6 | 11212 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
11213 | s = *names32; |
11214 | else | |
11215 | s = *names16; | |
161a04f6 | 11216 | if (!(rex & REX_W)) |
52fd6d94 JB |
11217 | used_prefixes |= (prefixes & PREFIX_DATA); |
11218 | break; | |
252b5132 RH |
11219 | default: |
11220 | s = INTERNAL_DISASSEMBLER_ERROR; | |
11221 | break; | |
11222 | } | |
11223 | oappend (s); | |
11224 | } | |
11225 | ||
11226 | static void | |
26ca5450 | 11227 | OP_I (int bytemode, int sizeflag) |
252b5132 | 11228 | { |
52b15da3 JH |
11229 | bfd_signed_vma op; |
11230 | bfd_signed_vma mask = -1; | |
252b5132 RH |
11231 | |
11232 | switch (bytemode) | |
11233 | { | |
11234 | case b_mode: | |
11235 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
11236 | op = *codep++; |
11237 | mask = 0xff; | |
11238 | break; | |
11239 | case q_mode: | |
cb712a9e | 11240 | if (address_mode == mode_64bit) |
6439fc28 AM |
11241 | { |
11242 | op = get32s (); | |
11243 | break; | |
11244 | } | |
6608db57 | 11245 | /* Fall through. */ |
252b5132 | 11246 | case v_mode: |
161a04f6 L |
11247 | USED_REX (REX_W); |
11248 | if (rex & REX_W) | |
52b15da3 JH |
11249 | op = get32s (); |
11250 | else if (sizeflag & DFLAG) | |
11251 | { | |
11252 | op = get32 (); | |
11253 | mask = 0xffffffff; | |
11254 | } | |
252b5132 | 11255 | else |
52b15da3 JH |
11256 | { |
11257 | op = get16 (); | |
11258 | mask = 0xfffff; | |
11259 | } | |
7d421014 | 11260 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11261 | break; |
11262 | case w_mode: | |
52b15da3 | 11263 | mask = 0xfffff; |
252b5132 RH |
11264 | op = get16 (); |
11265 | break; | |
9306ca4a JB |
11266 | case const_1_mode: |
11267 | if (intel_syntax) | |
11268 | oappend ("1"); | |
11269 | return; | |
252b5132 RH |
11270 | default: |
11271 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11272 | return; | |
11273 | } | |
11274 | ||
52b15da3 JH |
11275 | op &= mask; |
11276 | scratchbuf[0] = '$'; | |
d708bcba AM |
11277 | print_operand_value (scratchbuf + 1, 1, op); |
11278 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
11279 | scratchbuf[0] = '\0'; |
11280 | } | |
11281 | ||
11282 | static void | |
26ca5450 | 11283 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
11284 | { |
11285 | bfd_signed_vma op; | |
11286 | bfd_signed_vma mask = -1; | |
11287 | ||
cb712a9e | 11288 | if (address_mode != mode_64bit) |
6439fc28 AM |
11289 | { |
11290 | OP_I (bytemode, sizeflag); | |
11291 | return; | |
11292 | } | |
11293 | ||
52b15da3 JH |
11294 | switch (bytemode) |
11295 | { | |
11296 | case b_mode: | |
11297 | FETCH_DATA (the_info, codep + 1); | |
11298 | op = *codep++; | |
11299 | mask = 0xff; | |
11300 | break; | |
11301 | case v_mode: | |
161a04f6 L |
11302 | USED_REX (REX_W); |
11303 | if (rex & REX_W) | |
52b15da3 JH |
11304 | op = get64 (); |
11305 | else if (sizeflag & DFLAG) | |
11306 | { | |
11307 | op = get32 (); | |
11308 | mask = 0xffffffff; | |
11309 | } | |
11310 | else | |
11311 | { | |
11312 | op = get16 (); | |
11313 | mask = 0xfffff; | |
11314 | } | |
11315 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11316 | break; | |
11317 | case w_mode: | |
11318 | mask = 0xfffff; | |
11319 | op = get16 (); | |
11320 | break; | |
11321 | default: | |
11322 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11323 | return; | |
11324 | } | |
11325 | ||
11326 | op &= mask; | |
11327 | scratchbuf[0] = '$'; | |
d708bcba AM |
11328 | print_operand_value (scratchbuf + 1, 1, op); |
11329 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
11330 | scratchbuf[0] = '\0'; |
11331 | } | |
11332 | ||
11333 | static void | |
26ca5450 | 11334 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 11335 | { |
52b15da3 JH |
11336 | bfd_signed_vma op; |
11337 | bfd_signed_vma mask = -1; | |
252b5132 RH |
11338 | |
11339 | switch (bytemode) | |
11340 | { | |
11341 | case b_mode: | |
11342 | FETCH_DATA (the_info, codep + 1); | |
11343 | op = *codep++; | |
11344 | if ((op & 0x80) != 0) | |
11345 | op -= 0x100; | |
52b15da3 | 11346 | mask = 0xffffffff; |
252b5132 RH |
11347 | break; |
11348 | case v_mode: | |
161a04f6 L |
11349 | USED_REX (REX_W); |
11350 | if (rex & REX_W) | |
52b15da3 JH |
11351 | op = get32s (); |
11352 | else if (sizeflag & DFLAG) | |
11353 | { | |
11354 | op = get32s (); | |
11355 | mask = 0xffffffff; | |
11356 | } | |
252b5132 RH |
11357 | else |
11358 | { | |
52b15da3 | 11359 | mask = 0xffffffff; |
6608db57 | 11360 | op = get16 (); |
252b5132 RH |
11361 | if ((op & 0x8000) != 0) |
11362 | op -= 0x10000; | |
11363 | } | |
7d421014 | 11364 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11365 | break; |
11366 | case w_mode: | |
11367 | op = get16 (); | |
52b15da3 | 11368 | mask = 0xffffffff; |
252b5132 RH |
11369 | if ((op & 0x8000) != 0) |
11370 | op -= 0x10000; | |
11371 | break; | |
11372 | default: | |
11373 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11374 | return; | |
11375 | } | |
52b15da3 JH |
11376 | |
11377 | scratchbuf[0] = '$'; | |
11378 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 11379 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11380 | } |
11381 | ||
11382 | static void | |
26ca5450 | 11383 | OP_J (int bytemode, int sizeflag) |
252b5132 | 11384 | { |
52b15da3 | 11385 | bfd_vma disp; |
7081ff04 | 11386 | bfd_vma mask = -1; |
65ca155d | 11387 | bfd_vma segment = 0; |
252b5132 RH |
11388 | |
11389 | switch (bytemode) | |
11390 | { | |
11391 | case b_mode: | |
11392 | FETCH_DATA (the_info, codep + 1); | |
11393 | disp = *codep++; | |
11394 | if ((disp & 0x80) != 0) | |
11395 | disp -= 0x100; | |
11396 | break; | |
11397 | case v_mode: | |
161a04f6 | 11398 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 11399 | disp = get32s (); |
252b5132 RH |
11400 | else |
11401 | { | |
11402 | disp = get16 (); | |
206717e8 L |
11403 | if ((disp & 0x8000) != 0) |
11404 | disp -= 0x10000; | |
65ca155d L |
11405 | /* In 16bit mode, address is wrapped around at 64k within |
11406 | the same segment. Otherwise, a data16 prefix on a jump | |
11407 | instruction means that the pc is masked to 16 bits after | |
11408 | the displacement is added! */ | |
11409 | mask = 0xffff; | |
11410 | if ((prefixes & PREFIX_DATA) == 0) | |
11411 | segment = ((start_pc + codep - start_codep) | |
11412 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 11413 | } |
d807a492 | 11414 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11415 | break; |
11416 | default: | |
11417 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11418 | return; | |
11419 | } | |
65ca155d | 11420 | disp = ((start_pc + codep - start_codep + disp) & mask) | segment; |
52b15da3 JH |
11421 | set_op (disp, 0); |
11422 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
11423 | oappend (scratchbuf); |
11424 | } | |
11425 | ||
252b5132 | 11426 | static void |
ed7841b3 | 11427 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 11428 | { |
ed7841b3 | 11429 | if (bytemode == w_mode) |
7967e09e | 11430 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 11431 | else |
7967e09e | 11432 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
11433 | } |
11434 | ||
11435 | static void | |
26ca5450 | 11436 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
11437 | { |
11438 | int seg, offset; | |
11439 | ||
c608c12e | 11440 | if (sizeflag & DFLAG) |
252b5132 | 11441 | { |
c608c12e AM |
11442 | offset = get32 (); |
11443 | seg = get16 (); | |
252b5132 | 11444 | } |
c608c12e AM |
11445 | else |
11446 | { | |
11447 | offset = get16 (); | |
11448 | seg = get16 (); | |
11449 | } | |
7d421014 | 11450 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 11451 | if (intel_syntax) |
3f31e633 | 11452 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
11453 | else |
11454 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 11455 | oappend (scratchbuf); |
252b5132 RH |
11456 | } |
11457 | ||
252b5132 | 11458 | static void |
3f31e633 | 11459 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 11460 | { |
52b15da3 | 11461 | bfd_vma off; |
252b5132 | 11462 | |
3f31e633 JB |
11463 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
11464 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
11465 | append_seg (); |
11466 | ||
cb712a9e | 11467 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
11468 | off = get32 (); |
11469 | else | |
11470 | off = get16 (); | |
11471 | ||
11472 | if (intel_syntax) | |
11473 | { | |
11474 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 11475 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 11476 | { |
d708bcba | 11477 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
11478 | oappend (":"); |
11479 | } | |
11480 | } | |
52b15da3 JH |
11481 | print_operand_value (scratchbuf, 1, off); |
11482 | oappend (scratchbuf); | |
11483 | } | |
6439fc28 | 11484 | |
52b15da3 | 11485 | static void |
3f31e633 | 11486 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
11487 | { |
11488 | bfd_vma off; | |
11489 | ||
539e75ad L |
11490 | if (address_mode != mode_64bit |
11491 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
11492 | { |
11493 | OP_OFF (bytemode, sizeflag); | |
11494 | return; | |
11495 | } | |
11496 | ||
3f31e633 JB |
11497 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
11498 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
11499 | append_seg (); |
11500 | ||
6608db57 | 11501 | off = get64 (); |
52b15da3 JH |
11502 | |
11503 | if (intel_syntax) | |
11504 | { | |
11505 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 11506 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 11507 | { |
d708bcba | 11508 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
11509 | oappend (":"); |
11510 | } | |
11511 | } | |
11512 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
11513 | oappend (scratchbuf); |
11514 | } | |
11515 | ||
11516 | static void | |
26ca5450 | 11517 | ptr_reg (int code, int sizeflag) |
252b5132 | 11518 | { |
2da11e11 | 11519 | const char *s; |
d708bcba | 11520 | |
1d9f512f | 11521 | *obufp++ = open_char; |
20f0a1fc | 11522 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 11523 | if (address_mode == mode_64bit) |
c1a64871 JH |
11524 | { |
11525 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 11526 | s = names32[code - eAX_reg]; |
c1a64871 | 11527 | else |
db6eb5be | 11528 | s = names64[code - eAX_reg]; |
c1a64871 | 11529 | } |
52b15da3 | 11530 | else if (sizeflag & AFLAG) |
252b5132 RH |
11531 | s = names32[code - eAX_reg]; |
11532 | else | |
11533 | s = names16[code - eAX_reg]; | |
11534 | oappend (s); | |
1d9f512f AM |
11535 | *obufp++ = close_char; |
11536 | *obufp = 0; | |
252b5132 RH |
11537 | } |
11538 | ||
11539 | static void | |
26ca5450 | 11540 | OP_ESreg (int code, int sizeflag) |
252b5132 | 11541 | { |
9306ca4a | 11542 | if (intel_syntax) |
52fd6d94 JB |
11543 | { |
11544 | switch (codep[-1]) | |
11545 | { | |
11546 | case 0x6d: /* insw/insl */ | |
11547 | intel_operand_size (z_mode, sizeflag); | |
11548 | break; | |
11549 | case 0xa5: /* movsw/movsl/movsq */ | |
11550 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
11551 | case 0xab: /* stosw/stosl */ | |
11552 | case 0xaf: /* scasw/scasl */ | |
11553 | intel_operand_size (v_mode, sizeflag); | |
11554 | break; | |
11555 | default: | |
11556 | intel_operand_size (b_mode, sizeflag); | |
11557 | } | |
11558 | } | |
d708bcba | 11559 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
11560 | ptr_reg (code, sizeflag); |
11561 | } | |
11562 | ||
11563 | static void | |
26ca5450 | 11564 | OP_DSreg (int code, int sizeflag) |
252b5132 | 11565 | { |
9306ca4a | 11566 | if (intel_syntax) |
52fd6d94 JB |
11567 | { |
11568 | switch (codep[-1]) | |
11569 | { | |
11570 | case 0x6f: /* outsw/outsl */ | |
11571 | intel_operand_size (z_mode, sizeflag); | |
11572 | break; | |
11573 | case 0xa5: /* movsw/movsl/movsq */ | |
11574 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
11575 | case 0xad: /* lodsw/lodsl/lodsq */ | |
11576 | intel_operand_size (v_mode, sizeflag); | |
11577 | break; | |
11578 | default: | |
11579 | intel_operand_size (b_mode, sizeflag); | |
11580 | } | |
11581 | } | |
252b5132 RH |
11582 | if ((prefixes |
11583 | & (PREFIX_CS | |
11584 | | PREFIX_DS | |
11585 | | PREFIX_SS | |
11586 | | PREFIX_ES | |
11587 | | PREFIX_FS | |
11588 | | PREFIX_GS)) == 0) | |
11589 | prefixes |= PREFIX_DS; | |
6608db57 | 11590 | append_seg (); |
252b5132 RH |
11591 | ptr_reg (code, sizeflag); |
11592 | } | |
11593 | ||
252b5132 | 11594 | static void |
26ca5450 | 11595 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11596 | { |
9b60702d | 11597 | int add; |
161a04f6 | 11598 | if (rex & REX_R) |
c4a530c5 | 11599 | { |
161a04f6 | 11600 | USED_REX (REX_R); |
c4a530c5 JB |
11601 | add = 8; |
11602 | } | |
cb712a9e | 11603 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 11604 | { |
b844680a | 11605 | lock_prefix = NULL; |
c4a530c5 JB |
11606 | used_prefixes |= PREFIX_LOCK; |
11607 | add = 8; | |
11608 | } | |
9b60702d L |
11609 | else |
11610 | add = 0; | |
7967e09e | 11611 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 11612 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11613 | } |
11614 | ||
252b5132 | 11615 | static void |
26ca5450 | 11616 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11617 | { |
9b60702d | 11618 | int add; |
161a04f6 L |
11619 | USED_REX (REX_R); |
11620 | if (rex & REX_R) | |
52b15da3 | 11621 | add = 8; |
9b60702d L |
11622 | else |
11623 | add = 0; | |
d708bcba | 11624 | if (intel_syntax) |
7967e09e | 11625 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 11626 | else |
7967e09e | 11627 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
11628 | oappend (scratchbuf); |
11629 | } | |
11630 | ||
252b5132 | 11631 | static void |
26ca5450 | 11632 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11633 | { |
7967e09e | 11634 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 11635 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11636 | } |
11637 | ||
11638 | static void | |
6f74c397 | 11639 | OP_R (int bytemode, int sizeflag) |
252b5132 | 11640 | { |
7967e09e | 11641 | if (modrm.mod == 3) |
2da11e11 AM |
11642 | OP_E (bytemode, sizeflag); |
11643 | else | |
6608db57 | 11644 | BadOp (); |
252b5132 RH |
11645 | } |
11646 | ||
11647 | static void | |
26ca5450 | 11648 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11649 | { |
041bd2e0 JH |
11650 | used_prefixes |= (prefixes & PREFIX_DATA); |
11651 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 11652 | { |
9b60702d | 11653 | int add; |
161a04f6 L |
11654 | USED_REX (REX_R); |
11655 | if (rex & REX_R) | |
20f0a1fc | 11656 | add = 8; |
9b60702d L |
11657 | else |
11658 | add = 0; | |
7967e09e | 11659 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); |
20f0a1fc | 11660 | } |
041bd2e0 | 11661 | else |
7967e09e | 11662 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
d708bcba | 11663 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11664 | } |
11665 | ||
c608c12e | 11666 | static void |
c0f3af97 | 11667 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 11668 | { |
9b60702d | 11669 | int add; |
161a04f6 L |
11670 | USED_REX (REX_R); |
11671 | if (rex & REX_R) | |
041bd2e0 | 11672 | add = 8; |
9b60702d L |
11673 | else |
11674 | add = 0; | |
c0f3af97 L |
11675 | if (need_vex && bytemode != xmm_mode) |
11676 | { | |
11677 | switch (vex.length) | |
11678 | { | |
11679 | case 128: | |
11680 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); | |
11681 | break; | |
11682 | case 256: | |
11683 | sprintf (scratchbuf, "%%ymm%d", modrm.reg + add); | |
11684 | break; | |
11685 | default: | |
11686 | abort (); | |
11687 | } | |
11688 | } | |
11689 | else | |
11690 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); | |
d708bcba | 11691 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
11692 | } |
11693 | ||
252b5132 | 11694 | static void |
26ca5450 | 11695 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 11696 | { |
7967e09e | 11697 | if (modrm.mod != 3) |
252b5132 | 11698 | { |
b6169b20 L |
11699 | if (intel_syntax |
11700 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
11701 | { |
11702 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
11703 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11704 | } | |
252b5132 RH |
11705 | OP_E (bytemode, sizeflag); |
11706 | return; | |
11707 | } | |
11708 | ||
b6169b20 L |
11709 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
11710 | swap_operand (); | |
11711 | ||
6608db57 | 11712 | /* Skip mod/rm byte. */ |
4bba6815 | 11713 | MODRM_CHECK; |
252b5132 | 11714 | codep++; |
041bd2e0 JH |
11715 | used_prefixes |= (prefixes & PREFIX_DATA); |
11716 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 11717 | { |
9b60702d | 11718 | int add; |
20f0a1fc | 11719 | |
161a04f6 L |
11720 | USED_REX (REX_B); |
11721 | if (rex & REX_B) | |
20f0a1fc | 11722 | add = 8; |
9b60702d L |
11723 | else |
11724 | add = 0; | |
7967e09e | 11725 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); |
20f0a1fc | 11726 | } |
041bd2e0 | 11727 | else |
7967e09e | 11728 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
d708bcba | 11729 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11730 | } |
11731 | ||
246c51aa L |
11732 | /* cvt* are the only instructions in sse2 which have |
11733 | both SSE and MMX operands and also have 0x66 prefix | |
11734 | in their opcode. 0x66 was originally used to differentiate | |
11735 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
11736 | cvt* separately using OP_EMC and OP_MXC */ |
11737 | static void | |
11738 | OP_EMC (int bytemode, int sizeflag) | |
11739 | { | |
7967e09e | 11740 | if (modrm.mod != 3) |
4d9567e0 MM |
11741 | { |
11742 | if (intel_syntax && bytemode == v_mode) | |
11743 | { | |
11744 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
11745 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11746 | } | |
11747 | OP_E (bytemode, sizeflag); | |
11748 | return; | |
11749 | } | |
246c51aa | 11750 | |
4d9567e0 MM |
11751 | /* Skip mod/rm byte. */ |
11752 | MODRM_CHECK; | |
11753 | codep++; | |
11754 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 11755 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
4d9567e0 MM |
11756 | oappend (scratchbuf + intel_syntax); |
11757 | } | |
11758 | ||
11759 | static void | |
11760 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
11761 | { | |
11762 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 11763 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
4d9567e0 MM |
11764 | oappend (scratchbuf + intel_syntax); |
11765 | } | |
11766 | ||
c608c12e | 11767 | static void |
26ca5450 | 11768 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 11769 | { |
9b60702d | 11770 | int add; |
d6f574e0 L |
11771 | |
11772 | /* Skip mod/rm byte. */ | |
11773 | MODRM_CHECK; | |
11774 | codep++; | |
11775 | ||
7967e09e | 11776 | if (modrm.mod != 3) |
c608c12e | 11777 | { |
c1e679ec | 11778 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
11779 | return; |
11780 | } | |
d6f574e0 | 11781 | |
161a04f6 L |
11782 | USED_REX (REX_B); |
11783 | if (rex & REX_B) | |
041bd2e0 | 11784 | add = 8; |
9b60702d L |
11785 | else |
11786 | add = 0; | |
c608c12e | 11787 | |
b6169b20 | 11788 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
11789 | && (bytemode == x_swap_mode |
11790 | || bytemode == d_swap_mode | |
11791 | || bytemode == q_swap_mode)) | |
b6169b20 L |
11792 | swap_operand (); |
11793 | ||
c0f3af97 L |
11794 | if (need_vex |
11795 | && bytemode != xmm_mode | |
11796 | && bytemode != xmmq_mode) | |
11797 | { | |
11798 | switch (vex.length) | |
11799 | { | |
11800 | case 128: | |
11801 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); | |
11802 | break; | |
11803 | case 256: | |
11804 | sprintf (scratchbuf, "%%ymm%d", modrm.rm + add); | |
11805 | break; | |
11806 | default: | |
11807 | abort (); | |
11808 | } | |
11809 | } | |
11810 | else | |
11811 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); | |
d708bcba | 11812 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
11813 | } |
11814 | ||
252b5132 | 11815 | static void |
26ca5450 | 11816 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 11817 | { |
7967e09e | 11818 | if (modrm.mod == 3) |
2da11e11 AM |
11819 | OP_EM (bytemode, sizeflag); |
11820 | else | |
6608db57 | 11821 | BadOp (); |
252b5132 RH |
11822 | } |
11823 | ||
992aaec9 | 11824 | static void |
26ca5450 | 11825 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 11826 | { |
7967e09e | 11827 | if (modrm.mod == 3) |
992aaec9 AM |
11828 | OP_EX (bytemode, sizeflag); |
11829 | else | |
6608db57 | 11830 | BadOp (); |
992aaec9 AM |
11831 | } |
11832 | ||
cc0ec051 AM |
11833 | static void |
11834 | OP_M (int bytemode, int sizeflag) | |
11835 | { | |
7967e09e | 11836 | if (modrm.mod == 3) |
75413a22 L |
11837 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
11838 | BadOp (); | |
cc0ec051 AM |
11839 | else |
11840 | OP_E (bytemode, sizeflag); | |
11841 | } | |
11842 | ||
11843 | static void | |
11844 | OP_0f07 (int bytemode, int sizeflag) | |
11845 | { | |
7967e09e | 11846 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
11847 | BadOp (); |
11848 | else | |
11849 | OP_E (bytemode, sizeflag); | |
11850 | } | |
11851 | ||
46e883c5 | 11852 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 11853 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 11854 | |
cc0ec051 | 11855 | static void |
46e883c5 | 11856 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 11857 | { |
8b38ad71 L |
11858 | if ((prefixes & PREFIX_DATA) != 0 |
11859 | || (rex != 0 | |
11860 | && rex != 0x48 | |
11861 | && address_mode == mode_64bit)) | |
46e883c5 L |
11862 | OP_REG (bytemode, sizeflag); |
11863 | else | |
11864 | strcpy (obuf, "nop"); | |
11865 | } | |
11866 | ||
11867 | static void | |
11868 | NOP_Fixup2 (int bytemode, int sizeflag) | |
11869 | { | |
8b38ad71 L |
11870 | if ((prefixes & PREFIX_DATA) != 0 |
11871 | || (rex != 0 | |
11872 | && rex != 0x48 | |
11873 | && address_mode == mode_64bit)) | |
46e883c5 | 11874 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
11875 | } |
11876 | ||
84037f8c | 11877 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
11878 | /* 00 */ NULL, NULL, NULL, NULL, |
11879 | /* 04 */ NULL, NULL, NULL, NULL, | |
11880 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 11881 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
11882 | /* 10 */ NULL, NULL, NULL, NULL, |
11883 | /* 14 */ NULL, NULL, NULL, NULL, | |
11884 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 11885 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
11886 | /* 20 */ NULL, NULL, NULL, NULL, |
11887 | /* 24 */ NULL, NULL, NULL, NULL, | |
11888 | /* 28 */ NULL, NULL, NULL, NULL, | |
11889 | /* 2C */ NULL, NULL, NULL, NULL, | |
11890 | /* 30 */ NULL, NULL, NULL, NULL, | |
11891 | /* 34 */ NULL, NULL, NULL, NULL, | |
11892 | /* 38 */ NULL, NULL, NULL, NULL, | |
11893 | /* 3C */ NULL, NULL, NULL, NULL, | |
11894 | /* 40 */ NULL, NULL, NULL, NULL, | |
11895 | /* 44 */ NULL, NULL, NULL, NULL, | |
11896 | /* 48 */ NULL, NULL, NULL, NULL, | |
11897 | /* 4C */ NULL, NULL, NULL, NULL, | |
11898 | /* 50 */ NULL, NULL, NULL, NULL, | |
11899 | /* 54 */ NULL, NULL, NULL, NULL, | |
11900 | /* 58 */ NULL, NULL, NULL, NULL, | |
11901 | /* 5C */ NULL, NULL, NULL, NULL, | |
11902 | /* 60 */ NULL, NULL, NULL, NULL, | |
11903 | /* 64 */ NULL, NULL, NULL, NULL, | |
11904 | /* 68 */ NULL, NULL, NULL, NULL, | |
11905 | /* 6C */ NULL, NULL, NULL, NULL, | |
11906 | /* 70 */ NULL, NULL, NULL, NULL, | |
11907 | /* 74 */ NULL, NULL, NULL, NULL, | |
11908 | /* 78 */ NULL, NULL, NULL, NULL, | |
11909 | /* 7C */ NULL, NULL, NULL, NULL, | |
11910 | /* 80 */ NULL, NULL, NULL, NULL, | |
11911 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
11912 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
11913 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
11914 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
11915 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
11916 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
11917 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
11918 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
11919 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
11920 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
11921 | /* AC */ NULL, NULL, "pfacc", NULL, | |
11922 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 11923 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 11924 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
11925 | /* BC */ NULL, NULL, NULL, "pavgusb", |
11926 | /* C0 */ NULL, NULL, NULL, NULL, | |
11927 | /* C4 */ NULL, NULL, NULL, NULL, | |
11928 | /* C8 */ NULL, NULL, NULL, NULL, | |
11929 | /* CC */ NULL, NULL, NULL, NULL, | |
11930 | /* D0 */ NULL, NULL, NULL, NULL, | |
11931 | /* D4 */ NULL, NULL, NULL, NULL, | |
11932 | /* D8 */ NULL, NULL, NULL, NULL, | |
11933 | /* DC */ NULL, NULL, NULL, NULL, | |
11934 | /* E0 */ NULL, NULL, NULL, NULL, | |
11935 | /* E4 */ NULL, NULL, NULL, NULL, | |
11936 | /* E8 */ NULL, NULL, NULL, NULL, | |
11937 | /* EC */ NULL, NULL, NULL, NULL, | |
11938 | /* F0 */ NULL, NULL, NULL, NULL, | |
11939 | /* F4 */ NULL, NULL, NULL, NULL, | |
11940 | /* F8 */ NULL, NULL, NULL, NULL, | |
11941 | /* FC */ NULL, NULL, NULL, NULL, | |
11942 | }; | |
11943 | ||
11944 | static void | |
26ca5450 | 11945 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
11946 | { |
11947 | const char *mnemonic; | |
11948 | ||
11949 | FETCH_DATA (the_info, codep + 1); | |
11950 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
11951 | place where an 8-bit immediate would normally go. ie. the last | |
11952 | byte of the instruction. */ | |
ea397f5b | 11953 | obufp = mnemonicendp; |
c608c12e | 11954 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 11955 | if (mnemonic) |
2da11e11 | 11956 | oappend (mnemonic); |
252b5132 RH |
11957 | else |
11958 | { | |
11959 | /* Since a variable sized modrm/sib chunk is between the start | |
11960 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
11961 | all the modrm processing first, and don't know until now that | |
11962 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
11963 | op_out[0][0] = '\0'; |
11964 | op_out[1][0] = '\0'; | |
6608db57 | 11965 | BadOp (); |
252b5132 | 11966 | } |
ea397f5b | 11967 | mnemonicendp = obufp; |
252b5132 | 11968 | } |
c608c12e | 11969 | |
ea397f5b L |
11970 | static struct op simd_cmp_op[] = |
11971 | { | |
11972 | { STRING_COMMA_LEN ("eq") }, | |
11973 | { STRING_COMMA_LEN ("lt") }, | |
11974 | { STRING_COMMA_LEN ("le") }, | |
11975 | { STRING_COMMA_LEN ("unord") }, | |
11976 | { STRING_COMMA_LEN ("neq") }, | |
11977 | { STRING_COMMA_LEN ("nlt") }, | |
11978 | { STRING_COMMA_LEN ("nle") }, | |
11979 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
11980 | }; |
11981 | ||
11982 | static void | |
ad19981d | 11983 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
11984 | { |
11985 | unsigned int cmp_type; | |
11986 | ||
11987 | FETCH_DATA (the_info, codep + 1); | |
11988 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 11989 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 11990 | { |
ad19981d | 11991 | char suffix [3]; |
ea397f5b | 11992 | char *p = mnemonicendp - 2; |
ad19981d L |
11993 | suffix[0] = p[0]; |
11994 | suffix[1] = p[1]; | |
11995 | suffix[2] = '\0'; | |
ea397f5b L |
11996 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
11997 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
11998 | } |
11999 | else | |
12000 | { | |
ad19981d L |
12001 | /* We have a reserved extension byte. Output it directly. */ |
12002 | scratchbuf[0] = '$'; | |
12003 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
12004 | oappend (scratchbuf + intel_syntax); | |
12005 | scratchbuf[0] = '\0'; | |
c608c12e AM |
12006 | } |
12007 | } | |
12008 | ||
ca164297 | 12009 | static void |
b844680a L |
12010 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
12011 | int sizeflag ATTRIBUTE_UNUSED) | |
12012 | { | |
12013 | /* mwait %eax,%ecx */ | |
12014 | if (!intel_syntax) | |
12015 | { | |
12016 | const char **names = (address_mode == mode_64bit | |
12017 | ? names64 : names32); | |
12018 | strcpy (op_out[0], names[0]); | |
12019 | strcpy (op_out[1], names[1]); | |
12020 | two_source_ops = 1; | |
12021 | } | |
12022 | /* Skip mod/rm byte. */ | |
12023 | MODRM_CHECK; | |
12024 | codep++; | |
12025 | } | |
12026 | ||
12027 | static void | |
12028 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
12029 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 12030 | { |
b844680a L |
12031 | /* monitor %eax,%ecx,%edx" */ |
12032 | if (!intel_syntax) | |
ca164297 | 12033 | { |
b844680a | 12034 | const char **op1_names; |
cb712a9e L |
12035 | const char **names = (address_mode == mode_64bit |
12036 | ? names64 : names32); | |
1d9f512f | 12037 | |
b844680a L |
12038 | if (!(prefixes & PREFIX_ADDR)) |
12039 | op1_names = (address_mode == mode_16bit | |
12040 | ? names16 : names); | |
ca164297 L |
12041 | else |
12042 | { | |
b844680a L |
12043 | /* Remove "addr16/addr32". */ |
12044 | addr_prefix = NULL; | |
12045 | op1_names = (address_mode != mode_32bit | |
12046 | ? names32 : names16); | |
12047 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 12048 | } |
b844680a L |
12049 | strcpy (op_out[0], op1_names[0]); |
12050 | strcpy (op_out[1], names[1]); | |
12051 | strcpy (op_out[2], names[2]); | |
12052 | two_source_ops = 1; | |
ca164297 | 12053 | } |
b844680a L |
12054 | /* Skip mod/rm byte. */ |
12055 | MODRM_CHECK; | |
12056 | codep++; | |
30123838 JB |
12057 | } |
12058 | ||
6608db57 KH |
12059 | static void |
12060 | BadOp (void) | |
2da11e11 | 12061 | { |
6608db57 KH |
12062 | /* Throw away prefixes and 1st. opcode byte. */ |
12063 | codep = insn_codep + 1; | |
2da11e11 AM |
12064 | oappend ("(bad)"); |
12065 | } | |
4cc91dba | 12066 | |
35c52694 L |
12067 | static void |
12068 | REP_Fixup (int bytemode, int sizeflag) | |
12069 | { | |
12070 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
12071 | lods and stos. */ | |
35c52694 | 12072 | if (prefixes & PREFIX_REPZ) |
b844680a | 12073 | repz_prefix = "rep "; |
35c52694 L |
12074 | |
12075 | switch (bytemode) | |
12076 | { | |
12077 | case al_reg: | |
12078 | case eAX_reg: | |
12079 | case indir_dx_reg: | |
12080 | OP_IMREG (bytemode, sizeflag); | |
12081 | break; | |
12082 | case eDI_reg: | |
12083 | OP_ESreg (bytemode, sizeflag); | |
12084 | break; | |
12085 | case eSI_reg: | |
12086 | OP_DSreg (bytemode, sizeflag); | |
12087 | break; | |
12088 | default: | |
12089 | abort (); | |
12090 | break; | |
12091 | } | |
12092 | } | |
f5804c90 L |
12093 | |
12094 | static void | |
12095 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
12096 | { | |
161a04f6 L |
12097 | USED_REX (REX_W); |
12098 | if (rex & REX_W) | |
f5804c90 L |
12099 | { |
12100 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
12101 | char *p = mnemonicendp - 2; |
12102 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 12103 | bytemode = o_mode; |
f5804c90 L |
12104 | } |
12105 | OP_M (bytemode, sizeflag); | |
12106 | } | |
42903f7f L |
12107 | |
12108 | static void | |
12109 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
12110 | { | |
c0f3af97 L |
12111 | if (need_vex) |
12112 | { | |
12113 | switch (vex.length) | |
12114 | { | |
12115 | case 128: | |
12116 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12117 | break; | |
12118 | case 256: | |
12119 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12120 | break; | |
12121 | default: | |
12122 | abort (); | |
12123 | } | |
12124 | } | |
12125 | else | |
12126 | sprintf (scratchbuf, "%%xmm%d", reg); | |
42903f7f L |
12127 | oappend (scratchbuf + intel_syntax); |
12128 | } | |
381d071f L |
12129 | |
12130 | static void | |
12131 | CRC32_Fixup (int bytemode, int sizeflag) | |
12132 | { | |
12133 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 12134 | char *p = mnemonicendp; |
381d071f L |
12135 | |
12136 | switch (bytemode) | |
12137 | { | |
12138 | case b_mode: | |
20592a94 | 12139 | if (intel_syntax) |
ea397f5b | 12140 | goto skip; |
20592a94 | 12141 | |
381d071f L |
12142 | *p++ = 'b'; |
12143 | break; | |
12144 | case v_mode: | |
20592a94 | 12145 | if (intel_syntax) |
ea397f5b | 12146 | goto skip; |
20592a94 | 12147 | |
381d071f L |
12148 | USED_REX (REX_W); |
12149 | if (rex & REX_W) | |
12150 | *p++ = 'q'; | |
9344ff29 | 12151 | else if (sizeflag & DFLAG) |
20592a94 | 12152 | *p++ = 'l'; |
381d071f | 12153 | else |
9344ff29 L |
12154 | *p++ = 'w'; |
12155 | used_prefixes |= (prefixes & PREFIX_DATA); | |
381d071f L |
12156 | break; |
12157 | default: | |
12158 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12159 | break; | |
12160 | } | |
ea397f5b | 12161 | mnemonicendp = p; |
381d071f L |
12162 | *p = '\0'; |
12163 | ||
ea397f5b | 12164 | skip: |
381d071f L |
12165 | if (modrm.mod == 3) |
12166 | { | |
12167 | int add; | |
12168 | ||
12169 | /* Skip mod/rm byte. */ | |
12170 | MODRM_CHECK; | |
12171 | codep++; | |
12172 | ||
12173 | USED_REX (REX_B); | |
12174 | add = (rex & REX_B) ? 8 : 0; | |
12175 | if (bytemode == b_mode) | |
12176 | { | |
12177 | USED_REX (0); | |
12178 | if (rex) | |
12179 | oappend (names8rex[modrm.rm + add]); | |
12180 | else | |
12181 | oappend (names8[modrm.rm + add]); | |
12182 | } | |
12183 | else | |
12184 | { | |
12185 | USED_REX (REX_W); | |
12186 | if (rex & REX_W) | |
12187 | oappend (names64[modrm.rm + add]); | |
12188 | else if ((prefixes & PREFIX_DATA)) | |
12189 | oappend (names16[modrm.rm + add]); | |
12190 | else | |
12191 | oappend (names32[modrm.rm + add]); | |
12192 | } | |
12193 | } | |
12194 | else | |
9344ff29 | 12195 | OP_E (bytemode, sizeflag); |
381d071f | 12196 | } |
85f10a01 | 12197 | |
c0f3af97 L |
12198 | /* Display the destination register operand for instructions with |
12199 | VEX. */ | |
12200 | ||
12201 | static void | |
12202 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
12203 | { | |
12204 | if (!need_vex) | |
12205 | abort (); | |
12206 | ||
12207 | if (!need_vex_reg) | |
12208 | return; | |
12209 | ||
12210 | switch (vex.length) | |
12211 | { | |
12212 | case 128: | |
12213 | switch (bytemode) | |
12214 | { | |
12215 | case vex_mode: | |
12216 | case vex128_mode: | |
12217 | break; | |
12218 | default: | |
12219 | abort (); | |
12220 | return; | |
12221 | } | |
12222 | ||
12223 | sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); | |
12224 | break; | |
12225 | case 256: | |
12226 | switch (bytemode) | |
12227 | { | |
12228 | case vex_mode: | |
12229 | case vex256_mode: | |
12230 | break; | |
12231 | default: | |
12232 | abort (); | |
12233 | return; | |
12234 | } | |
12235 | ||
12236 | sprintf (scratchbuf, "%%ymm%d", vex.register_specifier); | |
12237 | break; | |
12238 | default: | |
12239 | abort (); | |
12240 | break; | |
12241 | } | |
12242 | oappend (scratchbuf + intel_syntax); | |
12243 | } | |
12244 | ||
c0f3af97 L |
12245 | static void |
12246 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
12247 | { | |
12248 | int reg; | |
12249 | FETCH_DATA (the_info, codep + 1); | |
12250 | reg = *codep++; | |
12251 | ||
12252 | if (bytemode != x_mode) | |
12253 | abort (); | |
12254 | ||
12255 | if (reg & 0xf) | |
12256 | BadOp (); | |
12257 | ||
12258 | reg >>= 4; | |
dae39acc L |
12259 | if (reg > 7 && address_mode != mode_64bit) |
12260 | BadOp (); | |
12261 | ||
c0f3af97 L |
12262 | switch (vex.length) |
12263 | { | |
12264 | case 128: | |
12265 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12266 | break; | |
12267 | case 256: | |
12268 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12269 | break; | |
12270 | default: | |
12271 | abort (); | |
12272 | } | |
12273 | oappend (scratchbuf + intel_syntax); | |
12274 | } | |
12275 | ||
c0f3af97 L |
12276 | static void |
12277 | OP_EX_Vex (int bytemode, int sizeflag) | |
12278 | { | |
12279 | if (modrm.mod != 3) | |
12280 | { | |
12281 | if (vex.register_specifier != 0) | |
12282 | BadOp (); | |
12283 | need_vex_reg = 0; | |
12284 | } | |
12285 | OP_EX (bytemode, sizeflag); | |
12286 | } | |
12287 | ||
12288 | static void | |
12289 | OP_XMM_Vex (int bytemode, int sizeflag) | |
12290 | { | |
12291 | if (modrm.mod != 3) | |
12292 | { | |
12293 | if (vex.register_specifier != 0) | |
12294 | BadOp (); | |
12295 | need_vex_reg = 0; | |
12296 | } | |
12297 | OP_XMM (bytemode, sizeflag); | |
12298 | } | |
12299 | ||
12300 | static void | |
12301 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12302 | { | |
12303 | switch (vex.length) | |
12304 | { | |
12305 | case 128: | |
ea397f5b | 12306 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
12307 | break; |
12308 | case 256: | |
ea397f5b | 12309 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
12310 | break; |
12311 | default: | |
12312 | abort (); | |
12313 | } | |
12314 | } | |
12315 | ||
ea397f5b L |
12316 | static struct op vex_cmp_op[] = |
12317 | { | |
12318 | { STRING_COMMA_LEN ("eq") }, | |
12319 | { STRING_COMMA_LEN ("lt") }, | |
12320 | { STRING_COMMA_LEN ("le") }, | |
12321 | { STRING_COMMA_LEN ("unord") }, | |
12322 | { STRING_COMMA_LEN ("neq") }, | |
12323 | { STRING_COMMA_LEN ("nlt") }, | |
12324 | { STRING_COMMA_LEN ("nle") }, | |
12325 | { STRING_COMMA_LEN ("ord") }, | |
12326 | { STRING_COMMA_LEN ("eq_uq") }, | |
12327 | { STRING_COMMA_LEN ("nge") }, | |
12328 | { STRING_COMMA_LEN ("ngt") }, | |
12329 | { STRING_COMMA_LEN ("false") }, | |
12330 | { STRING_COMMA_LEN ("neq_oq") }, | |
12331 | { STRING_COMMA_LEN ("ge") }, | |
12332 | { STRING_COMMA_LEN ("gt") }, | |
12333 | { STRING_COMMA_LEN ("true") }, | |
12334 | { STRING_COMMA_LEN ("eq_os") }, | |
12335 | { STRING_COMMA_LEN ("lt_oq") }, | |
12336 | { STRING_COMMA_LEN ("le_oq") }, | |
12337 | { STRING_COMMA_LEN ("unord_s") }, | |
12338 | { STRING_COMMA_LEN ("neq_us") }, | |
12339 | { STRING_COMMA_LEN ("nlt_uq") }, | |
12340 | { STRING_COMMA_LEN ("nle_uq") }, | |
12341 | { STRING_COMMA_LEN ("ord_s") }, | |
12342 | { STRING_COMMA_LEN ("eq_us") }, | |
12343 | { STRING_COMMA_LEN ("nge_uq") }, | |
12344 | { STRING_COMMA_LEN ("ngt_uq") }, | |
12345 | { STRING_COMMA_LEN ("false_os") }, | |
12346 | { STRING_COMMA_LEN ("neq_os") }, | |
12347 | { STRING_COMMA_LEN ("ge_oq") }, | |
12348 | { STRING_COMMA_LEN ("gt_oq") }, | |
12349 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
12350 | }; |
12351 | ||
12352 | static void | |
12353 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12354 | { | |
12355 | unsigned int cmp_type; | |
12356 | ||
12357 | FETCH_DATA (the_info, codep + 1); | |
12358 | cmp_type = *codep++ & 0xff; | |
12359 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
12360 | { | |
12361 | char suffix [3]; | |
ea397f5b | 12362 | char *p = mnemonicendp - 2; |
c0f3af97 L |
12363 | suffix[0] = p[0]; |
12364 | suffix[1] = p[1]; | |
12365 | suffix[2] = '\0'; | |
ea397f5b L |
12366 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
12367 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
12368 | } |
12369 | else | |
12370 | { | |
12371 | /* We have a reserved extension byte. Output it directly. */ | |
12372 | scratchbuf[0] = '$'; | |
12373 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
12374 | oappend (scratchbuf + intel_syntax); | |
12375 | scratchbuf[0] = '\0'; | |
12376 | } | |
12377 | } | |
12378 | ||
ea397f5b L |
12379 | static const struct op pclmul_op[] = |
12380 | { | |
12381 | { STRING_COMMA_LEN ("lql") }, | |
12382 | { STRING_COMMA_LEN ("hql") }, | |
12383 | { STRING_COMMA_LEN ("lqh") }, | |
12384 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
12385 | }; |
12386 | ||
12387 | static void | |
12388 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
12389 | int sizeflag ATTRIBUTE_UNUSED) | |
12390 | { | |
12391 | unsigned int pclmul_type; | |
12392 | ||
12393 | FETCH_DATA (the_info, codep + 1); | |
12394 | pclmul_type = *codep++ & 0xff; | |
12395 | switch (pclmul_type) | |
12396 | { | |
12397 | case 0x10: | |
12398 | pclmul_type = 2; | |
12399 | break; | |
12400 | case 0x11: | |
12401 | pclmul_type = 3; | |
12402 | break; | |
12403 | default: | |
12404 | break; | |
12405 | } | |
12406 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) | |
12407 | { | |
12408 | char suffix [4]; | |
ea397f5b | 12409 | char *p = mnemonicendp - 3; |
c0f3af97 L |
12410 | suffix[0] = p[0]; |
12411 | suffix[1] = p[1]; | |
12412 | suffix[2] = p[2]; | |
12413 | suffix[3] = '\0'; | |
ea397f5b L |
12414 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
12415 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
12416 | } |
12417 | else | |
12418 | { | |
12419 | /* We have a reserved extension byte. Output it directly. */ | |
12420 | scratchbuf[0] = '$'; | |
12421 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
12422 | oappend (scratchbuf + intel_syntax); | |
12423 | scratchbuf[0] = '\0'; | |
12424 | } | |
12425 | } | |
12426 | ||
f1f8f695 L |
12427 | static void |
12428 | MOVBE_Fixup (int bytemode, int sizeflag) | |
12429 | { | |
12430 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 12431 | char *p = mnemonicendp; |
f1f8f695 L |
12432 | |
12433 | switch (bytemode) | |
12434 | { | |
12435 | case v_mode: | |
12436 | if (intel_syntax) | |
ea397f5b | 12437 | goto skip; |
f1f8f695 L |
12438 | |
12439 | USED_REX (REX_W); | |
12440 | if (sizeflag & SUFFIX_ALWAYS) | |
12441 | { | |
12442 | if (rex & REX_W) | |
12443 | *p++ = 'q'; | |
12444 | else if (sizeflag & DFLAG) | |
12445 | *p++ = 'l'; | |
12446 | else | |
12447 | *p++ = 'w'; | |
12448 | } | |
12449 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12450 | break; | |
12451 | default: | |
12452 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12453 | break; | |
12454 | } | |
ea397f5b | 12455 | mnemonicendp = p; |
f1f8f695 L |
12456 | *p = '\0'; |
12457 | ||
ea397f5b | 12458 | skip: |
f1f8f695 L |
12459 | OP_M (bytemode, sizeflag); |
12460 | } |