Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
bc31405e | 127 | static void MOVSXD_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 251 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 252 | #define Ev { OP_E, v_mode } |
de89d0a3 | 253 | #define Eva { OP_E, va_mode } |
7e8b059b | 254 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 255 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
256 | #define Ed { OP_E, d_mode } |
257 | #define Edq { OP_E, dq_mode } | |
258 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 259 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
260 | #define Edb { OP_E, db_mode } |
261 | #define Edw { OP_E, dw_mode } | |
42903f7f | 262 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 263 | #define Eq { OP_E, q_mode } |
07f5af7d | 264 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
265 | #define indirEp { OP_indirE, f_mode } |
266 | #define stackEv { OP_E, stack_v_mode } | |
267 | #define Em { OP_E, m_mode } | |
268 | #define Ew { OP_E, w_mode } | |
269 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 270 | #define Ma { OP_M, a_mode } |
b844680a | 271 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 272 | #define Md { OP_M, d_mode } |
f1f8f695 | 273 | #define Mo { OP_M, o_mode } |
ce518a5f L |
274 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
275 | #define Mq { OP_M, q_mode } | |
d276ec69 | 276 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 277 | #define Mx { OP_M, x_mode } |
c0f3af97 | 278 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 279 | #define Gb { OP_G, b_mode } |
7e8b059b | 280 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
281 | #define Gv { OP_G, v_mode } |
282 | #define Gd { OP_G, d_mode } | |
283 | #define Gdq { OP_G, dq_mode } | |
284 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 285 | #define Gva { OP_G, va_mode } |
ce518a5f | 286 | #define Gw { OP_G, w_mode } |
6f74c397 | 287 | #define Rd { OP_R, d_mode } |
43234a1e | 288 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 289 | #define Rm { OP_R, m_mode } |
ce518a5f L |
290 | #define Ib { OP_I, b_mode } |
291 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 292 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 293 | #define Iv { OP_I, v_mode } |
7bb15c6f | 294 | #define sIv { OP_sI, v_mode } |
ce518a5f | 295 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 296 | #define Id { OP_I, d_mode } |
ce518a5f L |
297 | #define Iw { OP_I, w_mode } |
298 | #define I1 { OP_I, const_1_mode } | |
299 | #define Jb { OP_J, b_mode } | |
300 | #define Jv { OP_J, v_mode } | |
376cd056 | 301 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
302 | #define Cm { OP_C, m_mode } |
303 | #define Dm { OP_D, m_mode } | |
304 | #define Td { OP_T, d_mode } | |
b844680a | 305 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
306 | |
307 | #define RMeAX { OP_REG, eAX_reg } | |
308 | #define RMeBX { OP_REG, eBX_reg } | |
309 | #define RMeCX { OP_REG, eCX_reg } | |
310 | #define RMeDX { OP_REG, eDX_reg } | |
311 | #define RMeSP { OP_REG, eSP_reg } | |
312 | #define RMeBP { OP_REG, eBP_reg } | |
313 | #define RMeSI { OP_REG, eSI_reg } | |
314 | #define RMeDI { OP_REG, eDI_reg } | |
315 | #define RMrAX { OP_REG, rAX_reg } | |
316 | #define RMrBX { OP_REG, rBX_reg } | |
317 | #define RMrCX { OP_REG, rCX_reg } | |
318 | #define RMrDX { OP_REG, rDX_reg } | |
319 | #define RMrSP { OP_REG, rSP_reg } | |
320 | #define RMrBP { OP_REG, rBP_reg } | |
321 | #define RMrSI { OP_REG, rSI_reg } | |
322 | #define RMrDI { OP_REG, rDI_reg } | |
323 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
324 | #define RMCL { OP_REG, cl_reg } |
325 | #define RMDL { OP_REG, dl_reg } | |
326 | #define RMBL { OP_REG, bl_reg } | |
327 | #define RMAH { OP_REG, ah_reg } | |
328 | #define RMCH { OP_REG, ch_reg } | |
329 | #define RMDH { OP_REG, dh_reg } | |
330 | #define RMBH { OP_REG, bh_reg } | |
331 | #define RMAX { OP_REG, ax_reg } | |
332 | #define RMDX { OP_REG, dx_reg } | |
333 | ||
334 | #define eAX { OP_IMREG, eAX_reg } | |
335 | #define eBX { OP_IMREG, eBX_reg } | |
336 | #define eCX { OP_IMREG, eCX_reg } | |
337 | #define eDX { OP_IMREG, eDX_reg } | |
338 | #define eSP { OP_IMREG, eSP_reg } | |
339 | #define eBP { OP_IMREG, eBP_reg } | |
340 | #define eSI { OP_IMREG, eSI_reg } | |
341 | #define eDI { OP_IMREG, eDI_reg } | |
342 | #define AL { OP_IMREG, al_reg } | |
343 | #define CL { OP_IMREG, cl_reg } | |
344 | #define DL { OP_IMREG, dl_reg } | |
345 | #define BL { OP_IMREG, bl_reg } | |
346 | #define AH { OP_IMREG, ah_reg } | |
347 | #define CH { OP_IMREG, ch_reg } | |
348 | #define DH { OP_IMREG, dh_reg } | |
349 | #define BH { OP_IMREG, bh_reg } | |
350 | #define AX { OP_IMREG, ax_reg } | |
351 | #define DX { OP_IMREG, dx_reg } | |
352 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
353 | #define indirDX { OP_IMREG, indir_dx_reg } | |
354 | ||
355 | #define Sw { OP_SEG, w_mode } | |
356 | #define Sv { OP_SEG, v_mode } | |
357 | #define Ap { OP_DIR, 0 } | |
358 | #define Ob { OP_OFF64, b_mode } | |
359 | #define Ov { OP_OFF64, v_mode } | |
360 | #define Xb { OP_DSreg, eSI_reg } | |
361 | #define Xv { OP_DSreg, eSI_reg } | |
362 | #define Xz { OP_DSreg, eSI_reg } | |
363 | #define Yb { OP_ESreg, eDI_reg } | |
364 | #define Yv { OP_ESreg, eDI_reg } | |
365 | #define DSBX { OP_DSreg, eBX_reg } | |
366 | ||
367 | #define es { OP_REG, es_reg } | |
368 | #define ss { OP_REG, ss_reg } | |
369 | #define cs { OP_REG, cs_reg } | |
370 | #define ds { OP_REG, ds_reg } | |
371 | #define fs { OP_REG, fs_reg } | |
372 | #define gs { OP_REG, gs_reg } | |
373 | ||
374 | #define MX { OP_MMX, 0 } | |
375 | #define XM { OP_XMM, 0 } | |
539f890d | 376 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 377 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 378 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 379 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 380 | #define EM { OP_EM, v_mode } |
b6169b20 | 381 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 382 | #define EMd { OP_EM, d_mode } |
14051056 | 383 | #define EMx { OP_EM, x_mode } |
53467f57 | 384 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 385 | #define EXw { OP_EX, w_mode } |
53467f57 | 386 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 387 | #define EXd { OP_EX, d_mode } |
539f890d | 388 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 389 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 390 | #define EXq { OP_EX, q_mode } |
539f890d L |
391 | #define EXqScalar { OP_EX, q_scalar_mode } |
392 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 393 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 394 | #define EXx { OP_EX, x_mode } |
b6169b20 | 395 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 396 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 397 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 398 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 399 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
400 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
401 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
402 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
403 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 404 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
405 | #define EXxmmdw { OP_EX, xmmdw_mode } |
406 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 407 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 408 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 409 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
410 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
411 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
412 | #define MS { OP_MS, v_mode } |
413 | #define XS { OP_XS, v_mode } | |
09335d05 | 414 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 415 | #define MXC { OP_MXC, 0 } |
ce518a5f | 416 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 417 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 418 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 419 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 420 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
421 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
422 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 423 | |
c0f3af97 | 424 | #define Vex { OP_VEX, vex_mode } |
539f890d | 425 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 426 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
427 | #define Vex128 { OP_VEX, vex128_mode } |
428 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 429 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 430 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 431 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
432 | #define EXVexW { OP_EX_VexW, x_mode } |
433 | #define EXdVexW { OP_EX_VexW, d_mode } | |
434 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 435 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 436 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 437 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
438 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
439 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 440 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 441 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 442 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
443 | |
444 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 445 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
446 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
447 | ||
448 | #define XMask { OP_Mask, mask_mode } | |
449 | #define MaskG { OP_G, mask_mode } | |
450 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 451 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
452 | #define MaskR { OP_R, mask_mode } |
453 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 454 | |
6c30d220 | 455 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 456 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 457 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 458 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 459 | |
35c52694 | 460 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
461 | #define Xbr { REP_Fixup, eSI_reg } |
462 | #define Xvr { REP_Fixup, eSI_reg } | |
463 | #define Ybr { REP_Fixup, eDI_reg } | |
464 | #define Yvr { REP_Fixup, eDI_reg } | |
465 | #define Yzr { REP_Fixup, eDI_reg } | |
466 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
467 | #define ALr { REP_Fixup, al_reg } | |
468 | #define eAXr { REP_Fixup, eAX_reg } | |
469 | ||
42164a71 L |
470 | /* Used handle HLE prefix for lockable instructions. */ |
471 | #define Ebh1 { HLE_Fixup1, b_mode } | |
472 | #define Evh1 { HLE_Fixup1, v_mode } | |
473 | #define Ebh2 { HLE_Fixup2, b_mode } | |
474 | #define Evh2 { HLE_Fixup2, v_mode } | |
475 | #define Ebh3 { HLE_Fixup3, b_mode } | |
476 | #define Evh3 { HLE_Fixup3, v_mode } | |
477 | ||
7e8b059b | 478 | #define BND { BND_Fixup, 0 } |
04ef582a | 479 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 480 | |
ce518a5f L |
481 | #define cond_jump_flag { NULL, cond_jump_mode } |
482 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 483 | |
252b5132 | 484 | /* bits in sizeflag */ |
252b5132 | 485 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
486 | #define AFLAG 2 |
487 | #define DFLAG 1 | |
488 | ||
51e7da1b L |
489 | enum |
490 | { | |
491 | /* byte operand */ | |
492 | b_mode = 1, | |
493 | /* byte operand with operand swapped */ | |
3873ba12 | 494 | b_swap_mode, |
e3949f17 L |
495 | /* byte operand, sign extend like 'T' suffix */ |
496 | b_T_mode, | |
51e7da1b | 497 | /* operand size depends on prefixes */ |
3873ba12 | 498 | v_mode, |
51e7da1b | 499 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 500 | v_swap_mode, |
de89d0a3 IT |
501 | /* operand size depends on address prefix */ |
502 | va_mode, | |
51e7da1b | 503 | /* word operand */ |
3873ba12 | 504 | w_mode, |
51e7da1b | 505 | /* double word operand */ |
3873ba12 | 506 | d_mode, |
51e7da1b | 507 | /* double word operand with operand swapped */ |
3873ba12 | 508 | d_swap_mode, |
51e7da1b | 509 | /* quad word operand */ |
3873ba12 | 510 | q_mode, |
51e7da1b | 511 | /* quad word operand with operand swapped */ |
3873ba12 | 512 | q_swap_mode, |
51e7da1b | 513 | /* ten-byte operand */ |
3873ba12 | 514 | t_mode, |
43234a1e L |
515 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
516 | broadcast enabled. */ | |
3873ba12 | 517 | x_mode, |
43234a1e L |
518 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
519 | evex_x_gscat_mode, | |
520 | /* Similar to x_mode, but with disabled broadcast. */ | |
521 | evex_x_nobcst_mode, | |
522 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
523 | in EVEX. */ | |
3873ba12 | 524 | x_swap_mode, |
51e7da1b | 525 | /* 16-byte XMM operand */ |
3873ba12 | 526 | xmm_mode, |
43234a1e L |
527 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
528 | memory operand (depending on vector length). Broadcast isn't | |
529 | allowed. */ | |
3873ba12 | 530 | xmmq_mode, |
43234a1e L |
531 | /* Same as xmmq_mode, but broadcast is allowed. */ |
532 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
533 | /* XMM register or byte memory operand */ |
534 | xmm_mb_mode, | |
535 | /* XMM register or word memory operand */ | |
536 | xmm_mw_mode, | |
537 | /* XMM register or double word memory operand */ | |
538 | xmm_md_mode, | |
539 | /* XMM register or quad word memory operand */ | |
540 | xmm_mq_mode, | |
43234a1e L |
541 | /* XMM register or double/quad word memory operand, depending on |
542 | VEX.W. */ | |
543 | xmm_mdq_mode, | |
544 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 545 | xmmdw_mode, |
43234a1e | 546 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 547 | xmmqd_mode, |
43234a1e L |
548 | /* 32-byte YMM operand */ |
549 | ymm_mode, | |
550 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 551 | ymmq_mode, |
6c30d220 L |
552 | /* 32-byte YMM or 16-byte word operand */ |
553 | ymmxmm_mode, | |
51e7da1b | 554 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 555 | m_mode, |
51e7da1b | 556 | /* pair of v_mode operands */ |
3873ba12 L |
557 | a_mode, |
558 | cond_jump_mode, | |
559 | loop_jcxz_mode, | |
bc31405e | 560 | movsxd_mode, |
7e8b059b | 561 | v_bnd_mode, |
d276ec69 JB |
562 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
563 | v_bndmk_mode, | |
51e7da1b | 564 | /* operand size depends on REX prefixes. */ |
3873ba12 | 565 | dq_mode, |
376cd056 JB |
566 | /* registers like dq_mode, memory like w_mode, displacements like |
567 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 568 | dqw_mode, |
9f79e886 | 569 | /* bounds operand */ |
7e8b059b | 570 | bnd_mode, |
9f79e886 JB |
571 | /* bounds operand with operand swapped */ |
572 | bnd_swap_mode, | |
51e7da1b | 573 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
574 | f_mode, |
575 | const_1_mode, | |
07f5af7d L |
576 | /* v_mode for indirect branch opcodes. */ |
577 | indir_v_mode, | |
51e7da1b | 578 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 579 | stack_v_mode, |
51e7da1b | 580 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 581 | z_mode, |
51e7da1b | 582 | /* 16-byte operand */ |
3873ba12 | 583 | o_mode, |
51e7da1b | 584 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 585 | dqb_mode, |
1ba585e8 IT |
586 | /* registers like d_mode, memory like b_mode. */ |
587 | db_mode, | |
588 | /* registers like d_mode, memory like w_mode. */ | |
589 | dw_mode, | |
51e7da1b | 590 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 591 | dqd_mode, |
51e7da1b | 592 | /* normal vex mode */ |
3873ba12 | 593 | vex_mode, |
51e7da1b | 594 | /* 128bit vex mode */ |
3873ba12 | 595 | vex128_mode, |
51e7da1b | 596 | /* 256bit vex mode */ |
3873ba12 | 597 | vex256_mode, |
51e7da1b | 598 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 599 | vex_w_dq_mode, |
d55ee72f | 600 | |
6c30d220 L |
601 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
602 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
603 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
604 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
605 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
606 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
607 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
608 | vex_vsib_q_w_d_mode, | |
6c30d220 | 609 | |
539f890d L |
610 | /* scalar, ignore vector length. */ |
611 | scalar_mode, | |
53467f57 IT |
612 | /* like b_mode, ignore vector length. */ |
613 | b_scalar_mode, | |
614 | /* like w_mode, ignore vector length. */ | |
615 | w_scalar_mode, | |
539f890d L |
616 | /* like d_mode, ignore vector length. */ |
617 | d_scalar_mode, | |
618 | /* like d_swap_mode, ignore vector length. */ | |
619 | d_scalar_swap_mode, | |
620 | /* like q_mode, ignore vector length. */ | |
621 | q_scalar_mode, | |
622 | /* like q_swap_mode, ignore vector length. */ | |
623 | q_scalar_swap_mode, | |
624 | /* like vex_mode, ignore vector length. */ | |
625 | vex_scalar_mode, | |
1c480963 L |
626 | /* like vex_w_dq_mode, ignore vector length. */ |
627 | vex_scalar_w_dq_mode, | |
539f890d | 628 | |
43234a1e L |
629 | /* Static rounding. */ |
630 | evex_rounding_mode, | |
70df6fc9 L |
631 | /* Static rounding, 64-bit mode only. */ |
632 | evex_rounding_64_mode, | |
43234a1e L |
633 | /* Supress all exceptions. */ |
634 | evex_sae_mode, | |
635 | ||
636 | /* Mask register operand. */ | |
637 | mask_mode, | |
1ba585e8 IT |
638 | /* Mask register operand. */ |
639 | mask_bd_mode, | |
43234a1e | 640 | |
3873ba12 L |
641 | es_reg, |
642 | cs_reg, | |
643 | ss_reg, | |
644 | ds_reg, | |
645 | fs_reg, | |
646 | gs_reg, | |
d55ee72f | 647 | |
3873ba12 L |
648 | eAX_reg, |
649 | eCX_reg, | |
650 | eDX_reg, | |
651 | eBX_reg, | |
652 | eSP_reg, | |
653 | eBP_reg, | |
654 | eSI_reg, | |
655 | eDI_reg, | |
d55ee72f | 656 | |
3873ba12 L |
657 | al_reg, |
658 | cl_reg, | |
659 | dl_reg, | |
660 | bl_reg, | |
661 | ah_reg, | |
662 | ch_reg, | |
663 | dh_reg, | |
664 | bh_reg, | |
d55ee72f | 665 | |
3873ba12 L |
666 | ax_reg, |
667 | cx_reg, | |
668 | dx_reg, | |
669 | bx_reg, | |
670 | sp_reg, | |
671 | bp_reg, | |
672 | si_reg, | |
673 | di_reg, | |
d55ee72f | 674 | |
3873ba12 L |
675 | rAX_reg, |
676 | rCX_reg, | |
677 | rDX_reg, | |
678 | rBX_reg, | |
679 | rSP_reg, | |
680 | rBP_reg, | |
681 | rSI_reg, | |
682 | rDI_reg, | |
d55ee72f | 683 | |
3873ba12 L |
684 | z_mode_ax_reg, |
685 | indir_dx_reg | |
51e7da1b | 686 | }; |
252b5132 | 687 | |
51e7da1b L |
688 | enum |
689 | { | |
690 | FLOATCODE = 1, | |
3873ba12 L |
691 | USE_REG_TABLE, |
692 | USE_MOD_TABLE, | |
693 | USE_RM_TABLE, | |
694 | USE_PREFIX_TABLE, | |
695 | USE_X86_64_TABLE, | |
696 | USE_3BYTE_TABLE, | |
f88c9eb0 | 697 | USE_XOP_8F_TABLE, |
3873ba12 L |
698 | USE_VEX_C4_TABLE, |
699 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 700 | USE_VEX_LEN_TABLE, |
43234a1e | 701 | USE_VEX_W_TABLE, |
04e2a182 L |
702 | USE_EVEX_TABLE, |
703 | USE_EVEX_LEN_TABLE | |
51e7da1b | 704 | }; |
6439fc28 | 705 | |
bf890a93 | 706 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 707 | |
bf890a93 IT |
708 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
709 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
710 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
711 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
712 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
713 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
714 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
715 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 716 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 717 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
718 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
719 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
720 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 721 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 722 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 723 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 724 | |
51e7da1b L |
725 | enum |
726 | { | |
727 | REG_80 = 0, | |
3873ba12 | 728 | REG_81, |
7148c369 | 729 | REG_83, |
3873ba12 L |
730 | REG_8F, |
731 | REG_C0, | |
732 | REG_C1, | |
733 | REG_C6, | |
734 | REG_C7, | |
735 | REG_D0, | |
736 | REG_D1, | |
737 | REG_D2, | |
738 | REG_D3, | |
739 | REG_F6, | |
740 | REG_F7, | |
741 | REG_FE, | |
742 | REG_FF, | |
743 | REG_0F00, | |
744 | REG_0F01, | |
745 | REG_0F0D, | |
746 | REG_0F18, | |
f8687e93 JB |
747 | REG_0F1C_P_0_MOD_0, |
748 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
749 | REG_0F71, |
750 | REG_0F72, | |
751 | REG_0F73, | |
752 | REG_0FA6, | |
753 | REG_0FA7, | |
754 | REG_0FAE, | |
755 | REG_0FBA, | |
756 | REG_0FC7, | |
592a252b L |
757 | REG_VEX_0F71, |
758 | REG_VEX_0F72, | |
759 | REG_VEX_0F73, | |
760 | REG_VEX_0FAE, | |
f12dc422 | 761 | REG_VEX_0F38F3, |
f88c9eb0 | 762 | REG_XOP_LWPCB, |
2a2a0f38 QN |
763 | REG_XOP_LWP, |
764 | REG_XOP_TBM_01, | |
43234a1e L |
765 | REG_XOP_TBM_02, |
766 | ||
1ba585e8 | 767 | REG_EVEX_0F71, |
43234a1e L |
768 | REG_EVEX_0F72, |
769 | REG_EVEX_0F73, | |
770 | REG_EVEX_0F38C6, | |
771 | REG_EVEX_0F38C7 | |
51e7da1b | 772 | }; |
1ceb70f8 | 773 | |
51e7da1b L |
774 | enum |
775 | { | |
776 | MOD_8D = 0, | |
42164a71 L |
777 | MOD_C6_REG_7, |
778 | MOD_C7_REG_7, | |
4a357820 MZ |
779 | MOD_FF_REG_3, |
780 | MOD_FF_REG_5, | |
3873ba12 L |
781 | MOD_0F01_REG_0, |
782 | MOD_0F01_REG_1, | |
783 | MOD_0F01_REG_2, | |
784 | MOD_0F01_REG_3, | |
8eab4136 | 785 | MOD_0F01_REG_5, |
3873ba12 L |
786 | MOD_0F01_REG_7, |
787 | MOD_0F12_PREFIX_0, | |
788 | MOD_0F13, | |
789 | MOD_0F16_PREFIX_0, | |
790 | MOD_0F17, | |
791 | MOD_0F18_REG_0, | |
792 | MOD_0F18_REG_1, | |
793 | MOD_0F18_REG_2, | |
794 | MOD_0F18_REG_3, | |
d7189fa5 RM |
795 | MOD_0F18_REG_4, |
796 | MOD_0F18_REG_5, | |
797 | MOD_0F18_REG_6, | |
798 | MOD_0F18_REG_7, | |
7e8b059b L |
799 | MOD_0F1A_PREFIX_0, |
800 | MOD_0F1B_PREFIX_0, | |
801 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 802 | MOD_0F1C_PREFIX_0, |
603555e5 | 803 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
804 | MOD_0F24, |
805 | MOD_0F26, | |
806 | MOD_0F2B_PREFIX_0, | |
807 | MOD_0F2B_PREFIX_1, | |
808 | MOD_0F2B_PREFIX_2, | |
809 | MOD_0F2B_PREFIX_3, | |
810 | MOD_0F51, | |
811 | MOD_0F71_REG_2, | |
812 | MOD_0F71_REG_4, | |
813 | MOD_0F71_REG_6, | |
814 | MOD_0F72_REG_2, | |
815 | MOD_0F72_REG_4, | |
816 | MOD_0F72_REG_6, | |
817 | MOD_0F73_REG_2, | |
818 | MOD_0F73_REG_3, | |
819 | MOD_0F73_REG_6, | |
820 | MOD_0F73_REG_7, | |
821 | MOD_0FAE_REG_0, | |
822 | MOD_0FAE_REG_1, | |
823 | MOD_0FAE_REG_2, | |
824 | MOD_0FAE_REG_3, | |
825 | MOD_0FAE_REG_4, | |
826 | MOD_0FAE_REG_5, | |
827 | MOD_0FAE_REG_6, | |
828 | MOD_0FAE_REG_7, | |
829 | MOD_0FB2, | |
830 | MOD_0FB4, | |
831 | MOD_0FB5, | |
a8484f96 | 832 | MOD_0FC3, |
963f3586 IT |
833 | MOD_0FC7_REG_3, |
834 | MOD_0FC7_REG_4, | |
835 | MOD_0FC7_REG_5, | |
3873ba12 L |
836 | MOD_0FC7_REG_6, |
837 | MOD_0FC7_REG_7, | |
838 | MOD_0FD7, | |
839 | MOD_0FE7_PREFIX_2, | |
840 | MOD_0FF0_PREFIX_3, | |
841 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
842 | MOD_0F38F5_PREFIX_2, |
843 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 844 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 845 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 846 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 847 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
848 | MOD_62_32BIT, |
849 | MOD_C4_32BIT, | |
850 | MOD_C5_32BIT, | |
592a252b L |
851 | MOD_VEX_0F12_PREFIX_0, |
852 | MOD_VEX_0F13, | |
853 | MOD_VEX_0F16_PREFIX_0, | |
854 | MOD_VEX_0F17, | |
855 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
856 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
857 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
858 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
859 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
860 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
861 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
862 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
863 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
864 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
865 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
866 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
867 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
868 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
869 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
870 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
871 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
872 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
873 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
874 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
875 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
876 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
877 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
878 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
879 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
880 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
881 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
882 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
883 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
884 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
885 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
886 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
887 | MOD_VEX_0F50, |
888 | MOD_VEX_0F71_REG_2, | |
889 | MOD_VEX_0F71_REG_4, | |
890 | MOD_VEX_0F71_REG_6, | |
891 | MOD_VEX_0F72_REG_2, | |
892 | MOD_VEX_0F72_REG_4, | |
893 | MOD_VEX_0F72_REG_6, | |
894 | MOD_VEX_0F73_REG_2, | |
895 | MOD_VEX_0F73_REG_3, | |
896 | MOD_VEX_0F73_REG_6, | |
897 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
898 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
899 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
900 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
901 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
902 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
903 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 904 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
905 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
906 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 907 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
908 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
909 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
910 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
911 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
912 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
913 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
914 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
915 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
916 | MOD_VEX_0FAE_REG_2, |
917 | MOD_VEX_0FAE_REG_3, | |
918 | MOD_VEX_0FD7_PREFIX_2, | |
919 | MOD_VEX_0FE7_PREFIX_2, | |
920 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
921 | MOD_VEX_0F381A_PREFIX_2, |
922 | MOD_VEX_0F382A_PREFIX_2, | |
923 | MOD_VEX_0F382C_PREFIX_2, | |
924 | MOD_VEX_0F382D_PREFIX_2, | |
925 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
926 | MOD_VEX_0F382F_PREFIX_2, |
927 | MOD_VEX_0F385A_PREFIX_2, | |
928 | MOD_VEX_0F388C_PREFIX_2, | |
929 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
930 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
931 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
932 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
933 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
934 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
935 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
936 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
937 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 938 | |
43234a1e L |
939 | MOD_EVEX_0F12_PREFIX_0, |
940 | MOD_EVEX_0F16_PREFIX_0, | |
941 | MOD_EVEX_0F38C6_REG_1, | |
942 | MOD_EVEX_0F38C6_REG_2, | |
943 | MOD_EVEX_0F38C6_REG_5, | |
944 | MOD_EVEX_0F38C6_REG_6, | |
945 | MOD_EVEX_0F38C7_REG_1, | |
946 | MOD_EVEX_0F38C7_REG_2, | |
947 | MOD_EVEX_0F38C7_REG_5, | |
948 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 949 | }; |
1ceb70f8 | 950 | |
51e7da1b L |
951 | enum |
952 | { | |
42164a71 L |
953 | RM_C6_REG_7 = 0, |
954 | RM_C7_REG_7, | |
955 | RM_0F01_REG_0, | |
3873ba12 L |
956 | RM_0F01_REG_1, |
957 | RM_0F01_REG_2, | |
958 | RM_0F01_REG_3, | |
f8687e93 JB |
959 | RM_0F01_REG_5_MOD_3, |
960 | RM_0F01_REG_7_MOD_3, | |
961 | RM_0F1E_P_1_MOD_3_REG_7, | |
962 | RM_0FAE_REG_6_MOD_3_P_0, | |
963 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 964 | }; |
1ceb70f8 | 965 | |
51e7da1b L |
966 | enum |
967 | { | |
968 | PREFIX_90 = 0, | |
f8687e93 JB |
969 | PREFIX_0F01_REG_5_MOD_0, |
970 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
971 | PREFIX_0F01_REG_5_MOD_3_RM_2, | |
267b8516 JB |
972 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
973 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 974 | PREFIX_0F09, |
3873ba12 L |
975 | PREFIX_0F10, |
976 | PREFIX_0F11, | |
977 | PREFIX_0F12, | |
978 | PREFIX_0F16, | |
7e8b059b L |
979 | PREFIX_0F1A, |
980 | PREFIX_0F1B, | |
c48935d7 | 981 | PREFIX_0F1C, |
603555e5 | 982 | PREFIX_0F1E, |
3873ba12 L |
983 | PREFIX_0F2A, |
984 | PREFIX_0F2B, | |
985 | PREFIX_0F2C, | |
986 | PREFIX_0F2D, | |
987 | PREFIX_0F2E, | |
988 | PREFIX_0F2F, | |
989 | PREFIX_0F51, | |
990 | PREFIX_0F52, | |
991 | PREFIX_0F53, | |
992 | PREFIX_0F58, | |
993 | PREFIX_0F59, | |
994 | PREFIX_0F5A, | |
995 | PREFIX_0F5B, | |
996 | PREFIX_0F5C, | |
997 | PREFIX_0F5D, | |
998 | PREFIX_0F5E, | |
999 | PREFIX_0F5F, | |
1000 | PREFIX_0F60, | |
1001 | PREFIX_0F61, | |
1002 | PREFIX_0F62, | |
1003 | PREFIX_0F6C, | |
1004 | PREFIX_0F6D, | |
1005 | PREFIX_0F6F, | |
1006 | PREFIX_0F70, | |
1007 | PREFIX_0F73_REG_3, | |
1008 | PREFIX_0F73_REG_7, | |
1009 | PREFIX_0F78, | |
1010 | PREFIX_0F79, | |
1011 | PREFIX_0F7C, | |
1012 | PREFIX_0F7D, | |
1013 | PREFIX_0F7E, | |
1014 | PREFIX_0F7F, | |
f8687e93 JB |
1015 | PREFIX_0FAE_REG_0_MOD_3, |
1016 | PREFIX_0FAE_REG_1_MOD_3, | |
1017 | PREFIX_0FAE_REG_2_MOD_3, | |
1018 | PREFIX_0FAE_REG_3_MOD_3, | |
1019 | PREFIX_0FAE_REG_4_MOD_0, | |
1020 | PREFIX_0FAE_REG_4_MOD_3, | |
1021 | PREFIX_0FAE_REG_5_MOD_0, | |
1022 | PREFIX_0FAE_REG_5_MOD_3, | |
1023 | PREFIX_0FAE_REG_6_MOD_0, | |
1024 | PREFIX_0FAE_REG_6_MOD_3, | |
1025 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1026 | PREFIX_0FB8, |
f12dc422 | 1027 | PREFIX_0FBC, |
3873ba12 L |
1028 | PREFIX_0FBD, |
1029 | PREFIX_0FC2, | |
f8687e93 JB |
1030 | PREFIX_0FC3_MOD_0, |
1031 | PREFIX_0FC7_REG_6_MOD_0, | |
1032 | PREFIX_0FC7_REG_6_MOD_3, | |
1033 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1034 | PREFIX_0FD0, |
1035 | PREFIX_0FD6, | |
1036 | PREFIX_0FE6, | |
1037 | PREFIX_0FE7, | |
1038 | PREFIX_0FF0, | |
1039 | PREFIX_0FF7, | |
1040 | PREFIX_0F3810, | |
1041 | PREFIX_0F3814, | |
1042 | PREFIX_0F3815, | |
1043 | PREFIX_0F3817, | |
1044 | PREFIX_0F3820, | |
1045 | PREFIX_0F3821, | |
1046 | PREFIX_0F3822, | |
1047 | PREFIX_0F3823, | |
1048 | PREFIX_0F3824, | |
1049 | PREFIX_0F3825, | |
1050 | PREFIX_0F3828, | |
1051 | PREFIX_0F3829, | |
1052 | PREFIX_0F382A, | |
1053 | PREFIX_0F382B, | |
1054 | PREFIX_0F3830, | |
1055 | PREFIX_0F3831, | |
1056 | PREFIX_0F3832, | |
1057 | PREFIX_0F3833, | |
1058 | PREFIX_0F3834, | |
1059 | PREFIX_0F3835, | |
1060 | PREFIX_0F3837, | |
1061 | PREFIX_0F3838, | |
1062 | PREFIX_0F3839, | |
1063 | PREFIX_0F383A, | |
1064 | PREFIX_0F383B, | |
1065 | PREFIX_0F383C, | |
1066 | PREFIX_0F383D, | |
1067 | PREFIX_0F383E, | |
1068 | PREFIX_0F383F, | |
1069 | PREFIX_0F3840, | |
1070 | PREFIX_0F3841, | |
1071 | PREFIX_0F3880, | |
1072 | PREFIX_0F3881, | |
6c30d220 | 1073 | PREFIX_0F3882, |
a0046408 L |
1074 | PREFIX_0F38C8, |
1075 | PREFIX_0F38C9, | |
1076 | PREFIX_0F38CA, | |
1077 | PREFIX_0F38CB, | |
1078 | PREFIX_0F38CC, | |
1079 | PREFIX_0F38CD, | |
48521003 | 1080 | PREFIX_0F38CF, |
3873ba12 L |
1081 | PREFIX_0F38DB, |
1082 | PREFIX_0F38DC, | |
1083 | PREFIX_0F38DD, | |
1084 | PREFIX_0F38DE, | |
1085 | PREFIX_0F38DF, | |
1086 | PREFIX_0F38F0, | |
1087 | PREFIX_0F38F1, | |
603555e5 | 1088 | PREFIX_0F38F5, |
e2e1fcde | 1089 | PREFIX_0F38F6, |
c0a30a9f L |
1090 | PREFIX_0F38F8, |
1091 | PREFIX_0F38F9, | |
3873ba12 L |
1092 | PREFIX_0F3A08, |
1093 | PREFIX_0F3A09, | |
1094 | PREFIX_0F3A0A, | |
1095 | PREFIX_0F3A0B, | |
1096 | PREFIX_0F3A0C, | |
1097 | PREFIX_0F3A0D, | |
1098 | PREFIX_0F3A0E, | |
1099 | PREFIX_0F3A14, | |
1100 | PREFIX_0F3A15, | |
1101 | PREFIX_0F3A16, | |
1102 | PREFIX_0F3A17, | |
1103 | PREFIX_0F3A20, | |
1104 | PREFIX_0F3A21, | |
1105 | PREFIX_0F3A22, | |
1106 | PREFIX_0F3A40, | |
1107 | PREFIX_0F3A41, | |
1108 | PREFIX_0F3A42, | |
1109 | PREFIX_0F3A44, | |
1110 | PREFIX_0F3A60, | |
1111 | PREFIX_0F3A61, | |
1112 | PREFIX_0F3A62, | |
1113 | PREFIX_0F3A63, | |
a0046408 | 1114 | PREFIX_0F3ACC, |
48521003 IT |
1115 | PREFIX_0F3ACE, |
1116 | PREFIX_0F3ACF, | |
3873ba12 | 1117 | PREFIX_0F3ADF, |
592a252b L |
1118 | PREFIX_VEX_0F10, |
1119 | PREFIX_VEX_0F11, | |
1120 | PREFIX_VEX_0F12, | |
1121 | PREFIX_VEX_0F16, | |
1122 | PREFIX_VEX_0F2A, | |
1123 | PREFIX_VEX_0F2C, | |
1124 | PREFIX_VEX_0F2D, | |
1125 | PREFIX_VEX_0F2E, | |
1126 | PREFIX_VEX_0F2F, | |
43234a1e L |
1127 | PREFIX_VEX_0F41, |
1128 | PREFIX_VEX_0F42, | |
1129 | PREFIX_VEX_0F44, | |
1130 | PREFIX_VEX_0F45, | |
1131 | PREFIX_VEX_0F46, | |
1132 | PREFIX_VEX_0F47, | |
1ba585e8 | 1133 | PREFIX_VEX_0F4A, |
43234a1e | 1134 | PREFIX_VEX_0F4B, |
592a252b L |
1135 | PREFIX_VEX_0F51, |
1136 | PREFIX_VEX_0F52, | |
1137 | PREFIX_VEX_0F53, | |
1138 | PREFIX_VEX_0F58, | |
1139 | PREFIX_VEX_0F59, | |
1140 | PREFIX_VEX_0F5A, | |
1141 | PREFIX_VEX_0F5B, | |
1142 | PREFIX_VEX_0F5C, | |
1143 | PREFIX_VEX_0F5D, | |
1144 | PREFIX_VEX_0F5E, | |
1145 | PREFIX_VEX_0F5F, | |
1146 | PREFIX_VEX_0F60, | |
1147 | PREFIX_VEX_0F61, | |
1148 | PREFIX_VEX_0F62, | |
1149 | PREFIX_VEX_0F63, | |
1150 | PREFIX_VEX_0F64, | |
1151 | PREFIX_VEX_0F65, | |
1152 | PREFIX_VEX_0F66, | |
1153 | PREFIX_VEX_0F67, | |
1154 | PREFIX_VEX_0F68, | |
1155 | PREFIX_VEX_0F69, | |
1156 | PREFIX_VEX_0F6A, | |
1157 | PREFIX_VEX_0F6B, | |
1158 | PREFIX_VEX_0F6C, | |
1159 | PREFIX_VEX_0F6D, | |
1160 | PREFIX_VEX_0F6E, | |
1161 | PREFIX_VEX_0F6F, | |
1162 | PREFIX_VEX_0F70, | |
1163 | PREFIX_VEX_0F71_REG_2, | |
1164 | PREFIX_VEX_0F71_REG_4, | |
1165 | PREFIX_VEX_0F71_REG_6, | |
1166 | PREFIX_VEX_0F72_REG_2, | |
1167 | PREFIX_VEX_0F72_REG_4, | |
1168 | PREFIX_VEX_0F72_REG_6, | |
1169 | PREFIX_VEX_0F73_REG_2, | |
1170 | PREFIX_VEX_0F73_REG_3, | |
1171 | PREFIX_VEX_0F73_REG_6, | |
1172 | PREFIX_VEX_0F73_REG_7, | |
1173 | PREFIX_VEX_0F74, | |
1174 | PREFIX_VEX_0F75, | |
1175 | PREFIX_VEX_0F76, | |
1176 | PREFIX_VEX_0F77, | |
1177 | PREFIX_VEX_0F7C, | |
1178 | PREFIX_VEX_0F7D, | |
1179 | PREFIX_VEX_0F7E, | |
1180 | PREFIX_VEX_0F7F, | |
43234a1e L |
1181 | PREFIX_VEX_0F90, |
1182 | PREFIX_VEX_0F91, | |
1183 | PREFIX_VEX_0F92, | |
1184 | PREFIX_VEX_0F93, | |
1185 | PREFIX_VEX_0F98, | |
1ba585e8 | 1186 | PREFIX_VEX_0F99, |
592a252b L |
1187 | PREFIX_VEX_0FC2, |
1188 | PREFIX_VEX_0FC4, | |
1189 | PREFIX_VEX_0FC5, | |
1190 | PREFIX_VEX_0FD0, | |
1191 | PREFIX_VEX_0FD1, | |
1192 | PREFIX_VEX_0FD2, | |
1193 | PREFIX_VEX_0FD3, | |
1194 | PREFIX_VEX_0FD4, | |
1195 | PREFIX_VEX_0FD5, | |
1196 | PREFIX_VEX_0FD6, | |
1197 | PREFIX_VEX_0FD7, | |
1198 | PREFIX_VEX_0FD8, | |
1199 | PREFIX_VEX_0FD9, | |
1200 | PREFIX_VEX_0FDA, | |
1201 | PREFIX_VEX_0FDB, | |
1202 | PREFIX_VEX_0FDC, | |
1203 | PREFIX_VEX_0FDD, | |
1204 | PREFIX_VEX_0FDE, | |
1205 | PREFIX_VEX_0FDF, | |
1206 | PREFIX_VEX_0FE0, | |
1207 | PREFIX_VEX_0FE1, | |
1208 | PREFIX_VEX_0FE2, | |
1209 | PREFIX_VEX_0FE3, | |
1210 | PREFIX_VEX_0FE4, | |
1211 | PREFIX_VEX_0FE5, | |
1212 | PREFIX_VEX_0FE6, | |
1213 | PREFIX_VEX_0FE7, | |
1214 | PREFIX_VEX_0FE8, | |
1215 | PREFIX_VEX_0FE9, | |
1216 | PREFIX_VEX_0FEA, | |
1217 | PREFIX_VEX_0FEB, | |
1218 | PREFIX_VEX_0FEC, | |
1219 | PREFIX_VEX_0FED, | |
1220 | PREFIX_VEX_0FEE, | |
1221 | PREFIX_VEX_0FEF, | |
1222 | PREFIX_VEX_0FF0, | |
1223 | PREFIX_VEX_0FF1, | |
1224 | PREFIX_VEX_0FF2, | |
1225 | PREFIX_VEX_0FF3, | |
1226 | PREFIX_VEX_0FF4, | |
1227 | PREFIX_VEX_0FF5, | |
1228 | PREFIX_VEX_0FF6, | |
1229 | PREFIX_VEX_0FF7, | |
1230 | PREFIX_VEX_0FF8, | |
1231 | PREFIX_VEX_0FF9, | |
1232 | PREFIX_VEX_0FFA, | |
1233 | PREFIX_VEX_0FFB, | |
1234 | PREFIX_VEX_0FFC, | |
1235 | PREFIX_VEX_0FFD, | |
1236 | PREFIX_VEX_0FFE, | |
1237 | PREFIX_VEX_0F3800, | |
1238 | PREFIX_VEX_0F3801, | |
1239 | PREFIX_VEX_0F3802, | |
1240 | PREFIX_VEX_0F3803, | |
1241 | PREFIX_VEX_0F3804, | |
1242 | PREFIX_VEX_0F3805, | |
1243 | PREFIX_VEX_0F3806, | |
1244 | PREFIX_VEX_0F3807, | |
1245 | PREFIX_VEX_0F3808, | |
1246 | PREFIX_VEX_0F3809, | |
1247 | PREFIX_VEX_0F380A, | |
1248 | PREFIX_VEX_0F380B, | |
1249 | PREFIX_VEX_0F380C, | |
1250 | PREFIX_VEX_0F380D, | |
1251 | PREFIX_VEX_0F380E, | |
1252 | PREFIX_VEX_0F380F, | |
1253 | PREFIX_VEX_0F3813, | |
6c30d220 | 1254 | PREFIX_VEX_0F3816, |
592a252b L |
1255 | PREFIX_VEX_0F3817, |
1256 | PREFIX_VEX_0F3818, | |
1257 | PREFIX_VEX_0F3819, | |
1258 | PREFIX_VEX_0F381A, | |
1259 | PREFIX_VEX_0F381C, | |
1260 | PREFIX_VEX_0F381D, | |
1261 | PREFIX_VEX_0F381E, | |
1262 | PREFIX_VEX_0F3820, | |
1263 | PREFIX_VEX_0F3821, | |
1264 | PREFIX_VEX_0F3822, | |
1265 | PREFIX_VEX_0F3823, | |
1266 | PREFIX_VEX_0F3824, | |
1267 | PREFIX_VEX_0F3825, | |
1268 | PREFIX_VEX_0F3828, | |
1269 | PREFIX_VEX_0F3829, | |
1270 | PREFIX_VEX_0F382A, | |
1271 | PREFIX_VEX_0F382B, | |
1272 | PREFIX_VEX_0F382C, | |
1273 | PREFIX_VEX_0F382D, | |
1274 | PREFIX_VEX_0F382E, | |
1275 | PREFIX_VEX_0F382F, | |
1276 | PREFIX_VEX_0F3830, | |
1277 | PREFIX_VEX_0F3831, | |
1278 | PREFIX_VEX_0F3832, | |
1279 | PREFIX_VEX_0F3833, | |
1280 | PREFIX_VEX_0F3834, | |
1281 | PREFIX_VEX_0F3835, | |
6c30d220 | 1282 | PREFIX_VEX_0F3836, |
592a252b L |
1283 | PREFIX_VEX_0F3837, |
1284 | PREFIX_VEX_0F3838, | |
1285 | PREFIX_VEX_0F3839, | |
1286 | PREFIX_VEX_0F383A, | |
1287 | PREFIX_VEX_0F383B, | |
1288 | PREFIX_VEX_0F383C, | |
1289 | PREFIX_VEX_0F383D, | |
1290 | PREFIX_VEX_0F383E, | |
1291 | PREFIX_VEX_0F383F, | |
1292 | PREFIX_VEX_0F3840, | |
1293 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1294 | PREFIX_VEX_0F3845, |
1295 | PREFIX_VEX_0F3846, | |
1296 | PREFIX_VEX_0F3847, | |
1297 | PREFIX_VEX_0F3858, | |
1298 | PREFIX_VEX_0F3859, | |
1299 | PREFIX_VEX_0F385A, | |
1300 | PREFIX_VEX_0F3878, | |
1301 | PREFIX_VEX_0F3879, | |
1302 | PREFIX_VEX_0F388C, | |
1303 | PREFIX_VEX_0F388E, | |
1304 | PREFIX_VEX_0F3890, | |
1305 | PREFIX_VEX_0F3891, | |
1306 | PREFIX_VEX_0F3892, | |
1307 | PREFIX_VEX_0F3893, | |
592a252b L |
1308 | PREFIX_VEX_0F3896, |
1309 | PREFIX_VEX_0F3897, | |
1310 | PREFIX_VEX_0F3898, | |
1311 | PREFIX_VEX_0F3899, | |
1312 | PREFIX_VEX_0F389A, | |
1313 | PREFIX_VEX_0F389B, | |
1314 | PREFIX_VEX_0F389C, | |
1315 | PREFIX_VEX_0F389D, | |
1316 | PREFIX_VEX_0F389E, | |
1317 | PREFIX_VEX_0F389F, | |
1318 | PREFIX_VEX_0F38A6, | |
1319 | PREFIX_VEX_0F38A7, | |
1320 | PREFIX_VEX_0F38A8, | |
1321 | PREFIX_VEX_0F38A9, | |
1322 | PREFIX_VEX_0F38AA, | |
1323 | PREFIX_VEX_0F38AB, | |
1324 | PREFIX_VEX_0F38AC, | |
1325 | PREFIX_VEX_0F38AD, | |
1326 | PREFIX_VEX_0F38AE, | |
1327 | PREFIX_VEX_0F38AF, | |
1328 | PREFIX_VEX_0F38B6, | |
1329 | PREFIX_VEX_0F38B7, | |
1330 | PREFIX_VEX_0F38B8, | |
1331 | PREFIX_VEX_0F38B9, | |
1332 | PREFIX_VEX_0F38BA, | |
1333 | PREFIX_VEX_0F38BB, | |
1334 | PREFIX_VEX_0F38BC, | |
1335 | PREFIX_VEX_0F38BD, | |
1336 | PREFIX_VEX_0F38BE, | |
1337 | PREFIX_VEX_0F38BF, | |
48521003 | 1338 | PREFIX_VEX_0F38CF, |
592a252b L |
1339 | PREFIX_VEX_0F38DB, |
1340 | PREFIX_VEX_0F38DC, | |
1341 | PREFIX_VEX_0F38DD, | |
1342 | PREFIX_VEX_0F38DE, | |
1343 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1344 | PREFIX_VEX_0F38F2, |
1345 | PREFIX_VEX_0F38F3_REG_1, | |
1346 | PREFIX_VEX_0F38F3_REG_2, | |
1347 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1348 | PREFIX_VEX_0F38F5, |
1349 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1350 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1351 | PREFIX_VEX_0F3A00, |
1352 | PREFIX_VEX_0F3A01, | |
1353 | PREFIX_VEX_0F3A02, | |
592a252b L |
1354 | PREFIX_VEX_0F3A04, |
1355 | PREFIX_VEX_0F3A05, | |
1356 | PREFIX_VEX_0F3A06, | |
1357 | PREFIX_VEX_0F3A08, | |
1358 | PREFIX_VEX_0F3A09, | |
1359 | PREFIX_VEX_0F3A0A, | |
1360 | PREFIX_VEX_0F3A0B, | |
1361 | PREFIX_VEX_0F3A0C, | |
1362 | PREFIX_VEX_0F3A0D, | |
1363 | PREFIX_VEX_0F3A0E, | |
1364 | PREFIX_VEX_0F3A0F, | |
1365 | PREFIX_VEX_0F3A14, | |
1366 | PREFIX_VEX_0F3A15, | |
1367 | PREFIX_VEX_0F3A16, | |
1368 | PREFIX_VEX_0F3A17, | |
1369 | PREFIX_VEX_0F3A18, | |
1370 | PREFIX_VEX_0F3A19, | |
1371 | PREFIX_VEX_0F3A1D, | |
1372 | PREFIX_VEX_0F3A20, | |
1373 | PREFIX_VEX_0F3A21, | |
1374 | PREFIX_VEX_0F3A22, | |
43234a1e | 1375 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1376 | PREFIX_VEX_0F3A31, |
43234a1e | 1377 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1378 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1379 | PREFIX_VEX_0F3A38, |
1380 | PREFIX_VEX_0F3A39, | |
592a252b L |
1381 | PREFIX_VEX_0F3A40, |
1382 | PREFIX_VEX_0F3A41, | |
1383 | PREFIX_VEX_0F3A42, | |
1384 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1385 | PREFIX_VEX_0F3A46, |
592a252b L |
1386 | PREFIX_VEX_0F3A48, |
1387 | PREFIX_VEX_0F3A49, | |
1388 | PREFIX_VEX_0F3A4A, | |
1389 | PREFIX_VEX_0F3A4B, | |
1390 | PREFIX_VEX_0F3A4C, | |
1391 | PREFIX_VEX_0F3A5C, | |
1392 | PREFIX_VEX_0F3A5D, | |
1393 | PREFIX_VEX_0F3A5E, | |
1394 | PREFIX_VEX_0F3A5F, | |
1395 | PREFIX_VEX_0F3A60, | |
1396 | PREFIX_VEX_0F3A61, | |
1397 | PREFIX_VEX_0F3A62, | |
1398 | PREFIX_VEX_0F3A63, | |
1399 | PREFIX_VEX_0F3A68, | |
1400 | PREFIX_VEX_0F3A69, | |
1401 | PREFIX_VEX_0F3A6A, | |
1402 | PREFIX_VEX_0F3A6B, | |
1403 | PREFIX_VEX_0F3A6C, | |
1404 | PREFIX_VEX_0F3A6D, | |
1405 | PREFIX_VEX_0F3A6E, | |
1406 | PREFIX_VEX_0F3A6F, | |
1407 | PREFIX_VEX_0F3A78, | |
1408 | PREFIX_VEX_0F3A79, | |
1409 | PREFIX_VEX_0F3A7A, | |
1410 | PREFIX_VEX_0F3A7B, | |
1411 | PREFIX_VEX_0F3A7C, | |
1412 | PREFIX_VEX_0F3A7D, | |
1413 | PREFIX_VEX_0F3A7E, | |
1414 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1415 | PREFIX_VEX_0F3ACE, |
1416 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1417 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1418 | PREFIX_VEX_0F3AF0, |
1419 | ||
1420 | PREFIX_EVEX_0F10, | |
1421 | PREFIX_EVEX_0F11, | |
1422 | PREFIX_EVEX_0F12, | |
1423 | PREFIX_EVEX_0F13, | |
1424 | PREFIX_EVEX_0F14, | |
1425 | PREFIX_EVEX_0F15, | |
1426 | PREFIX_EVEX_0F16, | |
1427 | PREFIX_EVEX_0F17, | |
1428 | PREFIX_EVEX_0F28, | |
1429 | PREFIX_EVEX_0F29, | |
1430 | PREFIX_EVEX_0F2A, | |
1431 | PREFIX_EVEX_0F2B, | |
1432 | PREFIX_EVEX_0F2C, | |
1433 | PREFIX_EVEX_0F2D, | |
1434 | PREFIX_EVEX_0F2E, | |
1435 | PREFIX_EVEX_0F2F, | |
1436 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1437 | PREFIX_EVEX_0F54, |
1438 | PREFIX_EVEX_0F55, | |
1439 | PREFIX_EVEX_0F56, | |
1440 | PREFIX_EVEX_0F57, | |
43234a1e L |
1441 | PREFIX_EVEX_0F58, |
1442 | PREFIX_EVEX_0F59, | |
1443 | PREFIX_EVEX_0F5A, | |
1444 | PREFIX_EVEX_0F5B, | |
1445 | PREFIX_EVEX_0F5C, | |
1446 | PREFIX_EVEX_0F5D, | |
1447 | PREFIX_EVEX_0F5E, | |
1448 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1449 | PREFIX_EVEX_0F60, |
1450 | PREFIX_EVEX_0F61, | |
43234a1e | 1451 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1452 | PREFIX_EVEX_0F63, |
1453 | PREFIX_EVEX_0F64, | |
1454 | PREFIX_EVEX_0F65, | |
43234a1e | 1455 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1456 | PREFIX_EVEX_0F67, |
1457 | PREFIX_EVEX_0F68, | |
1458 | PREFIX_EVEX_0F69, | |
43234a1e | 1459 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1460 | PREFIX_EVEX_0F6B, |
43234a1e L |
1461 | PREFIX_EVEX_0F6C, |
1462 | PREFIX_EVEX_0F6D, | |
1463 | PREFIX_EVEX_0F6E, | |
1464 | PREFIX_EVEX_0F6F, | |
1465 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1466 | PREFIX_EVEX_0F71_REG_2, |
1467 | PREFIX_EVEX_0F71_REG_4, | |
1468 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1469 | PREFIX_EVEX_0F72_REG_0, |
1470 | PREFIX_EVEX_0F72_REG_1, | |
1471 | PREFIX_EVEX_0F72_REG_2, | |
1472 | PREFIX_EVEX_0F72_REG_4, | |
1473 | PREFIX_EVEX_0F72_REG_6, | |
1474 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1475 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1476 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1477 | PREFIX_EVEX_0F73_REG_7, |
1478 | PREFIX_EVEX_0F74, | |
1479 | PREFIX_EVEX_0F75, | |
43234a1e L |
1480 | PREFIX_EVEX_0F76, |
1481 | PREFIX_EVEX_0F78, | |
1482 | PREFIX_EVEX_0F79, | |
1483 | PREFIX_EVEX_0F7A, | |
1484 | PREFIX_EVEX_0F7B, | |
1485 | PREFIX_EVEX_0F7E, | |
1486 | PREFIX_EVEX_0F7F, | |
1487 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1488 | PREFIX_EVEX_0FC4, |
1489 | PREFIX_EVEX_0FC5, | |
43234a1e | 1490 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1491 | PREFIX_EVEX_0FD1, |
43234a1e L |
1492 | PREFIX_EVEX_0FD2, |
1493 | PREFIX_EVEX_0FD3, | |
1494 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1495 | PREFIX_EVEX_0FD5, |
43234a1e | 1496 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1497 | PREFIX_EVEX_0FD8, |
1498 | PREFIX_EVEX_0FD9, | |
1499 | PREFIX_EVEX_0FDA, | |
43234a1e | 1500 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1501 | PREFIX_EVEX_0FDC, |
1502 | PREFIX_EVEX_0FDD, | |
1503 | PREFIX_EVEX_0FDE, | |
43234a1e | 1504 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1505 | PREFIX_EVEX_0FE0, |
1506 | PREFIX_EVEX_0FE1, | |
43234a1e | 1507 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1508 | PREFIX_EVEX_0FE3, |
1509 | PREFIX_EVEX_0FE4, | |
1510 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1511 | PREFIX_EVEX_0FE6, |
1512 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1513 | PREFIX_EVEX_0FE8, |
1514 | PREFIX_EVEX_0FE9, | |
1515 | PREFIX_EVEX_0FEA, | |
43234a1e | 1516 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1517 | PREFIX_EVEX_0FEC, |
1518 | PREFIX_EVEX_0FED, | |
1519 | PREFIX_EVEX_0FEE, | |
43234a1e | 1520 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1521 | PREFIX_EVEX_0FF1, |
43234a1e L |
1522 | PREFIX_EVEX_0FF2, |
1523 | PREFIX_EVEX_0FF3, | |
1524 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1525 | PREFIX_EVEX_0FF5, |
1526 | PREFIX_EVEX_0FF6, | |
1527 | PREFIX_EVEX_0FF8, | |
1528 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1529 | PREFIX_EVEX_0FFA, |
1530 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1531 | PREFIX_EVEX_0FFC, |
1532 | PREFIX_EVEX_0FFD, | |
43234a1e | 1533 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1534 | PREFIX_EVEX_0F3800, |
1535 | PREFIX_EVEX_0F3804, | |
1536 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1537 | PREFIX_EVEX_0F380C, |
1538 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1539 | PREFIX_EVEX_0F3810, |
43234a1e L |
1540 | PREFIX_EVEX_0F3811, |
1541 | PREFIX_EVEX_0F3812, | |
1542 | PREFIX_EVEX_0F3813, | |
1543 | PREFIX_EVEX_0F3814, | |
1544 | PREFIX_EVEX_0F3815, | |
1545 | PREFIX_EVEX_0F3816, | |
1546 | PREFIX_EVEX_0F3818, | |
1547 | PREFIX_EVEX_0F3819, | |
1548 | PREFIX_EVEX_0F381A, | |
1549 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1550 | PREFIX_EVEX_0F381C, |
1551 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1552 | PREFIX_EVEX_0F381E, |
1553 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1554 | PREFIX_EVEX_0F3820, |
43234a1e L |
1555 | PREFIX_EVEX_0F3821, |
1556 | PREFIX_EVEX_0F3822, | |
1557 | PREFIX_EVEX_0F3823, | |
1558 | PREFIX_EVEX_0F3824, | |
1559 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1560 | PREFIX_EVEX_0F3826, |
43234a1e L |
1561 | PREFIX_EVEX_0F3827, |
1562 | PREFIX_EVEX_0F3828, | |
1563 | PREFIX_EVEX_0F3829, | |
1564 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1565 | PREFIX_EVEX_0F382B, |
43234a1e L |
1566 | PREFIX_EVEX_0F382C, |
1567 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1568 | PREFIX_EVEX_0F3830, |
43234a1e L |
1569 | PREFIX_EVEX_0F3831, |
1570 | PREFIX_EVEX_0F3832, | |
1571 | PREFIX_EVEX_0F3833, | |
1572 | PREFIX_EVEX_0F3834, | |
1573 | PREFIX_EVEX_0F3835, | |
1574 | PREFIX_EVEX_0F3836, | |
1575 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1576 | PREFIX_EVEX_0F3838, |
43234a1e L |
1577 | PREFIX_EVEX_0F3839, |
1578 | PREFIX_EVEX_0F383A, | |
1579 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1580 | PREFIX_EVEX_0F383C, |
43234a1e | 1581 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1582 | PREFIX_EVEX_0F383E, |
43234a1e L |
1583 | PREFIX_EVEX_0F383F, |
1584 | PREFIX_EVEX_0F3840, | |
1585 | PREFIX_EVEX_0F3842, | |
1586 | PREFIX_EVEX_0F3843, | |
1587 | PREFIX_EVEX_0F3844, | |
1588 | PREFIX_EVEX_0F3845, | |
1589 | PREFIX_EVEX_0F3846, | |
1590 | PREFIX_EVEX_0F3847, | |
1591 | PREFIX_EVEX_0F384C, | |
1592 | PREFIX_EVEX_0F384D, | |
1593 | PREFIX_EVEX_0F384E, | |
1594 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1595 | PREFIX_EVEX_0F3850, |
1596 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1597 | PREFIX_EVEX_0F3852, |
1598 | PREFIX_EVEX_0F3853, | |
ee6872be | 1599 | PREFIX_EVEX_0F3854, |
620214f7 | 1600 | PREFIX_EVEX_0F3855, |
43234a1e L |
1601 | PREFIX_EVEX_0F3858, |
1602 | PREFIX_EVEX_0F3859, | |
1603 | PREFIX_EVEX_0F385A, | |
1604 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1605 | PREFIX_EVEX_0F3862, |
1606 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1607 | PREFIX_EVEX_0F3864, |
1608 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1609 | PREFIX_EVEX_0F3866, |
9186c494 | 1610 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1611 | PREFIX_EVEX_0F3870, |
1612 | PREFIX_EVEX_0F3871, | |
1613 | PREFIX_EVEX_0F3872, | |
1614 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1615 | PREFIX_EVEX_0F3875, |
43234a1e L |
1616 | PREFIX_EVEX_0F3876, |
1617 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1618 | PREFIX_EVEX_0F3878, |
1619 | PREFIX_EVEX_0F3879, | |
1620 | PREFIX_EVEX_0F387A, | |
1621 | PREFIX_EVEX_0F387B, | |
43234a1e | 1622 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1623 | PREFIX_EVEX_0F387D, |
43234a1e L |
1624 | PREFIX_EVEX_0F387E, |
1625 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1626 | PREFIX_EVEX_0F3883, |
43234a1e L |
1627 | PREFIX_EVEX_0F3888, |
1628 | PREFIX_EVEX_0F3889, | |
1629 | PREFIX_EVEX_0F388A, | |
1630 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1631 | PREFIX_EVEX_0F388D, |
ee6872be | 1632 | PREFIX_EVEX_0F388F, |
43234a1e L |
1633 | PREFIX_EVEX_0F3890, |
1634 | PREFIX_EVEX_0F3891, | |
1635 | PREFIX_EVEX_0F3892, | |
1636 | PREFIX_EVEX_0F3893, | |
1637 | PREFIX_EVEX_0F3896, | |
1638 | PREFIX_EVEX_0F3897, | |
1639 | PREFIX_EVEX_0F3898, | |
1640 | PREFIX_EVEX_0F3899, | |
1641 | PREFIX_EVEX_0F389A, | |
1642 | PREFIX_EVEX_0F389B, | |
1643 | PREFIX_EVEX_0F389C, | |
1644 | PREFIX_EVEX_0F389D, | |
1645 | PREFIX_EVEX_0F389E, | |
1646 | PREFIX_EVEX_0F389F, | |
1647 | PREFIX_EVEX_0F38A0, | |
1648 | PREFIX_EVEX_0F38A1, | |
1649 | PREFIX_EVEX_0F38A2, | |
1650 | PREFIX_EVEX_0F38A3, | |
1651 | PREFIX_EVEX_0F38A6, | |
1652 | PREFIX_EVEX_0F38A7, | |
1653 | PREFIX_EVEX_0F38A8, | |
1654 | PREFIX_EVEX_0F38A9, | |
1655 | PREFIX_EVEX_0F38AA, | |
1656 | PREFIX_EVEX_0F38AB, | |
1657 | PREFIX_EVEX_0F38AC, | |
1658 | PREFIX_EVEX_0F38AD, | |
1659 | PREFIX_EVEX_0F38AE, | |
1660 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1661 | PREFIX_EVEX_0F38B4, |
1662 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1663 | PREFIX_EVEX_0F38B6, |
1664 | PREFIX_EVEX_0F38B7, | |
1665 | PREFIX_EVEX_0F38B8, | |
1666 | PREFIX_EVEX_0F38B9, | |
1667 | PREFIX_EVEX_0F38BA, | |
1668 | PREFIX_EVEX_0F38BB, | |
1669 | PREFIX_EVEX_0F38BC, | |
1670 | PREFIX_EVEX_0F38BD, | |
1671 | PREFIX_EVEX_0F38BE, | |
1672 | PREFIX_EVEX_0F38BF, | |
1673 | PREFIX_EVEX_0F38C4, | |
1674 | PREFIX_EVEX_0F38C6_REG_1, | |
1675 | PREFIX_EVEX_0F38C6_REG_2, | |
1676 | PREFIX_EVEX_0F38C6_REG_5, | |
1677 | PREFIX_EVEX_0F38C6_REG_6, | |
1678 | PREFIX_EVEX_0F38C7_REG_1, | |
1679 | PREFIX_EVEX_0F38C7_REG_2, | |
1680 | PREFIX_EVEX_0F38C7_REG_5, | |
1681 | PREFIX_EVEX_0F38C7_REG_6, | |
1682 | PREFIX_EVEX_0F38C8, | |
1683 | PREFIX_EVEX_0F38CA, | |
1684 | PREFIX_EVEX_0F38CB, | |
1685 | PREFIX_EVEX_0F38CC, | |
1686 | PREFIX_EVEX_0F38CD, | |
48521003 | 1687 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1688 | PREFIX_EVEX_0F38DC, |
1689 | PREFIX_EVEX_0F38DD, | |
1690 | PREFIX_EVEX_0F38DE, | |
1691 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1692 | |
1693 | PREFIX_EVEX_0F3A00, | |
1694 | PREFIX_EVEX_0F3A01, | |
1695 | PREFIX_EVEX_0F3A03, | |
1696 | PREFIX_EVEX_0F3A04, | |
1697 | PREFIX_EVEX_0F3A05, | |
1698 | PREFIX_EVEX_0F3A08, | |
1699 | PREFIX_EVEX_0F3A09, | |
1700 | PREFIX_EVEX_0F3A0A, | |
1701 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1702 | PREFIX_EVEX_0F3A0F, |
1703 | PREFIX_EVEX_0F3A14, | |
1704 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1705 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1706 | PREFIX_EVEX_0F3A17, |
1707 | PREFIX_EVEX_0F3A18, | |
1708 | PREFIX_EVEX_0F3A19, | |
1709 | PREFIX_EVEX_0F3A1A, | |
1710 | PREFIX_EVEX_0F3A1B, | |
1711 | PREFIX_EVEX_0F3A1D, | |
1712 | PREFIX_EVEX_0F3A1E, | |
1713 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1714 | PREFIX_EVEX_0F3A20, |
43234a1e | 1715 | PREFIX_EVEX_0F3A21, |
90a915bf | 1716 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1717 | PREFIX_EVEX_0F3A23, |
1718 | PREFIX_EVEX_0F3A25, | |
1719 | PREFIX_EVEX_0F3A26, | |
1720 | PREFIX_EVEX_0F3A27, | |
1721 | PREFIX_EVEX_0F3A38, | |
1722 | PREFIX_EVEX_0F3A39, | |
1723 | PREFIX_EVEX_0F3A3A, | |
1724 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1725 | PREFIX_EVEX_0F3A3E, |
1726 | PREFIX_EVEX_0F3A3F, | |
1727 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1728 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1729 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1730 | PREFIX_EVEX_0F3A50, |
1731 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1732 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1733 | PREFIX_EVEX_0F3A55, |
1734 | PREFIX_EVEX_0F3A56, | |
1735 | PREFIX_EVEX_0F3A57, | |
1736 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1737 | PREFIX_EVEX_0F3A67, |
1738 | PREFIX_EVEX_0F3A70, | |
1739 | PREFIX_EVEX_0F3A71, | |
1740 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1741 | PREFIX_EVEX_0F3A73, |
1742 | PREFIX_EVEX_0F3ACE, | |
1743 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1744 | }; |
4e7d34a6 | 1745 | |
51e7da1b L |
1746 | enum |
1747 | { | |
1748 | X86_64_06 = 0, | |
3873ba12 L |
1749 | X86_64_07, |
1750 | X86_64_0D, | |
1751 | X86_64_16, | |
1752 | X86_64_17, | |
1753 | X86_64_1E, | |
1754 | X86_64_1F, | |
1755 | X86_64_27, | |
1756 | X86_64_2F, | |
1757 | X86_64_37, | |
1758 | X86_64_3F, | |
1759 | X86_64_60, | |
1760 | X86_64_61, | |
1761 | X86_64_62, | |
1762 | X86_64_63, | |
1763 | X86_64_6D, | |
1764 | X86_64_6F, | |
d039fef3 | 1765 | X86_64_82, |
3873ba12 L |
1766 | X86_64_9A, |
1767 | X86_64_C4, | |
1768 | X86_64_C5, | |
1769 | X86_64_CE, | |
1770 | X86_64_D4, | |
1771 | X86_64_D5, | |
a72d2af2 L |
1772 | X86_64_E8, |
1773 | X86_64_E9, | |
3873ba12 L |
1774 | X86_64_EA, |
1775 | X86_64_0F01_REG_0, | |
1776 | X86_64_0F01_REG_1, | |
1777 | X86_64_0F01_REG_2, | |
1778 | X86_64_0F01_REG_3 | |
51e7da1b | 1779 | }; |
4e7d34a6 | 1780 | |
51e7da1b L |
1781 | enum |
1782 | { | |
1783 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1784 | THREE_BYTE_0F3A |
51e7da1b | 1785 | }; |
4e7d34a6 | 1786 | |
f88c9eb0 SP |
1787 | enum |
1788 | { | |
5dd85c99 SP |
1789 | XOP_08 = 0, |
1790 | XOP_09, | |
f88c9eb0 SP |
1791 | XOP_0A |
1792 | }; | |
1793 | ||
51e7da1b L |
1794 | enum |
1795 | { | |
1796 | VEX_0F = 0, | |
3873ba12 L |
1797 | VEX_0F38, |
1798 | VEX_0F3A | |
51e7da1b | 1799 | }; |
c0f3af97 | 1800 | |
43234a1e L |
1801 | enum |
1802 | { | |
1803 | EVEX_0F = 0, | |
1804 | EVEX_0F38, | |
1805 | EVEX_0F3A | |
1806 | }; | |
1807 | ||
51e7da1b L |
1808 | enum |
1809 | { | |
ec6f095a | 1810 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b L |
1811 | VEX_LEN_0F12_P_0_M_1, |
1812 | VEX_LEN_0F12_P_2, | |
1813 | VEX_LEN_0F13_M_0, | |
1814 | VEX_LEN_0F16_P_0_M_0, | |
1815 | VEX_LEN_0F16_P_0_M_1, | |
1816 | VEX_LEN_0F16_P_2, | |
1817 | VEX_LEN_0F17_M_0, | |
43234a1e | 1818 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1819 | VEX_LEN_0F41_P_2, |
43234a1e | 1820 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1821 | VEX_LEN_0F42_P_2, |
43234a1e | 1822 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1823 | VEX_LEN_0F44_P_2, |
43234a1e | 1824 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1825 | VEX_LEN_0F45_P_2, |
43234a1e | 1826 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1827 | VEX_LEN_0F46_P_2, |
43234a1e | 1828 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1829 | VEX_LEN_0F47_P_2, |
1830 | VEX_LEN_0F4A_P_0, | |
1831 | VEX_LEN_0F4A_P_2, | |
1832 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1833 | VEX_LEN_0F4B_P_2, |
592a252b | 1834 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1835 | VEX_LEN_0F77_P_0, |
592a252b L |
1836 | VEX_LEN_0F7E_P_1, |
1837 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1838 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1839 | VEX_LEN_0F90_P_2, |
43234a1e | 1840 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1841 | VEX_LEN_0F91_P_2, |
43234a1e | 1842 | VEX_LEN_0F92_P_0, |
90a915bf | 1843 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1844 | VEX_LEN_0F92_P_3, |
43234a1e | 1845 | VEX_LEN_0F93_P_0, |
90a915bf | 1846 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1847 | VEX_LEN_0F93_P_3, |
43234a1e | 1848 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1849 | VEX_LEN_0F98_P_2, |
1850 | VEX_LEN_0F99_P_0, | |
1851 | VEX_LEN_0F99_P_2, | |
592a252b L |
1852 | VEX_LEN_0FAE_R_2_M_0, |
1853 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1854 | VEX_LEN_0FC4_P_2, |
1855 | VEX_LEN_0FC5_P_2, | |
592a252b | 1856 | VEX_LEN_0FD6_P_2, |
592a252b | 1857 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1858 | VEX_LEN_0F3816_P_2, |
1859 | VEX_LEN_0F3819_P_2, | |
592a252b | 1860 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1861 | VEX_LEN_0F3836_P_2, |
592a252b | 1862 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1863 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1864 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1865 | VEX_LEN_0F38F2_P_0, |
1866 | VEX_LEN_0F38F3_R_1_P_0, | |
1867 | VEX_LEN_0F38F3_R_2_P_0, | |
1868 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1869 | VEX_LEN_0F38F5_P_0, |
1870 | VEX_LEN_0F38F5_P_1, | |
1871 | VEX_LEN_0F38F5_P_3, | |
1872 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1873 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1874 | VEX_LEN_0F38F7_P_1, |
1875 | VEX_LEN_0F38F7_P_2, | |
1876 | VEX_LEN_0F38F7_P_3, | |
1877 | VEX_LEN_0F3A00_P_2, | |
1878 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1879 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1880 | VEX_LEN_0F3A14_P_2, |
1881 | VEX_LEN_0F3A15_P_2, | |
1882 | VEX_LEN_0F3A16_P_2, | |
1883 | VEX_LEN_0F3A17_P_2, | |
1884 | VEX_LEN_0F3A18_P_2, | |
1885 | VEX_LEN_0F3A19_P_2, | |
1886 | VEX_LEN_0F3A20_P_2, | |
1887 | VEX_LEN_0F3A21_P_2, | |
1888 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1889 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1890 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1891 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1892 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1893 | VEX_LEN_0F3A38_P_2, |
1894 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1895 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1896 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1897 | VEX_LEN_0F3A60_P_2, |
1898 | VEX_LEN_0F3A61_P_2, | |
1899 | VEX_LEN_0F3A62_P_2, | |
1900 | VEX_LEN_0F3A63_P_2, | |
1901 | VEX_LEN_0F3A6A_P_2, | |
1902 | VEX_LEN_0F3A6B_P_2, | |
1903 | VEX_LEN_0F3A6E_P_2, | |
1904 | VEX_LEN_0F3A6F_P_2, | |
1905 | VEX_LEN_0F3A7A_P_2, | |
1906 | VEX_LEN_0F3A7B_P_2, | |
1907 | VEX_LEN_0F3A7E_P_2, | |
1908 | VEX_LEN_0F3A7F_P_2, | |
1909 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1910 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1911 | VEX_LEN_0FXOP_08_CC, |
1912 | VEX_LEN_0FXOP_08_CD, | |
1913 | VEX_LEN_0FXOP_08_CE, | |
1914 | VEX_LEN_0FXOP_08_CF, | |
1915 | VEX_LEN_0FXOP_08_EC, | |
1916 | VEX_LEN_0FXOP_08_ED, | |
1917 | VEX_LEN_0FXOP_08_EE, | |
1918 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1919 | VEX_LEN_0FXOP_09_80, |
1920 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1921 | }; |
c0f3af97 | 1922 | |
04e2a182 L |
1923 | enum |
1924 | { | |
1925 | EVEX_LEN_0F6E_P_2 = 0, | |
1926 | EVEX_LEN_0F7E_P_1, | |
1927 | EVEX_LEN_0F7E_P_2, | |
12efd68d | 1928 | EVEX_LEN_0FD6_P_2, |
f0a6222e L |
1929 | EVEX_LEN_0F3819_P_2_W_0, |
1930 | EVEX_LEN_0F3819_P_2_W_1, | |
1931 | EVEX_LEN_0F381A_P_2_W_0, | |
1932 | EVEX_LEN_0F381A_P_2_W_1, | |
1933 | EVEX_LEN_0F381B_P_2_W_0, | |
1934 | EVEX_LEN_0F381B_P_2_W_1, | |
1935 | EVEX_LEN_0F385A_P_2_W_0, | |
1936 | EVEX_LEN_0F385A_P_2_W_1, | |
1937 | EVEX_LEN_0F385B_P_2_W_0, | |
1938 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1939 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1940 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1941 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1942 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1943 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1944 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1945 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1946 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1947 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1948 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1949 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1950 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
12efd68d L |
1951 | EVEX_LEN_0F3A18_P_2_W_0, |
1952 | EVEX_LEN_0F3A18_P_2_W_1, | |
1953 | EVEX_LEN_0F3A19_P_2_W_0, | |
1954 | EVEX_LEN_0F3A19_P_2_W_1, | |
1955 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1956 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1957 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 L |
1958 | EVEX_LEN_0F3A1B_P_2_W_1, |
1959 | EVEX_LEN_0F3A23_P_2_W_0, | |
1960 | EVEX_LEN_0F3A23_P_2_W_1, | |
1961 | EVEX_LEN_0F3A38_P_2_W_0, | |
1962 | EVEX_LEN_0F3A38_P_2_W_1, | |
1963 | EVEX_LEN_0F3A39_P_2_W_0, | |
1964 | EVEX_LEN_0F3A39_P_2_W_1, | |
1965 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1966 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1967 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1968 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1969 | EVEX_LEN_0F3A43_P_2_W_0, | |
1970 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1971 | }; |
1972 | ||
9e30b8e0 L |
1973 | enum |
1974 | { | |
ec6f095a | 1975 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1976 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1977 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1978 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1979 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1980 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1981 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1982 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1983 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1984 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1985 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1986 | VEX_W_0F47_P_2_LEN_1, |
1987 | VEX_W_0F4A_P_0_LEN_1, | |
1988 | VEX_W_0F4A_P_2_LEN_1, | |
1989 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1990 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1991 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1992 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1993 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1994 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1995 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1996 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1997 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1998 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1999 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2000 | VEX_W_0F98_P_2_LEN_0, |
2001 | VEX_W_0F99_P_0_LEN_0, | |
2002 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2003 | VEX_W_0F380C_P_2, |
2004 | VEX_W_0F380D_P_2, | |
2005 | VEX_W_0F380E_P_2, | |
2006 | VEX_W_0F380F_P_2, | |
6c30d220 | 2007 | VEX_W_0F3816_P_2, |
6c30d220 L |
2008 | VEX_W_0F3818_P_2, |
2009 | VEX_W_0F3819_P_2, | |
592a252b | 2010 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
2011 | VEX_W_0F382C_P_2_M_0, |
2012 | VEX_W_0F382D_P_2_M_0, | |
2013 | VEX_W_0F382E_P_2_M_0, | |
2014 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 2015 | VEX_W_0F3836_P_2, |
6c30d220 L |
2016 | VEX_W_0F3846_P_2, |
2017 | VEX_W_0F3858_P_2, | |
2018 | VEX_W_0F3859_P_2, | |
2019 | VEX_W_0F385A_P_2_M_0, | |
2020 | VEX_W_0F3878_P_2, | |
2021 | VEX_W_0F3879_P_2, | |
48521003 | 2022 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2023 | VEX_W_0F3A00_P_2, |
2024 | VEX_W_0F3A01_P_2, | |
2025 | VEX_W_0F3A02_P_2, | |
592a252b L |
2026 | VEX_W_0F3A04_P_2, |
2027 | VEX_W_0F3A05_P_2, | |
2028 | VEX_W_0F3A06_P_2, | |
592a252b L |
2029 | VEX_W_0F3A18_P_2, |
2030 | VEX_W_0F3A19_P_2, | |
43234a1e | 2031 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2032 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2033 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2034 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2035 | VEX_W_0F3A38_P_2, |
2036 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2037 | VEX_W_0F3A46_P_2, |
592a252b L |
2038 | VEX_W_0F3A48_P_2, |
2039 | VEX_W_0F3A49_P_2, | |
2040 | VEX_W_0F3A4A_P_2, | |
2041 | VEX_W_0F3A4B_P_2, | |
2042 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2043 | VEX_W_0F3ACE_P_2, |
2044 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2045 | |
2046 | EVEX_W_0F10_P_0, | |
36cc073e | 2047 | EVEX_W_0F10_P_1, |
43234a1e | 2048 | EVEX_W_0F10_P_2, |
36cc073e | 2049 | EVEX_W_0F10_P_3, |
43234a1e | 2050 | EVEX_W_0F11_P_0, |
36cc073e | 2051 | EVEX_W_0F11_P_1, |
43234a1e | 2052 | EVEX_W_0F11_P_2, |
36cc073e | 2053 | EVEX_W_0F11_P_3, |
43234a1e L |
2054 | EVEX_W_0F12_P_0_M_0, |
2055 | EVEX_W_0F12_P_0_M_1, | |
2056 | EVEX_W_0F12_P_1, | |
2057 | EVEX_W_0F12_P_2, | |
2058 | EVEX_W_0F12_P_3, | |
2059 | EVEX_W_0F13_P_0, | |
2060 | EVEX_W_0F13_P_2, | |
2061 | EVEX_W_0F14_P_0, | |
2062 | EVEX_W_0F14_P_2, | |
2063 | EVEX_W_0F15_P_0, | |
2064 | EVEX_W_0F15_P_2, | |
2065 | EVEX_W_0F16_P_0_M_0, | |
2066 | EVEX_W_0F16_P_0_M_1, | |
2067 | EVEX_W_0F16_P_1, | |
2068 | EVEX_W_0F16_P_2, | |
2069 | EVEX_W_0F17_P_0, | |
2070 | EVEX_W_0F17_P_2, | |
2071 | EVEX_W_0F28_P_0, | |
2072 | EVEX_W_0F28_P_2, | |
2073 | EVEX_W_0F29_P_0, | |
2074 | EVEX_W_0F29_P_2, | |
43234a1e L |
2075 | EVEX_W_0F2A_P_3, |
2076 | EVEX_W_0F2B_P_0, | |
2077 | EVEX_W_0F2B_P_2, | |
2078 | EVEX_W_0F2E_P_0, | |
2079 | EVEX_W_0F2E_P_2, | |
2080 | EVEX_W_0F2F_P_0, | |
2081 | EVEX_W_0F2F_P_2, | |
2082 | EVEX_W_0F51_P_0, | |
2083 | EVEX_W_0F51_P_1, | |
2084 | EVEX_W_0F51_P_2, | |
2085 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2086 | EVEX_W_0F54_P_0, |
2087 | EVEX_W_0F54_P_2, | |
2088 | EVEX_W_0F55_P_0, | |
2089 | EVEX_W_0F55_P_2, | |
2090 | EVEX_W_0F56_P_0, | |
2091 | EVEX_W_0F56_P_2, | |
2092 | EVEX_W_0F57_P_0, | |
2093 | EVEX_W_0F57_P_2, | |
43234a1e L |
2094 | EVEX_W_0F58_P_0, |
2095 | EVEX_W_0F58_P_1, | |
2096 | EVEX_W_0F58_P_2, | |
2097 | EVEX_W_0F58_P_3, | |
2098 | EVEX_W_0F59_P_0, | |
2099 | EVEX_W_0F59_P_1, | |
2100 | EVEX_W_0F59_P_2, | |
2101 | EVEX_W_0F59_P_3, | |
2102 | EVEX_W_0F5A_P_0, | |
2103 | EVEX_W_0F5A_P_1, | |
2104 | EVEX_W_0F5A_P_2, | |
2105 | EVEX_W_0F5A_P_3, | |
2106 | EVEX_W_0F5B_P_0, | |
2107 | EVEX_W_0F5B_P_1, | |
2108 | EVEX_W_0F5B_P_2, | |
2109 | EVEX_W_0F5C_P_0, | |
2110 | EVEX_W_0F5C_P_1, | |
2111 | EVEX_W_0F5C_P_2, | |
2112 | EVEX_W_0F5C_P_3, | |
2113 | EVEX_W_0F5D_P_0, | |
2114 | EVEX_W_0F5D_P_1, | |
2115 | EVEX_W_0F5D_P_2, | |
2116 | EVEX_W_0F5D_P_3, | |
2117 | EVEX_W_0F5E_P_0, | |
2118 | EVEX_W_0F5E_P_1, | |
2119 | EVEX_W_0F5E_P_2, | |
2120 | EVEX_W_0F5E_P_3, | |
2121 | EVEX_W_0F5F_P_0, | |
2122 | EVEX_W_0F5F_P_1, | |
2123 | EVEX_W_0F5F_P_2, | |
2124 | EVEX_W_0F5F_P_3, | |
2125 | EVEX_W_0F62_P_2, | |
2126 | EVEX_W_0F66_P_2, | |
2127 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2128 | EVEX_W_0F6B_P_2, |
43234a1e L |
2129 | EVEX_W_0F6C_P_2, |
2130 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2131 | EVEX_W_0F6F_P_1, |
2132 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2133 | EVEX_W_0F6F_P_3, |
43234a1e L |
2134 | EVEX_W_0F70_P_2, |
2135 | EVEX_W_0F72_R_2_P_2, | |
2136 | EVEX_W_0F72_R_6_P_2, | |
2137 | EVEX_W_0F73_R_2_P_2, | |
2138 | EVEX_W_0F73_R_6_P_2, | |
2139 | EVEX_W_0F76_P_2, | |
2140 | EVEX_W_0F78_P_0, | |
90a915bf | 2141 | EVEX_W_0F78_P_2, |
43234a1e | 2142 | EVEX_W_0F79_P_0, |
90a915bf | 2143 | EVEX_W_0F79_P_2, |
43234a1e | 2144 | EVEX_W_0F7A_P_1, |
90a915bf | 2145 | EVEX_W_0F7A_P_2, |
43234a1e | 2146 | EVEX_W_0F7A_P_3, |
90a915bf | 2147 | EVEX_W_0F7B_P_2, |
43234a1e L |
2148 | EVEX_W_0F7B_P_3, |
2149 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2150 | EVEX_W_0F7F_P_1, |
2151 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2152 | EVEX_W_0F7F_P_3, |
43234a1e L |
2153 | EVEX_W_0FC2_P_0, |
2154 | EVEX_W_0FC2_P_1, | |
2155 | EVEX_W_0FC2_P_2, | |
2156 | EVEX_W_0FC2_P_3, | |
2157 | EVEX_W_0FC6_P_0, | |
2158 | EVEX_W_0FC6_P_2, | |
2159 | EVEX_W_0FD2_P_2, | |
2160 | EVEX_W_0FD3_P_2, | |
2161 | EVEX_W_0FD4_P_2, | |
2162 | EVEX_W_0FD6_P_2, | |
2163 | EVEX_W_0FE6_P_1, | |
2164 | EVEX_W_0FE6_P_2, | |
2165 | EVEX_W_0FE6_P_3, | |
2166 | EVEX_W_0FE7_P_2, | |
2167 | EVEX_W_0FF2_P_2, | |
2168 | EVEX_W_0FF3_P_2, | |
2169 | EVEX_W_0FF4_P_2, | |
2170 | EVEX_W_0FFA_P_2, | |
2171 | EVEX_W_0FFB_P_2, | |
2172 | EVEX_W_0FFE_P_2, | |
2173 | EVEX_W_0F380C_P_2, | |
2174 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2175 | EVEX_W_0F3810_P_1, |
2176 | EVEX_W_0F3810_P_2, | |
43234a1e | 2177 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2178 | EVEX_W_0F3811_P_2, |
43234a1e | 2179 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2180 | EVEX_W_0F3812_P_2, |
43234a1e L |
2181 | EVEX_W_0F3813_P_1, |
2182 | EVEX_W_0F3813_P_2, | |
2183 | EVEX_W_0F3814_P_1, | |
2184 | EVEX_W_0F3815_P_1, | |
2185 | EVEX_W_0F3818_P_2, | |
2186 | EVEX_W_0F3819_P_2, | |
2187 | EVEX_W_0F381A_P_2, | |
2188 | EVEX_W_0F381B_P_2, | |
2189 | EVEX_W_0F381E_P_2, | |
2190 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2191 | EVEX_W_0F3820_P_1, |
43234a1e L |
2192 | EVEX_W_0F3821_P_1, |
2193 | EVEX_W_0F3822_P_1, | |
2194 | EVEX_W_0F3823_P_1, | |
2195 | EVEX_W_0F3824_P_1, | |
2196 | EVEX_W_0F3825_P_1, | |
2197 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2198 | EVEX_W_0F3826_P_1, |
2199 | EVEX_W_0F3826_P_2, | |
2200 | EVEX_W_0F3828_P_1, | |
43234a1e | 2201 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2202 | EVEX_W_0F3829_P_1, |
43234a1e L |
2203 | EVEX_W_0F3829_P_2, |
2204 | EVEX_W_0F382A_P_1, | |
2205 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2206 | EVEX_W_0F382B_P_2, |
2207 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2208 | EVEX_W_0F3831_P_1, |
2209 | EVEX_W_0F3832_P_1, | |
2210 | EVEX_W_0F3833_P_1, | |
2211 | EVEX_W_0F3834_P_1, | |
2212 | EVEX_W_0F3835_P_1, | |
2213 | EVEX_W_0F3835_P_2, | |
2214 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2215 | EVEX_W_0F3838_P_1, |
2216 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2217 | EVEX_W_0F383A_P_1, |
2218 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2219 | EVEX_W_0F3852_P_1, |
ee6872be | 2220 | EVEX_W_0F3854_P_2, |
620214f7 | 2221 | EVEX_W_0F3855_P_2, |
43234a1e L |
2222 | EVEX_W_0F3858_P_2, |
2223 | EVEX_W_0F3859_P_2, | |
2224 | EVEX_W_0F385A_P_2, | |
2225 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2226 | EVEX_W_0F3862_P_2, |
2227 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2228 | EVEX_W_0F3866_P_2, |
9186c494 | 2229 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2230 | EVEX_W_0F3870_P_2, |
2231 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2232 | EVEX_W_0F3872_P_1, |
53467f57 | 2233 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2234 | EVEX_W_0F3872_P_3, |
53467f57 | 2235 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2236 | EVEX_W_0F3875_P_2, |
2237 | EVEX_W_0F3878_P_2, | |
2238 | EVEX_W_0F3879_P_2, | |
2239 | EVEX_W_0F387A_P_2, | |
2240 | EVEX_W_0F387B_P_2, | |
2241 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2242 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2243 | EVEX_W_0F388D_P_2, |
43234a1e L |
2244 | EVEX_W_0F3891_P_2, |
2245 | EVEX_W_0F3893_P_2, | |
2246 | EVEX_W_0F38A1_P_2, | |
2247 | EVEX_W_0F38A3_P_2, | |
2248 | EVEX_W_0F38C7_R_1_P_2, | |
2249 | EVEX_W_0F38C7_R_2_P_2, | |
2250 | EVEX_W_0F38C7_R_5_P_2, | |
2251 | EVEX_W_0F38C7_R_6_P_2, | |
2252 | ||
2253 | EVEX_W_0F3A00_P_2, | |
2254 | EVEX_W_0F3A01_P_2, | |
2255 | EVEX_W_0F3A04_P_2, | |
2256 | EVEX_W_0F3A05_P_2, | |
2257 | EVEX_W_0F3A08_P_2, | |
2258 | EVEX_W_0F3A09_P_2, | |
2259 | EVEX_W_0F3A0A_P_2, | |
2260 | EVEX_W_0F3A0B_P_2, | |
2261 | EVEX_W_0F3A18_P_2, | |
2262 | EVEX_W_0F3A19_P_2, | |
2263 | EVEX_W_0F3A1A_P_2, | |
2264 | EVEX_W_0F3A1B_P_2, | |
2265 | EVEX_W_0F3A1D_P_2, | |
2266 | EVEX_W_0F3A21_P_2, | |
2267 | EVEX_W_0F3A23_P_2, | |
2268 | EVEX_W_0F3A38_P_2, | |
2269 | EVEX_W_0F3A39_P_2, | |
2270 | EVEX_W_0F3A3A_P_2, | |
2271 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2272 | EVEX_W_0F3A3E_P_2, |
2273 | EVEX_W_0F3A3F_P_2, | |
2274 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2275 | EVEX_W_0F3A43_P_2, |
2276 | EVEX_W_0F3A50_P_2, | |
2277 | EVEX_W_0F3A51_P_2, | |
2278 | EVEX_W_0F3A56_P_2, | |
2279 | EVEX_W_0F3A57_P_2, | |
2280 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2281 | EVEX_W_0F3A67_P_2, |
2282 | EVEX_W_0F3A70_P_2, | |
2283 | EVEX_W_0F3A71_P_2, | |
2284 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2285 | EVEX_W_0F3A73_P_2, |
2286 | EVEX_W_0F3ACE_P_2, | |
2287 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2288 | }; |
2289 | ||
26ca5450 | 2290 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2291 | |
2292 | struct dis386 { | |
2da11e11 | 2293 | const char *name; |
ce518a5f L |
2294 | struct |
2295 | { | |
2296 | op_rtn rtn; | |
2297 | int bytemode; | |
2298 | } op[MAX_OPERANDS]; | |
bf890a93 | 2299 | unsigned int prefix_requirement; |
252b5132 RH |
2300 | }; |
2301 | ||
2302 | /* Upper case letters in the instruction names here are macros. | |
2303 | 'A' => print 'b' if no register operands or suffix_always is true | |
2304 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2305 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2306 | size prefix |
ed7841b3 | 2307 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2308 | suffix_always is true |
252b5132 | 2309 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2310 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2311 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2312 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2313 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2314 | for some of the macro letters) |
9306ca4a | 2315 | 'J' => print 'l' |
42903f7f | 2316 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2317 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2318 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2319 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2320 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2321 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2322 | or suffix_always is true. print 'q' if rex prefix is present. |
2323 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2324 | is true | |
a35ca55a | 2325 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2326 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2327 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2328 | prefix and behave as 'P' otherwise | |
2329 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2330 | prefix and behave as 'Q' otherwise | |
2331 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2332 | prefix and behave as 'S' otherwise | |
a35ca55a | 2333 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2334 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2335 | 'Y' unused. |
6dd5059a | 2336 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2337 | '!' => change condition from true to false or from false to true. |
98b528ac | 2338 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2339 | '^' => print 'w' or 'l' depending on operand size prefix or |
2340 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2341 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2342 | on operand size prefix. | |
07f5af7d L |
2343 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2344 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2345 | otherwise | |
98b528ac L |
2346 | |
2347 | 2 upper case letter macros: | |
04d824a4 JB |
2348 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2349 | operands and no broadcast. | |
2350 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2351 | register operands and no broadcast. | |
4b06377f L |
2352 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2353 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2354 | or suffix_always is true |
4b06377f L |
2355 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2356 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2357 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2358 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2359 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2360 | an operand size prefix, or suffix_always is true. print | |
2361 | 'q' if rex prefix is present. | |
52b15da3 | 2362 | |
6439fc28 AM |
2363 | Many of the above letters print nothing in Intel mode. See "putop" |
2364 | for the details. | |
52b15da3 | 2365 | |
6439fc28 | 2366 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2367 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2368 | |
6439fc28 | 2369 | static const struct dis386 dis386[] = { |
252b5132 | 2370 | /* 00 */ |
bf890a93 IT |
2371 | { "addB", { Ebh1, Gb }, 0 }, |
2372 | { "addS", { Evh1, Gv }, 0 }, | |
2373 | { "addB", { Gb, EbS }, 0 }, | |
2374 | { "addS", { Gv, EvS }, 0 }, | |
2375 | { "addB", { AL, Ib }, 0 }, | |
2376 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2377 | { X86_64_TABLE (X86_64_06) }, |
2378 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2379 | /* 08 */ |
bf890a93 IT |
2380 | { "orB", { Ebh1, Gb }, 0 }, |
2381 | { "orS", { Evh1, Gv }, 0 }, | |
2382 | { "orB", { Gb, EbS }, 0 }, | |
2383 | { "orS", { Gv, EvS }, 0 }, | |
2384 | { "orB", { AL, Ib }, 0 }, | |
2385 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2386 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2387 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2388 | /* 10 */ |
bf890a93 IT |
2389 | { "adcB", { Ebh1, Gb }, 0 }, |
2390 | { "adcS", { Evh1, Gv }, 0 }, | |
2391 | { "adcB", { Gb, EbS }, 0 }, | |
2392 | { "adcS", { Gv, EvS }, 0 }, | |
2393 | { "adcB", { AL, Ib }, 0 }, | |
2394 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2395 | { X86_64_TABLE (X86_64_16) }, |
2396 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2397 | /* 18 */ |
bf890a93 IT |
2398 | { "sbbB", { Ebh1, Gb }, 0 }, |
2399 | { "sbbS", { Evh1, Gv }, 0 }, | |
2400 | { "sbbB", { Gb, EbS }, 0 }, | |
2401 | { "sbbS", { Gv, EvS }, 0 }, | |
2402 | { "sbbB", { AL, Ib }, 0 }, | |
2403 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2404 | { X86_64_TABLE (X86_64_1E) }, |
2405 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2406 | /* 20 */ |
bf890a93 IT |
2407 | { "andB", { Ebh1, Gb }, 0 }, |
2408 | { "andS", { Evh1, Gv }, 0 }, | |
2409 | { "andB", { Gb, EbS }, 0 }, | |
2410 | { "andS", { Gv, EvS }, 0 }, | |
2411 | { "andB", { AL, Ib }, 0 }, | |
2412 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2413 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2414 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2415 | /* 28 */ |
bf890a93 IT |
2416 | { "subB", { Ebh1, Gb }, 0 }, |
2417 | { "subS", { Evh1, Gv }, 0 }, | |
2418 | { "subB", { Gb, EbS }, 0 }, | |
2419 | { "subS", { Gv, EvS }, 0 }, | |
2420 | { "subB", { AL, Ib }, 0 }, | |
2421 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2422 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2423 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2424 | /* 30 */ |
bf890a93 IT |
2425 | { "xorB", { Ebh1, Gb }, 0 }, |
2426 | { "xorS", { Evh1, Gv }, 0 }, | |
2427 | { "xorB", { Gb, EbS }, 0 }, | |
2428 | { "xorS", { Gv, EvS }, 0 }, | |
2429 | { "xorB", { AL, Ib }, 0 }, | |
2430 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2431 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2432 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2433 | /* 38 */ |
bf890a93 IT |
2434 | { "cmpB", { Eb, Gb }, 0 }, |
2435 | { "cmpS", { Ev, Gv }, 0 }, | |
2436 | { "cmpB", { Gb, EbS }, 0 }, | |
2437 | { "cmpS", { Gv, EvS }, 0 }, | |
2438 | { "cmpB", { AL, Ib }, 0 }, | |
2439 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2440 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2441 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2442 | /* 40 */ |
bf890a93 IT |
2443 | { "inc{S|}", { RMeAX }, 0 }, |
2444 | { "inc{S|}", { RMeCX }, 0 }, | |
2445 | { "inc{S|}", { RMeDX }, 0 }, | |
2446 | { "inc{S|}", { RMeBX }, 0 }, | |
2447 | { "inc{S|}", { RMeSP }, 0 }, | |
2448 | { "inc{S|}", { RMeBP }, 0 }, | |
2449 | { "inc{S|}", { RMeSI }, 0 }, | |
2450 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2451 | /* 48 */ |
bf890a93 IT |
2452 | { "dec{S|}", { RMeAX }, 0 }, |
2453 | { "dec{S|}", { RMeCX }, 0 }, | |
2454 | { "dec{S|}", { RMeDX }, 0 }, | |
2455 | { "dec{S|}", { RMeBX }, 0 }, | |
2456 | { "dec{S|}", { RMeSP }, 0 }, | |
2457 | { "dec{S|}", { RMeBP }, 0 }, | |
2458 | { "dec{S|}", { RMeSI }, 0 }, | |
2459 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2460 | /* 50 */ |
bf890a93 IT |
2461 | { "pushV", { RMrAX }, 0 }, |
2462 | { "pushV", { RMrCX }, 0 }, | |
2463 | { "pushV", { RMrDX }, 0 }, | |
2464 | { "pushV", { RMrBX }, 0 }, | |
2465 | { "pushV", { RMrSP }, 0 }, | |
2466 | { "pushV", { RMrBP }, 0 }, | |
2467 | { "pushV", { RMrSI }, 0 }, | |
2468 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2469 | /* 58 */ |
bf890a93 IT |
2470 | { "popV", { RMrAX }, 0 }, |
2471 | { "popV", { RMrCX }, 0 }, | |
2472 | { "popV", { RMrDX }, 0 }, | |
2473 | { "popV", { RMrBX }, 0 }, | |
2474 | { "popV", { RMrSP }, 0 }, | |
2475 | { "popV", { RMrBP }, 0 }, | |
2476 | { "popV", { RMrSI }, 0 }, | |
2477 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2478 | /* 60 */ |
4e7d34a6 L |
2479 | { X86_64_TABLE (X86_64_60) }, |
2480 | { X86_64_TABLE (X86_64_61) }, | |
2481 | { X86_64_TABLE (X86_64_62) }, | |
2482 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2483 | { Bad_Opcode }, /* seg fs */ |
2484 | { Bad_Opcode }, /* seg gs */ | |
2485 | { Bad_Opcode }, /* op size prefix */ | |
2486 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2487 | /* 68 */ |
bf890a93 IT |
2488 | { "pushT", { sIv }, 0 }, |
2489 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2490 | { "pushT", { sIbT }, 0 }, | |
2491 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2492 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2493 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2494 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2495 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2496 | /* 70 */ |
bf890a93 IT |
2497 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2498 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2499 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2500 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2501 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2502 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2503 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2504 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2505 | /* 78 */ |
bf890a93 IT |
2506 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2507 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2508 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2509 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2510 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2511 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2512 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2513 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2514 | /* 80 */ |
1ceb70f8 L |
2515 | { REG_TABLE (REG_80) }, |
2516 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2517 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2518 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2519 | { "testB", { Eb, Gb }, 0 }, |
2520 | { "testS", { Ev, Gv }, 0 }, | |
2521 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2522 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2523 | /* 88 */ |
bf890a93 IT |
2524 | { "movB", { Ebh3, Gb }, 0 }, |
2525 | { "movS", { Evh3, Gv }, 0 }, | |
2526 | { "movB", { Gb, EbS }, 0 }, | |
2527 | { "movS", { Gv, EvS }, 0 }, | |
2528 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2529 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2530 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2531 | { REG_TABLE (REG_8F) }, |
252b5132 | 2532 | /* 90 */ |
1ceb70f8 | 2533 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2534 | { "xchgS", { RMeCX, eAX }, 0 }, |
2535 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2536 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2537 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2538 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2539 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2540 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2541 | /* 98 */ |
bf890a93 IT |
2542 | { "cW{t|}R", { XX }, 0 }, |
2543 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2544 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2545 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2546 | { "pushfT", { XX }, 0 }, |
2547 | { "popfT", { XX }, 0 }, | |
2548 | { "sahf", { XX }, 0 }, | |
2549 | { "lahf", { XX }, 0 }, | |
252b5132 | 2550 | /* a0 */ |
bf890a93 IT |
2551 | { "mov%LB", { AL, Ob }, 0 }, |
2552 | { "mov%LS", { eAX, Ov }, 0 }, | |
2553 | { "mov%LB", { Ob, AL }, 0 }, | |
2554 | { "mov%LS", { Ov, eAX }, 0 }, | |
2555 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2556 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2557 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2558 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2559 | /* a8 */ |
bf890a93 IT |
2560 | { "testB", { AL, Ib }, 0 }, |
2561 | { "testS", { eAX, Iv }, 0 }, | |
2562 | { "stosB", { Ybr, AL }, 0 }, | |
2563 | { "stosS", { Yvr, eAX }, 0 }, | |
2564 | { "lodsB", { ALr, Xb }, 0 }, | |
2565 | { "lodsS", { eAXr, Xv }, 0 }, | |
2566 | { "scasB", { AL, Yb }, 0 }, | |
2567 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2568 | /* b0 */ |
bf890a93 IT |
2569 | { "movB", { RMAL, Ib }, 0 }, |
2570 | { "movB", { RMCL, Ib }, 0 }, | |
2571 | { "movB", { RMDL, Ib }, 0 }, | |
2572 | { "movB", { RMBL, Ib }, 0 }, | |
2573 | { "movB", { RMAH, Ib }, 0 }, | |
2574 | { "movB", { RMCH, Ib }, 0 }, | |
2575 | { "movB", { RMDH, Ib }, 0 }, | |
2576 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2577 | /* b8 */ |
bf890a93 IT |
2578 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2579 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2580 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2581 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2582 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2583 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2584 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2585 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2586 | /* c0 */ |
1ceb70f8 L |
2587 | { REG_TABLE (REG_C0) }, |
2588 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2589 | { "retT", { Iw, BND }, 0 }, |
2590 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2591 | { X86_64_TABLE (X86_64_C4) }, |
2592 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2593 | { REG_TABLE (REG_C6) }, |
2594 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2595 | /* c8 */ |
bf890a93 IT |
2596 | { "enterT", { Iw, Ib }, 0 }, |
2597 | { "leaveT", { XX }, 0 }, | |
2598 | { "Jret{|f}P", { Iw }, 0 }, | |
2599 | { "Jret{|f}P", { XX }, 0 }, | |
2600 | { "int3", { XX }, 0 }, | |
2601 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2602 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2603 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2604 | /* d0 */ |
1ceb70f8 L |
2605 | { REG_TABLE (REG_D0) }, |
2606 | { REG_TABLE (REG_D1) }, | |
2607 | { REG_TABLE (REG_D2) }, | |
2608 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2609 | { X86_64_TABLE (X86_64_D4) }, |
2610 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2611 | { Bad_Opcode }, |
bf890a93 | 2612 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2613 | /* d8 */ |
2614 | { FLOAT }, | |
2615 | { FLOAT }, | |
2616 | { FLOAT }, | |
2617 | { FLOAT }, | |
2618 | { FLOAT }, | |
2619 | { FLOAT }, | |
2620 | { FLOAT }, | |
2621 | { FLOAT }, | |
2622 | /* e0 */ | |
bf890a93 IT |
2623 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2624 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2625 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2626 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2627 | { "inB", { AL, Ib }, 0 }, | |
2628 | { "inG", { zAX, Ib }, 0 }, | |
2629 | { "outB", { Ib, AL }, 0 }, | |
2630 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2631 | /* e8 */ |
a72d2af2 L |
2632 | { X86_64_TABLE (X86_64_E8) }, |
2633 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2634 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2635 | { "jmp", { Jb, BND }, 0 }, |
2636 | { "inB", { AL, indirDX }, 0 }, | |
2637 | { "inG", { zAX, indirDX }, 0 }, | |
2638 | { "outB", { indirDX, AL }, 0 }, | |
2639 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2640 | /* f0 */ |
592d1631 | 2641 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2642 | { "icebp", { XX }, 0 }, |
592d1631 L |
2643 | { Bad_Opcode }, /* repne */ |
2644 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2645 | { "hlt", { XX }, 0 }, |
2646 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2647 | { REG_TABLE (REG_F6) }, |
2648 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2649 | /* f8 */ |
bf890a93 IT |
2650 | { "clc", { XX }, 0 }, |
2651 | { "stc", { XX }, 0 }, | |
2652 | { "cli", { XX }, 0 }, | |
2653 | { "sti", { XX }, 0 }, | |
2654 | { "cld", { XX }, 0 }, | |
2655 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2656 | { REG_TABLE (REG_FE) }, |
2657 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2658 | }; |
2659 | ||
6439fc28 | 2660 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2661 | /* 00 */ |
1ceb70f8 L |
2662 | { REG_TABLE (REG_0F00 ) }, |
2663 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2664 | { "larS", { Gv, Ew }, 0 }, |
2665 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2666 | { Bad_Opcode }, |
bf890a93 IT |
2667 | { "syscall", { XX }, 0 }, |
2668 | { "clts", { XX }, 0 }, | |
2669 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2670 | /* 08 */ |
bf890a93 | 2671 | { "invd", { XX }, 0 }, |
3233d7d0 | 2672 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2673 | { Bad_Opcode }, |
bf890a93 | 2674 | { "ud2", { XX }, 0 }, |
592d1631 | 2675 | { Bad_Opcode }, |
b5b1fc4f | 2676 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2677 | { "femms", { XX }, 0 }, |
2678 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2679 | /* 10 */ |
1ceb70f8 L |
2680 | { PREFIX_TABLE (PREFIX_0F10) }, |
2681 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2682 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2683 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2684 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2685 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2686 | { PREFIX_TABLE (PREFIX_0F16) }, |
2687 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2688 | /* 18 */ |
1ceb70f8 | 2689 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2690 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2691 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2692 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2693 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2694 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2695 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2696 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2697 | /* 20 */ |
bf890a93 IT |
2698 | { "movZ", { Rm, Cm }, 0 }, |
2699 | { "movZ", { Rm, Dm }, 0 }, | |
2700 | { "movZ", { Cm, Rm }, 0 }, | |
2701 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2702 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2703 | { Bad_Opcode }, |
1ceb70f8 | 2704 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2705 | { Bad_Opcode }, |
252b5132 | 2706 | /* 28 */ |
507bd325 L |
2707 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2708 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2709 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2710 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2711 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2712 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2713 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2714 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2715 | /* 30 */ |
bf890a93 IT |
2716 | { "wrmsr", { XX }, 0 }, |
2717 | { "rdtsc", { XX }, 0 }, | |
2718 | { "rdmsr", { XX }, 0 }, | |
2719 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2720 | { "sysenter", { SEP }, 0 }, |
2721 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2722 | { Bad_Opcode }, |
bf890a93 | 2723 | { "getsec", { XX }, 0 }, |
252b5132 | 2724 | /* 38 */ |
507bd325 | 2725 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2726 | { Bad_Opcode }, |
507bd325 | 2727 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2728 | { Bad_Opcode }, |
2729 | { Bad_Opcode }, | |
2730 | { Bad_Opcode }, | |
2731 | { Bad_Opcode }, | |
2732 | { Bad_Opcode }, | |
252b5132 | 2733 | /* 40 */ |
bf890a93 IT |
2734 | { "cmovoS", { Gv, Ev }, 0 }, |
2735 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2736 | { "cmovbS", { Gv, Ev }, 0 }, | |
2737 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2738 | { "cmoveS", { Gv, Ev }, 0 }, | |
2739 | { "cmovneS", { Gv, Ev }, 0 }, | |
2740 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2741 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2742 | /* 48 */ |
bf890a93 IT |
2743 | { "cmovsS", { Gv, Ev }, 0 }, |
2744 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2745 | { "cmovpS", { Gv, Ev }, 0 }, | |
2746 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2747 | { "cmovlS", { Gv, Ev }, 0 }, | |
2748 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2749 | { "cmovleS", { Gv, Ev }, 0 }, | |
2750 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2751 | /* 50 */ |
75c135a8 | 2752 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2753 | { PREFIX_TABLE (PREFIX_0F51) }, |
2754 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2755 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2756 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2757 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2758 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2759 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2760 | /* 58 */ |
1ceb70f8 L |
2761 | { PREFIX_TABLE (PREFIX_0F58) }, |
2762 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2763 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2764 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2765 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2766 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2767 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2768 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2769 | /* 60 */ |
1ceb70f8 L |
2770 | { PREFIX_TABLE (PREFIX_0F60) }, |
2771 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2772 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2773 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2774 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2775 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2776 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2777 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2778 | /* 68 */ |
507bd325 L |
2779 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2780 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2781 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2782 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2783 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2784 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2785 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2786 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2787 | /* 70 */ |
1ceb70f8 L |
2788 | { PREFIX_TABLE (PREFIX_0F70) }, |
2789 | { REG_TABLE (REG_0F71) }, | |
2790 | { REG_TABLE (REG_0F72) }, | |
2791 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2792 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2793 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2794 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2795 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2796 | /* 78 */ |
1ceb70f8 L |
2797 | { PREFIX_TABLE (PREFIX_0F78) }, |
2798 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2799 | { Bad_Opcode }, |
592d1631 | 2800 | { Bad_Opcode }, |
1ceb70f8 L |
2801 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2802 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2803 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2804 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2805 | /* 80 */ |
bf890a93 IT |
2806 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2807 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2808 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2809 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2810 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2811 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2812 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2813 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2814 | /* 88 */ |
bf890a93 IT |
2815 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2816 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2817 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2818 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2819 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2820 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2821 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2822 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2823 | /* 90 */ |
bf890a93 IT |
2824 | { "seto", { Eb }, 0 }, |
2825 | { "setno", { Eb }, 0 }, | |
2826 | { "setb", { Eb }, 0 }, | |
2827 | { "setae", { Eb }, 0 }, | |
2828 | { "sete", { Eb }, 0 }, | |
2829 | { "setne", { Eb }, 0 }, | |
2830 | { "setbe", { Eb }, 0 }, | |
2831 | { "seta", { Eb }, 0 }, | |
252b5132 | 2832 | /* 98 */ |
bf890a93 IT |
2833 | { "sets", { Eb }, 0 }, |
2834 | { "setns", { Eb }, 0 }, | |
2835 | { "setp", { Eb }, 0 }, | |
2836 | { "setnp", { Eb }, 0 }, | |
2837 | { "setl", { Eb }, 0 }, | |
2838 | { "setge", { Eb }, 0 }, | |
2839 | { "setle", { Eb }, 0 }, | |
2840 | { "setg", { Eb }, 0 }, | |
252b5132 | 2841 | /* a0 */ |
bf890a93 IT |
2842 | { "pushT", { fs }, 0 }, |
2843 | { "popT", { fs }, 0 }, | |
2844 | { "cpuid", { XX }, 0 }, | |
2845 | { "btS", { Ev, Gv }, 0 }, | |
2846 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2847 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2848 | { REG_TABLE (REG_0FA6) }, |
2849 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2850 | /* a8 */ |
bf890a93 IT |
2851 | { "pushT", { gs }, 0 }, |
2852 | { "popT", { gs }, 0 }, | |
2853 | { "rsm", { XX }, 0 }, | |
2854 | { "btsS", { Evh1, Gv }, 0 }, | |
2855 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2856 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2857 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2858 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2859 | /* b0 */ |
bf890a93 IT |
2860 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2861 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2862 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2863 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2864 | { MOD_TABLE (MOD_0FB4) }, |
2865 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2866 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2867 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2868 | /* b8 */ |
1ceb70f8 | 2869 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2870 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2871 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2872 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2873 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2874 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2875 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2876 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2877 | /* c0 */ |
bf890a93 IT |
2878 | { "xaddB", { Ebh1, Gb }, 0 }, |
2879 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2880 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2881 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2882 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2883 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2884 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2885 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2886 | /* c8 */ |
bf890a93 IT |
2887 | { "bswap", { RMeAX }, 0 }, |
2888 | { "bswap", { RMeCX }, 0 }, | |
2889 | { "bswap", { RMeDX }, 0 }, | |
2890 | { "bswap", { RMeBX }, 0 }, | |
2891 | { "bswap", { RMeSP }, 0 }, | |
2892 | { "bswap", { RMeBP }, 0 }, | |
2893 | { "bswap", { RMeSI }, 0 }, | |
2894 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2895 | /* d0 */ |
1ceb70f8 | 2896 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2897 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2898 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2899 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2900 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2901 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2902 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2903 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2904 | /* d8 */ |
507bd325 L |
2905 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2906 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2907 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2908 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2909 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2910 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2911 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2912 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2913 | /* e0 */ |
507bd325 L |
2914 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2915 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2916 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2917 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2918 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2919 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2920 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2921 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2922 | /* e8 */ |
507bd325 L |
2923 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2924 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2925 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2926 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2927 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2928 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2929 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2930 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2931 | /* f0 */ |
1ceb70f8 | 2932 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2933 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2934 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2935 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2936 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2937 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2938 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2939 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2940 | /* f8 */ |
507bd325 L |
2941 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2942 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2943 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2944 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2945 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2946 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2947 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2948 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2949 | }; |
2950 | ||
2951 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2952 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2953 | /* ------------------------------- */ | |
2954 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2955 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2956 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2957 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2958 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2959 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2960 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2961 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2962 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2963 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2964 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2965 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2966 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2967 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2968 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2969 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2970 | /* ------------------------------- */ | |
2971 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2972 | }; |
2973 | ||
2974 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2975 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2976 | /* ------------------------------- */ | |
252b5132 | 2977 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2978 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2979 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2980 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2981 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2982 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2983 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2984 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2985 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2986 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2987 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2988 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2989 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2990 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2991 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2992 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2993 | /* ------------------------------- */ |
2994 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2995 | }; | |
2996 | ||
252b5132 RH |
2997 | static char obuf[100]; |
2998 | static char *obufp; | |
ea397f5b | 2999 | static char *mnemonicendp; |
252b5132 RH |
3000 | static char scratchbuf[100]; |
3001 | static unsigned char *start_codep; | |
3002 | static unsigned char *insn_codep; | |
3003 | static unsigned char *codep; | |
285ca992 | 3004 | static unsigned char *end_codep; |
f16cd0d5 L |
3005 | static int last_lock_prefix; |
3006 | static int last_repz_prefix; | |
3007 | static int last_repnz_prefix; | |
3008 | static int last_data_prefix; | |
3009 | static int last_addr_prefix; | |
3010 | static int last_rex_prefix; | |
3011 | static int last_seg_prefix; | |
d9949a36 | 3012 | static int fwait_prefix; |
285ca992 L |
3013 | /* The active segment register prefix. */ |
3014 | static int active_seg_prefix; | |
f16cd0d5 L |
3015 | #define MAX_CODE_LENGTH 15 |
3016 | /* We can up to 14 prefixes since the maximum instruction length is | |
3017 | 15bytes. */ | |
3018 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3019 | static disassemble_info *the_info; |
7967e09e L |
3020 | static struct |
3021 | { | |
3022 | int mod; | |
7967e09e | 3023 | int reg; |
484c222e | 3024 | int rm; |
7967e09e L |
3025 | } |
3026 | modrm; | |
4bba6815 | 3027 | static unsigned char need_modrm; |
dfc8cf43 L |
3028 | static struct |
3029 | { | |
3030 | int scale; | |
3031 | int index; | |
3032 | int base; | |
3033 | } | |
3034 | sib; | |
c0f3af97 L |
3035 | static struct |
3036 | { | |
3037 | int register_specifier; | |
3038 | int length; | |
3039 | int prefix; | |
3040 | int w; | |
43234a1e L |
3041 | int evex; |
3042 | int r; | |
3043 | int v; | |
3044 | int mask_register_specifier; | |
3045 | int zeroing; | |
3046 | int ll; | |
3047 | int b; | |
c0f3af97 L |
3048 | } |
3049 | vex; | |
3050 | static unsigned char need_vex; | |
3051 | static unsigned char need_vex_reg; | |
dae39acc | 3052 | static unsigned char vex_w_done; |
252b5132 | 3053 | |
ea397f5b L |
3054 | struct op |
3055 | { | |
3056 | const char *name; | |
3057 | unsigned int len; | |
3058 | }; | |
3059 | ||
4bba6815 AM |
3060 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3061 | values are stale. Hitting this abort likely indicates that you | |
3062 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3063 | #define MODRM_CHECK if (!need_modrm) abort () | |
3064 | ||
d708bcba AM |
3065 | static const char **names64; |
3066 | static const char **names32; | |
3067 | static const char **names16; | |
3068 | static const char **names8; | |
3069 | static const char **names8rex; | |
3070 | static const char **names_seg; | |
db51cc60 L |
3071 | static const char *index64; |
3072 | static const char *index32; | |
d708bcba | 3073 | static const char **index16; |
7e8b059b | 3074 | static const char **names_bnd; |
d708bcba AM |
3075 | |
3076 | static const char *intel_names64[] = { | |
3077 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3078 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3079 | }; | |
3080 | static const char *intel_names32[] = { | |
3081 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3082 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3083 | }; | |
3084 | static const char *intel_names16[] = { | |
3085 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3086 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3087 | }; | |
3088 | static const char *intel_names8[] = { | |
3089 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3090 | }; | |
3091 | static const char *intel_names8rex[] = { | |
3092 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3093 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3094 | }; | |
3095 | static const char *intel_names_seg[] = { | |
3096 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3097 | }; | |
db51cc60 L |
3098 | static const char *intel_index64 = "riz"; |
3099 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3100 | static const char *intel_index16[] = { |
3101 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3102 | }; | |
3103 | ||
3104 | static const char *att_names64[] = { | |
3105 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3106 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3107 | }; | |
d708bcba AM |
3108 | static const char *att_names32[] = { |
3109 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3110 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3111 | }; |
d708bcba AM |
3112 | static const char *att_names16[] = { |
3113 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3114 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3115 | }; |
d708bcba AM |
3116 | static const char *att_names8[] = { |
3117 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3118 | }; |
d708bcba AM |
3119 | static const char *att_names8rex[] = { |
3120 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3121 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3122 | }; | |
d708bcba AM |
3123 | static const char *att_names_seg[] = { |
3124 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3125 | }; |
db51cc60 L |
3126 | static const char *att_index64 = "%riz"; |
3127 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3128 | static const char *att_index16[] = { |
3129 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3130 | }; |
3131 | ||
b9733481 L |
3132 | static const char **names_mm; |
3133 | static const char *intel_names_mm[] = { | |
3134 | "mm0", "mm1", "mm2", "mm3", | |
3135 | "mm4", "mm5", "mm6", "mm7" | |
3136 | }; | |
3137 | static const char *att_names_mm[] = { | |
3138 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3139 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3140 | }; | |
3141 | ||
7e8b059b L |
3142 | static const char *intel_names_bnd[] = { |
3143 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3144 | }; | |
3145 | ||
3146 | static const char *att_names_bnd[] = { | |
3147 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3148 | }; | |
3149 | ||
b9733481 L |
3150 | static const char **names_xmm; |
3151 | static const char *intel_names_xmm[] = { | |
3152 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3153 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3154 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3155 | "xmm12", "xmm13", "xmm14", "xmm15", |
3156 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3157 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3158 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3159 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3160 | }; |
3161 | static const char *att_names_xmm[] = { | |
3162 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3163 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3164 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3165 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3166 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3167 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3168 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3169 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3170 | }; |
3171 | ||
3172 | static const char **names_ymm; | |
3173 | static const char *intel_names_ymm[] = { | |
3174 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3175 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3176 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3177 | "ymm12", "ymm13", "ymm14", "ymm15", |
3178 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3179 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3180 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3181 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3182 | }; |
3183 | static const char *att_names_ymm[] = { | |
3184 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3185 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3186 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3187 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3188 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3189 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3190 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3191 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3192 | }; | |
3193 | ||
3194 | static const char **names_zmm; | |
3195 | static const char *intel_names_zmm[] = { | |
3196 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3197 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3198 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3199 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3200 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3201 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3202 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3203 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3204 | }; | |
3205 | static const char *att_names_zmm[] = { | |
3206 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3207 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3208 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3209 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3210 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3211 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3212 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3213 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3214 | }; | |
3215 | ||
3216 | static const char **names_mask; | |
3217 | static const char *intel_names_mask[] = { | |
3218 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3219 | }; | |
3220 | static const char *att_names_mask[] = { | |
3221 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3222 | }; | |
3223 | ||
3224 | static const char *names_rounding[] = | |
3225 | { | |
3226 | "{rn-sae}", | |
3227 | "{rd-sae}", | |
3228 | "{ru-sae}", | |
3229 | "{rz-sae}" | |
b9733481 L |
3230 | }; |
3231 | ||
1ceb70f8 L |
3232 | static const struct dis386 reg_table[][8] = { |
3233 | /* REG_80 */ | |
252b5132 | 3234 | { |
bf890a93 IT |
3235 | { "addA", { Ebh1, Ib }, 0 }, |
3236 | { "orA", { Ebh1, Ib }, 0 }, | |
3237 | { "adcA", { Ebh1, Ib }, 0 }, | |
3238 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3239 | { "andA", { Ebh1, Ib }, 0 }, | |
3240 | { "subA", { Ebh1, Ib }, 0 }, | |
3241 | { "xorA", { Ebh1, Ib }, 0 }, | |
3242 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3243 | }, |
1ceb70f8 | 3244 | /* REG_81 */ |
252b5132 | 3245 | { |
bf890a93 IT |
3246 | { "addQ", { Evh1, Iv }, 0 }, |
3247 | { "orQ", { Evh1, Iv }, 0 }, | |
3248 | { "adcQ", { Evh1, Iv }, 0 }, | |
3249 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3250 | { "andQ", { Evh1, Iv }, 0 }, | |
3251 | { "subQ", { Evh1, Iv }, 0 }, | |
3252 | { "xorQ", { Evh1, Iv }, 0 }, | |
3253 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3254 | }, |
7148c369 | 3255 | /* REG_83 */ |
252b5132 | 3256 | { |
bf890a93 IT |
3257 | { "addQ", { Evh1, sIb }, 0 }, |
3258 | { "orQ", { Evh1, sIb }, 0 }, | |
3259 | { "adcQ", { Evh1, sIb }, 0 }, | |
3260 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3261 | { "andQ", { Evh1, sIb }, 0 }, | |
3262 | { "subQ", { Evh1, sIb }, 0 }, | |
3263 | { "xorQ", { Evh1, sIb }, 0 }, | |
3264 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3265 | }, |
1ceb70f8 | 3266 | /* REG_8F */ |
4e7d34a6 | 3267 | { |
bf890a93 | 3268 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3269 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3270 | { Bad_Opcode }, |
3271 | { Bad_Opcode }, | |
3272 | { Bad_Opcode }, | |
f88c9eb0 | 3273 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3274 | }, |
1ceb70f8 | 3275 | /* REG_C0 */ |
252b5132 | 3276 | { |
bf890a93 IT |
3277 | { "rolA", { Eb, Ib }, 0 }, |
3278 | { "rorA", { Eb, Ib }, 0 }, | |
3279 | { "rclA", { Eb, Ib }, 0 }, | |
3280 | { "rcrA", { Eb, Ib }, 0 }, | |
3281 | { "shlA", { Eb, Ib }, 0 }, | |
3282 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3283 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3284 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3285 | }, |
1ceb70f8 | 3286 | /* REG_C1 */ |
252b5132 | 3287 | { |
bf890a93 IT |
3288 | { "rolQ", { Ev, Ib }, 0 }, |
3289 | { "rorQ", { Ev, Ib }, 0 }, | |
3290 | { "rclQ", { Ev, Ib }, 0 }, | |
3291 | { "rcrQ", { Ev, Ib }, 0 }, | |
3292 | { "shlQ", { Ev, Ib }, 0 }, | |
3293 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3294 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3295 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3296 | }, |
1ceb70f8 | 3297 | /* REG_C6 */ |
4e7d34a6 | 3298 | { |
bf890a93 | 3299 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3300 | { Bad_Opcode }, |
3301 | { Bad_Opcode }, | |
3302 | { Bad_Opcode }, | |
3303 | { Bad_Opcode }, | |
3304 | { Bad_Opcode }, | |
3305 | { Bad_Opcode }, | |
3306 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3307 | }, |
1ceb70f8 | 3308 | /* REG_C7 */ |
4e7d34a6 | 3309 | { |
bf890a93 | 3310 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3311 | { Bad_Opcode }, |
3312 | { Bad_Opcode }, | |
3313 | { Bad_Opcode }, | |
3314 | { Bad_Opcode }, | |
3315 | { Bad_Opcode }, | |
3316 | { Bad_Opcode }, | |
3317 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3318 | }, |
1ceb70f8 | 3319 | /* REG_D0 */ |
252b5132 | 3320 | { |
bf890a93 IT |
3321 | { "rolA", { Eb, I1 }, 0 }, |
3322 | { "rorA", { Eb, I1 }, 0 }, | |
3323 | { "rclA", { Eb, I1 }, 0 }, | |
3324 | { "rcrA", { Eb, I1 }, 0 }, | |
3325 | { "shlA", { Eb, I1 }, 0 }, | |
3326 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3327 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3328 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3329 | }, |
1ceb70f8 | 3330 | /* REG_D1 */ |
252b5132 | 3331 | { |
bf890a93 IT |
3332 | { "rolQ", { Ev, I1 }, 0 }, |
3333 | { "rorQ", { Ev, I1 }, 0 }, | |
3334 | { "rclQ", { Ev, I1 }, 0 }, | |
3335 | { "rcrQ", { Ev, I1 }, 0 }, | |
3336 | { "shlQ", { Ev, I1 }, 0 }, | |
3337 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3338 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3339 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_D2 */ |
252b5132 | 3342 | { |
bf890a93 IT |
3343 | { "rolA", { Eb, CL }, 0 }, |
3344 | { "rorA", { Eb, CL }, 0 }, | |
3345 | { "rclA", { Eb, CL }, 0 }, | |
3346 | { "rcrA", { Eb, CL }, 0 }, | |
3347 | { "shlA", { Eb, CL }, 0 }, | |
3348 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3349 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3350 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3351 | }, |
1ceb70f8 | 3352 | /* REG_D3 */ |
252b5132 | 3353 | { |
bf890a93 IT |
3354 | { "rolQ", { Ev, CL }, 0 }, |
3355 | { "rorQ", { Ev, CL }, 0 }, | |
3356 | { "rclQ", { Ev, CL }, 0 }, | |
3357 | { "rcrQ", { Ev, CL }, 0 }, | |
3358 | { "shlQ", { Ev, CL }, 0 }, | |
3359 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3360 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3361 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3362 | }, |
1ceb70f8 | 3363 | /* REG_F6 */ |
252b5132 | 3364 | { |
bf890a93 | 3365 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3366 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3367 | { "notA", { Ebh1 }, 0 }, |
3368 | { "negA", { Ebh1 }, 0 }, | |
3369 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3370 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3371 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3372 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3373 | }, |
1ceb70f8 | 3374 | /* REG_F7 */ |
252b5132 | 3375 | { |
bf890a93 | 3376 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3377 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3378 | { "notQ", { Evh1 }, 0 }, |
3379 | { "negQ", { Evh1 }, 0 }, | |
3380 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3381 | { "imulQ", { Ev }, 0 }, | |
3382 | { "divQ", { Ev }, 0 }, | |
3383 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3384 | }, |
1ceb70f8 | 3385 | /* REG_FE */ |
252b5132 | 3386 | { |
bf890a93 IT |
3387 | { "incA", { Ebh1 }, 0 }, |
3388 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3389 | }, |
1ceb70f8 | 3390 | /* REG_FF */ |
252b5132 | 3391 | { |
bf890a93 IT |
3392 | { "incQ", { Evh1 }, 0 }, |
3393 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3394 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3395 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3396 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3397 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3398 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3399 | { Bad_Opcode }, |
252b5132 | 3400 | }, |
1ceb70f8 | 3401 | /* REG_0F00 */ |
252b5132 | 3402 | { |
bf890a93 IT |
3403 | { "sldtD", { Sv }, 0 }, |
3404 | { "strD", { Sv }, 0 }, | |
3405 | { "lldt", { Ew }, 0 }, | |
3406 | { "ltr", { Ew }, 0 }, | |
3407 | { "verr", { Ew }, 0 }, | |
3408 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3409 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, | |
252b5132 | 3411 | }, |
1ceb70f8 | 3412 | /* REG_0F01 */ |
252b5132 | 3413 | { |
1ceb70f8 L |
3414 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3415 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3416 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3417 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3418 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3419 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3420 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3421 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3422 | }, |
b5b1fc4f | 3423 | /* REG_0F0D */ |
252b5132 | 3424 | { |
bf890a93 IT |
3425 | { "prefetch", { Mb }, 0 }, |
3426 | { "prefetchw", { Mb }, 0 }, | |
3427 | { "prefetchwt1", { Mb }, 0 }, | |
3428 | { "prefetch", { Mb }, 0 }, | |
3429 | { "prefetch", { Mb }, 0 }, | |
3430 | { "prefetch", { Mb }, 0 }, | |
3431 | { "prefetch", { Mb }, 0 }, | |
3432 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3433 | }, |
1ceb70f8 | 3434 | /* REG_0F18 */ |
252b5132 | 3435 | { |
1ceb70f8 L |
3436 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3437 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3438 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3439 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3440 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3441 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3442 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3443 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3444 | }, |
f8687e93 | 3445 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3446 | { |
3447 | { "cldemote", { Mb }, 0 }, | |
3448 | { "nopQ", { Ev }, 0 }, | |
3449 | { "nopQ", { Ev }, 0 }, | |
3450 | { "nopQ", { Ev }, 0 }, | |
3451 | { "nopQ", { Ev }, 0 }, | |
3452 | { "nopQ", { Ev }, 0 }, | |
3453 | { "nopQ", { Ev }, 0 }, | |
3454 | { "nopQ", { Ev }, 0 }, | |
3455 | }, | |
f8687e93 | 3456 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3457 | { |
3458 | { "nopQ", { Ev }, 0 }, | |
3459 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3460 | { "nopQ", { Ev }, 0 }, | |
3461 | { "nopQ", { Ev }, 0 }, | |
3462 | { "nopQ", { Ev }, 0 }, | |
3463 | { "nopQ", { Ev }, 0 }, | |
3464 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3465 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3466 | }, |
1ceb70f8 | 3467 | /* REG_0F71 */ |
a6bd098c | 3468 | { |
592d1631 L |
3469 | { Bad_Opcode }, |
3470 | { Bad_Opcode }, | |
1ceb70f8 | 3471 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3472 | { Bad_Opcode }, |
1ceb70f8 | 3473 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3474 | { Bad_Opcode }, |
1ceb70f8 | 3475 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3476 | }, |
1ceb70f8 | 3477 | /* REG_0F72 */ |
a6bd098c | 3478 | { |
592d1631 L |
3479 | { Bad_Opcode }, |
3480 | { Bad_Opcode }, | |
1ceb70f8 | 3481 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3482 | { Bad_Opcode }, |
1ceb70f8 | 3483 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3484 | { Bad_Opcode }, |
1ceb70f8 | 3485 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3486 | }, |
1ceb70f8 | 3487 | /* REG_0F73 */ |
252b5132 | 3488 | { |
592d1631 L |
3489 | { Bad_Opcode }, |
3490 | { Bad_Opcode }, | |
1ceb70f8 L |
3491 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3492 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3493 | { Bad_Opcode }, |
3494 | { Bad_Opcode }, | |
1ceb70f8 L |
3495 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3496 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3497 | }, |
1ceb70f8 | 3498 | /* REG_0FA6 */ |
252b5132 | 3499 | { |
bf890a93 IT |
3500 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3501 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3502 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3503 | }, |
1ceb70f8 | 3504 | /* REG_0FA7 */ |
4e7d34a6 | 3505 | { |
bf890a93 IT |
3506 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3507 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3508 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3509 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3510 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3511 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3512 | }, |
1ceb70f8 | 3513 | /* REG_0FAE */ |
4e7d34a6 | 3514 | { |
1ceb70f8 L |
3515 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3516 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3517 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3518 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3519 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3520 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3521 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3522 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3523 | }, |
1ceb70f8 | 3524 | /* REG_0FBA */ |
252b5132 | 3525 | { |
592d1631 L |
3526 | { Bad_Opcode }, |
3527 | { Bad_Opcode }, | |
3528 | { Bad_Opcode }, | |
3529 | { Bad_Opcode }, | |
bf890a93 IT |
3530 | { "btQ", { Ev, Ib }, 0 }, |
3531 | { "btsQ", { Evh1, Ib }, 0 }, | |
3532 | { "btrQ", { Evh1, Ib }, 0 }, | |
3533 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3534 | }, |
1ceb70f8 | 3535 | /* REG_0FC7 */ |
c608c12e | 3536 | { |
592d1631 | 3537 | { Bad_Opcode }, |
bf890a93 | 3538 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3539 | { Bad_Opcode }, |
963f3586 IT |
3540 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3541 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3542 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3543 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3544 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3545 | }, |
592a252b | 3546 | /* REG_VEX_0F71 */ |
c0f3af97 | 3547 | { |
592d1631 L |
3548 | { Bad_Opcode }, |
3549 | { Bad_Opcode }, | |
592a252b | 3550 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3551 | { Bad_Opcode }, |
592a252b | 3552 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3553 | { Bad_Opcode }, |
592a252b | 3554 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3555 | }, |
592a252b | 3556 | /* REG_VEX_0F72 */ |
c0f3af97 | 3557 | { |
592d1631 L |
3558 | { Bad_Opcode }, |
3559 | { Bad_Opcode }, | |
592a252b | 3560 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3561 | { Bad_Opcode }, |
592a252b | 3562 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3563 | { Bad_Opcode }, |
592a252b | 3564 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3565 | }, |
592a252b | 3566 | /* REG_VEX_0F73 */ |
c0f3af97 | 3567 | { |
592d1631 L |
3568 | { Bad_Opcode }, |
3569 | { Bad_Opcode }, | |
592a252b L |
3570 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3571 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3572 | { Bad_Opcode }, |
3573 | { Bad_Opcode }, | |
592a252b L |
3574 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3575 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3576 | }, |
592a252b | 3577 | /* REG_VEX_0FAE */ |
c0f3af97 | 3578 | { |
592d1631 L |
3579 | { Bad_Opcode }, |
3580 | { Bad_Opcode }, | |
592a252b L |
3581 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3582 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3583 | }, |
f12dc422 L |
3584 | /* REG_VEX_0F38F3 */ |
3585 | { | |
3586 | { Bad_Opcode }, | |
3587 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3588 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3589 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3590 | }, | |
f88c9eb0 SP |
3591 | /* REG_XOP_LWPCB */ |
3592 | { | |
bf890a93 IT |
3593 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3594 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3595 | }, |
3596 | /* REG_XOP_LWP */ | |
3597 | { | |
c1dc7af5 JB |
3598 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3599 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3600 | }, |
2a2a0f38 QN |
3601 | /* REG_XOP_TBM_01 */ |
3602 | { | |
3603 | { Bad_Opcode }, | |
c1dc7af5 JB |
3604 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3605 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3606 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3607 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3608 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3609 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3610 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3611 | }, |
3612 | /* REG_XOP_TBM_02 */ | |
3613 | { | |
3614 | { Bad_Opcode }, | |
c1dc7af5 | 3615 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3616 | { Bad_Opcode }, |
3617 | { Bad_Opcode }, | |
3618 | { Bad_Opcode }, | |
3619 | { Bad_Opcode }, | |
c1dc7af5 | 3620 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3621 | }, |
ad692897 L |
3622 | |
3623 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3624 | }; |
3625 | ||
1ceb70f8 L |
3626 | static const struct dis386 prefix_table[][4] = { |
3627 | /* PREFIX_90 */ | |
252b5132 | 3628 | { |
bf890a93 IT |
3629 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3630 | { "pause", { XX }, 0 }, | |
3631 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3632 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3633 | }, |
4e7d34a6 | 3634 | |
f8687e93 | 3635 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3636 | { |
3637 | { Bad_Opcode }, | |
3638 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3639 | }, | |
3640 | ||
f8687e93 | 3641 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 L |
3642 | { |
3643 | { Bad_Opcode }, | |
2234eee6 | 3644 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3645 | }, |
3646 | ||
f8687e93 | 3647 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3648 | { |
3649 | { Bad_Opcode }, | |
c2f76402 | 3650 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3651 | }, |
3652 | ||
267b8516 JB |
3653 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3654 | { | |
3655 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3656 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3657 | }, |
3658 | ||
3659 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3660 | { | |
7abb8d81 | 3661 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3662 | }, |
3663 | ||
3233d7d0 IT |
3664 | /* PREFIX_0F09 */ |
3665 | { | |
3666 | { "wbinvd", { XX }, 0 }, | |
3667 | { "wbnoinvd", { XX }, 0 }, | |
3668 | }, | |
3669 | ||
1ceb70f8 | 3670 | /* PREFIX_0F10 */ |
cc0ec051 | 3671 | { |
507bd325 L |
3672 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3673 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3674 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3675 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3676 | }, |
4e7d34a6 | 3677 | |
1ceb70f8 | 3678 | /* PREFIX_0F11 */ |
30d1c836 | 3679 | { |
507bd325 L |
3680 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3681 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3682 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3683 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3684 | }, |
252b5132 | 3685 | |
1ceb70f8 | 3686 | /* PREFIX_0F12 */ |
c608c12e | 3687 | { |
1ceb70f8 | 3688 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3689 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3690 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3691 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3692 | }, |
4e7d34a6 | 3693 | |
1ceb70f8 | 3694 | /* PREFIX_0F16 */ |
c608c12e | 3695 | { |
1ceb70f8 | 3696 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3697 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3698 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3699 | }, |
4e7d34a6 | 3700 | |
7e8b059b L |
3701 | /* PREFIX_0F1A */ |
3702 | { | |
3703 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3704 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3705 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3706 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3707 | }, |
3708 | ||
3709 | /* PREFIX_0F1B */ | |
3710 | { | |
3711 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3712 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3713 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3714 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3715 | }, |
3716 | ||
c48935d7 IT |
3717 | /* PREFIX_0F1C */ |
3718 | { | |
3719 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3720 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3721 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3722 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3723 | }, | |
3724 | ||
603555e5 L |
3725 | /* PREFIX_0F1E */ |
3726 | { | |
3727 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3728 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3729 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3730 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3731 | }, | |
3732 | ||
1ceb70f8 | 3733 | /* PREFIX_0F2A */ |
c608c12e | 3734 | { |
507bd325 | 3735 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3736 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3737 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3738 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3739 | }, |
4e7d34a6 | 3740 | |
1ceb70f8 | 3741 | /* PREFIX_0F2B */ |
c608c12e | 3742 | { |
75c135a8 L |
3743 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3744 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3745 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3746 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3747 | }, |
4e7d34a6 | 3748 | |
1ceb70f8 | 3749 | /* PREFIX_0F2C */ |
c608c12e | 3750 | { |
507bd325 | 3751 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3752 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3753 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3754 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3755 | }, |
4e7d34a6 | 3756 | |
1ceb70f8 | 3757 | /* PREFIX_0F2D */ |
c608c12e | 3758 | { |
507bd325 | 3759 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3760 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3761 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3762 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3763 | }, |
4e7d34a6 | 3764 | |
1ceb70f8 | 3765 | /* PREFIX_0F2E */ |
c608c12e | 3766 | { |
bf890a93 | 3767 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3768 | { Bad_Opcode }, |
bf890a93 | 3769 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3770 | }, |
4e7d34a6 | 3771 | |
1ceb70f8 | 3772 | /* PREFIX_0F2F */ |
c608c12e | 3773 | { |
bf890a93 | 3774 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3775 | { Bad_Opcode }, |
bf890a93 | 3776 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3777 | }, |
4e7d34a6 | 3778 | |
1ceb70f8 | 3779 | /* PREFIX_0F51 */ |
c608c12e | 3780 | { |
507bd325 L |
3781 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3782 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3783 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3784 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3785 | }, |
4e7d34a6 | 3786 | |
1ceb70f8 | 3787 | /* PREFIX_0F52 */ |
c608c12e | 3788 | { |
507bd325 L |
3789 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3790 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3791 | }, |
4e7d34a6 | 3792 | |
1ceb70f8 | 3793 | /* PREFIX_0F53 */ |
c608c12e | 3794 | { |
507bd325 L |
3795 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3796 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3797 | }, |
4e7d34a6 | 3798 | |
1ceb70f8 | 3799 | /* PREFIX_0F58 */ |
c608c12e | 3800 | { |
507bd325 L |
3801 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3802 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3803 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3804 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3805 | }, |
4e7d34a6 | 3806 | |
1ceb70f8 | 3807 | /* PREFIX_0F59 */ |
c608c12e | 3808 | { |
507bd325 L |
3809 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3810 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3811 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3812 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3813 | }, |
4e7d34a6 | 3814 | |
1ceb70f8 | 3815 | /* PREFIX_0F5A */ |
041bd2e0 | 3816 | { |
507bd325 L |
3817 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3818 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3819 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3820 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3821 | }, |
4e7d34a6 | 3822 | |
1ceb70f8 | 3823 | /* PREFIX_0F5B */ |
041bd2e0 | 3824 | { |
507bd325 L |
3825 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3826 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3827 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3828 | }, |
4e7d34a6 | 3829 | |
1ceb70f8 | 3830 | /* PREFIX_0F5C */ |
041bd2e0 | 3831 | { |
507bd325 L |
3832 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3833 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3834 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3835 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3836 | }, |
4e7d34a6 | 3837 | |
1ceb70f8 | 3838 | /* PREFIX_0F5D */ |
041bd2e0 | 3839 | { |
507bd325 L |
3840 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3841 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3842 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3843 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3844 | }, |
4e7d34a6 | 3845 | |
1ceb70f8 | 3846 | /* PREFIX_0F5E */ |
041bd2e0 | 3847 | { |
507bd325 L |
3848 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3849 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3850 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3851 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3852 | }, |
4e7d34a6 | 3853 | |
1ceb70f8 | 3854 | /* PREFIX_0F5F */ |
041bd2e0 | 3855 | { |
507bd325 L |
3856 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3857 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3858 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3859 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F60 */ |
041bd2e0 | 3863 | { |
507bd325 | 3864 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3865 | { Bad_Opcode }, |
507bd325 | 3866 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3867 | }, |
4e7d34a6 | 3868 | |
1ceb70f8 | 3869 | /* PREFIX_0F61 */ |
041bd2e0 | 3870 | { |
507bd325 | 3871 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3872 | { Bad_Opcode }, |
507bd325 | 3873 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3874 | }, |
4e7d34a6 | 3875 | |
1ceb70f8 | 3876 | /* PREFIX_0F62 */ |
041bd2e0 | 3877 | { |
507bd325 | 3878 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3879 | { Bad_Opcode }, |
507bd325 | 3880 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3881 | }, |
4e7d34a6 | 3882 | |
1ceb70f8 | 3883 | /* PREFIX_0F6C */ |
041bd2e0 | 3884 | { |
592d1631 L |
3885 | { Bad_Opcode }, |
3886 | { Bad_Opcode }, | |
507bd325 | 3887 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3888 | }, |
4e7d34a6 | 3889 | |
1ceb70f8 | 3890 | /* PREFIX_0F6D */ |
0f17484f | 3891 | { |
592d1631 L |
3892 | { Bad_Opcode }, |
3893 | { Bad_Opcode }, | |
507bd325 | 3894 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3895 | }, |
4e7d34a6 | 3896 | |
1ceb70f8 | 3897 | /* PREFIX_0F6F */ |
ca164297 | 3898 | { |
507bd325 L |
3899 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3900 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3901 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3902 | }, |
4e7d34a6 | 3903 | |
1ceb70f8 | 3904 | /* PREFIX_0F70 */ |
4e7d34a6 | 3905 | { |
507bd325 L |
3906 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3907 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3908 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3909 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3910 | }, |
3911 | ||
92fddf8e L |
3912 | /* PREFIX_0F73_REG_3 */ |
3913 | { | |
592d1631 L |
3914 | { Bad_Opcode }, |
3915 | { Bad_Opcode }, | |
bf890a93 | 3916 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3917 | }, |
3918 | ||
3919 | /* PREFIX_0F73_REG_7 */ | |
3920 | { | |
592d1631 L |
3921 | { Bad_Opcode }, |
3922 | { Bad_Opcode }, | |
bf890a93 | 3923 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3924 | }, |
3925 | ||
1ceb70f8 | 3926 | /* PREFIX_0F78 */ |
4e7d34a6 | 3927 | { |
bf890a93 | 3928 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3929 | { Bad_Opcode }, |
bf890a93 IT |
3930 | {"extrq", { XS, Ib, Ib }, 0 }, |
3931 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3932 | }, |
3933 | ||
1ceb70f8 | 3934 | /* PREFIX_0F79 */ |
4e7d34a6 | 3935 | { |
bf890a93 | 3936 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3937 | { Bad_Opcode }, |
bf890a93 IT |
3938 | {"extrq", { XM, XS }, 0 }, |
3939 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3940 | }, |
3941 | ||
1ceb70f8 | 3942 | /* PREFIX_0F7C */ |
ca164297 | 3943 | { |
592d1631 L |
3944 | { Bad_Opcode }, |
3945 | { Bad_Opcode }, | |
507bd325 L |
3946 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3947 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3948 | }, |
4e7d34a6 | 3949 | |
1ceb70f8 | 3950 | /* PREFIX_0F7D */ |
ca164297 | 3951 | { |
592d1631 L |
3952 | { Bad_Opcode }, |
3953 | { Bad_Opcode }, | |
507bd325 L |
3954 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3955 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3956 | }, |
4e7d34a6 | 3957 | |
1ceb70f8 | 3958 | /* PREFIX_0F7E */ |
ca164297 | 3959 | { |
507bd325 L |
3960 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3961 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3962 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3963 | }, |
4e7d34a6 | 3964 | |
1ceb70f8 | 3965 | /* PREFIX_0F7F */ |
ca164297 | 3966 | { |
507bd325 L |
3967 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3968 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3969 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3970 | }, |
4e7d34a6 | 3971 | |
f8687e93 | 3972 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3973 | { |
3974 | { Bad_Opcode }, | |
bf890a93 | 3975 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3976 | }, |
3977 | ||
f8687e93 | 3978 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3979 | { |
3980 | { Bad_Opcode }, | |
bf890a93 | 3981 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3982 | }, |
3983 | ||
f8687e93 | 3984 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3985 | { |
3986 | { Bad_Opcode }, | |
bf890a93 | 3987 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3988 | }, |
3989 | ||
f8687e93 | 3990 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3991 | { |
3992 | { Bad_Opcode }, | |
bf890a93 | 3993 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3994 | }, |
3995 | ||
f8687e93 | 3996 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3997 | { |
3998 | { "xsave", { FXSAVE }, 0 }, | |
3999 | { "ptwrite%LQ", { Edq }, 0 }, | |
4000 | }, | |
4001 | ||
f8687e93 | 4002 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
4003 | { |
4004 | { Bad_Opcode }, | |
4005 | { "ptwrite%LQ", { Edq }, 0 }, | |
4006 | }, | |
4007 | ||
f8687e93 | 4008 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
4009 | { |
4010 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4011 | }, |
4012 | ||
f8687e93 | 4013 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
4014 | { |
4015 | { "lfence", { Skip_MODRM }, 0 }, | |
4016 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4017 | }, |
4018 | ||
f8687e93 | 4019 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 4020 | { |
603555e5 L |
4021 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4022 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4023 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4024 | }, |
4025 | ||
f8687e93 | 4026 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 4027 | { |
f8687e93 | 4028 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 4029 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
4030 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4031 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4032 | }, |
4033 | ||
f8687e93 | 4034 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 4035 | { |
bf890a93 | 4036 | { "clflush", { Mb }, 0 }, |
963f3586 | 4037 | { Bad_Opcode }, |
bf890a93 | 4038 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4039 | }, |
4040 | ||
1ceb70f8 | 4041 | /* PREFIX_0FB8 */ |
ca164297 | 4042 | { |
592d1631 | 4043 | { Bad_Opcode }, |
bf890a93 | 4044 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4045 | }, |
4e7d34a6 | 4046 | |
f12dc422 L |
4047 | /* PREFIX_0FBC */ |
4048 | { | |
bf890a93 IT |
4049 | { "bsfS", { Gv, Ev }, 0 }, |
4050 | { "tzcntS", { Gv, Ev }, 0 }, | |
4051 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4052 | }, |
4053 | ||
1ceb70f8 | 4054 | /* PREFIX_0FBD */ |
050dfa73 | 4055 | { |
bf890a93 IT |
4056 | { "bsrS", { Gv, Ev }, 0 }, |
4057 | { "lzcntS", { Gv, Ev }, 0 }, | |
4058 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4059 | }, |
4060 | ||
1ceb70f8 | 4061 | /* PREFIX_0FC2 */ |
050dfa73 | 4062 | { |
507bd325 L |
4063 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4064 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4065 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4066 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4067 | }, |
246c51aa | 4068 | |
f8687e93 | 4069 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4070 | { |
e1a1babd | 4071 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4072 | }, |
4073 | ||
f8687e93 | 4074 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4075 | { |
bf890a93 IT |
4076 | { "vmptrld",{ Mq }, 0 }, |
4077 | { "vmxon", { Mq }, 0 }, | |
4078 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4079 | }, |
4080 | ||
f8687e93 | 4081 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4082 | { |
4083 | { "rdrand", { Ev }, 0 }, | |
4084 | { Bad_Opcode }, | |
4085 | { "rdrand", { Ev }, 0 } | |
4086 | }, | |
4087 | ||
f8687e93 | 4088 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4089 | { |
4090 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4091 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4092 | { "rdseed", { Ev }, 0 }, |
4093 | }, | |
4094 | ||
1ceb70f8 | 4095 | /* PREFIX_0FD0 */ |
050dfa73 | 4096 | { |
592d1631 L |
4097 | { Bad_Opcode }, |
4098 | { Bad_Opcode }, | |
bf890a93 IT |
4099 | { "addsubpd", { XM, EXx }, 0 }, |
4100 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4101 | }, |
050dfa73 | 4102 | |
1ceb70f8 | 4103 | /* PREFIX_0FD6 */ |
050dfa73 | 4104 | { |
592d1631 | 4105 | { Bad_Opcode }, |
bf890a93 IT |
4106 | { "movq2dq",{ XM, MS }, 0 }, |
4107 | { "movq", { EXqS, XM }, 0 }, | |
4108 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4109 | }, |
4110 | ||
1ceb70f8 | 4111 | /* PREFIX_0FE6 */ |
7918206c | 4112 | { |
592d1631 | 4113 | { Bad_Opcode }, |
507bd325 L |
4114 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4115 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4116 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4117 | }, |
8b38ad71 | 4118 | |
1ceb70f8 | 4119 | /* PREFIX_0FE7 */ |
8b38ad71 | 4120 | { |
507bd325 | 4121 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4122 | { Bad_Opcode }, |
75c135a8 | 4123 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4124 | }, |
4125 | ||
1ceb70f8 | 4126 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4127 | { |
592d1631 L |
4128 | { Bad_Opcode }, |
4129 | { Bad_Opcode }, | |
4130 | { Bad_Opcode }, | |
1ceb70f8 | 4131 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4132 | }, |
4133 | ||
1ceb70f8 | 4134 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4135 | { |
507bd325 | 4136 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4137 | { Bad_Opcode }, |
507bd325 | 4138 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4139 | }, |
42903f7f | 4140 | |
1ceb70f8 | 4141 | /* PREFIX_0F3810 */ |
42903f7f | 4142 | { |
592d1631 L |
4143 | { Bad_Opcode }, |
4144 | { Bad_Opcode }, | |
507bd325 | 4145 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4146 | }, |
4147 | ||
1ceb70f8 | 4148 | /* PREFIX_0F3814 */ |
42903f7f | 4149 | { |
592d1631 L |
4150 | { Bad_Opcode }, |
4151 | { Bad_Opcode }, | |
507bd325 | 4152 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4153 | }, |
4154 | ||
1ceb70f8 | 4155 | /* PREFIX_0F3815 */ |
42903f7f | 4156 | { |
592d1631 L |
4157 | { Bad_Opcode }, |
4158 | { Bad_Opcode }, | |
507bd325 | 4159 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4160 | }, |
4161 | ||
1ceb70f8 | 4162 | /* PREFIX_0F3817 */ |
42903f7f | 4163 | { |
592d1631 L |
4164 | { Bad_Opcode }, |
4165 | { Bad_Opcode }, | |
507bd325 | 4166 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4167 | }, |
4168 | ||
1ceb70f8 | 4169 | /* PREFIX_0F3820 */ |
42903f7f | 4170 | { |
592d1631 L |
4171 | { Bad_Opcode }, |
4172 | { Bad_Opcode }, | |
507bd325 | 4173 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4174 | }, |
4175 | ||
1ceb70f8 | 4176 | /* PREFIX_0F3821 */ |
42903f7f | 4177 | { |
592d1631 L |
4178 | { Bad_Opcode }, |
4179 | { Bad_Opcode }, | |
507bd325 | 4180 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4181 | }, |
4182 | ||
1ceb70f8 | 4183 | /* PREFIX_0F3822 */ |
42903f7f | 4184 | { |
592d1631 L |
4185 | { Bad_Opcode }, |
4186 | { Bad_Opcode }, | |
507bd325 | 4187 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4188 | }, |
4189 | ||
1ceb70f8 | 4190 | /* PREFIX_0F3823 */ |
42903f7f | 4191 | { |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
507bd325 | 4194 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0F3824 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
507bd325 | 4201 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4202 | }, |
4203 | ||
1ceb70f8 | 4204 | /* PREFIX_0F3825 */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3828 */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3829 */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F382A */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
75c135a8 | 4229 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F382B */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
507bd325 | 4236 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3830 */ |
42903f7f | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
507bd325 | 4243 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3831 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
507bd325 | 4250 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3832 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
507bd325 | 4257 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F3833 */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
507bd325 | 4264 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F3834 */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
507bd325 | 4271 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F3835 */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
507bd325 | 4278 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
507bd325 | 4285 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F3838 */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
507bd325 | 4292 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F3839 */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
507bd325 | 4299 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F383A */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
507bd325 | 4306 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4307 | }, |
4308 | ||
1ceb70f8 | 4309 | /* PREFIX_0F383B */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F383C */ |
42903f7f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F383D */ |
42903f7f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F383E */ |
42903f7f | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F383F */ |
42903f7f | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
507bd325 | 4341 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4342 | }, |
4343 | ||
1ceb70f8 | 4344 | /* PREFIX_0F3840 */ |
42903f7f | 4345 | { |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
507bd325 | 4348 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4349 | }, |
4350 | ||
1ceb70f8 | 4351 | /* PREFIX_0F3841 */ |
42903f7f | 4352 | { |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
507bd325 | 4355 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4356 | }, |
4357 | ||
f1f8f695 L |
4358 | /* PREFIX_0F3880 */ |
4359 | { | |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
507bd325 | 4362 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4363 | }, |
4364 | ||
4365 | /* PREFIX_0F3881 */ | |
4366 | { | |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4370 | }, |
4371 | ||
6c30d220 L |
4372 | /* PREFIX_0F3882 */ |
4373 | { | |
4374 | { Bad_Opcode }, | |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4377 | }, |
4378 | ||
a0046408 L |
4379 | /* PREFIX_0F38C8 */ |
4380 | { | |
507bd325 | 4381 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4382 | }, |
4383 | ||
4384 | /* PREFIX_0F38C9 */ | |
4385 | { | |
507bd325 | 4386 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4387 | }, |
4388 | ||
4389 | /* PREFIX_0F38CA */ | |
4390 | { | |
507bd325 | 4391 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4392 | }, |
4393 | ||
4394 | /* PREFIX_0F38CB */ | |
4395 | { | |
507bd325 | 4396 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4397 | }, |
4398 | ||
4399 | /* PREFIX_0F38CC */ | |
4400 | { | |
507bd325 | 4401 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4402 | }, |
4403 | ||
4404 | /* PREFIX_0F38CD */ | |
4405 | { | |
507bd325 | 4406 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4407 | }, |
4408 | ||
48521003 IT |
4409 | /* PREFIX_0F38CF */ |
4410 | { | |
4411 | { Bad_Opcode }, | |
4412 | { Bad_Opcode }, | |
4413 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4414 | }, | |
4415 | ||
c0f3af97 L |
4416 | /* PREFIX_0F38DB */ |
4417 | { | |
592d1631 L |
4418 | { Bad_Opcode }, |
4419 | { Bad_Opcode }, | |
507bd325 | 4420 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4421 | }, |
4422 | ||
4423 | /* PREFIX_0F38DC */ | |
4424 | { | |
592d1631 L |
4425 | { Bad_Opcode }, |
4426 | { Bad_Opcode }, | |
507bd325 | 4427 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4428 | }, |
4429 | ||
4430 | /* PREFIX_0F38DD */ | |
4431 | { | |
592d1631 L |
4432 | { Bad_Opcode }, |
4433 | { Bad_Opcode }, | |
507bd325 | 4434 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4435 | }, |
4436 | ||
4437 | /* PREFIX_0F38DE */ | |
4438 | { | |
592d1631 L |
4439 | { Bad_Opcode }, |
4440 | { Bad_Opcode }, | |
507bd325 | 4441 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4442 | }, |
4443 | ||
4444 | /* PREFIX_0F38DF */ | |
4445 | { | |
592d1631 L |
4446 | { Bad_Opcode }, |
4447 | { Bad_Opcode }, | |
507bd325 | 4448 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4449 | }, |
4450 | ||
1ceb70f8 | 4451 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4452 | { |
507bd325 | 4453 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4454 | { Bad_Opcode }, |
507bd325 L |
4455 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4456 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4457 | }, |
4458 | ||
1ceb70f8 | 4459 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4460 | { |
507bd325 | 4461 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4462 | { Bad_Opcode }, |
507bd325 L |
4463 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4464 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4465 | }, |
4466 | ||
603555e5 | 4467 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4468 | { |
4469 | { Bad_Opcode }, | |
603555e5 L |
4470 | { Bad_Opcode }, |
4471 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4472 | }, | |
4473 | ||
4474 | /* PREFIX_0F38F6 */ | |
4475 | { | |
4476 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4477 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4478 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4479 | { Bad_Opcode }, |
4480 | }, | |
4481 | ||
c0a30a9f L |
4482 | /* PREFIX_0F38F8 */ |
4483 | { | |
4484 | { Bad_Opcode }, | |
5d79adc4 | 4485 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4486 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4487 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4488 | }, |
4489 | ||
4490 | /* PREFIX_0F38F9 */ | |
4491 | { | |
4492 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4493 | }, | |
4494 | ||
1ceb70f8 | 4495 | /* PREFIX_0F3A08 */ |
42903f7f | 4496 | { |
592d1631 L |
4497 | { Bad_Opcode }, |
4498 | { Bad_Opcode }, | |
507bd325 | 4499 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4500 | }, |
4501 | ||
1ceb70f8 | 4502 | /* PREFIX_0F3A09 */ |
42903f7f | 4503 | { |
592d1631 L |
4504 | { Bad_Opcode }, |
4505 | { Bad_Opcode }, | |
507bd325 | 4506 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4507 | }, |
4508 | ||
1ceb70f8 | 4509 | /* PREFIX_0F3A0A */ |
42903f7f | 4510 | { |
592d1631 L |
4511 | { Bad_Opcode }, |
4512 | { Bad_Opcode }, | |
507bd325 | 4513 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4514 | }, |
4515 | ||
1ceb70f8 | 4516 | /* PREFIX_0F3A0B */ |
42903f7f | 4517 | { |
592d1631 L |
4518 | { Bad_Opcode }, |
4519 | { Bad_Opcode }, | |
507bd325 | 4520 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4521 | }, |
4522 | ||
1ceb70f8 | 4523 | /* PREFIX_0F3A0C */ |
42903f7f | 4524 | { |
592d1631 L |
4525 | { Bad_Opcode }, |
4526 | { Bad_Opcode }, | |
507bd325 | 4527 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4528 | }, |
4529 | ||
1ceb70f8 | 4530 | /* PREFIX_0F3A0D */ |
42903f7f | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
507bd325 | 4534 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4535 | }, |
4536 | ||
1ceb70f8 | 4537 | /* PREFIX_0F3A0E */ |
42903f7f | 4538 | { |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
507bd325 | 4541 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4542 | }, |
4543 | ||
1ceb70f8 | 4544 | /* PREFIX_0F3A14 */ |
42903f7f | 4545 | { |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
507bd325 | 4548 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4549 | }, |
4550 | ||
1ceb70f8 | 4551 | /* PREFIX_0F3A15 */ |
42903f7f | 4552 | { |
592d1631 L |
4553 | { Bad_Opcode }, |
4554 | { Bad_Opcode }, | |
507bd325 | 4555 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4556 | }, |
4557 | ||
1ceb70f8 | 4558 | /* PREFIX_0F3A16 */ |
42903f7f | 4559 | { |
592d1631 L |
4560 | { Bad_Opcode }, |
4561 | { Bad_Opcode }, | |
507bd325 | 4562 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4563 | }, |
4564 | ||
1ceb70f8 | 4565 | /* PREFIX_0F3A17 */ |
42903f7f | 4566 | { |
592d1631 L |
4567 | { Bad_Opcode }, |
4568 | { Bad_Opcode }, | |
507bd325 | 4569 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4570 | }, |
4571 | ||
1ceb70f8 | 4572 | /* PREFIX_0F3A20 */ |
42903f7f | 4573 | { |
592d1631 L |
4574 | { Bad_Opcode }, |
4575 | { Bad_Opcode }, | |
507bd325 | 4576 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4577 | }, |
4578 | ||
1ceb70f8 | 4579 | /* PREFIX_0F3A21 */ |
42903f7f | 4580 | { |
592d1631 L |
4581 | { Bad_Opcode }, |
4582 | { Bad_Opcode }, | |
507bd325 | 4583 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4584 | }, |
4585 | ||
1ceb70f8 | 4586 | /* PREFIX_0F3A22 */ |
42903f7f | 4587 | { |
592d1631 L |
4588 | { Bad_Opcode }, |
4589 | { Bad_Opcode }, | |
507bd325 | 4590 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4591 | }, |
4592 | ||
1ceb70f8 | 4593 | /* PREFIX_0F3A40 */ |
42903f7f | 4594 | { |
592d1631 L |
4595 | { Bad_Opcode }, |
4596 | { Bad_Opcode }, | |
507bd325 | 4597 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4598 | }, |
4599 | ||
1ceb70f8 | 4600 | /* PREFIX_0F3A41 */ |
42903f7f | 4601 | { |
592d1631 L |
4602 | { Bad_Opcode }, |
4603 | { Bad_Opcode }, | |
507bd325 | 4604 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4605 | }, |
4606 | ||
1ceb70f8 | 4607 | /* PREFIX_0F3A42 */ |
42903f7f | 4608 | { |
592d1631 L |
4609 | { Bad_Opcode }, |
4610 | { Bad_Opcode }, | |
507bd325 | 4611 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4612 | }, |
381d071f | 4613 | |
c0f3af97 L |
4614 | /* PREFIX_0F3A44 */ |
4615 | { | |
592d1631 L |
4616 | { Bad_Opcode }, |
4617 | { Bad_Opcode }, | |
507bd325 | 4618 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4619 | }, |
4620 | ||
1ceb70f8 | 4621 | /* PREFIX_0F3A60 */ |
381d071f | 4622 | { |
592d1631 L |
4623 | { Bad_Opcode }, |
4624 | { Bad_Opcode }, | |
15c7c1d8 | 4625 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4626 | }, |
4627 | ||
1ceb70f8 | 4628 | /* PREFIX_0F3A61 */ |
381d071f | 4629 | { |
592d1631 L |
4630 | { Bad_Opcode }, |
4631 | { Bad_Opcode }, | |
15c7c1d8 | 4632 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4633 | }, |
4634 | ||
1ceb70f8 | 4635 | /* PREFIX_0F3A62 */ |
381d071f | 4636 | { |
592d1631 L |
4637 | { Bad_Opcode }, |
4638 | { Bad_Opcode }, | |
507bd325 | 4639 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4640 | }, |
4641 | ||
1ceb70f8 | 4642 | /* PREFIX_0F3A63 */ |
381d071f | 4643 | { |
592d1631 L |
4644 | { Bad_Opcode }, |
4645 | { Bad_Opcode }, | |
507bd325 | 4646 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4647 | }, |
09a2c6cf | 4648 | |
a0046408 L |
4649 | /* PREFIX_0F3ACC */ |
4650 | { | |
507bd325 | 4651 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4652 | }, |
4653 | ||
48521003 IT |
4654 | /* PREFIX_0F3ACE */ |
4655 | { | |
4656 | { Bad_Opcode }, | |
4657 | { Bad_Opcode }, | |
4658 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4659 | }, | |
4660 | ||
4661 | /* PREFIX_0F3ACF */ | |
4662 | { | |
4663 | { Bad_Opcode }, | |
4664 | { Bad_Opcode }, | |
4665 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4666 | }, | |
4667 | ||
c0f3af97 | 4668 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4669 | { |
592d1631 L |
4670 | { Bad_Opcode }, |
4671 | { Bad_Opcode }, | |
507bd325 | 4672 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4673 | }, |
4674 | ||
592a252b | 4675 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4676 | { |
ec6f095a L |
4677 | { "vmovups", { XM, EXx }, 0 }, |
4678 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4679 | { "vmovupd", { XM, EXx }, 0 }, | |
4680 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4681 | }, |
4682 | ||
592a252b | 4683 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4684 | { |
ec6f095a L |
4685 | { "vmovups", { EXxS, XM }, 0 }, |
4686 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4687 | { "vmovupd", { EXxS, XM }, 0 }, | |
4688 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4689 | }, |
4690 | ||
592a252b | 4691 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4692 | { |
592a252b | 4693 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4694 | { "vmovsldup", { XM, EXx }, 0 }, |
592a252b | 4695 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
ec6f095a | 4696 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4697 | }, |
4698 | ||
592a252b | 4699 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4700 | { |
592a252b | 4701 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4702 | { "vmovshdup", { XM, EXx }, 0 }, |
592a252b | 4703 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
5f754f58 | 4704 | }, |
7c52e0e8 | 4705 | |
592a252b | 4706 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4707 | { |
592d1631 | 4708 | { Bad_Opcode }, |
2b7bcc87 | 4709 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4710 | { Bad_Opcode }, |
2b7bcc87 | 4711 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4712 | }, |
7c52e0e8 | 4713 | |
592a252b | 4714 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4715 | { |
592d1631 | 4716 | { Bad_Opcode }, |
2b7bcc87 | 4717 | { "vcvttss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4718 | { Bad_Opcode }, |
2b7bcc87 | 4719 | { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, |
5f754f58 | 4720 | }, |
7c52e0e8 | 4721 | |
592a252b | 4722 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4723 | { |
592d1631 | 4724 | { Bad_Opcode }, |
2b7bcc87 | 4725 | { "vcvtss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4726 | { Bad_Opcode }, |
2b7bcc87 | 4727 | { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, |
7c52e0e8 L |
4728 | }, |
4729 | ||
592a252b | 4730 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4731 | { |
ec6f095a | 4732 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4733 | { Bad_Opcode }, |
ec6f095a | 4734 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4735 | }, |
4736 | ||
592a252b | 4737 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4738 | { |
ec6f095a | 4739 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4740 | { Bad_Opcode }, |
ec6f095a | 4741 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4742 | }, |
4743 | ||
43234a1e L |
4744 | /* PREFIX_VEX_0F41 */ |
4745 | { | |
4746 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4747 | { Bad_Opcode }, |
4748 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4749 | }, |
4750 | ||
4751 | /* PREFIX_VEX_0F42 */ | |
4752 | { | |
4753 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4754 | { Bad_Opcode }, |
4755 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4756 | }, |
4757 | ||
4758 | /* PREFIX_VEX_0F44 */ | |
4759 | { | |
4760 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4761 | { Bad_Opcode }, |
4762 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4763 | }, |
4764 | ||
4765 | /* PREFIX_VEX_0F45 */ | |
4766 | { | |
4767 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4768 | { Bad_Opcode }, |
4769 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4770 | }, |
4771 | ||
4772 | /* PREFIX_VEX_0F46 */ | |
4773 | { | |
4774 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4775 | { Bad_Opcode }, |
4776 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4777 | }, |
4778 | ||
4779 | /* PREFIX_VEX_0F47 */ | |
4780 | { | |
4781 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4782 | { Bad_Opcode }, |
4783 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4784 | }, |
4785 | ||
1ba585e8 | 4786 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4787 | { |
1ba585e8 | 4788 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4789 | { Bad_Opcode }, |
1ba585e8 IT |
4790 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4791 | }, | |
4792 | ||
4793 | /* PREFIX_VEX_0F4B */ | |
4794 | { | |
4795 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4796 | { Bad_Opcode }, |
4797 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4798 | }, | |
4799 | ||
592a252b | 4800 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4801 | { |
ec6f095a L |
4802 | { "vsqrtps", { XM, EXx }, 0 }, |
4803 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4804 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4805 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4806 | }, |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4809 | { |
ec6f095a L |
4810 | { "vrsqrtps", { XM, EXx }, 0 }, |
4811 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4812 | }, |
4813 | ||
592a252b | 4814 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4815 | { |
ec6f095a L |
4816 | { "vrcpps", { XM, EXx }, 0 }, |
4817 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4818 | }, |
4819 | ||
592a252b | 4820 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4821 | { |
ec6f095a L |
4822 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4823 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4824 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4825 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4826 | }, |
4827 | ||
592a252b | 4828 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4829 | { |
ec6f095a L |
4830 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4831 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4832 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4833 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4837 | { |
ec6f095a L |
4838 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4839 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4840 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4841 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4842 | }, |
4843 | ||
592a252b | 4844 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4845 | { |
ec6f095a L |
4846 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4847 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4848 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4849 | }, |
4850 | ||
592a252b | 4851 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4852 | { |
ec6f095a L |
4853 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4854 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4855 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4856 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4860 | { |
ec6f095a L |
4861 | { "vminps", { XM, Vex, EXx }, 0 }, |
4862 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4863 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4864 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4865 | }, |
4866 | ||
592a252b | 4867 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4868 | { |
ec6f095a L |
4869 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4870 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4871 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4872 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4873 | }, |
4874 | ||
592a252b | 4875 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4876 | { |
ec6f095a L |
4877 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4878 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4879 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4880 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4881 | }, |
4882 | ||
592a252b | 4883 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4884 | { |
592d1631 L |
4885 | { Bad_Opcode }, |
4886 | { Bad_Opcode }, | |
ec6f095a | 4887 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4888 | }, |
4889 | ||
592a252b | 4890 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4891 | { |
592d1631 L |
4892 | { Bad_Opcode }, |
4893 | { Bad_Opcode }, | |
ec6f095a | 4894 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4898 | { |
592d1631 L |
4899 | { Bad_Opcode }, |
4900 | { Bad_Opcode }, | |
ec6f095a | 4901 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4902 | }, |
4903 | ||
592a252b | 4904 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4905 | { |
592d1631 L |
4906 | { Bad_Opcode }, |
4907 | { Bad_Opcode }, | |
ec6f095a | 4908 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4909 | }, |
4910 | ||
592a252b | 4911 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4912 | { |
592d1631 L |
4913 | { Bad_Opcode }, |
4914 | { Bad_Opcode }, | |
ec6f095a | 4915 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4916 | }, |
4917 | ||
592a252b | 4918 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4919 | { |
592d1631 L |
4920 | { Bad_Opcode }, |
4921 | { Bad_Opcode }, | |
ec6f095a | 4922 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4923 | }, |
4924 | ||
592a252b | 4925 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4926 | { |
592d1631 L |
4927 | { Bad_Opcode }, |
4928 | { Bad_Opcode }, | |
ec6f095a | 4929 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4930 | }, |
6439fc28 | 4931 | |
592a252b | 4932 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4933 | { |
592d1631 L |
4934 | { Bad_Opcode }, |
4935 | { Bad_Opcode }, | |
ec6f095a | 4936 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4937 | }, |
4938 | ||
592a252b | 4939 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4940 | { |
592d1631 L |
4941 | { Bad_Opcode }, |
4942 | { Bad_Opcode }, | |
ec6f095a | 4943 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4944 | }, |
4945 | ||
592a252b | 4946 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4947 | { |
592d1631 L |
4948 | { Bad_Opcode }, |
4949 | { Bad_Opcode }, | |
ec6f095a | 4950 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4951 | }, |
4952 | ||
592a252b | 4953 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4954 | { |
592d1631 L |
4955 | { Bad_Opcode }, |
4956 | { Bad_Opcode }, | |
ec6f095a | 4957 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4958 | }, |
4959 | ||
592a252b | 4960 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4961 | { |
592d1631 L |
4962 | { Bad_Opcode }, |
4963 | { Bad_Opcode }, | |
ec6f095a | 4964 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4965 | }, |
4966 | ||
592a252b | 4967 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4968 | { |
592d1631 L |
4969 | { Bad_Opcode }, |
4970 | { Bad_Opcode }, | |
ec6f095a | 4971 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4972 | }, |
4973 | ||
592a252b | 4974 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4975 | { |
592d1631 L |
4976 | { Bad_Opcode }, |
4977 | { Bad_Opcode }, | |
ec6f095a | 4978 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4979 | }, |
4980 | ||
592a252b | 4981 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4982 | { |
592d1631 L |
4983 | { Bad_Opcode }, |
4984 | { Bad_Opcode }, | |
592a252b | 4985 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4986 | }, |
4987 | ||
592a252b | 4988 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4989 | { |
592d1631 | 4990 | { Bad_Opcode }, |
ec6f095a L |
4991 | { "vmovdqu", { XM, EXx }, 0 }, |
4992 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4993 | }, |
4994 | ||
592a252b | 4995 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4996 | { |
592d1631 | 4997 | { Bad_Opcode }, |
ec6f095a L |
4998 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4999 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
5000 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
5001 | }, |
5002 | ||
592a252b | 5003 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5004 | { |
592d1631 L |
5005 | { Bad_Opcode }, |
5006 | { Bad_Opcode }, | |
ec6f095a | 5007 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5008 | }, |
5009 | ||
592a252b | 5010 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5011 | { |
592d1631 L |
5012 | { Bad_Opcode }, |
5013 | { Bad_Opcode }, | |
ec6f095a | 5014 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5015 | }, |
5016 | ||
592a252b | 5017 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5018 | { |
592d1631 L |
5019 | { Bad_Opcode }, |
5020 | { Bad_Opcode }, | |
ec6f095a | 5021 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5022 | }, |
5023 | ||
592a252b | 5024 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5025 | { |
592d1631 L |
5026 | { Bad_Opcode }, |
5027 | { Bad_Opcode }, | |
ec6f095a | 5028 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5029 | }, |
5030 | ||
592a252b | 5031 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5032 | { |
592d1631 L |
5033 | { Bad_Opcode }, |
5034 | { Bad_Opcode }, | |
ec6f095a | 5035 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5036 | }, |
5037 | ||
592a252b | 5038 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5039 | { |
592d1631 L |
5040 | { Bad_Opcode }, |
5041 | { Bad_Opcode }, | |
ec6f095a | 5042 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5043 | }, |
5044 | ||
592a252b | 5045 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
ec6f095a | 5049 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5050 | }, |
5051 | ||
592a252b | 5052 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5053 | { |
592d1631 L |
5054 | { Bad_Opcode }, |
5055 | { Bad_Opcode }, | |
ec6f095a | 5056 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5057 | }, |
5058 | ||
592a252b | 5059 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5060 | { |
592d1631 L |
5061 | { Bad_Opcode }, |
5062 | { Bad_Opcode }, | |
ec6f095a | 5063 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5064 | }, |
5065 | ||
592a252b | 5066 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5067 | { |
592d1631 L |
5068 | { Bad_Opcode }, |
5069 | { Bad_Opcode }, | |
ec6f095a | 5070 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
ec6f095a | 5077 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5081 | { |
592d1631 L |
5082 | { Bad_Opcode }, |
5083 | { Bad_Opcode }, | |
ec6f095a | 5084 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5085 | }, |
5086 | ||
592a252b | 5087 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5088 | { |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
ec6f095a | 5091 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5092 | }, |
5093 | ||
592a252b | 5094 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5095 | { |
ec6f095a | 5096 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5097 | }, |
5098 | ||
592a252b | 5099 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5100 | { |
592d1631 L |
5101 | { Bad_Opcode }, |
5102 | { Bad_Opcode }, | |
ec6f095a L |
5103 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5104 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5105 | }, |
5106 | ||
592a252b | 5107 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5108 | { |
592d1631 L |
5109 | { Bad_Opcode }, |
5110 | { Bad_Opcode }, | |
ec6f095a L |
5111 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5112 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5113 | }, |
5114 | ||
592a252b | 5115 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5116 | { |
592d1631 | 5117 | { Bad_Opcode }, |
592a252b L |
5118 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5119 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5123 | { |
592d1631 | 5124 | { Bad_Opcode }, |
ec6f095a L |
5125 | { "vmovdqu", { EXxS, XM }, 0 }, |
5126 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5127 | }, |
5128 | ||
43234a1e L |
5129 | /* PREFIX_VEX_0F90 */ |
5130 | { | |
5131 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5132 | { Bad_Opcode }, |
5133 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5134 | }, |
5135 | ||
5136 | /* PREFIX_VEX_0F91 */ | |
5137 | { | |
5138 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5139 | { Bad_Opcode }, |
5140 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5141 | }, |
5142 | ||
5143 | /* PREFIX_VEX_0F92 */ | |
5144 | { | |
5145 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5146 | { Bad_Opcode }, |
90a915bf | 5147 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5148 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5149 | }, |
5150 | ||
5151 | /* PREFIX_VEX_0F93 */ | |
5152 | { | |
5153 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5154 | { Bad_Opcode }, |
90a915bf | 5155 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5156 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5157 | }, |
5158 | ||
5159 | /* PREFIX_VEX_0F98 */ | |
5160 | { | |
5161 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5162 | { Bad_Opcode }, |
5163 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5164 | }, | |
5165 | ||
5166 | /* PREFIX_VEX_0F99 */ | |
5167 | { | |
5168 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5169 | { Bad_Opcode }, | |
5170 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5171 | }, |
5172 | ||
592a252b | 5173 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5174 | { |
ec6f095a L |
5175 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5176 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5177 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5178 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5179 | }, |
5180 | ||
592a252b | 5181 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5182 | { |
592d1631 L |
5183 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, | |
592a252b | 5185 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5186 | }, |
5187 | ||
592a252b | 5188 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5189 | { |
592d1631 L |
5190 | { Bad_Opcode }, |
5191 | { Bad_Opcode }, | |
592a252b | 5192 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5193 | }, |
5194 | ||
592a252b | 5195 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5196 | { |
592d1631 L |
5197 | { Bad_Opcode }, |
5198 | { Bad_Opcode }, | |
ec6f095a L |
5199 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5200 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5201 | }, |
5202 | ||
592a252b | 5203 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5204 | { |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
ec6f095a | 5207 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5208 | }, |
5209 | ||
592a252b | 5210 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5211 | { |
592d1631 L |
5212 | { Bad_Opcode }, |
5213 | { Bad_Opcode }, | |
ec6f095a | 5214 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5215 | }, |
5216 | ||
592a252b | 5217 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5218 | { |
592d1631 L |
5219 | { Bad_Opcode }, |
5220 | { Bad_Opcode }, | |
ec6f095a | 5221 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5222 | }, |
5223 | ||
592a252b | 5224 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5225 | { |
592d1631 L |
5226 | { Bad_Opcode }, |
5227 | { Bad_Opcode }, | |
ec6f095a | 5228 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5229 | }, |
5230 | ||
592a252b | 5231 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5232 | { |
592d1631 L |
5233 | { Bad_Opcode }, |
5234 | { Bad_Opcode }, | |
ec6f095a | 5235 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5236 | }, |
5237 | ||
592a252b | 5238 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5239 | { |
592d1631 L |
5240 | { Bad_Opcode }, |
5241 | { Bad_Opcode }, | |
592a252b | 5242 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5243 | }, |
5244 | ||
592a252b | 5245 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5246 | { |
592d1631 L |
5247 | { Bad_Opcode }, |
5248 | { Bad_Opcode }, | |
592a252b | 5249 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5250 | }, |
5251 | ||
592a252b | 5252 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5253 | { |
592d1631 L |
5254 | { Bad_Opcode }, |
5255 | { Bad_Opcode }, | |
ec6f095a | 5256 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5257 | }, |
5258 | ||
592a252b | 5259 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5260 | { |
592d1631 L |
5261 | { Bad_Opcode }, |
5262 | { Bad_Opcode }, | |
ec6f095a | 5263 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5264 | }, |
5265 | ||
592a252b | 5266 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5267 | { |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
ec6f095a | 5270 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5271 | }, |
5272 | ||
592a252b | 5273 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5274 | { |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
ec6f095a | 5277 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5278 | }, |
5279 | ||
592a252b | 5280 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5281 | { |
592d1631 L |
5282 | { Bad_Opcode }, |
5283 | { Bad_Opcode }, | |
ec6f095a | 5284 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5285 | }, |
5286 | ||
592a252b | 5287 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5288 | { |
592d1631 L |
5289 | { Bad_Opcode }, |
5290 | { Bad_Opcode }, | |
ec6f095a | 5291 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5292 | }, |
5293 | ||
592a252b | 5294 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5295 | { |
592d1631 L |
5296 | { Bad_Opcode }, |
5297 | { Bad_Opcode }, | |
ec6f095a | 5298 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5299 | }, |
5300 | ||
592a252b | 5301 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5302 | { |
592d1631 L |
5303 | { Bad_Opcode }, |
5304 | { Bad_Opcode }, | |
ec6f095a | 5305 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5306 | }, |
5307 | ||
592a252b | 5308 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5309 | { |
592d1631 L |
5310 | { Bad_Opcode }, |
5311 | { Bad_Opcode }, | |
ec6f095a | 5312 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5313 | }, |
5314 | ||
592a252b | 5315 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5316 | { |
592d1631 L |
5317 | { Bad_Opcode }, |
5318 | { Bad_Opcode }, | |
ec6f095a | 5319 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5320 | }, |
5321 | ||
592a252b | 5322 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5323 | { |
592d1631 L |
5324 | { Bad_Opcode }, |
5325 | { Bad_Opcode }, | |
ec6f095a | 5326 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5327 | }, |
5328 | ||
592a252b | 5329 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5330 | { |
592d1631 L |
5331 | { Bad_Opcode }, |
5332 | { Bad_Opcode }, | |
ec6f095a | 5333 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5334 | }, |
5335 | ||
592a252b | 5336 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5337 | { |
592d1631 L |
5338 | { Bad_Opcode }, |
5339 | { Bad_Opcode }, | |
ec6f095a | 5340 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5341 | }, |
5342 | ||
592a252b | 5343 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5344 | { |
592d1631 L |
5345 | { Bad_Opcode }, |
5346 | { Bad_Opcode }, | |
ec6f095a | 5347 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5348 | }, |
5349 | ||
592a252b | 5350 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5351 | { |
592d1631 | 5352 | { Bad_Opcode }, |
ec6f095a L |
5353 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5354 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5355 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
592a252b | 5362 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
ec6f095a | 5369 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5373 | { |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
ec6f095a | 5376 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5377 | }, |
5378 | ||
592a252b | 5379 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5380 | { |
592d1631 L |
5381 | { Bad_Opcode }, |
5382 | { Bad_Opcode }, | |
ec6f095a | 5383 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5384 | }, |
5385 | ||
592a252b | 5386 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5387 | { |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
ec6f095a | 5390 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
ec6f095a | 5397 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
ec6f095a | 5404 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5405 | }, |
5406 | ||
592a252b | 5407 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5408 | { |
592d1631 L |
5409 | { Bad_Opcode }, |
5410 | { Bad_Opcode }, | |
ec6f095a | 5411 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5412 | }, |
5413 | ||
592a252b | 5414 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5415 | { |
592d1631 L |
5416 | { Bad_Opcode }, |
5417 | { Bad_Opcode }, | |
ec6f095a | 5418 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5419 | }, |
5420 | ||
592a252b | 5421 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5422 | { |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
5425 | { Bad_Opcode }, | |
592a252b | 5426 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
ec6f095a | 5433 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
ec6f095a | 5440 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
ec6f095a | 5447 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
ec6f095a | 5454 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
ec6f095a | 5461 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
ec6f095a | 5468 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
592a252b | 5475 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
ec6f095a | 5482 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5483 | }, |
5484 | ||
592a252b | 5485 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5486 | { |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
ec6f095a | 5489 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5490 | }, |
5491 | ||
592a252b | 5492 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5493 | { |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
ec6f095a | 5496 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5497 | }, |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
ec6f095a | 5503 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5504 | }, |
5505 | ||
592a252b | 5506 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5507 | { |
592d1631 L |
5508 | { Bad_Opcode }, |
5509 | { Bad_Opcode }, | |
ec6f095a | 5510 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
ec6f095a | 5517 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
ec6f095a | 5524 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
ec6f095a | 5531 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
ec6f095a | 5538 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
ec6f095a | 5545 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
ec6f095a | 5552 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5556 | { |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
ec6f095a | 5559 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5560 | }, |
5561 | ||
592a252b | 5562 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5563 | { |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
ec6f095a | 5566 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5567 | }, |
5568 | ||
592a252b | 5569 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5570 | { |
592d1631 L |
5571 | { Bad_Opcode }, |
5572 | { Bad_Opcode }, | |
ec6f095a | 5573 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5574 | }, |
5575 | ||
592a252b | 5576 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5577 | { |
592d1631 L |
5578 | { Bad_Opcode }, |
5579 | { Bad_Opcode }, | |
ec6f095a | 5580 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5581 | }, |
5582 | ||
592a252b | 5583 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5584 | { |
592d1631 L |
5585 | { Bad_Opcode }, |
5586 | { Bad_Opcode }, | |
ec6f095a | 5587 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5588 | }, |
5589 | ||
592a252b | 5590 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5591 | { |
592d1631 L |
5592 | { Bad_Opcode }, |
5593 | { Bad_Opcode }, | |
ec6f095a | 5594 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5595 | }, |
5596 | ||
592a252b | 5597 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5598 | { |
592d1631 L |
5599 | { Bad_Opcode }, |
5600 | { Bad_Opcode }, | |
ec6f095a | 5601 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5602 | }, |
5603 | ||
592a252b | 5604 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5605 | { |
592d1631 L |
5606 | { Bad_Opcode }, |
5607 | { Bad_Opcode }, | |
ec6f095a | 5608 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5609 | }, |
5610 | ||
592a252b | 5611 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5612 | { |
592d1631 L |
5613 | { Bad_Opcode }, |
5614 | { Bad_Opcode }, | |
592a252b | 5615 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5616 | }, |
5617 | ||
592a252b | 5618 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5619 | { |
592d1631 L |
5620 | { Bad_Opcode }, |
5621 | { Bad_Opcode }, | |
592a252b | 5622 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5623 | }, |
5624 | ||
592a252b | 5625 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5626 | { |
592d1631 L |
5627 | { Bad_Opcode }, |
5628 | { Bad_Opcode }, | |
592a252b | 5629 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5630 | }, |
5631 | ||
592a252b | 5632 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5633 | { |
592d1631 L |
5634 | { Bad_Opcode }, |
5635 | { Bad_Opcode }, | |
592a252b | 5636 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5637 | }, |
5638 | ||
592a252b | 5639 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5640 | { |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
bf890a93 | 5643 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5644 | }, |
5645 | ||
6c30d220 L |
5646 | /* PREFIX_VEX_0F3816 */ |
5647 | { | |
5648 | { Bad_Opcode }, | |
5649 | { Bad_Opcode }, | |
5650 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5651 | }, | |
5652 | ||
592a252b | 5653 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5654 | { |
592d1631 L |
5655 | { Bad_Opcode }, |
5656 | { Bad_Opcode }, | |
ec6f095a | 5657 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5658 | }, |
5659 | ||
592a252b | 5660 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5661 | { |
592d1631 L |
5662 | { Bad_Opcode }, |
5663 | { Bad_Opcode }, | |
6c30d220 | 5664 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5665 | }, |
5666 | ||
592a252b | 5667 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5668 | { |
592d1631 L |
5669 | { Bad_Opcode }, |
5670 | { Bad_Opcode }, | |
6c30d220 | 5671 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5672 | }, |
5673 | ||
592a252b | 5674 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5675 | { |
592d1631 L |
5676 | { Bad_Opcode }, |
5677 | { Bad_Opcode }, | |
592a252b | 5678 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5679 | }, |
5680 | ||
592a252b | 5681 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5682 | { |
592d1631 L |
5683 | { Bad_Opcode }, |
5684 | { Bad_Opcode }, | |
ec6f095a | 5685 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5686 | }, |
5687 | ||
592a252b | 5688 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5689 | { |
592d1631 L |
5690 | { Bad_Opcode }, |
5691 | { Bad_Opcode }, | |
ec6f095a | 5692 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5693 | }, |
5694 | ||
592a252b | 5695 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5696 | { |
592d1631 L |
5697 | { Bad_Opcode }, |
5698 | { Bad_Opcode }, | |
ec6f095a | 5699 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5700 | }, |
5701 | ||
592a252b | 5702 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5703 | { |
592d1631 L |
5704 | { Bad_Opcode }, |
5705 | { Bad_Opcode }, | |
ec6f095a | 5706 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5707 | }, |
5708 | ||
592a252b | 5709 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5710 | { |
592d1631 L |
5711 | { Bad_Opcode }, |
5712 | { Bad_Opcode }, | |
ec6f095a | 5713 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5714 | }, |
5715 | ||
592a252b | 5716 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5717 | { |
592d1631 L |
5718 | { Bad_Opcode }, |
5719 | { Bad_Opcode }, | |
ec6f095a | 5720 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5721 | }, |
5722 | ||
592a252b | 5723 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5724 | { |
592d1631 L |
5725 | { Bad_Opcode }, |
5726 | { Bad_Opcode }, | |
ec6f095a | 5727 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5728 | }, |
5729 | ||
592a252b | 5730 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5731 | { |
592d1631 L |
5732 | { Bad_Opcode }, |
5733 | { Bad_Opcode }, | |
ec6f095a | 5734 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5735 | }, |
5736 | ||
592a252b | 5737 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5738 | { |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
ec6f095a | 5741 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5742 | }, |
5743 | ||
592a252b | 5744 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5745 | { |
592d1631 L |
5746 | { Bad_Opcode }, |
5747 | { Bad_Opcode }, | |
ec6f095a | 5748 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5749 | }, |
5750 | ||
592a252b | 5751 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5752 | { |
592d1631 L |
5753 | { Bad_Opcode }, |
5754 | { Bad_Opcode }, | |
ec6f095a | 5755 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5756 | }, |
5757 | ||
592a252b | 5758 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5759 | { |
592d1631 L |
5760 | { Bad_Opcode }, |
5761 | { Bad_Opcode }, | |
592a252b | 5762 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5763 | }, |
5764 | ||
592a252b | 5765 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5766 | { |
592d1631 L |
5767 | { Bad_Opcode }, |
5768 | { Bad_Opcode }, | |
ec6f095a | 5769 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5770 | }, |
5771 | ||
592a252b | 5772 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5773 | { |
592d1631 L |
5774 | { Bad_Opcode }, |
5775 | { Bad_Opcode }, | |
592a252b | 5776 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5777 | }, |
5778 | ||
592a252b | 5779 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5780 | { |
592d1631 L |
5781 | { Bad_Opcode }, |
5782 | { Bad_Opcode }, | |
592a252b | 5783 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5784 | }, |
5785 | ||
592a252b | 5786 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5787 | { |
592d1631 L |
5788 | { Bad_Opcode }, |
5789 | { Bad_Opcode }, | |
592a252b | 5790 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5791 | }, |
5792 | ||
592a252b | 5793 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5794 | { |
592d1631 L |
5795 | { Bad_Opcode }, |
5796 | { Bad_Opcode }, | |
592a252b | 5797 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5798 | }, |
5799 | ||
592a252b | 5800 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5801 | { |
592d1631 L |
5802 | { Bad_Opcode }, |
5803 | { Bad_Opcode }, | |
ec6f095a | 5804 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5805 | }, |
5806 | ||
592a252b | 5807 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5808 | { |
592d1631 L |
5809 | { Bad_Opcode }, |
5810 | { Bad_Opcode }, | |
ec6f095a | 5811 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5812 | }, |
5813 | ||
592a252b | 5814 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5815 | { |
592d1631 L |
5816 | { Bad_Opcode }, |
5817 | { Bad_Opcode }, | |
ec6f095a | 5818 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5819 | }, |
5820 | ||
592a252b | 5821 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5822 | { |
592d1631 L |
5823 | { Bad_Opcode }, |
5824 | { Bad_Opcode }, | |
ec6f095a | 5825 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5826 | }, |
5827 | ||
592a252b | 5828 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5829 | { |
592d1631 L |
5830 | { Bad_Opcode }, |
5831 | { Bad_Opcode }, | |
ec6f095a | 5832 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5833 | }, |
5834 | ||
592a252b | 5835 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5836 | { |
592d1631 L |
5837 | { Bad_Opcode }, |
5838 | { Bad_Opcode }, | |
ec6f095a | 5839 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5840 | }, |
5841 | ||
5842 | /* PREFIX_VEX_0F3836 */ | |
5843 | { | |
5844 | { Bad_Opcode }, | |
5845 | { Bad_Opcode }, | |
5846 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5847 | }, |
5848 | ||
592a252b | 5849 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5850 | { |
592d1631 L |
5851 | { Bad_Opcode }, |
5852 | { Bad_Opcode }, | |
ec6f095a | 5853 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5854 | }, |
5855 | ||
592a252b | 5856 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5857 | { |
592d1631 L |
5858 | { Bad_Opcode }, |
5859 | { Bad_Opcode }, | |
ec6f095a | 5860 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5861 | }, |
5862 | ||
592a252b | 5863 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5864 | { |
592d1631 L |
5865 | { Bad_Opcode }, |
5866 | { Bad_Opcode }, | |
ec6f095a | 5867 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5868 | }, |
5869 | ||
592a252b | 5870 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5871 | { |
592d1631 L |
5872 | { Bad_Opcode }, |
5873 | { Bad_Opcode }, | |
ec6f095a | 5874 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5875 | }, |
5876 | ||
592a252b | 5877 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5878 | { |
592d1631 L |
5879 | { Bad_Opcode }, |
5880 | { Bad_Opcode }, | |
ec6f095a | 5881 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5882 | }, |
5883 | ||
592a252b | 5884 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5885 | { |
592d1631 L |
5886 | { Bad_Opcode }, |
5887 | { Bad_Opcode }, | |
ec6f095a | 5888 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5889 | }, |
5890 | ||
592a252b | 5891 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5892 | { |
592d1631 L |
5893 | { Bad_Opcode }, |
5894 | { Bad_Opcode }, | |
ec6f095a | 5895 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5896 | }, |
5897 | ||
592a252b | 5898 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5899 | { |
592d1631 L |
5900 | { Bad_Opcode }, |
5901 | { Bad_Opcode }, | |
ec6f095a | 5902 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5903 | }, |
5904 | ||
592a252b | 5905 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5906 | { |
592d1631 L |
5907 | { Bad_Opcode }, |
5908 | { Bad_Opcode }, | |
ec6f095a | 5909 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5910 | }, |
5911 | ||
592a252b | 5912 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5913 | { |
592d1631 L |
5914 | { Bad_Opcode }, |
5915 | { Bad_Opcode }, | |
ec6f095a | 5916 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5917 | }, |
5918 | ||
592a252b | 5919 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5920 | { |
592d1631 L |
5921 | { Bad_Opcode }, |
5922 | { Bad_Opcode }, | |
592a252b | 5923 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5924 | }, |
5925 | ||
6c30d220 L |
5926 | /* PREFIX_VEX_0F3845 */ |
5927 | { | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
bf890a93 | 5930 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5931 | }, |
5932 | ||
5933 | /* PREFIX_VEX_0F3846 */ | |
5934 | { | |
5935 | { Bad_Opcode }, | |
5936 | { Bad_Opcode }, | |
5937 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5938 | }, | |
5939 | ||
5940 | /* PREFIX_VEX_0F3847 */ | |
5941 | { | |
5942 | { Bad_Opcode }, | |
5943 | { Bad_Opcode }, | |
bf890a93 | 5944 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5945 | }, |
5946 | ||
5947 | /* PREFIX_VEX_0F3858 */ | |
5948 | { | |
5949 | { Bad_Opcode }, | |
5950 | { Bad_Opcode }, | |
5951 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5952 | }, | |
5953 | ||
5954 | /* PREFIX_VEX_0F3859 */ | |
5955 | { | |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
5958 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5959 | }, | |
5960 | ||
5961 | /* PREFIX_VEX_0F385A */ | |
5962 | { | |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
5965 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5966 | }, | |
5967 | ||
5968 | /* PREFIX_VEX_0F3878 */ | |
5969 | { | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
5972 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5973 | }, | |
5974 | ||
5975 | /* PREFIX_VEX_0F3879 */ | |
5976 | { | |
5977 | { Bad_Opcode }, | |
5978 | { Bad_Opcode }, | |
5979 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5980 | }, | |
5981 | ||
5982 | /* PREFIX_VEX_0F388C */ | |
5983 | { | |
5984 | { Bad_Opcode }, | |
5985 | { Bad_Opcode }, | |
f7002f42 | 5986 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5987 | }, |
5988 | ||
5989 | /* PREFIX_VEX_0F388E */ | |
5990 | { | |
5991 | { Bad_Opcode }, | |
5992 | { Bad_Opcode }, | |
f7002f42 | 5993 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5994 | }, |
5995 | ||
5996 | /* PREFIX_VEX_0F3890 */ | |
5997 | { | |
5998 | { Bad_Opcode }, | |
5999 | { Bad_Opcode }, | |
bf890a93 | 6000 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6001 | }, |
6002 | ||
6003 | /* PREFIX_VEX_0F3891 */ | |
6004 | { | |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
bf890a93 | 6007 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6008 | }, |
6009 | ||
6010 | /* PREFIX_VEX_0F3892 */ | |
6011 | { | |
6012 | { Bad_Opcode }, | |
6013 | { Bad_Opcode }, | |
bf890a93 | 6014 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6015 | }, |
6016 | ||
6017 | /* PREFIX_VEX_0F3893 */ | |
6018 | { | |
6019 | { Bad_Opcode }, | |
6020 | { Bad_Opcode }, | |
bf890a93 | 6021 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6022 | }, |
6023 | ||
592a252b | 6024 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6025 | { |
592d1631 L |
6026 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, | |
bf890a93 | 6028 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6029 | }, |
6030 | ||
592a252b | 6031 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6032 | { |
592d1631 L |
6033 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, | |
bf890a93 | 6035 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6036 | }, |
6037 | ||
592a252b | 6038 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6039 | { |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
bf890a93 | 6042 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6043 | }, |
6044 | ||
592a252b | 6045 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6046 | { |
592d1631 L |
6047 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, | |
bf890a93 | 6049 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6050 | }, |
6051 | ||
592a252b | 6052 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6053 | { |
592d1631 L |
6054 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, | |
bf890a93 | 6056 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6057 | }, |
6058 | ||
592a252b | 6059 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6060 | { |
592d1631 L |
6061 | { Bad_Opcode }, |
6062 | { Bad_Opcode }, | |
bf890a93 | 6063 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6064 | }, |
6065 | ||
592a252b | 6066 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6067 | { |
592d1631 L |
6068 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, | |
bf890a93 | 6070 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6071 | }, |
6072 | ||
592a252b | 6073 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6074 | { |
592d1631 L |
6075 | { Bad_Opcode }, |
6076 | { Bad_Opcode }, | |
bf890a93 | 6077 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6078 | }, |
6079 | ||
592a252b | 6080 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6081 | { |
592d1631 L |
6082 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, | |
bf890a93 | 6084 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6085 | }, |
6086 | ||
592a252b | 6087 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6088 | { |
592d1631 L |
6089 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, | |
bf890a93 | 6091 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6092 | }, |
6093 | ||
592a252b | 6094 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6095 | { |
592d1631 L |
6096 | { Bad_Opcode }, |
6097 | { Bad_Opcode }, | |
bf890a93 | 6098 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6099 | { Bad_Opcode }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
bf890a93 | 6106 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
bf890a93 | 6113 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6114 | }, |
6115 | ||
592a252b | 6116 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6117 | { |
592d1631 L |
6118 | { Bad_Opcode }, |
6119 | { Bad_Opcode }, | |
bf890a93 | 6120 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6121 | }, |
6122 | ||
592a252b | 6123 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6124 | { |
592d1631 L |
6125 | { Bad_Opcode }, |
6126 | { Bad_Opcode }, | |
bf890a93 | 6127 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6128 | }, |
6129 | ||
592a252b | 6130 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6131 | { |
592d1631 L |
6132 | { Bad_Opcode }, |
6133 | { Bad_Opcode }, | |
bf890a93 | 6134 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6135 | }, |
6136 | ||
592a252b | 6137 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6138 | { |
592d1631 L |
6139 | { Bad_Opcode }, |
6140 | { Bad_Opcode }, | |
bf890a93 | 6141 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6142 | }, |
6143 | ||
592a252b | 6144 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6145 | { |
592d1631 L |
6146 | { Bad_Opcode }, |
6147 | { Bad_Opcode }, | |
bf890a93 | 6148 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6149 | }, |
6150 | ||
592a252b | 6151 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6152 | { |
592d1631 L |
6153 | { Bad_Opcode }, |
6154 | { Bad_Opcode }, | |
bf890a93 | 6155 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6156 | }, |
6157 | ||
592a252b | 6158 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6159 | { |
592d1631 L |
6160 | { Bad_Opcode }, |
6161 | { Bad_Opcode }, | |
bf890a93 | 6162 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6163 | }, |
6164 | ||
592a252b | 6165 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6166 | { |
592d1631 L |
6167 | { Bad_Opcode }, |
6168 | { Bad_Opcode }, | |
bf890a93 | 6169 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6170 | }, |
6171 | ||
592a252b | 6172 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6173 | { |
592d1631 L |
6174 | { Bad_Opcode }, |
6175 | { Bad_Opcode }, | |
bf890a93 | 6176 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6177 | }, |
6178 | ||
592a252b | 6179 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6180 | { |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
bf890a93 | 6183 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6184 | }, |
6185 | ||
592a252b | 6186 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6187 | { |
592d1631 L |
6188 | { Bad_Opcode }, |
6189 | { Bad_Opcode }, | |
bf890a93 | 6190 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6191 | }, |
6192 | ||
592a252b | 6193 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6194 | { |
592d1631 L |
6195 | { Bad_Opcode }, |
6196 | { Bad_Opcode }, | |
bf890a93 | 6197 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6198 | }, |
6199 | ||
592a252b | 6200 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6201 | { |
592d1631 L |
6202 | { Bad_Opcode }, |
6203 | { Bad_Opcode }, | |
bf890a93 | 6204 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6205 | }, |
6206 | ||
592a252b | 6207 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6208 | { |
592d1631 L |
6209 | { Bad_Opcode }, |
6210 | { Bad_Opcode }, | |
bf890a93 | 6211 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6212 | }, |
6213 | ||
592a252b | 6214 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6215 | { |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
bf890a93 | 6218 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6219 | }, |
6220 | ||
592a252b | 6221 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6222 | { |
592d1631 L |
6223 | { Bad_Opcode }, |
6224 | { Bad_Opcode }, | |
bf890a93 | 6225 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6226 | }, |
6227 | ||
592a252b | 6228 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6229 | { |
592d1631 L |
6230 | { Bad_Opcode }, |
6231 | { Bad_Opcode }, | |
bf890a93 | 6232 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6233 | }, |
6234 | ||
48521003 IT |
6235 | /* PREFIX_VEX_0F38CF */ |
6236 | { | |
6237 | { Bad_Opcode }, | |
6238 | { Bad_Opcode }, | |
6239 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6240 | }, | |
6241 | ||
592a252b | 6242 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6243 | { |
592d1631 L |
6244 | { Bad_Opcode }, |
6245 | { Bad_Opcode }, | |
592a252b | 6246 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6247 | }, |
6248 | ||
592a252b | 6249 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6250 | { |
592d1631 L |
6251 | { Bad_Opcode }, |
6252 | { Bad_Opcode }, | |
8dcf1fad | 6253 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6254 | }, |
6255 | ||
592a252b | 6256 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6257 | { |
592d1631 L |
6258 | { Bad_Opcode }, |
6259 | { Bad_Opcode }, | |
8dcf1fad | 6260 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6261 | }, |
6262 | ||
592a252b | 6263 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6264 | { |
592d1631 L |
6265 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, | |
8dcf1fad | 6267 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6268 | }, |
6269 | ||
592a252b | 6270 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6271 | { |
592d1631 L |
6272 | { Bad_Opcode }, |
6273 | { Bad_Opcode }, | |
8dcf1fad | 6274 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6275 | }, |
6276 | ||
f12dc422 L |
6277 | /* PREFIX_VEX_0F38F2 */ |
6278 | { | |
6279 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6280 | }, | |
6281 | ||
6282 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6283 | { | |
6284 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6285 | }, | |
6286 | ||
6287 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6288 | { | |
6289 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6290 | }, | |
6291 | ||
6292 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6293 | { | |
6294 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6295 | }, | |
6296 | ||
6c30d220 L |
6297 | /* PREFIX_VEX_0F38F5 */ |
6298 | { | |
6299 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6300 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6301 | { Bad_Opcode }, | |
6302 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6303 | }, | |
6304 | ||
6305 | /* PREFIX_VEX_0F38F6 */ | |
6306 | { | |
6307 | { Bad_Opcode }, | |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6311 | }, | |
6312 | ||
f12dc422 L |
6313 | /* PREFIX_VEX_0F38F7 */ |
6314 | { | |
6315 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6316 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6317 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6318 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6319 | }, | |
6320 | ||
6321 | /* PREFIX_VEX_0F3A00 */ | |
6322 | { | |
6323 | { Bad_Opcode }, | |
6324 | { Bad_Opcode }, | |
6325 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6326 | }, | |
6327 | ||
6328 | /* PREFIX_VEX_0F3A01 */ | |
6329 | { | |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6333 | }, | |
6334 | ||
6335 | /* PREFIX_VEX_0F3A02 */ | |
6336 | { | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6340 | }, |
6341 | ||
592a252b | 6342 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6343 | { |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
592a252b | 6346 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6347 | }, |
6348 | ||
592a252b | 6349 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6350 | { |
592d1631 L |
6351 | { Bad_Opcode }, |
6352 | { Bad_Opcode }, | |
592a252b | 6353 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6354 | }, |
6355 | ||
592a252b | 6356 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6357 | { |
592d1631 L |
6358 | { Bad_Opcode }, |
6359 | { Bad_Opcode }, | |
592a252b | 6360 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6361 | }, |
6362 | ||
592a252b | 6363 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6364 | { |
592d1631 L |
6365 | { Bad_Opcode }, |
6366 | { Bad_Opcode }, | |
ec6f095a | 6367 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6368 | }, |
6369 | ||
592a252b | 6370 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6371 | { |
592d1631 L |
6372 | { Bad_Opcode }, |
6373 | { Bad_Opcode }, | |
ec6f095a | 6374 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6375 | }, |
6376 | ||
592a252b | 6377 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6378 | { |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
ec6f095a | 6381 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6382 | }, |
6383 | ||
592a252b | 6384 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6385 | { |
592d1631 L |
6386 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, | |
ec6f095a | 6388 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6389 | }, |
6390 | ||
592a252b | 6391 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6392 | { |
592d1631 L |
6393 | { Bad_Opcode }, |
6394 | { Bad_Opcode }, | |
ec6f095a | 6395 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6396 | }, |
6397 | ||
592a252b | 6398 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6399 | { |
592d1631 L |
6400 | { Bad_Opcode }, |
6401 | { Bad_Opcode }, | |
ec6f095a | 6402 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6403 | }, |
6404 | ||
592a252b | 6405 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6406 | { |
592d1631 L |
6407 | { Bad_Opcode }, |
6408 | { Bad_Opcode }, | |
ec6f095a | 6409 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6410 | }, |
6411 | ||
592a252b | 6412 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6413 | { |
592d1631 L |
6414 | { Bad_Opcode }, |
6415 | { Bad_Opcode }, | |
ec6f095a | 6416 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6417 | }, |
6418 | ||
592a252b | 6419 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6420 | { |
592d1631 L |
6421 | { Bad_Opcode }, |
6422 | { Bad_Opcode }, | |
592a252b | 6423 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6424 | }, |
6425 | ||
592a252b | 6426 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6427 | { |
592d1631 L |
6428 | { Bad_Opcode }, |
6429 | { Bad_Opcode }, | |
592a252b | 6430 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6431 | }, |
6432 | ||
592a252b | 6433 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6434 | { |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
592a252b | 6437 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6438 | }, |
6439 | ||
592a252b | 6440 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6441 | { |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
592a252b | 6444 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6445 | }, |
6446 | ||
592a252b | 6447 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6448 | { |
592d1631 L |
6449 | { Bad_Opcode }, |
6450 | { Bad_Opcode }, | |
592a252b | 6451 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6452 | }, |
6453 | ||
592a252b | 6454 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6455 | { |
592d1631 L |
6456 | { Bad_Opcode }, |
6457 | { Bad_Opcode }, | |
592a252b | 6458 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6459 | }, |
6460 | ||
592a252b | 6461 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6462 | { |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
bf890a93 | 6465 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6466 | }, |
6467 | ||
592a252b | 6468 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6469 | { |
592d1631 L |
6470 | { Bad_Opcode }, |
6471 | { Bad_Opcode }, | |
592a252b | 6472 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6473 | }, |
6474 | ||
592a252b | 6475 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6476 | { |
592d1631 L |
6477 | { Bad_Opcode }, |
6478 | { Bad_Opcode }, | |
592a252b | 6479 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6480 | }, |
6481 | ||
592a252b | 6482 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6483 | { |
592d1631 L |
6484 | { Bad_Opcode }, |
6485 | { Bad_Opcode }, | |
592a252b | 6486 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6487 | }, |
6488 | ||
43234a1e L |
6489 | /* PREFIX_VEX_0F3A30 */ |
6490 | { | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6494 | }, | |
6495 | ||
1ba585e8 IT |
6496 | /* PREFIX_VEX_0F3A31 */ |
6497 | { | |
6498 | { Bad_Opcode }, | |
6499 | { Bad_Opcode }, | |
6500 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6501 | }, | |
6502 | ||
43234a1e L |
6503 | /* PREFIX_VEX_0F3A32 */ |
6504 | { | |
6505 | { Bad_Opcode }, | |
6506 | { Bad_Opcode }, | |
6507 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6508 | }, | |
6509 | ||
1ba585e8 IT |
6510 | /* PREFIX_VEX_0F3A33 */ |
6511 | { | |
6512 | { Bad_Opcode }, | |
6513 | { Bad_Opcode }, | |
6514 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6515 | }, | |
6516 | ||
6c30d220 L |
6517 | /* PREFIX_VEX_0F3A38 */ |
6518 | { | |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
6521 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6522 | }, | |
6523 | ||
6524 | /* PREFIX_VEX_0F3A39 */ | |
6525 | { | |
6526 | { Bad_Opcode }, | |
6527 | { Bad_Opcode }, | |
6528 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6529 | }, | |
6530 | ||
592a252b | 6531 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6532 | { |
592d1631 L |
6533 | { Bad_Opcode }, |
6534 | { Bad_Opcode }, | |
ec6f095a | 6535 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6536 | }, |
6537 | ||
592a252b | 6538 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6539 | { |
592d1631 L |
6540 | { Bad_Opcode }, |
6541 | { Bad_Opcode }, | |
592a252b | 6542 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6543 | }, |
6544 | ||
592a252b | 6545 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6546 | { |
592d1631 L |
6547 | { Bad_Opcode }, |
6548 | { Bad_Opcode }, | |
ec6f095a | 6549 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6550 | }, |
6551 | ||
592a252b | 6552 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6553 | { |
592d1631 L |
6554 | { Bad_Opcode }, |
6555 | { Bad_Opcode }, | |
ff1982d5 | 6556 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6557 | }, |
6558 | ||
6c30d220 L |
6559 | /* PREFIX_VEX_0F3A46 */ |
6560 | { | |
6561 | { Bad_Opcode }, | |
6562 | { Bad_Opcode }, | |
6563 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6564 | }, | |
6565 | ||
592a252b | 6566 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6567 | { |
6568 | { Bad_Opcode }, | |
6569 | { Bad_Opcode }, | |
592a252b | 6570 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6571 | }, |
6572 | ||
592a252b | 6573 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6574 | { |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
592a252b | 6577 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6578 | }, |
6579 | ||
592a252b | 6580 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6581 | { |
592d1631 L |
6582 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, | |
592a252b | 6584 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6585 | }, |
6586 | ||
592a252b | 6587 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6588 | { |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
592a252b | 6591 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6592 | }, |
6593 | ||
592a252b | 6594 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6595 | { |
592d1631 L |
6596 | { Bad_Opcode }, |
6597 | { Bad_Opcode }, | |
6c30d220 | 6598 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6599 | }, |
6600 | ||
592a252b | 6601 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6602 | { |
592d1631 L |
6603 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, | |
3a2430e0 | 6605 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6606 | }, |
6607 | ||
592a252b | 6608 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6609 | { |
592d1631 L |
6610 | { Bad_Opcode }, |
6611 | { Bad_Opcode }, | |
3a2430e0 | 6612 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6613 | }, |
6614 | ||
592a252b | 6615 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6616 | { |
592d1631 L |
6617 | { Bad_Opcode }, |
6618 | { Bad_Opcode }, | |
3a2430e0 | 6619 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6620 | }, |
6621 | ||
592a252b | 6622 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6623 | { |
592d1631 L |
6624 | { Bad_Opcode }, |
6625 | { Bad_Opcode }, | |
3a2430e0 | 6626 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6627 | }, |
6628 | ||
592a252b | 6629 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6630 | { |
592d1631 L |
6631 | { Bad_Opcode }, |
6632 | { Bad_Opcode }, | |
592a252b | 6633 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6634 | { Bad_Opcode }, |
c0f3af97 L |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6642 | }, |
6643 | ||
592a252b | 6644 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6645 | { |
592d1631 L |
6646 | { Bad_Opcode }, |
6647 | { Bad_Opcode }, | |
592a252b | 6648 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6649 | }, |
6650 | ||
592a252b | 6651 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6652 | { |
592d1631 L |
6653 | { Bad_Opcode }, |
6654 | { Bad_Opcode }, | |
592a252b | 6655 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6656 | }, |
a5ff0eb2 | 6657 | |
592a252b | 6658 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6659 | { |
592d1631 L |
6660 | { Bad_Opcode }, |
6661 | { Bad_Opcode }, | |
3a2430e0 | 6662 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6663 | }, |
6664 | ||
592a252b | 6665 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6666 | { |
592d1631 L |
6667 | { Bad_Opcode }, |
6668 | { Bad_Opcode }, | |
3a2430e0 | 6669 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6670 | }, |
6671 | ||
592a252b | 6672 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6673 | { |
592d1631 L |
6674 | { Bad_Opcode }, |
6675 | { Bad_Opcode }, | |
592a252b | 6676 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6677 | }, |
6678 | ||
592a252b | 6679 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6680 | { |
592d1631 L |
6681 | { Bad_Opcode }, |
6682 | { Bad_Opcode }, | |
592a252b | 6683 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6684 | }, |
6685 | ||
592a252b | 6686 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6687 | { |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
3a2430e0 | 6690 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6691 | }, |
6692 | ||
592a252b | 6693 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6694 | { |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
3a2430e0 | 6697 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6698 | }, |
6699 | ||
592a252b | 6700 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6701 | { |
592d1631 L |
6702 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, | |
592a252b | 6704 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6705 | }, |
6706 | ||
592a252b | 6707 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6708 | { |
592d1631 L |
6709 | { Bad_Opcode }, |
6710 | { Bad_Opcode }, | |
592a252b | 6711 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6712 | }, |
6713 | ||
592a252b | 6714 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6715 | { |
592d1631 L |
6716 | { Bad_Opcode }, |
6717 | { Bad_Opcode }, | |
3a2430e0 | 6718 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6719 | }, |
6720 | ||
592a252b | 6721 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6722 | { |
592d1631 L |
6723 | { Bad_Opcode }, |
6724 | { Bad_Opcode }, | |
3a2430e0 | 6725 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6726 | }, |
6727 | ||
592a252b | 6728 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6729 | { |
592d1631 L |
6730 | { Bad_Opcode }, |
6731 | { Bad_Opcode }, | |
592a252b | 6732 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6733 | }, |
6734 | ||
592a252b | 6735 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6736 | { |
592d1631 L |
6737 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, | |
592a252b | 6739 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6740 | }, |
6741 | ||
592a252b | 6742 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6743 | { |
592d1631 L |
6744 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, | |
3a2430e0 | 6746 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6747 | { Bad_Opcode }, |
922d8de8 DR |
6748 | }, |
6749 | ||
592a252b | 6750 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6751 | { |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
3a2430e0 | 6754 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6755 | }, |
6756 | ||
592a252b | 6757 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6758 | { |
592d1631 L |
6759 | { Bad_Opcode }, |
6760 | { Bad_Opcode }, | |
592a252b | 6761 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6762 | }, |
6763 | ||
592a252b | 6764 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6765 | { |
592d1631 L |
6766 | { Bad_Opcode }, |
6767 | { Bad_Opcode }, | |
592a252b | 6768 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6769 | }, |
6770 | ||
48521003 IT |
6771 | /* PREFIX_VEX_0F3ACE */ |
6772 | { | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6776 | }, | |
6777 | ||
6778 | /* PREFIX_VEX_0F3ACF */ | |
6779 | { | |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
6782 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6783 | }, | |
6784 | ||
592a252b | 6785 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6786 | { |
592d1631 L |
6787 | { Bad_Opcode }, |
6788 | { Bad_Opcode }, | |
592a252b | 6789 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6790 | }, |
6c30d220 L |
6791 | |
6792 | /* PREFIX_VEX_0F3AF0 */ | |
6793 | { | |
6794 | { Bad_Opcode }, | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
6797 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6798 | }, | |
43234a1e | 6799 | |
ad692897 | 6800 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6801 | }; |
6802 | ||
6803 | static const struct dis386 x86_64_table[][2] = { | |
6804 | /* X86_64_06 */ | |
6805 | { | |
bf890a93 | 6806 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6807 | }, |
6808 | ||
6809 | /* X86_64_07 */ | |
6810 | { | |
bf890a93 | 6811 | { "popP", { es }, 0 }, |
c0f3af97 L |
6812 | }, |
6813 | ||
6814 | /* X86_64_0D */ | |
6815 | { | |
bf890a93 | 6816 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6817 | }, |
6818 | ||
6819 | /* X86_64_16 */ | |
6820 | { | |
bf890a93 | 6821 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6822 | }, |
6823 | ||
6824 | /* X86_64_17 */ | |
6825 | { | |
bf890a93 | 6826 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6827 | }, |
6828 | ||
6829 | /* X86_64_1E */ | |
6830 | { | |
bf890a93 | 6831 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6832 | }, |
6833 | ||
6834 | /* X86_64_1F */ | |
6835 | { | |
bf890a93 | 6836 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6837 | }, |
6838 | ||
6839 | /* X86_64_27 */ | |
6840 | { | |
bf890a93 | 6841 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6842 | }, |
6843 | ||
6844 | /* X86_64_2F */ | |
6845 | { | |
bf890a93 | 6846 | { "das", { XX }, 0 }, |
c0f3af97 L |
6847 | }, |
6848 | ||
6849 | /* X86_64_37 */ | |
6850 | { | |
bf890a93 | 6851 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6852 | }, |
6853 | ||
6854 | /* X86_64_3F */ | |
6855 | { | |
bf890a93 | 6856 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6857 | }, |
6858 | ||
6859 | /* X86_64_60 */ | |
6860 | { | |
bf890a93 | 6861 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6862 | }, |
6863 | ||
6864 | /* X86_64_61 */ | |
6865 | { | |
bf890a93 | 6866 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6867 | }, |
6868 | ||
6869 | /* X86_64_62 */ | |
6870 | { | |
6871 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6872 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6873 | }, |
6874 | ||
6875 | /* X86_64_63 */ | |
6876 | { | |
bf890a93 | 6877 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6878 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6879 | }, |
6880 | ||
6881 | /* X86_64_6D */ | |
6882 | { | |
bf890a93 IT |
6883 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6884 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6885 | }, |
6886 | ||
6887 | /* X86_64_6F */ | |
6888 | { | |
bf890a93 IT |
6889 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6890 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6891 | }, |
6892 | ||
d039fef3 | 6893 | /* X86_64_82 */ |
8b89fe14 | 6894 | { |
de194d85 | 6895 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6896 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6897 | }, |
6898 | ||
c0f3af97 L |
6899 | /* X86_64_9A */ |
6900 | { | |
bf890a93 | 6901 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6902 | }, |
6903 | ||
6904 | /* X86_64_C4 */ | |
6905 | { | |
6906 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6907 | { VEX_C4_TABLE (VEX_0F) }, | |
6908 | }, | |
6909 | ||
6910 | /* X86_64_C5 */ | |
6911 | { | |
6912 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6913 | { VEX_C5_TABLE (VEX_0F) }, | |
6914 | }, | |
6915 | ||
6916 | /* X86_64_CE */ | |
6917 | { | |
bf890a93 | 6918 | { "into", { XX }, 0 }, |
c0f3af97 L |
6919 | }, |
6920 | ||
6921 | /* X86_64_D4 */ | |
6922 | { | |
bf890a93 | 6923 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6924 | }, |
6925 | ||
6926 | /* X86_64_D5 */ | |
6927 | { | |
bf890a93 | 6928 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6929 | }, |
6930 | ||
a72d2af2 L |
6931 | /* X86_64_E8 */ |
6932 | { | |
6933 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6934 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6935 | }, |
6936 | ||
6937 | /* X86_64_E9 */ | |
6938 | { | |
6939 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6940 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6941 | }, |
6942 | ||
c0f3af97 L |
6943 | /* X86_64_EA */ |
6944 | { | |
bf890a93 | 6945 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6946 | }, |
6947 | ||
6948 | /* X86_64_0F01_REG_0 */ | |
6949 | { | |
bf890a93 IT |
6950 | { "sgdt{Q|IQ}", { M }, 0 }, |
6951 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6952 | }, |
6953 | ||
6954 | /* X86_64_0F01_REG_1 */ | |
6955 | { | |
bf890a93 IT |
6956 | { "sidt{Q|IQ}", { M }, 0 }, |
6957 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6958 | }, |
6959 | ||
6960 | /* X86_64_0F01_REG_2 */ | |
6961 | { | |
bf890a93 IT |
6962 | { "lgdt{Q|Q}", { M }, 0 }, |
6963 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6964 | }, |
6965 | ||
6966 | /* X86_64_0F01_REG_3 */ | |
6967 | { | |
bf890a93 IT |
6968 | { "lidt{Q|Q}", { M }, 0 }, |
6969 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6970 | }, |
6971 | }; | |
6972 | ||
6973 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6974 | |
6975 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6976 | { |
6977 | /* 00 */ | |
507bd325 L |
6978 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6979 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6980 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6981 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6982 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6983 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6984 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6985 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6986 | /* 08 */ |
507bd325 L |
6987 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6988 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6989 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6990 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6991 | { Bad_Opcode }, |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
f88c9eb0 SP |
6995 | /* 10 */ |
6996 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6997 | { Bad_Opcode }, |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
f88c9eb0 SP |
7000 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7001 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7002 | { Bad_Opcode }, |
f88c9eb0 SP |
7003 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7004 | /* 18 */ | |
592d1631 L |
7005 | { Bad_Opcode }, |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
507bd325 L |
7009 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7010 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7011 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7012 | { Bad_Opcode }, |
f88c9eb0 SP |
7013 | /* 20 */ |
7014 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7017 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7018 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7019 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7020 | { Bad_Opcode }, |
7021 | { Bad_Opcode }, | |
f88c9eb0 SP |
7022 | /* 28 */ |
7023 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7024 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7025 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7026 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7027 | { Bad_Opcode }, |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
f88c9eb0 SP |
7031 | /* 30 */ |
7032 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7033 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7034 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7035 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7036 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7037 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7038 | { Bad_Opcode }, |
f88c9eb0 SP |
7039 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7040 | /* 38 */ | |
7041 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7042 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7043 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7044 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7045 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7046 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7047 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7048 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7049 | /* 40 */ | |
7050 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7051 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7052 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
f88c9eb0 | 7058 | /* 48 */ |
592d1631 L |
7059 | { Bad_Opcode }, |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
f88c9eb0 | 7067 | /* 50 */ |
592d1631 L |
7068 | { Bad_Opcode }, |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
f88c9eb0 | 7076 | /* 58 */ |
592d1631 L |
7077 | { Bad_Opcode }, |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
f88c9eb0 | 7085 | /* 60 */ |
592d1631 L |
7086 | { Bad_Opcode }, |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
f88c9eb0 | 7094 | /* 68 */ |
592d1631 L |
7095 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
f88c9eb0 | 7103 | /* 70 */ |
592d1631 L |
7104 | { Bad_Opcode }, |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
f88c9eb0 | 7112 | /* 78 */ |
592d1631 L |
7113 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
f88c9eb0 SP |
7121 | /* 80 */ |
7122 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7123 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7124 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7125 | { Bad_Opcode }, |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
f88c9eb0 | 7130 | /* 88 */ |
592d1631 L |
7131 | { Bad_Opcode }, |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
f88c9eb0 | 7139 | /* 90 */ |
592d1631 L |
7140 | { Bad_Opcode }, |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
f88c9eb0 | 7148 | /* 98 */ |
592d1631 L |
7149 | { Bad_Opcode }, |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
f88c9eb0 | 7157 | /* a0 */ |
592d1631 L |
7158 | { Bad_Opcode }, |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
f88c9eb0 | 7166 | /* a8 */ |
592d1631 L |
7167 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
f88c9eb0 | 7175 | /* b0 */ |
592d1631 L |
7176 | { Bad_Opcode }, |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
f88c9eb0 | 7184 | /* b8 */ |
592d1631 L |
7185 | { Bad_Opcode }, |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
f88c9eb0 | 7193 | /* c0 */ |
592d1631 L |
7194 | { Bad_Opcode }, |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
f88c9eb0 | 7202 | /* c8 */ |
a0046408 L |
7203 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7204 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7206 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7207 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7208 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7209 | { Bad_Opcode }, |
48521003 | 7210 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7211 | /* d0 */ |
592d1631 L |
7212 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
f88c9eb0 | 7220 | /* d8 */ |
592d1631 L |
7221 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
f88c9eb0 SP |
7224 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7225 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7226 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7227 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7228 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7229 | /* e0 */ | |
592d1631 L |
7230 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
f88c9eb0 | 7238 | /* e8 */ |
592d1631 L |
7239 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
f88c9eb0 SP |
7247 | /* f0 */ |
7248 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7250 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
603555e5 | 7253 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7254 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7255 | { Bad_Opcode }, |
f88c9eb0 | 7256 | /* f8 */ |
c0a30a9f L |
7257 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7258 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7259 | { Bad_Opcode }, |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
f88c9eb0 SP |
7265 | }, |
7266 | /* THREE_BYTE_0F3A */ | |
7267 | { | |
7268 | /* 00 */ | |
592d1631 L |
7269 | { Bad_Opcode }, |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
f88c9eb0 SP |
7277 | /* 08 */ |
7278 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7279 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7280 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7281 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7282 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7283 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7284 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7285 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7286 | /* 10 */ |
592d1631 L |
7287 | { Bad_Opcode }, |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
f88c9eb0 SP |
7291 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7292 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7293 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7294 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7295 | /* 18 */ | |
592d1631 L |
7296 | { Bad_Opcode }, |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
f88c9eb0 SP |
7304 | /* 20 */ |
7305 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7306 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7307 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7308 | { Bad_Opcode }, |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
f88c9eb0 | 7313 | /* 28 */ |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
f88c9eb0 | 7322 | /* 30 */ |
592d1631 L |
7323 | { Bad_Opcode }, |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
f88c9eb0 | 7331 | /* 38 */ |
592d1631 L |
7332 | { Bad_Opcode }, |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
f88c9eb0 SP |
7340 | /* 40 */ |
7341 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7342 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7343 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7344 | { Bad_Opcode }, |
f88c9eb0 | 7345 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7346 | { Bad_Opcode }, |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
f88c9eb0 | 7349 | /* 48 */ |
592d1631 L |
7350 | { Bad_Opcode }, |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
f88c9eb0 | 7358 | /* 50 */ |
592d1631 L |
7359 | { Bad_Opcode }, |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
f88c9eb0 | 7367 | /* 58 */ |
592d1631 L |
7368 | { Bad_Opcode }, |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
f88c9eb0 SP |
7376 | /* 60 */ |
7377 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7378 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7379 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7380 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
f88c9eb0 | 7385 | /* 68 */ |
592d1631 L |
7386 | { Bad_Opcode }, |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
f88c9eb0 | 7394 | /* 70 */ |
592d1631 L |
7395 | { Bad_Opcode }, |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
f88c9eb0 | 7403 | /* 78 */ |
592d1631 L |
7404 | { Bad_Opcode }, |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
f88c9eb0 | 7412 | /* 80 */ |
592d1631 L |
7413 | { Bad_Opcode }, |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
f88c9eb0 | 7421 | /* 88 */ |
592d1631 L |
7422 | { Bad_Opcode }, |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
f88c9eb0 | 7430 | /* 90 */ |
592d1631 L |
7431 | { Bad_Opcode }, |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
f88c9eb0 | 7439 | /* 98 */ |
592d1631 L |
7440 | { Bad_Opcode }, |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
f88c9eb0 | 7448 | /* a0 */ |
592d1631 L |
7449 | { Bad_Opcode }, |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
f88c9eb0 | 7457 | /* a8 */ |
592d1631 L |
7458 | { Bad_Opcode }, |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
f88c9eb0 | 7466 | /* b0 */ |
592d1631 L |
7467 | { Bad_Opcode }, |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
f88c9eb0 | 7475 | /* b8 */ |
592d1631 L |
7476 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
f88c9eb0 | 7484 | /* c0 */ |
592d1631 L |
7485 | { Bad_Opcode }, |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
f88c9eb0 | 7493 | /* c8 */ |
592d1631 L |
7494 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
a0046408 | 7498 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7499 | { Bad_Opcode }, |
48521003 IT |
7500 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7501 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7502 | /* d0 */ |
592d1631 L |
7503 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
f88c9eb0 | 7511 | /* d8 */ |
592d1631 L |
7512 | { Bad_Opcode }, |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
f88c9eb0 SP |
7519 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7520 | /* e0 */ | |
592d1631 L |
7521 | { Bad_Opcode }, |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
592d1631 L |
7526 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
85f10a01 | 7529 | /* e8 */ |
592d1631 L |
7530 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
85f10a01 | 7538 | /* f0 */ |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
85f10a01 | 7547 | /* f8 */ |
592d1631 L |
7548 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
85f10a01 | 7556 | }, |
f88c9eb0 SP |
7557 | }; |
7558 | ||
7559 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7560 | /* XOP_08 */ |
85f10a01 MM |
7561 | { |
7562 | /* 00 */ | |
592d1631 L |
7563 | { Bad_Opcode }, |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
85f10a01 | 7571 | /* 08 */ |
592d1631 L |
7572 | { Bad_Opcode }, |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
85f10a01 | 7580 | /* 10 */ |
3929df09 | 7581 | { Bad_Opcode }, |
592d1631 L |
7582 | { Bad_Opcode }, |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
85f10a01 | 7589 | /* 18 */ |
592d1631 L |
7590 | { Bad_Opcode }, |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
85f10a01 | 7598 | /* 20 */ |
592d1631 L |
7599 | { Bad_Opcode }, |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
85f10a01 | 7607 | /* 28 */ |
592d1631 L |
7608 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
c0f3af97 | 7616 | /* 30 */ |
592d1631 L |
7617 | { Bad_Opcode }, |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
c0f3af97 | 7625 | /* 38 */ |
592d1631 L |
7626 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
c0f3af97 | 7634 | /* 40 */ |
592d1631 L |
7635 | { Bad_Opcode }, |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
85f10a01 | 7643 | /* 48 */ |
592d1631 L |
7644 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
c0f3af97 | 7652 | /* 50 */ |
592d1631 L |
7653 | { Bad_Opcode }, |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
85f10a01 | 7661 | /* 58 */ |
592d1631 L |
7662 | { Bad_Opcode }, |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
c1e679ec | 7670 | /* 60 */ |
592d1631 L |
7671 | { Bad_Opcode }, |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
c0f3af97 | 7679 | /* 68 */ |
592d1631 L |
7680 | { Bad_Opcode }, |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
85f10a01 | 7688 | /* 70 */ |
592d1631 L |
7689 | { Bad_Opcode }, |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
85f10a01 | 7697 | /* 78 */ |
592d1631 L |
7698 | { Bad_Opcode }, |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
85f10a01 | 7706 | /* 80 */ |
592d1631 L |
7707 | { Bad_Opcode }, |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
3a2430e0 JB |
7712 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7713 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7714 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7715 | /* 88 */ |
592d1631 L |
7716 | { Bad_Opcode }, |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
3a2430e0 JB |
7722 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7723 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7724 | /* 90 */ |
592d1631 L |
7725 | { Bad_Opcode }, |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
3a2430e0 JB |
7730 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7731 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7732 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7733 | /* 98 */ |
592d1631 L |
7734 | { Bad_Opcode }, |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
3a2430e0 JB |
7740 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7741 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7742 | /* a0 */ |
592d1631 L |
7743 | { Bad_Opcode }, |
7744 | { Bad_Opcode }, | |
3a2430e0 JB |
7745 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7746 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
3a2430e0 | 7749 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7750 | { Bad_Opcode }, |
5dd85c99 | 7751 | /* a8 */ |
592d1631 L |
7752 | { Bad_Opcode }, |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
5dd85c99 | 7760 | /* b0 */ |
592d1631 L |
7761 | { Bad_Opcode }, |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
3a2430e0 | 7767 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7768 | { Bad_Opcode }, |
5dd85c99 | 7769 | /* b8 */ |
592d1631 L |
7770 | { Bad_Opcode }, |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
5dd85c99 | 7778 | /* c0 */ |
bf890a93 IT |
7779 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7780 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7781 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7782 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
5dd85c99 | 7787 | /* c8 */ |
592d1631 L |
7788 | { Bad_Opcode }, |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
ff688e1f L |
7792 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7793 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7794 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7795 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7796 | /* d0 */ |
592d1631 L |
7797 | { Bad_Opcode }, |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
5dd85c99 | 7805 | /* d8 */ |
592d1631 L |
7806 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
5dd85c99 | 7814 | /* e0 */ |
592d1631 L |
7815 | { Bad_Opcode }, |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
5dd85c99 | 7823 | /* e8 */ |
592d1631 L |
7824 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
ff688e1f L |
7828 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7829 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7830 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7831 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7832 | /* f0 */ |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
5dd85c99 | 7841 | /* f8 */ |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
5dd85c99 SP |
7850 | }, |
7851 | /* XOP_09 */ | |
7852 | { | |
7853 | /* 00 */ | |
592d1631 | 7854 | { Bad_Opcode }, |
2a2a0f38 QN |
7855 | { REG_TABLE (REG_XOP_TBM_01) }, |
7856 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7857 | { Bad_Opcode }, |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
5dd85c99 | 7862 | /* 08 */ |
592d1631 L |
7863 | { Bad_Opcode }, |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
5dd85c99 | 7871 | /* 10 */ |
592d1631 L |
7872 | { Bad_Opcode }, |
7873 | { Bad_Opcode }, | |
5dd85c99 | 7874 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7875 | { Bad_Opcode }, |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
5dd85c99 | 7880 | /* 18 */ |
592d1631 L |
7881 | { Bad_Opcode }, |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
5dd85c99 | 7889 | /* 20 */ |
592d1631 L |
7890 | { Bad_Opcode }, |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
5dd85c99 | 7898 | /* 28 */ |
592d1631 L |
7899 | { Bad_Opcode }, |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
5dd85c99 | 7907 | /* 30 */ |
592d1631 L |
7908 | { Bad_Opcode }, |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
5dd85c99 | 7916 | /* 38 */ |
592d1631 L |
7917 | { Bad_Opcode }, |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
5dd85c99 | 7925 | /* 40 */ |
592d1631 L |
7926 | { Bad_Opcode }, |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
5dd85c99 | 7934 | /* 48 */ |
592d1631 L |
7935 | { Bad_Opcode }, |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
5dd85c99 | 7943 | /* 50 */ |
592d1631 L |
7944 | { Bad_Opcode }, |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
5dd85c99 | 7952 | /* 58 */ |
592d1631 L |
7953 | { Bad_Opcode }, |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
5dd85c99 | 7961 | /* 60 */ |
592d1631 L |
7962 | { Bad_Opcode }, |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
5dd85c99 | 7970 | /* 68 */ |
592d1631 L |
7971 | { Bad_Opcode }, |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
5dd85c99 | 7979 | /* 70 */ |
592d1631 L |
7980 | { Bad_Opcode }, |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
5dd85c99 | 7988 | /* 78 */ |
592d1631 L |
7989 | { Bad_Opcode }, |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
5dd85c99 | 7997 | /* 80 */ |
592a252b L |
7998 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7999 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8000 | { "vfrczss", { XM, EXd }, 0 }, |
8001 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8002 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
5dd85c99 | 8006 | /* 88 */ |
592d1631 L |
8007 | { Bad_Opcode }, |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
5dd85c99 | 8015 | /* 90 */ |
bf890a93 IT |
8016 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8017 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8018 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8019 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8020 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8021 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8022 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8023 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8024 | /* 98 */ |
bf890a93 IT |
8025 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8026 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8027 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8028 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8029 | { Bad_Opcode }, |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
5dd85c99 | 8033 | /* a0 */ |
592d1631 L |
8034 | { Bad_Opcode }, |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
5dd85c99 | 8042 | /* a8 */ |
592d1631 L |
8043 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
5dd85c99 | 8051 | /* b0 */ |
592d1631 L |
8052 | { Bad_Opcode }, |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
5dd85c99 | 8060 | /* b8 */ |
592d1631 L |
8061 | { Bad_Opcode }, |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
5dd85c99 | 8069 | /* c0 */ |
592d1631 | 8070 | { Bad_Opcode }, |
bf890a93 IT |
8071 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8072 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8073 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8074 | { Bad_Opcode }, |
8075 | { Bad_Opcode }, | |
bf890a93 IT |
8076 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8077 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8078 | /* c8 */ |
592d1631 L |
8079 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
bf890a93 | 8082 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
5dd85c99 | 8087 | /* d0 */ |
592d1631 | 8088 | { Bad_Opcode }, |
bf890a93 IT |
8089 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8090 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8091 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
bf890a93 IT |
8094 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8095 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8096 | /* d8 */ |
592d1631 L |
8097 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
bf890a93 | 8100 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8101 | { Bad_Opcode }, |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
5dd85c99 | 8105 | /* e0 */ |
592d1631 | 8106 | { Bad_Opcode }, |
bf890a93 IT |
8107 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8108 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8109 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8110 | { Bad_Opcode }, |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
4e7d34a6 | 8114 | /* e8 */ |
592d1631 L |
8115 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
4e7d34a6 | 8123 | /* f0 */ |
592d1631 L |
8124 | { Bad_Opcode }, |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
4e7d34a6 | 8132 | /* f8 */ |
592d1631 L |
8133 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
4e7d34a6 | 8141 | }, |
f88c9eb0 | 8142 | /* XOP_0A */ |
4e7d34a6 L |
8143 | { |
8144 | /* 00 */ | |
592d1631 L |
8145 | { Bad_Opcode }, |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
4e7d34a6 | 8153 | /* 08 */ |
592d1631 L |
8154 | { Bad_Opcode }, |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
4e7d34a6 | 8162 | /* 10 */ |
c1dc7af5 | 8163 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8164 | { Bad_Opcode }, |
f88c9eb0 | 8165 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8166 | { Bad_Opcode }, |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
4e7d34a6 | 8171 | /* 18 */ |
592d1631 L |
8172 | { Bad_Opcode }, |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
4e7d34a6 | 8180 | /* 20 */ |
592d1631 L |
8181 | { Bad_Opcode }, |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
4e7d34a6 | 8189 | /* 28 */ |
592d1631 L |
8190 | { Bad_Opcode }, |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
4e7d34a6 | 8198 | /* 30 */ |
592d1631 L |
8199 | { Bad_Opcode }, |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
c0f3af97 | 8207 | /* 38 */ |
592d1631 L |
8208 | { Bad_Opcode }, |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
c0f3af97 | 8216 | /* 40 */ |
592d1631 L |
8217 | { Bad_Opcode }, |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
c1e679ec | 8225 | /* 48 */ |
592d1631 L |
8226 | { Bad_Opcode }, |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
c1e679ec | 8234 | /* 50 */ |
592d1631 L |
8235 | { Bad_Opcode }, |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
4e7d34a6 | 8243 | /* 58 */ |
592d1631 L |
8244 | { Bad_Opcode }, |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
4e7d34a6 | 8252 | /* 60 */ |
592d1631 L |
8253 | { Bad_Opcode }, |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
4e7d34a6 | 8261 | /* 68 */ |
592d1631 L |
8262 | { Bad_Opcode }, |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
4e7d34a6 | 8270 | /* 70 */ |
592d1631 L |
8271 | { Bad_Opcode }, |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
4e7d34a6 | 8279 | /* 78 */ |
592d1631 L |
8280 | { Bad_Opcode }, |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
4e7d34a6 | 8288 | /* 80 */ |
592d1631 L |
8289 | { Bad_Opcode }, |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
4e7d34a6 | 8297 | /* 88 */ |
592d1631 L |
8298 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
4e7d34a6 | 8306 | /* 90 */ |
592d1631 L |
8307 | { Bad_Opcode }, |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
4e7d34a6 | 8315 | /* 98 */ |
592d1631 L |
8316 | { Bad_Opcode }, |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
4e7d34a6 | 8324 | /* a0 */ |
592d1631 L |
8325 | { Bad_Opcode }, |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
4e7d34a6 | 8333 | /* a8 */ |
592d1631 L |
8334 | { Bad_Opcode }, |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
d5d7db8e | 8342 | /* b0 */ |
592d1631 L |
8343 | { Bad_Opcode }, |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
85f10a01 | 8351 | /* b8 */ |
592d1631 L |
8352 | { Bad_Opcode }, |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
85f10a01 | 8360 | /* c0 */ |
592d1631 L |
8361 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
85f10a01 | 8369 | /* c8 */ |
592d1631 L |
8370 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
85f10a01 | 8378 | /* d0 */ |
592d1631 L |
8379 | { Bad_Opcode }, |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
85f10a01 | 8387 | /* d8 */ |
592d1631 L |
8388 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
85f10a01 | 8396 | /* e0 */ |
592d1631 L |
8397 | { Bad_Opcode }, |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
85f10a01 | 8405 | /* e8 */ |
592d1631 L |
8406 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
85f10a01 | 8414 | /* f0 */ |
592d1631 L |
8415 | { Bad_Opcode }, |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
85f10a01 | 8423 | /* f8 */ |
592d1631 L |
8424 | { Bad_Opcode }, |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
85f10a01 | 8432 | }, |
c0f3af97 L |
8433 | }; |
8434 | ||
8435 | static const struct dis386 vex_table[][256] = { | |
8436 | /* VEX_0F */ | |
85f10a01 MM |
8437 | { |
8438 | /* 00 */ | |
592d1631 L |
8439 | { Bad_Opcode }, |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
85f10a01 | 8447 | /* 08 */ |
592d1631 L |
8448 | { Bad_Opcode }, |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
c0f3af97 | 8456 | /* 10 */ |
592a252b L |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8458 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8460 | { MOD_TABLE (MOD_VEX_0F13) }, | |
ec6f095a L |
8461 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
8462 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, | |
592a252b L |
8463 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8464 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8465 | /* 18 */ |
592d1631 L |
8466 | { Bad_Opcode }, |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
c0f3af97 | 8474 | /* 20 */ |
592d1631 L |
8475 | { Bad_Opcode }, |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
c0f3af97 | 8483 | /* 28 */ |
ec6f095a L |
8484 | { "vmovapX", { XM, EXx }, 0 }, |
8485 | { "vmovapX", { EXxS, XM }, 0 }, | |
592a252b L |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8487 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8488 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8489 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8490 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8491 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8492 | /* 30 */ |
592d1631 L |
8493 | { Bad_Opcode }, |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
4e7d34a6 | 8501 | /* 38 */ |
592d1631 L |
8502 | { Bad_Opcode }, |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
d5d7db8e | 8510 | /* 40 */ |
592d1631 | 8511 | { Bad_Opcode }, |
43234a1e L |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8514 | { Bad_Opcode }, |
43234a1e L |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8516 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8517 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8519 | /* 48 */ |
592d1631 L |
8520 | { Bad_Opcode }, |
8521 | { Bad_Opcode }, | |
1ba585e8 | 8522 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8523 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8524 | { Bad_Opcode }, |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
d5d7db8e | 8528 | /* 50 */ |
592a252b L |
8529 | { MOD_TABLE (MOD_VEX_0F50) }, |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8532 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8533 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8534 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8535 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8536 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8537 | /* 58 */ |
592a252b L |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8541 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8542 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8543 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8544 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8546 | /* 60 */ |
592a252b L |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8551 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8555 | /* 68 */ |
592a252b L |
8556 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8557 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8564 | /* 70 */ |
592a252b L |
8565 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8566 | { REG_TABLE (REG_VEX_0F71) }, | |
8567 | { REG_TABLE (REG_VEX_0F72) }, | |
8568 | { REG_TABLE (REG_VEX_0F73) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8573 | /* 78 */ |
592d1631 L |
8574 | { Bad_Opcode }, |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
592a252b L |
8578 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8579 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8582 | /* 80 */ |
592d1631 L |
8583 | { Bad_Opcode }, |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
c0f3af97 | 8591 | /* 88 */ |
592d1631 L |
8592 | { Bad_Opcode }, |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
c0f3af97 | 8600 | /* 90 */ |
43234a1e L |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
c0f3af97 | 8609 | /* 98 */ |
43234a1e | 8610 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8611 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8612 | { Bad_Opcode }, |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
c0f3af97 | 8618 | /* a0 */ |
592d1631 L |
8619 | { Bad_Opcode }, |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
c0f3af97 | 8627 | /* a8 */ |
592d1631 L |
8628 | { Bad_Opcode }, |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
592a252b | 8634 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8635 | { Bad_Opcode }, |
c0f3af97 | 8636 | /* b0 */ |
592d1631 L |
8637 | { Bad_Opcode }, |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
c0f3af97 | 8645 | /* b8 */ |
592d1631 L |
8646 | { Bad_Opcode }, |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
c0f3af97 | 8654 | /* c0 */ |
592d1631 L |
8655 | { Bad_Opcode }, |
8656 | { Bad_Opcode }, | |
592a252b | 8657 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8658 | { Bad_Opcode }, |
592a252b L |
8659 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8660 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8661 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8662 | { Bad_Opcode }, |
c0f3af97 | 8663 | /* c8 */ |
592d1631 L |
8664 | { Bad_Opcode }, |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
c0f3af97 | 8672 | /* d0 */ |
592a252b L |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8676 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8681 | /* d8 */ |
592a252b L |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8690 | /* e0 */ |
592a252b L |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8695 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8696 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8699 | /* e8 */ |
592a252b L |
8700 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8701 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8708 | /* f0 */ |
592a252b L |
8709 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8710 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8717 | /* f8 */ |
592a252b L |
8718 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8719 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8721 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8722 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8723 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8724 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8725 | { Bad_Opcode }, |
c0f3af97 L |
8726 | }, |
8727 | /* VEX_0F38 */ | |
8728 | { | |
8729 | /* 00 */ | |
592a252b L |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8738 | /* 08 */ |
592a252b L |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8747 | /* 10 */ |
592d1631 L |
8748 | { Bad_Opcode }, |
8749 | { Bad_Opcode }, | |
8750 | { Bad_Opcode }, | |
592a252b | 8751 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8752 | { Bad_Opcode }, |
8753 | { Bad_Opcode }, | |
6c30d220 | 8754 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8755 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8756 | /* 18 */ |
592a252b L |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8760 | { Bad_Opcode }, |
592a252b L |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8764 | { Bad_Opcode }, |
c0f3af97 | 8765 | /* 20 */ |
592a252b L |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8772 | { Bad_Opcode }, |
8773 | { Bad_Opcode }, | |
c0f3af97 | 8774 | /* 28 */ |
592a252b L |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8783 | /* 30 */ |
592a252b L |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8790 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8791 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8792 | /* 38 */ |
592a252b L |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8801 | /* 40 */ |
592a252b L |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8804 | { Bad_Opcode }, |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
6c30d220 L |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8810 | /* 48 */ |
592d1631 L |
8811 | { Bad_Opcode }, |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
c0f3af97 | 8819 | /* 50 */ |
592d1631 L |
8820 | { Bad_Opcode }, |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
c0f3af97 | 8828 | /* 58 */ |
6c30d220 L |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8832 | { Bad_Opcode }, |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
c0f3af97 | 8837 | /* 60 */ |
592d1631 L |
8838 | { Bad_Opcode }, |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
c0f3af97 | 8846 | /* 68 */ |
592d1631 L |
8847 | { Bad_Opcode }, |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
c0f3af97 | 8855 | /* 70 */ |
592d1631 L |
8856 | { Bad_Opcode }, |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
c0f3af97 | 8864 | /* 78 */ |
6c30d220 L |
8865 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8866 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8867 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
c0f3af97 | 8873 | /* 80 */ |
592d1631 L |
8874 | { Bad_Opcode }, |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
c0f3af97 | 8882 | /* 88 */ |
592d1631 L |
8883 | { Bad_Opcode }, |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
6c30d220 | 8887 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8888 | { Bad_Opcode }, |
6c30d220 | 8889 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8890 | { Bad_Opcode }, |
c0f3af97 | 8891 | /* 90 */ |
6c30d220 L |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8896 | { Bad_Opcode }, |
8897 | { Bad_Opcode }, | |
592a252b L |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8900 | /* 98 */ |
592a252b L |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8909 | /* a0 */ |
592d1631 L |
8910 | { Bad_Opcode }, |
8911 | { Bad_Opcode }, | |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
592a252b L |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8918 | /* a8 */ |
592a252b L |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8924 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8927 | /* b0 */ |
592d1631 L |
8928 | { Bad_Opcode }, |
8929 | { Bad_Opcode }, | |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
592a252b L |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8936 | /* b8 */ |
592a252b L |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8945 | /* c0 */ |
592d1631 L |
8946 | { Bad_Opcode }, |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
c0f3af97 | 8954 | /* c8 */ |
592d1631 L |
8955 | { Bad_Opcode }, |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
48521003 | 8962 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8963 | /* d0 */ |
592d1631 L |
8964 | { Bad_Opcode }, |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
c0f3af97 | 8972 | /* d8 */ |
592d1631 L |
8973 | { Bad_Opcode }, |
8974 | { Bad_Opcode }, | |
8975 | { Bad_Opcode }, | |
592a252b L |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8981 | /* e0 */ |
592d1631 L |
8982 | { Bad_Opcode }, |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
8988 | { Bad_Opcode }, | |
8989 | { Bad_Opcode }, | |
c0f3af97 | 8990 | /* e8 */ |
592d1631 L |
8991 | { Bad_Opcode }, |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
c0f3af97 | 8999 | /* f0 */ |
592d1631 L |
9000 | { Bad_Opcode }, |
9001 | { Bad_Opcode }, | |
f12dc422 L |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9003 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9004 | { Bad_Opcode }, |
6c30d220 L |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9007 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9008 | /* f8 */ |
592d1631 L |
9009 | { Bad_Opcode }, |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
9015 | { Bad_Opcode }, | |
9016 | { Bad_Opcode }, | |
c0f3af97 L |
9017 | }, |
9018 | /* VEX_0F3A */ | |
9019 | { | |
9020 | /* 00 */ | |
6c30d220 L |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9024 | { Bad_Opcode }, |
592a252b L |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9028 | { Bad_Opcode }, |
c0f3af97 | 9029 | /* 08 */ |
592a252b L |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9038 | /* 10 */ |
592d1631 L |
9039 | { Bad_Opcode }, |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
592a252b L |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9047 | /* 18 */ |
592a252b L |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9049 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9050 | { Bad_Opcode }, |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
592a252b | 9053 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9054 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, | |
c0f3af97 | 9056 | /* 20 */ |
592a252b L |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9060 | { Bad_Opcode }, |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
c0f3af97 | 9065 | /* 28 */ |
592d1631 L |
9066 | { Bad_Opcode }, |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
c0f3af97 | 9074 | /* 30 */ |
43234a1e | 9075 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9076 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9077 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9078 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
c0f3af97 | 9083 | /* 38 */ |
6c30d220 L |
9084 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
c0f3af97 | 9092 | /* 40 */ |
592a252b L |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9096 | { Bad_Opcode }, |
592a252b | 9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9098 | { Bad_Opcode }, |
6c30d220 | 9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9100 | { Bad_Opcode }, |
c0f3af97 | 9101 | /* 48 */ |
592a252b L |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9103 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9104 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9105 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9107 | { Bad_Opcode }, |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
c0f3af97 | 9110 | /* 50 */ |
592d1631 L |
9111 | { Bad_Opcode }, |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
c0f3af97 | 9119 | /* 58 */ |
592d1631 L |
9120 | { Bad_Opcode }, |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
592a252b L |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9128 | /* 60 */ |
592a252b L |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9133 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
c0f3af97 | 9137 | /* 68 */ |
592a252b L |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9143 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9144 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9145 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9146 | /* 70 */ |
592d1631 L |
9147 | { Bad_Opcode }, |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
c0f3af97 | 9155 | /* 78 */ |
592a252b L |
9156 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9161 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9162 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9163 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9164 | /* 80 */ |
592d1631 L |
9165 | { Bad_Opcode }, |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
c0f3af97 | 9173 | /* 88 */ |
592d1631 L |
9174 | { Bad_Opcode }, |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
c0f3af97 | 9182 | /* 90 */ |
592d1631 L |
9183 | { Bad_Opcode }, |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
c0f3af97 | 9191 | /* 98 */ |
592d1631 L |
9192 | { Bad_Opcode }, |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
c0f3af97 | 9200 | /* a0 */ |
592d1631 L |
9201 | { Bad_Opcode }, |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
c0f3af97 | 9209 | /* a8 */ |
592d1631 L |
9210 | { Bad_Opcode }, |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
c0f3af97 | 9218 | /* b0 */ |
592d1631 L |
9219 | { Bad_Opcode }, |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
c0f3af97 | 9227 | /* b8 */ |
592d1631 L |
9228 | { Bad_Opcode }, |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
c0f3af97 | 9236 | /* c0 */ |
592d1631 L |
9237 | { Bad_Opcode }, |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
c0f3af97 | 9245 | /* c8 */ |
592d1631 L |
9246 | { Bad_Opcode }, |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
48521003 IT |
9252 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9253 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9254 | /* d0 */ |
592d1631 L |
9255 | { Bad_Opcode }, |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
c0f3af97 | 9263 | /* d8 */ |
592d1631 L |
9264 | { Bad_Opcode }, |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
592a252b | 9271 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9272 | /* e0 */ |
592d1631 L |
9273 | { Bad_Opcode }, |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
c0f3af97 | 9281 | /* e8 */ |
592d1631 L |
9282 | { Bad_Opcode }, |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
c0f3af97 | 9290 | /* f0 */ |
6c30d220 | 9291 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9292 | { Bad_Opcode }, |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
c0f3af97 | 9299 | /* f8 */ |
592d1631 L |
9300 | { Bad_Opcode }, |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
c0f3af97 L |
9308 | }, |
9309 | }; | |
9310 | ||
43234a1e | 9311 | #include "i386-dis-evex.h" |
ad692897 | 9312 | |
c0f3af97 | 9313 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9314 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9315 | { |
ec6f095a | 9316 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9317 | }, |
9318 | ||
592a252b | 9319 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9320 | { |
ec6f095a | 9321 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9322 | }, |
9323 | ||
592a252b | 9324 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9325 | { |
ec6f095a | 9326 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9327 | }, |
9328 | ||
592a252b | 9329 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9330 | { |
ec6f095a | 9331 | { "vmovlpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9332 | }, |
9333 | ||
592a252b | 9334 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9335 | { |
ec6f095a | 9336 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9337 | }, |
9338 | ||
592a252b | 9339 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9340 | { |
ec6f095a | 9341 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9342 | }, |
9343 | ||
592a252b | 9344 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9345 | { |
ec6f095a | 9346 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9347 | }, |
9348 | ||
592a252b | 9349 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9350 | { |
ec6f095a | 9351 | { "vmovhpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9352 | }, |
9353 | ||
43234a1e L |
9354 | /* VEX_LEN_0F41_P_0 */ |
9355 | { | |
9356 | { Bad_Opcode }, | |
9357 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9358 | }, | |
1ba585e8 IT |
9359 | /* VEX_LEN_0F41_P_2 */ |
9360 | { | |
9361 | { Bad_Opcode }, | |
9362 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9363 | }, | |
43234a1e L |
9364 | /* VEX_LEN_0F42_P_0 */ |
9365 | { | |
9366 | { Bad_Opcode }, | |
9367 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9368 | }, | |
1ba585e8 IT |
9369 | /* VEX_LEN_0F42_P_2 */ |
9370 | { | |
9371 | { Bad_Opcode }, | |
9372 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9373 | }, | |
43234a1e L |
9374 | /* VEX_LEN_0F44_P_0 */ |
9375 | { | |
9376 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9377 | }, | |
1ba585e8 IT |
9378 | /* VEX_LEN_0F44_P_2 */ |
9379 | { | |
9380 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9381 | }, | |
43234a1e L |
9382 | /* VEX_LEN_0F45_P_0 */ |
9383 | { | |
9384 | { Bad_Opcode }, | |
9385 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9386 | }, | |
1ba585e8 IT |
9387 | /* VEX_LEN_0F45_P_2 */ |
9388 | { | |
9389 | { Bad_Opcode }, | |
9390 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9391 | }, | |
43234a1e L |
9392 | /* VEX_LEN_0F46_P_0 */ |
9393 | { | |
9394 | { Bad_Opcode }, | |
9395 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9396 | }, | |
1ba585e8 IT |
9397 | /* VEX_LEN_0F46_P_2 */ |
9398 | { | |
9399 | { Bad_Opcode }, | |
9400 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9401 | }, | |
43234a1e L |
9402 | /* VEX_LEN_0F47_P_0 */ |
9403 | { | |
9404 | { Bad_Opcode }, | |
9405 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9406 | }, | |
1ba585e8 IT |
9407 | /* VEX_LEN_0F47_P_2 */ |
9408 | { | |
9409 | { Bad_Opcode }, | |
9410 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9411 | }, | |
9412 | /* VEX_LEN_0F4A_P_0 */ | |
9413 | { | |
9414 | { Bad_Opcode }, | |
9415 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9416 | }, | |
9417 | /* VEX_LEN_0F4A_P_2 */ | |
9418 | { | |
9419 | { Bad_Opcode }, | |
9420 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9421 | }, | |
9422 | /* VEX_LEN_0F4B_P_0 */ | |
9423 | { | |
9424 | { Bad_Opcode }, | |
9425 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9426 | }, | |
43234a1e L |
9427 | /* VEX_LEN_0F4B_P_2 */ |
9428 | { | |
9429 | { Bad_Opcode }, | |
9430 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9431 | }, | |
9432 | ||
ec6f095a | 9433 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9434 | { |
ec6f095a | 9435 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9436 | }, |
9437 | ||
ec6f095a | 9438 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9439 | { |
ec6f095a L |
9440 | { "vzeroupper", { XX }, 0 }, |
9441 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9442 | }, |
9443 | ||
ec6f095a | 9444 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9445 | { |
ec6f095a | 9446 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9447 | }, |
9448 | ||
ec6f095a | 9449 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9450 | { |
ec6f095a | 9451 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9452 | }, |
9453 | ||
ec6f095a | 9454 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9455 | { |
ec6f095a | 9456 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9457 | }, |
9458 | ||
ec6f095a | 9459 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9460 | { |
ec6f095a | 9461 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9462 | }, |
9463 | ||
ec6f095a | 9464 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9465 | { |
ec6f095a | 9466 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9467 | }, |
9468 | ||
ec6f095a | 9469 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9470 | { |
ec6f095a | 9471 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9472 | }, |
9473 | ||
ec6f095a | 9474 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9475 | { |
ec6f095a | 9476 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9477 | }, |
9478 | ||
ec6f095a | 9479 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9480 | { |
ec6f095a | 9481 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9482 | }, |
9483 | ||
ec6f095a | 9484 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9485 | { |
58a211d2 | 9486 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9487 | }, |
9488 | ||
ec6f095a | 9489 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9490 | { |
ec6f095a | 9491 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9492 | }, |
9493 | ||
ec6f095a | 9494 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9495 | { |
ec6f095a | 9496 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9497 | }, |
9498 | ||
ec6f095a | 9499 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9500 | { |
58a211d2 | 9501 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9502 | }, |
9503 | ||
ec6f095a | 9504 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9505 | { |
9506 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9507 | }, | |
9508 | ||
1ba585e8 IT |
9509 | /* VEX_LEN_0F98_P_2 */ |
9510 | { | |
9511 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9512 | }, | |
9513 | ||
9514 | /* VEX_LEN_0F99_P_0 */ | |
9515 | { | |
9516 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9517 | }, | |
9518 | ||
9519 | /* VEX_LEN_0F99_P_2 */ | |
9520 | { | |
9521 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9522 | }, | |
9523 | ||
6c30d220 | 9524 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9525 | { |
ec6f095a | 9526 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9527 | }, |
9528 | ||
6c30d220 | 9529 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9530 | { |
ec6f095a | 9531 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9532 | }, |
9533 | ||
6c30d220 | 9534 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9535 | { |
b50c9f31 | 9536 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9537 | }, |
9538 | ||
6c30d220 | 9539 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9540 | { |
b50c9f31 | 9541 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9542 | }, |
9543 | ||
6c30d220 | 9544 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9545 | { |
ec6f095a | 9546 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9547 | }, |
9548 | ||
6c30d220 | 9549 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9550 | { |
ec6f095a | 9551 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9552 | }, |
9553 | ||
6c30d220 | 9554 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9555 | { |
6c30d220 L |
9556 | { Bad_Opcode }, |
9557 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9558 | }, |
9559 | ||
6c30d220 | 9560 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9561 | { |
6c30d220 L |
9562 | { Bad_Opcode }, |
9563 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9564 | }, |
9565 | ||
6c30d220 | 9566 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9567 | { |
6c30d220 L |
9568 | { Bad_Opcode }, |
9569 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9570 | }, |
9571 | ||
6c30d220 | 9572 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9573 | { |
6c30d220 L |
9574 | { Bad_Opcode }, |
9575 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9576 | }, |
9577 | ||
592a252b | 9578 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9579 | { |
ec6f095a | 9580 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9581 | }, |
9582 | ||
6c30d220 L |
9583 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9584 | { | |
9585 | { Bad_Opcode }, | |
9586 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9587 | }, | |
9588 | ||
592a252b | 9589 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9590 | { |
ec6f095a | 9591 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9592 | }, |
9593 | ||
f12dc422 L |
9594 | /* VEX_LEN_0F38F2_P_0 */ |
9595 | { | |
bf890a93 | 9596 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9597 | }, |
9598 | ||
9599 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9600 | { | |
bf890a93 | 9601 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9602 | }, |
9603 | ||
9604 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9605 | { | |
bf890a93 | 9606 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9607 | }, |
9608 | ||
9609 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9610 | { | |
bf890a93 | 9611 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9612 | }, |
9613 | ||
6c30d220 L |
9614 | /* VEX_LEN_0F38F5_P_0 */ |
9615 | { | |
bf890a93 | 9616 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9617 | }, |
9618 | ||
9619 | /* VEX_LEN_0F38F5_P_1 */ | |
9620 | { | |
bf890a93 | 9621 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9622 | }, |
9623 | ||
9624 | /* VEX_LEN_0F38F5_P_3 */ | |
9625 | { | |
bf890a93 | 9626 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9627 | }, |
9628 | ||
9629 | /* VEX_LEN_0F38F6_P_3 */ | |
9630 | { | |
bf890a93 | 9631 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9632 | }, |
9633 | ||
f12dc422 L |
9634 | /* VEX_LEN_0F38F7_P_0 */ |
9635 | { | |
bf890a93 | 9636 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9637 | }, |
9638 | ||
6c30d220 L |
9639 | /* VEX_LEN_0F38F7_P_1 */ |
9640 | { | |
bf890a93 | 9641 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9642 | }, |
9643 | ||
9644 | /* VEX_LEN_0F38F7_P_2 */ | |
9645 | { | |
bf890a93 | 9646 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9647 | }, |
9648 | ||
9649 | /* VEX_LEN_0F38F7_P_3 */ | |
9650 | { | |
bf890a93 | 9651 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9652 | }, |
9653 | ||
9654 | /* VEX_LEN_0F3A00_P_2 */ | |
9655 | { | |
9656 | { Bad_Opcode }, | |
9657 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9658 | }, | |
9659 | ||
9660 | /* VEX_LEN_0F3A01_P_2 */ | |
9661 | { | |
9662 | { Bad_Opcode }, | |
9663 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9664 | }, | |
9665 | ||
592a252b | 9666 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9667 | { |
592d1631 | 9668 | { Bad_Opcode }, |
592a252b | 9669 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9670 | }, |
9671 | ||
592a252b | 9672 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9673 | { |
b50c9f31 | 9674 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9675 | }, |
9676 | ||
592a252b | 9677 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9678 | { |
b50c9f31 | 9679 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9680 | }, |
9681 | ||
592a252b | 9682 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9683 | { |
bf890a93 | 9684 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9685 | }, |
9686 | ||
592a252b | 9687 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9688 | { |
bf890a93 | 9689 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9693 | { |
592d1631 | 9694 | { Bad_Opcode }, |
592a252b | 9695 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9696 | }, |
9697 | ||
592a252b | 9698 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9699 | { |
592d1631 | 9700 | { Bad_Opcode }, |
592a252b | 9701 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9702 | }, |
9703 | ||
592a252b | 9704 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9705 | { |
b50c9f31 | 9706 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9707 | }, |
9708 | ||
592a252b | 9709 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9710 | { |
ec6f095a | 9711 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9712 | }, |
9713 | ||
592a252b | 9714 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9715 | { |
bf890a93 | 9716 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9717 | }, |
9718 | ||
43234a1e L |
9719 | /* VEX_LEN_0F3A30_P_2 */ |
9720 | { | |
9721 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9722 | }, | |
9723 | ||
1ba585e8 IT |
9724 | /* VEX_LEN_0F3A31_P_2 */ |
9725 | { | |
9726 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9727 | }, | |
9728 | ||
43234a1e L |
9729 | /* VEX_LEN_0F3A32_P_2 */ |
9730 | { | |
9731 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9732 | }, | |
9733 | ||
1ba585e8 IT |
9734 | /* VEX_LEN_0F3A33_P_2 */ |
9735 | { | |
9736 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9737 | }, | |
9738 | ||
6c30d220 | 9739 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9740 | { |
6c30d220 L |
9741 | { Bad_Opcode }, |
9742 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9743 | }, |
9744 | ||
6c30d220 | 9745 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9746 | { |
6c30d220 L |
9747 | { Bad_Opcode }, |
9748 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9749 | }, | |
9750 | ||
9751 | /* VEX_LEN_0F3A41_P_2 */ | |
9752 | { | |
ec6f095a | 9753 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9754 | }, |
9755 | ||
6c30d220 | 9756 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9757 | { |
6c30d220 L |
9758 | { Bad_Opcode }, |
9759 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9760 | }, |
9761 | ||
592a252b | 9762 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9763 | { |
15c7c1d8 | 9764 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9765 | }, |
9766 | ||
592a252b | 9767 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9768 | { |
15c7c1d8 | 9769 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9770 | }, |
9771 | ||
592a252b | 9772 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9773 | { |
ec6f095a | 9774 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9778 | { |
ec6f095a | 9779 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9783 | { |
3a2430e0 | 9784 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9785 | }, |
9786 | ||
592a252b | 9787 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9788 | { |
3a2430e0 | 9789 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9790 | }, |
9791 | ||
592a252b | 9792 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9793 | { |
3a2430e0 | 9794 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9795 | }, |
9796 | ||
592a252b | 9797 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9798 | { |
3a2430e0 | 9799 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9800 | }, |
9801 | ||
592a252b | 9802 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9803 | { |
3a2430e0 | 9804 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9805 | }, |
9806 | ||
592a252b | 9807 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9808 | { |
3a2430e0 | 9809 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9810 | }, |
9811 | ||
592a252b | 9812 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9813 | { |
3a2430e0 | 9814 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9815 | }, |
9816 | ||
592a252b | 9817 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9818 | { |
3a2430e0 | 9819 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9820 | }, |
9821 | ||
592a252b | 9822 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9823 | { |
ec6f095a | 9824 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9825 | }, |
4c807e72 | 9826 | |
6c30d220 L |
9827 | /* VEX_LEN_0F3AF0_P_3 */ |
9828 | { | |
bf890a93 | 9829 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9830 | }, |
9831 | ||
ff688e1f L |
9832 | /* VEX_LEN_0FXOP_08_CC */ |
9833 | { | |
be92cb14 | 9834 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9835 | }, |
9836 | ||
9837 | /* VEX_LEN_0FXOP_08_CD */ | |
9838 | { | |
be92cb14 | 9839 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9840 | }, |
9841 | ||
9842 | /* VEX_LEN_0FXOP_08_CE */ | |
9843 | { | |
be92cb14 | 9844 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9845 | }, |
9846 | ||
9847 | /* VEX_LEN_0FXOP_08_CF */ | |
9848 | { | |
be92cb14 | 9849 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9850 | }, |
9851 | ||
9852 | /* VEX_LEN_0FXOP_08_EC */ | |
9853 | { | |
be92cb14 | 9854 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9855 | }, |
9856 | ||
9857 | /* VEX_LEN_0FXOP_08_ED */ | |
9858 | { | |
be92cb14 | 9859 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9860 | }, |
9861 | ||
9862 | /* VEX_LEN_0FXOP_08_EE */ | |
9863 | { | |
be92cb14 | 9864 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9865 | }, |
9866 | ||
9867 | /* VEX_LEN_0FXOP_08_EF */ | |
9868 | { | |
be92cb14 | 9869 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9870 | }, |
9871 | ||
592a252b | 9872 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9873 | { |
bf890a93 IT |
9874 | { "vfrczps", { XM, EXxmm }, 0 }, |
9875 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9876 | }, |
4c807e72 | 9877 | |
592a252b | 9878 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9879 | { |
bf890a93 IT |
9880 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9881 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9882 | }, |
331d2d0d L |
9883 | }; |
9884 | ||
ad692897 | 9885 | #include "i386-dis-evex-len.h" |
04e2a182 | 9886 | |
9e30b8e0 | 9887 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9888 | { |
9889 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9890 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9891 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9892 | }, |
9893 | { | |
9894 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9895 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9896 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9897 | }, |
9898 | { | |
9899 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9900 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9901 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9902 | }, |
9903 | { | |
9904 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9905 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9906 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9907 | }, |
9908 | { | |
9909 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9910 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9911 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9912 | }, |
9913 | { | |
9914 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9915 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9916 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9917 | }, |
9918 | { | |
ec6f095a L |
9919 | /* VEX_W_0F45_P_0_LEN_1 */ |
9920 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9921 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9922 | }, |
9923 | { | |
ec6f095a L |
9924 | /* VEX_W_0F45_P_2_LEN_1 */ |
9925 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9926 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9927 | }, |
9928 | { | |
ec6f095a L |
9929 | /* VEX_W_0F46_P_0_LEN_1 */ |
9930 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9931 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9932 | }, |
9933 | { | |
ec6f095a L |
9934 | /* VEX_W_0F46_P_2_LEN_1 */ |
9935 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9936 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9937 | }, |
9938 | { | |
ec6f095a L |
9939 | /* VEX_W_0F47_P_0_LEN_1 */ |
9940 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9941 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9942 | }, |
9943 | { | |
ec6f095a L |
9944 | /* VEX_W_0F47_P_2_LEN_1 */ |
9945 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9946 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9947 | }, |
9948 | { | |
ec6f095a L |
9949 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9950 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9951 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9952 | }, |
9953 | { | |
ec6f095a L |
9954 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9955 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9956 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9957 | }, |
9958 | { | |
ec6f095a L |
9959 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9960 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9961 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9962 | }, |
9963 | { | |
ec6f095a L |
9964 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9965 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9966 | }, |
9967 | { | |
ec6f095a L |
9968 | /* VEX_W_0F90_P_0_LEN_0 */ |
9969 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9970 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9971 | }, |
9972 | { | |
ec6f095a L |
9973 | /* VEX_W_0F90_P_2_LEN_0 */ |
9974 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9975 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9976 | }, |
9977 | { | |
ec6f095a L |
9978 | /* VEX_W_0F91_P_0_LEN_0 */ |
9979 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9980 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9981 | }, |
9982 | { | |
ec6f095a L |
9983 | /* VEX_W_0F91_P_2_LEN_0 */ |
9984 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9985 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9986 | }, |
9987 | { | |
ec6f095a L |
9988 | /* VEX_W_0F92_P_0_LEN_0 */ |
9989 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9990 | }, |
9991 | { | |
ec6f095a L |
9992 | /* VEX_W_0F92_P_2_LEN_0 */ |
9993 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9994 | }, |
9e30b8e0 | 9995 | { |
ec6f095a L |
9996 | /* VEX_W_0F93_P_0_LEN_0 */ |
9997 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9998 | }, |
9999 | { | |
ec6f095a L |
10000 | /* VEX_W_0F93_P_2_LEN_0 */ |
10001 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10002 | }, |
9e30b8e0 | 10003 | { |
ec6f095a L |
10004 | /* VEX_W_0F98_P_0_LEN_0 */ |
10005 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10006 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10007 | }, |
10008 | { | |
ec6f095a L |
10009 | /* VEX_W_0F98_P_2_LEN_0 */ |
10010 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10011 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10012 | }, |
10013 | { | |
ec6f095a L |
10014 | /* VEX_W_0F99_P_0_LEN_0 */ |
10015 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10016 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10017 | }, |
10018 | { | |
ec6f095a L |
10019 | /* VEX_W_0F99_P_2_LEN_0 */ |
10020 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10021 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10022 | }, |
9e30b8e0 | 10023 | { |
592a252b | 10024 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10025 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10026 | }, |
10027 | { | |
592a252b | 10028 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10029 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10030 | }, |
10031 | { | |
592a252b | 10032 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10033 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10034 | }, |
10035 | { | |
592a252b | 10036 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10037 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10038 | }, |
6c30d220 L |
10039 | { |
10040 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10041 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10042 | }, |
bcf2684f | 10043 | { |
6c30d220 | 10044 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10045 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10046 | }, |
9e30b8e0 | 10047 | { |
6c30d220 | 10048 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10049 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10050 | }, |
10051 | { | |
592a252b | 10052 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10053 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10054 | }, |
53aa04a0 | 10055 | { |
592a252b | 10056 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10057 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10058 | }, |
10059 | { | |
592a252b | 10060 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10061 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10062 | }, |
10063 | { | |
592a252b | 10064 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10065 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10066 | }, |
10067 | { | |
592a252b | 10068 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10069 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10070 | }, |
6c30d220 L |
10071 | { |
10072 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10073 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10074 | }, |
6c30d220 L |
10075 | { |
10076 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10077 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10078 | }, |
10079 | { | |
10080 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10081 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10082 | }, |
10083 | { | |
10084 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10085 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10086 | }, |
10087 | { | |
10088 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10089 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10090 | }, |
10091 | { | |
10092 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10093 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10094 | }, |
10095 | { | |
10096 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10097 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10098 | }, |
48521003 IT |
10099 | { |
10100 | /* VEX_W_0F38CF_P_2 */ | |
10101 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10102 | }, | |
6c30d220 L |
10103 | { |
10104 | /* VEX_W_0F3A00_P_2 */ | |
10105 | { Bad_Opcode }, | |
bf890a93 | 10106 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10107 | }, |
10108 | { | |
10109 | /* VEX_W_0F3A01_P_2 */ | |
10110 | { Bad_Opcode }, | |
bf890a93 | 10111 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10112 | }, |
10113 | { | |
10114 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10115 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10116 | }, |
9e30b8e0 | 10117 | { |
592a252b | 10118 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10119 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10120 | }, |
10121 | { | |
592a252b | 10122 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10123 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10124 | }, |
10125 | { | |
592a252b | 10126 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10127 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10128 | }, |
9e30b8e0 | 10129 | { |
592a252b | 10130 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10131 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10132 | }, |
10133 | { | |
592a252b | 10134 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10135 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10136 | }, |
43234a1e | 10137 | { |
1ba585e8 | 10138 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10139 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10140 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10141 | }, |
10142 | { | |
1ba585e8 | 10143 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10144 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10145 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10146 | }, |
10147 | { | |
10148 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10149 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10150 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10151 | }, |
1ba585e8 IT |
10152 | { |
10153 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10154 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10155 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10156 | }, |
6c30d220 L |
10157 | { |
10158 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10159 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10160 | }, |
10161 | { | |
10162 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10163 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10164 | }, |
6c30d220 L |
10165 | { |
10166 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10167 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10168 | }, |
a683cc34 | 10169 | { |
592a252b | 10170 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10171 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10172 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10173 | }, |
10174 | { | |
592a252b | 10175 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10176 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10177 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10178 | }, |
9e30b8e0 | 10179 | { |
592a252b | 10180 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10181 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10182 | }, |
10183 | { | |
592a252b | 10184 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10185 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10186 | }, |
10187 | { | |
592a252b | 10188 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10189 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10190 | }, |
48521003 IT |
10191 | { |
10192 | /* VEX_W_0F3ACE_P_2 */ | |
10193 | { Bad_Opcode }, | |
10194 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10195 | }, | |
10196 | { | |
10197 | /* VEX_W_0F3ACF_P_2 */ | |
10198 | { Bad_Opcode }, | |
10199 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10200 | }, | |
ad692897 L |
10201 | |
10202 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10203 | }; |
10204 | ||
10205 | static const struct dis386 mod_table[][2] = { | |
10206 | { | |
10207 | /* MOD_8D */ | |
bf890a93 | 10208 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10209 | }, |
42164a71 L |
10210 | { |
10211 | /* MOD_C6_REG_7 */ | |
10212 | { Bad_Opcode }, | |
10213 | { RM_TABLE (RM_C6_REG_7) }, | |
10214 | }, | |
10215 | { | |
10216 | /* MOD_C7_REG_7 */ | |
10217 | { Bad_Opcode }, | |
10218 | { RM_TABLE (RM_C7_REG_7) }, | |
10219 | }, | |
4a357820 MZ |
10220 | { |
10221 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 10222 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
10223 | }, |
10224 | { | |
10225 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 10226 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 10227 | }, |
9e30b8e0 L |
10228 | { |
10229 | /* MOD_0F01_REG_0 */ | |
10230 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10231 | { RM_TABLE (RM_0F01_REG_0) }, | |
10232 | }, | |
10233 | { | |
10234 | /* MOD_0F01_REG_1 */ | |
10235 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10236 | { RM_TABLE (RM_0F01_REG_1) }, | |
10237 | }, | |
10238 | { | |
10239 | /* MOD_0F01_REG_2 */ | |
10240 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10241 | { RM_TABLE (RM_0F01_REG_2) }, | |
10242 | }, | |
10243 | { | |
10244 | /* MOD_0F01_REG_3 */ | |
10245 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10246 | { RM_TABLE (RM_0F01_REG_3) }, | |
10247 | }, | |
8eab4136 L |
10248 | { |
10249 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10250 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10251 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10252 | }, |
9e30b8e0 L |
10253 | { |
10254 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10255 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10256 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10257 | }, |
10258 | { | |
10259 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
10260 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
10261 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
10262 | }, |
10263 | { | |
10264 | /* MOD_0F13 */ | |
507bd325 | 10265 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10266 | }, |
10267 | { | |
10268 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
10269 | { "movhps", { XM, EXq }, 0 }, |
10270 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10271 | }, |
10272 | { | |
10273 | /* MOD_0F17 */ | |
507bd325 | 10274 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10275 | }, |
10276 | { | |
10277 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10278 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10279 | }, |
10280 | { | |
10281 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10282 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10283 | }, |
10284 | { | |
10285 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10286 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10287 | }, |
10288 | { | |
10289 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10290 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10291 | }, |
d7189fa5 RM |
10292 | { |
10293 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10294 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10295 | }, |
10296 | { | |
10297 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10298 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10299 | }, |
10300 | { | |
10301 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10302 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10303 | }, |
10304 | { | |
10305 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10306 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10307 | }, |
7e8b059b L |
10308 | { |
10309 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10310 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10311 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10312 | }, |
10313 | { | |
10314 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10315 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10316 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10317 | }, |
10318 | { | |
10319 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10320 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10321 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10322 | }, |
c48935d7 IT |
10323 | { |
10324 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10325 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10326 | { "nopQ", { Ev }, 0 }, |
10327 | }, | |
603555e5 L |
10328 | { |
10329 | /* MOD_0F1E_PREFIX_1 */ | |
10330 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10331 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10332 | }, |
b844680a | 10333 | { |
92fddf8e | 10334 | /* MOD_0F24 */ |
7bb15c6f | 10335 | { Bad_Opcode }, |
bf890a93 | 10336 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10337 | }, |
10338 | { | |
92fddf8e | 10339 | /* MOD_0F26 */ |
592d1631 | 10340 | { Bad_Opcode }, |
bf890a93 | 10341 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10342 | }, |
75c135a8 L |
10343 | { |
10344 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10345 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10346 | }, |
10347 | { | |
10348 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10349 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10350 | }, |
10351 | { | |
10352 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10353 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10354 | }, |
10355 | { | |
10356 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10357 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10358 | }, |
10359 | { | |
10360 | /* MOD_0F51 */ | |
592d1631 | 10361 | { Bad_Opcode }, |
507bd325 | 10362 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10363 | }, |
b844680a | 10364 | { |
1ceb70f8 | 10365 | /* MOD_0F71_REG_2 */ |
592d1631 | 10366 | { Bad_Opcode }, |
bf890a93 | 10367 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10368 | }, |
10369 | { | |
1ceb70f8 | 10370 | /* MOD_0F71_REG_4 */ |
592d1631 | 10371 | { Bad_Opcode }, |
bf890a93 | 10372 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10373 | }, |
10374 | { | |
1ceb70f8 | 10375 | /* MOD_0F71_REG_6 */ |
592d1631 | 10376 | { Bad_Opcode }, |
bf890a93 | 10377 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10378 | }, |
10379 | { | |
1ceb70f8 | 10380 | /* MOD_0F72_REG_2 */ |
592d1631 | 10381 | { Bad_Opcode }, |
bf890a93 | 10382 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10383 | }, |
10384 | { | |
1ceb70f8 | 10385 | /* MOD_0F72_REG_4 */ |
592d1631 | 10386 | { Bad_Opcode }, |
bf890a93 | 10387 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10388 | }, |
10389 | { | |
1ceb70f8 | 10390 | /* MOD_0F72_REG_6 */ |
592d1631 | 10391 | { Bad_Opcode }, |
bf890a93 | 10392 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10393 | }, |
10394 | { | |
1ceb70f8 | 10395 | /* MOD_0F73_REG_2 */ |
592d1631 | 10396 | { Bad_Opcode }, |
bf890a93 | 10397 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10398 | }, |
10399 | { | |
1ceb70f8 | 10400 | /* MOD_0F73_REG_3 */ |
592d1631 | 10401 | { Bad_Opcode }, |
c0f3af97 L |
10402 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10403 | }, | |
10404 | { | |
10405 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10406 | { Bad_Opcode }, |
bf890a93 | 10407 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10408 | }, |
10409 | { | |
10410 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10411 | { Bad_Opcode }, |
c0f3af97 L |
10412 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10413 | }, | |
10414 | { | |
10415 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10416 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10417 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10418 | }, |
10419 | { | |
10420 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10421 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10422 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10423 | }, |
10424 | { | |
10425 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10426 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10427 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10428 | }, |
10429 | { | |
10430 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10431 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10432 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10433 | }, |
10434 | { | |
10435 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10436 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10437 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10438 | }, |
10439 | { | |
10440 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10441 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10442 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10443 | }, |
10444 | { | |
10445 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10446 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10447 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10448 | }, |
10449 | { | |
10450 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10451 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10452 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10453 | }, |
10454 | { | |
10455 | /* MOD_0FB2 */ | |
bf890a93 | 10456 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10457 | }, |
10458 | { | |
10459 | /* MOD_0FB4 */ | |
bf890a93 | 10460 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10461 | }, |
10462 | { | |
10463 | /* MOD_0FB5 */ | |
bf890a93 | 10464 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10465 | }, |
a8484f96 L |
10466 | { |
10467 | /* MOD_0FC3 */ | |
f8687e93 | 10468 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10469 | }, |
963f3586 IT |
10470 | { |
10471 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10472 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10473 | }, |
10474 | { | |
10475 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10476 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10477 | }, |
10478 | { | |
10479 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10480 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10481 | }, |
c0f3af97 L |
10482 | { |
10483 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10484 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10485 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10486 | }, |
10487 | { | |
10488 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10489 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10490 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10491 | }, |
10492 | { | |
10493 | /* MOD_0FD7 */ | |
592d1631 | 10494 | { Bad_Opcode }, |
bf890a93 | 10495 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10496 | }, |
10497 | { | |
10498 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10499 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10500 | }, |
10501 | { | |
10502 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10503 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10504 | }, |
10505 | { | |
10506 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10507 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10508 | }, |
603555e5 L |
10509 | { |
10510 | /* MOD_0F38F5_PREFIX_2 */ | |
10511 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10512 | }, | |
10513 | { | |
10514 | /* MOD_0F38F6_PREFIX_0 */ | |
10515 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10516 | }, | |
5d79adc4 L |
10517 | { |
10518 | /* MOD_0F38F8_PREFIX_1 */ | |
10519 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10520 | }, | |
c0a30a9f L |
10521 | { |
10522 | /* MOD_0F38F8_PREFIX_2 */ | |
10523 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10524 | }, | |
5d79adc4 L |
10525 | { |
10526 | /* MOD_0F38F8_PREFIX_3 */ | |
10527 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10528 | }, | |
c0a30a9f L |
10529 | { |
10530 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10531 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10532 | }, |
c0f3af97 L |
10533 | { |
10534 | /* MOD_62_32BIT */ | |
bf890a93 | 10535 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10536 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10537 | }, |
10538 | { | |
10539 | /* MOD_C4_32BIT */ | |
bf890a93 | 10540 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10541 | { VEX_C4_TABLE (VEX_0F) }, |
10542 | }, | |
10543 | { | |
10544 | /* MOD_C5_32BIT */ | |
bf890a93 | 10545 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10546 | { VEX_C5_TABLE (VEX_0F) }, |
10547 | }, | |
10548 | { | |
592a252b L |
10549 | /* MOD_VEX_0F12_PREFIX_0 */ |
10550 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10551 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10552 | }, |
10553 | { | |
592a252b L |
10554 | /* MOD_VEX_0F13 */ |
10555 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10556 | }, |
10557 | { | |
592a252b L |
10558 | /* MOD_VEX_0F16_PREFIX_0 */ |
10559 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10560 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10561 | }, |
10562 | { | |
592a252b L |
10563 | /* MOD_VEX_0F17 */ |
10564 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10565 | }, |
10566 | { | |
592a252b | 10567 | /* MOD_VEX_0F2B */ |
ec6f095a | 10568 | { "vmovntpX", { Mx, XM }, 0 }, |
c0f3af97 | 10569 | }, |
ab4e4ed5 AF |
10570 | { |
10571 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10572 | { Bad_Opcode }, | |
10573 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10574 | }, | |
10575 | { | |
10576 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10577 | { Bad_Opcode }, | |
10578 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10579 | }, | |
10580 | { | |
10581 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10582 | { Bad_Opcode }, | |
10583 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10584 | }, | |
10585 | { | |
10586 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10587 | { Bad_Opcode }, | |
10588 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10589 | }, | |
10590 | { | |
10591 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10592 | { Bad_Opcode }, | |
10593 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10594 | }, | |
10595 | { | |
10596 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10597 | { Bad_Opcode }, | |
10598 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10599 | }, | |
10600 | { | |
10601 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10602 | { Bad_Opcode }, | |
10603 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10604 | }, | |
10605 | { | |
10606 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10607 | { Bad_Opcode }, | |
10608 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10609 | }, | |
10610 | { | |
10611 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10612 | { Bad_Opcode }, | |
10613 | { "knotw", { MaskG, MaskR }, 0 }, | |
10614 | }, | |
10615 | { | |
10616 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10617 | { Bad_Opcode }, | |
10618 | { "knotq", { MaskG, MaskR }, 0 }, | |
10619 | }, | |
10620 | { | |
10621 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10622 | { Bad_Opcode }, | |
10623 | { "knotb", { MaskG, MaskR }, 0 }, | |
10624 | }, | |
10625 | { | |
10626 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10627 | { Bad_Opcode }, | |
10628 | { "knotd", { MaskG, MaskR }, 0 }, | |
10629 | }, | |
10630 | { | |
10631 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10632 | { Bad_Opcode }, | |
10633 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10634 | }, | |
10635 | { | |
10636 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10637 | { Bad_Opcode }, | |
10638 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10639 | }, | |
10640 | { | |
10641 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10642 | { Bad_Opcode }, | |
10643 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10644 | }, | |
10645 | { | |
10646 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10647 | { Bad_Opcode }, | |
10648 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10649 | }, | |
10650 | { | |
10651 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10652 | { Bad_Opcode }, | |
10653 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10654 | }, | |
10655 | { | |
10656 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10657 | { Bad_Opcode }, | |
10658 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10659 | }, | |
10660 | { | |
10661 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10662 | { Bad_Opcode }, | |
10663 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10664 | }, | |
10665 | { | |
10666 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10667 | { Bad_Opcode }, | |
10668 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10669 | }, | |
10670 | { | |
10671 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10672 | { Bad_Opcode }, | |
10673 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10674 | }, | |
10675 | { | |
10676 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10677 | { Bad_Opcode }, | |
10678 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10679 | }, | |
10680 | { | |
10681 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10682 | { Bad_Opcode }, | |
10683 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10684 | }, | |
10685 | { | |
10686 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10687 | { Bad_Opcode }, | |
10688 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10689 | }, | |
10690 | { | |
10691 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10692 | { Bad_Opcode }, | |
10693 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10694 | }, | |
10695 | { | |
10696 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10697 | { Bad_Opcode }, | |
10698 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10699 | }, | |
10700 | { | |
10701 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10702 | { Bad_Opcode }, | |
10703 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10704 | }, | |
10705 | { | |
10706 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10707 | { Bad_Opcode }, | |
10708 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10709 | }, | |
10710 | { | |
10711 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10712 | { Bad_Opcode }, | |
10713 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10714 | }, | |
10715 | { | |
10716 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10717 | { Bad_Opcode }, | |
10718 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10719 | }, | |
10720 | { | |
10721 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10722 | { Bad_Opcode }, | |
10723 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10724 | }, | |
c0f3af97 | 10725 | { |
592a252b | 10726 | /* MOD_VEX_0F50 */ |
592d1631 | 10727 | { Bad_Opcode }, |
ec6f095a | 10728 | { "vmovmskpX", { Gdq, XS }, 0 }, |
c0f3af97 L |
10729 | }, |
10730 | { | |
592a252b | 10731 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10732 | { Bad_Opcode }, |
592a252b | 10733 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10734 | }, |
10735 | { | |
592a252b | 10736 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10737 | { Bad_Opcode }, |
592a252b | 10738 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10739 | }, |
10740 | { | |
592a252b | 10741 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10742 | { Bad_Opcode }, |
592a252b | 10743 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10744 | }, |
10745 | { | |
592a252b | 10746 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10747 | { Bad_Opcode }, |
592a252b | 10748 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10749 | }, |
d8faab4e | 10750 | { |
592a252b | 10751 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10752 | { Bad_Opcode }, |
592a252b | 10753 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10754 | }, |
10755 | { | |
592a252b | 10756 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10757 | { Bad_Opcode }, |
592a252b | 10758 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10759 | }, |
876d4bfa | 10760 | { |
592a252b | 10761 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10762 | { Bad_Opcode }, |
592a252b | 10763 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10764 | }, |
10765 | { | |
592a252b | 10766 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10767 | { Bad_Opcode }, |
592a252b | 10768 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10769 | }, |
10770 | { | |
592a252b | 10771 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10772 | { Bad_Opcode }, |
592a252b | 10773 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10777 | { Bad_Opcode }, |
592a252b | 10778 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10779 | }, |
ab4e4ed5 AF |
10780 | { |
10781 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10782 | { "kmovw", { Ew, MaskG }, 0 }, | |
10783 | { Bad_Opcode }, | |
10784 | }, | |
10785 | { | |
10786 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10787 | { "kmovq", { Eq, MaskG }, 0 }, | |
10788 | { Bad_Opcode }, | |
10789 | }, | |
10790 | { | |
10791 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10792 | { "kmovb", { Eb, MaskG }, 0 }, | |
10793 | { Bad_Opcode }, | |
10794 | }, | |
10795 | { | |
10796 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10797 | { "kmovd", { Ed, MaskG }, 0 }, | |
10798 | { Bad_Opcode }, | |
10799 | }, | |
10800 | { | |
10801 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10802 | { Bad_Opcode }, | |
10803 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10804 | }, | |
10805 | { | |
10806 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10807 | { Bad_Opcode }, | |
10808 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10809 | }, | |
10810 | { | |
58a211d2 | 10811 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10812 | { Bad_Opcode }, |
58a211d2 | 10813 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10814 | }, |
10815 | { | |
10816 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10817 | { Bad_Opcode }, | |
10818 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10819 | }, | |
10820 | { | |
10821 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10822 | { Bad_Opcode }, | |
10823 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10824 | }, | |
10825 | { | |
58a211d2 | 10826 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10827 | { Bad_Opcode }, |
58a211d2 | 10828 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10829 | }, |
10830 | { | |
10831 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10832 | { Bad_Opcode }, | |
10833 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10834 | }, | |
10835 | { | |
10836 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10837 | { Bad_Opcode }, | |
10838 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10839 | }, | |
10840 | { | |
10841 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10842 | { Bad_Opcode }, | |
10843 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10844 | }, | |
10845 | { | |
10846 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10847 | { Bad_Opcode }, | |
10848 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10849 | }, | |
10850 | { | |
10851 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10852 | { Bad_Opcode }, | |
10853 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10854 | }, | |
10855 | { | |
10856 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10857 | { Bad_Opcode }, | |
10858 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10859 | }, | |
10860 | { | |
10861 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10862 | { Bad_Opcode }, | |
10863 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10864 | }, | |
10865 | { | |
10866 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10867 | { Bad_Opcode }, | |
10868 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10869 | }, | |
876d4bfa | 10870 | { |
592a252b L |
10871 | /* MOD_VEX_0FAE_REG_2 */ |
10872 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10873 | }, |
bbedc832 | 10874 | { |
592a252b L |
10875 | /* MOD_VEX_0FAE_REG_3 */ |
10876 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10877 | }, |
144c41d9 | 10878 | { |
592a252b | 10879 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10880 | { Bad_Opcode }, |
ec6f095a | 10881 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10882 | }, |
1afd85e3 | 10883 | { |
592a252b | 10884 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10885 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10886 | }, |
10887 | { | |
592a252b | 10888 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10889 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10890 | }, |
75c135a8 | 10891 | { |
592a252b L |
10892 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10893 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10894 | }, |
1afd85e3 | 10895 | { |
592a252b | 10896 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10897 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10898 | }, |
75c135a8 | 10899 | { |
592a252b L |
10900 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10901 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10902 | }, |
1afd85e3 | 10903 | { |
592a252b L |
10904 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10905 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10906 | }, |
10907 | { | |
592a252b L |
10908 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10909 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10910 | }, |
10911 | { | |
592a252b L |
10912 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10913 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10914 | }, |
6c30d220 L |
10915 | { |
10916 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10917 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10918 | }, | |
10919 | { | |
10920 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10921 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10922 | }, |
10923 | { | |
10924 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10925 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10926 | }, |
ab4e4ed5 AF |
10927 | { |
10928 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10929 | { Bad_Opcode }, | |
10930 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10931 | }, | |
10932 | { | |
10933 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10934 | { Bad_Opcode }, | |
10935 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10936 | }, | |
10937 | { | |
10938 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10939 | { Bad_Opcode }, | |
10940 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10941 | }, | |
10942 | { | |
10943 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10944 | { Bad_Opcode }, | |
10945 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10946 | }, | |
10947 | { | |
10948 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10949 | { Bad_Opcode }, | |
10950 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10951 | }, | |
10952 | { | |
10953 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10954 | { Bad_Opcode }, | |
10955 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10956 | }, | |
10957 | { | |
10958 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10959 | { Bad_Opcode }, | |
10960 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10961 | }, | |
10962 | { | |
10963 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10964 | { Bad_Opcode }, | |
10965 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10966 | }, | |
ad692897 L |
10967 | |
10968 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10969 | }; |
10970 | ||
1ceb70f8 | 10971 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10972 | { |
10973 | /* RM_C6_REG_7 */ | |
bf890a93 | 10974 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10975 | }, |
10976 | { | |
10977 | /* RM_C7_REG_7 */ | |
376cd056 | 10978 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10979 | }, |
b844680a | 10980 | { |
1ceb70f8 | 10981 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10982 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10983 | { "vmcall", { Skip_MODRM }, 0 }, |
10984 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10985 | { "vmresume", { Skip_MODRM }, 0 }, | |
10986 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10987 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10988 | }, |
10989 | { | |
1ceb70f8 | 10990 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10991 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10992 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10993 | { "clac", { Skip_MODRM }, 0 }, | |
10994 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10995 | { Bad_Opcode }, |
10996 | { Bad_Opcode }, | |
10997 | { Bad_Opcode }, | |
bf890a93 | 10998 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10999 | }, |
475a2301 L |
11000 | { |
11001 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11002 | { "xgetbv", { Skip_MODRM }, 0 }, |
11003 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11004 | { Bad_Opcode }, |
11005 | { Bad_Opcode }, | |
bf890a93 IT |
11006 | { "vmfunc", { Skip_MODRM }, 0 }, |
11007 | { "xend", { Skip_MODRM }, 0 }, | |
11008 | { "xtest", { Skip_MODRM }, 0 }, | |
11009 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11010 | }, |
b844680a | 11011 | { |
1ceb70f8 | 11012 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
11013 | { "vmrun", { Skip_MODRM }, 0 }, |
11014 | { "vmmcall", { Skip_MODRM }, 0 }, | |
11015 | { "vmload", { Skip_MODRM }, 0 }, | |
11016 | { "vmsave", { Skip_MODRM }, 0 }, | |
11017 | { "stgi", { Skip_MODRM }, 0 }, | |
11018 | { "clgi", { Skip_MODRM }, 0 }, | |
11019 | { "skinit", { Skip_MODRM }, 0 }, | |
11020 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11021 | }, |
8eab4136 | 11022 | { |
f8687e93 JB |
11023 | /* RM_0F01_REG_5_MOD_3 */ |
11024 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
8eab4136 | 11025 | { Bad_Opcode }, |
f8687e93 | 11026 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11027 | { Bad_Opcode }, |
11028 | { Bad_Opcode }, | |
11029 | { Bad_Opcode }, | |
11030 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11031 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11032 | }, | |
4e7d34a6 | 11033 | { |
f8687e93 | 11034 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11035 | { "swapgs", { Skip_MODRM }, 0 }, |
11036 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11037 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11038 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11039 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11040 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11041 | }, |
603555e5 | 11042 | { |
f8687e93 | 11043 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11044 | { "nopQ", { Ev }, 0 }, |
11045 | { "nopQ", { Ev }, 0 }, | |
11046 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11047 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11048 | { "nopQ", { Ev }, 0 }, | |
11049 | { "nopQ", { Ev }, 0 }, | |
11050 | { "nopQ", { Ev }, 0 }, | |
11051 | { "nopQ", { Ev }, 0 }, | |
11052 | }, | |
b844680a | 11053 | { |
f8687e93 | 11054 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11055 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11056 | }, |
bbedc832 | 11057 | { |
f8687e93 | 11058 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11059 | { "sfence", { Skip_MODRM }, 0 }, |
11060 | ||
144c41d9 | 11061 | }, |
b844680a L |
11062 | }; |
11063 | ||
c608c12e AM |
11064 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11065 | ||
f16cd0d5 L |
11066 | /* We use the high bit to indicate different name for the same |
11067 | prefix. */ | |
f16cd0d5 | 11068 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11069 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11070 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11071 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11072 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11073 | |
1d67fe3b TT |
11074 | /* Remember if the current op is a jump instruction. */ |
11075 | static bfd_boolean op_is_jump = FALSE; | |
11076 | ||
f16cd0d5 | 11077 | static int |
26ca5450 | 11078 | ckprefix (void) |
252b5132 | 11079 | { |
f16cd0d5 | 11080 | int newrex, i, length; |
52b15da3 | 11081 | rex = 0; |
c0f3af97 | 11082 | rex_ignored = 0; |
252b5132 | 11083 | prefixes = 0; |
7d421014 | 11084 | used_prefixes = 0; |
52b15da3 | 11085 | rex_used = 0; |
f16cd0d5 L |
11086 | last_lock_prefix = -1; |
11087 | last_repz_prefix = -1; | |
11088 | last_repnz_prefix = -1; | |
11089 | last_data_prefix = -1; | |
11090 | last_addr_prefix = -1; | |
11091 | last_rex_prefix = -1; | |
11092 | last_seg_prefix = -1; | |
d9949a36 | 11093 | fwait_prefix = -1; |
285ca992 | 11094 | active_seg_prefix = 0; |
f310f33d L |
11095 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11096 | all_prefixes[i] = 0; | |
11097 | i = 0; | |
f16cd0d5 L |
11098 | length = 0; |
11099 | /* The maximum instruction length is 15bytes. */ | |
11100 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11101 | { |
11102 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11103 | newrex = 0; |
252b5132 RH |
11104 | switch (*codep) |
11105 | { | |
52b15da3 JH |
11106 | /* REX prefixes family. */ |
11107 | case 0x40: | |
11108 | case 0x41: | |
11109 | case 0x42: | |
11110 | case 0x43: | |
11111 | case 0x44: | |
11112 | case 0x45: | |
11113 | case 0x46: | |
11114 | case 0x47: | |
11115 | case 0x48: | |
11116 | case 0x49: | |
11117 | case 0x4a: | |
11118 | case 0x4b: | |
11119 | case 0x4c: | |
11120 | case 0x4d: | |
11121 | case 0x4e: | |
11122 | case 0x4f: | |
f16cd0d5 L |
11123 | if (address_mode == mode_64bit) |
11124 | newrex = *codep; | |
11125 | else | |
11126 | return 1; | |
11127 | last_rex_prefix = i; | |
52b15da3 | 11128 | break; |
252b5132 RH |
11129 | case 0xf3: |
11130 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11131 | last_repz_prefix = i; |
252b5132 RH |
11132 | break; |
11133 | case 0xf2: | |
11134 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11135 | last_repnz_prefix = i; |
252b5132 RH |
11136 | break; |
11137 | case 0xf0: | |
11138 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11139 | last_lock_prefix = i; |
252b5132 RH |
11140 | break; |
11141 | case 0x2e: | |
11142 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11143 | last_seg_prefix = i; |
285ca992 | 11144 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11145 | break; |
11146 | case 0x36: | |
11147 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11148 | last_seg_prefix = i; |
285ca992 | 11149 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11150 | break; |
11151 | case 0x3e: | |
11152 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11153 | last_seg_prefix = i; |
285ca992 | 11154 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11155 | break; |
11156 | case 0x26: | |
11157 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11158 | last_seg_prefix = i; |
285ca992 | 11159 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11160 | break; |
11161 | case 0x64: | |
11162 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11163 | last_seg_prefix = i; |
285ca992 | 11164 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11165 | break; |
11166 | case 0x65: | |
11167 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11168 | last_seg_prefix = i; |
285ca992 | 11169 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11170 | break; |
11171 | case 0x66: | |
11172 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11173 | last_data_prefix = i; |
252b5132 RH |
11174 | break; |
11175 | case 0x67: | |
11176 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11177 | last_addr_prefix = i; |
252b5132 | 11178 | break; |
5076851f | 11179 | case FWAIT_OPCODE: |
252b5132 RH |
11180 | /* fwait is really an instruction. If there are prefixes |
11181 | before the fwait, they belong to the fwait, *not* to the | |
11182 | following instruction. */ | |
d9949a36 | 11183 | fwait_prefix = i; |
3e7d61b2 | 11184 | if (prefixes || rex) |
252b5132 RH |
11185 | { |
11186 | prefixes |= PREFIX_FWAIT; | |
11187 | codep++; | |
6c067bbb RM |
11188 | /* This ensures that the previous REX prefixes are noticed |
11189 | as unused prefixes, as in the return case below. */ | |
11190 | rex_used = rex; | |
f16cd0d5 | 11191 | return 1; |
252b5132 RH |
11192 | } |
11193 | prefixes = PREFIX_FWAIT; | |
11194 | break; | |
11195 | default: | |
f16cd0d5 | 11196 | return 1; |
252b5132 | 11197 | } |
52b15da3 JH |
11198 | /* Rex is ignored when followed by another prefix. */ |
11199 | if (rex) | |
11200 | { | |
3e7d61b2 | 11201 | rex_used = rex; |
f16cd0d5 | 11202 | return 1; |
52b15da3 | 11203 | } |
f16cd0d5 | 11204 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11205 | all_prefixes[i++] = *codep; |
52b15da3 | 11206 | rex = newrex; |
252b5132 | 11207 | codep++; |
f16cd0d5 L |
11208 | length++; |
11209 | } | |
11210 | return 0; | |
11211 | } | |
11212 | ||
7d421014 ILT |
11213 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11214 | prefix byte. */ | |
11215 | ||
11216 | static const char * | |
26ca5450 | 11217 | prefix_name (int pref, int sizeflag) |
7d421014 | 11218 | { |
0003779b L |
11219 | static const char *rexes [16] = |
11220 | { | |
11221 | "rex", /* 0x40 */ | |
11222 | "rex.B", /* 0x41 */ | |
11223 | "rex.X", /* 0x42 */ | |
11224 | "rex.XB", /* 0x43 */ | |
11225 | "rex.R", /* 0x44 */ | |
11226 | "rex.RB", /* 0x45 */ | |
11227 | "rex.RX", /* 0x46 */ | |
11228 | "rex.RXB", /* 0x47 */ | |
11229 | "rex.W", /* 0x48 */ | |
11230 | "rex.WB", /* 0x49 */ | |
11231 | "rex.WX", /* 0x4a */ | |
11232 | "rex.WXB", /* 0x4b */ | |
11233 | "rex.WR", /* 0x4c */ | |
11234 | "rex.WRB", /* 0x4d */ | |
11235 | "rex.WRX", /* 0x4e */ | |
11236 | "rex.WRXB", /* 0x4f */ | |
11237 | }; | |
11238 | ||
7d421014 ILT |
11239 | switch (pref) |
11240 | { | |
52b15da3 JH |
11241 | /* REX prefixes family. */ |
11242 | case 0x40: | |
52b15da3 | 11243 | case 0x41: |
52b15da3 | 11244 | case 0x42: |
52b15da3 | 11245 | case 0x43: |
52b15da3 | 11246 | case 0x44: |
52b15da3 | 11247 | case 0x45: |
52b15da3 | 11248 | case 0x46: |
52b15da3 | 11249 | case 0x47: |
52b15da3 | 11250 | case 0x48: |
52b15da3 | 11251 | case 0x49: |
52b15da3 | 11252 | case 0x4a: |
52b15da3 | 11253 | case 0x4b: |
52b15da3 | 11254 | case 0x4c: |
52b15da3 | 11255 | case 0x4d: |
52b15da3 | 11256 | case 0x4e: |
52b15da3 | 11257 | case 0x4f: |
0003779b | 11258 | return rexes [pref - 0x40]; |
7d421014 ILT |
11259 | case 0xf3: |
11260 | return "repz"; | |
11261 | case 0xf2: | |
11262 | return "repnz"; | |
11263 | case 0xf0: | |
11264 | return "lock"; | |
11265 | case 0x2e: | |
11266 | return "cs"; | |
11267 | case 0x36: | |
11268 | return "ss"; | |
11269 | case 0x3e: | |
11270 | return "ds"; | |
11271 | case 0x26: | |
11272 | return "es"; | |
11273 | case 0x64: | |
11274 | return "fs"; | |
11275 | case 0x65: | |
11276 | return "gs"; | |
11277 | case 0x66: | |
11278 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11279 | case 0x67: | |
cb712a9e | 11280 | if (address_mode == mode_64bit) |
db6eb5be | 11281 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11282 | else |
2888cb7a | 11283 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11284 | case FWAIT_OPCODE: |
11285 | return "fwait"; | |
f16cd0d5 L |
11286 | case REP_PREFIX: |
11287 | return "rep"; | |
42164a71 L |
11288 | case XACQUIRE_PREFIX: |
11289 | return "xacquire"; | |
11290 | case XRELEASE_PREFIX: | |
11291 | return "xrelease"; | |
7e8b059b L |
11292 | case BND_PREFIX: |
11293 | return "bnd"; | |
04ef582a L |
11294 | case NOTRACK_PREFIX: |
11295 | return "notrack"; | |
7d421014 ILT |
11296 | default: |
11297 | return NULL; | |
11298 | } | |
11299 | } | |
11300 | ||
ce518a5f L |
11301 | static char op_out[MAX_OPERANDS][100]; |
11302 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11303 | static int two_source_ops; |
ce518a5f L |
11304 | static bfd_vma op_address[MAX_OPERANDS]; |
11305 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11306 | static bfd_vma start_pc; |
ce518a5f | 11307 | |
252b5132 RH |
11308 | /* |
11309 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11310 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11311 | * section of the "Virtual 8086 Mode" chapter.) | |
11312 | * 'pc' should be the address of this instruction, it will | |
11313 | * be used to print the target address if this is a relative jump or call | |
11314 | * The function returns the length of this instruction in bytes. | |
11315 | */ | |
11316 | ||
252b5132 | 11317 | static char intel_syntax; |
9d141669 | 11318 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11319 | static char open_char; |
11320 | static char close_char; | |
11321 | static char separator_char; | |
11322 | static char scale_char; | |
11323 | ||
5db04b09 L |
11324 | enum x86_64_isa |
11325 | { | |
d835a58b | 11326 | amd64 = 1, |
5db04b09 L |
11327 | intel64 |
11328 | }; | |
11329 | ||
11330 | static enum x86_64_isa isa64; | |
11331 | ||
e396998b AM |
11332 | /* Here for backwards compatibility. When gdb stops using |
11333 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11334 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11335 | int |
26ca5450 | 11336 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11337 | { |
11338 | intel_syntax = 0; | |
e396998b AM |
11339 | |
11340 | return print_insn (pc, info); | |
252b5132 RH |
11341 | } |
11342 | ||
11343 | int | |
26ca5450 | 11344 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11345 | { |
11346 | intel_syntax = 1; | |
e396998b AM |
11347 | |
11348 | return print_insn (pc, info); | |
252b5132 RH |
11349 | } |
11350 | ||
e396998b | 11351 | int |
26ca5450 | 11352 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11353 | { |
11354 | intel_syntax = -1; | |
11355 | ||
11356 | return print_insn (pc, info); | |
11357 | } | |
11358 | ||
f59a29b9 L |
11359 | void |
11360 | print_i386_disassembler_options (FILE *stream) | |
11361 | { | |
11362 | fprintf (stream, _("\n\ | |
11363 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11364 | with the -M switch (multiple options should be separated by commas):\n")); | |
11365 | ||
11366 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11367 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11368 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11369 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11370 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11371 | fprintf (stream, _(" att-mnemonic\n" |
11372 | " Display instruction in AT&T mnemonic\n")); | |
11373 | fprintf (stream, _(" intel-mnemonic\n" | |
11374 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11375 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11376 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11377 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11378 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11379 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11380 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11381 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11382 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11383 | } |
11384 | ||
592d1631 | 11385 | /* Bad opcode. */ |
bf890a93 | 11386 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11387 | |
b844680a L |
11388 | /* Get a pointer to struct dis386 with a valid name. */ |
11389 | ||
11390 | static const struct dis386 * | |
8bb15339 | 11391 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11392 | { |
91d6fa6a | 11393 | int vindex, vex_table_index; |
b844680a L |
11394 | |
11395 | if (dp->name != NULL) | |
11396 | return dp; | |
11397 | ||
11398 | switch (dp->op[0].bytemode) | |
11399 | { | |
1ceb70f8 L |
11400 | case USE_REG_TABLE: |
11401 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11402 | break; | |
11403 | ||
11404 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11405 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11406 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11407 | break; |
11408 | ||
11409 | case USE_RM_TABLE: | |
11410 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11411 | break; |
11412 | ||
4e7d34a6 | 11413 | case USE_PREFIX_TABLE: |
c0f3af97 | 11414 | if (need_vex) |
b844680a | 11415 | { |
c0f3af97 L |
11416 | /* The prefix in VEX is implicit. */ |
11417 | switch (vex.prefix) | |
11418 | { | |
11419 | case 0: | |
91d6fa6a | 11420 | vindex = 0; |
c0f3af97 L |
11421 | break; |
11422 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11423 | vindex = 1; |
c0f3af97 L |
11424 | break; |
11425 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11426 | vindex = 2; |
c0f3af97 L |
11427 | break; |
11428 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11429 | vindex = 3; |
c0f3af97 L |
11430 | break; |
11431 | default: | |
11432 | abort (); | |
11433 | break; | |
11434 | } | |
b844680a | 11435 | } |
7bb15c6f | 11436 | else |
b844680a | 11437 | { |
285ca992 L |
11438 | int last_prefix = -1; |
11439 | int prefix = 0; | |
91d6fa6a | 11440 | vindex = 0; |
285ca992 L |
11441 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11442 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11443 | last one wins. */ | |
11444 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11445 | { |
285ca992 | 11446 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11447 | { |
285ca992 L |
11448 | vindex = 1; |
11449 | prefix = PREFIX_REPZ; | |
11450 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11451 | } |
11452 | else | |
b844680a | 11453 | { |
285ca992 L |
11454 | vindex = 3; |
11455 | prefix = PREFIX_REPNZ; | |
11456 | last_prefix = last_repnz_prefix; | |
b844680a | 11457 | } |
285ca992 | 11458 | |
507bd325 L |
11459 | /* Check if prefix should be ignored. */ |
11460 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11461 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11462 | & prefix) != 0) | |
285ca992 L |
11463 | vindex = 0; |
11464 | } | |
11465 | ||
11466 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11467 | { | |
11468 | vindex = 2; | |
11469 | prefix = PREFIX_DATA; | |
11470 | last_prefix = last_data_prefix; | |
11471 | } | |
11472 | ||
11473 | if (vindex != 0) | |
11474 | { | |
11475 | used_prefixes |= prefix; | |
11476 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11477 | } |
11478 | } | |
91d6fa6a | 11479 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11480 | break; |
11481 | ||
4e7d34a6 | 11482 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11483 | vindex = address_mode == mode_64bit ? 1 : 0; |
11484 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11485 | break; |
11486 | ||
4e7d34a6 | 11487 | case USE_3BYTE_TABLE: |
8bb15339 | 11488 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11489 | vindex = *codep++; |
11490 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11491 | end_codep = codep; |
8bb15339 L |
11492 | modrm.mod = (*codep >> 6) & 3; |
11493 | modrm.reg = (*codep >> 3) & 7; | |
11494 | modrm.rm = *codep & 7; | |
11495 | break; | |
11496 | ||
c0f3af97 L |
11497 | case USE_VEX_LEN_TABLE: |
11498 | if (!need_vex) | |
11499 | abort (); | |
11500 | ||
11501 | switch (vex.length) | |
11502 | { | |
11503 | case 128: | |
91d6fa6a | 11504 | vindex = 0; |
c0f3af97 L |
11505 | break; |
11506 | case 256: | |
91d6fa6a | 11507 | vindex = 1; |
c0f3af97 L |
11508 | break; |
11509 | default: | |
11510 | abort (); | |
11511 | break; | |
11512 | } | |
11513 | ||
91d6fa6a | 11514 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11515 | break; |
11516 | ||
04e2a182 L |
11517 | case USE_EVEX_LEN_TABLE: |
11518 | if (!vex.evex) | |
11519 | abort (); | |
11520 | ||
11521 | switch (vex.length) | |
11522 | { | |
11523 | case 128: | |
11524 | vindex = 0; | |
11525 | break; | |
11526 | case 256: | |
11527 | vindex = 1; | |
11528 | break; | |
11529 | case 512: | |
11530 | vindex = 2; | |
11531 | break; | |
11532 | default: | |
11533 | abort (); | |
11534 | break; | |
11535 | } | |
11536 | ||
11537 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11538 | break; | |
11539 | ||
f88c9eb0 SP |
11540 | case USE_XOP_8F_TABLE: |
11541 | FETCH_DATA (info, codep + 3); | |
11542 | /* All bits in the REX prefix are ignored. */ | |
11543 | rex_ignored = rex; | |
11544 | rex = ~(*codep >> 5) & 0x7; | |
11545 | ||
11546 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11547 | switch ((*codep & 0x1f)) | |
11548 | { | |
11549 | default: | |
f07af43e L |
11550 | dp = &bad_opcode; |
11551 | return dp; | |
5dd85c99 SP |
11552 | case 0x8: |
11553 | vex_table_index = XOP_08; | |
11554 | break; | |
f88c9eb0 SP |
11555 | case 0x9: |
11556 | vex_table_index = XOP_09; | |
11557 | break; | |
11558 | case 0xa: | |
11559 | vex_table_index = XOP_0A; | |
11560 | break; | |
11561 | } | |
11562 | codep++; | |
11563 | vex.w = *codep & 0x80; | |
11564 | if (vex.w && address_mode == mode_64bit) | |
11565 | rex |= REX_W; | |
11566 | ||
11567 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11568 | if (address_mode != mode_64bit) |
f07af43e | 11569 | { |
abfcb414 AP |
11570 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11571 | rex &= ~REX_B; | |
f07af43e | 11572 | } |
f88c9eb0 SP |
11573 | |
11574 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11575 | switch ((*codep & 0x3)) | |
11576 | { | |
11577 | case 0: | |
f88c9eb0 SP |
11578 | break; |
11579 | case 1: | |
11580 | vex.prefix = DATA_PREFIX_OPCODE; | |
11581 | break; | |
11582 | case 2: | |
11583 | vex.prefix = REPE_PREFIX_OPCODE; | |
11584 | break; | |
11585 | case 3: | |
11586 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11587 | break; | |
11588 | } | |
11589 | need_vex = 1; | |
11590 | need_vex_reg = 1; | |
11591 | codep++; | |
91d6fa6a NC |
11592 | vindex = *codep++; |
11593 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11594 | |
285ca992 | 11595 | end_codep = codep; |
c48244a5 SP |
11596 | FETCH_DATA (info, codep + 1); |
11597 | modrm.mod = (*codep >> 6) & 3; | |
11598 | modrm.reg = (*codep >> 3) & 7; | |
11599 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11600 | break; |
11601 | ||
c0f3af97 | 11602 | case USE_VEX_C4_TABLE: |
43234a1e | 11603 | /* VEX prefix. */ |
c0f3af97 L |
11604 | FETCH_DATA (info, codep + 3); |
11605 | /* All bits in the REX prefix are ignored. */ | |
11606 | rex_ignored = rex; | |
11607 | rex = ~(*codep >> 5) & 0x7; | |
11608 | switch ((*codep & 0x1f)) | |
11609 | { | |
11610 | default: | |
f07af43e L |
11611 | dp = &bad_opcode; |
11612 | return dp; | |
c0f3af97 | 11613 | case 0x1: |
f88c9eb0 | 11614 | vex_table_index = VEX_0F; |
c0f3af97 L |
11615 | break; |
11616 | case 0x2: | |
f88c9eb0 | 11617 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11618 | break; |
11619 | case 0x3: | |
f88c9eb0 | 11620 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11621 | break; |
11622 | } | |
11623 | codep++; | |
11624 | vex.w = *codep & 0x80; | |
9889cbb1 | 11625 | if (address_mode == mode_64bit) |
f07af43e | 11626 | { |
9889cbb1 L |
11627 | if (vex.w) |
11628 | rex |= REX_W; | |
9889cbb1 L |
11629 | } |
11630 | else | |
11631 | { | |
11632 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11633 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11634 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11635 | rex = 0; |
f07af43e | 11636 | } |
5f847646 | 11637 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11638 | vex.length = (*codep & 0x4) ? 256 : 128; |
11639 | switch ((*codep & 0x3)) | |
11640 | { | |
11641 | case 0: | |
c0f3af97 L |
11642 | break; |
11643 | case 1: | |
11644 | vex.prefix = DATA_PREFIX_OPCODE; | |
11645 | break; | |
11646 | case 2: | |
11647 | vex.prefix = REPE_PREFIX_OPCODE; | |
11648 | break; | |
11649 | case 3: | |
11650 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11651 | break; | |
11652 | } | |
11653 | need_vex = 1; | |
11654 | need_vex_reg = 1; | |
11655 | codep++; | |
91d6fa6a NC |
11656 | vindex = *codep++; |
11657 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11658 | end_codep = codep; |
53c4d625 JB |
11659 | /* There is no MODRM byte for VEX0F 77. */ |
11660 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11661 | { |
11662 | FETCH_DATA (info, codep + 1); | |
11663 | modrm.mod = (*codep >> 6) & 3; | |
11664 | modrm.reg = (*codep >> 3) & 7; | |
11665 | modrm.rm = *codep & 7; | |
11666 | } | |
11667 | break; | |
11668 | ||
11669 | case USE_VEX_C5_TABLE: | |
43234a1e | 11670 | /* VEX prefix. */ |
c0f3af97 L |
11671 | FETCH_DATA (info, codep + 2); |
11672 | /* All bits in the REX prefix are ignored. */ | |
11673 | rex_ignored = rex; | |
11674 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11675 | ||
9889cbb1 L |
11676 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11677 | VEX.vvvv is 1. */ | |
c0f3af97 | 11678 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11679 | vex.length = (*codep & 0x4) ? 256 : 128; |
11680 | switch ((*codep & 0x3)) | |
11681 | { | |
11682 | case 0: | |
c0f3af97 L |
11683 | break; |
11684 | case 1: | |
11685 | vex.prefix = DATA_PREFIX_OPCODE; | |
11686 | break; | |
11687 | case 2: | |
11688 | vex.prefix = REPE_PREFIX_OPCODE; | |
11689 | break; | |
11690 | case 3: | |
11691 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11692 | break; | |
11693 | } | |
11694 | need_vex = 1; | |
11695 | need_vex_reg = 1; | |
11696 | codep++; | |
91d6fa6a NC |
11697 | vindex = *codep++; |
11698 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11699 | end_codep = codep; |
53c4d625 JB |
11700 | /* There is no MODRM byte for VEX 77. */ |
11701 | if (vindex != 0x77) | |
c0f3af97 L |
11702 | { |
11703 | FETCH_DATA (info, codep + 1); | |
11704 | modrm.mod = (*codep >> 6) & 3; | |
11705 | modrm.reg = (*codep >> 3) & 7; | |
11706 | modrm.rm = *codep & 7; | |
11707 | } | |
11708 | break; | |
11709 | ||
9e30b8e0 L |
11710 | case USE_VEX_W_TABLE: |
11711 | if (!need_vex) | |
11712 | abort (); | |
11713 | ||
11714 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11715 | break; | |
11716 | ||
43234a1e L |
11717 | case USE_EVEX_TABLE: |
11718 | two_source_ops = 0; | |
11719 | /* EVEX prefix. */ | |
11720 | vex.evex = 1; | |
11721 | FETCH_DATA (info, codep + 4); | |
11722 | /* All bits in the REX prefix are ignored. */ | |
11723 | rex_ignored = rex; | |
11724 | /* The first byte after 0x62. */ | |
11725 | rex = ~(*codep >> 5) & 0x7; | |
11726 | vex.r = *codep & 0x10; | |
11727 | switch ((*codep & 0xf)) | |
11728 | { | |
11729 | default: | |
11730 | return &bad_opcode; | |
11731 | case 0x1: | |
11732 | vex_table_index = EVEX_0F; | |
11733 | break; | |
11734 | case 0x2: | |
11735 | vex_table_index = EVEX_0F38; | |
11736 | break; | |
11737 | case 0x3: | |
11738 | vex_table_index = EVEX_0F3A; | |
11739 | break; | |
11740 | } | |
11741 | ||
11742 | /* The second byte after 0x62. */ | |
11743 | codep++; | |
11744 | vex.w = *codep & 0x80; | |
11745 | if (vex.w && address_mode == mode_64bit) | |
11746 | rex |= REX_W; | |
11747 | ||
11748 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11749 | |
11750 | /* The U bit. */ | |
11751 | if (!(*codep & 0x4)) | |
11752 | return &bad_opcode; | |
11753 | ||
11754 | switch ((*codep & 0x3)) | |
11755 | { | |
11756 | case 0: | |
43234a1e L |
11757 | break; |
11758 | case 1: | |
11759 | vex.prefix = DATA_PREFIX_OPCODE; | |
11760 | break; | |
11761 | case 2: | |
11762 | vex.prefix = REPE_PREFIX_OPCODE; | |
11763 | break; | |
11764 | case 3: | |
11765 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11766 | break; | |
11767 | } | |
11768 | ||
11769 | /* The third byte after 0x62. */ | |
11770 | codep++; | |
11771 | ||
11772 | /* Remember the static rounding bits. */ | |
11773 | vex.ll = (*codep >> 5) & 3; | |
11774 | vex.b = (*codep & 0x10) != 0; | |
11775 | ||
11776 | vex.v = *codep & 0x8; | |
11777 | vex.mask_register_specifier = *codep & 0x7; | |
11778 | vex.zeroing = *codep & 0x80; | |
11779 | ||
5f847646 JB |
11780 | if (address_mode != mode_64bit) |
11781 | { | |
11782 | /* In 16/32-bit mode silently ignore following bits. */ | |
11783 | rex &= ~REX_B; | |
11784 | vex.r = 1; | |
11785 | vex.v = 1; | |
11786 | } | |
11787 | ||
43234a1e L |
11788 | need_vex = 1; |
11789 | need_vex_reg = 1; | |
11790 | codep++; | |
11791 | vindex = *codep++; | |
11792 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11793 | end_codep = codep; |
43234a1e L |
11794 | FETCH_DATA (info, codep + 1); |
11795 | modrm.mod = (*codep >> 6) & 3; | |
11796 | modrm.reg = (*codep >> 3) & 7; | |
11797 | modrm.rm = *codep & 7; | |
11798 | ||
11799 | /* Set vector length. */ | |
11800 | if (modrm.mod == 3 && vex.b) | |
11801 | vex.length = 512; | |
11802 | else | |
11803 | { | |
11804 | switch (vex.ll) | |
11805 | { | |
11806 | case 0x0: | |
11807 | vex.length = 128; | |
11808 | break; | |
11809 | case 0x1: | |
11810 | vex.length = 256; | |
11811 | break; | |
11812 | case 0x2: | |
11813 | vex.length = 512; | |
11814 | break; | |
11815 | default: | |
11816 | return &bad_opcode; | |
11817 | } | |
11818 | } | |
11819 | break; | |
11820 | ||
592d1631 L |
11821 | case 0: |
11822 | dp = &bad_opcode; | |
11823 | break; | |
11824 | ||
b844680a | 11825 | default: |
d34b5006 | 11826 | abort (); |
b844680a L |
11827 | } |
11828 | ||
11829 | if (dp->name != NULL) | |
11830 | return dp; | |
11831 | else | |
8bb15339 | 11832 | return get_valid_dis386 (dp, info); |
b844680a L |
11833 | } |
11834 | ||
dfc8cf43 | 11835 | static void |
55cf16e1 | 11836 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11837 | { |
11838 | /* If modrm.mod == 3, operand must be register. */ | |
11839 | if (need_modrm | |
55cf16e1 | 11840 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11841 | && modrm.mod != 3 |
11842 | && modrm.rm == 4) | |
11843 | { | |
11844 | FETCH_DATA (info, codep + 2); | |
11845 | sib.index = (codep [1] >> 3) & 7; | |
11846 | sib.scale = (codep [1] >> 6) & 3; | |
11847 | sib.base = codep [1] & 7; | |
11848 | } | |
11849 | } | |
11850 | ||
e396998b | 11851 | static int |
26ca5450 | 11852 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11853 | { |
2da11e11 | 11854 | const struct dis386 *dp; |
252b5132 | 11855 | int i; |
ce518a5f | 11856 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11857 | int needcomma; |
df18fdba | 11858 | int sizeflag, orig_sizeflag; |
e396998b | 11859 | const char *p; |
252b5132 | 11860 | struct dis_private priv; |
f16cd0d5 | 11861 | int prefix_length; |
252b5132 | 11862 | |
d7921315 L |
11863 | priv.orig_sizeflag = AFLAG | DFLAG; |
11864 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11865 | address_mode = mode_32bit; |
2da11e11 | 11866 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11867 | { |
11868 | address_mode = mode_16bit; | |
11869 | priv.orig_sizeflag = 0; | |
11870 | } | |
2da11e11 | 11871 | else |
d7921315 L |
11872 | address_mode = mode_64bit; |
11873 | ||
11874 | if (intel_syntax == (char) -1) | |
11875 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11876 | |
11877 | for (p = info->disassembler_options; p != NULL; ) | |
11878 | { | |
5db04b09 L |
11879 | if (CONST_STRNEQ (p, "amd64")) |
11880 | isa64 = amd64; | |
11881 | else if (CONST_STRNEQ (p, "intel64")) | |
11882 | isa64 = intel64; | |
11883 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11884 | { |
cb712a9e | 11885 | address_mode = mode_64bit; |
e396998b AM |
11886 | priv.orig_sizeflag = AFLAG | DFLAG; |
11887 | } | |
0112cd26 | 11888 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11889 | { |
cb712a9e | 11890 | address_mode = mode_32bit; |
e396998b AM |
11891 | priv.orig_sizeflag = AFLAG | DFLAG; |
11892 | } | |
0112cd26 | 11893 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11894 | { |
cb712a9e | 11895 | address_mode = mode_16bit; |
e396998b AM |
11896 | priv.orig_sizeflag = 0; |
11897 | } | |
0112cd26 | 11898 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11899 | { |
11900 | intel_syntax = 1; | |
9d141669 L |
11901 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11902 | intel_mnemonic = 1; | |
e396998b | 11903 | } |
0112cd26 | 11904 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11905 | { |
11906 | intel_syntax = 0; | |
9d141669 L |
11907 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11908 | intel_mnemonic = 0; | |
e396998b | 11909 | } |
0112cd26 | 11910 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11911 | { |
f59a29b9 L |
11912 | if (address_mode == mode_64bit) |
11913 | { | |
11914 | if (p[4] == '3' && p[5] == '2') | |
11915 | priv.orig_sizeflag &= ~AFLAG; | |
11916 | else if (p[4] == '6' && p[5] == '4') | |
11917 | priv.orig_sizeflag |= AFLAG; | |
11918 | } | |
11919 | else | |
11920 | { | |
11921 | if (p[4] == '1' && p[5] == '6') | |
11922 | priv.orig_sizeflag &= ~AFLAG; | |
11923 | else if (p[4] == '3' && p[5] == '2') | |
11924 | priv.orig_sizeflag |= AFLAG; | |
11925 | } | |
e396998b | 11926 | } |
0112cd26 | 11927 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11928 | { |
11929 | if (p[4] == '1' && p[5] == '6') | |
11930 | priv.orig_sizeflag &= ~DFLAG; | |
11931 | else if (p[4] == '3' && p[5] == '2') | |
11932 | priv.orig_sizeflag |= DFLAG; | |
11933 | } | |
0112cd26 | 11934 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11935 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11936 | ||
11937 | p = strchr (p, ','); | |
11938 | if (p != NULL) | |
11939 | p++; | |
11940 | } | |
11941 | ||
c0f92bf9 L |
11942 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11943 | { | |
11944 | (*info->fprintf_func) (info->stream, | |
11945 | _("64-bit address is disabled")); | |
11946 | return -1; | |
11947 | } | |
11948 | ||
e396998b AM |
11949 | if (intel_syntax) |
11950 | { | |
11951 | names64 = intel_names64; | |
11952 | names32 = intel_names32; | |
11953 | names16 = intel_names16; | |
11954 | names8 = intel_names8; | |
11955 | names8rex = intel_names8rex; | |
11956 | names_seg = intel_names_seg; | |
b9733481 | 11957 | names_mm = intel_names_mm; |
7e8b059b | 11958 | names_bnd = intel_names_bnd; |
b9733481 L |
11959 | names_xmm = intel_names_xmm; |
11960 | names_ymm = intel_names_ymm; | |
43234a1e | 11961 | names_zmm = intel_names_zmm; |
db51cc60 L |
11962 | index64 = intel_index64; |
11963 | index32 = intel_index32; | |
43234a1e | 11964 | names_mask = intel_names_mask; |
e396998b AM |
11965 | index16 = intel_index16; |
11966 | open_char = '['; | |
11967 | close_char = ']'; | |
11968 | separator_char = '+'; | |
11969 | scale_char = '*'; | |
11970 | } | |
11971 | else | |
11972 | { | |
11973 | names64 = att_names64; | |
11974 | names32 = att_names32; | |
11975 | names16 = att_names16; | |
11976 | names8 = att_names8; | |
11977 | names8rex = att_names8rex; | |
11978 | names_seg = att_names_seg; | |
b9733481 | 11979 | names_mm = att_names_mm; |
7e8b059b | 11980 | names_bnd = att_names_bnd; |
b9733481 L |
11981 | names_xmm = att_names_xmm; |
11982 | names_ymm = att_names_ymm; | |
43234a1e | 11983 | names_zmm = att_names_zmm; |
db51cc60 L |
11984 | index64 = att_index64; |
11985 | index32 = att_index32; | |
43234a1e | 11986 | names_mask = att_names_mask; |
e396998b AM |
11987 | index16 = att_index16; |
11988 | open_char = '('; | |
11989 | close_char = ')'; | |
11990 | separator_char = ','; | |
11991 | scale_char = ','; | |
11992 | } | |
2da11e11 | 11993 | |
4fe53c98 | 11994 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11995 | puts most long word instructions on a single line. Use 8 bytes |
11996 | for Intel L1OM. */ | |
d7921315 | 11997 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11998 | info->bytes_per_line = 8; |
11999 | else | |
12000 | info->bytes_per_line = 7; | |
252b5132 | 12001 | |
26ca5450 | 12002 | info->private_data = &priv; |
252b5132 RH |
12003 | priv.max_fetched = priv.the_buffer; |
12004 | priv.insn_start = pc; | |
252b5132 RH |
12005 | |
12006 | obuf[0] = 0; | |
ce518a5f L |
12007 | for (i = 0; i < MAX_OPERANDS; ++i) |
12008 | { | |
12009 | op_out[i][0] = 0; | |
12010 | op_index[i] = -1; | |
12011 | } | |
252b5132 RH |
12012 | |
12013 | the_info = info; | |
12014 | start_pc = pc; | |
e396998b AM |
12015 | start_codep = priv.the_buffer; |
12016 | codep = priv.the_buffer; | |
252b5132 | 12017 | |
8df14d78 | 12018 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12019 | { |
7d421014 ILT |
12020 | const char *name; |
12021 | ||
5076851f | 12022 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12023 | means we have an incomplete instruction of some sort. Just |
12024 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12025 | if (codep > priv.the_buffer) | |
5076851f | 12026 | { |
e396998b | 12027 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12028 | if (name != NULL) |
12029 | (*info->fprintf_func) (info->stream, "%s", name); | |
12030 | else | |
5076851f | 12031 | { |
7d421014 ILT |
12032 | /* Just print the first byte as a .byte instruction. */ |
12033 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12034 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12035 | } |
5076851f | 12036 | |
7d421014 | 12037 | return 1; |
5076851f ILT |
12038 | } |
12039 | ||
12040 | return -1; | |
12041 | } | |
12042 | ||
52b15da3 | 12043 | obufp = obuf; |
f16cd0d5 L |
12044 | sizeflag = priv.orig_sizeflag; |
12045 | ||
12046 | if (!ckprefix () || rex_used) | |
12047 | { | |
12048 | /* Too many prefixes or unused REX prefixes. */ | |
12049 | for (i = 0; | |
f6dd4781 | 12050 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12051 | i++) |
de882298 | 12052 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12053 | i == 0 ? "" : " ", |
f16cd0d5 | 12054 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12055 | return i; |
f16cd0d5 | 12056 | } |
252b5132 RH |
12057 | |
12058 | insn_codep = codep; | |
12059 | ||
12060 | FETCH_DATA (info, codep + 1); | |
12061 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12062 | ||
3e7d61b2 | 12063 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12064 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12065 | { |
86a80a50 | 12066 | /* Handle prefixes before fwait. */ |
d9949a36 | 12067 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12068 | i++) |
12069 | (*info->fprintf_func) (info->stream, "%s ", | |
12070 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12071 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12072 | return i + 1; |
252b5132 RH |
12073 | } |
12074 | ||
252b5132 RH |
12075 | if (*codep == 0x0f) |
12076 | { | |
eec0f4ca | 12077 | unsigned char threebyte; |
5f40e14d JS |
12078 | |
12079 | codep++; | |
12080 | FETCH_DATA (info, codep + 1); | |
12081 | threebyte = *codep; | |
eec0f4ca | 12082 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12083 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12084 | codep++; |
252b5132 RH |
12085 | } |
12086 | else | |
12087 | { | |
6439fc28 | 12088 | dp = &dis386[*codep]; |
252b5132 | 12089 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12090 | codep++; |
252b5132 | 12091 | } |
246c51aa | 12092 | |
df18fdba L |
12093 | /* Save sizeflag for printing the extra prefixes later before updating |
12094 | it for mnemonic and operand processing. The prefix names depend | |
12095 | only on the address mode. */ | |
12096 | orig_sizeflag = sizeflag; | |
c608c12e | 12097 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12098 | sizeflag ^= AFLAG; |
b844680a | 12099 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12100 | sizeflag ^= DFLAG; |
3ffd33cf | 12101 | |
285ca992 | 12102 | end_codep = codep; |
8bb15339 | 12103 | if (need_modrm) |
252b5132 RH |
12104 | { |
12105 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12106 | modrm.mod = (*codep >> 6) & 3; |
12107 | modrm.reg = (*codep >> 3) & 7; | |
12108 | modrm.rm = *codep & 7; | |
252b5132 RH |
12109 | } |
12110 | ||
42d5f9c6 MS |
12111 | need_vex = 0; |
12112 | need_vex_reg = 0; | |
12113 | vex_w_done = 0; | |
caf0678c | 12114 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12115 | |
ce518a5f | 12116 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12117 | { |
55cf16e1 | 12118 | get_sib (info, sizeflag); |
252b5132 RH |
12119 | dofloat (sizeflag); |
12120 | } | |
12121 | else | |
12122 | { | |
8bb15339 | 12123 | dp = get_valid_dis386 (dp, info); |
b844680a | 12124 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12125 | { |
55cf16e1 | 12126 | get_sib (info, sizeflag); |
ce518a5f L |
12127 | for (i = 0; i < MAX_OPERANDS; ++i) |
12128 | { | |
246c51aa | 12129 | obufp = op_out[i]; |
ce518a5f L |
12130 | op_ad = MAX_OPERANDS - 1 - i; |
12131 | if (dp->op[i].rtn) | |
12132 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12133 | /* For EVEX instruction after the last operand masking |
12134 | should be printed. */ | |
12135 | if (i == 0 && vex.evex) | |
12136 | { | |
12137 | /* Don't print {%k0}. */ | |
12138 | if (vex.mask_register_specifier) | |
12139 | { | |
12140 | oappend ("{"); | |
12141 | oappend (names_mask[vex.mask_register_specifier]); | |
12142 | oappend ("}"); | |
12143 | } | |
12144 | if (vex.zeroing) | |
12145 | oappend ("{z}"); | |
12146 | } | |
ce518a5f | 12147 | } |
6439fc28 | 12148 | } |
252b5132 RH |
12149 | } |
12150 | ||
1d67fe3b TT |
12151 | /* Clear instruction information. */ |
12152 | if (the_info) | |
12153 | { | |
12154 | the_info->insn_info_valid = 0; | |
12155 | the_info->branch_delay_insns = 0; | |
12156 | the_info->data_size = 0; | |
12157 | the_info->insn_type = dis_noninsn; | |
12158 | the_info->target = 0; | |
12159 | the_info->target2 = 0; | |
12160 | } | |
12161 | ||
12162 | /* Reset jump operation indicator. */ | |
12163 | op_is_jump = FALSE; | |
12164 | ||
12165 | { | |
12166 | int jump_detection = 0; | |
12167 | ||
12168 | /* Extract flags. */ | |
12169 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12170 | { | |
12171 | if ((dp->op[i].rtn == OP_J) | |
12172 | || (dp->op[i].rtn == OP_indirE)) | |
12173 | jump_detection |= 1; | |
12174 | else if ((dp->op[i].rtn == BND_Fixup) | |
12175 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12176 | jump_detection |= 2; | |
12177 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12178 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12179 | jump_detection |= 4; | |
12180 | } | |
12181 | ||
12182 | /* Determine if this is a jump or branch. */ | |
12183 | if ((jump_detection & 0x3) == 0x3) | |
12184 | { | |
12185 | op_is_jump = TRUE; | |
12186 | if (jump_detection & 0x4) | |
12187 | the_info->insn_type = dis_condbranch; | |
12188 | else | |
12189 | the_info->insn_type = | |
12190 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12191 | ? dis_jsr : dis_branch; | |
12192 | } | |
12193 | } | |
12194 | ||
63c6fc6c L |
12195 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12196 | are all 0s in inverted form. */ | |
12197 | if (need_vex && vex.register_specifier != 0) | |
12198 | { | |
12199 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12200 | return end_codep - priv.the_buffer; | |
12201 | } | |
12202 | ||
d869730d | 12203 | /* Check if the REX prefix is used. */ |
e2e6193d | 12204 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12205 | all_prefixes[last_rex_prefix] = 0; |
12206 | ||
5e6718e4 | 12207 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12208 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12209 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12210 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12211 | all_prefixes[last_seg_prefix] = 0; |
12212 | ||
5e6718e4 | 12213 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12214 | if ((prefixes & PREFIX_ADDR) != 0 |
12215 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12216 | all_prefixes[last_addr_prefix] = 0; | |
12217 | ||
df18fdba L |
12218 | /* Check if the DATA prefix is used. */ |
12219 | if ((prefixes & PREFIX_DATA) != 0 | |
12220 | && (used_prefixes & PREFIX_DATA) != 0) | |
12221 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 12222 | |
df18fdba | 12223 | /* Print the extra prefixes. */ |
f16cd0d5 | 12224 | prefix_length = 0; |
f310f33d | 12225 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12226 | if (all_prefixes[i]) |
12227 | { | |
12228 | const char *name; | |
df18fdba | 12229 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12230 | if (name == NULL) |
12231 | abort (); | |
12232 | prefix_length += strlen (name) + 1; | |
12233 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12234 | } | |
b844680a | 12235 | |
285ca992 L |
12236 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12237 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12238 | used by putop and MMX/SSE operand and may be overriden by the | |
12239 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12240 | separately. */ | |
3888916d | 12241 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
12242 | && dp != &bad_opcode |
12243 | && (((prefixes | |
12244 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
12245 | && (used_prefixes | |
12246 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
12247 | || ((((prefixes | |
12248 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12249 | == PREFIX_DATA) | |
12250 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
12251 | { | |
12252 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12253 | return end_codep - priv.the_buffer; | |
12254 | } | |
12255 | ||
f16cd0d5 L |
12256 | /* Check maximum code length. */ |
12257 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12258 | { | |
12259 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12260 | return MAX_CODE_LENGTH; | |
12261 | } | |
b844680a | 12262 | |
ea397f5b | 12263 | obufp = mnemonicendp; |
f16cd0d5 | 12264 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12265 | oappend (" "); |
12266 | oappend (" "); | |
12267 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12268 | ||
12269 | /* The enter and bound instructions are printed with operands in the same | |
12270 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12271 | if (intel_syntax || two_source_ops) |
252b5132 | 12272 | { |
185b1163 L |
12273 | bfd_vma riprel; |
12274 | ||
ce518a5f | 12275 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12276 | op_txt[i] = op_out[i]; |
246c51aa | 12277 | |
3a8547d2 JB |
12278 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12279 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12280 | { | |
12281 | op_txt[2] = op_out[3]; | |
12282 | op_txt[3] = op_out[2]; | |
12283 | } | |
12284 | ||
ce518a5f L |
12285 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12286 | { | |
6c067bbb RM |
12287 | op_ad = op_index[i]; |
12288 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12289 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12290 | riprel = op_riprel[i]; |
12291 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12292 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12293 | } |
252b5132 RH |
12294 | } |
12295 | else | |
12296 | { | |
ce518a5f | 12297 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12298 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12299 | } |
12300 | ||
ce518a5f L |
12301 | needcomma = 0; |
12302 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12303 | if (*op_txt[i]) | |
12304 | { | |
12305 | if (needcomma) | |
12306 | (*info->fprintf_func) (info->stream, ","); | |
12307 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12308 | { |
12309 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12310 | ||
12311 | if (the_info && op_is_jump) | |
12312 | { | |
12313 | the_info->insn_info_valid = 1; | |
12314 | the_info->branch_delay_insns = 0; | |
12315 | the_info->data_size = 0; | |
12316 | the_info->target = target; | |
12317 | the_info->target2 = 0; | |
12318 | } | |
12319 | (*info->print_address_func) (target, info); | |
12320 | } | |
ce518a5f L |
12321 | else |
12322 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12323 | needcomma = 1; | |
12324 | } | |
050dfa73 | 12325 | |
ce518a5f | 12326 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12327 | if (op_index[i] != -1 && op_riprel[i]) |
12328 | { | |
12329 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12330 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12331 | + op_address[op_index[i]]), info); |
185b1163 | 12332 | break; |
52b15da3 | 12333 | } |
e396998b | 12334 | return codep - priv.the_buffer; |
252b5132 RH |
12335 | } |
12336 | ||
6439fc28 | 12337 | static const char *float_mem[] = { |
252b5132 | 12338 | /* d8 */ |
7c52e0e8 L |
12339 | "fadd{s|}", |
12340 | "fmul{s|}", | |
12341 | "fcom{s|}", | |
12342 | "fcomp{s|}", | |
12343 | "fsub{s|}", | |
12344 | "fsubr{s|}", | |
12345 | "fdiv{s|}", | |
12346 | "fdivr{s|}", | |
db6eb5be | 12347 | /* d9 */ |
7c52e0e8 | 12348 | "fld{s|}", |
252b5132 | 12349 | "(bad)", |
7c52e0e8 L |
12350 | "fst{s|}", |
12351 | "fstp{s|}", | |
9306ca4a | 12352 | "fldenvIC", |
252b5132 | 12353 | "fldcw", |
9306ca4a | 12354 | "fNstenvIC", |
252b5132 RH |
12355 | "fNstcw", |
12356 | /* da */ | |
7c52e0e8 L |
12357 | "fiadd{l|}", |
12358 | "fimul{l|}", | |
12359 | "ficom{l|}", | |
12360 | "ficomp{l|}", | |
12361 | "fisub{l|}", | |
12362 | "fisubr{l|}", | |
12363 | "fidiv{l|}", | |
12364 | "fidivr{l|}", | |
252b5132 | 12365 | /* db */ |
7c52e0e8 L |
12366 | "fild{l|}", |
12367 | "fisttp{l|}", | |
12368 | "fist{l|}", | |
12369 | "fistp{l|}", | |
252b5132 | 12370 | "(bad)", |
6439fc28 | 12371 | "fld{t||t|}", |
252b5132 | 12372 | "(bad)", |
6439fc28 | 12373 | "fstp{t||t|}", |
252b5132 | 12374 | /* dc */ |
7c52e0e8 L |
12375 | "fadd{l|}", |
12376 | "fmul{l|}", | |
12377 | "fcom{l|}", | |
12378 | "fcomp{l|}", | |
12379 | "fsub{l|}", | |
12380 | "fsubr{l|}", | |
12381 | "fdiv{l|}", | |
12382 | "fdivr{l|}", | |
252b5132 | 12383 | /* dd */ |
7c52e0e8 L |
12384 | "fld{l|}", |
12385 | "fisttp{ll|}", | |
12386 | "fst{l||}", | |
12387 | "fstp{l|}", | |
9306ca4a | 12388 | "frstorIC", |
252b5132 | 12389 | "(bad)", |
9306ca4a | 12390 | "fNsaveIC", |
252b5132 RH |
12391 | "fNstsw", |
12392 | /* de */ | |
ac465521 JB |
12393 | "fiadd{s|}", |
12394 | "fimul{s|}", | |
12395 | "ficom{s|}", | |
12396 | "ficomp{s|}", | |
12397 | "fisub{s|}", | |
12398 | "fisubr{s|}", | |
12399 | "fidiv{s|}", | |
12400 | "fidivr{s|}", | |
252b5132 | 12401 | /* df */ |
ac465521 JB |
12402 | "fild{s|}", |
12403 | "fisttp{s|}", | |
12404 | "fist{s|}", | |
12405 | "fistp{s|}", | |
252b5132 | 12406 | "fbld", |
7c52e0e8 | 12407 | "fild{ll|}", |
252b5132 | 12408 | "fbstp", |
7c52e0e8 | 12409 | "fistp{ll|}", |
1d9f512f AM |
12410 | }; |
12411 | ||
12412 | static const unsigned char float_mem_mode[] = { | |
12413 | /* d8 */ | |
12414 | d_mode, | |
12415 | d_mode, | |
12416 | d_mode, | |
12417 | d_mode, | |
12418 | d_mode, | |
12419 | d_mode, | |
12420 | d_mode, | |
12421 | d_mode, | |
12422 | /* d9 */ | |
12423 | d_mode, | |
12424 | 0, | |
12425 | d_mode, | |
12426 | d_mode, | |
12427 | 0, | |
12428 | w_mode, | |
12429 | 0, | |
12430 | w_mode, | |
12431 | /* da */ | |
12432 | d_mode, | |
12433 | d_mode, | |
12434 | d_mode, | |
12435 | d_mode, | |
12436 | d_mode, | |
12437 | d_mode, | |
12438 | d_mode, | |
12439 | d_mode, | |
12440 | /* db */ | |
12441 | d_mode, | |
12442 | d_mode, | |
12443 | d_mode, | |
12444 | d_mode, | |
12445 | 0, | |
9306ca4a | 12446 | t_mode, |
1d9f512f | 12447 | 0, |
9306ca4a | 12448 | t_mode, |
1d9f512f AM |
12449 | /* dc */ |
12450 | q_mode, | |
12451 | q_mode, | |
12452 | q_mode, | |
12453 | q_mode, | |
12454 | q_mode, | |
12455 | q_mode, | |
12456 | q_mode, | |
12457 | q_mode, | |
12458 | /* dd */ | |
12459 | q_mode, | |
12460 | q_mode, | |
12461 | q_mode, | |
12462 | q_mode, | |
12463 | 0, | |
12464 | 0, | |
12465 | 0, | |
12466 | w_mode, | |
12467 | /* de */ | |
12468 | w_mode, | |
12469 | w_mode, | |
12470 | w_mode, | |
12471 | w_mode, | |
12472 | w_mode, | |
12473 | w_mode, | |
12474 | w_mode, | |
12475 | w_mode, | |
12476 | /* df */ | |
12477 | w_mode, | |
12478 | w_mode, | |
12479 | w_mode, | |
12480 | w_mode, | |
9306ca4a | 12481 | t_mode, |
1d9f512f | 12482 | q_mode, |
9306ca4a | 12483 | t_mode, |
1d9f512f | 12484 | q_mode |
252b5132 RH |
12485 | }; |
12486 | ||
ce518a5f L |
12487 | #define ST { OP_ST, 0 } |
12488 | #define STi { OP_STi, 0 } | |
252b5132 | 12489 | |
48c97fa1 L |
12490 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12491 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12492 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12493 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12494 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12495 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12496 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12497 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12498 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12499 | |
2da11e11 | 12500 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12501 | /* d8 */ |
12502 | { | |
bf890a93 IT |
12503 | { "fadd", { ST, STi }, 0 }, |
12504 | { "fmul", { ST, STi }, 0 }, | |
12505 | { "fcom", { STi }, 0 }, | |
12506 | { "fcomp", { STi }, 0 }, | |
12507 | { "fsub", { ST, STi }, 0 }, | |
12508 | { "fsubr", { ST, STi }, 0 }, | |
12509 | { "fdiv", { ST, STi }, 0 }, | |
12510 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12511 | }, |
12512 | /* d9 */ | |
12513 | { | |
bf890a93 IT |
12514 | { "fld", { STi }, 0 }, |
12515 | { "fxch", { STi }, 0 }, | |
252b5132 | 12516 | { FGRPd9_2 }, |
592d1631 | 12517 | { Bad_Opcode }, |
252b5132 RH |
12518 | { FGRPd9_4 }, |
12519 | { FGRPd9_5 }, | |
12520 | { FGRPd9_6 }, | |
12521 | { FGRPd9_7 }, | |
12522 | }, | |
12523 | /* da */ | |
12524 | { | |
bf890a93 IT |
12525 | { "fcmovb", { ST, STi }, 0 }, |
12526 | { "fcmove", { ST, STi }, 0 }, | |
12527 | { "fcmovbe",{ ST, STi }, 0 }, | |
12528 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12529 | { Bad_Opcode }, |
252b5132 | 12530 | { FGRPda_5 }, |
592d1631 L |
12531 | { Bad_Opcode }, |
12532 | { Bad_Opcode }, | |
252b5132 RH |
12533 | }, |
12534 | /* db */ | |
12535 | { | |
bf890a93 IT |
12536 | { "fcmovnb",{ ST, STi }, 0 }, |
12537 | { "fcmovne",{ ST, STi }, 0 }, | |
12538 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12539 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12540 | { FGRPdb_4 }, |
bf890a93 IT |
12541 | { "fucomi", { ST, STi }, 0 }, |
12542 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12543 | { Bad_Opcode }, |
252b5132 RH |
12544 | }, |
12545 | /* dc */ | |
12546 | { | |
bf890a93 IT |
12547 | { "fadd", { STi, ST }, 0 }, |
12548 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12549 | { Bad_Opcode }, |
12550 | { Bad_Opcode }, | |
d53e6b98 JB |
12551 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12552 | { "fsub{M|}", { STi, ST }, 0 }, | |
12553 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12554 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12555 | }, |
12556 | /* dd */ | |
12557 | { | |
bf890a93 | 12558 | { "ffree", { STi }, 0 }, |
592d1631 | 12559 | { Bad_Opcode }, |
bf890a93 IT |
12560 | { "fst", { STi }, 0 }, |
12561 | { "fstp", { STi }, 0 }, | |
12562 | { "fucom", { STi }, 0 }, | |
12563 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12564 | { Bad_Opcode }, |
12565 | { Bad_Opcode }, | |
252b5132 RH |
12566 | }, |
12567 | /* de */ | |
12568 | { | |
bf890a93 IT |
12569 | { "faddp", { STi, ST }, 0 }, |
12570 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12571 | { Bad_Opcode }, |
252b5132 | 12572 | { FGRPde_3 }, |
d53e6b98 JB |
12573 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12574 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12575 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12576 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12577 | }, |
12578 | /* df */ | |
12579 | { | |
bf890a93 | 12580 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12581 | { Bad_Opcode }, |
12582 | { Bad_Opcode }, | |
12583 | { Bad_Opcode }, | |
252b5132 | 12584 | { FGRPdf_4 }, |
bf890a93 IT |
12585 | { "fucomip", { ST, STi }, 0 }, |
12586 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12587 | { Bad_Opcode }, |
252b5132 RH |
12588 | }, |
12589 | }; | |
12590 | ||
252b5132 | 12591 | static char *fgrps[][8] = { |
48c97fa1 L |
12592 | /* Bad opcode 0 */ |
12593 | { | |
12594 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12595 | }, | |
12596 | ||
12597 | /* d9_2 1 */ | |
252b5132 RH |
12598 | { |
12599 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12600 | }, | |
12601 | ||
48c97fa1 | 12602 | /* d9_4 2 */ |
252b5132 RH |
12603 | { |
12604 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12605 | }, | |
12606 | ||
48c97fa1 | 12607 | /* d9_5 3 */ |
252b5132 RH |
12608 | { |
12609 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12610 | }, | |
12611 | ||
48c97fa1 | 12612 | /* d9_6 4 */ |
252b5132 RH |
12613 | { |
12614 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12615 | }, | |
12616 | ||
48c97fa1 | 12617 | /* d9_7 5 */ |
252b5132 RH |
12618 | { |
12619 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12620 | }, | |
12621 | ||
48c97fa1 | 12622 | /* da_5 6 */ |
252b5132 RH |
12623 | { |
12624 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12625 | }, | |
12626 | ||
48c97fa1 | 12627 | /* db_4 7 */ |
252b5132 | 12628 | { |
309d3373 JB |
12629 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12630 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12631 | }, |
12632 | ||
48c97fa1 | 12633 | /* de_3 8 */ |
252b5132 RH |
12634 | { |
12635 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12636 | }, | |
12637 | ||
48c97fa1 | 12638 | /* df_4 9 */ |
252b5132 RH |
12639 | { |
12640 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12641 | }, | |
12642 | }; | |
12643 | ||
b6169b20 L |
12644 | static void |
12645 | swap_operand (void) | |
12646 | { | |
12647 | mnemonicendp[0] = '.'; | |
12648 | mnemonicendp[1] = 's'; | |
12649 | mnemonicendp += 2; | |
12650 | } | |
12651 | ||
b844680a L |
12652 | static void |
12653 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12654 | int sizeflag ATTRIBUTE_UNUSED) | |
12655 | { | |
12656 | /* Skip mod/rm byte. */ | |
12657 | MODRM_CHECK; | |
12658 | codep++; | |
12659 | } | |
12660 | ||
252b5132 | 12661 | static void |
26ca5450 | 12662 | dofloat (int sizeflag) |
252b5132 | 12663 | { |
2da11e11 | 12664 | const struct dis386 *dp; |
252b5132 RH |
12665 | unsigned char floatop; |
12666 | ||
12667 | floatop = codep[-1]; | |
12668 | ||
7967e09e | 12669 | if (modrm.mod != 3) |
252b5132 | 12670 | { |
7967e09e | 12671 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12672 | |
12673 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12674 | obufp = op_out[0]; |
6e50d963 | 12675 | op_ad = 2; |
1d9f512f | 12676 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12677 | return; |
12678 | } | |
6608db57 | 12679 | /* Skip mod/rm byte. */ |
4bba6815 | 12680 | MODRM_CHECK; |
252b5132 RH |
12681 | codep++; |
12682 | ||
7967e09e | 12683 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12684 | if (dp->name == NULL) |
12685 | { | |
7967e09e | 12686 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12687 | |
6608db57 | 12688 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12689 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12690 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12691 | } |
12692 | else | |
12693 | { | |
12694 | putop (dp->name, sizeflag); | |
12695 | ||
ce518a5f | 12696 | obufp = op_out[0]; |
6e50d963 | 12697 | op_ad = 2; |
ce518a5f L |
12698 | if (dp->op[0].rtn) |
12699 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12700 | |
ce518a5f | 12701 | obufp = op_out[1]; |
6e50d963 | 12702 | op_ad = 1; |
ce518a5f L |
12703 | if (dp->op[1].rtn) |
12704 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12705 | } |
12706 | } | |
12707 | ||
9ce09ba2 RM |
12708 | /* Like oappend (below), but S is a string starting with '%'. |
12709 | In Intel syntax, the '%' is elided. */ | |
12710 | static void | |
12711 | oappend_maybe_intel (const char *s) | |
12712 | { | |
12713 | oappend (s + intel_syntax); | |
12714 | } | |
12715 | ||
252b5132 | 12716 | static void |
26ca5450 | 12717 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12718 | { |
9ce09ba2 | 12719 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12720 | } |
12721 | ||
252b5132 | 12722 | static void |
26ca5450 | 12723 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12724 | { |
7967e09e | 12725 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12726 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12727 | } |
12728 | ||
6608db57 | 12729 | /* Capital letters in template are macros. */ |
6439fc28 | 12730 | static int |
d3ce72d0 | 12731 | putop (const char *in_template, int sizeflag) |
252b5132 | 12732 | { |
2da11e11 | 12733 | const char *p; |
9306ca4a | 12734 | int alt = 0; |
9d141669 | 12735 | int cond = 1; |
98b528ac L |
12736 | unsigned int l = 0, len = 1; |
12737 | char last[4]; | |
12738 | ||
12739 | #define SAVE_LAST(c) \ | |
12740 | if (l < len && l < sizeof (last)) \ | |
12741 | last[l++] = c; \ | |
12742 | else \ | |
12743 | abort (); | |
252b5132 | 12744 | |
d3ce72d0 | 12745 | for (p = in_template; *p; p++) |
252b5132 RH |
12746 | { |
12747 | switch (*p) | |
12748 | { | |
12749 | default: | |
12750 | *obufp++ = *p; | |
12751 | break; | |
98b528ac L |
12752 | case '%': |
12753 | len++; | |
12754 | break; | |
9d141669 L |
12755 | case '!': |
12756 | cond = 0; | |
12757 | break; | |
6439fc28 | 12758 | case '{': |
6439fc28 | 12759 | if (intel_syntax) |
6439fc28 AM |
12760 | { |
12761 | while (*++p != '|') | |
7c52e0e8 L |
12762 | if (*p == '}' || *p == '\0') |
12763 | abort (); | |
6439fc28 | 12764 | } |
9306ca4a JB |
12765 | /* Fall through. */ |
12766 | case 'I': | |
12767 | alt = 1; | |
12768 | continue; | |
6439fc28 AM |
12769 | case '|': |
12770 | while (*++p != '}') | |
12771 | { | |
12772 | if (*p == '\0') | |
12773 | abort (); | |
12774 | } | |
12775 | break; | |
12776 | case '}': | |
12777 | break; | |
252b5132 | 12778 | case 'A': |
db6eb5be AM |
12779 | if (intel_syntax) |
12780 | break; | |
7967e09e | 12781 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12782 | *obufp++ = 'b'; |
12783 | break; | |
12784 | case 'B': | |
4b06377f L |
12785 | if (l == 0 && len == 1) |
12786 | { | |
12787 | case_B: | |
12788 | if (intel_syntax) | |
12789 | break; | |
12790 | if (sizeflag & SUFFIX_ALWAYS) | |
12791 | *obufp++ = 'b'; | |
12792 | } | |
12793 | else | |
12794 | { | |
12795 | if (l != 1 | |
12796 | || len != 2 | |
12797 | || last[0] != 'L') | |
12798 | { | |
12799 | SAVE_LAST (*p); | |
12800 | break; | |
12801 | } | |
12802 | ||
12803 | if (address_mode == mode_64bit | |
12804 | && !(prefixes & PREFIX_ADDR)) | |
12805 | { | |
12806 | *obufp++ = 'a'; | |
12807 | *obufp++ = 'b'; | |
12808 | *obufp++ = 's'; | |
12809 | } | |
12810 | ||
12811 | goto case_B; | |
12812 | } | |
252b5132 | 12813 | break; |
9306ca4a JB |
12814 | case 'C': |
12815 | if (intel_syntax && !alt) | |
12816 | break; | |
12817 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12818 | { | |
12819 | if (sizeflag & DFLAG) | |
12820 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12821 | else | |
12822 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12823 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12824 | } | |
12825 | break; | |
ed7841b3 JB |
12826 | case 'D': |
12827 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12828 | break; | |
161a04f6 | 12829 | USED_REX (REX_W); |
7967e09e | 12830 | if (modrm.mod == 3) |
ed7841b3 | 12831 | { |
161a04f6 | 12832 | if (rex & REX_W) |
ed7841b3 | 12833 | *obufp++ = 'q'; |
ed7841b3 | 12834 | else |
f16cd0d5 L |
12835 | { |
12836 | if (sizeflag & DFLAG) | |
12837 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12838 | else | |
12839 | *obufp++ = 'w'; | |
12840 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12841 | } | |
ed7841b3 JB |
12842 | } |
12843 | else | |
12844 | *obufp++ = 'w'; | |
12845 | break; | |
252b5132 | 12846 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12847 | if (address_mode == mode_64bit) |
c1a64871 JH |
12848 | { |
12849 | if (sizeflag & AFLAG) | |
12850 | *obufp++ = 'r'; | |
12851 | else | |
12852 | *obufp++ = 'e'; | |
12853 | } | |
12854 | else | |
12855 | if (sizeflag & AFLAG) | |
12856 | *obufp++ = 'e'; | |
3ffd33cf AM |
12857 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12858 | break; | |
12859 | case 'F': | |
db6eb5be AM |
12860 | if (intel_syntax) |
12861 | break; | |
e396998b | 12862 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12863 | { |
12864 | if (sizeflag & AFLAG) | |
cb712a9e | 12865 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12866 | else |
cb712a9e | 12867 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12868 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12869 | } | |
252b5132 | 12870 | break; |
52fd6d94 JB |
12871 | case 'G': |
12872 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12873 | break; | |
161a04f6 | 12874 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12875 | *obufp++ = 'l'; |
12876 | else | |
12877 | *obufp++ = 'w'; | |
161a04f6 | 12878 | if (!(rex & REX_W)) |
52fd6d94 JB |
12879 | used_prefixes |= (prefixes & PREFIX_DATA); |
12880 | break; | |
5dd0794d | 12881 | case 'H': |
db6eb5be AM |
12882 | if (intel_syntax) |
12883 | break; | |
5dd0794d AM |
12884 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12885 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12886 | { | |
12887 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12888 | *obufp++ = ','; | |
12889 | *obufp++ = 'p'; | |
12890 | if (prefixes & PREFIX_DS) | |
12891 | *obufp++ = 't'; | |
12892 | else | |
12893 | *obufp++ = 'n'; | |
12894 | } | |
12895 | break; | |
9306ca4a JB |
12896 | case 'J': |
12897 | if (intel_syntax) | |
12898 | break; | |
12899 | *obufp++ = 'l'; | |
12900 | break; | |
42903f7f L |
12901 | case 'K': |
12902 | USED_REX (REX_W); | |
12903 | if (rex & REX_W) | |
12904 | *obufp++ = 'q'; | |
12905 | else | |
12906 | *obufp++ = 'd'; | |
12907 | break; | |
6dd5059a | 12908 | case 'Z': |
04d824a4 JB |
12909 | if (l != 0 || len != 1) |
12910 | { | |
12911 | if (l != 1 || len != 2 || last[0] != 'X') | |
12912 | { | |
12913 | SAVE_LAST (*p); | |
12914 | break; | |
12915 | } | |
12916 | if (!need_vex || !vex.evex) | |
12917 | abort (); | |
12918 | if (intel_syntax | |
12919 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12920 | break; | |
12921 | switch (vex.length) | |
12922 | { | |
12923 | case 128: | |
12924 | *obufp++ = 'x'; | |
12925 | break; | |
12926 | case 256: | |
12927 | *obufp++ = 'y'; | |
12928 | break; | |
12929 | case 512: | |
12930 | *obufp++ = 'z'; | |
12931 | break; | |
12932 | default: | |
12933 | abort (); | |
12934 | } | |
12935 | break; | |
12936 | } | |
6dd5059a L |
12937 | if (intel_syntax) |
12938 | break; | |
12939 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12940 | { | |
12941 | *obufp++ = 'q'; | |
12942 | break; | |
12943 | } | |
12944 | /* Fall through. */ | |
98b528ac | 12945 | goto case_L; |
252b5132 | 12946 | case 'L': |
98b528ac L |
12947 | if (l != 0 || len != 1) |
12948 | { | |
12949 | SAVE_LAST (*p); | |
12950 | break; | |
12951 | } | |
12952 | case_L: | |
db6eb5be AM |
12953 | if (intel_syntax) |
12954 | break; | |
252b5132 RH |
12955 | if (sizeflag & SUFFIX_ALWAYS) |
12956 | *obufp++ = 'l'; | |
252b5132 | 12957 | break; |
9d141669 L |
12958 | case 'M': |
12959 | if (intel_mnemonic != cond) | |
12960 | *obufp++ = 'r'; | |
12961 | break; | |
252b5132 RH |
12962 | case 'N': |
12963 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12964 | *obufp++ = 'n'; | |
7d421014 ILT |
12965 | else |
12966 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12967 | break; |
52b15da3 | 12968 | case 'O': |
161a04f6 L |
12969 | USED_REX (REX_W); |
12970 | if (rex & REX_W) | |
6439fc28 | 12971 | *obufp++ = 'o'; |
a35ca55a JB |
12972 | else if (intel_syntax && (sizeflag & DFLAG)) |
12973 | *obufp++ = 'q'; | |
52b15da3 JH |
12974 | else |
12975 | *obufp++ = 'd'; | |
161a04f6 | 12976 | if (!(rex & REX_W)) |
a35ca55a | 12977 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12978 | break; |
07f5af7d L |
12979 | case '&': |
12980 | if (!intel_syntax | |
12981 | && address_mode == mode_64bit | |
12982 | && isa64 == intel64) | |
12983 | { | |
12984 | *obufp++ = 'q'; | |
12985 | break; | |
12986 | } | |
12987 | /* Fall through. */ | |
6439fc28 | 12988 | case 'T': |
d9e3625e L |
12989 | if (!intel_syntax |
12990 | && address_mode == mode_64bit | |
7bb15c6f | 12991 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12992 | { |
12993 | *obufp++ = 'q'; | |
12994 | break; | |
12995 | } | |
6608db57 | 12996 | /* Fall through. */ |
4b4c407a | 12997 | goto case_P; |
252b5132 | 12998 | case 'P': |
4b4c407a | 12999 | if (l == 0 && len == 1) |
d9e3625e | 13000 | { |
4b4c407a L |
13001 | case_P: |
13002 | if (intel_syntax) | |
d9e3625e | 13003 | { |
4b4c407a L |
13004 | if ((rex & REX_W) == 0 |
13005 | && (prefixes & PREFIX_DATA)) | |
13006 | { | |
13007 | if ((sizeflag & DFLAG) == 0) | |
13008 | *obufp++ = 'w'; | |
13009 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13010 | } | |
13011 | break; | |
13012 | } | |
13013 | if ((prefixes & PREFIX_DATA) | |
13014 | || (rex & REX_W) | |
13015 | || (sizeflag & SUFFIX_ALWAYS)) | |
13016 | { | |
13017 | USED_REX (REX_W); | |
13018 | if (rex & REX_W) | |
13019 | *obufp++ = 'q'; | |
13020 | else | |
13021 | { | |
13022 | if (sizeflag & DFLAG) | |
13023 | *obufp++ = 'l'; | |
13024 | else | |
13025 | *obufp++ = 'w'; | |
13026 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13027 | } | |
d9e3625e | 13028 | } |
d9e3625e | 13029 | } |
4b4c407a | 13030 | else |
252b5132 | 13031 | { |
4b4c407a L |
13032 | if (l != 1 || len != 2 || last[0] != 'L') |
13033 | { | |
13034 | SAVE_LAST (*p); | |
13035 | break; | |
13036 | } | |
13037 | ||
13038 | if ((prefixes & PREFIX_DATA) | |
13039 | || (rex & REX_W) | |
13040 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13041 | { |
4b4c407a L |
13042 | USED_REX (REX_W); |
13043 | if (rex & REX_W) | |
13044 | *obufp++ = 'q'; | |
13045 | else | |
13046 | { | |
13047 | if (sizeflag & DFLAG) | |
13048 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13049 | else | |
13050 | *obufp++ = 'w'; | |
13051 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13052 | } | |
52b15da3 | 13053 | } |
252b5132 RH |
13054 | } |
13055 | break; | |
6439fc28 | 13056 | case 'U': |
db6eb5be AM |
13057 | if (intel_syntax) |
13058 | break; | |
7bb15c6f | 13059 | if (address_mode == mode_64bit |
6c067bbb | 13060 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13061 | { |
7967e09e | 13062 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13063 | *obufp++ = 'q'; |
6439fc28 AM |
13064 | break; |
13065 | } | |
6608db57 | 13066 | /* Fall through. */ |
98b528ac | 13067 | goto case_Q; |
252b5132 | 13068 | case 'Q': |
98b528ac | 13069 | if (l == 0 && len == 1) |
252b5132 | 13070 | { |
98b528ac L |
13071 | case_Q: |
13072 | if (intel_syntax && !alt) | |
13073 | break; | |
13074 | USED_REX (REX_W); | |
13075 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13076 | { |
98b528ac L |
13077 | if (rex & REX_W) |
13078 | *obufp++ = 'q'; | |
52b15da3 | 13079 | else |
98b528ac L |
13080 | { |
13081 | if (sizeflag & DFLAG) | |
13082 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13083 | else | |
13084 | *obufp++ = 'w'; | |
f16cd0d5 | 13085 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13086 | } |
52b15da3 | 13087 | } |
98b528ac L |
13088 | } |
13089 | else | |
13090 | { | |
13091 | if (l != 1 || len != 2 || last[0] != 'L') | |
13092 | { | |
13093 | SAVE_LAST (*p); | |
13094 | break; | |
13095 | } | |
13096 | if (intel_syntax | |
13097 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13098 | break; | |
13099 | if ((rex & REX_W)) | |
13100 | { | |
13101 | USED_REX (REX_W); | |
13102 | *obufp++ = 'q'; | |
13103 | } | |
13104 | else | |
13105 | *obufp++ = 'l'; | |
252b5132 RH |
13106 | } |
13107 | break; | |
13108 | case 'R': | |
161a04f6 L |
13109 | USED_REX (REX_W); |
13110 | if (rex & REX_W) | |
a35ca55a JB |
13111 | *obufp++ = 'q'; |
13112 | else if (sizeflag & DFLAG) | |
c608c12e | 13113 | { |
a35ca55a | 13114 | if (intel_syntax) |
c608c12e | 13115 | *obufp++ = 'd'; |
c608c12e | 13116 | else |
a35ca55a | 13117 | *obufp++ = 'l'; |
c608c12e | 13118 | } |
252b5132 | 13119 | else |
a35ca55a JB |
13120 | *obufp++ = 'w'; |
13121 | if (intel_syntax && !p[1] | |
161a04f6 | 13122 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13123 | *obufp++ = 'e'; |
161a04f6 | 13124 | if (!(rex & REX_W)) |
52b15da3 | 13125 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13126 | break; |
1a114b12 | 13127 | case 'V': |
4b06377f | 13128 | if (l == 0 && len == 1) |
1a114b12 | 13129 | { |
4b06377f L |
13130 | if (intel_syntax) |
13131 | break; | |
7bb15c6f | 13132 | if (address_mode == mode_64bit |
6c067bbb | 13133 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13134 | { |
13135 | if (sizeflag & SUFFIX_ALWAYS) | |
13136 | *obufp++ = 'q'; | |
13137 | break; | |
13138 | } | |
13139 | } | |
13140 | else | |
13141 | { | |
13142 | if (l != 1 | |
13143 | || len != 2 | |
13144 | || last[0] != 'L') | |
13145 | { | |
13146 | SAVE_LAST (*p); | |
13147 | break; | |
13148 | } | |
13149 | ||
13150 | if (rex & REX_W) | |
13151 | { | |
13152 | *obufp++ = 'a'; | |
13153 | *obufp++ = 'b'; | |
13154 | *obufp++ = 's'; | |
13155 | } | |
1a114b12 JB |
13156 | } |
13157 | /* Fall through. */ | |
4b06377f | 13158 | goto case_S; |
252b5132 | 13159 | case 'S': |
4b06377f | 13160 | if (l == 0 && len == 1) |
252b5132 | 13161 | { |
4b06377f L |
13162 | case_S: |
13163 | if (intel_syntax) | |
13164 | break; | |
13165 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13166 | { |
4b06377f L |
13167 | if (rex & REX_W) |
13168 | *obufp++ = 'q'; | |
52b15da3 | 13169 | else |
4b06377f L |
13170 | { |
13171 | if (sizeflag & DFLAG) | |
13172 | *obufp++ = 'l'; | |
13173 | else | |
13174 | *obufp++ = 'w'; | |
13175 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13176 | } | |
13177 | } | |
13178 | } | |
13179 | else | |
13180 | { | |
13181 | if (l != 1 | |
13182 | || len != 2 | |
13183 | || last[0] != 'L') | |
13184 | { | |
13185 | SAVE_LAST (*p); | |
13186 | break; | |
52b15da3 | 13187 | } |
4b06377f L |
13188 | |
13189 | if (address_mode == mode_64bit | |
13190 | && !(prefixes & PREFIX_ADDR)) | |
13191 | { | |
13192 | *obufp++ = 'a'; | |
13193 | *obufp++ = 'b'; | |
13194 | *obufp++ = 's'; | |
13195 | } | |
13196 | ||
13197 | goto case_S; | |
252b5132 | 13198 | } |
252b5132 | 13199 | break; |
041bd2e0 | 13200 | case 'X': |
c0f3af97 L |
13201 | if (l != 0 || len != 1) |
13202 | { | |
13203 | SAVE_LAST (*p); | |
13204 | break; | |
13205 | } | |
13206 | if (need_vex && vex.prefix) | |
13207 | { | |
13208 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13209 | *obufp++ = 'd'; | |
13210 | else | |
13211 | *obufp++ = 's'; | |
13212 | } | |
041bd2e0 | 13213 | else |
f16cd0d5 L |
13214 | { |
13215 | if (prefixes & PREFIX_DATA) | |
13216 | *obufp++ = 'd'; | |
13217 | else | |
13218 | *obufp++ = 's'; | |
13219 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13220 | } | |
041bd2e0 | 13221 | break; |
76f227a5 | 13222 | case 'Y': |
c0f3af97 | 13223 | if (l == 0 && len == 1) |
9646c87b | 13224 | abort (); |
c0f3af97 L |
13225 | else |
13226 | { | |
13227 | if (l != 1 || len != 2 || last[0] != 'X') | |
13228 | { | |
13229 | SAVE_LAST (*p); | |
13230 | break; | |
13231 | } | |
13232 | if (!need_vex) | |
13233 | abort (); | |
13234 | if (intel_syntax | |
04d824a4 | 13235 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13236 | break; |
13237 | switch (vex.length) | |
13238 | { | |
13239 | case 128: | |
13240 | *obufp++ = 'x'; | |
13241 | break; | |
13242 | case 256: | |
13243 | *obufp++ = 'y'; | |
13244 | break; | |
04d824a4 JB |
13245 | case 512: |
13246 | if (!vex.evex) | |
c0f3af97 | 13247 | default: |
04d824a4 | 13248 | abort (); |
c0f3af97 | 13249 | } |
76f227a5 JH |
13250 | } |
13251 | break; | |
252b5132 | 13252 | case 'W': |
0bfee649 | 13253 | if (l == 0 && len == 1) |
a35ca55a | 13254 | { |
0bfee649 L |
13255 | /* operand size flag for cwtl, cbtw */ |
13256 | USED_REX (REX_W); | |
13257 | if (rex & REX_W) | |
13258 | { | |
13259 | if (intel_syntax) | |
13260 | *obufp++ = 'd'; | |
13261 | else | |
13262 | *obufp++ = 'l'; | |
13263 | } | |
13264 | else if (sizeflag & DFLAG) | |
13265 | *obufp++ = 'w'; | |
a35ca55a | 13266 | else |
0bfee649 L |
13267 | *obufp++ = 'b'; |
13268 | if (!(rex & REX_W)) | |
13269 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13270 | } |
252b5132 | 13271 | else |
0bfee649 | 13272 | { |
6c30d220 L |
13273 | if (l != 1 |
13274 | || len != 2 | |
13275 | || (last[0] != 'X' | |
13276 | && last[0] != 'L')) | |
0bfee649 L |
13277 | { |
13278 | SAVE_LAST (*p); | |
13279 | break; | |
13280 | } | |
13281 | if (!need_vex) | |
13282 | abort (); | |
6c30d220 L |
13283 | if (last[0] == 'X') |
13284 | *obufp++ = vex.w ? 'd': 's'; | |
13285 | else | |
13286 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13287 | } |
252b5132 | 13288 | break; |
a72d2af2 L |
13289 | case '^': |
13290 | if (intel_syntax) | |
13291 | break; | |
13292 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13293 | { | |
13294 | if (sizeflag & DFLAG) | |
13295 | *obufp++ = 'l'; | |
13296 | else | |
13297 | *obufp++ = 'w'; | |
13298 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13299 | } | |
13300 | break; | |
5db04b09 L |
13301 | case '@': |
13302 | if (intel_syntax) | |
13303 | break; | |
13304 | if (address_mode == mode_64bit | |
13305 | && (isa64 == intel64 | |
13306 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13307 | *obufp++ = 'q'; | |
13308 | else if ((prefixes & PREFIX_DATA)) | |
13309 | { | |
13310 | if (!(sizeflag & DFLAG)) | |
13311 | *obufp++ = 'w'; | |
13312 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13313 | } | |
13314 | break; | |
252b5132 | 13315 | } |
9306ca4a | 13316 | alt = 0; |
252b5132 RH |
13317 | } |
13318 | *obufp = 0; | |
ea397f5b | 13319 | mnemonicendp = obufp; |
6439fc28 | 13320 | return 0; |
252b5132 RH |
13321 | } |
13322 | ||
13323 | static void | |
26ca5450 | 13324 | oappend (const char *s) |
252b5132 | 13325 | { |
ea397f5b | 13326 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13327 | } |
13328 | ||
13329 | static void | |
26ca5450 | 13330 | append_seg (void) |
252b5132 | 13331 | { |
285ca992 L |
13332 | /* Only print the active segment register. */ |
13333 | if (!active_seg_prefix) | |
13334 | return; | |
13335 | ||
13336 | used_prefixes |= active_seg_prefix; | |
13337 | switch (active_seg_prefix) | |
7d421014 | 13338 | { |
285ca992 | 13339 | case PREFIX_CS: |
9ce09ba2 | 13340 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13341 | break; |
13342 | case PREFIX_DS: | |
9ce09ba2 | 13343 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13344 | break; |
13345 | case PREFIX_SS: | |
9ce09ba2 | 13346 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13347 | break; |
13348 | case PREFIX_ES: | |
9ce09ba2 | 13349 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13350 | break; |
13351 | case PREFIX_FS: | |
9ce09ba2 | 13352 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13353 | break; |
13354 | case PREFIX_GS: | |
9ce09ba2 | 13355 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13356 | break; |
13357 | default: | |
13358 | break; | |
7d421014 | 13359 | } |
252b5132 RH |
13360 | } |
13361 | ||
13362 | static void | |
26ca5450 | 13363 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13364 | { |
13365 | if (!intel_syntax) | |
13366 | oappend ("*"); | |
13367 | OP_E (bytemode, sizeflag); | |
13368 | } | |
13369 | ||
52b15da3 | 13370 | static void |
26ca5450 | 13371 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13372 | { |
cb712a9e | 13373 | if (address_mode == mode_64bit) |
52b15da3 JH |
13374 | { |
13375 | if (hex) | |
13376 | { | |
13377 | char tmp[30]; | |
13378 | int i; | |
13379 | buf[0] = '0'; | |
13380 | buf[1] = 'x'; | |
13381 | sprintf_vma (tmp, disp); | |
6608db57 | 13382 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13383 | strcpy (buf + 2, tmp + i); |
13384 | } | |
13385 | else | |
13386 | { | |
13387 | bfd_signed_vma v = disp; | |
13388 | char tmp[30]; | |
13389 | int i; | |
13390 | if (v < 0) | |
13391 | { | |
13392 | *(buf++) = '-'; | |
13393 | v = -disp; | |
6608db57 | 13394 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13395 | if (v < 0) |
13396 | { | |
13397 | strcpy (buf, "9223372036854775808"); | |
13398 | return; | |
13399 | } | |
13400 | } | |
13401 | if (!v) | |
13402 | { | |
13403 | strcpy (buf, "0"); | |
13404 | return; | |
13405 | } | |
13406 | ||
13407 | i = 0; | |
13408 | tmp[29] = 0; | |
13409 | while (v) | |
13410 | { | |
6608db57 | 13411 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13412 | v /= 10; |
13413 | i++; | |
13414 | } | |
13415 | strcpy (buf, tmp + 29 - i); | |
13416 | } | |
13417 | } | |
13418 | else | |
13419 | { | |
13420 | if (hex) | |
13421 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13422 | else | |
13423 | sprintf (buf, "%d", (int) disp); | |
13424 | } | |
13425 | } | |
13426 | ||
5d669648 L |
13427 | /* Put DISP in BUF as signed hex number. */ |
13428 | ||
13429 | static void | |
13430 | print_displacement (char *buf, bfd_vma disp) | |
13431 | { | |
13432 | bfd_signed_vma val = disp; | |
13433 | char tmp[30]; | |
13434 | int i, j = 0; | |
13435 | ||
13436 | if (val < 0) | |
13437 | { | |
13438 | buf[j++] = '-'; | |
13439 | val = -disp; | |
13440 | ||
13441 | /* Check for possible overflow. */ | |
13442 | if (val < 0) | |
13443 | { | |
13444 | switch (address_mode) | |
13445 | { | |
13446 | case mode_64bit: | |
13447 | strcpy (buf + j, "0x8000000000000000"); | |
13448 | break; | |
13449 | case mode_32bit: | |
13450 | strcpy (buf + j, "0x80000000"); | |
13451 | break; | |
13452 | case mode_16bit: | |
13453 | strcpy (buf + j, "0x8000"); | |
13454 | break; | |
13455 | } | |
13456 | return; | |
13457 | } | |
13458 | } | |
13459 | ||
13460 | buf[j++] = '0'; | |
13461 | buf[j++] = 'x'; | |
13462 | ||
0af1713e | 13463 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13464 | for (i = 0; tmp[i] == '0'; i++) |
13465 | continue; | |
13466 | if (tmp[i] == '\0') | |
13467 | i--; | |
13468 | strcpy (buf + j, tmp + i); | |
13469 | } | |
13470 | ||
3f31e633 JB |
13471 | static void |
13472 | intel_operand_size (int bytemode, int sizeflag) | |
13473 | { | |
43234a1e L |
13474 | if (vex.evex |
13475 | && vex.b | |
13476 | && (bytemode == x_mode | |
13477 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13478 | { | |
13479 | if (vex.w) | |
13480 | oappend ("QWORD PTR "); | |
13481 | else | |
13482 | oappend ("DWORD PTR "); | |
13483 | return; | |
13484 | } | |
3f31e633 JB |
13485 | switch (bytemode) |
13486 | { | |
13487 | case b_mode: | |
b6169b20 | 13488 | case b_swap_mode: |
42903f7f | 13489 | case dqb_mode: |
1ba585e8 | 13490 | case db_mode: |
3f31e633 JB |
13491 | oappend ("BYTE PTR "); |
13492 | break; | |
13493 | case w_mode: | |
1ba585e8 | 13494 | case dw_mode: |
3f31e633 JB |
13495 | case dqw_mode: |
13496 | oappend ("WORD PTR "); | |
13497 | break; | |
07f5af7d L |
13498 | case indir_v_mode: |
13499 | if (address_mode == mode_64bit && isa64 == intel64) | |
13500 | { | |
13501 | oappend ("QWORD PTR "); | |
13502 | break; | |
13503 | } | |
1a0670f3 | 13504 | /* Fall through. */ |
1a114b12 | 13505 | case stack_v_mode: |
7bb15c6f | 13506 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13507 | { |
13508 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13509 | break; |
13510 | } | |
1a0670f3 | 13511 | /* Fall through. */ |
3f31e633 | 13512 | case v_mode: |
b6169b20 | 13513 | case v_swap_mode: |
3f31e633 | 13514 | case dq_mode: |
161a04f6 L |
13515 | USED_REX (REX_W); |
13516 | if (rex & REX_W) | |
3f31e633 | 13517 | oappend ("QWORD PTR "); |
3f31e633 | 13518 | else |
f16cd0d5 L |
13519 | { |
13520 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13521 | oappend ("DWORD PTR "); | |
13522 | else | |
13523 | oappend ("WORD PTR "); | |
13524 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13525 | } | |
3f31e633 | 13526 | break; |
52fd6d94 | 13527 | case z_mode: |
161a04f6 | 13528 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13529 | *obufp++ = 'D'; |
13530 | oappend ("WORD PTR "); | |
161a04f6 | 13531 | if (!(rex & REX_W)) |
52fd6d94 JB |
13532 | used_prefixes |= (prefixes & PREFIX_DATA); |
13533 | break; | |
34b772a6 JB |
13534 | case a_mode: |
13535 | if (sizeflag & DFLAG) | |
13536 | oappend ("QWORD PTR "); | |
13537 | else | |
13538 | oappend ("DWORD PTR "); | |
13539 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13540 | break; | |
bc31405e L |
13541 | case movsxd_mode: |
13542 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13543 | oappend ("WORD PTR "); | |
13544 | else | |
13545 | oappend ("DWORD PTR "); | |
13546 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13547 | break; | |
3f31e633 | 13548 | case d_mode: |
539f890d L |
13549 | case d_scalar_mode: |
13550 | case d_scalar_swap_mode: | |
fa99fab2 | 13551 | case d_swap_mode: |
42903f7f | 13552 | case dqd_mode: |
3f31e633 JB |
13553 | oappend ("DWORD PTR "); |
13554 | break; | |
13555 | case q_mode: | |
539f890d L |
13556 | case q_scalar_mode: |
13557 | case q_scalar_swap_mode: | |
b6169b20 | 13558 | case q_swap_mode: |
3f31e633 JB |
13559 | oappend ("QWORD PTR "); |
13560 | break; | |
13561 | case m_mode: | |
cb712a9e | 13562 | if (address_mode == mode_64bit) |
3f31e633 JB |
13563 | oappend ("QWORD PTR "); |
13564 | else | |
13565 | oappend ("DWORD PTR "); | |
13566 | break; | |
13567 | case f_mode: | |
13568 | if (sizeflag & DFLAG) | |
13569 | oappend ("FWORD PTR "); | |
13570 | else | |
13571 | oappend ("DWORD PTR "); | |
13572 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13573 | break; | |
13574 | case t_mode: | |
13575 | oappend ("TBYTE PTR "); | |
13576 | break; | |
13577 | case x_mode: | |
b6169b20 | 13578 | case x_swap_mode: |
43234a1e L |
13579 | case evex_x_gscat_mode: |
13580 | case evex_x_nobcst_mode: | |
53467f57 IT |
13581 | case b_scalar_mode: |
13582 | case w_scalar_mode: | |
c0f3af97 L |
13583 | if (need_vex) |
13584 | { | |
13585 | switch (vex.length) | |
13586 | { | |
13587 | case 128: | |
13588 | oappend ("XMMWORD PTR "); | |
13589 | break; | |
13590 | case 256: | |
13591 | oappend ("YMMWORD PTR "); | |
13592 | break; | |
43234a1e L |
13593 | case 512: |
13594 | oappend ("ZMMWORD PTR "); | |
13595 | break; | |
c0f3af97 L |
13596 | default: |
13597 | abort (); | |
13598 | } | |
13599 | } | |
13600 | else | |
13601 | oappend ("XMMWORD PTR "); | |
13602 | break; | |
13603 | case xmm_mode: | |
3f31e633 JB |
13604 | oappend ("XMMWORD PTR "); |
13605 | break; | |
43234a1e L |
13606 | case ymm_mode: |
13607 | oappend ("YMMWORD PTR "); | |
13608 | break; | |
c0f3af97 | 13609 | case xmmq_mode: |
43234a1e | 13610 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13611 | if (!need_vex) |
13612 | abort (); | |
13613 | ||
13614 | switch (vex.length) | |
13615 | { | |
13616 | case 128: | |
13617 | oappend ("QWORD PTR "); | |
13618 | break; | |
13619 | case 256: | |
13620 | oappend ("XMMWORD PTR "); | |
13621 | break; | |
43234a1e L |
13622 | case 512: |
13623 | oappend ("YMMWORD PTR "); | |
13624 | break; | |
c0f3af97 L |
13625 | default: |
13626 | abort (); | |
13627 | } | |
13628 | break; | |
6c30d220 L |
13629 | case xmm_mb_mode: |
13630 | if (!need_vex) | |
13631 | abort (); | |
13632 | ||
13633 | switch (vex.length) | |
13634 | { | |
13635 | case 128: | |
13636 | case 256: | |
43234a1e | 13637 | case 512: |
6c30d220 L |
13638 | oappend ("BYTE PTR "); |
13639 | break; | |
13640 | default: | |
13641 | abort (); | |
13642 | } | |
13643 | break; | |
13644 | case xmm_mw_mode: | |
13645 | if (!need_vex) | |
13646 | abort (); | |
13647 | ||
13648 | switch (vex.length) | |
13649 | { | |
13650 | case 128: | |
13651 | case 256: | |
43234a1e | 13652 | case 512: |
6c30d220 L |
13653 | oappend ("WORD PTR "); |
13654 | break; | |
13655 | default: | |
13656 | abort (); | |
13657 | } | |
13658 | break; | |
13659 | case xmm_md_mode: | |
13660 | if (!need_vex) | |
13661 | abort (); | |
13662 | ||
13663 | switch (vex.length) | |
13664 | { | |
13665 | case 128: | |
13666 | case 256: | |
43234a1e | 13667 | case 512: |
6c30d220 L |
13668 | oappend ("DWORD PTR "); |
13669 | break; | |
13670 | default: | |
13671 | abort (); | |
13672 | } | |
13673 | break; | |
13674 | case xmm_mq_mode: | |
13675 | if (!need_vex) | |
13676 | abort (); | |
13677 | ||
13678 | switch (vex.length) | |
13679 | { | |
13680 | case 128: | |
13681 | case 256: | |
43234a1e | 13682 | case 512: |
6c30d220 L |
13683 | oappend ("QWORD PTR "); |
13684 | break; | |
13685 | default: | |
13686 | abort (); | |
13687 | } | |
13688 | break; | |
13689 | case xmmdw_mode: | |
13690 | if (!need_vex) | |
13691 | abort (); | |
13692 | ||
13693 | switch (vex.length) | |
13694 | { | |
13695 | case 128: | |
13696 | oappend ("WORD PTR "); | |
13697 | break; | |
13698 | case 256: | |
13699 | oappend ("DWORD PTR "); | |
13700 | break; | |
43234a1e L |
13701 | case 512: |
13702 | oappend ("QWORD PTR "); | |
13703 | break; | |
6c30d220 L |
13704 | default: |
13705 | abort (); | |
13706 | } | |
13707 | break; | |
13708 | case xmmqd_mode: | |
13709 | if (!need_vex) | |
13710 | abort (); | |
13711 | ||
13712 | switch (vex.length) | |
13713 | { | |
13714 | case 128: | |
13715 | oappend ("DWORD PTR "); | |
13716 | break; | |
13717 | case 256: | |
13718 | oappend ("QWORD PTR "); | |
13719 | break; | |
43234a1e L |
13720 | case 512: |
13721 | oappend ("XMMWORD PTR "); | |
13722 | break; | |
6c30d220 L |
13723 | default: |
13724 | abort (); | |
13725 | } | |
13726 | break; | |
c0f3af97 L |
13727 | case ymmq_mode: |
13728 | if (!need_vex) | |
13729 | abort (); | |
13730 | ||
13731 | switch (vex.length) | |
13732 | { | |
13733 | case 128: | |
13734 | oappend ("QWORD PTR "); | |
13735 | break; | |
13736 | case 256: | |
13737 | oappend ("YMMWORD PTR "); | |
13738 | break; | |
43234a1e L |
13739 | case 512: |
13740 | oappend ("ZMMWORD PTR "); | |
13741 | break; | |
c0f3af97 L |
13742 | default: |
13743 | abort (); | |
13744 | } | |
13745 | break; | |
6c30d220 L |
13746 | case ymmxmm_mode: |
13747 | if (!need_vex) | |
13748 | abort (); | |
13749 | ||
13750 | switch (vex.length) | |
13751 | { | |
13752 | case 128: | |
13753 | case 256: | |
13754 | oappend ("XMMWORD PTR "); | |
13755 | break; | |
13756 | default: | |
13757 | abort (); | |
13758 | } | |
13759 | break; | |
fb9c77c7 L |
13760 | case o_mode: |
13761 | oappend ("OWORD PTR "); | |
13762 | break; | |
43234a1e | 13763 | case xmm_mdq_mode: |
0bfee649 | 13764 | case vex_w_dq_mode: |
1c480963 | 13765 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13766 | if (!need_vex) |
13767 | abort (); | |
13768 | ||
13769 | if (vex.w) | |
13770 | oappend ("QWORD PTR "); | |
13771 | else | |
13772 | oappend ("DWORD PTR "); | |
13773 | break; | |
43234a1e L |
13774 | case vex_vsib_d_w_dq_mode: |
13775 | case vex_vsib_q_w_dq_mode: | |
13776 | if (!need_vex) | |
13777 | abort (); | |
13778 | ||
13779 | if (!vex.evex) | |
13780 | { | |
13781 | if (vex.w) | |
13782 | oappend ("QWORD PTR "); | |
13783 | else | |
13784 | oappend ("DWORD PTR "); | |
13785 | } | |
13786 | else | |
13787 | { | |
b28d1bda IT |
13788 | switch (vex.length) |
13789 | { | |
13790 | case 128: | |
13791 | oappend ("XMMWORD PTR "); | |
13792 | break; | |
13793 | case 256: | |
13794 | oappend ("YMMWORD PTR "); | |
13795 | break; | |
13796 | case 512: | |
13797 | oappend ("ZMMWORD PTR "); | |
13798 | break; | |
13799 | default: | |
13800 | abort (); | |
13801 | } | |
43234a1e L |
13802 | } |
13803 | break; | |
5fc35d96 IT |
13804 | case vex_vsib_q_w_d_mode: |
13805 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13806 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13807 | abort (); |
13808 | ||
b28d1bda IT |
13809 | switch (vex.length) |
13810 | { | |
13811 | case 128: | |
13812 | oappend ("QWORD PTR "); | |
13813 | break; | |
13814 | case 256: | |
13815 | oappend ("XMMWORD PTR "); | |
13816 | break; | |
13817 | case 512: | |
13818 | oappend ("YMMWORD PTR "); | |
13819 | break; | |
13820 | default: | |
13821 | abort (); | |
13822 | } | |
5fc35d96 IT |
13823 | |
13824 | break; | |
1ba585e8 IT |
13825 | case mask_bd_mode: |
13826 | if (!need_vex || vex.length != 128) | |
13827 | abort (); | |
13828 | if (vex.w) | |
13829 | oappend ("DWORD PTR "); | |
13830 | else | |
13831 | oappend ("BYTE PTR "); | |
13832 | break; | |
43234a1e L |
13833 | case mask_mode: |
13834 | if (!need_vex) | |
13835 | abort (); | |
1ba585e8 IT |
13836 | if (vex.w) |
13837 | oappend ("QWORD PTR "); | |
13838 | else | |
13839 | oappend ("WORD PTR "); | |
43234a1e | 13840 | break; |
6c75cc62 | 13841 | case v_bnd_mode: |
d276ec69 | 13842 | case v_bndmk_mode: |
3f31e633 JB |
13843 | default: |
13844 | break; | |
13845 | } | |
13846 | } | |
13847 | ||
252b5132 | 13848 | static void |
c0f3af97 | 13849 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13850 | { |
c0f3af97 L |
13851 | int reg = modrm.rm; |
13852 | const char **names; | |
252b5132 | 13853 | |
c0f3af97 L |
13854 | USED_REX (REX_B); |
13855 | if ((rex & REX_B)) | |
13856 | reg += 8; | |
252b5132 | 13857 | |
b6169b20 | 13858 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13859 | && (bytemode == b_swap_mode |
9f79e886 | 13860 | || bytemode == bnd_swap_mode |
60227d64 | 13861 | || bytemode == v_swap_mode)) |
b6169b20 L |
13862 | swap_operand (); |
13863 | ||
c0f3af97 | 13864 | switch (bytemode) |
252b5132 | 13865 | { |
c0f3af97 | 13866 | case b_mode: |
b6169b20 | 13867 | case b_swap_mode: |
c0f3af97 L |
13868 | USED_REX (0); |
13869 | if (rex) | |
13870 | names = names8rex; | |
13871 | else | |
13872 | names = names8; | |
13873 | break; | |
13874 | case w_mode: | |
13875 | names = names16; | |
13876 | break; | |
13877 | case d_mode: | |
1ba585e8 IT |
13878 | case dw_mode: |
13879 | case db_mode: | |
c0f3af97 L |
13880 | names = names32; |
13881 | break; | |
13882 | case q_mode: | |
13883 | names = names64; | |
13884 | break; | |
13885 | case m_mode: | |
6c75cc62 | 13886 | case v_bnd_mode: |
c0f3af97 L |
13887 | names = address_mode == mode_64bit ? names64 : names32; |
13888 | break; | |
7e8b059b | 13889 | case bnd_mode: |
9f79e886 | 13890 | case bnd_swap_mode: |
0d96e4df L |
13891 | if (reg > 0x3) |
13892 | { | |
13893 | oappend ("(bad)"); | |
13894 | return; | |
13895 | } | |
7e8b059b L |
13896 | names = names_bnd; |
13897 | break; | |
07f5af7d L |
13898 | case indir_v_mode: |
13899 | if (address_mode == mode_64bit && isa64 == intel64) | |
13900 | { | |
13901 | names = names64; | |
13902 | break; | |
13903 | } | |
1a0670f3 | 13904 | /* Fall through. */ |
c0f3af97 | 13905 | case stack_v_mode: |
7bb15c6f | 13906 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13907 | { |
c0f3af97 | 13908 | names = names64; |
252b5132 | 13909 | break; |
252b5132 | 13910 | } |
c0f3af97 | 13911 | bytemode = v_mode; |
1a0670f3 | 13912 | /* Fall through. */ |
c0f3af97 | 13913 | case v_mode: |
b6169b20 | 13914 | case v_swap_mode: |
c0f3af97 L |
13915 | case dq_mode: |
13916 | case dqb_mode: | |
13917 | case dqd_mode: | |
13918 | case dqw_mode: | |
13919 | USED_REX (REX_W); | |
13920 | if (rex & REX_W) | |
13921 | names = names64; | |
c0f3af97 | 13922 | else |
f16cd0d5 | 13923 | { |
7bb15c6f | 13924 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13925 | || (bytemode != v_mode |
13926 | && bytemode != v_swap_mode)) | |
13927 | names = names32; | |
13928 | else | |
13929 | names = names16; | |
13930 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13931 | } | |
c0f3af97 | 13932 | break; |
bc31405e L |
13933 | case movsxd_mode: |
13934 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13935 | names = names16; | |
13936 | else | |
13937 | names = names32; | |
13938 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13939 | break; | |
de89d0a3 IT |
13940 | case va_mode: |
13941 | names = (address_mode == mode_64bit | |
13942 | ? names64 : names32); | |
13943 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13944 | names = (address_mode == mode_16bit |
13945 | ? names16 : names); | |
de89d0a3 IT |
13946 | else |
13947 | { | |
13948 | /* Remove "addr16/addr32". */ | |
13949 | all_prefixes[last_addr_prefix] = 0; | |
13950 | names = (address_mode != mode_32bit | |
13951 | ? names32 : names16); | |
13952 | used_prefixes |= PREFIX_ADDR; | |
13953 | } | |
13954 | break; | |
1ba585e8 | 13955 | case mask_bd_mode: |
43234a1e | 13956 | case mask_mode: |
9889cbb1 L |
13957 | if (reg > 0x7) |
13958 | { | |
13959 | oappend ("(bad)"); | |
13960 | return; | |
13961 | } | |
43234a1e L |
13962 | names = names_mask; |
13963 | break; | |
c0f3af97 L |
13964 | case 0: |
13965 | return; | |
13966 | default: | |
13967 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13968 | return; |
13969 | } | |
c0f3af97 L |
13970 | oappend (names[reg]); |
13971 | } | |
13972 | ||
13973 | static void | |
c1e679ec | 13974 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13975 | { |
13976 | bfd_vma disp = 0; | |
13977 | int add = (rex & REX_B) ? 8 : 0; | |
13978 | int riprel = 0; | |
43234a1e L |
13979 | int shift; |
13980 | ||
13981 | if (vex.evex) | |
13982 | { | |
13983 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13984 | if (vex.b | |
13985 | && bytemode != x_mode | |
90a915bf | 13986 | && bytemode != xmmq_mode |
43234a1e L |
13987 | && bytemode != evex_half_bcst_xmmq_mode) |
13988 | { | |
13989 | BadOp (); | |
13990 | return; | |
13991 | } | |
13992 | switch (bytemode) | |
13993 | { | |
1ba585e8 IT |
13994 | case dqw_mode: |
13995 | case dw_mode: | |
1ba585e8 IT |
13996 | shift = 1; |
13997 | break; | |
13998 | case dqb_mode: | |
13999 | case db_mode: | |
14000 | shift = 0; | |
14001 | break; | |
b50c9f31 JB |
14002 | case dq_mode: |
14003 | if (address_mode != mode_64bit) | |
14004 | { | |
14005 | shift = 2; | |
14006 | break; | |
14007 | } | |
14008 | /* fall through */ | |
43234a1e | 14009 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14010 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14011 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14012 | case vex_vsib_q_w_d_mode: |
43234a1e L |
14013 | case evex_x_gscat_mode: |
14014 | case xmm_mdq_mode: | |
14015 | shift = vex.w ? 3 : 2; | |
14016 | break; | |
43234a1e L |
14017 | case x_mode: |
14018 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14019 | case xmmq_mode: |
43234a1e L |
14020 | if (vex.b) |
14021 | { | |
14022 | shift = vex.w ? 3 : 2; | |
14023 | break; | |
14024 | } | |
1a0670f3 | 14025 | /* Fall through. */ |
43234a1e L |
14026 | case xmmqd_mode: |
14027 | case xmmdw_mode: | |
43234a1e L |
14028 | case ymmq_mode: |
14029 | case evex_x_nobcst_mode: | |
14030 | case x_swap_mode: | |
14031 | switch (vex.length) | |
14032 | { | |
14033 | case 128: | |
14034 | shift = 4; | |
14035 | break; | |
14036 | case 256: | |
14037 | shift = 5; | |
14038 | break; | |
14039 | case 512: | |
14040 | shift = 6; | |
14041 | break; | |
14042 | default: | |
14043 | abort (); | |
14044 | } | |
14045 | break; | |
14046 | case ymm_mode: | |
14047 | shift = 5; | |
14048 | break; | |
14049 | case xmm_mode: | |
14050 | shift = 4; | |
14051 | break; | |
14052 | case xmm_mq_mode: | |
14053 | case q_mode: | |
14054 | case q_scalar_mode: | |
14055 | case q_swap_mode: | |
14056 | case q_scalar_swap_mode: | |
14057 | shift = 3; | |
14058 | break; | |
14059 | case dqd_mode: | |
14060 | case xmm_md_mode: | |
14061 | case d_mode: | |
14062 | case d_scalar_mode: | |
14063 | case d_swap_mode: | |
14064 | case d_scalar_swap_mode: | |
14065 | shift = 2; | |
14066 | break; | |
5074ad8a | 14067 | case w_scalar_mode: |
43234a1e L |
14068 | case xmm_mw_mode: |
14069 | shift = 1; | |
14070 | break; | |
5074ad8a | 14071 | case b_scalar_mode: |
43234a1e L |
14072 | case xmm_mb_mode: |
14073 | shift = 0; | |
14074 | break; | |
14075 | default: | |
14076 | abort (); | |
14077 | } | |
14078 | /* Make necessary corrections to shift for modes that need it. | |
14079 | For these modes we currently have shift 4, 5 or 6 depending on | |
14080 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14081 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14082 | xmmq_mode). In case of broadcast enabled the corrections | |
14083 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14084 | if (!vex.b |
14085 | && (bytemode == xmmq_mode | |
14086 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14087 | shift -= 1; |
14088 | else if (bytemode == xmmqd_mode) | |
14089 | shift -= 2; | |
14090 | else if (bytemode == xmmdw_mode) | |
14091 | shift -= 3; | |
b28d1bda IT |
14092 | else if (bytemode == ymmq_mode && vex.length == 128) |
14093 | shift -= 1; | |
43234a1e L |
14094 | } |
14095 | else | |
14096 | shift = 0; | |
252b5132 | 14097 | |
c0f3af97 | 14098 | USED_REX (REX_B); |
3f31e633 JB |
14099 | if (intel_syntax) |
14100 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14101 | append_seg (); |
14102 | ||
5d669648 | 14103 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14104 | { |
5d669648 L |
14105 | /* 32/64 bit address mode */ |
14106 | int havedisp; | |
252b5132 RH |
14107 | int havesib; |
14108 | int havebase; | |
0f7da397 | 14109 | int haveindex; |
20afcfb7 | 14110 | int needindex; |
1bc60e56 | 14111 | int needaddr32; |
82c18208 | 14112 | int base, rbase; |
91d6fa6a | 14113 | int vindex = 0; |
252b5132 | 14114 | int scale = 0; |
7e8b059b L |
14115 | int addr32flag = !((sizeflag & AFLAG) |
14116 | || bytemode == v_bnd_mode | |
d276ec69 | 14117 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14118 | || bytemode == bnd_mode |
14119 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14120 | const char **indexes64 = names64; |
14121 | const char **indexes32 = names32; | |
252b5132 RH |
14122 | |
14123 | havesib = 0; | |
14124 | havebase = 1; | |
0f7da397 | 14125 | haveindex = 0; |
7967e09e | 14126 | base = modrm.rm; |
252b5132 RH |
14127 | |
14128 | if (base == 4) | |
14129 | { | |
14130 | havesib = 1; | |
dfc8cf43 | 14131 | vindex = sib.index; |
161a04f6 L |
14132 | USED_REX (REX_X); |
14133 | if (rex & REX_X) | |
91d6fa6a | 14134 | vindex += 8; |
6c30d220 L |
14135 | switch (bytemode) |
14136 | { | |
14137 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14138 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14139 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14140 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14141 | if (!need_vex) |
14142 | abort (); | |
43234a1e L |
14143 | if (vex.evex) |
14144 | { | |
14145 | if (!vex.v) | |
14146 | vindex += 16; | |
14147 | } | |
6c30d220 L |
14148 | |
14149 | haveindex = 1; | |
14150 | switch (vex.length) | |
14151 | { | |
14152 | case 128: | |
7bb15c6f | 14153 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14154 | break; |
14155 | case 256: | |
5fc35d96 IT |
14156 | if (!vex.w |
14157 | || bytemode == vex_vsib_q_w_dq_mode | |
14158 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14159 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14160 | else |
7bb15c6f | 14161 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14162 | break; |
43234a1e | 14163 | case 512: |
5fc35d96 IT |
14164 | if (!vex.w |
14165 | || bytemode == vex_vsib_q_w_dq_mode | |
14166 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14167 | indexes64 = indexes32 = names_zmm; |
14168 | else | |
14169 | indexes64 = indexes32 = names_ymm; | |
14170 | break; | |
6c30d220 L |
14171 | default: |
14172 | abort (); | |
14173 | } | |
14174 | break; | |
14175 | default: | |
14176 | haveindex = vindex != 4; | |
14177 | break; | |
14178 | } | |
14179 | scale = sib.scale; | |
14180 | base = sib.base; | |
252b5132 RH |
14181 | codep++; |
14182 | } | |
82c18208 | 14183 | rbase = base + add; |
252b5132 | 14184 | |
7967e09e | 14185 | switch (modrm.mod) |
252b5132 RH |
14186 | { |
14187 | case 0: | |
82c18208 | 14188 | if (base == 5) |
252b5132 RH |
14189 | { |
14190 | havebase = 0; | |
cb712a9e | 14191 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14192 | riprel = 1; |
14193 | disp = get32s (); | |
d276ec69 JB |
14194 | if (riprel && bytemode == v_bndmk_mode) |
14195 | { | |
14196 | oappend ("(bad)"); | |
14197 | return; | |
14198 | } | |
252b5132 RH |
14199 | } |
14200 | break; | |
14201 | case 1: | |
14202 | FETCH_DATA (the_info, codep + 1); | |
14203 | disp = *codep++; | |
14204 | if ((disp & 0x80) != 0) | |
14205 | disp -= 0x100; | |
43234a1e L |
14206 | if (vex.evex && shift > 0) |
14207 | disp <<= shift; | |
252b5132 RH |
14208 | break; |
14209 | case 2: | |
52b15da3 | 14210 | disp = get32s (); |
252b5132 RH |
14211 | break; |
14212 | } | |
14213 | ||
1bc60e56 L |
14214 | needindex = 0; |
14215 | needaddr32 = 0; | |
14216 | if (havesib | |
14217 | && !havebase | |
14218 | && !haveindex | |
14219 | && address_mode != mode_16bit) | |
14220 | { | |
14221 | if (address_mode == mode_64bit) | |
14222 | { | |
14223 | /* Display eiz instead of addr32. */ | |
14224 | needindex = addr32flag; | |
14225 | needaddr32 = 1; | |
14226 | } | |
14227 | else | |
14228 | { | |
14229 | /* In 32-bit mode, we need index register to tell [offset] | |
14230 | from [eiz*1 + offset]. */ | |
14231 | needindex = 1; | |
14232 | } | |
14233 | } | |
14234 | ||
20afcfb7 L |
14235 | havedisp = (havebase |
14236 | || needindex | |
14237 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14238 | |
252b5132 | 14239 | if (!intel_syntax) |
82c18208 | 14240 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14241 | { |
5d669648 L |
14242 | if (havedisp || riprel) |
14243 | print_displacement (scratchbuf, disp); | |
14244 | else | |
14245 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14246 | oappend (scratchbuf); |
52b15da3 JH |
14247 | if (riprel) |
14248 | { | |
14249 | set_op (disp, 1); | |
28596323 | 14250 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14251 | } |
db6eb5be | 14252 | } |
2da11e11 | 14253 | |
c1dc7af5 | 14254 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
7e8b059b | 14255 | && (bytemode != v_bnd_mode) |
d276ec69 | 14256 | && (bytemode != v_bndmk_mode) |
9f79e886 JB |
14257 | && (bytemode != bnd_mode) |
14258 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
14259 | used_prefixes |= PREFIX_ADDR; |
14260 | ||
5d669648 | 14261 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14262 | { |
252b5132 | 14263 | *obufp++ = open_char; |
52b15da3 | 14264 | if (intel_syntax && riprel) |
185b1163 L |
14265 | { |
14266 | set_op (disp, 1); | |
28596323 | 14267 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14268 | } |
db6eb5be | 14269 | *obufp = '\0'; |
252b5132 | 14270 | if (havebase) |
7e8b059b | 14271 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14272 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14273 | if (havesib) |
14274 | { | |
db51cc60 L |
14275 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14276 | print index to tell base + index from base. */ | |
14277 | if (scale != 0 | |
20afcfb7 | 14278 | || needindex |
db51cc60 L |
14279 | || haveindex |
14280 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14281 | { |
9306ca4a | 14282 | if (!intel_syntax || havebase) |
db6eb5be | 14283 | { |
9306ca4a JB |
14284 | *obufp++ = separator_char; |
14285 | *obufp = '\0'; | |
db6eb5be | 14286 | } |
db51cc60 | 14287 | if (haveindex) |
7e8b059b | 14288 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14289 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14290 | else |
7e8b059b | 14291 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14292 | ? index64 : index32); |
14293 | ||
db6eb5be AM |
14294 | *obufp++ = scale_char; |
14295 | *obufp = '\0'; | |
14296 | sprintf (scratchbuf, "%d", 1 << scale); | |
14297 | oappend (scratchbuf); | |
14298 | } | |
252b5132 | 14299 | } |
185b1163 | 14300 | if (intel_syntax |
82c18208 | 14301 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14302 | { |
db51cc60 | 14303 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14304 | { |
14305 | *obufp++ = '+'; | |
14306 | *obufp = '\0'; | |
14307 | } | |
05203043 | 14308 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14309 | { |
14310 | *obufp++ = '-'; | |
14311 | *obufp = '\0'; | |
14312 | disp = - (bfd_signed_vma) disp; | |
14313 | } | |
14314 | ||
db51cc60 L |
14315 | if (havedisp) |
14316 | print_displacement (scratchbuf, disp); | |
14317 | else | |
14318 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14319 | oappend (scratchbuf); |
14320 | } | |
252b5132 RH |
14321 | |
14322 | *obufp++ = close_char; | |
db6eb5be | 14323 | *obufp = '\0'; |
252b5132 RH |
14324 | } |
14325 | else if (intel_syntax) | |
db6eb5be | 14326 | { |
82c18208 | 14327 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14328 | { |
285ca992 | 14329 | if (!active_seg_prefix) |
252b5132 | 14330 | { |
d708bcba | 14331 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14332 | oappend (":"); |
14333 | } | |
52b15da3 | 14334 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14335 | oappend (scratchbuf); |
14336 | } | |
14337 | } | |
252b5132 RH |
14338 | } |
14339 | else | |
f16cd0d5 L |
14340 | { |
14341 | /* 16 bit address mode */ | |
14342 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14343 | switch (modrm.mod) |
252b5132 RH |
14344 | { |
14345 | case 0: | |
7967e09e | 14346 | if (modrm.rm == 6) |
252b5132 RH |
14347 | { |
14348 | disp = get16 (); | |
14349 | if ((disp & 0x8000) != 0) | |
14350 | disp -= 0x10000; | |
14351 | } | |
14352 | break; | |
14353 | case 1: | |
14354 | FETCH_DATA (the_info, codep + 1); | |
14355 | disp = *codep++; | |
14356 | if ((disp & 0x80) != 0) | |
14357 | disp -= 0x100; | |
65f3ed04 JB |
14358 | if (vex.evex && shift > 0) |
14359 | disp <<= shift; | |
252b5132 RH |
14360 | break; |
14361 | case 2: | |
14362 | disp = get16 (); | |
14363 | if ((disp & 0x8000) != 0) | |
14364 | disp -= 0x10000; | |
14365 | break; | |
14366 | } | |
14367 | ||
14368 | if (!intel_syntax) | |
7967e09e | 14369 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14370 | { |
5d669648 | 14371 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14372 | oappend (scratchbuf); |
14373 | } | |
252b5132 | 14374 | |
7967e09e | 14375 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14376 | { |
14377 | *obufp++ = open_char; | |
db6eb5be | 14378 | *obufp = '\0'; |
7967e09e | 14379 | oappend (index16[modrm.rm]); |
5d669648 L |
14380 | if (intel_syntax |
14381 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14382 | { |
5d669648 | 14383 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14384 | { |
14385 | *obufp++ = '+'; | |
14386 | *obufp = '\0'; | |
14387 | } | |
7967e09e | 14388 | else if (modrm.mod != 1) |
3d456fa1 JB |
14389 | { |
14390 | *obufp++ = '-'; | |
14391 | *obufp = '\0'; | |
14392 | disp = - (bfd_signed_vma) disp; | |
14393 | } | |
14394 | ||
5d669648 | 14395 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14396 | oappend (scratchbuf); |
14397 | } | |
14398 | ||
db6eb5be AM |
14399 | *obufp++ = close_char; |
14400 | *obufp = '\0'; | |
252b5132 | 14401 | } |
3d456fa1 JB |
14402 | else if (intel_syntax) |
14403 | { | |
285ca992 | 14404 | if (!active_seg_prefix) |
3d456fa1 JB |
14405 | { |
14406 | oappend (names_seg[ds_reg - es_reg]); | |
14407 | oappend (":"); | |
14408 | } | |
14409 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14410 | oappend (scratchbuf); | |
14411 | } | |
252b5132 | 14412 | } |
43234a1e L |
14413 | if (vex.evex && vex.b |
14414 | && (bytemode == x_mode | |
90a915bf | 14415 | || bytemode == xmmq_mode |
43234a1e L |
14416 | || bytemode == evex_half_bcst_xmmq_mode)) |
14417 | { | |
90a915bf IT |
14418 | if (vex.w |
14419 | || bytemode == xmmq_mode | |
14420 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14421 | { |
14422 | switch (vex.length) | |
14423 | { | |
14424 | case 128: | |
14425 | oappend ("{1to2}"); | |
14426 | break; | |
14427 | case 256: | |
14428 | oappend ("{1to4}"); | |
14429 | break; | |
14430 | case 512: | |
14431 | oappend ("{1to8}"); | |
14432 | break; | |
14433 | default: | |
14434 | abort (); | |
14435 | } | |
14436 | } | |
43234a1e | 14437 | else |
b28d1bda IT |
14438 | { |
14439 | switch (vex.length) | |
14440 | { | |
14441 | case 128: | |
14442 | oappend ("{1to4}"); | |
14443 | break; | |
14444 | case 256: | |
14445 | oappend ("{1to8}"); | |
14446 | break; | |
14447 | case 512: | |
14448 | oappend ("{1to16}"); | |
14449 | break; | |
14450 | default: | |
14451 | abort (); | |
14452 | } | |
14453 | } | |
43234a1e | 14454 | } |
252b5132 RH |
14455 | } |
14456 | ||
c0f3af97 | 14457 | static void |
8b3f93e7 | 14458 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14459 | { |
14460 | /* Skip mod/rm byte. */ | |
14461 | MODRM_CHECK; | |
14462 | codep++; | |
14463 | ||
14464 | if (modrm.mod == 3) | |
14465 | OP_E_register (bytemode, sizeflag); | |
14466 | else | |
c1e679ec | 14467 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14468 | } |
14469 | ||
252b5132 | 14470 | static void |
26ca5450 | 14471 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14472 | { |
52b15da3 | 14473 | int add = 0; |
c0a30a9f | 14474 | const char **names; |
161a04f6 L |
14475 | USED_REX (REX_R); |
14476 | if (rex & REX_R) | |
52b15da3 | 14477 | add += 8; |
252b5132 RH |
14478 | switch (bytemode) |
14479 | { | |
14480 | case b_mode: | |
52b15da3 JH |
14481 | USED_REX (0); |
14482 | if (rex) | |
7967e09e | 14483 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14484 | else |
7967e09e | 14485 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14486 | break; |
14487 | case w_mode: | |
7967e09e | 14488 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14489 | break; |
14490 | case d_mode: | |
1ba585e8 IT |
14491 | case db_mode: |
14492 | case dw_mode: | |
7967e09e | 14493 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14494 | break; |
14495 | case q_mode: | |
7967e09e | 14496 | oappend (names64[modrm.reg + add]); |
252b5132 | 14497 | break; |
7e8b059b | 14498 | case bnd_mode: |
0d96e4df L |
14499 | if (modrm.reg > 0x3) |
14500 | { | |
14501 | oappend ("(bad)"); | |
14502 | return; | |
14503 | } | |
7e8b059b L |
14504 | oappend (names_bnd[modrm.reg]); |
14505 | break; | |
252b5132 | 14506 | case v_mode: |
9306ca4a | 14507 | case dq_mode: |
42903f7f L |
14508 | case dqb_mode: |
14509 | case dqd_mode: | |
9306ca4a | 14510 | case dqw_mode: |
bc31405e | 14511 | case movsxd_mode: |
161a04f6 L |
14512 | USED_REX (REX_W); |
14513 | if (rex & REX_W) | |
7967e09e | 14514 | oappend (names64[modrm.reg + add]); |
252b5132 | 14515 | else |
f16cd0d5 | 14516 | { |
bc31405e L |
14517 | if ((sizeflag & DFLAG) |
14518 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14519 | oappend (names32[modrm.reg + add]); |
14520 | else | |
14521 | oappend (names16[modrm.reg + add]); | |
14522 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14523 | } | |
252b5132 | 14524 | break; |
c0a30a9f L |
14525 | case va_mode: |
14526 | names = (address_mode == mode_64bit | |
14527 | ? names64 : names32); | |
14528 | if (!(prefixes & PREFIX_ADDR)) | |
14529 | { | |
14530 | if (address_mode == mode_16bit) | |
14531 | names = names16; | |
14532 | } | |
14533 | else | |
14534 | { | |
14535 | /* Remove "addr16/addr32". */ | |
14536 | all_prefixes[last_addr_prefix] = 0; | |
14537 | names = (address_mode != mode_32bit | |
14538 | ? names32 : names16); | |
14539 | used_prefixes |= PREFIX_ADDR; | |
14540 | } | |
14541 | oappend (names[modrm.reg + add]); | |
14542 | break; | |
90700ea2 | 14543 | case m_mode: |
cb712a9e | 14544 | if (address_mode == mode_64bit) |
7967e09e | 14545 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14546 | else |
7967e09e | 14547 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14548 | break; |
1ba585e8 | 14549 | case mask_bd_mode: |
43234a1e | 14550 | case mask_mode: |
9889cbb1 L |
14551 | if ((modrm.reg + add) > 0x7) |
14552 | { | |
14553 | oappend ("(bad)"); | |
14554 | return; | |
14555 | } | |
43234a1e L |
14556 | oappend (names_mask[modrm.reg + add]); |
14557 | break; | |
252b5132 RH |
14558 | default: |
14559 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14560 | break; | |
14561 | } | |
14562 | } | |
14563 | ||
52b15da3 | 14564 | static bfd_vma |
26ca5450 | 14565 | get64 (void) |
52b15da3 | 14566 | { |
5dd0794d | 14567 | bfd_vma x; |
52b15da3 | 14568 | #ifdef BFD64 |
5dd0794d AM |
14569 | unsigned int a; |
14570 | unsigned int b; | |
14571 | ||
52b15da3 JH |
14572 | FETCH_DATA (the_info, codep + 8); |
14573 | a = *codep++ & 0xff; | |
14574 | a |= (*codep++ & 0xff) << 8; | |
14575 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14576 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14577 | b = *codep++ & 0xff; |
52b15da3 JH |
14578 | b |= (*codep++ & 0xff) << 8; |
14579 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14580 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14581 | x = a + ((bfd_vma) b << 32); |
14582 | #else | |
6608db57 | 14583 | abort (); |
5dd0794d | 14584 | x = 0; |
52b15da3 JH |
14585 | #endif |
14586 | return x; | |
14587 | } | |
14588 | ||
14589 | static bfd_signed_vma | |
26ca5450 | 14590 | get32 (void) |
252b5132 | 14591 | { |
52b15da3 | 14592 | bfd_signed_vma x = 0; |
252b5132 RH |
14593 | |
14594 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14595 | x = *codep++ & (bfd_signed_vma) 0xff; |
14596 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14597 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14598 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14599 | return x; | |
14600 | } | |
14601 | ||
14602 | static bfd_signed_vma | |
26ca5450 | 14603 | get32s (void) |
52b15da3 JH |
14604 | { |
14605 | bfd_signed_vma x = 0; | |
14606 | ||
14607 | FETCH_DATA (the_info, codep + 4); | |
14608 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14609 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14610 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14611 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14612 | ||
14613 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14614 | ||
252b5132 RH |
14615 | return x; |
14616 | } | |
14617 | ||
14618 | static int | |
26ca5450 | 14619 | get16 (void) |
252b5132 RH |
14620 | { |
14621 | int x = 0; | |
14622 | ||
14623 | FETCH_DATA (the_info, codep + 2); | |
14624 | x = *codep++ & 0xff; | |
14625 | x |= (*codep++ & 0xff) << 8; | |
14626 | return x; | |
14627 | } | |
14628 | ||
14629 | static void | |
26ca5450 | 14630 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14631 | { |
14632 | op_index[op_ad] = op_ad; | |
cb712a9e | 14633 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14634 | { |
14635 | op_address[op_ad] = op; | |
14636 | op_riprel[op_ad] = riprel; | |
14637 | } | |
14638 | else | |
14639 | { | |
14640 | /* Mask to get a 32-bit address. */ | |
14641 | op_address[op_ad] = op & 0xffffffff; | |
14642 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14643 | } | |
252b5132 RH |
14644 | } |
14645 | ||
14646 | static void | |
26ca5450 | 14647 | OP_REG (int code, int sizeflag) |
252b5132 | 14648 | { |
2da11e11 | 14649 | const char *s; |
9b60702d | 14650 | int add; |
de882298 RM |
14651 | |
14652 | switch (code) | |
14653 | { | |
14654 | case es_reg: case ss_reg: case cs_reg: | |
14655 | case ds_reg: case fs_reg: case gs_reg: | |
14656 | oappend (names_seg[code - es_reg]); | |
14657 | return; | |
14658 | } | |
14659 | ||
161a04f6 L |
14660 | USED_REX (REX_B); |
14661 | if (rex & REX_B) | |
52b15da3 | 14662 | add = 8; |
9b60702d L |
14663 | else |
14664 | add = 0; | |
52b15da3 JH |
14665 | |
14666 | switch (code) | |
14667 | { | |
52b15da3 JH |
14668 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14669 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14670 | s = names16[code - ax_reg + add]; | |
14671 | break; | |
52b15da3 JH |
14672 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14673 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14674 | USED_REX (0); | |
14675 | if (rex) | |
14676 | s = names8rex[code - al_reg + add]; | |
14677 | else | |
14678 | s = names8[code - al_reg]; | |
14679 | break; | |
6439fc28 AM |
14680 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14681 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14682 | if (address_mode == mode_64bit |
6c067bbb | 14683 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14684 | { |
14685 | s = names64[code - rAX_reg + add]; | |
14686 | break; | |
14687 | } | |
14688 | code += eAX_reg - rAX_reg; | |
6608db57 | 14689 | /* Fall through. */ |
52b15da3 JH |
14690 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14691 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14692 | USED_REX (REX_W); |
14693 | if (rex & REX_W) | |
52b15da3 | 14694 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14695 | else |
f16cd0d5 L |
14696 | { |
14697 | if (sizeflag & DFLAG) | |
14698 | s = names32[code - eAX_reg + add]; | |
14699 | else | |
14700 | s = names16[code - eAX_reg + add]; | |
14701 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14702 | } | |
52b15da3 | 14703 | break; |
52b15da3 JH |
14704 | default: |
14705 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14706 | break; | |
14707 | } | |
14708 | oappend (s); | |
14709 | } | |
14710 | ||
14711 | static void | |
26ca5450 | 14712 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14713 | { |
14714 | const char *s; | |
252b5132 RH |
14715 | |
14716 | switch (code) | |
14717 | { | |
14718 | case indir_dx_reg: | |
d708bcba | 14719 | if (intel_syntax) |
52fd6d94 | 14720 | s = "dx"; |
d708bcba | 14721 | else |
db6eb5be | 14722 | s = "(%dx)"; |
252b5132 RH |
14723 | break; |
14724 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14725 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14726 | s = names16[code - ax_reg]; | |
14727 | break; | |
14728 | case es_reg: case ss_reg: case cs_reg: | |
14729 | case ds_reg: case fs_reg: case gs_reg: | |
14730 | s = names_seg[code - es_reg]; | |
14731 | break; | |
14732 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14733 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14734 | USED_REX (0); |
14735 | if (rex) | |
14736 | s = names8rex[code - al_reg]; | |
14737 | else | |
14738 | s = names8[code - al_reg]; | |
252b5132 RH |
14739 | break; |
14740 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14741 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14742 | USED_REX (REX_W); |
14743 | if (rex & REX_W) | |
52b15da3 | 14744 | s = names64[code - eAX_reg]; |
252b5132 | 14745 | else |
f16cd0d5 L |
14746 | { |
14747 | if (sizeflag & DFLAG) | |
14748 | s = names32[code - eAX_reg]; | |
14749 | else | |
14750 | s = names16[code - eAX_reg]; | |
14751 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14752 | } | |
252b5132 | 14753 | break; |
52fd6d94 | 14754 | case z_mode_ax_reg: |
161a04f6 | 14755 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14756 | s = *names32; |
14757 | else | |
14758 | s = *names16; | |
161a04f6 | 14759 | if (!(rex & REX_W)) |
52fd6d94 JB |
14760 | used_prefixes |= (prefixes & PREFIX_DATA); |
14761 | break; | |
252b5132 RH |
14762 | default: |
14763 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14764 | break; | |
14765 | } | |
14766 | oappend (s); | |
14767 | } | |
14768 | ||
14769 | static void | |
26ca5450 | 14770 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14771 | { |
52b15da3 JH |
14772 | bfd_signed_vma op; |
14773 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14774 | |
14775 | switch (bytemode) | |
14776 | { | |
14777 | case b_mode: | |
14778 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14779 | op = *codep++; |
14780 | mask = 0xff; | |
14781 | break; | |
252b5132 | 14782 | case v_mode: |
161a04f6 L |
14783 | USED_REX (REX_W); |
14784 | if (rex & REX_W) | |
52b15da3 | 14785 | op = get32s (); |
252b5132 | 14786 | else |
52b15da3 | 14787 | { |
f16cd0d5 L |
14788 | if (sizeflag & DFLAG) |
14789 | { | |
14790 | op = get32 (); | |
14791 | mask = 0xffffffff; | |
14792 | } | |
14793 | else | |
14794 | { | |
14795 | op = get16 (); | |
14796 | mask = 0xfffff; | |
14797 | } | |
14798 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14799 | } |
252b5132 | 14800 | break; |
c1dc7af5 JB |
14801 | case d_mode: |
14802 | mask = 0xffffffff; | |
14803 | op = get32 (); | |
14804 | break; | |
252b5132 | 14805 | case w_mode: |
52b15da3 | 14806 | mask = 0xfffff; |
252b5132 RH |
14807 | op = get16 (); |
14808 | break; | |
9306ca4a JB |
14809 | case const_1_mode: |
14810 | if (intel_syntax) | |
6c067bbb | 14811 | oappend ("1"); |
9306ca4a | 14812 | return; |
252b5132 RH |
14813 | default: |
14814 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14815 | return; | |
14816 | } | |
14817 | ||
52b15da3 JH |
14818 | op &= mask; |
14819 | scratchbuf[0] = '$'; | |
d708bcba | 14820 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14821 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14822 | scratchbuf[0] = '\0'; |
14823 | } | |
14824 | ||
14825 | static void | |
26ca5450 | 14826 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14827 | { |
a280ab8e | 14828 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14829 | { |
14830 | OP_I (bytemode, sizeflag); | |
14831 | return; | |
14832 | } | |
14833 | ||
a280ab8e | 14834 | USED_REX (REX_W); |
52b15da3 | 14835 | |
52b15da3 | 14836 | scratchbuf[0] = '$'; |
a280ab8e | 14837 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14838 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14839 | scratchbuf[0] = '\0'; |
14840 | } | |
14841 | ||
14842 | static void | |
26ca5450 | 14843 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14844 | { |
52b15da3 | 14845 | bfd_signed_vma op; |
252b5132 RH |
14846 | |
14847 | switch (bytemode) | |
14848 | { | |
14849 | case b_mode: | |
e3949f17 | 14850 | case b_T_mode: |
252b5132 RH |
14851 | FETCH_DATA (the_info, codep + 1); |
14852 | op = *codep++; | |
14853 | if ((op & 0x80) != 0) | |
14854 | op -= 0x100; | |
e3949f17 L |
14855 | if (bytemode == b_T_mode) |
14856 | { | |
14857 | if (address_mode != mode_64bit | |
7bb15c6f | 14858 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14859 | { |
6c067bbb RM |
14860 | /* The operand-size prefix is overridden by a REX prefix. */ |
14861 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14862 | op &= 0xffffffff; |
14863 | else | |
14864 | op &= 0xffff; | |
14865 | } | |
14866 | } | |
14867 | else | |
14868 | { | |
14869 | if (!(rex & REX_W)) | |
14870 | { | |
14871 | if (sizeflag & DFLAG) | |
14872 | op &= 0xffffffff; | |
14873 | else | |
14874 | op &= 0xffff; | |
14875 | } | |
14876 | } | |
252b5132 RH |
14877 | break; |
14878 | case v_mode: | |
7bb15c6f RM |
14879 | /* The operand-size prefix is overridden by a REX prefix. */ |
14880 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14881 | op = get32s (); |
252b5132 | 14882 | else |
d9e3625e | 14883 | op = get16 (); |
252b5132 RH |
14884 | break; |
14885 | default: | |
14886 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14887 | return; | |
14888 | } | |
52b15da3 JH |
14889 | |
14890 | scratchbuf[0] = '$'; | |
14891 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14892 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14893 | } |
14894 | ||
14895 | static void | |
26ca5450 | 14896 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14897 | { |
52b15da3 | 14898 | bfd_vma disp; |
7081ff04 | 14899 | bfd_vma mask = -1; |
65ca155d | 14900 | bfd_vma segment = 0; |
252b5132 RH |
14901 | |
14902 | switch (bytemode) | |
14903 | { | |
14904 | case b_mode: | |
14905 | FETCH_DATA (the_info, codep + 1); | |
14906 | disp = *codep++; | |
14907 | if ((disp & 0x80) != 0) | |
14908 | disp -= 0x100; | |
14909 | break; | |
14910 | case v_mode: | |
d835a58b | 14911 | if (isa64 != intel64) |
376cd056 | 14912 | case dqw_mode: |
5db04b09 L |
14913 | USED_REX (REX_W); |
14914 | if ((sizeflag & DFLAG) | |
14915 | || (address_mode == mode_64bit | |
d835a58b | 14916 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14917 | || (rex & REX_W)))) |
52b15da3 | 14918 | disp = get32s (); |
252b5132 RH |
14919 | else |
14920 | { | |
14921 | disp = get16 (); | |
206717e8 L |
14922 | if ((disp & 0x8000) != 0) |
14923 | disp -= 0x10000; | |
65ca155d L |
14924 | /* In 16bit mode, address is wrapped around at 64k within |
14925 | the same segment. Otherwise, a data16 prefix on a jump | |
14926 | instruction means that the pc is masked to 16 bits after | |
14927 | the displacement is added! */ | |
14928 | mask = 0xffff; | |
14929 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14930 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14931 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14932 | } |
5db04b09 | 14933 | if (address_mode != mode_64bit |
d835a58b | 14934 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14935 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14936 | break; |
14937 | default: | |
14938 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14939 | return; | |
14940 | } | |
42d5f9c6 | 14941 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14942 | set_op (disp, 0); |
14943 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14944 | oappend (scratchbuf); |
14945 | } | |
14946 | ||
252b5132 | 14947 | static void |
ed7841b3 | 14948 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14949 | { |
ed7841b3 | 14950 | if (bytemode == w_mode) |
7967e09e | 14951 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14952 | else |
7967e09e | 14953 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14954 | } |
14955 | ||
14956 | static void | |
26ca5450 | 14957 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14958 | { |
14959 | int seg, offset; | |
14960 | ||
c608c12e | 14961 | if (sizeflag & DFLAG) |
252b5132 | 14962 | { |
c608c12e AM |
14963 | offset = get32 (); |
14964 | seg = get16 (); | |
252b5132 | 14965 | } |
c608c12e AM |
14966 | else |
14967 | { | |
14968 | offset = get16 (); | |
14969 | seg = get16 (); | |
14970 | } | |
7d421014 | 14971 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14972 | if (intel_syntax) |
3f31e633 | 14973 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14974 | else |
14975 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14976 | oappend (scratchbuf); |
252b5132 RH |
14977 | } |
14978 | ||
252b5132 | 14979 | static void |
3f31e633 | 14980 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14981 | { |
52b15da3 | 14982 | bfd_vma off; |
252b5132 | 14983 | |
3f31e633 JB |
14984 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14985 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14986 | append_seg (); |
14987 | ||
cb712a9e | 14988 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14989 | off = get32 (); |
14990 | else | |
14991 | off = get16 (); | |
14992 | ||
14993 | if (intel_syntax) | |
14994 | { | |
285ca992 | 14995 | if (!active_seg_prefix) |
252b5132 | 14996 | { |
d708bcba | 14997 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14998 | oappend (":"); |
14999 | } | |
15000 | } | |
52b15da3 JH |
15001 | print_operand_value (scratchbuf, 1, off); |
15002 | oappend (scratchbuf); | |
15003 | } | |
6439fc28 | 15004 | |
52b15da3 | 15005 | static void |
3f31e633 | 15006 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15007 | { |
15008 | bfd_vma off; | |
15009 | ||
539e75ad L |
15010 | if (address_mode != mode_64bit |
15011 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15012 | { |
15013 | OP_OFF (bytemode, sizeflag); | |
15014 | return; | |
15015 | } | |
15016 | ||
3f31e633 JB |
15017 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15018 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15019 | append_seg (); |
15020 | ||
6608db57 | 15021 | off = get64 (); |
52b15da3 JH |
15022 | |
15023 | if (intel_syntax) | |
15024 | { | |
285ca992 | 15025 | if (!active_seg_prefix) |
52b15da3 | 15026 | { |
d708bcba | 15027 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15028 | oappend (":"); |
15029 | } | |
15030 | } | |
15031 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15032 | oappend (scratchbuf); |
15033 | } | |
15034 | ||
15035 | static void | |
26ca5450 | 15036 | ptr_reg (int code, int sizeflag) |
252b5132 | 15037 | { |
2da11e11 | 15038 | const char *s; |
d708bcba | 15039 | |
1d9f512f | 15040 | *obufp++ = open_char; |
20f0a1fc | 15041 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15042 | if (address_mode == mode_64bit) |
c1a64871 JH |
15043 | { |
15044 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15045 | s = names32[code - eAX_reg]; |
c1a64871 | 15046 | else |
db6eb5be | 15047 | s = names64[code - eAX_reg]; |
c1a64871 | 15048 | } |
52b15da3 | 15049 | else if (sizeflag & AFLAG) |
252b5132 RH |
15050 | s = names32[code - eAX_reg]; |
15051 | else | |
15052 | s = names16[code - eAX_reg]; | |
15053 | oappend (s); | |
1d9f512f AM |
15054 | *obufp++ = close_char; |
15055 | *obufp = 0; | |
252b5132 RH |
15056 | } |
15057 | ||
15058 | static void | |
26ca5450 | 15059 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15060 | { |
9306ca4a | 15061 | if (intel_syntax) |
52fd6d94 JB |
15062 | { |
15063 | switch (codep[-1]) | |
15064 | { | |
15065 | case 0x6d: /* insw/insl */ | |
15066 | intel_operand_size (z_mode, sizeflag); | |
15067 | break; | |
15068 | case 0xa5: /* movsw/movsl/movsq */ | |
15069 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15070 | case 0xab: /* stosw/stosl */ | |
15071 | case 0xaf: /* scasw/scasl */ | |
15072 | intel_operand_size (v_mode, sizeflag); | |
15073 | break; | |
15074 | default: | |
15075 | intel_operand_size (b_mode, sizeflag); | |
15076 | } | |
15077 | } | |
9ce09ba2 | 15078 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15079 | ptr_reg (code, sizeflag); |
15080 | } | |
15081 | ||
15082 | static void | |
26ca5450 | 15083 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15084 | { |
9306ca4a | 15085 | if (intel_syntax) |
52fd6d94 JB |
15086 | { |
15087 | switch (codep[-1]) | |
15088 | { | |
15089 | case 0x6f: /* outsw/outsl */ | |
15090 | intel_operand_size (z_mode, sizeflag); | |
15091 | break; | |
15092 | case 0xa5: /* movsw/movsl/movsq */ | |
15093 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15094 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15095 | intel_operand_size (v_mode, sizeflag); | |
15096 | break; | |
15097 | default: | |
15098 | intel_operand_size (b_mode, sizeflag); | |
15099 | } | |
15100 | } | |
285ca992 L |
15101 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15102 | default segment register DS is printed. */ | |
15103 | if (!active_seg_prefix) | |
15104 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15105 | append_seg (); |
252b5132 RH |
15106 | ptr_reg (code, sizeflag); |
15107 | } | |
15108 | ||
252b5132 | 15109 | static void |
26ca5450 | 15110 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15111 | { |
9b60702d | 15112 | int add; |
161a04f6 | 15113 | if (rex & REX_R) |
c4a530c5 | 15114 | { |
161a04f6 | 15115 | USED_REX (REX_R); |
c4a530c5 JB |
15116 | add = 8; |
15117 | } | |
cb712a9e | 15118 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15119 | { |
f16cd0d5 | 15120 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15121 | used_prefixes |= PREFIX_LOCK; |
15122 | add = 8; | |
15123 | } | |
9b60702d L |
15124 | else |
15125 | add = 0; | |
7967e09e | 15126 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15127 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15128 | } |
15129 | ||
252b5132 | 15130 | static void |
26ca5450 | 15131 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15132 | { |
9b60702d | 15133 | int add; |
161a04f6 L |
15134 | USED_REX (REX_R); |
15135 | if (rex & REX_R) | |
52b15da3 | 15136 | add = 8; |
9b60702d L |
15137 | else |
15138 | add = 0; | |
d708bcba | 15139 | if (intel_syntax) |
7967e09e | 15140 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15141 | else |
7967e09e | 15142 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15143 | oappend (scratchbuf); |
15144 | } | |
15145 | ||
252b5132 | 15146 | static void |
26ca5450 | 15147 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15148 | { |
7967e09e | 15149 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15150 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15151 | } |
15152 | ||
15153 | static void | |
6f74c397 | 15154 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15155 | { |
68f34464 L |
15156 | /* Skip mod/rm byte. */ |
15157 | MODRM_CHECK; | |
15158 | codep++; | |
15159 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15160 | } |
15161 | ||
15162 | static void | |
26ca5450 | 15163 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15164 | { |
b9733481 L |
15165 | int reg = modrm.reg; |
15166 | const char **names; | |
15167 | ||
041bd2e0 JH |
15168 | used_prefixes |= (prefixes & PREFIX_DATA); |
15169 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15170 | { |
b9733481 | 15171 | names = names_xmm; |
161a04f6 L |
15172 | USED_REX (REX_R); |
15173 | if (rex & REX_R) | |
b9733481 | 15174 | reg += 8; |
20f0a1fc | 15175 | } |
041bd2e0 | 15176 | else |
b9733481 L |
15177 | names = names_mm; |
15178 | oappend (names[reg]); | |
252b5132 RH |
15179 | } |
15180 | ||
c608c12e | 15181 | static void |
c0f3af97 | 15182 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15183 | { |
b9733481 L |
15184 | int reg = modrm.reg; |
15185 | const char **names; | |
15186 | ||
161a04f6 L |
15187 | USED_REX (REX_R); |
15188 | if (rex & REX_R) | |
b9733481 | 15189 | reg += 8; |
43234a1e L |
15190 | if (vex.evex) |
15191 | { | |
15192 | if (!vex.r) | |
15193 | reg += 16; | |
15194 | } | |
15195 | ||
539f890d L |
15196 | if (need_vex |
15197 | && bytemode != xmm_mode | |
43234a1e L |
15198 | && bytemode != xmmq_mode |
15199 | && bytemode != evex_half_bcst_xmmq_mode | |
15200 | && bytemode != ymm_mode | |
539f890d | 15201 | && bytemode != scalar_mode) |
c0f3af97 L |
15202 | { |
15203 | switch (vex.length) | |
15204 | { | |
15205 | case 128: | |
b9733481 | 15206 | names = names_xmm; |
c0f3af97 L |
15207 | break; |
15208 | case 256: | |
5fc35d96 IT |
15209 | if (vex.w |
15210 | || (bytemode != vex_vsib_q_w_dq_mode | |
15211 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15212 | names = names_ymm; |
15213 | else | |
15214 | names = names_xmm; | |
c0f3af97 | 15215 | break; |
43234a1e L |
15216 | case 512: |
15217 | names = names_zmm; | |
15218 | break; | |
c0f3af97 L |
15219 | default: |
15220 | abort (); | |
15221 | } | |
15222 | } | |
43234a1e L |
15223 | else if (bytemode == xmmq_mode |
15224 | || bytemode == evex_half_bcst_xmmq_mode) | |
15225 | { | |
15226 | switch (vex.length) | |
15227 | { | |
15228 | case 128: | |
15229 | case 256: | |
15230 | names = names_xmm; | |
15231 | break; | |
15232 | case 512: | |
15233 | names = names_ymm; | |
15234 | break; | |
15235 | default: | |
15236 | abort (); | |
15237 | } | |
15238 | } | |
15239 | else if (bytemode == ymm_mode) | |
15240 | names = names_ymm; | |
c0f3af97 | 15241 | else |
b9733481 L |
15242 | names = names_xmm; |
15243 | oappend (names[reg]); | |
c608c12e AM |
15244 | } |
15245 | ||
252b5132 | 15246 | static void |
26ca5450 | 15247 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15248 | { |
b9733481 L |
15249 | int reg; |
15250 | const char **names; | |
15251 | ||
7967e09e | 15252 | if (modrm.mod != 3) |
252b5132 | 15253 | { |
b6169b20 L |
15254 | if (intel_syntax |
15255 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15256 | { |
15257 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15258 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15259 | } |
252b5132 RH |
15260 | OP_E (bytemode, sizeflag); |
15261 | return; | |
15262 | } | |
15263 | ||
b6169b20 L |
15264 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15265 | swap_operand (); | |
15266 | ||
6608db57 | 15267 | /* Skip mod/rm byte. */ |
4bba6815 | 15268 | MODRM_CHECK; |
252b5132 | 15269 | codep++; |
041bd2e0 | 15270 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15271 | reg = modrm.rm; |
041bd2e0 | 15272 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15273 | { |
b9733481 | 15274 | names = names_xmm; |
161a04f6 L |
15275 | USED_REX (REX_B); |
15276 | if (rex & REX_B) | |
b9733481 | 15277 | reg += 8; |
20f0a1fc | 15278 | } |
041bd2e0 | 15279 | else |
b9733481 L |
15280 | names = names_mm; |
15281 | oappend (names[reg]); | |
252b5132 RH |
15282 | } |
15283 | ||
246c51aa L |
15284 | /* cvt* are the only instructions in sse2 which have |
15285 | both SSE and MMX operands and also have 0x66 prefix | |
15286 | in their opcode. 0x66 was originally used to differentiate | |
15287 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15288 | cvt* separately using OP_EMC and OP_MXC */ |
15289 | static void | |
15290 | OP_EMC (int bytemode, int sizeflag) | |
15291 | { | |
7967e09e | 15292 | if (modrm.mod != 3) |
4d9567e0 MM |
15293 | { |
15294 | if (intel_syntax && bytemode == v_mode) | |
15295 | { | |
15296 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15297 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15298 | } |
4d9567e0 MM |
15299 | OP_E (bytemode, sizeflag); |
15300 | return; | |
15301 | } | |
246c51aa | 15302 | |
4d9567e0 MM |
15303 | /* Skip mod/rm byte. */ |
15304 | MODRM_CHECK; | |
15305 | codep++; | |
15306 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15307 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15308 | } |
15309 | ||
15310 | static void | |
15311 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15312 | { | |
15313 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15314 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15315 | } |
15316 | ||
c608c12e | 15317 | static void |
26ca5450 | 15318 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15319 | { |
b9733481 L |
15320 | int reg; |
15321 | const char **names; | |
d6f574e0 L |
15322 | |
15323 | /* Skip mod/rm byte. */ | |
15324 | MODRM_CHECK; | |
15325 | codep++; | |
15326 | ||
7967e09e | 15327 | if (modrm.mod != 3) |
c608c12e | 15328 | { |
c1e679ec | 15329 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15330 | return; |
15331 | } | |
d6f574e0 | 15332 | |
b9733481 | 15333 | reg = modrm.rm; |
161a04f6 L |
15334 | USED_REX (REX_B); |
15335 | if (rex & REX_B) | |
b9733481 | 15336 | reg += 8; |
43234a1e L |
15337 | if (vex.evex) |
15338 | { | |
15339 | USED_REX (REX_X); | |
15340 | if ((rex & REX_X)) | |
15341 | reg += 16; | |
15342 | } | |
c608c12e | 15343 | |
b6169b20 | 15344 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15345 | && (bytemode == x_swap_mode |
15346 | || bytemode == d_swap_mode | |
7bb15c6f | 15347 | || bytemode == d_scalar_swap_mode |
539f890d L |
15348 | || bytemode == q_swap_mode |
15349 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15350 | swap_operand (); |
15351 | ||
c0f3af97 L |
15352 | if (need_vex |
15353 | && bytemode != xmm_mode | |
6c30d220 L |
15354 | && bytemode != xmmdw_mode |
15355 | && bytemode != xmmqd_mode | |
15356 | && bytemode != xmm_mb_mode | |
15357 | && bytemode != xmm_mw_mode | |
15358 | && bytemode != xmm_md_mode | |
15359 | && bytemode != xmm_mq_mode | |
43234a1e | 15360 | && bytemode != xmm_mdq_mode |
539f890d | 15361 | && bytemode != xmmq_mode |
43234a1e L |
15362 | && bytemode != evex_half_bcst_xmmq_mode |
15363 | && bytemode != ymm_mode | |
539f890d | 15364 | && bytemode != d_scalar_mode |
7bb15c6f | 15365 | && bytemode != d_scalar_swap_mode |
539f890d | 15366 | && bytemode != q_scalar_mode |
1c480963 L |
15367 | && bytemode != q_scalar_swap_mode |
15368 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15369 | { |
15370 | switch (vex.length) | |
15371 | { | |
15372 | case 128: | |
b9733481 | 15373 | names = names_xmm; |
c0f3af97 L |
15374 | break; |
15375 | case 256: | |
b9733481 | 15376 | names = names_ymm; |
c0f3af97 | 15377 | break; |
43234a1e L |
15378 | case 512: |
15379 | names = names_zmm; | |
15380 | break; | |
c0f3af97 L |
15381 | default: |
15382 | abort (); | |
15383 | } | |
15384 | } | |
43234a1e L |
15385 | else if (bytemode == xmmq_mode |
15386 | || bytemode == evex_half_bcst_xmmq_mode) | |
15387 | { | |
15388 | switch (vex.length) | |
15389 | { | |
15390 | case 128: | |
15391 | case 256: | |
15392 | names = names_xmm; | |
15393 | break; | |
15394 | case 512: | |
15395 | names = names_ymm; | |
15396 | break; | |
15397 | default: | |
15398 | abort (); | |
15399 | } | |
15400 | } | |
15401 | else if (bytemode == ymm_mode) | |
15402 | names = names_ymm; | |
c0f3af97 | 15403 | else |
b9733481 L |
15404 | names = names_xmm; |
15405 | oappend (names[reg]); | |
c608c12e AM |
15406 | } |
15407 | ||
252b5132 | 15408 | static void |
26ca5450 | 15409 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15410 | { |
7967e09e | 15411 | if (modrm.mod == 3) |
2da11e11 AM |
15412 | OP_EM (bytemode, sizeflag); |
15413 | else | |
6608db57 | 15414 | BadOp (); |
252b5132 RH |
15415 | } |
15416 | ||
992aaec9 | 15417 | static void |
26ca5450 | 15418 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15419 | { |
7967e09e | 15420 | if (modrm.mod == 3) |
992aaec9 AM |
15421 | OP_EX (bytemode, sizeflag); |
15422 | else | |
6608db57 | 15423 | BadOp (); |
992aaec9 AM |
15424 | } |
15425 | ||
cc0ec051 AM |
15426 | static void |
15427 | OP_M (int bytemode, int sizeflag) | |
15428 | { | |
7967e09e | 15429 | if (modrm.mod == 3) |
75413a22 L |
15430 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15431 | BadOp (); | |
cc0ec051 AM |
15432 | else |
15433 | OP_E (bytemode, sizeflag); | |
15434 | } | |
15435 | ||
15436 | static void | |
15437 | OP_0f07 (int bytemode, int sizeflag) | |
15438 | { | |
7967e09e | 15439 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15440 | BadOp (); |
15441 | else | |
15442 | OP_E (bytemode, sizeflag); | |
15443 | } | |
15444 | ||
46e883c5 | 15445 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15446 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15447 | |
cc0ec051 | 15448 | static void |
46e883c5 | 15449 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15450 | { |
8b38ad71 L |
15451 | if ((prefixes & PREFIX_DATA) != 0 |
15452 | || (rex != 0 | |
15453 | && rex != 0x48 | |
15454 | && address_mode == mode_64bit)) | |
46e883c5 L |
15455 | OP_REG (bytemode, sizeflag); |
15456 | else | |
15457 | strcpy (obuf, "nop"); | |
15458 | } | |
15459 | ||
15460 | static void | |
15461 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15462 | { | |
8b38ad71 L |
15463 | if ((prefixes & PREFIX_DATA) != 0 |
15464 | || (rex != 0 | |
15465 | && rex != 0x48 | |
15466 | && address_mode == mode_64bit)) | |
46e883c5 | 15467 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15468 | } |
15469 | ||
84037f8c | 15470 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15471 | /* 00 */ NULL, NULL, NULL, NULL, |
15472 | /* 04 */ NULL, NULL, NULL, NULL, | |
15473 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15474 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15475 | /* 10 */ NULL, NULL, NULL, NULL, |
15476 | /* 14 */ NULL, NULL, NULL, NULL, | |
15477 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15478 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15479 | /* 20 */ NULL, NULL, NULL, NULL, |
15480 | /* 24 */ NULL, NULL, NULL, NULL, | |
15481 | /* 28 */ NULL, NULL, NULL, NULL, | |
15482 | /* 2C */ NULL, NULL, NULL, NULL, | |
15483 | /* 30 */ NULL, NULL, NULL, NULL, | |
15484 | /* 34 */ NULL, NULL, NULL, NULL, | |
15485 | /* 38 */ NULL, NULL, NULL, NULL, | |
15486 | /* 3C */ NULL, NULL, NULL, NULL, | |
15487 | /* 40 */ NULL, NULL, NULL, NULL, | |
15488 | /* 44 */ NULL, NULL, NULL, NULL, | |
15489 | /* 48 */ NULL, NULL, NULL, NULL, | |
15490 | /* 4C */ NULL, NULL, NULL, NULL, | |
15491 | /* 50 */ NULL, NULL, NULL, NULL, | |
15492 | /* 54 */ NULL, NULL, NULL, NULL, | |
15493 | /* 58 */ NULL, NULL, NULL, NULL, | |
15494 | /* 5C */ NULL, NULL, NULL, NULL, | |
15495 | /* 60 */ NULL, NULL, NULL, NULL, | |
15496 | /* 64 */ NULL, NULL, NULL, NULL, | |
15497 | /* 68 */ NULL, NULL, NULL, NULL, | |
15498 | /* 6C */ NULL, NULL, NULL, NULL, | |
15499 | /* 70 */ NULL, NULL, NULL, NULL, | |
15500 | /* 74 */ NULL, NULL, NULL, NULL, | |
15501 | /* 78 */ NULL, NULL, NULL, NULL, | |
15502 | /* 7C */ NULL, NULL, NULL, NULL, | |
15503 | /* 80 */ NULL, NULL, NULL, NULL, | |
15504 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15505 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15506 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15507 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15508 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15509 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15510 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15511 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15512 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15513 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15514 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15515 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15516 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15517 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15518 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15519 | /* C0 */ NULL, NULL, NULL, NULL, | |
15520 | /* C4 */ NULL, NULL, NULL, NULL, | |
15521 | /* C8 */ NULL, NULL, NULL, NULL, | |
15522 | /* CC */ NULL, NULL, NULL, NULL, | |
15523 | /* D0 */ NULL, NULL, NULL, NULL, | |
15524 | /* D4 */ NULL, NULL, NULL, NULL, | |
15525 | /* D8 */ NULL, NULL, NULL, NULL, | |
15526 | /* DC */ NULL, NULL, NULL, NULL, | |
15527 | /* E0 */ NULL, NULL, NULL, NULL, | |
15528 | /* E4 */ NULL, NULL, NULL, NULL, | |
15529 | /* E8 */ NULL, NULL, NULL, NULL, | |
15530 | /* EC */ NULL, NULL, NULL, NULL, | |
15531 | /* F0 */ NULL, NULL, NULL, NULL, | |
15532 | /* F4 */ NULL, NULL, NULL, NULL, | |
15533 | /* F8 */ NULL, NULL, NULL, NULL, | |
15534 | /* FC */ NULL, NULL, NULL, NULL, | |
15535 | }; | |
15536 | ||
15537 | static void | |
26ca5450 | 15538 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15539 | { |
15540 | const char *mnemonic; | |
15541 | ||
15542 | FETCH_DATA (the_info, codep + 1); | |
15543 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15544 | place where an 8-bit immediate would normally go. ie. the last | |
15545 | byte of the instruction. */ | |
ea397f5b | 15546 | obufp = mnemonicendp; |
c608c12e | 15547 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15548 | if (mnemonic) |
2da11e11 | 15549 | oappend (mnemonic); |
252b5132 RH |
15550 | else |
15551 | { | |
15552 | /* Since a variable sized modrm/sib chunk is between the start | |
15553 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15554 | all the modrm processing first, and don't know until now that | |
15555 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15556 | op_out[0][0] = '\0'; |
15557 | op_out[1][0] = '\0'; | |
6608db57 | 15558 | BadOp (); |
252b5132 | 15559 | } |
ea397f5b | 15560 | mnemonicendp = obufp; |
252b5132 | 15561 | } |
c608c12e | 15562 | |
ea397f5b L |
15563 | static struct op simd_cmp_op[] = |
15564 | { | |
15565 | { STRING_COMMA_LEN ("eq") }, | |
15566 | { STRING_COMMA_LEN ("lt") }, | |
15567 | { STRING_COMMA_LEN ("le") }, | |
15568 | { STRING_COMMA_LEN ("unord") }, | |
15569 | { STRING_COMMA_LEN ("neq") }, | |
15570 | { STRING_COMMA_LEN ("nlt") }, | |
15571 | { STRING_COMMA_LEN ("nle") }, | |
15572 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15573 | }; |
15574 | ||
15575 | static void | |
ad19981d | 15576 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15577 | { |
15578 | unsigned int cmp_type; | |
15579 | ||
15580 | FETCH_DATA (the_info, codep + 1); | |
15581 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15582 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15583 | { |
ad19981d | 15584 | char suffix [3]; |
ea397f5b | 15585 | char *p = mnemonicendp - 2; |
ad19981d L |
15586 | suffix[0] = p[0]; |
15587 | suffix[1] = p[1]; | |
15588 | suffix[2] = '\0'; | |
ea397f5b L |
15589 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15590 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15591 | } |
15592 | else | |
15593 | { | |
ad19981d L |
15594 | /* We have a reserved extension byte. Output it directly. */ |
15595 | scratchbuf[0] = '$'; | |
15596 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15597 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15598 | scratchbuf[0] = '\0'; |
c608c12e AM |
15599 | } |
15600 | } | |
15601 | ||
9916071f | 15602 | static void |
7abb8d81 | 15603 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15604 | { |
7abb8d81 | 15605 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15606 | if (!intel_syntax) |
15607 | { | |
081e283f JB |
15608 | strcpy (op_out[0], names32[0]); |
15609 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15610 | if (bytemode == eBX_reg) |
081e283f | 15611 | strcpy (op_out[2], names32[3]); |
b844680a L |
15612 | two_source_ops = 1; |
15613 | } | |
15614 | /* Skip mod/rm byte. */ | |
15615 | MODRM_CHECK; | |
15616 | codep++; | |
15617 | } | |
15618 | ||
15619 | static void | |
15620 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15621 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15622 | { |
081e283f | 15623 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15624 | if (!intel_syntax) |
ca164297 | 15625 | { |
cb712a9e L |
15626 | const char **names = (address_mode == mode_64bit |
15627 | ? names64 : names32); | |
1d9f512f | 15628 | |
081e283f | 15629 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15630 | { |
b844680a | 15631 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15632 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15633 | names = (address_mode != mode_32bit |
15634 | ? names32 : names16); | |
b844680a | 15635 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15636 | } |
081e283f JB |
15637 | else if (address_mode == mode_16bit) |
15638 | names = names16; | |
15639 | strcpy (op_out[0], names[0]); | |
15640 | strcpy (op_out[1], names32[1]); | |
15641 | strcpy (op_out[2], names32[2]); | |
b844680a | 15642 | two_source_ops = 1; |
ca164297 | 15643 | } |
b844680a L |
15644 | /* Skip mod/rm byte. */ |
15645 | MODRM_CHECK; | |
15646 | codep++; | |
30123838 JB |
15647 | } |
15648 | ||
6608db57 KH |
15649 | static void |
15650 | BadOp (void) | |
2da11e11 | 15651 | { |
6608db57 KH |
15652 | /* Throw away prefixes and 1st. opcode byte. */ |
15653 | codep = insn_codep + 1; | |
2da11e11 AM |
15654 | oappend ("(bad)"); |
15655 | } | |
4cc91dba | 15656 | |
35c52694 L |
15657 | static void |
15658 | REP_Fixup (int bytemode, int sizeflag) | |
15659 | { | |
15660 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15661 | lods and stos. */ | |
35c52694 | 15662 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15663 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15664 | |
15665 | switch (bytemode) | |
15666 | { | |
15667 | case al_reg: | |
15668 | case eAX_reg: | |
15669 | case indir_dx_reg: | |
15670 | OP_IMREG (bytemode, sizeflag); | |
15671 | break; | |
15672 | case eDI_reg: | |
15673 | OP_ESreg (bytemode, sizeflag); | |
15674 | break; | |
15675 | case eSI_reg: | |
15676 | OP_DSreg (bytemode, sizeflag); | |
15677 | break; | |
15678 | default: | |
15679 | abort (); | |
15680 | break; | |
15681 | } | |
15682 | } | |
f5804c90 | 15683 | |
d835a58b JB |
15684 | static void |
15685 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15686 | { | |
15687 | if ( isa64 != amd64 ) | |
15688 | return; | |
15689 | ||
15690 | obufp = obuf; | |
15691 | BadOp (); | |
15692 | mnemonicendp = obufp; | |
15693 | ++codep; | |
15694 | } | |
15695 | ||
7e8b059b L |
15696 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15697 | "bnd". */ | |
15698 | ||
15699 | static void | |
15700 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15701 | { | |
15702 | if (prefixes & PREFIX_REPNZ) | |
15703 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15704 | } | |
15705 | ||
04ef582a L |
15706 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15707 | "notrack". */ | |
15708 | ||
15709 | static void | |
15710 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15711 | int sizeflag ATTRIBUTE_UNUSED) | |
15712 | { | |
9fef80d6 | 15713 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15714 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15715 | { | |
4e9ac44a | 15716 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15717 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15718 | active_seg_prefix = 0; |
15719 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15720 | } | |
15721 | } | |
15722 | ||
42164a71 L |
15723 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15724 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15725 | */ | |
15726 | ||
15727 | static void | |
15728 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15729 | { | |
15730 | if (modrm.mod != 3 | |
15731 | && (prefixes & PREFIX_LOCK) != 0) | |
15732 | { | |
15733 | if (prefixes & PREFIX_REPZ) | |
15734 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15735 | if (prefixes & PREFIX_REPNZ) | |
15736 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15737 | } | |
15738 | ||
15739 | OP_E (bytemode, sizeflag); | |
15740 | } | |
15741 | ||
15742 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15743 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15744 | */ | |
15745 | ||
15746 | static void | |
15747 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15748 | { | |
15749 | if (modrm.mod != 3) | |
15750 | { | |
15751 | if (prefixes & PREFIX_REPZ) | |
15752 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15753 | if (prefixes & PREFIX_REPNZ) | |
15754 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15755 | } | |
15756 | ||
15757 | OP_E (bytemode, sizeflag); | |
15758 | } | |
15759 | ||
15760 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15761 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15762 | ||
15763 | static void | |
15764 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15765 | { | |
15766 | if (modrm.mod != 3 | |
15767 | && last_repz_prefix > last_repnz_prefix | |
15768 | && (prefixes & PREFIX_REPZ) != 0) | |
15769 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15770 | ||
15771 | OP_E (bytemode, sizeflag); | |
15772 | } | |
15773 | ||
f5804c90 L |
15774 | static void |
15775 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15776 | { | |
161a04f6 L |
15777 | USED_REX (REX_W); |
15778 | if (rex & REX_W) | |
f5804c90 L |
15779 | { |
15780 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15781 | char *p = mnemonicendp - 2; |
15782 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15783 | bytemode = o_mode; |
f5804c90 | 15784 | } |
42164a71 L |
15785 | else if ((prefixes & PREFIX_LOCK) != 0) |
15786 | { | |
15787 | if (prefixes & PREFIX_REPZ) | |
15788 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15789 | if (prefixes & PREFIX_REPNZ) | |
15790 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15791 | } | |
15792 | ||
f5804c90 L |
15793 | OP_M (bytemode, sizeflag); |
15794 | } | |
42903f7f L |
15795 | |
15796 | static void | |
15797 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15798 | { | |
b9733481 L |
15799 | const char **names; |
15800 | ||
c0f3af97 L |
15801 | if (need_vex) |
15802 | { | |
15803 | switch (vex.length) | |
15804 | { | |
15805 | case 128: | |
b9733481 | 15806 | names = names_xmm; |
c0f3af97 L |
15807 | break; |
15808 | case 256: | |
b9733481 | 15809 | names = names_ymm; |
c0f3af97 L |
15810 | break; |
15811 | default: | |
15812 | abort (); | |
15813 | } | |
15814 | } | |
15815 | else | |
b9733481 L |
15816 | names = names_xmm; |
15817 | oappend (names[reg]); | |
42903f7f | 15818 | } |
381d071f L |
15819 | |
15820 | static void | |
15821 | CRC32_Fixup (int bytemode, int sizeflag) | |
15822 | { | |
15823 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15824 | char *p = mnemonicendp; |
381d071f L |
15825 | |
15826 | switch (bytemode) | |
15827 | { | |
15828 | case b_mode: | |
20592a94 | 15829 | if (intel_syntax) |
ea397f5b | 15830 | goto skip; |
20592a94 | 15831 | |
381d071f L |
15832 | *p++ = 'b'; |
15833 | break; | |
15834 | case v_mode: | |
20592a94 | 15835 | if (intel_syntax) |
ea397f5b | 15836 | goto skip; |
20592a94 | 15837 | |
381d071f L |
15838 | USED_REX (REX_W); |
15839 | if (rex & REX_W) | |
15840 | *p++ = 'q'; | |
7bb15c6f | 15841 | else |
f16cd0d5 L |
15842 | { |
15843 | if (sizeflag & DFLAG) | |
15844 | *p++ = 'l'; | |
15845 | else | |
15846 | *p++ = 'w'; | |
15847 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15848 | } | |
381d071f L |
15849 | break; |
15850 | default: | |
15851 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15852 | break; | |
15853 | } | |
ea397f5b | 15854 | mnemonicendp = p; |
381d071f L |
15855 | *p = '\0'; |
15856 | ||
ea397f5b | 15857 | skip: |
381d071f L |
15858 | if (modrm.mod == 3) |
15859 | { | |
15860 | int add; | |
15861 | ||
15862 | /* Skip mod/rm byte. */ | |
15863 | MODRM_CHECK; | |
15864 | codep++; | |
15865 | ||
15866 | USED_REX (REX_B); | |
15867 | add = (rex & REX_B) ? 8 : 0; | |
15868 | if (bytemode == b_mode) | |
15869 | { | |
15870 | USED_REX (0); | |
15871 | if (rex) | |
15872 | oappend (names8rex[modrm.rm + add]); | |
15873 | else | |
15874 | oappend (names8[modrm.rm + add]); | |
15875 | } | |
15876 | else | |
15877 | { | |
15878 | USED_REX (REX_W); | |
15879 | if (rex & REX_W) | |
15880 | oappend (names64[modrm.rm + add]); | |
15881 | else if ((prefixes & PREFIX_DATA)) | |
15882 | oappend (names16[modrm.rm + add]); | |
15883 | else | |
15884 | oappend (names32[modrm.rm + add]); | |
15885 | } | |
15886 | } | |
15887 | else | |
9344ff29 | 15888 | OP_E (bytemode, sizeflag); |
381d071f | 15889 | } |
85f10a01 | 15890 | |
eacc9c89 L |
15891 | static void |
15892 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15893 | { | |
15894 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15895 | USED_REX (REX_W); | |
15896 | if (rex & REX_W) | |
15897 | { | |
15898 | char *p = mnemonicendp; | |
15899 | *p++ = '6'; | |
15900 | *p++ = '4'; | |
15901 | *p = '\0'; | |
15902 | mnemonicendp = p; | |
15903 | } | |
15904 | OP_M (bytemode, sizeflag); | |
15905 | } | |
15906 | ||
15c7c1d8 JB |
15907 | static void |
15908 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15909 | { | |
15910 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15911 | if (!intel_syntax) | |
15912 | { | |
15913 | char *p = mnemonicendp; | |
15914 | ||
15915 | USED_REX (REX_W); | |
15916 | if (rex & REX_W) | |
15917 | *p++ = 'q'; | |
15918 | else if (sizeflag & SUFFIX_ALWAYS) | |
15919 | *p++ = 'l'; | |
15920 | ||
15921 | *p = '\0'; | |
15922 | mnemonicendp = p; | |
15923 | } | |
15924 | ||
15925 | OP_EX (bytemode, sizeflag); | |
15926 | } | |
15927 | ||
c0f3af97 L |
15928 | /* Display the destination register operand for instructions with |
15929 | VEX. */ | |
15930 | ||
15931 | static void | |
15932 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15933 | { | |
539f890d | 15934 | int reg; |
b9733481 L |
15935 | const char **names; |
15936 | ||
c0f3af97 L |
15937 | if (!need_vex) |
15938 | abort (); | |
15939 | ||
15940 | if (!need_vex_reg) | |
15941 | return; | |
15942 | ||
539f890d | 15943 | reg = vex.register_specifier; |
63c6fc6c | 15944 | vex.register_specifier = 0; |
5f847646 JB |
15945 | if (address_mode != mode_64bit) |
15946 | reg &= 7; | |
15947 | else if (vex.evex && !vex.v) | |
15948 | reg += 16; | |
43234a1e | 15949 | |
539f890d L |
15950 | if (bytemode == vex_scalar_mode) |
15951 | { | |
15952 | oappend (names_xmm[reg]); | |
15953 | return; | |
15954 | } | |
15955 | ||
c0f3af97 L |
15956 | switch (vex.length) |
15957 | { | |
15958 | case 128: | |
15959 | switch (bytemode) | |
15960 | { | |
15961 | case vex_mode: | |
15962 | case vex128_mode: | |
6c30d220 | 15963 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15964 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15965 | names = names_xmm; |
15966 | break; | |
15967 | case dq_mode: | |
390a6789 | 15968 | if (rex & REX_W) |
cb21baef L |
15969 | names = names64; |
15970 | else | |
15971 | names = names32; | |
c0f3af97 | 15972 | break; |
1ba585e8 | 15973 | case mask_bd_mode: |
43234a1e | 15974 | case mask_mode: |
9889cbb1 L |
15975 | if (reg > 0x7) |
15976 | { | |
15977 | oappend ("(bad)"); | |
15978 | return; | |
15979 | } | |
43234a1e L |
15980 | names = names_mask; |
15981 | break; | |
c0f3af97 L |
15982 | default: |
15983 | abort (); | |
15984 | return; | |
15985 | } | |
c0f3af97 L |
15986 | break; |
15987 | case 256: | |
15988 | switch (bytemode) | |
15989 | { | |
15990 | case vex_mode: | |
15991 | case vex256_mode: | |
6c30d220 L |
15992 | names = names_ymm; |
15993 | break; | |
15994 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15995 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15996 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15997 | break; |
1ba585e8 | 15998 | case mask_bd_mode: |
43234a1e | 15999 | case mask_mode: |
9889cbb1 L |
16000 | if (reg > 0x7) |
16001 | { | |
16002 | oappend ("(bad)"); | |
16003 | return; | |
16004 | } | |
43234a1e L |
16005 | names = names_mask; |
16006 | break; | |
c0f3af97 | 16007 | default: |
a37a2806 NC |
16008 | /* See PR binutils/20893 for a reproducer. */ |
16009 | oappend ("(bad)"); | |
c0f3af97 L |
16010 | return; |
16011 | } | |
c0f3af97 | 16012 | break; |
43234a1e L |
16013 | case 512: |
16014 | names = names_zmm; | |
16015 | break; | |
c0f3af97 L |
16016 | default: |
16017 | abort (); | |
16018 | break; | |
16019 | } | |
539f890d | 16020 | oappend (names[reg]); |
c0f3af97 L |
16021 | } |
16022 | ||
922d8de8 DR |
16023 | /* Get the VEX immediate byte without moving codep. */ |
16024 | ||
16025 | static unsigned char | |
ccc5981b | 16026 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16027 | { |
16028 | int bytes_before_imm = 0; | |
16029 | ||
922d8de8 DR |
16030 | if (modrm.mod != 3) |
16031 | { | |
16032 | /* There are SIB/displacement bytes. */ | |
16033 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16034 | { |
922d8de8 | 16035 | /* 32/64 bit address mode */ |
6c067bbb | 16036 | int base = modrm.rm; |
922d8de8 DR |
16037 | |
16038 | /* Check SIB byte. */ | |
6c067bbb RM |
16039 | if (base == 4) |
16040 | { | |
16041 | FETCH_DATA (the_info, codep + 1); | |
16042 | base = *codep & 7; | |
16043 | /* When decoding the third source, don't increase | |
16044 | bytes_before_imm as this has already been incremented | |
16045 | by one in OP_E_memory while decoding the second | |
16046 | source operand. */ | |
16047 | if (opnum == 0) | |
16048 | bytes_before_imm++; | |
16049 | } | |
16050 | ||
16051 | /* Don't increase bytes_before_imm when decoding the third source, | |
16052 | it has already been incremented by OP_E_memory while decoding | |
16053 | the second source operand. */ | |
16054 | if (opnum == 0) | |
16055 | { | |
16056 | switch (modrm.mod) | |
16057 | { | |
16058 | case 0: | |
16059 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16060 | SIB == 5, there is a 4 byte displacement. */ | |
16061 | if (base != 5) | |
16062 | /* No displacement. */ | |
16063 | break; | |
1a0670f3 | 16064 | /* Fall through. */ |
6c067bbb RM |
16065 | case 2: |
16066 | /* 4 byte displacement. */ | |
16067 | bytes_before_imm += 4; | |
16068 | break; | |
16069 | case 1: | |
16070 | /* 1 byte displacement. */ | |
16071 | bytes_before_imm++; | |
16072 | break; | |
16073 | } | |
16074 | } | |
16075 | } | |
922d8de8 | 16076 | else |
02e647f9 SP |
16077 | { |
16078 | /* 16 bit address mode */ | |
6c067bbb RM |
16079 | /* Don't increase bytes_before_imm when decoding the third source, |
16080 | it has already been incremented by OP_E_memory while decoding | |
16081 | the second source operand. */ | |
16082 | if (opnum == 0) | |
16083 | { | |
02e647f9 SP |
16084 | switch (modrm.mod) |
16085 | { | |
16086 | case 0: | |
16087 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16088 | if (modrm.rm != 6) | |
16089 | /* No displacement. */ | |
16090 | break; | |
1a0670f3 | 16091 | /* Fall through. */ |
02e647f9 SP |
16092 | case 2: |
16093 | /* 2 byte displacement. */ | |
16094 | bytes_before_imm += 2; | |
16095 | break; | |
16096 | case 1: | |
16097 | /* 1 byte displacement: when decoding the third source, | |
16098 | don't increase bytes_before_imm as this has already | |
16099 | been incremented by one in OP_E_memory while decoding | |
16100 | the second source operand. */ | |
16101 | if (opnum == 0) | |
16102 | bytes_before_imm++; | |
ccc5981b | 16103 | |
02e647f9 SP |
16104 | break; |
16105 | } | |
922d8de8 DR |
16106 | } |
16107 | } | |
16108 | } | |
16109 | ||
16110 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16111 | return codep [bytes_before_imm]; | |
16112 | } | |
16113 | ||
16114 | static void | |
16115 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16116 | { | |
b9733481 L |
16117 | const char **names; |
16118 | ||
922d8de8 DR |
16119 | if (reg == -1 && modrm.mod != 3) |
16120 | { | |
16121 | OP_E_memory (bytemode, sizeflag); | |
16122 | return; | |
16123 | } | |
16124 | else | |
16125 | { | |
16126 | if (reg == -1) | |
16127 | { | |
16128 | reg = modrm.rm; | |
16129 | USED_REX (REX_B); | |
16130 | if (rex & REX_B) | |
16131 | reg += 8; | |
16132 | } | |
5f847646 JB |
16133 | if (address_mode != mode_64bit) |
16134 | reg &= 7; | |
922d8de8 DR |
16135 | } |
16136 | ||
16137 | switch (vex.length) | |
16138 | { | |
16139 | case 128: | |
b9733481 | 16140 | names = names_xmm; |
922d8de8 DR |
16141 | break; |
16142 | case 256: | |
b9733481 | 16143 | names = names_ymm; |
922d8de8 DR |
16144 | break; |
16145 | default: | |
16146 | abort (); | |
16147 | } | |
b9733481 | 16148 | oappend (names[reg]); |
922d8de8 DR |
16149 | } |
16150 | ||
a683cc34 SP |
16151 | static void |
16152 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16153 | { | |
16154 | int reg = -1; | |
16155 | static unsigned char vex_imm8; | |
16156 | ||
16157 | if (vex_w_done == 0) | |
16158 | { | |
16159 | vex_w_done = 1; | |
16160 | ||
16161 | /* Skip mod/rm byte. */ | |
16162 | MODRM_CHECK; | |
16163 | codep++; | |
16164 | ||
16165 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16166 | ||
16167 | if (vex.w) | |
16168 | reg = vex_imm8 >> 4; | |
16169 | ||
16170 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16171 | } | |
16172 | else if (vex_w_done == 1) | |
16173 | { | |
16174 | vex_w_done = 2; | |
16175 | ||
16176 | if (!vex.w) | |
16177 | reg = vex_imm8 >> 4; | |
16178 | ||
16179 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16180 | } | |
16181 | else | |
16182 | { | |
16183 | /* Output the imm8 directly. */ | |
16184 | scratchbuf[0] = '$'; | |
16185 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16186 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16187 | scratchbuf[0] = '\0'; |
16188 | codep++; | |
16189 | } | |
16190 | } | |
16191 | ||
5dd85c99 SP |
16192 | static void |
16193 | OP_Vex_2src (int bytemode, int sizeflag) | |
16194 | { | |
16195 | if (modrm.mod == 3) | |
16196 | { | |
b9733481 | 16197 | int reg = modrm.rm; |
5dd85c99 | 16198 | USED_REX (REX_B); |
b9733481 L |
16199 | if (rex & REX_B) |
16200 | reg += 8; | |
16201 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16202 | } |
16203 | else | |
16204 | { | |
16205 | if (intel_syntax | |
16206 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16207 | { | |
16208 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16209 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16210 | } | |
16211 | OP_E (bytemode, sizeflag); | |
16212 | } | |
16213 | } | |
16214 | ||
16215 | static void | |
16216 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16217 | { | |
16218 | if (modrm.mod == 3) | |
16219 | { | |
16220 | /* Skip mod/rm byte. */ | |
16221 | MODRM_CHECK; | |
16222 | codep++; | |
16223 | } | |
16224 | ||
16225 | if (vex.w) | |
5f847646 JB |
16226 | { |
16227 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16228 | vex.register_specifier = 0; |
5f847646 JB |
16229 | |
16230 | if (address_mode != mode_64bit) | |
16231 | reg &= 7; | |
16232 | oappend (names_xmm[reg]); | |
16233 | } | |
5dd85c99 SP |
16234 | else |
16235 | OP_Vex_2src (bytemode, sizeflag); | |
16236 | } | |
16237 | ||
16238 | static void | |
16239 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16240 | { | |
16241 | if (vex.w) | |
16242 | OP_Vex_2src (bytemode, sizeflag); | |
16243 | else | |
5f847646 JB |
16244 | { |
16245 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16246 | vex.register_specifier = 0; |
5f847646 JB |
16247 | |
16248 | if (address_mode != mode_64bit) | |
16249 | reg &= 7; | |
16250 | oappend (names_xmm[reg]); | |
16251 | } | |
5dd85c99 SP |
16252 | } |
16253 | ||
922d8de8 DR |
16254 | static void |
16255 | OP_EX_VexW (int bytemode, int sizeflag) | |
16256 | { | |
16257 | int reg = -1; | |
16258 | ||
16259 | if (!vex_w_done) | |
16260 | { | |
41effecb SP |
16261 | /* Skip mod/rm byte. */ |
16262 | MODRM_CHECK; | |
16263 | codep++; | |
16264 | ||
922d8de8 | 16265 | if (vex.w) |
ccc5981b | 16266 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16267 | } |
16268 | else | |
16269 | { | |
16270 | if (!vex.w) | |
ccc5981b | 16271 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16272 | } |
16273 | ||
16274 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16275 | |
3a2430e0 JB |
16276 | if (vex_w_done) |
16277 | codep++; | |
16278 | vex_w_done = 1; | |
922d8de8 DR |
16279 | } |
16280 | ||
c0f3af97 L |
16281 | static void |
16282 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16283 | { | |
16284 | int reg; | |
b9733481 L |
16285 | const char **names; |
16286 | ||
c0f3af97 L |
16287 | FETCH_DATA (the_info, codep + 1); |
16288 | reg = *codep++; | |
16289 | ||
16290 | if (bytemode != x_mode) | |
16291 | abort (); | |
16292 | ||
c0f3af97 | 16293 | reg >>= 4; |
5f847646 JB |
16294 | if (address_mode != mode_64bit) |
16295 | reg &= 7; | |
dae39acc | 16296 | |
c0f3af97 L |
16297 | switch (vex.length) |
16298 | { | |
16299 | case 128: | |
b9733481 | 16300 | names = names_xmm; |
c0f3af97 L |
16301 | break; |
16302 | case 256: | |
b9733481 | 16303 | names = names_ymm; |
c0f3af97 L |
16304 | break; |
16305 | default: | |
16306 | abort (); | |
16307 | } | |
b9733481 | 16308 | oappend (names[reg]); |
c0f3af97 L |
16309 | } |
16310 | ||
922d8de8 DR |
16311 | static void |
16312 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16313 | { | |
16314 | /* Turn off the REX.W bit since it is used for swapping operands | |
16315 | now. */ | |
16316 | rex &= ~REX_W; | |
16317 | OP_XMM (bytemode, sizeflag); | |
16318 | } | |
16319 | ||
c0f3af97 L |
16320 | static void |
16321 | OP_EX_Vex (int bytemode, int sizeflag) | |
16322 | { | |
16323 | if (modrm.mod != 3) | |
63c6fc6c | 16324 | need_vex_reg = 0; |
c0f3af97 L |
16325 | OP_EX (bytemode, sizeflag); |
16326 | } | |
16327 | ||
16328 | static void | |
16329 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16330 | { | |
16331 | if (modrm.mod != 3) | |
63c6fc6c | 16332 | need_vex_reg = 0; |
c0f3af97 L |
16333 | OP_XMM (bytemode, sizeflag); |
16334 | } | |
16335 | ||
ea397f5b L |
16336 | static struct op vex_cmp_op[] = |
16337 | { | |
16338 | { STRING_COMMA_LEN ("eq") }, | |
16339 | { STRING_COMMA_LEN ("lt") }, | |
16340 | { STRING_COMMA_LEN ("le") }, | |
16341 | { STRING_COMMA_LEN ("unord") }, | |
16342 | { STRING_COMMA_LEN ("neq") }, | |
16343 | { STRING_COMMA_LEN ("nlt") }, | |
16344 | { STRING_COMMA_LEN ("nle") }, | |
16345 | { STRING_COMMA_LEN ("ord") }, | |
16346 | { STRING_COMMA_LEN ("eq_uq") }, | |
16347 | { STRING_COMMA_LEN ("nge") }, | |
16348 | { STRING_COMMA_LEN ("ngt") }, | |
16349 | { STRING_COMMA_LEN ("false") }, | |
16350 | { STRING_COMMA_LEN ("neq_oq") }, | |
16351 | { STRING_COMMA_LEN ("ge") }, | |
16352 | { STRING_COMMA_LEN ("gt") }, | |
16353 | { STRING_COMMA_LEN ("true") }, | |
16354 | { STRING_COMMA_LEN ("eq_os") }, | |
16355 | { STRING_COMMA_LEN ("lt_oq") }, | |
16356 | { STRING_COMMA_LEN ("le_oq") }, | |
16357 | { STRING_COMMA_LEN ("unord_s") }, | |
16358 | { STRING_COMMA_LEN ("neq_us") }, | |
16359 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16360 | { STRING_COMMA_LEN ("nle_uq") }, | |
16361 | { STRING_COMMA_LEN ("ord_s") }, | |
16362 | { STRING_COMMA_LEN ("eq_us") }, | |
16363 | { STRING_COMMA_LEN ("nge_uq") }, | |
16364 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16365 | { STRING_COMMA_LEN ("false_os") }, | |
16366 | { STRING_COMMA_LEN ("neq_os") }, | |
16367 | { STRING_COMMA_LEN ("ge_oq") }, | |
16368 | { STRING_COMMA_LEN ("gt_oq") }, | |
16369 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16370 | }; |
16371 | ||
16372 | static void | |
16373 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16374 | { | |
16375 | unsigned int cmp_type; | |
16376 | ||
16377 | FETCH_DATA (the_info, codep + 1); | |
16378 | cmp_type = *codep++ & 0xff; | |
16379 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16380 | { | |
16381 | char suffix [3]; | |
ea397f5b | 16382 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16383 | suffix[0] = p[0]; |
16384 | suffix[1] = p[1]; | |
16385 | suffix[2] = '\0'; | |
ea397f5b L |
16386 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16387 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16388 | } |
16389 | else | |
16390 | { | |
16391 | /* We have a reserved extension byte. Output it directly. */ | |
16392 | scratchbuf[0] = '$'; | |
16393 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16394 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16395 | scratchbuf[0] = '\0'; |
16396 | } | |
16397 | } | |
16398 | ||
43234a1e L |
16399 | static void |
16400 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16401 | int sizeflag ATTRIBUTE_UNUSED) | |
16402 | { | |
16403 | unsigned int cmp_type; | |
16404 | ||
16405 | if (!vex.evex) | |
16406 | abort (); | |
16407 | ||
16408 | FETCH_DATA (the_info, codep + 1); | |
16409 | cmp_type = *codep++ & 0xff; | |
16410 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16411 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16412 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16413 | && cmp_type != 3 | |
16414 | && cmp_type != 7) | |
16415 | { | |
16416 | char suffix [3]; | |
16417 | char *p = mnemonicendp - 2; | |
16418 | ||
16419 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16420 | if (p[0] == 'p') | |
16421 | { | |
16422 | p++; | |
16423 | suffix[0] = p[0]; | |
16424 | suffix[1] = '\0'; | |
16425 | } | |
16426 | else | |
16427 | { | |
16428 | suffix[0] = p[0]; | |
16429 | suffix[1] = p[1]; | |
16430 | suffix[2] = '\0'; | |
16431 | } | |
16432 | ||
16433 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16434 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16435 | } | |
be92cb14 JB |
16436 | else |
16437 | { | |
16438 | /* We have a reserved extension byte. Output it directly. */ | |
16439 | scratchbuf[0] = '$'; | |
16440 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16441 | oappend_maybe_intel (scratchbuf); | |
16442 | scratchbuf[0] = '\0'; | |
16443 | } | |
16444 | } | |
16445 | ||
16446 | static const struct op xop_cmp_op[] = | |
16447 | { | |
16448 | { STRING_COMMA_LEN ("lt") }, | |
16449 | { STRING_COMMA_LEN ("le") }, | |
16450 | { STRING_COMMA_LEN ("gt") }, | |
16451 | { STRING_COMMA_LEN ("ge") }, | |
16452 | { STRING_COMMA_LEN ("eq") }, | |
16453 | { STRING_COMMA_LEN ("neq") }, | |
16454 | { STRING_COMMA_LEN ("false") }, | |
16455 | { STRING_COMMA_LEN ("true") } | |
16456 | }; | |
16457 | ||
16458 | static void | |
16459 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16460 | int sizeflag ATTRIBUTE_UNUSED) | |
16461 | { | |
16462 | unsigned int cmp_type; | |
16463 | ||
16464 | FETCH_DATA (the_info, codep + 1); | |
16465 | cmp_type = *codep++ & 0xff; | |
16466 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16467 | { | |
16468 | char suffix[3]; | |
16469 | char *p = mnemonicendp - 2; | |
16470 | ||
16471 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16472 | if (p[0] == 'm') | |
16473 | { | |
16474 | p++; | |
16475 | suffix[0] = p[0]; | |
16476 | suffix[1] = '\0'; | |
16477 | } | |
16478 | else | |
16479 | { | |
16480 | suffix[0] = p[0]; | |
16481 | suffix[1] = p[1]; | |
16482 | suffix[2] = '\0'; | |
16483 | } | |
16484 | ||
16485 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16486 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16487 | } | |
43234a1e L |
16488 | else |
16489 | { | |
16490 | /* We have a reserved extension byte. Output it directly. */ | |
16491 | scratchbuf[0] = '$'; | |
16492 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16493 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16494 | scratchbuf[0] = '\0'; |
16495 | } | |
16496 | } | |
16497 | ||
ea397f5b L |
16498 | static const struct op pclmul_op[] = |
16499 | { | |
16500 | { STRING_COMMA_LEN ("lql") }, | |
16501 | { STRING_COMMA_LEN ("hql") }, | |
16502 | { STRING_COMMA_LEN ("lqh") }, | |
16503 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16504 | }; |
16505 | ||
16506 | static void | |
16507 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16508 | int sizeflag ATTRIBUTE_UNUSED) | |
16509 | { | |
16510 | unsigned int pclmul_type; | |
16511 | ||
16512 | FETCH_DATA (the_info, codep + 1); | |
16513 | pclmul_type = *codep++ & 0xff; | |
16514 | switch (pclmul_type) | |
16515 | { | |
16516 | case 0x10: | |
16517 | pclmul_type = 2; | |
16518 | break; | |
16519 | case 0x11: | |
16520 | pclmul_type = 3; | |
16521 | break; | |
16522 | default: | |
16523 | break; | |
7bb15c6f | 16524 | } |
c0f3af97 L |
16525 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16526 | { | |
16527 | char suffix [4]; | |
ea397f5b | 16528 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16529 | suffix[0] = p[0]; |
16530 | suffix[1] = p[1]; | |
16531 | suffix[2] = p[2]; | |
16532 | suffix[3] = '\0'; | |
ea397f5b L |
16533 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16534 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16535 | } |
16536 | else | |
16537 | { | |
16538 | /* We have a reserved extension byte. Output it directly. */ | |
16539 | scratchbuf[0] = '$'; | |
16540 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16541 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16542 | scratchbuf[0] = '\0'; |
16543 | } | |
16544 | } | |
16545 | ||
f1f8f695 L |
16546 | static void |
16547 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16548 | { | |
16549 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16550 | char *p = mnemonicendp; |
f1f8f695 L |
16551 | |
16552 | switch (bytemode) | |
16553 | { | |
16554 | case v_mode: | |
16555 | if (intel_syntax) | |
ea397f5b | 16556 | goto skip; |
f1f8f695 L |
16557 | |
16558 | USED_REX (REX_W); | |
16559 | if (sizeflag & SUFFIX_ALWAYS) | |
16560 | { | |
16561 | if (rex & REX_W) | |
16562 | *p++ = 'q'; | |
f1f8f695 | 16563 | else |
f16cd0d5 L |
16564 | { |
16565 | if (sizeflag & DFLAG) | |
16566 | *p++ = 'l'; | |
16567 | else | |
16568 | *p++ = 'w'; | |
16569 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16570 | } | |
f1f8f695 | 16571 | } |
f1f8f695 L |
16572 | break; |
16573 | default: | |
16574 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16575 | break; | |
16576 | } | |
ea397f5b | 16577 | mnemonicendp = p; |
f1f8f695 L |
16578 | *p = '\0'; |
16579 | ||
ea397f5b | 16580 | skip: |
f1f8f695 L |
16581 | OP_M (bytemode, sizeflag); |
16582 | } | |
f88c9eb0 | 16583 | |
bc31405e L |
16584 | static void |
16585 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16586 | { | |
16587 | /* Add proper suffix to "movsxd". */ | |
16588 | char *p = mnemonicendp; | |
16589 | ||
16590 | switch (bytemode) | |
16591 | { | |
16592 | case movsxd_mode: | |
16593 | if (intel_syntax) | |
16594 | { | |
16595 | *p++ = 'x'; | |
16596 | *p++ = 'd'; | |
16597 | goto skip; | |
16598 | } | |
16599 | ||
16600 | USED_REX (REX_W); | |
16601 | if (rex & REX_W) | |
16602 | { | |
16603 | *p++ = 'l'; | |
16604 | *p++ = 'q'; | |
16605 | } | |
16606 | else | |
16607 | { | |
16608 | *p++ = 'x'; | |
16609 | *p++ = 'd'; | |
16610 | } | |
16611 | break; | |
16612 | default: | |
16613 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16614 | break; | |
16615 | } | |
16616 | ||
16617 | skip: | |
16618 | mnemonicendp = p; | |
16619 | *p = '\0'; | |
16620 | OP_E (bytemode, sizeflag); | |
16621 | } | |
16622 | ||
f88c9eb0 SP |
16623 | static void |
16624 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16625 | { | |
16626 | int reg; | |
16627 | const char **names; | |
16628 | ||
16629 | /* Skip mod/rm byte. */ | |
16630 | MODRM_CHECK; | |
16631 | codep++; | |
16632 | ||
390a6789 | 16633 | if (rex & REX_W) |
f88c9eb0 | 16634 | names = names64; |
f88c9eb0 | 16635 | else |
ce7d077e | 16636 | names = names32; |
f88c9eb0 SP |
16637 | |
16638 | reg = modrm.rm; | |
16639 | USED_REX (REX_B); | |
16640 | if (rex & REX_B) | |
16641 | reg += 8; | |
16642 | ||
16643 | oappend (names[reg]); | |
16644 | } | |
16645 | ||
16646 | static void | |
16647 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16648 | { | |
16649 | const char **names; | |
5f847646 | 16650 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16651 | vex.register_specifier = 0; |
f88c9eb0 | 16652 | |
390a6789 | 16653 | if (rex & REX_W) |
f88c9eb0 | 16654 | names = names64; |
f88c9eb0 | 16655 | else |
ce7d077e | 16656 | names = names32; |
f88c9eb0 | 16657 | |
5f847646 JB |
16658 | if (address_mode != mode_64bit) |
16659 | reg &= 7; | |
16660 | oappend (names[reg]); | |
f88c9eb0 | 16661 | } |
43234a1e L |
16662 | |
16663 | static void | |
16664 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16665 | { | |
16666 | if (!vex.evex | |
1ba585e8 | 16667 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16668 | abort (); |
16669 | ||
16670 | USED_REX (REX_R); | |
16671 | if ((rex & REX_R) != 0 || !vex.r) | |
16672 | { | |
16673 | BadOp (); | |
16674 | return; | |
16675 | } | |
16676 | ||
16677 | oappend (names_mask [modrm.reg]); | |
16678 | } | |
16679 | ||
16680 | static void | |
16681 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16682 | { | |
16683 | if (!vex.evex | |
16684 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16685 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16686 | && bytemode != evex_sae_mode)) |
16687 | abort (); | |
16688 | if (modrm.mod == 3 && vex.b) | |
16689 | switch (bytemode) | |
16690 | { | |
70df6fc9 L |
16691 | case evex_rounding_64_mode: |
16692 | if (address_mode != mode_64bit) | |
16693 | { | |
16694 | oappend ("(bad)"); | |
16695 | break; | |
16696 | } | |
16697 | /* Fall through. */ | |
43234a1e L |
16698 | case evex_rounding_mode: |
16699 | oappend (names_rounding[vex.ll]); | |
16700 | break; | |
16701 | case evex_sae_mode: | |
16702 | oappend ("{sae}"); | |
16703 | break; | |
16704 | default: | |
16705 | break; | |
16706 | } | |
16707 | } |