Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
82704155 | 2 | Copyright (C) 1988-2019 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
9916071f | 104 | static void OP_Mwaitx (int, int); |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
252b5132 | 127 | |
43234a1e L |
128 | static void OP_Mask (int, int); |
129 | ||
6608db57 | 130 | struct dis_private { |
252b5132 RH |
131 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; | |
0b1cf022 | 133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 134 | bfd_vma insn_start; |
e396998b | 135 | int orig_sizeflag; |
8df14d78 | 136 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
137 | }; |
138 | ||
cb712a9e L |
139 | enum address_mode |
140 | { | |
141 | mode_16bit, | |
142 | mode_32bit, | |
143 | mode_64bit | |
144 | }; | |
145 | ||
146 | enum address_mode address_mode; | |
52b15da3 | 147 | |
5076851f ILT |
148 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; | |
150 | ||
52b15da3 JH |
151 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; | |
153 | /* Bits of REX we've already used. */ | |
154 | static int rex_used; | |
d869730d | 155 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 156 | static int rex_ignored; |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
d20dee9e | 262 | #define Edqa { OP_E, dqa_mode } |
09335d05 | 263 | #define Eq { OP_E, q_mode } |
07f5af7d | 264 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
265 | #define indirEp { OP_indirE, f_mode } |
266 | #define stackEv { OP_E, stack_v_mode } | |
267 | #define Em { OP_E, m_mode } | |
268 | #define Ew { OP_E, w_mode } | |
269 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 270 | #define Ma { OP_M, a_mode } |
b844680a | 271 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 272 | #define Md { OP_M, d_mode } |
f1f8f695 | 273 | #define Mo { OP_M, o_mode } |
ce518a5f L |
274 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
275 | #define Mq { OP_M, q_mode } | |
d276ec69 | 276 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 277 | #define Mx { OP_M, x_mode } |
c0f3af97 | 278 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 279 | #define Gb { OP_G, b_mode } |
7e8b059b | 280 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
281 | #define Gv { OP_G, v_mode } |
282 | #define Gd { OP_G, d_mode } | |
283 | #define Gdq { OP_G, dq_mode } | |
284 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 285 | #define Gva { OP_G, va_mode } |
ce518a5f | 286 | #define Gw { OP_G, w_mode } |
6f74c397 | 287 | #define Rd { OP_R, d_mode } |
43234a1e | 288 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 289 | #define Rm { OP_R, m_mode } |
ce518a5f L |
290 | #define Ib { OP_I, b_mode } |
291 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 292 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 293 | #define Iv { OP_I, v_mode } |
7bb15c6f | 294 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
295 | #define Iq { OP_I, q_mode } |
296 | #define Iv64 { OP_I64, v_mode } | |
297 | #define Iw { OP_I, w_mode } | |
298 | #define I1 { OP_I, const_1_mode } | |
299 | #define Jb { OP_J, b_mode } | |
300 | #define Jv { OP_J, v_mode } | |
301 | #define Cm { OP_C, m_mode } | |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
539f890d | 387 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 388 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 389 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 390 | #define EXq { OP_EX, q_mode } |
539f890d L |
391 | #define EXqScalar { OP_EX, q_scalar_mode } |
392 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 393 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 394 | #define EXx { OP_EX, x_mode } |
b6169b20 | 395 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 396 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 397 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 398 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 399 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
400 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
401 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
402 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
403 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 404 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
405 | #define EXxmmdw { OP_EX, xmmdw_mode } |
406 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 407 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 408 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 409 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
410 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
411 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
412 | #define MS { OP_MS, v_mode } |
413 | #define XS { OP_XS, v_mode } | |
09335d05 | 414 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 415 | #define MXC { OP_MXC, 0 } |
ce518a5f | 416 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 417 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 418 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 419 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
420 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
421 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 422 | |
c0f3af97 | 423 | #define Vex { OP_VEX, vex_mode } |
539f890d | 424 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 425 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
426 | #define Vex128 { OP_VEX, vex128_mode } |
427 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 428 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 429 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 430 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 431 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 432 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 433 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 434 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
435 | #define EXVexW { OP_EX_VexW, x_mode } |
436 | #define EXdVexW { OP_EX_VexW, d_mode } | |
437 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 438 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 439 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 440 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 441 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
442 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
443 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 444 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 445 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 446 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
447 | |
448 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 449 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
450 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
451 | ||
452 | #define XMask { OP_Mask, mask_mode } | |
453 | #define MaskG { OP_G, mask_mode } | |
454 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 455 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
456 | #define MaskR { OP_R, mask_mode } |
457 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 458 | |
6c30d220 | 459 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 460 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 461 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 462 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 463 | |
35c52694 | 464 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
465 | #define Xbr { REP_Fixup, eSI_reg } |
466 | #define Xvr { REP_Fixup, eSI_reg } | |
467 | #define Ybr { REP_Fixup, eDI_reg } | |
468 | #define Yvr { REP_Fixup, eDI_reg } | |
469 | #define Yzr { REP_Fixup, eDI_reg } | |
470 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
471 | #define ALr { REP_Fixup, al_reg } | |
472 | #define eAXr { REP_Fixup, eAX_reg } | |
473 | ||
42164a71 L |
474 | /* Used handle HLE prefix for lockable instructions. */ |
475 | #define Ebh1 { HLE_Fixup1, b_mode } | |
476 | #define Evh1 { HLE_Fixup1, v_mode } | |
477 | #define Ebh2 { HLE_Fixup2, b_mode } | |
478 | #define Evh2 { HLE_Fixup2, v_mode } | |
479 | #define Ebh3 { HLE_Fixup3, b_mode } | |
480 | #define Evh3 { HLE_Fixup3, v_mode } | |
481 | ||
7e8b059b | 482 | #define BND { BND_Fixup, 0 } |
04ef582a | 483 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 484 | |
ce518a5f L |
485 | #define cond_jump_flag { NULL, cond_jump_mode } |
486 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 487 | |
252b5132 | 488 | /* bits in sizeflag */ |
252b5132 | 489 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
490 | #define AFLAG 2 |
491 | #define DFLAG 1 | |
492 | ||
51e7da1b L |
493 | enum |
494 | { | |
495 | /* byte operand */ | |
496 | b_mode = 1, | |
497 | /* byte operand with operand swapped */ | |
3873ba12 | 498 | b_swap_mode, |
e3949f17 L |
499 | /* byte operand, sign extend like 'T' suffix */ |
500 | b_T_mode, | |
51e7da1b | 501 | /* operand size depends on prefixes */ |
3873ba12 | 502 | v_mode, |
51e7da1b | 503 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 504 | v_swap_mode, |
de89d0a3 IT |
505 | /* operand size depends on address prefix */ |
506 | va_mode, | |
51e7da1b | 507 | /* word operand */ |
3873ba12 | 508 | w_mode, |
51e7da1b | 509 | /* double word operand */ |
3873ba12 | 510 | d_mode, |
51e7da1b | 511 | /* double word operand with operand swapped */ |
3873ba12 | 512 | d_swap_mode, |
51e7da1b | 513 | /* quad word operand */ |
3873ba12 | 514 | q_mode, |
51e7da1b | 515 | /* quad word operand with operand swapped */ |
3873ba12 | 516 | q_swap_mode, |
51e7da1b | 517 | /* ten-byte operand */ |
3873ba12 | 518 | t_mode, |
43234a1e L |
519 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
520 | broadcast enabled. */ | |
3873ba12 | 521 | x_mode, |
43234a1e L |
522 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
523 | evex_x_gscat_mode, | |
524 | /* Similar to x_mode, but with disabled broadcast. */ | |
525 | evex_x_nobcst_mode, | |
526 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
527 | in EVEX. */ | |
3873ba12 | 528 | x_swap_mode, |
51e7da1b | 529 | /* 16-byte XMM operand */ |
3873ba12 | 530 | xmm_mode, |
43234a1e L |
531 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
532 | memory operand (depending on vector length). Broadcast isn't | |
533 | allowed. */ | |
3873ba12 | 534 | xmmq_mode, |
43234a1e L |
535 | /* Same as xmmq_mode, but broadcast is allowed. */ |
536 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
537 | /* XMM register or byte memory operand */ |
538 | xmm_mb_mode, | |
539 | /* XMM register or word memory operand */ | |
540 | xmm_mw_mode, | |
541 | /* XMM register or double word memory operand */ | |
542 | xmm_md_mode, | |
543 | /* XMM register or quad word memory operand */ | |
544 | xmm_mq_mode, | |
43234a1e L |
545 | /* XMM register or double/quad word memory operand, depending on |
546 | VEX.W. */ | |
547 | xmm_mdq_mode, | |
548 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 549 | xmmdw_mode, |
43234a1e | 550 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 551 | xmmqd_mode, |
43234a1e L |
552 | /* 32-byte YMM operand */ |
553 | ymm_mode, | |
554 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 555 | ymmq_mode, |
6c30d220 L |
556 | /* 32-byte YMM or 16-byte word operand */ |
557 | ymmxmm_mode, | |
51e7da1b | 558 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 559 | m_mode, |
51e7da1b | 560 | /* pair of v_mode operands */ |
3873ba12 L |
561 | a_mode, |
562 | cond_jump_mode, | |
563 | loop_jcxz_mode, | |
7e8b059b | 564 | v_bnd_mode, |
d276ec69 JB |
565 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
566 | v_bndmk_mode, | |
51e7da1b | 567 | /* operand size depends on REX prefixes. */ |
3873ba12 | 568 | dq_mode, |
51e7da1b | 569 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 570 | dqw_mode, |
9f79e886 | 571 | /* bounds operand */ |
7e8b059b | 572 | bnd_mode, |
9f79e886 JB |
573 | /* bounds operand with operand swapped */ |
574 | bnd_swap_mode, | |
51e7da1b | 575 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
576 | f_mode, |
577 | const_1_mode, | |
07f5af7d L |
578 | /* v_mode for indirect branch opcodes. */ |
579 | indir_v_mode, | |
51e7da1b | 580 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 581 | stack_v_mode, |
51e7da1b | 582 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 583 | z_mode, |
51e7da1b | 584 | /* 16-byte operand */ |
3873ba12 | 585 | o_mode, |
51e7da1b | 586 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 587 | dqb_mode, |
1ba585e8 IT |
588 | /* registers like d_mode, memory like b_mode. */ |
589 | db_mode, | |
590 | /* registers like d_mode, memory like w_mode. */ | |
591 | dw_mode, | |
51e7da1b | 592 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 593 | dqd_mode, |
d20dee9e L |
594 | /* operand size depends on the W bit as well as address mode. */ |
595 | dqa_mode, | |
51e7da1b | 596 | /* normal vex mode */ |
3873ba12 | 597 | vex_mode, |
51e7da1b | 598 | /* 128bit vex mode */ |
3873ba12 | 599 | vex128_mode, |
51e7da1b | 600 | /* 256bit vex mode */ |
3873ba12 | 601 | vex256_mode, |
51e7da1b | 602 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 603 | vex_w_dq_mode, |
d55ee72f | 604 | |
6c30d220 L |
605 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
606 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
607 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
608 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
609 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
610 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
611 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
612 | vex_vsib_q_w_d_mode, | |
6c30d220 | 613 | |
539f890d L |
614 | /* scalar, ignore vector length. */ |
615 | scalar_mode, | |
53467f57 IT |
616 | /* like b_mode, ignore vector length. */ |
617 | b_scalar_mode, | |
618 | /* like w_mode, ignore vector length. */ | |
619 | w_scalar_mode, | |
539f890d L |
620 | /* like d_mode, ignore vector length. */ |
621 | d_scalar_mode, | |
622 | /* like d_swap_mode, ignore vector length. */ | |
623 | d_scalar_swap_mode, | |
624 | /* like q_mode, ignore vector length. */ | |
625 | q_scalar_mode, | |
626 | /* like q_swap_mode, ignore vector length. */ | |
627 | q_scalar_swap_mode, | |
628 | /* like vex_mode, ignore vector length. */ | |
629 | vex_scalar_mode, | |
1c480963 L |
630 | /* like vex_w_dq_mode, ignore vector length. */ |
631 | vex_scalar_w_dq_mode, | |
539f890d | 632 | |
43234a1e L |
633 | /* Static rounding. */ |
634 | evex_rounding_mode, | |
70df6fc9 L |
635 | /* Static rounding, 64-bit mode only. */ |
636 | evex_rounding_64_mode, | |
43234a1e L |
637 | /* Supress all exceptions. */ |
638 | evex_sae_mode, | |
639 | ||
640 | /* Mask register operand. */ | |
641 | mask_mode, | |
1ba585e8 IT |
642 | /* Mask register operand. */ |
643 | mask_bd_mode, | |
43234a1e | 644 | |
3873ba12 L |
645 | es_reg, |
646 | cs_reg, | |
647 | ss_reg, | |
648 | ds_reg, | |
649 | fs_reg, | |
650 | gs_reg, | |
d55ee72f | 651 | |
3873ba12 L |
652 | eAX_reg, |
653 | eCX_reg, | |
654 | eDX_reg, | |
655 | eBX_reg, | |
656 | eSP_reg, | |
657 | eBP_reg, | |
658 | eSI_reg, | |
659 | eDI_reg, | |
d55ee72f | 660 | |
3873ba12 L |
661 | al_reg, |
662 | cl_reg, | |
663 | dl_reg, | |
664 | bl_reg, | |
665 | ah_reg, | |
666 | ch_reg, | |
667 | dh_reg, | |
668 | bh_reg, | |
d55ee72f | 669 | |
3873ba12 L |
670 | ax_reg, |
671 | cx_reg, | |
672 | dx_reg, | |
673 | bx_reg, | |
674 | sp_reg, | |
675 | bp_reg, | |
676 | si_reg, | |
677 | di_reg, | |
d55ee72f | 678 | |
3873ba12 L |
679 | rAX_reg, |
680 | rCX_reg, | |
681 | rDX_reg, | |
682 | rBX_reg, | |
683 | rSP_reg, | |
684 | rBP_reg, | |
685 | rSI_reg, | |
686 | rDI_reg, | |
d55ee72f | 687 | |
3873ba12 L |
688 | z_mode_ax_reg, |
689 | indir_dx_reg | |
51e7da1b | 690 | }; |
252b5132 | 691 | |
51e7da1b L |
692 | enum |
693 | { | |
694 | FLOATCODE = 1, | |
3873ba12 L |
695 | USE_REG_TABLE, |
696 | USE_MOD_TABLE, | |
697 | USE_RM_TABLE, | |
698 | USE_PREFIX_TABLE, | |
699 | USE_X86_64_TABLE, | |
700 | USE_3BYTE_TABLE, | |
f88c9eb0 | 701 | USE_XOP_8F_TABLE, |
3873ba12 L |
702 | USE_VEX_C4_TABLE, |
703 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 704 | USE_VEX_LEN_TABLE, |
43234a1e | 705 | USE_VEX_W_TABLE, |
04e2a182 L |
706 | USE_EVEX_TABLE, |
707 | USE_EVEX_LEN_TABLE | |
51e7da1b | 708 | }; |
6439fc28 | 709 | |
bf890a93 | 710 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 711 | |
bf890a93 IT |
712 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
713 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
714 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
715 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
716 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
717 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
718 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
719 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 720 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 721 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
722 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
723 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
724 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 725 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 726 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 727 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 728 | |
51e7da1b L |
729 | enum |
730 | { | |
731 | REG_80 = 0, | |
3873ba12 | 732 | REG_81, |
7148c369 | 733 | REG_83, |
3873ba12 L |
734 | REG_8F, |
735 | REG_C0, | |
736 | REG_C1, | |
737 | REG_C6, | |
738 | REG_C7, | |
739 | REG_D0, | |
740 | REG_D1, | |
741 | REG_D2, | |
742 | REG_D3, | |
743 | REG_F6, | |
744 | REG_F7, | |
745 | REG_FE, | |
746 | REG_FF, | |
747 | REG_0F00, | |
748 | REG_0F01, | |
749 | REG_0F0D, | |
750 | REG_0F18, | |
c48935d7 | 751 | REG_0F1C_MOD_0, |
603555e5 | 752 | REG_0F1E_MOD_3, |
3873ba12 L |
753 | REG_0F71, |
754 | REG_0F72, | |
755 | REG_0F73, | |
756 | REG_0FA6, | |
757 | REG_0FA7, | |
758 | REG_0FAE, | |
759 | REG_0FBA, | |
760 | REG_0FC7, | |
592a252b L |
761 | REG_VEX_0F71, |
762 | REG_VEX_0F72, | |
763 | REG_VEX_0F73, | |
764 | REG_VEX_0FAE, | |
f12dc422 | 765 | REG_VEX_0F38F3, |
f88c9eb0 | 766 | REG_XOP_LWPCB, |
2a2a0f38 QN |
767 | REG_XOP_LWP, |
768 | REG_XOP_TBM_01, | |
43234a1e L |
769 | REG_XOP_TBM_02, |
770 | ||
1ba585e8 | 771 | REG_EVEX_0F71, |
43234a1e L |
772 | REG_EVEX_0F72, |
773 | REG_EVEX_0F73, | |
774 | REG_EVEX_0F38C6, | |
775 | REG_EVEX_0F38C7 | |
51e7da1b | 776 | }; |
1ceb70f8 | 777 | |
51e7da1b L |
778 | enum |
779 | { | |
780 | MOD_8D = 0, | |
42164a71 L |
781 | MOD_C6_REG_7, |
782 | MOD_C7_REG_7, | |
4a357820 MZ |
783 | MOD_FF_REG_3, |
784 | MOD_FF_REG_5, | |
3873ba12 L |
785 | MOD_0F01_REG_0, |
786 | MOD_0F01_REG_1, | |
787 | MOD_0F01_REG_2, | |
788 | MOD_0F01_REG_3, | |
8eab4136 | 789 | MOD_0F01_REG_5, |
3873ba12 L |
790 | MOD_0F01_REG_7, |
791 | MOD_0F12_PREFIX_0, | |
792 | MOD_0F13, | |
793 | MOD_0F16_PREFIX_0, | |
794 | MOD_0F17, | |
795 | MOD_0F18_REG_0, | |
796 | MOD_0F18_REG_1, | |
797 | MOD_0F18_REG_2, | |
798 | MOD_0F18_REG_3, | |
d7189fa5 RM |
799 | MOD_0F18_REG_4, |
800 | MOD_0F18_REG_5, | |
801 | MOD_0F18_REG_6, | |
802 | MOD_0F18_REG_7, | |
7e8b059b L |
803 | MOD_0F1A_PREFIX_0, |
804 | MOD_0F1B_PREFIX_0, | |
805 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 806 | MOD_0F1C_PREFIX_0, |
603555e5 | 807 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
808 | MOD_0F24, |
809 | MOD_0F26, | |
810 | MOD_0F2B_PREFIX_0, | |
811 | MOD_0F2B_PREFIX_1, | |
812 | MOD_0F2B_PREFIX_2, | |
813 | MOD_0F2B_PREFIX_3, | |
814 | MOD_0F51, | |
815 | MOD_0F71_REG_2, | |
816 | MOD_0F71_REG_4, | |
817 | MOD_0F71_REG_6, | |
818 | MOD_0F72_REG_2, | |
819 | MOD_0F72_REG_4, | |
820 | MOD_0F72_REG_6, | |
821 | MOD_0F73_REG_2, | |
822 | MOD_0F73_REG_3, | |
823 | MOD_0F73_REG_6, | |
824 | MOD_0F73_REG_7, | |
825 | MOD_0FAE_REG_0, | |
826 | MOD_0FAE_REG_1, | |
827 | MOD_0FAE_REG_2, | |
828 | MOD_0FAE_REG_3, | |
829 | MOD_0FAE_REG_4, | |
830 | MOD_0FAE_REG_5, | |
831 | MOD_0FAE_REG_6, | |
832 | MOD_0FAE_REG_7, | |
833 | MOD_0FB2, | |
834 | MOD_0FB4, | |
835 | MOD_0FB5, | |
a8484f96 | 836 | MOD_0FC3, |
963f3586 IT |
837 | MOD_0FC7_REG_3, |
838 | MOD_0FC7_REG_4, | |
839 | MOD_0FC7_REG_5, | |
3873ba12 L |
840 | MOD_0FC7_REG_6, |
841 | MOD_0FC7_REG_7, | |
842 | MOD_0FD7, | |
843 | MOD_0FE7_PREFIX_2, | |
844 | MOD_0FF0_PREFIX_3, | |
845 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
846 | MOD_0F38F5_PREFIX_2, |
847 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 848 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 849 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 850 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 851 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
852 | MOD_62_32BIT, |
853 | MOD_C4_32BIT, | |
854 | MOD_C5_32BIT, | |
592a252b L |
855 | MOD_VEX_0F12_PREFIX_0, |
856 | MOD_VEX_0F13, | |
857 | MOD_VEX_0F16_PREFIX_0, | |
858 | MOD_VEX_0F17, | |
859 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
860 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
861 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
862 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
863 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
864 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
865 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
866 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
867 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
868 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
869 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
870 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
871 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
872 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
873 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
874 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
875 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
876 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
877 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
878 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
879 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
880 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
881 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
882 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
883 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
884 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
885 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
886 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
887 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
888 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
889 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
890 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
891 | MOD_VEX_0F50, |
892 | MOD_VEX_0F71_REG_2, | |
893 | MOD_VEX_0F71_REG_4, | |
894 | MOD_VEX_0F71_REG_6, | |
895 | MOD_VEX_0F72_REG_2, | |
896 | MOD_VEX_0F72_REG_4, | |
897 | MOD_VEX_0F72_REG_6, | |
898 | MOD_VEX_0F73_REG_2, | |
899 | MOD_VEX_0F73_REG_3, | |
900 | MOD_VEX_0F73_REG_6, | |
901 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
902 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
903 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
904 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
905 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
906 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
907 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 908 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
909 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
910 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 911 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
912 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
913 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
914 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
915 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
916 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
917 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
918 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
919 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
920 | MOD_VEX_0FAE_REG_2, |
921 | MOD_VEX_0FAE_REG_3, | |
922 | MOD_VEX_0FD7_PREFIX_2, | |
923 | MOD_VEX_0FE7_PREFIX_2, | |
924 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
925 | MOD_VEX_0F381A_PREFIX_2, |
926 | MOD_VEX_0F382A_PREFIX_2, | |
927 | MOD_VEX_0F382C_PREFIX_2, | |
928 | MOD_VEX_0F382D_PREFIX_2, | |
929 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
930 | MOD_VEX_0F382F_PREFIX_2, |
931 | MOD_VEX_0F385A_PREFIX_2, | |
932 | MOD_VEX_0F388C_PREFIX_2, | |
933 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
934 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
935 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
936 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
937 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
938 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
939 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
940 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
941 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
942 | |
943 | MOD_EVEX_0F10_PREFIX_1, | |
944 | MOD_EVEX_0F10_PREFIX_3, | |
945 | MOD_EVEX_0F11_PREFIX_1, | |
946 | MOD_EVEX_0F11_PREFIX_3, | |
947 | MOD_EVEX_0F12_PREFIX_0, | |
948 | MOD_EVEX_0F16_PREFIX_0, | |
949 | MOD_EVEX_0F38C6_REG_1, | |
950 | MOD_EVEX_0F38C6_REG_2, | |
951 | MOD_EVEX_0F38C6_REG_5, | |
952 | MOD_EVEX_0F38C6_REG_6, | |
953 | MOD_EVEX_0F38C7_REG_1, | |
954 | MOD_EVEX_0F38C7_REG_2, | |
955 | MOD_EVEX_0F38C7_REG_5, | |
956 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 957 | }; |
1ceb70f8 | 958 | |
51e7da1b L |
959 | enum |
960 | { | |
42164a71 L |
961 | RM_C6_REG_7 = 0, |
962 | RM_C7_REG_7, | |
963 | RM_0F01_REG_0, | |
3873ba12 L |
964 | RM_0F01_REG_1, |
965 | RM_0F01_REG_2, | |
966 | RM_0F01_REG_3, | |
8eab4136 | 967 | RM_0F01_REG_5, |
3873ba12 | 968 | RM_0F01_REG_7, |
603555e5 | 969 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
970 | RM_0FAE_REG_6, |
971 | RM_0FAE_REG_7 | |
51e7da1b | 972 | }; |
1ceb70f8 | 973 | |
51e7da1b L |
974 | enum |
975 | { | |
976 | PREFIX_90 = 0, | |
603555e5 | 977 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 978 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 979 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 980 | PREFIX_0F09, |
3873ba12 L |
981 | PREFIX_0F10, |
982 | PREFIX_0F11, | |
983 | PREFIX_0F12, | |
984 | PREFIX_0F16, | |
7e8b059b L |
985 | PREFIX_0F1A, |
986 | PREFIX_0F1B, | |
c48935d7 | 987 | PREFIX_0F1C, |
603555e5 | 988 | PREFIX_0F1E, |
3873ba12 L |
989 | PREFIX_0F2A, |
990 | PREFIX_0F2B, | |
991 | PREFIX_0F2C, | |
992 | PREFIX_0F2D, | |
993 | PREFIX_0F2E, | |
994 | PREFIX_0F2F, | |
995 | PREFIX_0F51, | |
996 | PREFIX_0F52, | |
997 | PREFIX_0F53, | |
998 | PREFIX_0F58, | |
999 | PREFIX_0F59, | |
1000 | PREFIX_0F5A, | |
1001 | PREFIX_0F5B, | |
1002 | PREFIX_0F5C, | |
1003 | PREFIX_0F5D, | |
1004 | PREFIX_0F5E, | |
1005 | PREFIX_0F5F, | |
1006 | PREFIX_0F60, | |
1007 | PREFIX_0F61, | |
1008 | PREFIX_0F62, | |
1009 | PREFIX_0F6C, | |
1010 | PREFIX_0F6D, | |
1011 | PREFIX_0F6F, | |
1012 | PREFIX_0F70, | |
1013 | PREFIX_0F73_REG_3, | |
1014 | PREFIX_0F73_REG_7, | |
1015 | PREFIX_0F78, | |
1016 | PREFIX_0F79, | |
1017 | PREFIX_0F7C, | |
1018 | PREFIX_0F7D, | |
1019 | PREFIX_0F7E, | |
1020 | PREFIX_0F7F, | |
c7b8aa3a L |
1021 | PREFIX_0FAE_REG_0, |
1022 | PREFIX_0FAE_REG_1, | |
1023 | PREFIX_0FAE_REG_2, | |
1024 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1025 | PREFIX_MOD_0_0FAE_REG_4, |
1026 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1027 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1028 | PREFIX_MOD_3_0FAE_REG_5, |
de89d0a3 IT |
1029 | PREFIX_MOD_0_0FAE_REG_6, |
1030 | PREFIX_MOD_1_0FAE_REG_6, | |
963f3586 | 1031 | PREFIX_0FAE_REG_7, |
3873ba12 | 1032 | PREFIX_0FB8, |
f12dc422 | 1033 | PREFIX_0FBC, |
3873ba12 L |
1034 | PREFIX_0FBD, |
1035 | PREFIX_0FC2, | |
a8484f96 | 1036 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1037 | PREFIX_MOD_0_0FC7_REG_6, |
1038 | PREFIX_MOD_3_0FC7_REG_6, | |
1039 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1040 | PREFIX_0FD0, |
1041 | PREFIX_0FD6, | |
1042 | PREFIX_0FE6, | |
1043 | PREFIX_0FE7, | |
1044 | PREFIX_0FF0, | |
1045 | PREFIX_0FF7, | |
1046 | PREFIX_0F3810, | |
1047 | PREFIX_0F3814, | |
1048 | PREFIX_0F3815, | |
1049 | PREFIX_0F3817, | |
1050 | PREFIX_0F3820, | |
1051 | PREFIX_0F3821, | |
1052 | PREFIX_0F3822, | |
1053 | PREFIX_0F3823, | |
1054 | PREFIX_0F3824, | |
1055 | PREFIX_0F3825, | |
1056 | PREFIX_0F3828, | |
1057 | PREFIX_0F3829, | |
1058 | PREFIX_0F382A, | |
1059 | PREFIX_0F382B, | |
1060 | PREFIX_0F3830, | |
1061 | PREFIX_0F3831, | |
1062 | PREFIX_0F3832, | |
1063 | PREFIX_0F3833, | |
1064 | PREFIX_0F3834, | |
1065 | PREFIX_0F3835, | |
1066 | PREFIX_0F3837, | |
1067 | PREFIX_0F3838, | |
1068 | PREFIX_0F3839, | |
1069 | PREFIX_0F383A, | |
1070 | PREFIX_0F383B, | |
1071 | PREFIX_0F383C, | |
1072 | PREFIX_0F383D, | |
1073 | PREFIX_0F383E, | |
1074 | PREFIX_0F383F, | |
1075 | PREFIX_0F3840, | |
1076 | PREFIX_0F3841, | |
1077 | PREFIX_0F3880, | |
1078 | PREFIX_0F3881, | |
6c30d220 | 1079 | PREFIX_0F3882, |
a0046408 L |
1080 | PREFIX_0F38C8, |
1081 | PREFIX_0F38C9, | |
1082 | PREFIX_0F38CA, | |
1083 | PREFIX_0F38CB, | |
1084 | PREFIX_0F38CC, | |
1085 | PREFIX_0F38CD, | |
48521003 | 1086 | PREFIX_0F38CF, |
3873ba12 L |
1087 | PREFIX_0F38DB, |
1088 | PREFIX_0F38DC, | |
1089 | PREFIX_0F38DD, | |
1090 | PREFIX_0F38DE, | |
1091 | PREFIX_0F38DF, | |
1092 | PREFIX_0F38F0, | |
1093 | PREFIX_0F38F1, | |
603555e5 | 1094 | PREFIX_0F38F5, |
e2e1fcde | 1095 | PREFIX_0F38F6, |
c0a30a9f L |
1096 | PREFIX_0F38F8, |
1097 | PREFIX_0F38F9, | |
3873ba12 L |
1098 | PREFIX_0F3A08, |
1099 | PREFIX_0F3A09, | |
1100 | PREFIX_0F3A0A, | |
1101 | PREFIX_0F3A0B, | |
1102 | PREFIX_0F3A0C, | |
1103 | PREFIX_0F3A0D, | |
1104 | PREFIX_0F3A0E, | |
1105 | PREFIX_0F3A14, | |
1106 | PREFIX_0F3A15, | |
1107 | PREFIX_0F3A16, | |
1108 | PREFIX_0F3A17, | |
1109 | PREFIX_0F3A20, | |
1110 | PREFIX_0F3A21, | |
1111 | PREFIX_0F3A22, | |
1112 | PREFIX_0F3A40, | |
1113 | PREFIX_0F3A41, | |
1114 | PREFIX_0F3A42, | |
1115 | PREFIX_0F3A44, | |
1116 | PREFIX_0F3A60, | |
1117 | PREFIX_0F3A61, | |
1118 | PREFIX_0F3A62, | |
1119 | PREFIX_0F3A63, | |
a0046408 | 1120 | PREFIX_0F3ACC, |
48521003 IT |
1121 | PREFIX_0F3ACE, |
1122 | PREFIX_0F3ACF, | |
3873ba12 | 1123 | PREFIX_0F3ADF, |
592a252b L |
1124 | PREFIX_VEX_0F10, |
1125 | PREFIX_VEX_0F11, | |
1126 | PREFIX_VEX_0F12, | |
1127 | PREFIX_VEX_0F16, | |
1128 | PREFIX_VEX_0F2A, | |
1129 | PREFIX_VEX_0F2C, | |
1130 | PREFIX_VEX_0F2D, | |
1131 | PREFIX_VEX_0F2E, | |
1132 | PREFIX_VEX_0F2F, | |
43234a1e L |
1133 | PREFIX_VEX_0F41, |
1134 | PREFIX_VEX_0F42, | |
1135 | PREFIX_VEX_0F44, | |
1136 | PREFIX_VEX_0F45, | |
1137 | PREFIX_VEX_0F46, | |
1138 | PREFIX_VEX_0F47, | |
1ba585e8 | 1139 | PREFIX_VEX_0F4A, |
43234a1e | 1140 | PREFIX_VEX_0F4B, |
592a252b L |
1141 | PREFIX_VEX_0F51, |
1142 | PREFIX_VEX_0F52, | |
1143 | PREFIX_VEX_0F53, | |
1144 | PREFIX_VEX_0F58, | |
1145 | PREFIX_VEX_0F59, | |
1146 | PREFIX_VEX_0F5A, | |
1147 | PREFIX_VEX_0F5B, | |
1148 | PREFIX_VEX_0F5C, | |
1149 | PREFIX_VEX_0F5D, | |
1150 | PREFIX_VEX_0F5E, | |
1151 | PREFIX_VEX_0F5F, | |
1152 | PREFIX_VEX_0F60, | |
1153 | PREFIX_VEX_0F61, | |
1154 | PREFIX_VEX_0F62, | |
1155 | PREFIX_VEX_0F63, | |
1156 | PREFIX_VEX_0F64, | |
1157 | PREFIX_VEX_0F65, | |
1158 | PREFIX_VEX_0F66, | |
1159 | PREFIX_VEX_0F67, | |
1160 | PREFIX_VEX_0F68, | |
1161 | PREFIX_VEX_0F69, | |
1162 | PREFIX_VEX_0F6A, | |
1163 | PREFIX_VEX_0F6B, | |
1164 | PREFIX_VEX_0F6C, | |
1165 | PREFIX_VEX_0F6D, | |
1166 | PREFIX_VEX_0F6E, | |
1167 | PREFIX_VEX_0F6F, | |
1168 | PREFIX_VEX_0F70, | |
1169 | PREFIX_VEX_0F71_REG_2, | |
1170 | PREFIX_VEX_0F71_REG_4, | |
1171 | PREFIX_VEX_0F71_REG_6, | |
1172 | PREFIX_VEX_0F72_REG_2, | |
1173 | PREFIX_VEX_0F72_REG_4, | |
1174 | PREFIX_VEX_0F72_REG_6, | |
1175 | PREFIX_VEX_0F73_REG_2, | |
1176 | PREFIX_VEX_0F73_REG_3, | |
1177 | PREFIX_VEX_0F73_REG_6, | |
1178 | PREFIX_VEX_0F73_REG_7, | |
1179 | PREFIX_VEX_0F74, | |
1180 | PREFIX_VEX_0F75, | |
1181 | PREFIX_VEX_0F76, | |
1182 | PREFIX_VEX_0F77, | |
1183 | PREFIX_VEX_0F7C, | |
1184 | PREFIX_VEX_0F7D, | |
1185 | PREFIX_VEX_0F7E, | |
1186 | PREFIX_VEX_0F7F, | |
43234a1e L |
1187 | PREFIX_VEX_0F90, |
1188 | PREFIX_VEX_0F91, | |
1189 | PREFIX_VEX_0F92, | |
1190 | PREFIX_VEX_0F93, | |
1191 | PREFIX_VEX_0F98, | |
1ba585e8 | 1192 | PREFIX_VEX_0F99, |
592a252b L |
1193 | PREFIX_VEX_0FC2, |
1194 | PREFIX_VEX_0FC4, | |
1195 | PREFIX_VEX_0FC5, | |
1196 | PREFIX_VEX_0FD0, | |
1197 | PREFIX_VEX_0FD1, | |
1198 | PREFIX_VEX_0FD2, | |
1199 | PREFIX_VEX_0FD3, | |
1200 | PREFIX_VEX_0FD4, | |
1201 | PREFIX_VEX_0FD5, | |
1202 | PREFIX_VEX_0FD6, | |
1203 | PREFIX_VEX_0FD7, | |
1204 | PREFIX_VEX_0FD8, | |
1205 | PREFIX_VEX_0FD9, | |
1206 | PREFIX_VEX_0FDA, | |
1207 | PREFIX_VEX_0FDB, | |
1208 | PREFIX_VEX_0FDC, | |
1209 | PREFIX_VEX_0FDD, | |
1210 | PREFIX_VEX_0FDE, | |
1211 | PREFIX_VEX_0FDF, | |
1212 | PREFIX_VEX_0FE0, | |
1213 | PREFIX_VEX_0FE1, | |
1214 | PREFIX_VEX_0FE2, | |
1215 | PREFIX_VEX_0FE3, | |
1216 | PREFIX_VEX_0FE4, | |
1217 | PREFIX_VEX_0FE5, | |
1218 | PREFIX_VEX_0FE6, | |
1219 | PREFIX_VEX_0FE7, | |
1220 | PREFIX_VEX_0FE8, | |
1221 | PREFIX_VEX_0FE9, | |
1222 | PREFIX_VEX_0FEA, | |
1223 | PREFIX_VEX_0FEB, | |
1224 | PREFIX_VEX_0FEC, | |
1225 | PREFIX_VEX_0FED, | |
1226 | PREFIX_VEX_0FEE, | |
1227 | PREFIX_VEX_0FEF, | |
1228 | PREFIX_VEX_0FF0, | |
1229 | PREFIX_VEX_0FF1, | |
1230 | PREFIX_VEX_0FF2, | |
1231 | PREFIX_VEX_0FF3, | |
1232 | PREFIX_VEX_0FF4, | |
1233 | PREFIX_VEX_0FF5, | |
1234 | PREFIX_VEX_0FF6, | |
1235 | PREFIX_VEX_0FF7, | |
1236 | PREFIX_VEX_0FF8, | |
1237 | PREFIX_VEX_0FF9, | |
1238 | PREFIX_VEX_0FFA, | |
1239 | PREFIX_VEX_0FFB, | |
1240 | PREFIX_VEX_0FFC, | |
1241 | PREFIX_VEX_0FFD, | |
1242 | PREFIX_VEX_0FFE, | |
1243 | PREFIX_VEX_0F3800, | |
1244 | PREFIX_VEX_0F3801, | |
1245 | PREFIX_VEX_0F3802, | |
1246 | PREFIX_VEX_0F3803, | |
1247 | PREFIX_VEX_0F3804, | |
1248 | PREFIX_VEX_0F3805, | |
1249 | PREFIX_VEX_0F3806, | |
1250 | PREFIX_VEX_0F3807, | |
1251 | PREFIX_VEX_0F3808, | |
1252 | PREFIX_VEX_0F3809, | |
1253 | PREFIX_VEX_0F380A, | |
1254 | PREFIX_VEX_0F380B, | |
1255 | PREFIX_VEX_0F380C, | |
1256 | PREFIX_VEX_0F380D, | |
1257 | PREFIX_VEX_0F380E, | |
1258 | PREFIX_VEX_0F380F, | |
1259 | PREFIX_VEX_0F3813, | |
6c30d220 | 1260 | PREFIX_VEX_0F3816, |
592a252b L |
1261 | PREFIX_VEX_0F3817, |
1262 | PREFIX_VEX_0F3818, | |
1263 | PREFIX_VEX_0F3819, | |
1264 | PREFIX_VEX_0F381A, | |
1265 | PREFIX_VEX_0F381C, | |
1266 | PREFIX_VEX_0F381D, | |
1267 | PREFIX_VEX_0F381E, | |
1268 | PREFIX_VEX_0F3820, | |
1269 | PREFIX_VEX_0F3821, | |
1270 | PREFIX_VEX_0F3822, | |
1271 | PREFIX_VEX_0F3823, | |
1272 | PREFIX_VEX_0F3824, | |
1273 | PREFIX_VEX_0F3825, | |
1274 | PREFIX_VEX_0F3828, | |
1275 | PREFIX_VEX_0F3829, | |
1276 | PREFIX_VEX_0F382A, | |
1277 | PREFIX_VEX_0F382B, | |
1278 | PREFIX_VEX_0F382C, | |
1279 | PREFIX_VEX_0F382D, | |
1280 | PREFIX_VEX_0F382E, | |
1281 | PREFIX_VEX_0F382F, | |
1282 | PREFIX_VEX_0F3830, | |
1283 | PREFIX_VEX_0F3831, | |
1284 | PREFIX_VEX_0F3832, | |
1285 | PREFIX_VEX_0F3833, | |
1286 | PREFIX_VEX_0F3834, | |
1287 | PREFIX_VEX_0F3835, | |
6c30d220 | 1288 | PREFIX_VEX_0F3836, |
592a252b L |
1289 | PREFIX_VEX_0F3837, |
1290 | PREFIX_VEX_0F3838, | |
1291 | PREFIX_VEX_0F3839, | |
1292 | PREFIX_VEX_0F383A, | |
1293 | PREFIX_VEX_0F383B, | |
1294 | PREFIX_VEX_0F383C, | |
1295 | PREFIX_VEX_0F383D, | |
1296 | PREFIX_VEX_0F383E, | |
1297 | PREFIX_VEX_0F383F, | |
1298 | PREFIX_VEX_0F3840, | |
1299 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1300 | PREFIX_VEX_0F3845, |
1301 | PREFIX_VEX_0F3846, | |
1302 | PREFIX_VEX_0F3847, | |
1303 | PREFIX_VEX_0F3858, | |
1304 | PREFIX_VEX_0F3859, | |
1305 | PREFIX_VEX_0F385A, | |
1306 | PREFIX_VEX_0F3878, | |
1307 | PREFIX_VEX_0F3879, | |
1308 | PREFIX_VEX_0F388C, | |
1309 | PREFIX_VEX_0F388E, | |
1310 | PREFIX_VEX_0F3890, | |
1311 | PREFIX_VEX_0F3891, | |
1312 | PREFIX_VEX_0F3892, | |
1313 | PREFIX_VEX_0F3893, | |
592a252b L |
1314 | PREFIX_VEX_0F3896, |
1315 | PREFIX_VEX_0F3897, | |
1316 | PREFIX_VEX_0F3898, | |
1317 | PREFIX_VEX_0F3899, | |
1318 | PREFIX_VEX_0F389A, | |
1319 | PREFIX_VEX_0F389B, | |
1320 | PREFIX_VEX_0F389C, | |
1321 | PREFIX_VEX_0F389D, | |
1322 | PREFIX_VEX_0F389E, | |
1323 | PREFIX_VEX_0F389F, | |
1324 | PREFIX_VEX_0F38A6, | |
1325 | PREFIX_VEX_0F38A7, | |
1326 | PREFIX_VEX_0F38A8, | |
1327 | PREFIX_VEX_0F38A9, | |
1328 | PREFIX_VEX_0F38AA, | |
1329 | PREFIX_VEX_0F38AB, | |
1330 | PREFIX_VEX_0F38AC, | |
1331 | PREFIX_VEX_0F38AD, | |
1332 | PREFIX_VEX_0F38AE, | |
1333 | PREFIX_VEX_0F38AF, | |
1334 | PREFIX_VEX_0F38B6, | |
1335 | PREFIX_VEX_0F38B7, | |
1336 | PREFIX_VEX_0F38B8, | |
1337 | PREFIX_VEX_0F38B9, | |
1338 | PREFIX_VEX_0F38BA, | |
1339 | PREFIX_VEX_0F38BB, | |
1340 | PREFIX_VEX_0F38BC, | |
1341 | PREFIX_VEX_0F38BD, | |
1342 | PREFIX_VEX_0F38BE, | |
1343 | PREFIX_VEX_0F38BF, | |
48521003 | 1344 | PREFIX_VEX_0F38CF, |
592a252b L |
1345 | PREFIX_VEX_0F38DB, |
1346 | PREFIX_VEX_0F38DC, | |
1347 | PREFIX_VEX_0F38DD, | |
1348 | PREFIX_VEX_0F38DE, | |
1349 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1350 | PREFIX_VEX_0F38F2, |
1351 | PREFIX_VEX_0F38F3_REG_1, | |
1352 | PREFIX_VEX_0F38F3_REG_2, | |
1353 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1354 | PREFIX_VEX_0F38F5, |
1355 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1356 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1357 | PREFIX_VEX_0F3A00, |
1358 | PREFIX_VEX_0F3A01, | |
1359 | PREFIX_VEX_0F3A02, | |
592a252b L |
1360 | PREFIX_VEX_0F3A04, |
1361 | PREFIX_VEX_0F3A05, | |
1362 | PREFIX_VEX_0F3A06, | |
1363 | PREFIX_VEX_0F3A08, | |
1364 | PREFIX_VEX_0F3A09, | |
1365 | PREFIX_VEX_0F3A0A, | |
1366 | PREFIX_VEX_0F3A0B, | |
1367 | PREFIX_VEX_0F3A0C, | |
1368 | PREFIX_VEX_0F3A0D, | |
1369 | PREFIX_VEX_0F3A0E, | |
1370 | PREFIX_VEX_0F3A0F, | |
1371 | PREFIX_VEX_0F3A14, | |
1372 | PREFIX_VEX_0F3A15, | |
1373 | PREFIX_VEX_0F3A16, | |
1374 | PREFIX_VEX_0F3A17, | |
1375 | PREFIX_VEX_0F3A18, | |
1376 | PREFIX_VEX_0F3A19, | |
1377 | PREFIX_VEX_0F3A1D, | |
1378 | PREFIX_VEX_0F3A20, | |
1379 | PREFIX_VEX_0F3A21, | |
1380 | PREFIX_VEX_0F3A22, | |
43234a1e | 1381 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1382 | PREFIX_VEX_0F3A31, |
43234a1e | 1383 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1384 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1385 | PREFIX_VEX_0F3A38, |
1386 | PREFIX_VEX_0F3A39, | |
592a252b L |
1387 | PREFIX_VEX_0F3A40, |
1388 | PREFIX_VEX_0F3A41, | |
1389 | PREFIX_VEX_0F3A42, | |
1390 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1391 | PREFIX_VEX_0F3A46, |
592a252b L |
1392 | PREFIX_VEX_0F3A48, |
1393 | PREFIX_VEX_0F3A49, | |
1394 | PREFIX_VEX_0F3A4A, | |
1395 | PREFIX_VEX_0F3A4B, | |
1396 | PREFIX_VEX_0F3A4C, | |
1397 | PREFIX_VEX_0F3A5C, | |
1398 | PREFIX_VEX_0F3A5D, | |
1399 | PREFIX_VEX_0F3A5E, | |
1400 | PREFIX_VEX_0F3A5F, | |
1401 | PREFIX_VEX_0F3A60, | |
1402 | PREFIX_VEX_0F3A61, | |
1403 | PREFIX_VEX_0F3A62, | |
1404 | PREFIX_VEX_0F3A63, | |
1405 | PREFIX_VEX_0F3A68, | |
1406 | PREFIX_VEX_0F3A69, | |
1407 | PREFIX_VEX_0F3A6A, | |
1408 | PREFIX_VEX_0F3A6B, | |
1409 | PREFIX_VEX_0F3A6C, | |
1410 | PREFIX_VEX_0F3A6D, | |
1411 | PREFIX_VEX_0F3A6E, | |
1412 | PREFIX_VEX_0F3A6F, | |
1413 | PREFIX_VEX_0F3A78, | |
1414 | PREFIX_VEX_0F3A79, | |
1415 | PREFIX_VEX_0F3A7A, | |
1416 | PREFIX_VEX_0F3A7B, | |
1417 | PREFIX_VEX_0F3A7C, | |
1418 | PREFIX_VEX_0F3A7D, | |
1419 | PREFIX_VEX_0F3A7E, | |
1420 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1421 | PREFIX_VEX_0F3ACE, |
1422 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1423 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1424 | PREFIX_VEX_0F3AF0, |
1425 | ||
1426 | PREFIX_EVEX_0F10, | |
1427 | PREFIX_EVEX_0F11, | |
1428 | PREFIX_EVEX_0F12, | |
1429 | PREFIX_EVEX_0F13, | |
1430 | PREFIX_EVEX_0F14, | |
1431 | PREFIX_EVEX_0F15, | |
1432 | PREFIX_EVEX_0F16, | |
1433 | PREFIX_EVEX_0F17, | |
1434 | PREFIX_EVEX_0F28, | |
1435 | PREFIX_EVEX_0F29, | |
1436 | PREFIX_EVEX_0F2A, | |
1437 | PREFIX_EVEX_0F2B, | |
1438 | PREFIX_EVEX_0F2C, | |
1439 | PREFIX_EVEX_0F2D, | |
1440 | PREFIX_EVEX_0F2E, | |
1441 | PREFIX_EVEX_0F2F, | |
1442 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1443 | PREFIX_EVEX_0F54, |
1444 | PREFIX_EVEX_0F55, | |
1445 | PREFIX_EVEX_0F56, | |
1446 | PREFIX_EVEX_0F57, | |
43234a1e L |
1447 | PREFIX_EVEX_0F58, |
1448 | PREFIX_EVEX_0F59, | |
1449 | PREFIX_EVEX_0F5A, | |
1450 | PREFIX_EVEX_0F5B, | |
1451 | PREFIX_EVEX_0F5C, | |
1452 | PREFIX_EVEX_0F5D, | |
1453 | PREFIX_EVEX_0F5E, | |
1454 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1455 | PREFIX_EVEX_0F60, |
1456 | PREFIX_EVEX_0F61, | |
43234a1e | 1457 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1458 | PREFIX_EVEX_0F63, |
1459 | PREFIX_EVEX_0F64, | |
1460 | PREFIX_EVEX_0F65, | |
43234a1e | 1461 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1462 | PREFIX_EVEX_0F67, |
1463 | PREFIX_EVEX_0F68, | |
1464 | PREFIX_EVEX_0F69, | |
43234a1e | 1465 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1466 | PREFIX_EVEX_0F6B, |
43234a1e L |
1467 | PREFIX_EVEX_0F6C, |
1468 | PREFIX_EVEX_0F6D, | |
1469 | PREFIX_EVEX_0F6E, | |
1470 | PREFIX_EVEX_0F6F, | |
1471 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1472 | PREFIX_EVEX_0F71_REG_2, |
1473 | PREFIX_EVEX_0F71_REG_4, | |
1474 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1475 | PREFIX_EVEX_0F72_REG_0, |
1476 | PREFIX_EVEX_0F72_REG_1, | |
1477 | PREFIX_EVEX_0F72_REG_2, | |
1478 | PREFIX_EVEX_0F72_REG_4, | |
1479 | PREFIX_EVEX_0F72_REG_6, | |
1480 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1481 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1482 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1483 | PREFIX_EVEX_0F73_REG_7, |
1484 | PREFIX_EVEX_0F74, | |
1485 | PREFIX_EVEX_0F75, | |
43234a1e L |
1486 | PREFIX_EVEX_0F76, |
1487 | PREFIX_EVEX_0F78, | |
1488 | PREFIX_EVEX_0F79, | |
1489 | PREFIX_EVEX_0F7A, | |
1490 | PREFIX_EVEX_0F7B, | |
1491 | PREFIX_EVEX_0F7E, | |
1492 | PREFIX_EVEX_0F7F, | |
1493 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1494 | PREFIX_EVEX_0FC4, |
1495 | PREFIX_EVEX_0FC5, | |
43234a1e | 1496 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1497 | PREFIX_EVEX_0FD1, |
43234a1e L |
1498 | PREFIX_EVEX_0FD2, |
1499 | PREFIX_EVEX_0FD3, | |
1500 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1501 | PREFIX_EVEX_0FD5, |
43234a1e | 1502 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FD8, |
1504 | PREFIX_EVEX_0FD9, | |
1505 | PREFIX_EVEX_0FDA, | |
43234a1e | 1506 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1507 | PREFIX_EVEX_0FDC, |
1508 | PREFIX_EVEX_0FDD, | |
1509 | PREFIX_EVEX_0FDE, | |
43234a1e | 1510 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1511 | PREFIX_EVEX_0FE0, |
1512 | PREFIX_EVEX_0FE1, | |
43234a1e | 1513 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1514 | PREFIX_EVEX_0FE3, |
1515 | PREFIX_EVEX_0FE4, | |
1516 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1517 | PREFIX_EVEX_0FE6, |
1518 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1519 | PREFIX_EVEX_0FE8, |
1520 | PREFIX_EVEX_0FE9, | |
1521 | PREFIX_EVEX_0FEA, | |
43234a1e | 1522 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1523 | PREFIX_EVEX_0FEC, |
1524 | PREFIX_EVEX_0FED, | |
1525 | PREFIX_EVEX_0FEE, | |
43234a1e | 1526 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1527 | PREFIX_EVEX_0FF1, |
43234a1e L |
1528 | PREFIX_EVEX_0FF2, |
1529 | PREFIX_EVEX_0FF3, | |
1530 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1531 | PREFIX_EVEX_0FF5, |
1532 | PREFIX_EVEX_0FF6, | |
1533 | PREFIX_EVEX_0FF8, | |
1534 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1535 | PREFIX_EVEX_0FFA, |
1536 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1537 | PREFIX_EVEX_0FFC, |
1538 | PREFIX_EVEX_0FFD, | |
43234a1e | 1539 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1540 | PREFIX_EVEX_0F3800, |
1541 | PREFIX_EVEX_0F3804, | |
1542 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1543 | PREFIX_EVEX_0F380C, |
1544 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F3810, |
43234a1e L |
1546 | PREFIX_EVEX_0F3811, |
1547 | PREFIX_EVEX_0F3812, | |
1548 | PREFIX_EVEX_0F3813, | |
1549 | PREFIX_EVEX_0F3814, | |
1550 | PREFIX_EVEX_0F3815, | |
1551 | PREFIX_EVEX_0F3816, | |
1552 | PREFIX_EVEX_0F3818, | |
1553 | PREFIX_EVEX_0F3819, | |
1554 | PREFIX_EVEX_0F381A, | |
1555 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1556 | PREFIX_EVEX_0F381C, |
1557 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1558 | PREFIX_EVEX_0F381E, |
1559 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1560 | PREFIX_EVEX_0F3820, |
43234a1e L |
1561 | PREFIX_EVEX_0F3821, |
1562 | PREFIX_EVEX_0F3822, | |
1563 | PREFIX_EVEX_0F3823, | |
1564 | PREFIX_EVEX_0F3824, | |
1565 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3826, |
43234a1e L |
1567 | PREFIX_EVEX_0F3827, |
1568 | PREFIX_EVEX_0F3828, | |
1569 | PREFIX_EVEX_0F3829, | |
1570 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1571 | PREFIX_EVEX_0F382B, |
43234a1e L |
1572 | PREFIX_EVEX_0F382C, |
1573 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1574 | PREFIX_EVEX_0F3830, |
43234a1e L |
1575 | PREFIX_EVEX_0F3831, |
1576 | PREFIX_EVEX_0F3832, | |
1577 | PREFIX_EVEX_0F3833, | |
1578 | PREFIX_EVEX_0F3834, | |
1579 | PREFIX_EVEX_0F3835, | |
1580 | PREFIX_EVEX_0F3836, | |
1581 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1582 | PREFIX_EVEX_0F3838, |
43234a1e L |
1583 | PREFIX_EVEX_0F3839, |
1584 | PREFIX_EVEX_0F383A, | |
1585 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1586 | PREFIX_EVEX_0F383C, |
43234a1e | 1587 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1588 | PREFIX_EVEX_0F383E, |
43234a1e L |
1589 | PREFIX_EVEX_0F383F, |
1590 | PREFIX_EVEX_0F3840, | |
1591 | PREFIX_EVEX_0F3842, | |
1592 | PREFIX_EVEX_0F3843, | |
1593 | PREFIX_EVEX_0F3844, | |
1594 | PREFIX_EVEX_0F3845, | |
1595 | PREFIX_EVEX_0F3846, | |
1596 | PREFIX_EVEX_0F3847, | |
1597 | PREFIX_EVEX_0F384C, | |
1598 | PREFIX_EVEX_0F384D, | |
1599 | PREFIX_EVEX_0F384E, | |
1600 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1601 | PREFIX_EVEX_0F3850, |
1602 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1603 | PREFIX_EVEX_0F3852, |
1604 | PREFIX_EVEX_0F3853, | |
ee6872be | 1605 | PREFIX_EVEX_0F3854, |
620214f7 | 1606 | PREFIX_EVEX_0F3855, |
43234a1e L |
1607 | PREFIX_EVEX_0F3858, |
1608 | PREFIX_EVEX_0F3859, | |
1609 | PREFIX_EVEX_0F385A, | |
1610 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1611 | PREFIX_EVEX_0F3862, |
1612 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1613 | PREFIX_EVEX_0F3864, |
1614 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1615 | PREFIX_EVEX_0F3866, |
9186c494 | 1616 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1617 | PREFIX_EVEX_0F3870, |
1618 | PREFIX_EVEX_0F3871, | |
1619 | PREFIX_EVEX_0F3872, | |
1620 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1621 | PREFIX_EVEX_0F3875, |
43234a1e L |
1622 | PREFIX_EVEX_0F3876, |
1623 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1624 | PREFIX_EVEX_0F3878, |
1625 | PREFIX_EVEX_0F3879, | |
1626 | PREFIX_EVEX_0F387A, | |
1627 | PREFIX_EVEX_0F387B, | |
43234a1e | 1628 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1629 | PREFIX_EVEX_0F387D, |
43234a1e L |
1630 | PREFIX_EVEX_0F387E, |
1631 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1632 | PREFIX_EVEX_0F3883, |
43234a1e L |
1633 | PREFIX_EVEX_0F3888, |
1634 | PREFIX_EVEX_0F3889, | |
1635 | PREFIX_EVEX_0F388A, | |
1636 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1637 | PREFIX_EVEX_0F388D, |
ee6872be | 1638 | PREFIX_EVEX_0F388F, |
43234a1e L |
1639 | PREFIX_EVEX_0F3890, |
1640 | PREFIX_EVEX_0F3891, | |
1641 | PREFIX_EVEX_0F3892, | |
1642 | PREFIX_EVEX_0F3893, | |
1643 | PREFIX_EVEX_0F3896, | |
1644 | PREFIX_EVEX_0F3897, | |
1645 | PREFIX_EVEX_0F3898, | |
1646 | PREFIX_EVEX_0F3899, | |
1647 | PREFIX_EVEX_0F389A, | |
1648 | PREFIX_EVEX_0F389B, | |
1649 | PREFIX_EVEX_0F389C, | |
1650 | PREFIX_EVEX_0F389D, | |
1651 | PREFIX_EVEX_0F389E, | |
1652 | PREFIX_EVEX_0F389F, | |
1653 | PREFIX_EVEX_0F38A0, | |
1654 | PREFIX_EVEX_0F38A1, | |
1655 | PREFIX_EVEX_0F38A2, | |
1656 | PREFIX_EVEX_0F38A3, | |
1657 | PREFIX_EVEX_0F38A6, | |
1658 | PREFIX_EVEX_0F38A7, | |
1659 | PREFIX_EVEX_0F38A8, | |
1660 | PREFIX_EVEX_0F38A9, | |
1661 | PREFIX_EVEX_0F38AA, | |
1662 | PREFIX_EVEX_0F38AB, | |
1663 | PREFIX_EVEX_0F38AC, | |
1664 | PREFIX_EVEX_0F38AD, | |
1665 | PREFIX_EVEX_0F38AE, | |
1666 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1667 | PREFIX_EVEX_0F38B4, |
1668 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1669 | PREFIX_EVEX_0F38B6, |
1670 | PREFIX_EVEX_0F38B7, | |
1671 | PREFIX_EVEX_0F38B8, | |
1672 | PREFIX_EVEX_0F38B9, | |
1673 | PREFIX_EVEX_0F38BA, | |
1674 | PREFIX_EVEX_0F38BB, | |
1675 | PREFIX_EVEX_0F38BC, | |
1676 | PREFIX_EVEX_0F38BD, | |
1677 | PREFIX_EVEX_0F38BE, | |
1678 | PREFIX_EVEX_0F38BF, | |
1679 | PREFIX_EVEX_0F38C4, | |
1680 | PREFIX_EVEX_0F38C6_REG_1, | |
1681 | PREFIX_EVEX_0F38C6_REG_2, | |
1682 | PREFIX_EVEX_0F38C6_REG_5, | |
1683 | PREFIX_EVEX_0F38C6_REG_6, | |
1684 | PREFIX_EVEX_0F38C7_REG_1, | |
1685 | PREFIX_EVEX_0F38C7_REG_2, | |
1686 | PREFIX_EVEX_0F38C7_REG_5, | |
1687 | PREFIX_EVEX_0F38C7_REG_6, | |
1688 | PREFIX_EVEX_0F38C8, | |
1689 | PREFIX_EVEX_0F38CA, | |
1690 | PREFIX_EVEX_0F38CB, | |
1691 | PREFIX_EVEX_0F38CC, | |
1692 | PREFIX_EVEX_0F38CD, | |
48521003 | 1693 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1694 | PREFIX_EVEX_0F38DC, |
1695 | PREFIX_EVEX_0F38DD, | |
1696 | PREFIX_EVEX_0F38DE, | |
1697 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1698 | |
1699 | PREFIX_EVEX_0F3A00, | |
1700 | PREFIX_EVEX_0F3A01, | |
1701 | PREFIX_EVEX_0F3A03, | |
1702 | PREFIX_EVEX_0F3A04, | |
1703 | PREFIX_EVEX_0F3A05, | |
1704 | PREFIX_EVEX_0F3A08, | |
1705 | PREFIX_EVEX_0F3A09, | |
1706 | PREFIX_EVEX_0F3A0A, | |
1707 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1708 | PREFIX_EVEX_0F3A0F, |
1709 | PREFIX_EVEX_0F3A14, | |
1710 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1711 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1712 | PREFIX_EVEX_0F3A17, |
1713 | PREFIX_EVEX_0F3A18, | |
1714 | PREFIX_EVEX_0F3A19, | |
1715 | PREFIX_EVEX_0F3A1A, | |
1716 | PREFIX_EVEX_0F3A1B, | |
1717 | PREFIX_EVEX_0F3A1D, | |
1718 | PREFIX_EVEX_0F3A1E, | |
1719 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1720 | PREFIX_EVEX_0F3A20, |
43234a1e | 1721 | PREFIX_EVEX_0F3A21, |
90a915bf | 1722 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1723 | PREFIX_EVEX_0F3A23, |
1724 | PREFIX_EVEX_0F3A25, | |
1725 | PREFIX_EVEX_0F3A26, | |
1726 | PREFIX_EVEX_0F3A27, | |
1727 | PREFIX_EVEX_0F3A38, | |
1728 | PREFIX_EVEX_0F3A39, | |
1729 | PREFIX_EVEX_0F3A3A, | |
1730 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1731 | PREFIX_EVEX_0F3A3E, |
1732 | PREFIX_EVEX_0F3A3F, | |
1733 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1734 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1735 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1736 | PREFIX_EVEX_0F3A50, |
1737 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1738 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1739 | PREFIX_EVEX_0F3A55, |
1740 | PREFIX_EVEX_0F3A56, | |
1741 | PREFIX_EVEX_0F3A57, | |
1742 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1743 | PREFIX_EVEX_0F3A67, |
1744 | PREFIX_EVEX_0F3A70, | |
1745 | PREFIX_EVEX_0F3A71, | |
1746 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1747 | PREFIX_EVEX_0F3A73, |
1748 | PREFIX_EVEX_0F3ACE, | |
1749 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1750 | }; |
4e7d34a6 | 1751 | |
51e7da1b L |
1752 | enum |
1753 | { | |
1754 | X86_64_06 = 0, | |
3873ba12 L |
1755 | X86_64_07, |
1756 | X86_64_0D, | |
1757 | X86_64_16, | |
1758 | X86_64_17, | |
1759 | X86_64_1E, | |
1760 | X86_64_1F, | |
1761 | X86_64_27, | |
1762 | X86_64_2F, | |
1763 | X86_64_37, | |
1764 | X86_64_3F, | |
1765 | X86_64_60, | |
1766 | X86_64_61, | |
1767 | X86_64_62, | |
1768 | X86_64_63, | |
1769 | X86_64_6D, | |
1770 | X86_64_6F, | |
d039fef3 | 1771 | X86_64_82, |
3873ba12 L |
1772 | X86_64_9A, |
1773 | X86_64_C4, | |
1774 | X86_64_C5, | |
1775 | X86_64_CE, | |
1776 | X86_64_D4, | |
1777 | X86_64_D5, | |
a72d2af2 L |
1778 | X86_64_E8, |
1779 | X86_64_E9, | |
3873ba12 L |
1780 | X86_64_EA, |
1781 | X86_64_0F01_REG_0, | |
1782 | X86_64_0F01_REG_1, | |
1783 | X86_64_0F01_REG_2, | |
1784 | X86_64_0F01_REG_3 | |
51e7da1b | 1785 | }; |
4e7d34a6 | 1786 | |
51e7da1b L |
1787 | enum |
1788 | { | |
1789 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1790 | THREE_BYTE_0F3A |
51e7da1b | 1791 | }; |
4e7d34a6 | 1792 | |
f88c9eb0 SP |
1793 | enum |
1794 | { | |
5dd85c99 SP |
1795 | XOP_08 = 0, |
1796 | XOP_09, | |
f88c9eb0 SP |
1797 | XOP_0A |
1798 | }; | |
1799 | ||
51e7da1b L |
1800 | enum |
1801 | { | |
1802 | VEX_0F = 0, | |
3873ba12 L |
1803 | VEX_0F38, |
1804 | VEX_0F3A | |
51e7da1b | 1805 | }; |
c0f3af97 | 1806 | |
43234a1e L |
1807 | enum |
1808 | { | |
1809 | EVEX_0F = 0, | |
1810 | EVEX_0F38, | |
1811 | EVEX_0F3A | |
1812 | }; | |
1813 | ||
51e7da1b L |
1814 | enum |
1815 | { | |
ec6f095a | 1816 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b L |
1817 | VEX_LEN_0F12_P_0_M_1, |
1818 | VEX_LEN_0F12_P_2, | |
1819 | VEX_LEN_0F13_M_0, | |
1820 | VEX_LEN_0F16_P_0_M_0, | |
1821 | VEX_LEN_0F16_P_0_M_1, | |
1822 | VEX_LEN_0F16_P_2, | |
1823 | VEX_LEN_0F17_M_0, | |
1824 | VEX_LEN_0F2A_P_1, | |
1825 | VEX_LEN_0F2A_P_3, | |
1826 | VEX_LEN_0F2C_P_1, | |
1827 | VEX_LEN_0F2C_P_3, | |
1828 | VEX_LEN_0F2D_P_1, | |
1829 | VEX_LEN_0F2D_P_3, | |
43234a1e | 1830 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1831 | VEX_LEN_0F41_P_2, |
43234a1e | 1832 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1833 | VEX_LEN_0F42_P_2, |
43234a1e | 1834 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1835 | VEX_LEN_0F44_P_2, |
43234a1e | 1836 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1837 | VEX_LEN_0F45_P_2, |
43234a1e | 1838 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1839 | VEX_LEN_0F46_P_2, |
43234a1e | 1840 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1841 | VEX_LEN_0F47_P_2, |
1842 | VEX_LEN_0F4A_P_0, | |
1843 | VEX_LEN_0F4A_P_2, | |
1844 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1845 | VEX_LEN_0F4B_P_2, |
592a252b | 1846 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1847 | VEX_LEN_0F77_P_0, |
592a252b L |
1848 | VEX_LEN_0F7E_P_1, |
1849 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1850 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1851 | VEX_LEN_0F90_P_2, |
43234a1e | 1852 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1853 | VEX_LEN_0F91_P_2, |
43234a1e | 1854 | VEX_LEN_0F92_P_0, |
90a915bf | 1855 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1856 | VEX_LEN_0F92_P_3, |
43234a1e | 1857 | VEX_LEN_0F93_P_0, |
90a915bf | 1858 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1859 | VEX_LEN_0F93_P_3, |
43234a1e | 1860 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1861 | VEX_LEN_0F98_P_2, |
1862 | VEX_LEN_0F99_P_0, | |
1863 | VEX_LEN_0F99_P_2, | |
592a252b L |
1864 | VEX_LEN_0FAE_R_2_M_0, |
1865 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1866 | VEX_LEN_0FC4_P_2, |
1867 | VEX_LEN_0FC5_P_2, | |
592a252b | 1868 | VEX_LEN_0FD6_P_2, |
592a252b | 1869 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1870 | VEX_LEN_0F3816_P_2, |
1871 | VEX_LEN_0F3819_P_2, | |
592a252b | 1872 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1873 | VEX_LEN_0F3836_P_2, |
592a252b | 1874 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1875 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1876 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1877 | VEX_LEN_0F38F2_P_0, |
1878 | VEX_LEN_0F38F3_R_1_P_0, | |
1879 | VEX_LEN_0F38F3_R_2_P_0, | |
1880 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1881 | VEX_LEN_0F38F5_P_0, |
1882 | VEX_LEN_0F38F5_P_1, | |
1883 | VEX_LEN_0F38F5_P_3, | |
1884 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1885 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1886 | VEX_LEN_0F38F7_P_1, |
1887 | VEX_LEN_0F38F7_P_2, | |
1888 | VEX_LEN_0F38F7_P_3, | |
1889 | VEX_LEN_0F3A00_P_2, | |
1890 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1891 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1892 | VEX_LEN_0F3A14_P_2, |
1893 | VEX_LEN_0F3A15_P_2, | |
1894 | VEX_LEN_0F3A16_P_2, | |
1895 | VEX_LEN_0F3A17_P_2, | |
1896 | VEX_LEN_0F3A18_P_2, | |
1897 | VEX_LEN_0F3A19_P_2, | |
1898 | VEX_LEN_0F3A20_P_2, | |
1899 | VEX_LEN_0F3A21_P_2, | |
1900 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1901 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1902 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1903 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1904 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1905 | VEX_LEN_0F3A38_P_2, |
1906 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1907 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1908 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1909 | VEX_LEN_0F3A60_P_2, |
1910 | VEX_LEN_0F3A61_P_2, | |
1911 | VEX_LEN_0F3A62_P_2, | |
1912 | VEX_LEN_0F3A63_P_2, | |
1913 | VEX_LEN_0F3A6A_P_2, | |
1914 | VEX_LEN_0F3A6B_P_2, | |
1915 | VEX_LEN_0F3A6E_P_2, | |
1916 | VEX_LEN_0F3A6F_P_2, | |
1917 | VEX_LEN_0F3A7A_P_2, | |
1918 | VEX_LEN_0F3A7B_P_2, | |
1919 | VEX_LEN_0F3A7E_P_2, | |
1920 | VEX_LEN_0F3A7F_P_2, | |
1921 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1922 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1923 | VEX_LEN_0FXOP_08_CC, |
1924 | VEX_LEN_0FXOP_08_CD, | |
1925 | VEX_LEN_0FXOP_08_CE, | |
1926 | VEX_LEN_0FXOP_08_CF, | |
1927 | VEX_LEN_0FXOP_08_EC, | |
1928 | VEX_LEN_0FXOP_08_ED, | |
1929 | VEX_LEN_0FXOP_08_EE, | |
1930 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1931 | VEX_LEN_0FXOP_09_80, |
1932 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1933 | }; |
c0f3af97 | 1934 | |
04e2a182 L |
1935 | enum |
1936 | { | |
1937 | EVEX_LEN_0F6E_P_2 = 0, | |
1938 | EVEX_LEN_0F7E_P_1, | |
1939 | EVEX_LEN_0F7E_P_2, | |
1940 | EVEX_LEN_0FD6_P_2 | |
1941 | }; | |
1942 | ||
9e30b8e0 L |
1943 | enum |
1944 | { | |
ec6f095a | 1945 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1946 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1947 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1948 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1949 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1950 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1951 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1952 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1953 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1954 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1955 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1956 | VEX_W_0F47_P_2_LEN_1, |
1957 | VEX_W_0F4A_P_0_LEN_1, | |
1958 | VEX_W_0F4A_P_2_LEN_1, | |
1959 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1960 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1961 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1962 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1963 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1964 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1965 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1966 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1967 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1968 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1969 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1970 | VEX_W_0F98_P_2_LEN_0, |
1971 | VEX_W_0F99_P_0_LEN_0, | |
1972 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1973 | VEX_W_0F380C_P_2, |
1974 | VEX_W_0F380D_P_2, | |
1975 | VEX_W_0F380E_P_2, | |
1976 | VEX_W_0F380F_P_2, | |
6c30d220 | 1977 | VEX_W_0F3816_P_2, |
6c30d220 L |
1978 | VEX_W_0F3818_P_2, |
1979 | VEX_W_0F3819_P_2, | |
592a252b | 1980 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1981 | VEX_W_0F382C_P_2_M_0, |
1982 | VEX_W_0F382D_P_2_M_0, | |
1983 | VEX_W_0F382E_P_2_M_0, | |
1984 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1985 | VEX_W_0F3836_P_2, |
6c30d220 L |
1986 | VEX_W_0F3846_P_2, |
1987 | VEX_W_0F3858_P_2, | |
1988 | VEX_W_0F3859_P_2, | |
1989 | VEX_W_0F385A_P_2_M_0, | |
1990 | VEX_W_0F3878_P_2, | |
1991 | VEX_W_0F3879_P_2, | |
48521003 | 1992 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1993 | VEX_W_0F3A00_P_2, |
1994 | VEX_W_0F3A01_P_2, | |
1995 | VEX_W_0F3A02_P_2, | |
592a252b L |
1996 | VEX_W_0F3A04_P_2, |
1997 | VEX_W_0F3A05_P_2, | |
1998 | VEX_W_0F3A06_P_2, | |
592a252b L |
1999 | VEX_W_0F3A18_P_2, |
2000 | VEX_W_0F3A19_P_2, | |
43234a1e | 2001 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2002 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2003 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2004 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2005 | VEX_W_0F3A38_P_2, |
2006 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2007 | VEX_W_0F3A46_P_2, |
592a252b L |
2008 | VEX_W_0F3A48_P_2, |
2009 | VEX_W_0F3A49_P_2, | |
2010 | VEX_W_0F3A4A_P_2, | |
2011 | VEX_W_0F3A4B_P_2, | |
2012 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2013 | VEX_W_0F3ACE_P_2, |
2014 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2015 | |
2016 | EVEX_W_0F10_P_0, | |
2017 | EVEX_W_0F10_P_1_M_0, | |
2018 | EVEX_W_0F10_P_1_M_1, | |
2019 | EVEX_W_0F10_P_2, | |
2020 | EVEX_W_0F10_P_3_M_0, | |
2021 | EVEX_W_0F10_P_3_M_1, | |
2022 | EVEX_W_0F11_P_0, | |
2023 | EVEX_W_0F11_P_1_M_0, | |
2024 | EVEX_W_0F11_P_1_M_1, | |
2025 | EVEX_W_0F11_P_2, | |
2026 | EVEX_W_0F11_P_3_M_0, | |
2027 | EVEX_W_0F11_P_3_M_1, | |
2028 | EVEX_W_0F12_P_0_M_0, | |
2029 | EVEX_W_0F12_P_0_M_1, | |
2030 | EVEX_W_0F12_P_1, | |
2031 | EVEX_W_0F12_P_2, | |
2032 | EVEX_W_0F12_P_3, | |
2033 | EVEX_W_0F13_P_0, | |
2034 | EVEX_W_0F13_P_2, | |
2035 | EVEX_W_0F14_P_0, | |
2036 | EVEX_W_0F14_P_2, | |
2037 | EVEX_W_0F15_P_0, | |
2038 | EVEX_W_0F15_P_2, | |
2039 | EVEX_W_0F16_P_0_M_0, | |
2040 | EVEX_W_0F16_P_0_M_1, | |
2041 | EVEX_W_0F16_P_1, | |
2042 | EVEX_W_0F16_P_2, | |
2043 | EVEX_W_0F17_P_0, | |
2044 | EVEX_W_0F17_P_2, | |
2045 | EVEX_W_0F28_P_0, | |
2046 | EVEX_W_0F28_P_2, | |
2047 | EVEX_W_0F29_P_0, | |
2048 | EVEX_W_0F29_P_2, | |
2049 | EVEX_W_0F2A_P_1, | |
2050 | EVEX_W_0F2A_P_3, | |
2051 | EVEX_W_0F2B_P_0, | |
2052 | EVEX_W_0F2B_P_2, | |
2053 | EVEX_W_0F2E_P_0, | |
2054 | EVEX_W_0F2E_P_2, | |
2055 | EVEX_W_0F2F_P_0, | |
2056 | EVEX_W_0F2F_P_2, | |
2057 | EVEX_W_0F51_P_0, | |
2058 | EVEX_W_0F51_P_1, | |
2059 | EVEX_W_0F51_P_2, | |
2060 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2061 | EVEX_W_0F54_P_0, |
2062 | EVEX_W_0F54_P_2, | |
2063 | EVEX_W_0F55_P_0, | |
2064 | EVEX_W_0F55_P_2, | |
2065 | EVEX_W_0F56_P_0, | |
2066 | EVEX_W_0F56_P_2, | |
2067 | EVEX_W_0F57_P_0, | |
2068 | EVEX_W_0F57_P_2, | |
43234a1e L |
2069 | EVEX_W_0F58_P_0, |
2070 | EVEX_W_0F58_P_1, | |
2071 | EVEX_W_0F58_P_2, | |
2072 | EVEX_W_0F58_P_3, | |
2073 | EVEX_W_0F59_P_0, | |
2074 | EVEX_W_0F59_P_1, | |
2075 | EVEX_W_0F59_P_2, | |
2076 | EVEX_W_0F59_P_3, | |
2077 | EVEX_W_0F5A_P_0, | |
2078 | EVEX_W_0F5A_P_1, | |
2079 | EVEX_W_0F5A_P_2, | |
2080 | EVEX_W_0F5A_P_3, | |
2081 | EVEX_W_0F5B_P_0, | |
2082 | EVEX_W_0F5B_P_1, | |
2083 | EVEX_W_0F5B_P_2, | |
2084 | EVEX_W_0F5C_P_0, | |
2085 | EVEX_W_0F5C_P_1, | |
2086 | EVEX_W_0F5C_P_2, | |
2087 | EVEX_W_0F5C_P_3, | |
2088 | EVEX_W_0F5D_P_0, | |
2089 | EVEX_W_0F5D_P_1, | |
2090 | EVEX_W_0F5D_P_2, | |
2091 | EVEX_W_0F5D_P_3, | |
2092 | EVEX_W_0F5E_P_0, | |
2093 | EVEX_W_0F5E_P_1, | |
2094 | EVEX_W_0F5E_P_2, | |
2095 | EVEX_W_0F5E_P_3, | |
2096 | EVEX_W_0F5F_P_0, | |
2097 | EVEX_W_0F5F_P_1, | |
2098 | EVEX_W_0F5F_P_2, | |
2099 | EVEX_W_0F5F_P_3, | |
2100 | EVEX_W_0F62_P_2, | |
2101 | EVEX_W_0F66_P_2, | |
2102 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2103 | EVEX_W_0F6B_P_2, |
43234a1e L |
2104 | EVEX_W_0F6C_P_2, |
2105 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2106 | EVEX_W_0F6F_P_1, |
2107 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2108 | EVEX_W_0F6F_P_3, |
43234a1e L |
2109 | EVEX_W_0F70_P_2, |
2110 | EVEX_W_0F72_R_2_P_2, | |
2111 | EVEX_W_0F72_R_6_P_2, | |
2112 | EVEX_W_0F73_R_2_P_2, | |
2113 | EVEX_W_0F73_R_6_P_2, | |
2114 | EVEX_W_0F76_P_2, | |
2115 | EVEX_W_0F78_P_0, | |
90a915bf | 2116 | EVEX_W_0F78_P_2, |
43234a1e | 2117 | EVEX_W_0F79_P_0, |
90a915bf | 2118 | EVEX_W_0F79_P_2, |
43234a1e | 2119 | EVEX_W_0F7A_P_1, |
90a915bf | 2120 | EVEX_W_0F7A_P_2, |
43234a1e L |
2121 | EVEX_W_0F7A_P_3, |
2122 | EVEX_W_0F7B_P_1, | |
90a915bf | 2123 | EVEX_W_0F7B_P_2, |
43234a1e L |
2124 | EVEX_W_0F7B_P_3, |
2125 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2126 | EVEX_W_0F7F_P_1, |
2127 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2128 | EVEX_W_0F7F_P_3, |
43234a1e L |
2129 | EVEX_W_0FC2_P_0, |
2130 | EVEX_W_0FC2_P_1, | |
2131 | EVEX_W_0FC2_P_2, | |
2132 | EVEX_W_0FC2_P_3, | |
2133 | EVEX_W_0FC6_P_0, | |
2134 | EVEX_W_0FC6_P_2, | |
2135 | EVEX_W_0FD2_P_2, | |
2136 | EVEX_W_0FD3_P_2, | |
2137 | EVEX_W_0FD4_P_2, | |
2138 | EVEX_W_0FD6_P_2, | |
2139 | EVEX_W_0FE6_P_1, | |
2140 | EVEX_W_0FE6_P_2, | |
2141 | EVEX_W_0FE6_P_3, | |
2142 | EVEX_W_0FE7_P_2, | |
2143 | EVEX_W_0FF2_P_2, | |
2144 | EVEX_W_0FF3_P_2, | |
2145 | EVEX_W_0FF4_P_2, | |
2146 | EVEX_W_0FFA_P_2, | |
2147 | EVEX_W_0FFB_P_2, | |
2148 | EVEX_W_0FFE_P_2, | |
2149 | EVEX_W_0F380C_P_2, | |
2150 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2151 | EVEX_W_0F3810_P_1, |
2152 | EVEX_W_0F3810_P_2, | |
43234a1e | 2153 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2154 | EVEX_W_0F3811_P_2, |
43234a1e | 2155 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2156 | EVEX_W_0F3812_P_2, |
43234a1e L |
2157 | EVEX_W_0F3813_P_1, |
2158 | EVEX_W_0F3813_P_2, | |
2159 | EVEX_W_0F3814_P_1, | |
2160 | EVEX_W_0F3815_P_1, | |
2161 | EVEX_W_0F3818_P_2, | |
2162 | EVEX_W_0F3819_P_2, | |
2163 | EVEX_W_0F381A_P_2, | |
2164 | EVEX_W_0F381B_P_2, | |
2165 | EVEX_W_0F381E_P_2, | |
2166 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2167 | EVEX_W_0F3820_P_1, |
43234a1e L |
2168 | EVEX_W_0F3821_P_1, |
2169 | EVEX_W_0F3822_P_1, | |
2170 | EVEX_W_0F3823_P_1, | |
2171 | EVEX_W_0F3824_P_1, | |
2172 | EVEX_W_0F3825_P_1, | |
2173 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2174 | EVEX_W_0F3826_P_1, |
2175 | EVEX_W_0F3826_P_2, | |
2176 | EVEX_W_0F3828_P_1, | |
43234a1e | 2177 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2178 | EVEX_W_0F3829_P_1, |
43234a1e L |
2179 | EVEX_W_0F3829_P_2, |
2180 | EVEX_W_0F382A_P_1, | |
2181 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2182 | EVEX_W_0F382B_P_2, |
2183 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2184 | EVEX_W_0F3831_P_1, |
2185 | EVEX_W_0F3832_P_1, | |
2186 | EVEX_W_0F3833_P_1, | |
2187 | EVEX_W_0F3834_P_1, | |
2188 | EVEX_W_0F3835_P_1, | |
2189 | EVEX_W_0F3835_P_2, | |
2190 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2191 | EVEX_W_0F3838_P_1, |
2192 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2193 | EVEX_W_0F383A_P_1, |
2194 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2195 | EVEX_W_0F3852_P_1, |
ee6872be | 2196 | EVEX_W_0F3854_P_2, |
620214f7 | 2197 | EVEX_W_0F3855_P_2, |
43234a1e L |
2198 | EVEX_W_0F3858_P_2, |
2199 | EVEX_W_0F3859_P_2, | |
2200 | EVEX_W_0F385A_P_2, | |
2201 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2202 | EVEX_W_0F3862_P_2, |
2203 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2204 | EVEX_W_0F3866_P_2, |
9186c494 | 2205 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2206 | EVEX_W_0F3870_P_2, |
2207 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2208 | EVEX_W_0F3872_P_1, |
53467f57 | 2209 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2210 | EVEX_W_0F3872_P_3, |
53467f57 | 2211 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2212 | EVEX_W_0F3875_P_2, |
2213 | EVEX_W_0F3878_P_2, | |
2214 | EVEX_W_0F3879_P_2, | |
2215 | EVEX_W_0F387A_P_2, | |
2216 | EVEX_W_0F387B_P_2, | |
2217 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2218 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2219 | EVEX_W_0F388D_P_2, |
43234a1e L |
2220 | EVEX_W_0F3891_P_2, |
2221 | EVEX_W_0F3893_P_2, | |
2222 | EVEX_W_0F38A1_P_2, | |
2223 | EVEX_W_0F38A3_P_2, | |
2224 | EVEX_W_0F38C7_R_1_P_2, | |
2225 | EVEX_W_0F38C7_R_2_P_2, | |
2226 | EVEX_W_0F38C7_R_5_P_2, | |
2227 | EVEX_W_0F38C7_R_6_P_2, | |
2228 | ||
2229 | EVEX_W_0F3A00_P_2, | |
2230 | EVEX_W_0F3A01_P_2, | |
2231 | EVEX_W_0F3A04_P_2, | |
2232 | EVEX_W_0F3A05_P_2, | |
2233 | EVEX_W_0F3A08_P_2, | |
2234 | EVEX_W_0F3A09_P_2, | |
2235 | EVEX_W_0F3A0A_P_2, | |
2236 | EVEX_W_0F3A0B_P_2, | |
2237 | EVEX_W_0F3A18_P_2, | |
2238 | EVEX_W_0F3A19_P_2, | |
2239 | EVEX_W_0F3A1A_P_2, | |
2240 | EVEX_W_0F3A1B_P_2, | |
2241 | EVEX_W_0F3A1D_P_2, | |
2242 | EVEX_W_0F3A21_P_2, | |
2243 | EVEX_W_0F3A23_P_2, | |
2244 | EVEX_W_0F3A38_P_2, | |
2245 | EVEX_W_0F3A39_P_2, | |
2246 | EVEX_W_0F3A3A_P_2, | |
2247 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2248 | EVEX_W_0F3A3E_P_2, |
2249 | EVEX_W_0F3A3F_P_2, | |
2250 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2251 | EVEX_W_0F3A43_P_2, |
2252 | EVEX_W_0F3A50_P_2, | |
2253 | EVEX_W_0F3A51_P_2, | |
2254 | EVEX_W_0F3A56_P_2, | |
2255 | EVEX_W_0F3A57_P_2, | |
2256 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2257 | EVEX_W_0F3A67_P_2, |
2258 | EVEX_W_0F3A70_P_2, | |
2259 | EVEX_W_0F3A71_P_2, | |
2260 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2261 | EVEX_W_0F3A73_P_2, |
2262 | EVEX_W_0F3ACE_P_2, | |
2263 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2264 | }; |
2265 | ||
26ca5450 | 2266 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2267 | |
2268 | struct dis386 { | |
2da11e11 | 2269 | const char *name; |
ce518a5f L |
2270 | struct |
2271 | { | |
2272 | op_rtn rtn; | |
2273 | int bytemode; | |
2274 | } op[MAX_OPERANDS]; | |
bf890a93 | 2275 | unsigned int prefix_requirement; |
252b5132 RH |
2276 | }; |
2277 | ||
2278 | /* Upper case letters in the instruction names here are macros. | |
2279 | 'A' => print 'b' if no register operands or suffix_always is true | |
2280 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2281 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2282 | size prefix |
ed7841b3 | 2283 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2284 | suffix_always is true |
252b5132 | 2285 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2286 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2287 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2288 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2289 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2290 | for some of the macro letters) |
9306ca4a | 2291 | 'J' => print 'l' |
42903f7f | 2292 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2293 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2294 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2295 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2296 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2297 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2298 | or suffix_always is true. print 'q' if rex prefix is present. |
2299 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2300 | is true | |
a35ca55a | 2301 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2302 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2303 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2304 | prefix and behave as 'P' otherwise | |
2305 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2306 | prefix and behave as 'Q' otherwise | |
2307 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2308 | prefix and behave as 'S' otherwise | |
a35ca55a | 2309 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2310 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2311 | 'Y' unused. |
6dd5059a | 2312 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2313 | '!' => change condition from true to false or from false to true. |
98b528ac | 2314 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2315 | '^' => print 'w' or 'l' depending on operand size prefix or |
2316 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2317 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2318 | on operand size prefix. | |
07f5af7d L |
2319 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2320 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2321 | otherwise | |
98b528ac L |
2322 | |
2323 | 2 upper case letter macros: | |
04d824a4 JB |
2324 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2325 | operands and no broadcast. | |
2326 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2327 | register operands and no broadcast. | |
4b06377f L |
2328 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2329 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2330 | or suffix_always is true |
4b06377f L |
2331 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2332 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2333 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2334 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2335 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2336 | an operand size prefix, or suffix_always is true. print | |
2337 | 'q' if rex prefix is present. | |
52b15da3 | 2338 | |
6439fc28 AM |
2339 | Many of the above letters print nothing in Intel mode. See "putop" |
2340 | for the details. | |
52b15da3 | 2341 | |
6439fc28 | 2342 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2343 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2344 | |
6439fc28 | 2345 | static const struct dis386 dis386[] = { |
252b5132 | 2346 | /* 00 */ |
bf890a93 IT |
2347 | { "addB", { Ebh1, Gb }, 0 }, |
2348 | { "addS", { Evh1, Gv }, 0 }, | |
2349 | { "addB", { Gb, EbS }, 0 }, | |
2350 | { "addS", { Gv, EvS }, 0 }, | |
2351 | { "addB", { AL, Ib }, 0 }, | |
2352 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2353 | { X86_64_TABLE (X86_64_06) }, |
2354 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2355 | /* 08 */ |
bf890a93 IT |
2356 | { "orB", { Ebh1, Gb }, 0 }, |
2357 | { "orS", { Evh1, Gv }, 0 }, | |
2358 | { "orB", { Gb, EbS }, 0 }, | |
2359 | { "orS", { Gv, EvS }, 0 }, | |
2360 | { "orB", { AL, Ib }, 0 }, | |
2361 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2362 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2363 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2364 | /* 10 */ |
bf890a93 IT |
2365 | { "adcB", { Ebh1, Gb }, 0 }, |
2366 | { "adcS", { Evh1, Gv }, 0 }, | |
2367 | { "adcB", { Gb, EbS }, 0 }, | |
2368 | { "adcS", { Gv, EvS }, 0 }, | |
2369 | { "adcB", { AL, Ib }, 0 }, | |
2370 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2371 | { X86_64_TABLE (X86_64_16) }, |
2372 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2373 | /* 18 */ |
bf890a93 IT |
2374 | { "sbbB", { Ebh1, Gb }, 0 }, |
2375 | { "sbbS", { Evh1, Gv }, 0 }, | |
2376 | { "sbbB", { Gb, EbS }, 0 }, | |
2377 | { "sbbS", { Gv, EvS }, 0 }, | |
2378 | { "sbbB", { AL, Ib }, 0 }, | |
2379 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2380 | { X86_64_TABLE (X86_64_1E) }, |
2381 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2382 | /* 20 */ |
bf890a93 IT |
2383 | { "andB", { Ebh1, Gb }, 0 }, |
2384 | { "andS", { Evh1, Gv }, 0 }, | |
2385 | { "andB", { Gb, EbS }, 0 }, | |
2386 | { "andS", { Gv, EvS }, 0 }, | |
2387 | { "andB", { AL, Ib }, 0 }, | |
2388 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2389 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2390 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2391 | /* 28 */ |
bf890a93 IT |
2392 | { "subB", { Ebh1, Gb }, 0 }, |
2393 | { "subS", { Evh1, Gv }, 0 }, | |
2394 | { "subB", { Gb, EbS }, 0 }, | |
2395 | { "subS", { Gv, EvS }, 0 }, | |
2396 | { "subB", { AL, Ib }, 0 }, | |
2397 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2398 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2399 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2400 | /* 30 */ |
bf890a93 IT |
2401 | { "xorB", { Ebh1, Gb }, 0 }, |
2402 | { "xorS", { Evh1, Gv }, 0 }, | |
2403 | { "xorB", { Gb, EbS }, 0 }, | |
2404 | { "xorS", { Gv, EvS }, 0 }, | |
2405 | { "xorB", { AL, Ib }, 0 }, | |
2406 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2407 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2408 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2409 | /* 38 */ |
bf890a93 IT |
2410 | { "cmpB", { Eb, Gb }, 0 }, |
2411 | { "cmpS", { Ev, Gv }, 0 }, | |
2412 | { "cmpB", { Gb, EbS }, 0 }, | |
2413 | { "cmpS", { Gv, EvS }, 0 }, | |
2414 | { "cmpB", { AL, Ib }, 0 }, | |
2415 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2416 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2417 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2418 | /* 40 */ |
bf890a93 IT |
2419 | { "inc{S|}", { RMeAX }, 0 }, |
2420 | { "inc{S|}", { RMeCX }, 0 }, | |
2421 | { "inc{S|}", { RMeDX }, 0 }, | |
2422 | { "inc{S|}", { RMeBX }, 0 }, | |
2423 | { "inc{S|}", { RMeSP }, 0 }, | |
2424 | { "inc{S|}", { RMeBP }, 0 }, | |
2425 | { "inc{S|}", { RMeSI }, 0 }, | |
2426 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2427 | /* 48 */ |
bf890a93 IT |
2428 | { "dec{S|}", { RMeAX }, 0 }, |
2429 | { "dec{S|}", { RMeCX }, 0 }, | |
2430 | { "dec{S|}", { RMeDX }, 0 }, | |
2431 | { "dec{S|}", { RMeBX }, 0 }, | |
2432 | { "dec{S|}", { RMeSP }, 0 }, | |
2433 | { "dec{S|}", { RMeBP }, 0 }, | |
2434 | { "dec{S|}", { RMeSI }, 0 }, | |
2435 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2436 | /* 50 */ |
bf890a93 IT |
2437 | { "pushV", { RMrAX }, 0 }, |
2438 | { "pushV", { RMrCX }, 0 }, | |
2439 | { "pushV", { RMrDX }, 0 }, | |
2440 | { "pushV", { RMrBX }, 0 }, | |
2441 | { "pushV", { RMrSP }, 0 }, | |
2442 | { "pushV", { RMrBP }, 0 }, | |
2443 | { "pushV", { RMrSI }, 0 }, | |
2444 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2445 | /* 58 */ |
bf890a93 IT |
2446 | { "popV", { RMrAX }, 0 }, |
2447 | { "popV", { RMrCX }, 0 }, | |
2448 | { "popV", { RMrDX }, 0 }, | |
2449 | { "popV", { RMrBX }, 0 }, | |
2450 | { "popV", { RMrSP }, 0 }, | |
2451 | { "popV", { RMrBP }, 0 }, | |
2452 | { "popV", { RMrSI }, 0 }, | |
2453 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2454 | /* 60 */ |
4e7d34a6 L |
2455 | { X86_64_TABLE (X86_64_60) }, |
2456 | { X86_64_TABLE (X86_64_61) }, | |
2457 | { X86_64_TABLE (X86_64_62) }, | |
2458 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2459 | { Bad_Opcode }, /* seg fs */ |
2460 | { Bad_Opcode }, /* seg gs */ | |
2461 | { Bad_Opcode }, /* op size prefix */ | |
2462 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2463 | /* 68 */ |
bf890a93 IT |
2464 | { "pushT", { sIv }, 0 }, |
2465 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2466 | { "pushT", { sIbT }, 0 }, | |
2467 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2468 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2469 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2470 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2471 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2472 | /* 70 */ |
bf890a93 IT |
2473 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2474 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2475 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2476 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2477 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2478 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2479 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2480 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2481 | /* 78 */ |
bf890a93 IT |
2482 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2483 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2484 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2485 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2486 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2487 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2488 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2489 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2490 | /* 80 */ |
1ceb70f8 L |
2491 | { REG_TABLE (REG_80) }, |
2492 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2493 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2494 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2495 | { "testB", { Eb, Gb }, 0 }, |
2496 | { "testS", { Ev, Gv }, 0 }, | |
2497 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2498 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2499 | /* 88 */ |
bf890a93 IT |
2500 | { "movB", { Ebh3, Gb }, 0 }, |
2501 | { "movS", { Evh3, Gv }, 0 }, | |
2502 | { "movB", { Gb, EbS }, 0 }, | |
2503 | { "movS", { Gv, EvS }, 0 }, | |
2504 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2505 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2506 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2507 | { REG_TABLE (REG_8F) }, |
252b5132 | 2508 | /* 90 */ |
1ceb70f8 | 2509 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2510 | { "xchgS", { RMeCX, eAX }, 0 }, |
2511 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2512 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2513 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2514 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2515 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2516 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2517 | /* 98 */ |
bf890a93 IT |
2518 | { "cW{t|}R", { XX }, 0 }, |
2519 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2520 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2521 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2522 | { "pushfT", { XX }, 0 }, |
2523 | { "popfT", { XX }, 0 }, | |
2524 | { "sahf", { XX }, 0 }, | |
2525 | { "lahf", { XX }, 0 }, | |
252b5132 | 2526 | /* a0 */ |
bf890a93 IT |
2527 | { "mov%LB", { AL, Ob }, 0 }, |
2528 | { "mov%LS", { eAX, Ov }, 0 }, | |
2529 | { "mov%LB", { Ob, AL }, 0 }, | |
2530 | { "mov%LS", { Ov, eAX }, 0 }, | |
2531 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2532 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2533 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2534 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2535 | /* a8 */ |
bf890a93 IT |
2536 | { "testB", { AL, Ib }, 0 }, |
2537 | { "testS", { eAX, Iv }, 0 }, | |
2538 | { "stosB", { Ybr, AL }, 0 }, | |
2539 | { "stosS", { Yvr, eAX }, 0 }, | |
2540 | { "lodsB", { ALr, Xb }, 0 }, | |
2541 | { "lodsS", { eAXr, Xv }, 0 }, | |
2542 | { "scasB", { AL, Yb }, 0 }, | |
2543 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2544 | /* b0 */ |
bf890a93 IT |
2545 | { "movB", { RMAL, Ib }, 0 }, |
2546 | { "movB", { RMCL, Ib }, 0 }, | |
2547 | { "movB", { RMDL, Ib }, 0 }, | |
2548 | { "movB", { RMBL, Ib }, 0 }, | |
2549 | { "movB", { RMAH, Ib }, 0 }, | |
2550 | { "movB", { RMCH, Ib }, 0 }, | |
2551 | { "movB", { RMDH, Ib }, 0 }, | |
2552 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2553 | /* b8 */ |
bf890a93 IT |
2554 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2555 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2556 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2557 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2558 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2559 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2560 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2561 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2562 | /* c0 */ |
1ceb70f8 L |
2563 | { REG_TABLE (REG_C0) }, |
2564 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2565 | { "retT", { Iw, BND }, 0 }, |
2566 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2567 | { X86_64_TABLE (X86_64_C4) }, |
2568 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2569 | { REG_TABLE (REG_C6) }, |
2570 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2571 | /* c8 */ |
bf890a93 IT |
2572 | { "enterT", { Iw, Ib }, 0 }, |
2573 | { "leaveT", { XX }, 0 }, | |
2574 | { "Jret{|f}P", { Iw }, 0 }, | |
2575 | { "Jret{|f}P", { XX }, 0 }, | |
2576 | { "int3", { XX }, 0 }, | |
2577 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2578 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2579 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2580 | /* d0 */ |
1ceb70f8 L |
2581 | { REG_TABLE (REG_D0) }, |
2582 | { REG_TABLE (REG_D1) }, | |
2583 | { REG_TABLE (REG_D2) }, | |
2584 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2585 | { X86_64_TABLE (X86_64_D4) }, |
2586 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2587 | { Bad_Opcode }, |
bf890a93 | 2588 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2589 | /* d8 */ |
2590 | { FLOAT }, | |
2591 | { FLOAT }, | |
2592 | { FLOAT }, | |
2593 | { FLOAT }, | |
2594 | { FLOAT }, | |
2595 | { FLOAT }, | |
2596 | { FLOAT }, | |
2597 | { FLOAT }, | |
2598 | /* e0 */ | |
bf890a93 IT |
2599 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2600 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2601 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2602 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2603 | { "inB", { AL, Ib }, 0 }, | |
2604 | { "inG", { zAX, Ib }, 0 }, | |
2605 | { "outB", { Ib, AL }, 0 }, | |
2606 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2607 | /* e8 */ |
a72d2af2 L |
2608 | { X86_64_TABLE (X86_64_E8) }, |
2609 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2610 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2611 | { "jmp", { Jb, BND }, 0 }, |
2612 | { "inB", { AL, indirDX }, 0 }, | |
2613 | { "inG", { zAX, indirDX }, 0 }, | |
2614 | { "outB", { indirDX, AL }, 0 }, | |
2615 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2616 | /* f0 */ |
592d1631 | 2617 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2618 | { "icebp", { XX }, 0 }, |
592d1631 L |
2619 | { Bad_Opcode }, /* repne */ |
2620 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2621 | { "hlt", { XX }, 0 }, |
2622 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2623 | { REG_TABLE (REG_F6) }, |
2624 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2625 | /* f8 */ |
bf890a93 IT |
2626 | { "clc", { XX }, 0 }, |
2627 | { "stc", { XX }, 0 }, | |
2628 | { "cli", { XX }, 0 }, | |
2629 | { "sti", { XX }, 0 }, | |
2630 | { "cld", { XX }, 0 }, | |
2631 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2632 | { REG_TABLE (REG_FE) }, |
2633 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2634 | }; |
2635 | ||
6439fc28 | 2636 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2637 | /* 00 */ |
1ceb70f8 L |
2638 | { REG_TABLE (REG_0F00 ) }, |
2639 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2640 | { "larS", { Gv, Ew }, 0 }, |
2641 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2642 | { Bad_Opcode }, |
bf890a93 IT |
2643 | { "syscall", { XX }, 0 }, |
2644 | { "clts", { XX }, 0 }, | |
2645 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2646 | /* 08 */ |
bf890a93 | 2647 | { "invd", { XX }, 0 }, |
3233d7d0 | 2648 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2649 | { Bad_Opcode }, |
bf890a93 | 2650 | { "ud2", { XX }, 0 }, |
592d1631 | 2651 | { Bad_Opcode }, |
b5b1fc4f | 2652 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2653 | { "femms", { XX }, 0 }, |
2654 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2655 | /* 10 */ |
1ceb70f8 L |
2656 | { PREFIX_TABLE (PREFIX_0F10) }, |
2657 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2658 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2659 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2660 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2661 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2662 | { PREFIX_TABLE (PREFIX_0F16) }, |
2663 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2664 | /* 18 */ |
1ceb70f8 | 2665 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2666 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2667 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2668 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2669 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2670 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2671 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2672 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2673 | /* 20 */ |
bf890a93 IT |
2674 | { "movZ", { Rm, Cm }, 0 }, |
2675 | { "movZ", { Rm, Dm }, 0 }, | |
2676 | { "movZ", { Cm, Rm }, 0 }, | |
2677 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2678 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2679 | { Bad_Opcode }, |
1ceb70f8 | 2680 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2681 | { Bad_Opcode }, |
252b5132 | 2682 | /* 28 */ |
507bd325 L |
2683 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2684 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2685 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2686 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2687 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2688 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2689 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2690 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2691 | /* 30 */ |
bf890a93 IT |
2692 | { "wrmsr", { XX }, 0 }, |
2693 | { "rdtsc", { XX }, 0 }, | |
2694 | { "rdmsr", { XX }, 0 }, | |
2695 | { "rdpmc", { XX }, 0 }, | |
2696 | { "sysenter", { XX }, 0 }, | |
2697 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2698 | { Bad_Opcode }, |
bf890a93 | 2699 | { "getsec", { XX }, 0 }, |
252b5132 | 2700 | /* 38 */ |
507bd325 | 2701 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2702 | { Bad_Opcode }, |
507bd325 | 2703 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2704 | { Bad_Opcode }, |
2705 | { Bad_Opcode }, | |
2706 | { Bad_Opcode }, | |
2707 | { Bad_Opcode }, | |
2708 | { Bad_Opcode }, | |
252b5132 | 2709 | /* 40 */ |
bf890a93 IT |
2710 | { "cmovoS", { Gv, Ev }, 0 }, |
2711 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2712 | { "cmovbS", { Gv, Ev }, 0 }, | |
2713 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2714 | { "cmoveS", { Gv, Ev }, 0 }, | |
2715 | { "cmovneS", { Gv, Ev }, 0 }, | |
2716 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2717 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2718 | /* 48 */ |
bf890a93 IT |
2719 | { "cmovsS", { Gv, Ev }, 0 }, |
2720 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2721 | { "cmovpS", { Gv, Ev }, 0 }, | |
2722 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2723 | { "cmovlS", { Gv, Ev }, 0 }, | |
2724 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2725 | { "cmovleS", { Gv, Ev }, 0 }, | |
2726 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2727 | /* 50 */ |
75c135a8 | 2728 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2729 | { PREFIX_TABLE (PREFIX_0F51) }, |
2730 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2731 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2732 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2733 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2734 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2735 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2736 | /* 58 */ |
1ceb70f8 L |
2737 | { PREFIX_TABLE (PREFIX_0F58) }, |
2738 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2739 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2740 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2741 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2742 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2743 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2744 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2745 | /* 60 */ |
1ceb70f8 L |
2746 | { PREFIX_TABLE (PREFIX_0F60) }, |
2747 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2748 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2749 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2751 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2752 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2753 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2754 | /* 68 */ |
507bd325 L |
2755 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2756 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2757 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2758 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2759 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2760 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2761 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2762 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2763 | /* 70 */ |
1ceb70f8 L |
2764 | { PREFIX_TABLE (PREFIX_0F70) }, |
2765 | { REG_TABLE (REG_0F71) }, | |
2766 | { REG_TABLE (REG_0F72) }, | |
2767 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2768 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2769 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2770 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2771 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2772 | /* 78 */ |
1ceb70f8 L |
2773 | { PREFIX_TABLE (PREFIX_0F78) }, |
2774 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2775 | { Bad_Opcode }, |
592d1631 | 2776 | { Bad_Opcode }, |
1ceb70f8 L |
2777 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2778 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2779 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2780 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2781 | /* 80 */ |
bf890a93 IT |
2782 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2783 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2784 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2785 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2786 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2787 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2788 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2789 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2790 | /* 88 */ |
bf890a93 IT |
2791 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2792 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2793 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2794 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2795 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2796 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2797 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2798 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2799 | /* 90 */ |
bf890a93 IT |
2800 | { "seto", { Eb }, 0 }, |
2801 | { "setno", { Eb }, 0 }, | |
2802 | { "setb", { Eb }, 0 }, | |
2803 | { "setae", { Eb }, 0 }, | |
2804 | { "sete", { Eb }, 0 }, | |
2805 | { "setne", { Eb }, 0 }, | |
2806 | { "setbe", { Eb }, 0 }, | |
2807 | { "seta", { Eb }, 0 }, | |
252b5132 | 2808 | /* 98 */ |
bf890a93 IT |
2809 | { "sets", { Eb }, 0 }, |
2810 | { "setns", { Eb }, 0 }, | |
2811 | { "setp", { Eb }, 0 }, | |
2812 | { "setnp", { Eb }, 0 }, | |
2813 | { "setl", { Eb }, 0 }, | |
2814 | { "setge", { Eb }, 0 }, | |
2815 | { "setle", { Eb }, 0 }, | |
2816 | { "setg", { Eb }, 0 }, | |
252b5132 | 2817 | /* a0 */ |
bf890a93 IT |
2818 | { "pushT", { fs }, 0 }, |
2819 | { "popT", { fs }, 0 }, | |
2820 | { "cpuid", { XX }, 0 }, | |
2821 | { "btS", { Ev, Gv }, 0 }, | |
2822 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2823 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2824 | { REG_TABLE (REG_0FA6) }, |
2825 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2826 | /* a8 */ |
bf890a93 IT |
2827 | { "pushT", { gs }, 0 }, |
2828 | { "popT", { gs }, 0 }, | |
2829 | { "rsm", { XX }, 0 }, | |
2830 | { "btsS", { Evh1, Gv }, 0 }, | |
2831 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2832 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2833 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2834 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2835 | /* b0 */ |
bf890a93 IT |
2836 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2837 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2838 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2839 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2840 | { MOD_TABLE (MOD_0FB4) }, |
2841 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2842 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2843 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2844 | /* b8 */ |
1ceb70f8 | 2845 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2846 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2847 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2848 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2849 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2850 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2851 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2852 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2853 | /* c0 */ |
bf890a93 IT |
2854 | { "xaddB", { Ebh1, Gb }, 0 }, |
2855 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2856 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2857 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2858 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2859 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2860 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2861 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2862 | /* c8 */ |
bf890a93 IT |
2863 | { "bswap", { RMeAX }, 0 }, |
2864 | { "bswap", { RMeCX }, 0 }, | |
2865 | { "bswap", { RMeDX }, 0 }, | |
2866 | { "bswap", { RMeBX }, 0 }, | |
2867 | { "bswap", { RMeSP }, 0 }, | |
2868 | { "bswap", { RMeBP }, 0 }, | |
2869 | { "bswap", { RMeSI }, 0 }, | |
2870 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2871 | /* d0 */ |
1ceb70f8 | 2872 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2873 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2874 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2876 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2877 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2878 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2879 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2880 | /* d8 */ |
507bd325 L |
2881 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2882 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2886 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2887 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2888 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2889 | /* e0 */ |
507bd325 L |
2890 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2891 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2892 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2893 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2894 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2895 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2896 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2897 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2898 | /* e8 */ |
507bd325 L |
2899 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2900 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2901 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2902 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2903 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2904 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2905 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2906 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2907 | /* f0 */ |
1ceb70f8 | 2908 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2909 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2910 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2911 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2912 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2913 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2914 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2915 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2916 | /* f8 */ |
507bd325 L |
2917 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2918 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2919 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2920 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2921 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2922 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2923 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2924 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2925 | }; |
2926 | ||
2927 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2928 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2929 | /* ------------------------------- */ | |
2930 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2931 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2932 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2933 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2934 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2935 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2936 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2937 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2938 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2939 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2940 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2941 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2942 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2943 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2944 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2945 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2946 | /* ------------------------------- */ | |
2947 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2948 | }; |
2949 | ||
2950 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2951 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2952 | /* ------------------------------- */ | |
252b5132 | 2953 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2954 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2955 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2956 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2957 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2958 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2959 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2960 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2961 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2962 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2963 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2964 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2965 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2966 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2967 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2968 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2969 | /* ------------------------------- */ |
2970 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2971 | }; | |
2972 | ||
252b5132 RH |
2973 | static char obuf[100]; |
2974 | static char *obufp; | |
ea397f5b | 2975 | static char *mnemonicendp; |
252b5132 RH |
2976 | static char scratchbuf[100]; |
2977 | static unsigned char *start_codep; | |
2978 | static unsigned char *insn_codep; | |
2979 | static unsigned char *codep; | |
285ca992 | 2980 | static unsigned char *end_codep; |
f16cd0d5 L |
2981 | static int last_lock_prefix; |
2982 | static int last_repz_prefix; | |
2983 | static int last_repnz_prefix; | |
2984 | static int last_data_prefix; | |
2985 | static int last_addr_prefix; | |
2986 | static int last_rex_prefix; | |
2987 | static int last_seg_prefix; | |
d9949a36 | 2988 | static int fwait_prefix; |
285ca992 L |
2989 | /* The active segment register prefix. */ |
2990 | static int active_seg_prefix; | |
f16cd0d5 L |
2991 | #define MAX_CODE_LENGTH 15 |
2992 | /* We can up to 14 prefixes since the maximum instruction length is | |
2993 | 15bytes. */ | |
2994 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2995 | static disassemble_info *the_info; |
7967e09e L |
2996 | static struct |
2997 | { | |
2998 | int mod; | |
7967e09e | 2999 | int reg; |
484c222e | 3000 | int rm; |
7967e09e L |
3001 | } |
3002 | modrm; | |
4bba6815 | 3003 | static unsigned char need_modrm; |
dfc8cf43 L |
3004 | static struct |
3005 | { | |
3006 | int scale; | |
3007 | int index; | |
3008 | int base; | |
3009 | } | |
3010 | sib; | |
c0f3af97 L |
3011 | static struct |
3012 | { | |
3013 | int register_specifier; | |
3014 | int length; | |
3015 | int prefix; | |
3016 | int w; | |
43234a1e L |
3017 | int evex; |
3018 | int r; | |
3019 | int v; | |
3020 | int mask_register_specifier; | |
3021 | int zeroing; | |
3022 | int ll; | |
3023 | int b; | |
c0f3af97 L |
3024 | } |
3025 | vex; | |
3026 | static unsigned char need_vex; | |
3027 | static unsigned char need_vex_reg; | |
dae39acc | 3028 | static unsigned char vex_w_done; |
252b5132 | 3029 | |
ea397f5b L |
3030 | struct op |
3031 | { | |
3032 | const char *name; | |
3033 | unsigned int len; | |
3034 | }; | |
3035 | ||
4bba6815 AM |
3036 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3037 | values are stale. Hitting this abort likely indicates that you | |
3038 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3039 | #define MODRM_CHECK if (!need_modrm) abort () | |
3040 | ||
d708bcba AM |
3041 | static const char **names64; |
3042 | static const char **names32; | |
3043 | static const char **names16; | |
3044 | static const char **names8; | |
3045 | static const char **names8rex; | |
3046 | static const char **names_seg; | |
db51cc60 L |
3047 | static const char *index64; |
3048 | static const char *index32; | |
d708bcba | 3049 | static const char **index16; |
7e8b059b | 3050 | static const char **names_bnd; |
d708bcba AM |
3051 | |
3052 | static const char *intel_names64[] = { | |
3053 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3054 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3055 | }; | |
3056 | static const char *intel_names32[] = { | |
3057 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3058 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3059 | }; | |
3060 | static const char *intel_names16[] = { | |
3061 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3062 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3063 | }; | |
3064 | static const char *intel_names8[] = { | |
3065 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3066 | }; | |
3067 | static const char *intel_names8rex[] = { | |
3068 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3069 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3070 | }; | |
3071 | static const char *intel_names_seg[] = { | |
3072 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3073 | }; | |
db51cc60 L |
3074 | static const char *intel_index64 = "riz"; |
3075 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3076 | static const char *intel_index16[] = { |
3077 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3078 | }; | |
3079 | ||
3080 | static const char *att_names64[] = { | |
3081 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3082 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3083 | }; | |
d708bcba AM |
3084 | static const char *att_names32[] = { |
3085 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3086 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3087 | }; |
d708bcba AM |
3088 | static const char *att_names16[] = { |
3089 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3090 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3091 | }; |
d708bcba AM |
3092 | static const char *att_names8[] = { |
3093 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3094 | }; |
d708bcba AM |
3095 | static const char *att_names8rex[] = { |
3096 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3097 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3098 | }; | |
d708bcba AM |
3099 | static const char *att_names_seg[] = { |
3100 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3101 | }; |
db51cc60 L |
3102 | static const char *att_index64 = "%riz"; |
3103 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3104 | static const char *att_index16[] = { |
3105 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3106 | }; |
3107 | ||
b9733481 L |
3108 | static const char **names_mm; |
3109 | static const char *intel_names_mm[] = { | |
3110 | "mm0", "mm1", "mm2", "mm3", | |
3111 | "mm4", "mm5", "mm6", "mm7" | |
3112 | }; | |
3113 | static const char *att_names_mm[] = { | |
3114 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3115 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3116 | }; | |
3117 | ||
7e8b059b L |
3118 | static const char *intel_names_bnd[] = { |
3119 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3120 | }; | |
3121 | ||
3122 | static const char *att_names_bnd[] = { | |
3123 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3124 | }; | |
3125 | ||
b9733481 L |
3126 | static const char **names_xmm; |
3127 | static const char *intel_names_xmm[] = { | |
3128 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3129 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3130 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3131 | "xmm12", "xmm13", "xmm14", "xmm15", |
3132 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3133 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3134 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3135 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3136 | }; |
3137 | static const char *att_names_xmm[] = { | |
3138 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3139 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3140 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3141 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3142 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3143 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3144 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3145 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3146 | }; |
3147 | ||
3148 | static const char **names_ymm; | |
3149 | static const char *intel_names_ymm[] = { | |
3150 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3151 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3152 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3153 | "ymm12", "ymm13", "ymm14", "ymm15", |
3154 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3155 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3156 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3157 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3158 | }; |
3159 | static const char *att_names_ymm[] = { | |
3160 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3161 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3162 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3163 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3164 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3165 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3166 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3167 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3168 | }; | |
3169 | ||
3170 | static const char **names_zmm; | |
3171 | static const char *intel_names_zmm[] = { | |
3172 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3173 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3174 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3175 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3176 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3177 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3178 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3179 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3180 | }; | |
3181 | static const char *att_names_zmm[] = { | |
3182 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3183 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3184 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3185 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3186 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3187 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3188 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3189 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3190 | }; | |
3191 | ||
3192 | static const char **names_mask; | |
3193 | static const char *intel_names_mask[] = { | |
3194 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3195 | }; | |
3196 | static const char *att_names_mask[] = { | |
3197 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3198 | }; | |
3199 | ||
3200 | static const char *names_rounding[] = | |
3201 | { | |
3202 | "{rn-sae}", | |
3203 | "{rd-sae}", | |
3204 | "{ru-sae}", | |
3205 | "{rz-sae}" | |
b9733481 L |
3206 | }; |
3207 | ||
1ceb70f8 L |
3208 | static const struct dis386 reg_table[][8] = { |
3209 | /* REG_80 */ | |
252b5132 | 3210 | { |
bf890a93 IT |
3211 | { "addA", { Ebh1, Ib }, 0 }, |
3212 | { "orA", { Ebh1, Ib }, 0 }, | |
3213 | { "adcA", { Ebh1, Ib }, 0 }, | |
3214 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3215 | { "andA", { Ebh1, Ib }, 0 }, | |
3216 | { "subA", { Ebh1, Ib }, 0 }, | |
3217 | { "xorA", { Ebh1, Ib }, 0 }, | |
3218 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3219 | }, |
1ceb70f8 | 3220 | /* REG_81 */ |
252b5132 | 3221 | { |
bf890a93 IT |
3222 | { "addQ", { Evh1, Iv }, 0 }, |
3223 | { "orQ", { Evh1, Iv }, 0 }, | |
3224 | { "adcQ", { Evh1, Iv }, 0 }, | |
3225 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3226 | { "andQ", { Evh1, Iv }, 0 }, | |
3227 | { "subQ", { Evh1, Iv }, 0 }, | |
3228 | { "xorQ", { Evh1, Iv }, 0 }, | |
3229 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3230 | }, |
7148c369 | 3231 | /* REG_83 */ |
252b5132 | 3232 | { |
bf890a93 IT |
3233 | { "addQ", { Evh1, sIb }, 0 }, |
3234 | { "orQ", { Evh1, sIb }, 0 }, | |
3235 | { "adcQ", { Evh1, sIb }, 0 }, | |
3236 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3237 | { "andQ", { Evh1, sIb }, 0 }, | |
3238 | { "subQ", { Evh1, sIb }, 0 }, | |
3239 | { "xorQ", { Evh1, sIb }, 0 }, | |
3240 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3241 | }, |
1ceb70f8 | 3242 | /* REG_8F */ |
4e7d34a6 | 3243 | { |
bf890a93 | 3244 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3245 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3246 | { Bad_Opcode }, |
3247 | { Bad_Opcode }, | |
3248 | { Bad_Opcode }, | |
f88c9eb0 | 3249 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3250 | }, |
1ceb70f8 | 3251 | /* REG_C0 */ |
252b5132 | 3252 | { |
bf890a93 IT |
3253 | { "rolA", { Eb, Ib }, 0 }, |
3254 | { "rorA", { Eb, Ib }, 0 }, | |
3255 | { "rclA", { Eb, Ib }, 0 }, | |
3256 | { "rcrA", { Eb, Ib }, 0 }, | |
3257 | { "shlA", { Eb, Ib }, 0 }, | |
3258 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3259 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3260 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3261 | }, |
1ceb70f8 | 3262 | /* REG_C1 */ |
252b5132 | 3263 | { |
bf890a93 IT |
3264 | { "rolQ", { Ev, Ib }, 0 }, |
3265 | { "rorQ", { Ev, Ib }, 0 }, | |
3266 | { "rclQ", { Ev, Ib }, 0 }, | |
3267 | { "rcrQ", { Ev, Ib }, 0 }, | |
3268 | { "shlQ", { Ev, Ib }, 0 }, | |
3269 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3270 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3271 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3272 | }, |
1ceb70f8 | 3273 | /* REG_C6 */ |
4e7d34a6 | 3274 | { |
bf890a93 | 3275 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3276 | { Bad_Opcode }, |
3277 | { Bad_Opcode }, | |
3278 | { Bad_Opcode }, | |
3279 | { Bad_Opcode }, | |
3280 | { Bad_Opcode }, | |
3281 | { Bad_Opcode }, | |
3282 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3283 | }, |
1ceb70f8 | 3284 | /* REG_C7 */ |
4e7d34a6 | 3285 | { |
bf890a93 | 3286 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3287 | { Bad_Opcode }, |
3288 | { Bad_Opcode }, | |
3289 | { Bad_Opcode }, | |
3290 | { Bad_Opcode }, | |
3291 | { Bad_Opcode }, | |
3292 | { Bad_Opcode }, | |
3293 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3294 | }, |
1ceb70f8 | 3295 | /* REG_D0 */ |
252b5132 | 3296 | { |
bf890a93 IT |
3297 | { "rolA", { Eb, I1 }, 0 }, |
3298 | { "rorA", { Eb, I1 }, 0 }, | |
3299 | { "rclA", { Eb, I1 }, 0 }, | |
3300 | { "rcrA", { Eb, I1 }, 0 }, | |
3301 | { "shlA", { Eb, I1 }, 0 }, | |
3302 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3303 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3304 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3305 | }, |
1ceb70f8 | 3306 | /* REG_D1 */ |
252b5132 | 3307 | { |
bf890a93 IT |
3308 | { "rolQ", { Ev, I1 }, 0 }, |
3309 | { "rorQ", { Ev, I1 }, 0 }, | |
3310 | { "rclQ", { Ev, I1 }, 0 }, | |
3311 | { "rcrQ", { Ev, I1 }, 0 }, | |
3312 | { "shlQ", { Ev, I1 }, 0 }, | |
3313 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3314 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3315 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3316 | }, |
1ceb70f8 | 3317 | /* REG_D2 */ |
252b5132 | 3318 | { |
bf890a93 IT |
3319 | { "rolA", { Eb, CL }, 0 }, |
3320 | { "rorA", { Eb, CL }, 0 }, | |
3321 | { "rclA", { Eb, CL }, 0 }, | |
3322 | { "rcrA", { Eb, CL }, 0 }, | |
3323 | { "shlA", { Eb, CL }, 0 }, | |
3324 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3325 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3326 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3327 | }, |
1ceb70f8 | 3328 | /* REG_D3 */ |
252b5132 | 3329 | { |
bf890a93 IT |
3330 | { "rolQ", { Ev, CL }, 0 }, |
3331 | { "rorQ", { Ev, CL }, 0 }, | |
3332 | { "rclQ", { Ev, CL }, 0 }, | |
3333 | { "rcrQ", { Ev, CL }, 0 }, | |
3334 | { "shlQ", { Ev, CL }, 0 }, | |
3335 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3336 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3337 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3338 | }, |
1ceb70f8 | 3339 | /* REG_F6 */ |
252b5132 | 3340 | { |
bf890a93 | 3341 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3342 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3343 | { "notA", { Ebh1 }, 0 }, |
3344 | { "negA", { Ebh1 }, 0 }, | |
3345 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3346 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3347 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3348 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3349 | }, |
1ceb70f8 | 3350 | /* REG_F7 */ |
252b5132 | 3351 | { |
bf890a93 | 3352 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3353 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3354 | { "notQ", { Evh1 }, 0 }, |
3355 | { "negQ", { Evh1 }, 0 }, | |
3356 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3357 | { "imulQ", { Ev }, 0 }, | |
3358 | { "divQ", { Ev }, 0 }, | |
3359 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3360 | }, |
1ceb70f8 | 3361 | /* REG_FE */ |
252b5132 | 3362 | { |
bf890a93 IT |
3363 | { "incA", { Ebh1 }, 0 }, |
3364 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3365 | }, |
1ceb70f8 | 3366 | /* REG_FF */ |
252b5132 | 3367 | { |
bf890a93 IT |
3368 | { "incQ", { Evh1 }, 0 }, |
3369 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3370 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3371 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3372 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3373 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3374 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3375 | { Bad_Opcode }, |
252b5132 | 3376 | }, |
1ceb70f8 | 3377 | /* REG_0F00 */ |
252b5132 | 3378 | { |
bf890a93 IT |
3379 | { "sldtD", { Sv }, 0 }, |
3380 | { "strD", { Sv }, 0 }, | |
3381 | { "lldt", { Ew }, 0 }, | |
3382 | { "ltr", { Ew }, 0 }, | |
3383 | { "verr", { Ew }, 0 }, | |
3384 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3385 | { Bad_Opcode }, |
3386 | { Bad_Opcode }, | |
252b5132 | 3387 | }, |
1ceb70f8 | 3388 | /* REG_0F01 */ |
252b5132 | 3389 | { |
1ceb70f8 L |
3390 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3391 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3392 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3393 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3394 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3395 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3396 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3397 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3398 | }, |
b5b1fc4f | 3399 | /* REG_0F0D */ |
252b5132 | 3400 | { |
bf890a93 IT |
3401 | { "prefetch", { Mb }, 0 }, |
3402 | { "prefetchw", { Mb }, 0 }, | |
3403 | { "prefetchwt1", { Mb }, 0 }, | |
3404 | { "prefetch", { Mb }, 0 }, | |
3405 | { "prefetch", { Mb }, 0 }, | |
3406 | { "prefetch", { Mb }, 0 }, | |
3407 | { "prefetch", { Mb }, 0 }, | |
3408 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3409 | }, |
1ceb70f8 | 3410 | /* REG_0F18 */ |
252b5132 | 3411 | { |
1ceb70f8 L |
3412 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3413 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3414 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3415 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3416 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3417 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3418 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3419 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3420 | }, |
c48935d7 IT |
3421 | /* REG_0F1C_MOD_0 */ |
3422 | { | |
3423 | { "cldemote", { Mb }, 0 }, | |
3424 | { "nopQ", { Ev }, 0 }, | |
3425 | { "nopQ", { Ev }, 0 }, | |
3426 | { "nopQ", { Ev }, 0 }, | |
3427 | { "nopQ", { Ev }, 0 }, | |
3428 | { "nopQ", { Ev }, 0 }, | |
3429 | { "nopQ", { Ev }, 0 }, | |
3430 | { "nopQ", { Ev }, 0 }, | |
3431 | }, | |
603555e5 L |
3432 | /* REG_0F1E_MOD_3 */ |
3433 | { | |
3434 | { "nopQ", { Ev }, 0 }, | |
3435 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3436 | { "nopQ", { Ev }, 0 }, | |
3437 | { "nopQ", { Ev }, 0 }, | |
3438 | { "nopQ", { Ev }, 0 }, | |
3439 | { "nopQ", { Ev }, 0 }, | |
3440 | { "nopQ", { Ev }, 0 }, | |
3441 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3442 | }, | |
1ceb70f8 | 3443 | /* REG_0F71 */ |
a6bd098c | 3444 | { |
592d1631 L |
3445 | { Bad_Opcode }, |
3446 | { Bad_Opcode }, | |
1ceb70f8 | 3447 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3448 | { Bad_Opcode }, |
1ceb70f8 | 3449 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3450 | { Bad_Opcode }, |
1ceb70f8 | 3451 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3452 | }, |
1ceb70f8 | 3453 | /* REG_0F72 */ |
a6bd098c | 3454 | { |
592d1631 L |
3455 | { Bad_Opcode }, |
3456 | { Bad_Opcode }, | |
1ceb70f8 | 3457 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3458 | { Bad_Opcode }, |
1ceb70f8 | 3459 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3460 | { Bad_Opcode }, |
1ceb70f8 | 3461 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3462 | }, |
1ceb70f8 | 3463 | /* REG_0F73 */ |
252b5132 | 3464 | { |
592d1631 L |
3465 | { Bad_Opcode }, |
3466 | { Bad_Opcode }, | |
1ceb70f8 L |
3467 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3468 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3469 | { Bad_Opcode }, |
3470 | { Bad_Opcode }, | |
1ceb70f8 L |
3471 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3472 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3473 | }, |
1ceb70f8 | 3474 | /* REG_0FA6 */ |
252b5132 | 3475 | { |
bf890a93 IT |
3476 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3477 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3478 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3479 | }, |
1ceb70f8 | 3480 | /* REG_0FA7 */ |
4e7d34a6 | 3481 | { |
bf890a93 IT |
3482 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3483 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3484 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3485 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3486 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3487 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3488 | }, |
1ceb70f8 | 3489 | /* REG_0FAE */ |
4e7d34a6 | 3490 | { |
1ceb70f8 L |
3491 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3492 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3493 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3494 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3495 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3496 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3497 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3498 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3499 | }, |
1ceb70f8 | 3500 | /* REG_0FBA */ |
252b5132 | 3501 | { |
592d1631 L |
3502 | { Bad_Opcode }, |
3503 | { Bad_Opcode }, | |
3504 | { Bad_Opcode }, | |
3505 | { Bad_Opcode }, | |
bf890a93 IT |
3506 | { "btQ", { Ev, Ib }, 0 }, |
3507 | { "btsQ", { Evh1, Ib }, 0 }, | |
3508 | { "btrQ", { Evh1, Ib }, 0 }, | |
3509 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3510 | }, |
1ceb70f8 | 3511 | /* REG_0FC7 */ |
c608c12e | 3512 | { |
592d1631 | 3513 | { Bad_Opcode }, |
bf890a93 | 3514 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3515 | { Bad_Opcode }, |
963f3586 IT |
3516 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3517 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3518 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3519 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3520 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3521 | }, |
592a252b | 3522 | /* REG_VEX_0F71 */ |
c0f3af97 | 3523 | { |
592d1631 L |
3524 | { Bad_Opcode }, |
3525 | { Bad_Opcode }, | |
592a252b | 3526 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3527 | { Bad_Opcode }, |
592a252b | 3528 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3529 | { Bad_Opcode }, |
592a252b | 3530 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3531 | }, |
592a252b | 3532 | /* REG_VEX_0F72 */ |
c0f3af97 | 3533 | { |
592d1631 L |
3534 | { Bad_Opcode }, |
3535 | { Bad_Opcode }, | |
592a252b | 3536 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3537 | { Bad_Opcode }, |
592a252b | 3538 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3539 | { Bad_Opcode }, |
592a252b | 3540 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3541 | }, |
592a252b | 3542 | /* REG_VEX_0F73 */ |
c0f3af97 | 3543 | { |
592d1631 L |
3544 | { Bad_Opcode }, |
3545 | { Bad_Opcode }, | |
592a252b L |
3546 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3547 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3548 | { Bad_Opcode }, |
3549 | { Bad_Opcode }, | |
592a252b L |
3550 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3551 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3552 | }, |
592a252b | 3553 | /* REG_VEX_0FAE */ |
c0f3af97 | 3554 | { |
592d1631 L |
3555 | { Bad_Opcode }, |
3556 | { Bad_Opcode }, | |
592a252b L |
3557 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3558 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3559 | }, |
f12dc422 L |
3560 | /* REG_VEX_0F38F3 */ |
3561 | { | |
3562 | { Bad_Opcode }, | |
3563 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3564 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3565 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3566 | }, | |
f88c9eb0 SP |
3567 | /* REG_XOP_LWPCB */ |
3568 | { | |
bf890a93 IT |
3569 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3570 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3571 | }, |
3572 | /* REG_XOP_LWP */ | |
3573 | { | |
bf890a93 IT |
3574 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3575 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3576 | }, |
2a2a0f38 QN |
3577 | /* REG_XOP_TBM_01 */ |
3578 | { | |
3579 | { Bad_Opcode }, | |
bf890a93 IT |
3580 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3581 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3582 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3583 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3584 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3585 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3586 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3587 | }, |
3588 | /* REG_XOP_TBM_02 */ | |
3589 | { | |
3590 | { Bad_Opcode }, | |
bf890a93 | 3591 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3592 | { Bad_Opcode }, |
3593 | { Bad_Opcode }, | |
3594 | { Bad_Opcode }, | |
3595 | { Bad_Opcode }, | |
bf890a93 | 3596 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3597 | }, |
43234a1e L |
3598 | #define NEED_REG_TABLE |
3599 | #include "i386-dis-evex.h" | |
3600 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3601 | }; |
3602 | ||
1ceb70f8 L |
3603 | static const struct dis386 prefix_table[][4] = { |
3604 | /* PREFIX_90 */ | |
252b5132 | 3605 | { |
bf890a93 IT |
3606 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3607 | { "pause", { XX }, 0 }, | |
3608 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3609 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3610 | }, |
4e7d34a6 | 3611 | |
603555e5 L |
3612 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3613 | { | |
3614 | { Bad_Opcode }, | |
3615 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3616 | }, | |
3617 | ||
2234eee6 | 3618 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3619 | { |
3620 | { Bad_Opcode }, | |
2234eee6 | 3621 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3622 | }, |
3623 | ||
3624 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3625 | { | |
3626 | { Bad_Opcode }, | |
c2f76402 | 3627 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3628 | }, |
3629 | ||
3233d7d0 IT |
3630 | /* PREFIX_0F09 */ |
3631 | { | |
3632 | { "wbinvd", { XX }, 0 }, | |
3633 | { "wbnoinvd", { XX }, 0 }, | |
3634 | }, | |
3635 | ||
1ceb70f8 | 3636 | /* PREFIX_0F10 */ |
cc0ec051 | 3637 | { |
507bd325 L |
3638 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3639 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3640 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3641 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3642 | }, |
4e7d34a6 | 3643 | |
1ceb70f8 | 3644 | /* PREFIX_0F11 */ |
30d1c836 | 3645 | { |
507bd325 L |
3646 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3647 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3648 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3649 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3650 | }, |
252b5132 | 3651 | |
1ceb70f8 | 3652 | /* PREFIX_0F12 */ |
c608c12e | 3653 | { |
1ceb70f8 | 3654 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3655 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3656 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3657 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3658 | }, |
4e7d34a6 | 3659 | |
1ceb70f8 | 3660 | /* PREFIX_0F16 */ |
c608c12e | 3661 | { |
1ceb70f8 | 3662 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3663 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3664 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3665 | }, |
4e7d34a6 | 3666 | |
7e8b059b L |
3667 | /* PREFIX_0F1A */ |
3668 | { | |
3669 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3670 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3671 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3672 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3673 | }, |
3674 | ||
3675 | /* PREFIX_0F1B */ | |
3676 | { | |
3677 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3678 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3679 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3680 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3681 | }, |
3682 | ||
c48935d7 IT |
3683 | /* PREFIX_0F1C */ |
3684 | { | |
3685 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3686 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3687 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3688 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3689 | }, | |
3690 | ||
603555e5 L |
3691 | /* PREFIX_0F1E */ |
3692 | { | |
3693 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3694 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3695 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3696 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3697 | }, | |
3698 | ||
1ceb70f8 | 3699 | /* PREFIX_0F2A */ |
c608c12e | 3700 | { |
507bd325 L |
3701 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3702 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3703 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3704 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3705 | }, |
4e7d34a6 | 3706 | |
1ceb70f8 | 3707 | /* PREFIX_0F2B */ |
c608c12e | 3708 | { |
75c135a8 L |
3709 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3710 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3711 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3712 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3713 | }, |
4e7d34a6 | 3714 | |
1ceb70f8 | 3715 | /* PREFIX_0F2C */ |
c608c12e | 3716 | { |
507bd325 | 3717 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3718 | { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3719 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3720 | { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3721 | }, |
4e7d34a6 | 3722 | |
1ceb70f8 | 3723 | /* PREFIX_0F2D */ |
c608c12e | 3724 | { |
507bd325 | 3725 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3726 | { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3727 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3728 | { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3729 | }, |
4e7d34a6 | 3730 | |
1ceb70f8 | 3731 | /* PREFIX_0F2E */ |
c608c12e | 3732 | { |
bf890a93 | 3733 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3734 | { Bad_Opcode }, |
bf890a93 | 3735 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3736 | }, |
4e7d34a6 | 3737 | |
1ceb70f8 | 3738 | /* PREFIX_0F2F */ |
c608c12e | 3739 | { |
bf890a93 | 3740 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3741 | { Bad_Opcode }, |
bf890a93 | 3742 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3743 | }, |
4e7d34a6 | 3744 | |
1ceb70f8 | 3745 | /* PREFIX_0F51 */ |
c608c12e | 3746 | { |
507bd325 L |
3747 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3748 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3749 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3750 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3751 | }, |
4e7d34a6 | 3752 | |
1ceb70f8 | 3753 | /* PREFIX_0F52 */ |
c608c12e | 3754 | { |
507bd325 L |
3755 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3756 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3757 | }, |
4e7d34a6 | 3758 | |
1ceb70f8 | 3759 | /* PREFIX_0F53 */ |
c608c12e | 3760 | { |
507bd325 L |
3761 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3762 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3763 | }, |
4e7d34a6 | 3764 | |
1ceb70f8 | 3765 | /* PREFIX_0F58 */ |
c608c12e | 3766 | { |
507bd325 L |
3767 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3768 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3769 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3770 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3771 | }, |
4e7d34a6 | 3772 | |
1ceb70f8 | 3773 | /* PREFIX_0F59 */ |
c608c12e | 3774 | { |
507bd325 L |
3775 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3776 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3777 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3778 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3779 | }, |
4e7d34a6 | 3780 | |
1ceb70f8 | 3781 | /* PREFIX_0F5A */ |
041bd2e0 | 3782 | { |
507bd325 L |
3783 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3784 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3785 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3786 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3787 | }, |
4e7d34a6 | 3788 | |
1ceb70f8 | 3789 | /* PREFIX_0F5B */ |
041bd2e0 | 3790 | { |
507bd325 L |
3791 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3792 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3793 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3794 | }, |
4e7d34a6 | 3795 | |
1ceb70f8 | 3796 | /* PREFIX_0F5C */ |
041bd2e0 | 3797 | { |
507bd325 L |
3798 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3799 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3800 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3801 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3802 | }, |
4e7d34a6 | 3803 | |
1ceb70f8 | 3804 | /* PREFIX_0F5D */ |
041bd2e0 | 3805 | { |
507bd325 L |
3806 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3807 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3808 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3809 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3810 | }, |
4e7d34a6 | 3811 | |
1ceb70f8 | 3812 | /* PREFIX_0F5E */ |
041bd2e0 | 3813 | { |
507bd325 L |
3814 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3815 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3816 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3817 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3818 | }, |
4e7d34a6 | 3819 | |
1ceb70f8 | 3820 | /* PREFIX_0F5F */ |
041bd2e0 | 3821 | { |
507bd325 L |
3822 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3823 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3824 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3825 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3826 | }, |
4e7d34a6 | 3827 | |
1ceb70f8 | 3828 | /* PREFIX_0F60 */ |
041bd2e0 | 3829 | { |
507bd325 | 3830 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3831 | { Bad_Opcode }, |
507bd325 | 3832 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3833 | }, |
4e7d34a6 | 3834 | |
1ceb70f8 | 3835 | /* PREFIX_0F61 */ |
041bd2e0 | 3836 | { |
507bd325 | 3837 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3838 | { Bad_Opcode }, |
507bd325 | 3839 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3840 | }, |
4e7d34a6 | 3841 | |
1ceb70f8 | 3842 | /* PREFIX_0F62 */ |
041bd2e0 | 3843 | { |
507bd325 | 3844 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3845 | { Bad_Opcode }, |
507bd325 | 3846 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3847 | }, |
4e7d34a6 | 3848 | |
1ceb70f8 | 3849 | /* PREFIX_0F6C */ |
041bd2e0 | 3850 | { |
592d1631 L |
3851 | { Bad_Opcode }, |
3852 | { Bad_Opcode }, | |
507bd325 | 3853 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3854 | }, |
4e7d34a6 | 3855 | |
1ceb70f8 | 3856 | /* PREFIX_0F6D */ |
0f17484f | 3857 | { |
592d1631 L |
3858 | { Bad_Opcode }, |
3859 | { Bad_Opcode }, | |
507bd325 | 3860 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3861 | }, |
4e7d34a6 | 3862 | |
1ceb70f8 | 3863 | /* PREFIX_0F6F */ |
ca164297 | 3864 | { |
507bd325 L |
3865 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3866 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3867 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3868 | }, |
4e7d34a6 | 3869 | |
1ceb70f8 | 3870 | /* PREFIX_0F70 */ |
4e7d34a6 | 3871 | { |
507bd325 L |
3872 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3873 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3874 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3875 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3876 | }, |
3877 | ||
92fddf8e L |
3878 | /* PREFIX_0F73_REG_3 */ |
3879 | { | |
592d1631 L |
3880 | { Bad_Opcode }, |
3881 | { Bad_Opcode }, | |
bf890a93 | 3882 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3883 | }, |
3884 | ||
3885 | /* PREFIX_0F73_REG_7 */ | |
3886 | { | |
592d1631 L |
3887 | { Bad_Opcode }, |
3888 | { Bad_Opcode }, | |
bf890a93 | 3889 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3890 | }, |
3891 | ||
1ceb70f8 | 3892 | /* PREFIX_0F78 */ |
4e7d34a6 | 3893 | { |
bf890a93 | 3894 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3895 | { Bad_Opcode }, |
bf890a93 IT |
3896 | {"extrq", { XS, Ib, Ib }, 0 }, |
3897 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3898 | }, |
3899 | ||
1ceb70f8 | 3900 | /* PREFIX_0F79 */ |
4e7d34a6 | 3901 | { |
bf890a93 | 3902 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3903 | { Bad_Opcode }, |
bf890a93 IT |
3904 | {"extrq", { XM, XS }, 0 }, |
3905 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3906 | }, |
3907 | ||
1ceb70f8 | 3908 | /* PREFIX_0F7C */ |
ca164297 | 3909 | { |
592d1631 L |
3910 | { Bad_Opcode }, |
3911 | { Bad_Opcode }, | |
507bd325 L |
3912 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3913 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3914 | }, |
4e7d34a6 | 3915 | |
1ceb70f8 | 3916 | /* PREFIX_0F7D */ |
ca164297 | 3917 | { |
592d1631 L |
3918 | { Bad_Opcode }, |
3919 | { Bad_Opcode }, | |
507bd325 L |
3920 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3921 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3922 | }, |
4e7d34a6 | 3923 | |
1ceb70f8 | 3924 | /* PREFIX_0F7E */ |
ca164297 | 3925 | { |
507bd325 L |
3926 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3927 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3928 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3929 | }, |
4e7d34a6 | 3930 | |
1ceb70f8 | 3931 | /* PREFIX_0F7F */ |
ca164297 | 3932 | { |
507bd325 L |
3933 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3934 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3935 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3936 | }, |
4e7d34a6 | 3937 | |
c7b8aa3a L |
3938 | /* PREFIX_0FAE_REG_0 */ |
3939 | { | |
3940 | { Bad_Opcode }, | |
bf890a93 | 3941 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3942 | }, |
3943 | ||
3944 | /* PREFIX_0FAE_REG_1 */ | |
3945 | { | |
3946 | { Bad_Opcode }, | |
bf890a93 | 3947 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3948 | }, |
3949 | ||
3950 | /* PREFIX_0FAE_REG_2 */ | |
3951 | { | |
3952 | { Bad_Opcode }, | |
bf890a93 | 3953 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3954 | }, |
3955 | ||
3956 | /* PREFIX_0FAE_REG_3 */ | |
3957 | { | |
3958 | { Bad_Opcode }, | |
bf890a93 | 3959 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3960 | }, |
3961 | ||
6b40c462 L |
3962 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
3963 | { | |
3964 | { "xsave", { FXSAVE }, 0 }, | |
3965 | { "ptwrite%LQ", { Edq }, 0 }, | |
3966 | }, | |
3967 | ||
3968 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
3969 | { | |
3970 | { Bad_Opcode }, | |
3971 | { "ptwrite%LQ", { Edq }, 0 }, | |
3972 | }, | |
3973 | ||
603555e5 L |
3974 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
3975 | { | |
3976 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3977 | }, |
3978 | ||
3979 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
3980 | { | |
3981 | { "lfence", { Skip_MODRM }, 0 }, | |
3982 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3983 | }, |
3984 | ||
de89d0a3 | 3985 | /* PREFIX_MOD_0_0FAE_REG_6 */ |
c5e7287a | 3986 | { |
603555e5 L |
3987 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3988 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3989 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3990 | }, |
3991 | ||
de89d0a3 IT |
3992 | /* PREFIX_MOD_1_0FAE_REG_6 */ |
3993 | { | |
3994 | { RM_TABLE (RM_0FAE_REG_6) }, | |
3995 | { "umonitor", { Eva }, PREFIX_OPCODE }, | |
ae1d3843 L |
3996 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3997 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3998 | }, |
3999 | ||
963f3586 IT |
4000 | /* PREFIX_0FAE_REG_7 */ |
4001 | { | |
bf890a93 | 4002 | { "clflush", { Mb }, 0 }, |
963f3586 | 4003 | { Bad_Opcode }, |
bf890a93 | 4004 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4005 | }, |
4006 | ||
1ceb70f8 | 4007 | /* PREFIX_0FB8 */ |
ca164297 | 4008 | { |
592d1631 | 4009 | { Bad_Opcode }, |
bf890a93 | 4010 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4011 | }, |
4e7d34a6 | 4012 | |
f12dc422 L |
4013 | /* PREFIX_0FBC */ |
4014 | { | |
bf890a93 IT |
4015 | { "bsfS", { Gv, Ev }, 0 }, |
4016 | { "tzcntS", { Gv, Ev }, 0 }, | |
4017 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4018 | }, |
4019 | ||
1ceb70f8 | 4020 | /* PREFIX_0FBD */ |
050dfa73 | 4021 | { |
bf890a93 IT |
4022 | { "bsrS", { Gv, Ev }, 0 }, |
4023 | { "lzcntS", { Gv, Ev }, 0 }, | |
4024 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4025 | }, |
4026 | ||
1ceb70f8 | 4027 | /* PREFIX_0FC2 */ |
050dfa73 | 4028 | { |
507bd325 L |
4029 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4030 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4031 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4032 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4033 | }, |
246c51aa | 4034 | |
a8484f96 | 4035 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4036 | { |
a8484f96 | 4037 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4038 | }, |
4039 | ||
f24bcbaa | 4040 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4041 | { |
bf890a93 IT |
4042 | { "vmptrld",{ Mq }, 0 }, |
4043 | { "vmxon", { Mq }, 0 }, | |
4044 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4045 | }, |
4046 | ||
f24bcbaa L |
4047 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4048 | { | |
4049 | { "rdrand", { Ev }, 0 }, | |
4050 | { Bad_Opcode }, | |
4051 | { "rdrand", { Ev }, 0 } | |
4052 | }, | |
4053 | ||
4054 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4055 | { | |
4056 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4057 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4058 | { "rdseed", { Ev }, 0 }, |
4059 | }, | |
4060 | ||
1ceb70f8 | 4061 | /* PREFIX_0FD0 */ |
050dfa73 | 4062 | { |
592d1631 L |
4063 | { Bad_Opcode }, |
4064 | { Bad_Opcode }, | |
bf890a93 IT |
4065 | { "addsubpd", { XM, EXx }, 0 }, |
4066 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4067 | }, |
050dfa73 | 4068 | |
1ceb70f8 | 4069 | /* PREFIX_0FD6 */ |
050dfa73 | 4070 | { |
592d1631 | 4071 | { Bad_Opcode }, |
bf890a93 IT |
4072 | { "movq2dq",{ XM, MS }, 0 }, |
4073 | { "movq", { EXqS, XM }, 0 }, | |
4074 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4075 | }, |
4076 | ||
1ceb70f8 | 4077 | /* PREFIX_0FE6 */ |
7918206c | 4078 | { |
592d1631 | 4079 | { Bad_Opcode }, |
507bd325 L |
4080 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4081 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4082 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4083 | }, |
8b38ad71 | 4084 | |
1ceb70f8 | 4085 | /* PREFIX_0FE7 */ |
8b38ad71 | 4086 | { |
507bd325 | 4087 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4088 | { Bad_Opcode }, |
75c135a8 | 4089 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4090 | }, |
4091 | ||
1ceb70f8 | 4092 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4093 | { |
592d1631 L |
4094 | { Bad_Opcode }, |
4095 | { Bad_Opcode }, | |
4096 | { Bad_Opcode }, | |
1ceb70f8 | 4097 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4098 | }, |
4099 | ||
1ceb70f8 | 4100 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4101 | { |
507bd325 | 4102 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4103 | { Bad_Opcode }, |
507bd325 | 4104 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4105 | }, |
42903f7f | 4106 | |
1ceb70f8 | 4107 | /* PREFIX_0F3810 */ |
42903f7f | 4108 | { |
592d1631 L |
4109 | { Bad_Opcode }, |
4110 | { Bad_Opcode }, | |
507bd325 | 4111 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4112 | }, |
4113 | ||
1ceb70f8 | 4114 | /* PREFIX_0F3814 */ |
42903f7f | 4115 | { |
592d1631 L |
4116 | { Bad_Opcode }, |
4117 | { Bad_Opcode }, | |
507bd325 | 4118 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4119 | }, |
4120 | ||
1ceb70f8 | 4121 | /* PREFIX_0F3815 */ |
42903f7f | 4122 | { |
592d1631 L |
4123 | { Bad_Opcode }, |
4124 | { Bad_Opcode }, | |
507bd325 | 4125 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4126 | }, |
4127 | ||
1ceb70f8 | 4128 | /* PREFIX_0F3817 */ |
42903f7f | 4129 | { |
592d1631 L |
4130 | { Bad_Opcode }, |
4131 | { Bad_Opcode }, | |
507bd325 | 4132 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4133 | }, |
4134 | ||
1ceb70f8 | 4135 | /* PREFIX_0F3820 */ |
42903f7f | 4136 | { |
592d1631 L |
4137 | { Bad_Opcode }, |
4138 | { Bad_Opcode }, | |
507bd325 | 4139 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4140 | }, |
4141 | ||
1ceb70f8 | 4142 | /* PREFIX_0F3821 */ |
42903f7f | 4143 | { |
592d1631 L |
4144 | { Bad_Opcode }, |
4145 | { Bad_Opcode }, | |
507bd325 | 4146 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4147 | }, |
4148 | ||
1ceb70f8 | 4149 | /* PREFIX_0F3822 */ |
42903f7f | 4150 | { |
592d1631 L |
4151 | { Bad_Opcode }, |
4152 | { Bad_Opcode }, | |
507bd325 | 4153 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4154 | }, |
4155 | ||
1ceb70f8 | 4156 | /* PREFIX_0F3823 */ |
42903f7f | 4157 | { |
592d1631 L |
4158 | { Bad_Opcode }, |
4159 | { Bad_Opcode }, | |
507bd325 | 4160 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4161 | }, |
4162 | ||
1ceb70f8 | 4163 | /* PREFIX_0F3824 */ |
42903f7f | 4164 | { |
592d1631 L |
4165 | { Bad_Opcode }, |
4166 | { Bad_Opcode }, | |
507bd325 | 4167 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4168 | }, |
4169 | ||
1ceb70f8 | 4170 | /* PREFIX_0F3825 */ |
42903f7f | 4171 | { |
592d1631 L |
4172 | { Bad_Opcode }, |
4173 | { Bad_Opcode }, | |
507bd325 | 4174 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4175 | }, |
4176 | ||
1ceb70f8 | 4177 | /* PREFIX_0F3828 */ |
42903f7f | 4178 | { |
592d1631 L |
4179 | { Bad_Opcode }, |
4180 | { Bad_Opcode }, | |
507bd325 | 4181 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4182 | }, |
4183 | ||
1ceb70f8 | 4184 | /* PREFIX_0F3829 */ |
42903f7f | 4185 | { |
592d1631 L |
4186 | { Bad_Opcode }, |
4187 | { Bad_Opcode }, | |
507bd325 | 4188 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4189 | }, |
4190 | ||
1ceb70f8 | 4191 | /* PREFIX_0F382A */ |
42903f7f | 4192 | { |
592d1631 L |
4193 | { Bad_Opcode }, |
4194 | { Bad_Opcode }, | |
75c135a8 | 4195 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4196 | }, |
4197 | ||
1ceb70f8 | 4198 | /* PREFIX_0F382B */ |
42903f7f | 4199 | { |
592d1631 L |
4200 | { Bad_Opcode }, |
4201 | { Bad_Opcode }, | |
507bd325 | 4202 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4203 | }, |
4204 | ||
1ceb70f8 | 4205 | /* PREFIX_0F3830 */ |
42903f7f | 4206 | { |
592d1631 L |
4207 | { Bad_Opcode }, |
4208 | { Bad_Opcode }, | |
507bd325 | 4209 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4210 | }, |
4211 | ||
1ceb70f8 | 4212 | /* PREFIX_0F3831 */ |
42903f7f | 4213 | { |
592d1631 L |
4214 | { Bad_Opcode }, |
4215 | { Bad_Opcode }, | |
507bd325 | 4216 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4217 | }, |
4218 | ||
1ceb70f8 | 4219 | /* PREFIX_0F3832 */ |
42903f7f | 4220 | { |
592d1631 L |
4221 | { Bad_Opcode }, |
4222 | { Bad_Opcode }, | |
507bd325 | 4223 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4224 | }, |
4225 | ||
1ceb70f8 | 4226 | /* PREFIX_0F3833 */ |
42903f7f | 4227 | { |
592d1631 L |
4228 | { Bad_Opcode }, |
4229 | { Bad_Opcode }, | |
507bd325 | 4230 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4231 | }, |
4232 | ||
1ceb70f8 | 4233 | /* PREFIX_0F3834 */ |
42903f7f | 4234 | { |
592d1631 L |
4235 | { Bad_Opcode }, |
4236 | { Bad_Opcode }, | |
507bd325 | 4237 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4238 | }, |
4239 | ||
1ceb70f8 | 4240 | /* PREFIX_0F3835 */ |
42903f7f | 4241 | { |
592d1631 L |
4242 | { Bad_Opcode }, |
4243 | { Bad_Opcode }, | |
507bd325 | 4244 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4245 | }, |
4246 | ||
1ceb70f8 | 4247 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4248 | { |
592d1631 L |
4249 | { Bad_Opcode }, |
4250 | { Bad_Opcode }, | |
507bd325 | 4251 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4252 | }, |
4253 | ||
1ceb70f8 | 4254 | /* PREFIX_0F3838 */ |
42903f7f | 4255 | { |
592d1631 L |
4256 | { Bad_Opcode }, |
4257 | { Bad_Opcode }, | |
507bd325 | 4258 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4259 | }, |
4260 | ||
1ceb70f8 | 4261 | /* PREFIX_0F3839 */ |
42903f7f | 4262 | { |
592d1631 L |
4263 | { Bad_Opcode }, |
4264 | { Bad_Opcode }, | |
507bd325 | 4265 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4266 | }, |
4267 | ||
1ceb70f8 | 4268 | /* PREFIX_0F383A */ |
42903f7f | 4269 | { |
592d1631 L |
4270 | { Bad_Opcode }, |
4271 | { Bad_Opcode }, | |
507bd325 | 4272 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4273 | }, |
4274 | ||
1ceb70f8 | 4275 | /* PREFIX_0F383B */ |
42903f7f | 4276 | { |
592d1631 L |
4277 | { Bad_Opcode }, |
4278 | { Bad_Opcode }, | |
507bd325 | 4279 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4280 | }, |
4281 | ||
1ceb70f8 | 4282 | /* PREFIX_0F383C */ |
42903f7f | 4283 | { |
592d1631 L |
4284 | { Bad_Opcode }, |
4285 | { Bad_Opcode }, | |
507bd325 | 4286 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4287 | }, |
4288 | ||
1ceb70f8 | 4289 | /* PREFIX_0F383D */ |
42903f7f | 4290 | { |
592d1631 L |
4291 | { Bad_Opcode }, |
4292 | { Bad_Opcode }, | |
507bd325 | 4293 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4294 | }, |
4295 | ||
1ceb70f8 | 4296 | /* PREFIX_0F383E */ |
42903f7f | 4297 | { |
592d1631 L |
4298 | { Bad_Opcode }, |
4299 | { Bad_Opcode }, | |
507bd325 | 4300 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4301 | }, |
4302 | ||
1ceb70f8 | 4303 | /* PREFIX_0F383F */ |
42903f7f | 4304 | { |
592d1631 L |
4305 | { Bad_Opcode }, |
4306 | { Bad_Opcode }, | |
507bd325 | 4307 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4308 | }, |
4309 | ||
1ceb70f8 | 4310 | /* PREFIX_0F3840 */ |
42903f7f | 4311 | { |
592d1631 L |
4312 | { Bad_Opcode }, |
4313 | { Bad_Opcode }, | |
507bd325 | 4314 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4315 | }, |
4316 | ||
1ceb70f8 | 4317 | /* PREFIX_0F3841 */ |
42903f7f | 4318 | { |
592d1631 L |
4319 | { Bad_Opcode }, |
4320 | { Bad_Opcode }, | |
507bd325 | 4321 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4322 | }, |
4323 | ||
f1f8f695 L |
4324 | /* PREFIX_0F3880 */ |
4325 | { | |
592d1631 L |
4326 | { Bad_Opcode }, |
4327 | { Bad_Opcode }, | |
507bd325 | 4328 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4329 | }, |
4330 | ||
4331 | /* PREFIX_0F3881 */ | |
4332 | { | |
592d1631 L |
4333 | { Bad_Opcode }, |
4334 | { Bad_Opcode }, | |
507bd325 | 4335 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4336 | }, |
4337 | ||
6c30d220 L |
4338 | /* PREFIX_0F3882 */ |
4339 | { | |
4340 | { Bad_Opcode }, | |
4341 | { Bad_Opcode }, | |
507bd325 | 4342 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4343 | }, |
4344 | ||
a0046408 L |
4345 | /* PREFIX_0F38C8 */ |
4346 | { | |
507bd325 | 4347 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4348 | }, |
4349 | ||
4350 | /* PREFIX_0F38C9 */ | |
4351 | { | |
507bd325 | 4352 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4353 | }, |
4354 | ||
4355 | /* PREFIX_0F38CA */ | |
4356 | { | |
507bd325 | 4357 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4358 | }, |
4359 | ||
4360 | /* PREFIX_0F38CB */ | |
4361 | { | |
507bd325 | 4362 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4363 | }, |
4364 | ||
4365 | /* PREFIX_0F38CC */ | |
4366 | { | |
507bd325 | 4367 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4368 | }, |
4369 | ||
4370 | /* PREFIX_0F38CD */ | |
4371 | { | |
507bd325 | 4372 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4373 | }, |
4374 | ||
48521003 IT |
4375 | /* PREFIX_0F38CF */ |
4376 | { | |
4377 | { Bad_Opcode }, | |
4378 | { Bad_Opcode }, | |
4379 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4380 | }, | |
4381 | ||
c0f3af97 L |
4382 | /* PREFIX_0F38DB */ |
4383 | { | |
592d1631 L |
4384 | { Bad_Opcode }, |
4385 | { Bad_Opcode }, | |
507bd325 | 4386 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4387 | }, |
4388 | ||
4389 | /* PREFIX_0F38DC */ | |
4390 | { | |
592d1631 L |
4391 | { Bad_Opcode }, |
4392 | { Bad_Opcode }, | |
507bd325 | 4393 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4394 | }, |
4395 | ||
4396 | /* PREFIX_0F38DD */ | |
4397 | { | |
592d1631 L |
4398 | { Bad_Opcode }, |
4399 | { Bad_Opcode }, | |
507bd325 | 4400 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4401 | }, |
4402 | ||
4403 | /* PREFIX_0F38DE */ | |
4404 | { | |
592d1631 L |
4405 | { Bad_Opcode }, |
4406 | { Bad_Opcode }, | |
507bd325 | 4407 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4408 | }, |
4409 | ||
4410 | /* PREFIX_0F38DF */ | |
4411 | { | |
592d1631 L |
4412 | { Bad_Opcode }, |
4413 | { Bad_Opcode }, | |
507bd325 | 4414 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4415 | }, |
4416 | ||
1ceb70f8 | 4417 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4418 | { |
507bd325 | 4419 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4420 | { Bad_Opcode }, |
507bd325 L |
4421 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4422 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4423 | }, |
4424 | ||
1ceb70f8 | 4425 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4426 | { |
507bd325 | 4427 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4428 | { Bad_Opcode }, |
507bd325 L |
4429 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4430 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4431 | }, |
4432 | ||
603555e5 | 4433 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4434 | { |
4435 | { Bad_Opcode }, | |
603555e5 L |
4436 | { Bad_Opcode }, |
4437 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4438 | }, | |
4439 | ||
4440 | /* PREFIX_0F38F6 */ | |
4441 | { | |
4442 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4443 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4444 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4445 | { Bad_Opcode }, |
4446 | }, | |
4447 | ||
c0a30a9f L |
4448 | /* PREFIX_0F38F8 */ |
4449 | { | |
4450 | { Bad_Opcode }, | |
5d79adc4 | 4451 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4452 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4453 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4454 | }, |
4455 | ||
4456 | /* PREFIX_0F38F9 */ | |
4457 | { | |
4458 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4459 | }, | |
4460 | ||
1ceb70f8 | 4461 | /* PREFIX_0F3A08 */ |
42903f7f | 4462 | { |
592d1631 L |
4463 | { Bad_Opcode }, |
4464 | { Bad_Opcode }, | |
507bd325 | 4465 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4466 | }, |
4467 | ||
1ceb70f8 | 4468 | /* PREFIX_0F3A09 */ |
42903f7f | 4469 | { |
592d1631 L |
4470 | { Bad_Opcode }, |
4471 | { Bad_Opcode }, | |
507bd325 | 4472 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4473 | }, |
4474 | ||
1ceb70f8 | 4475 | /* PREFIX_0F3A0A */ |
42903f7f | 4476 | { |
592d1631 L |
4477 | { Bad_Opcode }, |
4478 | { Bad_Opcode }, | |
507bd325 | 4479 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4480 | }, |
4481 | ||
1ceb70f8 | 4482 | /* PREFIX_0F3A0B */ |
42903f7f | 4483 | { |
592d1631 L |
4484 | { Bad_Opcode }, |
4485 | { Bad_Opcode }, | |
507bd325 | 4486 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4487 | }, |
4488 | ||
1ceb70f8 | 4489 | /* PREFIX_0F3A0C */ |
42903f7f | 4490 | { |
592d1631 L |
4491 | { Bad_Opcode }, |
4492 | { Bad_Opcode }, | |
507bd325 | 4493 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4494 | }, |
4495 | ||
1ceb70f8 | 4496 | /* PREFIX_0F3A0D */ |
42903f7f | 4497 | { |
592d1631 L |
4498 | { Bad_Opcode }, |
4499 | { Bad_Opcode }, | |
507bd325 | 4500 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4501 | }, |
4502 | ||
1ceb70f8 | 4503 | /* PREFIX_0F3A0E */ |
42903f7f | 4504 | { |
592d1631 L |
4505 | { Bad_Opcode }, |
4506 | { Bad_Opcode }, | |
507bd325 | 4507 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4508 | }, |
4509 | ||
1ceb70f8 | 4510 | /* PREFIX_0F3A14 */ |
42903f7f | 4511 | { |
592d1631 L |
4512 | { Bad_Opcode }, |
4513 | { Bad_Opcode }, | |
507bd325 | 4514 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4515 | }, |
4516 | ||
1ceb70f8 | 4517 | /* PREFIX_0F3A15 */ |
42903f7f | 4518 | { |
592d1631 L |
4519 | { Bad_Opcode }, |
4520 | { Bad_Opcode }, | |
507bd325 | 4521 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4522 | }, |
4523 | ||
1ceb70f8 | 4524 | /* PREFIX_0F3A16 */ |
42903f7f | 4525 | { |
592d1631 L |
4526 | { Bad_Opcode }, |
4527 | { Bad_Opcode }, | |
507bd325 | 4528 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4529 | }, |
4530 | ||
1ceb70f8 | 4531 | /* PREFIX_0F3A17 */ |
42903f7f | 4532 | { |
592d1631 L |
4533 | { Bad_Opcode }, |
4534 | { Bad_Opcode }, | |
507bd325 | 4535 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4536 | }, |
4537 | ||
1ceb70f8 | 4538 | /* PREFIX_0F3A20 */ |
42903f7f | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4543 | }, |
4544 | ||
1ceb70f8 | 4545 | /* PREFIX_0F3A21 */ |
42903f7f | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
507bd325 | 4549 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4550 | }, |
4551 | ||
1ceb70f8 | 4552 | /* PREFIX_0F3A22 */ |
42903f7f | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
507bd325 | 4556 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4557 | }, |
4558 | ||
1ceb70f8 | 4559 | /* PREFIX_0F3A40 */ |
42903f7f | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
507bd325 | 4563 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4564 | }, |
4565 | ||
1ceb70f8 | 4566 | /* PREFIX_0F3A41 */ |
42903f7f | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
507bd325 | 4570 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4571 | }, |
4572 | ||
1ceb70f8 | 4573 | /* PREFIX_0F3A42 */ |
42903f7f | 4574 | { |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
507bd325 | 4577 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4578 | }, |
381d071f | 4579 | |
c0f3af97 L |
4580 | /* PREFIX_0F3A44 */ |
4581 | { | |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
507bd325 | 4584 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4585 | }, |
4586 | ||
1ceb70f8 | 4587 | /* PREFIX_0F3A60 */ |
381d071f | 4588 | { |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
15c7c1d8 | 4591 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4592 | }, |
4593 | ||
1ceb70f8 | 4594 | /* PREFIX_0F3A61 */ |
381d071f | 4595 | { |
592d1631 L |
4596 | { Bad_Opcode }, |
4597 | { Bad_Opcode }, | |
15c7c1d8 | 4598 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4599 | }, |
4600 | ||
1ceb70f8 | 4601 | /* PREFIX_0F3A62 */ |
381d071f | 4602 | { |
592d1631 L |
4603 | { Bad_Opcode }, |
4604 | { Bad_Opcode }, | |
507bd325 | 4605 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4606 | }, |
4607 | ||
1ceb70f8 | 4608 | /* PREFIX_0F3A63 */ |
381d071f | 4609 | { |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
507bd325 | 4612 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4613 | }, |
09a2c6cf | 4614 | |
a0046408 L |
4615 | /* PREFIX_0F3ACC */ |
4616 | { | |
507bd325 | 4617 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4618 | }, |
4619 | ||
48521003 IT |
4620 | /* PREFIX_0F3ACE */ |
4621 | { | |
4622 | { Bad_Opcode }, | |
4623 | { Bad_Opcode }, | |
4624 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4625 | }, | |
4626 | ||
4627 | /* PREFIX_0F3ACF */ | |
4628 | { | |
4629 | { Bad_Opcode }, | |
4630 | { Bad_Opcode }, | |
4631 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4632 | }, | |
4633 | ||
c0f3af97 | 4634 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4635 | { |
592d1631 L |
4636 | { Bad_Opcode }, |
4637 | { Bad_Opcode }, | |
507bd325 | 4638 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4639 | }, |
4640 | ||
592a252b | 4641 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4642 | { |
ec6f095a L |
4643 | { "vmovups", { XM, EXx }, 0 }, |
4644 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4645 | { "vmovupd", { XM, EXx }, 0 }, | |
4646 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4647 | }, |
4648 | ||
592a252b | 4649 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4650 | { |
ec6f095a L |
4651 | { "vmovups", { EXxS, XM }, 0 }, |
4652 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4653 | { "vmovupd", { EXxS, XM }, 0 }, | |
4654 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4655 | }, |
4656 | ||
592a252b | 4657 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4658 | { |
592a252b | 4659 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4660 | { "vmovsldup", { XM, EXx }, 0 }, |
592a252b | 4661 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
ec6f095a | 4662 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4663 | }, |
4664 | ||
592a252b | 4665 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4666 | { |
592a252b | 4667 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4668 | { "vmovshdup", { XM, EXx }, 0 }, |
592a252b | 4669 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
5f754f58 | 4670 | }, |
7c52e0e8 | 4671 | |
592a252b | 4672 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4673 | { |
592d1631 | 4674 | { Bad_Opcode }, |
592a252b | 4675 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4676 | { Bad_Opcode }, |
592a252b | 4677 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4678 | }, |
7c52e0e8 | 4679 | |
592a252b | 4680 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4681 | { |
592d1631 | 4682 | { Bad_Opcode }, |
592a252b | 4683 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4684 | { Bad_Opcode }, |
592a252b | 4685 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4686 | }, |
7c52e0e8 | 4687 | |
592a252b | 4688 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4689 | { |
592d1631 | 4690 | { Bad_Opcode }, |
592a252b | 4691 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4692 | { Bad_Opcode }, |
592a252b | 4693 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4694 | }, |
4695 | ||
592a252b | 4696 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4697 | { |
ec6f095a | 4698 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4699 | { Bad_Opcode }, |
ec6f095a | 4700 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4701 | }, |
4702 | ||
592a252b | 4703 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4704 | { |
ec6f095a | 4705 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4706 | { Bad_Opcode }, |
ec6f095a | 4707 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4708 | }, |
4709 | ||
43234a1e L |
4710 | /* PREFIX_VEX_0F41 */ |
4711 | { | |
4712 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4713 | { Bad_Opcode }, |
4714 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4715 | }, |
4716 | ||
4717 | /* PREFIX_VEX_0F42 */ | |
4718 | { | |
4719 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4720 | { Bad_Opcode }, |
4721 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4722 | }, |
4723 | ||
4724 | /* PREFIX_VEX_0F44 */ | |
4725 | { | |
4726 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4727 | { Bad_Opcode }, |
4728 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4729 | }, |
4730 | ||
4731 | /* PREFIX_VEX_0F45 */ | |
4732 | { | |
4733 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4734 | { Bad_Opcode }, |
4735 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4736 | }, |
4737 | ||
4738 | /* PREFIX_VEX_0F46 */ | |
4739 | { | |
4740 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4741 | { Bad_Opcode }, |
4742 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4743 | }, |
4744 | ||
4745 | /* PREFIX_VEX_0F47 */ | |
4746 | { | |
4747 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4748 | { Bad_Opcode }, |
4749 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4750 | }, |
4751 | ||
1ba585e8 | 4752 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4753 | { |
1ba585e8 | 4754 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4755 | { Bad_Opcode }, |
1ba585e8 IT |
4756 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4757 | }, | |
4758 | ||
4759 | /* PREFIX_VEX_0F4B */ | |
4760 | { | |
4761 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4762 | { Bad_Opcode }, |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4764 | }, | |
4765 | ||
592a252b | 4766 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4767 | { |
ec6f095a L |
4768 | { "vsqrtps", { XM, EXx }, 0 }, |
4769 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4770 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4771 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4772 | }, |
4773 | ||
592a252b | 4774 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4775 | { |
ec6f095a L |
4776 | { "vrsqrtps", { XM, EXx }, 0 }, |
4777 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4778 | }, |
4779 | ||
592a252b | 4780 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4781 | { |
ec6f095a L |
4782 | { "vrcpps", { XM, EXx }, 0 }, |
4783 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4784 | }, |
4785 | ||
592a252b | 4786 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4787 | { |
ec6f095a L |
4788 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4789 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4790 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4791 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4792 | }, |
4793 | ||
592a252b | 4794 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4795 | { |
ec6f095a L |
4796 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4797 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4798 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4799 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4800 | }, |
4801 | ||
592a252b | 4802 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4803 | { |
ec6f095a L |
4804 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4805 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4806 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4807 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4808 | }, |
4809 | ||
592a252b | 4810 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4811 | { |
ec6f095a L |
4812 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4813 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4814 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4815 | }, |
4816 | ||
592a252b | 4817 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4818 | { |
ec6f095a L |
4819 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4820 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4821 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4822 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4823 | }, |
4824 | ||
592a252b | 4825 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4826 | { |
ec6f095a L |
4827 | { "vminps", { XM, Vex, EXx }, 0 }, |
4828 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4829 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4830 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4831 | }, |
4832 | ||
592a252b | 4833 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4834 | { |
ec6f095a L |
4835 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4836 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4837 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4838 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4839 | }, |
4840 | ||
592a252b | 4841 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4842 | { |
ec6f095a L |
4843 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4844 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4845 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4846 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4847 | }, |
4848 | ||
592a252b | 4849 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4850 | { |
592d1631 L |
4851 | { Bad_Opcode }, |
4852 | { Bad_Opcode }, | |
ec6f095a | 4853 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4854 | }, |
4855 | ||
592a252b | 4856 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4857 | { |
592d1631 L |
4858 | { Bad_Opcode }, |
4859 | { Bad_Opcode }, | |
ec6f095a | 4860 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4861 | }, |
4862 | ||
592a252b | 4863 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4864 | { |
592d1631 L |
4865 | { Bad_Opcode }, |
4866 | { Bad_Opcode }, | |
ec6f095a | 4867 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4868 | }, |
4869 | ||
592a252b | 4870 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4871 | { |
592d1631 L |
4872 | { Bad_Opcode }, |
4873 | { Bad_Opcode }, | |
ec6f095a | 4874 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4875 | }, |
4876 | ||
592a252b | 4877 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4878 | { |
592d1631 L |
4879 | { Bad_Opcode }, |
4880 | { Bad_Opcode }, | |
ec6f095a | 4881 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4882 | }, |
4883 | ||
592a252b | 4884 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4885 | { |
592d1631 L |
4886 | { Bad_Opcode }, |
4887 | { Bad_Opcode }, | |
ec6f095a | 4888 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4889 | }, |
4890 | ||
592a252b | 4891 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4892 | { |
592d1631 L |
4893 | { Bad_Opcode }, |
4894 | { Bad_Opcode }, | |
ec6f095a | 4895 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4896 | }, |
6439fc28 | 4897 | |
592a252b | 4898 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4899 | { |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
ec6f095a | 4902 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
ec6f095a | 4909 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4910 | }, |
4911 | ||
592a252b | 4912 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
ec6f095a | 4916 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
ec6f095a | 4923 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4924 | }, |
4925 | ||
592a252b | 4926 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
ec6f095a | 4930 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4931 | }, |
4932 | ||
592a252b | 4933 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
ec6f095a | 4937 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4938 | }, |
4939 | ||
592a252b | 4940 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4941 | { |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
ec6f095a | 4944 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4945 | }, |
4946 | ||
592a252b | 4947 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4948 | { |
592d1631 L |
4949 | { Bad_Opcode }, |
4950 | { Bad_Opcode }, | |
592a252b | 4951 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4952 | }, |
4953 | ||
592a252b | 4954 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4955 | { |
592d1631 | 4956 | { Bad_Opcode }, |
ec6f095a L |
4957 | { "vmovdqu", { XM, EXx }, 0 }, |
4958 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4962 | { |
592d1631 | 4963 | { Bad_Opcode }, |
ec6f095a L |
4964 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4965 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4966 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4967 | }, |
4968 | ||
592a252b | 4969 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4970 | { |
592d1631 L |
4971 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, | |
ec6f095a | 4973 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4974 | }, |
4975 | ||
592a252b | 4976 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4977 | { |
592d1631 L |
4978 | { Bad_Opcode }, |
4979 | { Bad_Opcode }, | |
ec6f095a | 4980 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4981 | }, |
4982 | ||
592a252b | 4983 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4984 | { |
592d1631 L |
4985 | { Bad_Opcode }, |
4986 | { Bad_Opcode }, | |
ec6f095a | 4987 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4988 | }, |
4989 | ||
592a252b | 4990 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4991 | { |
592d1631 L |
4992 | { Bad_Opcode }, |
4993 | { Bad_Opcode }, | |
ec6f095a | 4994 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4995 | }, |
4996 | ||
592a252b | 4997 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4998 | { |
592d1631 L |
4999 | { Bad_Opcode }, |
5000 | { Bad_Opcode }, | |
ec6f095a | 5001 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5002 | }, |
5003 | ||
592a252b | 5004 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5005 | { |
592d1631 L |
5006 | { Bad_Opcode }, |
5007 | { Bad_Opcode }, | |
ec6f095a | 5008 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5009 | }, |
5010 | ||
592a252b | 5011 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5012 | { |
592d1631 L |
5013 | { Bad_Opcode }, |
5014 | { Bad_Opcode }, | |
ec6f095a | 5015 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5016 | }, |
5017 | ||
592a252b | 5018 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5019 | { |
592d1631 L |
5020 | { Bad_Opcode }, |
5021 | { Bad_Opcode }, | |
ec6f095a | 5022 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5026 | { |
592d1631 L |
5027 | { Bad_Opcode }, |
5028 | { Bad_Opcode }, | |
ec6f095a | 5029 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5030 | }, |
5031 | ||
592a252b | 5032 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5033 | { |
592d1631 L |
5034 | { Bad_Opcode }, |
5035 | { Bad_Opcode }, | |
ec6f095a | 5036 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5037 | }, |
5038 | ||
592a252b | 5039 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5040 | { |
592d1631 L |
5041 | { Bad_Opcode }, |
5042 | { Bad_Opcode }, | |
ec6f095a | 5043 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5044 | }, |
5045 | ||
592a252b | 5046 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5047 | { |
592d1631 L |
5048 | { Bad_Opcode }, |
5049 | { Bad_Opcode }, | |
ec6f095a | 5050 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5051 | }, |
5052 | ||
592a252b | 5053 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5054 | { |
592d1631 L |
5055 | { Bad_Opcode }, |
5056 | { Bad_Opcode }, | |
ec6f095a | 5057 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5058 | }, |
5059 | ||
592a252b | 5060 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5061 | { |
ec6f095a | 5062 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5063 | }, |
5064 | ||
592a252b | 5065 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5066 | { |
592d1631 L |
5067 | { Bad_Opcode }, |
5068 | { Bad_Opcode }, | |
ec6f095a L |
5069 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5070 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
ec6f095a L |
5077 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5078 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5082 | { |
592d1631 | 5083 | { Bad_Opcode }, |
592a252b L |
5084 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5085 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5089 | { |
592d1631 | 5090 | { Bad_Opcode }, |
ec6f095a L |
5091 | { "vmovdqu", { EXxS, XM }, 0 }, |
5092 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5093 | }, |
5094 | ||
43234a1e L |
5095 | /* PREFIX_VEX_0F90 */ |
5096 | { | |
5097 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5098 | { Bad_Opcode }, |
5099 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5100 | }, |
5101 | ||
5102 | /* PREFIX_VEX_0F91 */ | |
5103 | { | |
5104 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5105 | { Bad_Opcode }, |
5106 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5107 | }, |
5108 | ||
5109 | /* PREFIX_VEX_0F92 */ | |
5110 | { | |
5111 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5112 | { Bad_Opcode }, |
90a915bf | 5113 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5114 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5115 | }, |
5116 | ||
5117 | /* PREFIX_VEX_0F93 */ | |
5118 | { | |
5119 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5120 | { Bad_Opcode }, |
90a915bf | 5121 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5122 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5123 | }, |
5124 | ||
5125 | /* PREFIX_VEX_0F98 */ | |
5126 | { | |
5127 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5128 | { Bad_Opcode }, |
5129 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5130 | }, | |
5131 | ||
5132 | /* PREFIX_VEX_0F99 */ | |
5133 | { | |
5134 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5135 | { Bad_Opcode }, | |
5136 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5137 | }, |
5138 | ||
592a252b | 5139 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5140 | { |
ec6f095a L |
5141 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5142 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5143 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5144 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5145 | }, |
5146 | ||
592a252b | 5147 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5148 | { |
592d1631 L |
5149 | { Bad_Opcode }, |
5150 | { Bad_Opcode }, | |
592a252b | 5151 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5152 | }, |
5153 | ||
592a252b | 5154 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5155 | { |
592d1631 L |
5156 | { Bad_Opcode }, |
5157 | { Bad_Opcode }, | |
592a252b | 5158 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5162 | { |
592d1631 L |
5163 | { Bad_Opcode }, |
5164 | { Bad_Opcode }, | |
ec6f095a L |
5165 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5166 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5167 | }, |
5168 | ||
592a252b | 5169 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5170 | { |
592d1631 L |
5171 | { Bad_Opcode }, |
5172 | { Bad_Opcode }, | |
ec6f095a | 5173 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5174 | }, |
5175 | ||
592a252b | 5176 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5177 | { |
592d1631 L |
5178 | { Bad_Opcode }, |
5179 | { Bad_Opcode }, | |
ec6f095a | 5180 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5181 | }, |
5182 | ||
592a252b | 5183 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5184 | { |
592d1631 L |
5185 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, | |
ec6f095a | 5187 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5188 | }, |
5189 | ||
592a252b | 5190 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5191 | { |
592d1631 L |
5192 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, | |
ec6f095a | 5194 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5195 | }, |
5196 | ||
592a252b | 5197 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5198 | { |
592d1631 L |
5199 | { Bad_Opcode }, |
5200 | { Bad_Opcode }, | |
ec6f095a | 5201 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5202 | }, |
5203 | ||
592a252b | 5204 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5205 | { |
592d1631 L |
5206 | { Bad_Opcode }, |
5207 | { Bad_Opcode }, | |
592a252b | 5208 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5209 | }, |
5210 | ||
592a252b | 5211 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5212 | { |
592d1631 L |
5213 | { Bad_Opcode }, |
5214 | { Bad_Opcode }, | |
592a252b | 5215 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
ec6f095a | 5222 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
ec6f095a | 5229 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
ec6f095a | 5236 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
ec6f095a | 5243 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
ec6f095a | 5250 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
ec6f095a | 5257 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
ec6f095a | 5264 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5268 | { |
592d1631 L |
5269 | { Bad_Opcode }, |
5270 | { Bad_Opcode }, | |
ec6f095a | 5271 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5272 | }, |
5273 | ||
592a252b | 5274 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5275 | { |
592d1631 L |
5276 | { Bad_Opcode }, |
5277 | { Bad_Opcode }, | |
ec6f095a | 5278 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5279 | }, |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5282 | { |
592d1631 L |
5283 | { Bad_Opcode }, |
5284 | { Bad_Opcode }, | |
ec6f095a | 5285 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5289 | { |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
ec6f095a | 5292 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5293 | }, |
5294 | ||
592a252b | 5295 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5296 | { |
592d1631 L |
5297 | { Bad_Opcode }, |
5298 | { Bad_Opcode }, | |
ec6f095a | 5299 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
ec6f095a | 5306 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
ec6f095a | 5313 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5317 | { |
592d1631 | 5318 | { Bad_Opcode }, |
ec6f095a L |
5319 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5320 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5321 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5322 | }, |
5323 | ||
592a252b | 5324 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5325 | { |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
592a252b | 5328 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5329 | }, |
5330 | ||
592a252b | 5331 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5332 | { |
592d1631 L |
5333 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, | |
ec6f095a | 5335 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5336 | }, |
5337 | ||
592a252b | 5338 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5339 | { |
592d1631 L |
5340 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, | |
ec6f095a | 5342 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5343 | }, |
5344 | ||
592a252b | 5345 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5346 | { |
592d1631 L |
5347 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, | |
ec6f095a | 5349 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5350 | }, |
5351 | ||
592a252b | 5352 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5353 | { |
592d1631 L |
5354 | { Bad_Opcode }, |
5355 | { Bad_Opcode }, | |
ec6f095a | 5356 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5357 | }, |
5358 | ||
592a252b | 5359 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5360 | { |
592d1631 L |
5361 | { Bad_Opcode }, |
5362 | { Bad_Opcode }, | |
ec6f095a | 5363 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5364 | }, |
5365 | ||
592a252b | 5366 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5367 | { |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
ec6f095a | 5370 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
ec6f095a | 5377 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
ec6f095a | 5384 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
5391 | { Bad_Opcode }, | |
592a252b | 5392 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5393 | }, |
5394 | ||
592a252b | 5395 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5396 | { |
592d1631 L |
5397 | { Bad_Opcode }, |
5398 | { Bad_Opcode }, | |
ec6f095a | 5399 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5400 | }, |
5401 | ||
592a252b | 5402 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5403 | { |
592d1631 L |
5404 | { Bad_Opcode }, |
5405 | { Bad_Opcode }, | |
ec6f095a | 5406 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5407 | }, |
5408 | ||
592a252b | 5409 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5410 | { |
592d1631 L |
5411 | { Bad_Opcode }, |
5412 | { Bad_Opcode }, | |
ec6f095a | 5413 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5414 | }, |
5415 | ||
592a252b | 5416 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5417 | { |
592d1631 L |
5418 | { Bad_Opcode }, |
5419 | { Bad_Opcode }, | |
ec6f095a | 5420 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5421 | }, |
5422 | ||
592a252b | 5423 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5424 | { |
592d1631 L |
5425 | { Bad_Opcode }, |
5426 | { Bad_Opcode }, | |
ec6f095a | 5427 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5428 | }, |
5429 | ||
592a252b | 5430 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5431 | { |
592d1631 L |
5432 | { Bad_Opcode }, |
5433 | { Bad_Opcode }, | |
ec6f095a | 5434 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5435 | }, |
5436 | ||
592a252b | 5437 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5438 | { |
592d1631 L |
5439 | { Bad_Opcode }, |
5440 | { Bad_Opcode }, | |
592a252b | 5441 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5442 | }, |
5443 | ||
592a252b | 5444 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5445 | { |
592d1631 L |
5446 | { Bad_Opcode }, |
5447 | { Bad_Opcode }, | |
ec6f095a | 5448 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5449 | }, |
5450 | ||
592a252b | 5451 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5452 | { |
592d1631 L |
5453 | { Bad_Opcode }, |
5454 | { Bad_Opcode }, | |
ec6f095a | 5455 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5456 | }, |
5457 | ||
592a252b | 5458 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5459 | { |
592d1631 L |
5460 | { Bad_Opcode }, |
5461 | { Bad_Opcode }, | |
ec6f095a | 5462 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5463 | }, |
5464 | ||
592a252b | 5465 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5466 | { |
592d1631 L |
5467 | { Bad_Opcode }, |
5468 | { Bad_Opcode }, | |
ec6f095a | 5469 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5470 | }, |
5471 | ||
592a252b | 5472 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5473 | { |
592d1631 L |
5474 | { Bad_Opcode }, |
5475 | { Bad_Opcode }, | |
ec6f095a | 5476 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5477 | }, |
5478 | ||
592a252b | 5479 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5480 | { |
592d1631 L |
5481 | { Bad_Opcode }, |
5482 | { Bad_Opcode }, | |
ec6f095a | 5483 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5484 | }, |
5485 | ||
592a252b | 5486 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5487 | { |
592d1631 L |
5488 | { Bad_Opcode }, |
5489 | { Bad_Opcode }, | |
ec6f095a | 5490 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5491 | }, |
5492 | ||
592a252b | 5493 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5494 | { |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
ec6f095a | 5497 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5498 | }, |
5499 | ||
592a252b | 5500 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5501 | { |
592d1631 L |
5502 | { Bad_Opcode }, |
5503 | { Bad_Opcode }, | |
ec6f095a | 5504 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5505 | }, |
5506 | ||
592a252b | 5507 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5508 | { |
592d1631 L |
5509 | { Bad_Opcode }, |
5510 | { Bad_Opcode }, | |
ec6f095a | 5511 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5512 | }, |
5513 | ||
592a252b | 5514 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5515 | { |
592d1631 L |
5516 | { Bad_Opcode }, |
5517 | { Bad_Opcode }, | |
ec6f095a | 5518 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5519 | }, |
5520 | ||
592a252b | 5521 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5522 | { |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
ec6f095a | 5525 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5526 | }, |
5527 | ||
592a252b | 5528 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5529 | { |
592d1631 L |
5530 | { Bad_Opcode }, |
5531 | { Bad_Opcode }, | |
ec6f095a | 5532 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5533 | }, |
5534 | ||
592a252b | 5535 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5536 | { |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
ec6f095a | 5539 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5540 | }, |
5541 | ||
592a252b | 5542 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5543 | { |
592d1631 L |
5544 | { Bad_Opcode }, |
5545 | { Bad_Opcode }, | |
ec6f095a | 5546 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5547 | }, |
5548 | ||
592a252b | 5549 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5550 | { |
592d1631 L |
5551 | { Bad_Opcode }, |
5552 | { Bad_Opcode }, | |
ec6f095a | 5553 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5554 | }, |
5555 | ||
592a252b | 5556 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5557 | { |
592d1631 L |
5558 | { Bad_Opcode }, |
5559 | { Bad_Opcode }, | |
ec6f095a | 5560 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
ec6f095a | 5567 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
ec6f095a | 5574 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
592a252b | 5581 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
592a252b | 5588 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
592a252b | 5595 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
592a252b | 5602 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5606 | { |
5607 | { Bad_Opcode }, | |
5608 | { Bad_Opcode }, | |
bf890a93 | 5609 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5610 | }, |
5611 | ||
6c30d220 L |
5612 | /* PREFIX_VEX_0F3816 */ |
5613 | { | |
5614 | { Bad_Opcode }, | |
5615 | { Bad_Opcode }, | |
5616 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5617 | }, | |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
ec6f095a | 5623 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
6c30d220 | 5630 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5631 | }, |
5632 | ||
592a252b | 5633 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5634 | { |
592d1631 L |
5635 | { Bad_Opcode }, |
5636 | { Bad_Opcode }, | |
6c30d220 | 5637 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5638 | }, |
5639 | ||
592a252b | 5640 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5641 | { |
592d1631 L |
5642 | { Bad_Opcode }, |
5643 | { Bad_Opcode }, | |
592a252b | 5644 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5645 | }, |
5646 | ||
592a252b | 5647 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5648 | { |
592d1631 L |
5649 | { Bad_Opcode }, |
5650 | { Bad_Opcode }, | |
ec6f095a | 5651 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5652 | }, |
5653 | ||
592a252b | 5654 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5655 | { |
592d1631 L |
5656 | { Bad_Opcode }, |
5657 | { Bad_Opcode }, | |
ec6f095a | 5658 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5659 | }, |
5660 | ||
592a252b | 5661 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5662 | { |
592d1631 L |
5663 | { Bad_Opcode }, |
5664 | { Bad_Opcode }, | |
ec6f095a | 5665 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5666 | }, |
5667 | ||
592a252b | 5668 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5669 | { |
592d1631 L |
5670 | { Bad_Opcode }, |
5671 | { Bad_Opcode }, | |
ec6f095a | 5672 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5673 | }, |
5674 | ||
592a252b | 5675 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5676 | { |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
ec6f095a | 5679 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5680 | }, |
5681 | ||
592a252b | 5682 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5683 | { |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
ec6f095a | 5686 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5687 | }, |
5688 | ||
592a252b | 5689 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5690 | { |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
ec6f095a | 5693 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5694 | }, |
5695 | ||
592a252b | 5696 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5697 | { |
592d1631 L |
5698 | { Bad_Opcode }, |
5699 | { Bad_Opcode }, | |
ec6f095a | 5700 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5701 | }, |
5702 | ||
592a252b | 5703 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5704 | { |
592d1631 L |
5705 | { Bad_Opcode }, |
5706 | { Bad_Opcode }, | |
ec6f095a | 5707 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5708 | }, |
5709 | ||
592a252b | 5710 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5711 | { |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
ec6f095a | 5714 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5715 | }, |
5716 | ||
592a252b | 5717 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5718 | { |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
ec6f095a | 5721 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5722 | }, |
5723 | ||
592a252b | 5724 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5725 | { |
592d1631 L |
5726 | { Bad_Opcode }, |
5727 | { Bad_Opcode }, | |
592a252b | 5728 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5729 | }, |
5730 | ||
592a252b | 5731 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5732 | { |
592d1631 L |
5733 | { Bad_Opcode }, |
5734 | { Bad_Opcode }, | |
ec6f095a | 5735 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5736 | }, |
5737 | ||
592a252b | 5738 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5739 | { |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
592a252b | 5742 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
592a252b | 5749 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
592a252b | 5756 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
592a252b | 5763 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
ec6f095a | 5770 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
ec6f095a | 5777 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
ec6f095a | 5784 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
ec6f095a | 5791 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5795 | { |
592d1631 L |
5796 | { Bad_Opcode }, |
5797 | { Bad_Opcode }, | |
ec6f095a | 5798 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5799 | }, |
5800 | ||
592a252b | 5801 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5802 | { |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
ec6f095a | 5805 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5806 | }, |
5807 | ||
5808 | /* PREFIX_VEX_0F3836 */ | |
5809 | { | |
5810 | { Bad_Opcode }, | |
5811 | { Bad_Opcode }, | |
5812 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
ec6f095a | 5819 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
ec6f095a | 5826 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
ec6f095a | 5833 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
ec6f095a | 5840 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
ec6f095a | 5847 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5848 | }, |
5849 | ||
592a252b | 5850 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5851 | { |
592d1631 L |
5852 | { Bad_Opcode }, |
5853 | { Bad_Opcode }, | |
ec6f095a | 5854 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5855 | }, |
5856 | ||
592a252b | 5857 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5858 | { |
592d1631 L |
5859 | { Bad_Opcode }, |
5860 | { Bad_Opcode }, | |
ec6f095a | 5861 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5862 | }, |
5863 | ||
592a252b | 5864 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5865 | { |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
ec6f095a | 5868 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
ec6f095a | 5875 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
ec6f095a | 5882 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
592a252b | 5889 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
6c30d220 L |
5892 | /* PREFIX_VEX_0F3845 */ |
5893 | { | |
5894 | { Bad_Opcode }, | |
5895 | { Bad_Opcode }, | |
bf890a93 | 5896 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5897 | }, |
5898 | ||
5899 | /* PREFIX_VEX_0F3846 */ | |
5900 | { | |
5901 | { Bad_Opcode }, | |
5902 | { Bad_Opcode }, | |
5903 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5904 | }, | |
5905 | ||
5906 | /* PREFIX_VEX_0F3847 */ | |
5907 | { | |
5908 | { Bad_Opcode }, | |
5909 | { Bad_Opcode }, | |
bf890a93 | 5910 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5911 | }, |
5912 | ||
5913 | /* PREFIX_VEX_0F3858 */ | |
5914 | { | |
5915 | { Bad_Opcode }, | |
5916 | { Bad_Opcode }, | |
5917 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5918 | }, | |
5919 | ||
5920 | /* PREFIX_VEX_0F3859 */ | |
5921 | { | |
5922 | { Bad_Opcode }, | |
5923 | { Bad_Opcode }, | |
5924 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5925 | }, | |
5926 | ||
5927 | /* PREFIX_VEX_0F385A */ | |
5928 | { | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
5931 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5932 | }, | |
5933 | ||
5934 | /* PREFIX_VEX_0F3878 */ | |
5935 | { | |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
5938 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5939 | }, | |
5940 | ||
5941 | /* PREFIX_VEX_0F3879 */ | |
5942 | { | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
5945 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5946 | }, | |
5947 | ||
5948 | /* PREFIX_VEX_0F388C */ | |
5949 | { | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
f7002f42 | 5952 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5953 | }, |
5954 | ||
5955 | /* PREFIX_VEX_0F388E */ | |
5956 | { | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
f7002f42 | 5959 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5960 | }, |
5961 | ||
5962 | /* PREFIX_VEX_0F3890 */ | |
5963 | { | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
bf890a93 | 5966 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5967 | }, |
5968 | ||
5969 | /* PREFIX_VEX_0F3891 */ | |
5970 | { | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
bf890a93 | 5973 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5974 | }, |
5975 | ||
5976 | /* PREFIX_VEX_0F3892 */ | |
5977 | { | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
bf890a93 | 5980 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5981 | }, |
5982 | ||
5983 | /* PREFIX_VEX_0F3893 */ | |
5984 | { | |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
bf890a93 | 5987 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5988 | }, |
5989 | ||
592a252b | 5990 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5991 | { |
592d1631 L |
5992 | { Bad_Opcode }, |
5993 | { Bad_Opcode }, | |
bf890a93 | 5994 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5995 | }, |
5996 | ||
592a252b | 5997 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5998 | { |
592d1631 L |
5999 | { Bad_Opcode }, |
6000 | { Bad_Opcode }, | |
bf890a93 | 6001 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6002 | }, |
6003 | ||
592a252b | 6004 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6005 | { |
592d1631 L |
6006 | { Bad_Opcode }, |
6007 | { Bad_Opcode }, | |
bf890a93 | 6008 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6009 | }, |
6010 | ||
592a252b | 6011 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6012 | { |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
bf890a93 | 6015 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6016 | }, |
6017 | ||
592a252b | 6018 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6019 | { |
592d1631 L |
6020 | { Bad_Opcode }, |
6021 | { Bad_Opcode }, | |
bf890a93 | 6022 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6023 | }, |
6024 | ||
592a252b | 6025 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6026 | { |
592d1631 L |
6027 | { Bad_Opcode }, |
6028 | { Bad_Opcode }, | |
bf890a93 | 6029 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6030 | }, |
6031 | ||
592a252b | 6032 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6033 | { |
592d1631 L |
6034 | { Bad_Opcode }, |
6035 | { Bad_Opcode }, | |
bf890a93 | 6036 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6037 | }, |
6038 | ||
592a252b | 6039 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6040 | { |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
bf890a93 | 6043 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
bf890a93 | 6050 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
bf890a93 | 6057 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
bf890a93 | 6064 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6065 | { Bad_Opcode }, |
c0f3af97 L |
6066 | }, |
6067 | ||
592a252b | 6068 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6069 | { |
592d1631 L |
6070 | { Bad_Opcode }, |
6071 | { Bad_Opcode }, | |
bf890a93 | 6072 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6073 | }, |
6074 | ||
592a252b | 6075 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6076 | { |
592d1631 L |
6077 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, | |
bf890a93 | 6079 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6080 | }, |
6081 | ||
592a252b | 6082 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6083 | { |
592d1631 L |
6084 | { Bad_Opcode }, |
6085 | { Bad_Opcode }, | |
bf890a93 | 6086 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6087 | }, |
6088 | ||
592a252b | 6089 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6090 | { |
592d1631 L |
6091 | { Bad_Opcode }, |
6092 | { Bad_Opcode }, | |
bf890a93 | 6093 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6094 | }, |
6095 | ||
592a252b | 6096 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6097 | { |
592d1631 L |
6098 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, | |
bf890a93 | 6100 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6101 | }, |
6102 | ||
592a252b | 6103 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6104 | { |
592d1631 L |
6105 | { Bad_Opcode }, |
6106 | { Bad_Opcode }, | |
bf890a93 | 6107 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6108 | }, |
6109 | ||
592a252b | 6110 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6111 | { |
592d1631 L |
6112 | { Bad_Opcode }, |
6113 | { Bad_Opcode }, | |
bf890a93 | 6114 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6115 | }, |
6116 | ||
592a252b | 6117 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6118 | { |
592d1631 L |
6119 | { Bad_Opcode }, |
6120 | { Bad_Opcode }, | |
bf890a93 | 6121 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6122 | }, |
6123 | ||
592a252b | 6124 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6125 | { |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
bf890a93 | 6128 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6129 | }, |
6130 | ||
592a252b | 6131 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6132 | { |
592d1631 L |
6133 | { Bad_Opcode }, |
6134 | { Bad_Opcode }, | |
bf890a93 | 6135 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6136 | }, |
6137 | ||
592a252b | 6138 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6139 | { |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
bf890a93 | 6142 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6143 | }, |
6144 | ||
592a252b | 6145 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6146 | { |
592d1631 L |
6147 | { Bad_Opcode }, |
6148 | { Bad_Opcode }, | |
bf890a93 | 6149 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6150 | }, |
6151 | ||
592a252b | 6152 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6153 | { |
592d1631 L |
6154 | { Bad_Opcode }, |
6155 | { Bad_Opcode }, | |
bf890a93 | 6156 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6157 | }, |
6158 | ||
592a252b | 6159 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6160 | { |
592d1631 L |
6161 | { Bad_Opcode }, |
6162 | { Bad_Opcode }, | |
bf890a93 | 6163 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6164 | }, |
6165 | ||
592a252b | 6166 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6167 | { |
592d1631 L |
6168 | { Bad_Opcode }, |
6169 | { Bad_Opcode }, | |
bf890a93 | 6170 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6171 | }, |
6172 | ||
592a252b | 6173 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6174 | { |
592d1631 L |
6175 | { Bad_Opcode }, |
6176 | { Bad_Opcode }, | |
bf890a93 | 6177 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6178 | }, |
6179 | ||
592a252b | 6180 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6181 | { |
592d1631 L |
6182 | { Bad_Opcode }, |
6183 | { Bad_Opcode }, | |
bf890a93 | 6184 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6185 | }, |
6186 | ||
592a252b | 6187 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6188 | { |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
bf890a93 | 6191 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6192 | }, |
6193 | ||
592a252b | 6194 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6195 | { |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
bf890a93 | 6198 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6199 | }, |
6200 | ||
48521003 IT |
6201 | /* PREFIX_VEX_0F38CF */ |
6202 | { | |
6203 | { Bad_Opcode }, | |
6204 | { Bad_Opcode }, | |
6205 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6206 | }, | |
6207 | ||
592a252b | 6208 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6209 | { |
592d1631 L |
6210 | { Bad_Opcode }, |
6211 | { Bad_Opcode }, | |
592a252b | 6212 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
8dcf1fad | 6219 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
8dcf1fad | 6226 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
8dcf1fad | 6233 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
8dcf1fad | 6240 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6241 | }, |
6242 | ||
f12dc422 L |
6243 | /* PREFIX_VEX_0F38F2 */ |
6244 | { | |
6245 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6246 | }, | |
6247 | ||
6248 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6249 | { | |
6250 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6251 | }, | |
6252 | ||
6253 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6254 | { | |
6255 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6256 | }, | |
6257 | ||
6258 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6259 | { | |
6260 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6261 | }, | |
6262 | ||
6c30d220 L |
6263 | /* PREFIX_VEX_0F38F5 */ |
6264 | { | |
6265 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6266 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6267 | { Bad_Opcode }, | |
6268 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6269 | }, | |
6270 | ||
6271 | /* PREFIX_VEX_0F38F6 */ | |
6272 | { | |
6273 | { Bad_Opcode }, | |
6274 | { Bad_Opcode }, | |
6275 | { Bad_Opcode }, | |
6276 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6277 | }, | |
6278 | ||
f12dc422 L |
6279 | /* PREFIX_VEX_0F38F7 */ |
6280 | { | |
6281 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6282 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6283 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6284 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6285 | }, | |
6286 | ||
6287 | /* PREFIX_VEX_0F3A00 */ | |
6288 | { | |
6289 | { Bad_Opcode }, | |
6290 | { Bad_Opcode }, | |
6291 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6292 | }, | |
6293 | ||
6294 | /* PREFIX_VEX_0F3A01 */ | |
6295 | { | |
6296 | { Bad_Opcode }, | |
6297 | { Bad_Opcode }, | |
6298 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6299 | }, | |
6300 | ||
6301 | /* PREFIX_VEX_0F3A02 */ | |
6302 | { | |
6303 | { Bad_Opcode }, | |
6304 | { Bad_Opcode }, | |
6305 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6306 | }, |
6307 | ||
592a252b | 6308 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6309 | { |
592d1631 L |
6310 | { Bad_Opcode }, |
6311 | { Bad_Opcode }, | |
592a252b | 6312 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6313 | }, |
6314 | ||
592a252b | 6315 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6316 | { |
592d1631 L |
6317 | { Bad_Opcode }, |
6318 | { Bad_Opcode }, | |
592a252b | 6319 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6320 | }, |
6321 | ||
592a252b | 6322 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6323 | { |
592d1631 L |
6324 | { Bad_Opcode }, |
6325 | { Bad_Opcode }, | |
592a252b | 6326 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6327 | }, |
6328 | ||
592a252b | 6329 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6330 | { |
592d1631 L |
6331 | { Bad_Opcode }, |
6332 | { Bad_Opcode }, | |
ec6f095a | 6333 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6334 | }, |
6335 | ||
592a252b | 6336 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6337 | { |
592d1631 L |
6338 | { Bad_Opcode }, |
6339 | { Bad_Opcode }, | |
ec6f095a | 6340 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6341 | }, |
6342 | ||
592a252b | 6343 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6344 | { |
592d1631 L |
6345 | { Bad_Opcode }, |
6346 | { Bad_Opcode }, | |
ec6f095a | 6347 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6348 | }, |
6349 | ||
592a252b | 6350 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6351 | { |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
ec6f095a | 6354 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
ec6f095a | 6361 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
ec6f095a | 6368 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6369 | }, |
6370 | ||
592a252b | 6371 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6372 | { |
592d1631 L |
6373 | { Bad_Opcode }, |
6374 | { Bad_Opcode }, | |
ec6f095a | 6375 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6376 | }, |
6377 | ||
592a252b | 6378 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6379 | { |
592d1631 L |
6380 | { Bad_Opcode }, |
6381 | { Bad_Opcode }, | |
ec6f095a | 6382 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6383 | }, |
6384 | ||
592a252b | 6385 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6386 | { |
592d1631 L |
6387 | { Bad_Opcode }, |
6388 | { Bad_Opcode }, | |
592a252b | 6389 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6390 | }, |
6391 | ||
592a252b | 6392 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6393 | { |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
592a252b | 6396 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6397 | }, |
6398 | ||
592a252b | 6399 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6400 | { |
592d1631 L |
6401 | { Bad_Opcode }, |
6402 | { Bad_Opcode }, | |
592a252b | 6403 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6404 | }, |
6405 | ||
592a252b | 6406 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6407 | { |
592d1631 L |
6408 | { Bad_Opcode }, |
6409 | { Bad_Opcode }, | |
592a252b | 6410 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6411 | }, |
6412 | ||
592a252b | 6413 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6414 | { |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
592a252b | 6417 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6418 | }, |
6419 | ||
592a252b | 6420 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6421 | { |
592d1631 L |
6422 | { Bad_Opcode }, |
6423 | { Bad_Opcode }, | |
592a252b | 6424 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6425 | }, |
6426 | ||
592a252b | 6427 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6428 | { |
6429 | { Bad_Opcode }, | |
6430 | { Bad_Opcode }, | |
bf890a93 | 6431 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6432 | }, |
6433 | ||
592a252b | 6434 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6435 | { |
592d1631 L |
6436 | { Bad_Opcode }, |
6437 | { Bad_Opcode }, | |
592a252b | 6438 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6439 | }, |
6440 | ||
592a252b | 6441 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6442 | { |
592d1631 L |
6443 | { Bad_Opcode }, |
6444 | { Bad_Opcode }, | |
592a252b | 6445 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6446 | }, |
6447 | ||
592a252b | 6448 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6449 | { |
592d1631 L |
6450 | { Bad_Opcode }, |
6451 | { Bad_Opcode }, | |
592a252b | 6452 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6453 | }, |
6454 | ||
43234a1e L |
6455 | /* PREFIX_VEX_0F3A30 */ |
6456 | { | |
6457 | { Bad_Opcode }, | |
6458 | { Bad_Opcode }, | |
6459 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6460 | }, | |
6461 | ||
1ba585e8 IT |
6462 | /* PREFIX_VEX_0F3A31 */ |
6463 | { | |
6464 | { Bad_Opcode }, | |
6465 | { Bad_Opcode }, | |
6466 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6467 | }, | |
6468 | ||
43234a1e L |
6469 | /* PREFIX_VEX_0F3A32 */ |
6470 | { | |
6471 | { Bad_Opcode }, | |
6472 | { Bad_Opcode }, | |
6473 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6474 | }, | |
6475 | ||
1ba585e8 IT |
6476 | /* PREFIX_VEX_0F3A33 */ |
6477 | { | |
6478 | { Bad_Opcode }, | |
6479 | { Bad_Opcode }, | |
6480 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6481 | }, | |
6482 | ||
6c30d220 L |
6483 | /* PREFIX_VEX_0F3A38 */ |
6484 | { | |
6485 | { Bad_Opcode }, | |
6486 | { Bad_Opcode }, | |
6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6488 | }, | |
6489 | ||
6490 | /* PREFIX_VEX_0F3A39 */ | |
6491 | { | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6495 | }, | |
6496 | ||
592a252b | 6497 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6498 | { |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
ec6f095a | 6501 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6502 | }, |
6503 | ||
592a252b | 6504 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6505 | { |
592d1631 L |
6506 | { Bad_Opcode }, |
6507 | { Bad_Opcode }, | |
592a252b | 6508 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6509 | }, |
6510 | ||
592a252b | 6511 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6512 | { |
592d1631 L |
6513 | { Bad_Opcode }, |
6514 | { Bad_Opcode }, | |
ec6f095a | 6515 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6516 | }, |
6517 | ||
592a252b | 6518 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6519 | { |
592d1631 L |
6520 | { Bad_Opcode }, |
6521 | { Bad_Opcode }, | |
ff1982d5 | 6522 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6523 | }, |
6524 | ||
6c30d220 L |
6525 | /* PREFIX_VEX_0F3A46 */ |
6526 | { | |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6530 | }, | |
6531 | ||
592a252b | 6532 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6533 | { |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
592a252b | 6536 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6537 | }, |
6538 | ||
592a252b | 6539 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6540 | { |
6541 | { Bad_Opcode }, | |
6542 | { Bad_Opcode }, | |
592a252b | 6543 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6544 | }, |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
592a252b | 6550 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
592a252b | 6557 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6558 | }, |
6559 | ||
592a252b | 6560 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6561 | { |
592d1631 L |
6562 | { Bad_Opcode }, |
6563 | { Bad_Opcode }, | |
6c30d220 | 6564 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6565 | }, |
6566 | ||
592a252b | 6567 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6568 | { |
592d1631 L |
6569 | { Bad_Opcode }, |
6570 | { Bad_Opcode }, | |
3a2430e0 | 6571 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6572 | }, |
6573 | ||
592a252b | 6574 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6575 | { |
592d1631 L |
6576 | { Bad_Opcode }, |
6577 | { Bad_Opcode }, | |
3a2430e0 | 6578 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6579 | }, |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6582 | { |
592d1631 L |
6583 | { Bad_Opcode }, |
6584 | { Bad_Opcode }, | |
3a2430e0 | 6585 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6589 | { |
592d1631 L |
6590 | { Bad_Opcode }, |
6591 | { Bad_Opcode }, | |
3a2430e0 | 6592 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
592a252b | 6599 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6600 | { Bad_Opcode }, |
c0f3af97 L |
6601 | }, |
6602 | ||
592a252b | 6603 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6604 | { |
592d1631 L |
6605 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, | |
592a252b | 6607 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6608 | }, |
6609 | ||
592a252b | 6610 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6611 | { |
592d1631 L |
6612 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, | |
592a252b | 6614 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6615 | }, |
6616 | ||
592a252b | 6617 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6618 | { |
592d1631 L |
6619 | { Bad_Opcode }, |
6620 | { Bad_Opcode }, | |
592a252b | 6621 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6622 | }, |
a5ff0eb2 | 6623 | |
592a252b | 6624 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6625 | { |
592d1631 L |
6626 | { Bad_Opcode }, |
6627 | { Bad_Opcode }, | |
3a2430e0 | 6628 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6629 | }, |
6630 | ||
592a252b | 6631 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6632 | { |
592d1631 L |
6633 | { Bad_Opcode }, |
6634 | { Bad_Opcode }, | |
3a2430e0 | 6635 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6636 | }, |
6637 | ||
592a252b | 6638 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6639 | { |
592d1631 L |
6640 | { Bad_Opcode }, |
6641 | { Bad_Opcode }, | |
592a252b | 6642 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6643 | }, |
6644 | ||
592a252b | 6645 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6646 | { |
592d1631 L |
6647 | { Bad_Opcode }, |
6648 | { Bad_Opcode }, | |
592a252b | 6649 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6650 | }, |
6651 | ||
592a252b | 6652 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6653 | { |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
3a2430e0 | 6656 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6657 | }, |
6658 | ||
592a252b | 6659 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6660 | { |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
3a2430e0 | 6663 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6664 | }, |
6665 | ||
592a252b | 6666 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6667 | { |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
592a252b | 6670 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6671 | }, |
6672 | ||
592a252b | 6673 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6674 | { |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
592a252b | 6677 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6678 | }, |
6679 | ||
592a252b | 6680 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6681 | { |
592d1631 L |
6682 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, | |
3a2430e0 | 6684 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6685 | }, |
6686 | ||
592a252b | 6687 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6688 | { |
592d1631 L |
6689 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, | |
3a2430e0 | 6691 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6692 | }, |
6693 | ||
592a252b | 6694 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6695 | { |
592d1631 L |
6696 | { Bad_Opcode }, |
6697 | { Bad_Opcode }, | |
592a252b | 6698 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6699 | }, |
6700 | ||
592a252b | 6701 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6702 | { |
592d1631 L |
6703 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, | |
592a252b | 6705 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6706 | }, |
6707 | ||
592a252b | 6708 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6709 | { |
592d1631 L |
6710 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, | |
3a2430e0 | 6712 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6713 | { Bad_Opcode }, |
922d8de8 DR |
6714 | }, |
6715 | ||
592a252b | 6716 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6717 | { |
592d1631 L |
6718 | { Bad_Opcode }, |
6719 | { Bad_Opcode }, | |
3a2430e0 | 6720 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6721 | }, |
6722 | ||
592a252b | 6723 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6724 | { |
592d1631 L |
6725 | { Bad_Opcode }, |
6726 | { Bad_Opcode }, | |
592a252b | 6727 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6728 | }, |
6729 | ||
592a252b | 6730 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6731 | { |
592d1631 L |
6732 | { Bad_Opcode }, |
6733 | { Bad_Opcode }, | |
592a252b | 6734 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6735 | }, |
6736 | ||
48521003 IT |
6737 | /* PREFIX_VEX_0F3ACE */ |
6738 | { | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
6741 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6742 | }, | |
6743 | ||
6744 | /* PREFIX_VEX_0F3ACF */ | |
6745 | { | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6749 | }, | |
6750 | ||
592a252b | 6751 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6752 | { |
592d1631 L |
6753 | { Bad_Opcode }, |
6754 | { Bad_Opcode }, | |
592a252b | 6755 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6756 | }, |
6c30d220 L |
6757 | |
6758 | /* PREFIX_VEX_0F3AF0 */ | |
6759 | { | |
6760 | { Bad_Opcode }, | |
6761 | { Bad_Opcode }, | |
6762 | { Bad_Opcode }, | |
6763 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6764 | }, | |
43234a1e L |
6765 | |
6766 | #define NEED_PREFIX_TABLE | |
6767 | #include "i386-dis-evex.h" | |
6768 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6769 | }; |
6770 | ||
6771 | static const struct dis386 x86_64_table[][2] = { | |
6772 | /* X86_64_06 */ | |
6773 | { | |
bf890a93 | 6774 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6775 | }, |
6776 | ||
6777 | /* X86_64_07 */ | |
6778 | { | |
bf890a93 | 6779 | { "popP", { es }, 0 }, |
c0f3af97 L |
6780 | }, |
6781 | ||
6782 | /* X86_64_0D */ | |
6783 | { | |
bf890a93 | 6784 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6785 | }, |
6786 | ||
6787 | /* X86_64_16 */ | |
6788 | { | |
bf890a93 | 6789 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6790 | }, |
6791 | ||
6792 | /* X86_64_17 */ | |
6793 | { | |
bf890a93 | 6794 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6795 | }, |
6796 | ||
6797 | /* X86_64_1E */ | |
6798 | { | |
bf890a93 | 6799 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6800 | }, |
6801 | ||
6802 | /* X86_64_1F */ | |
6803 | { | |
bf890a93 | 6804 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6805 | }, |
6806 | ||
6807 | /* X86_64_27 */ | |
6808 | { | |
bf890a93 | 6809 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6810 | }, |
6811 | ||
6812 | /* X86_64_2F */ | |
6813 | { | |
bf890a93 | 6814 | { "das", { XX }, 0 }, |
c0f3af97 L |
6815 | }, |
6816 | ||
6817 | /* X86_64_37 */ | |
6818 | { | |
bf890a93 | 6819 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_3F */ | |
6823 | { | |
bf890a93 | 6824 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6825 | }, |
6826 | ||
6827 | /* X86_64_60 */ | |
6828 | { | |
bf890a93 | 6829 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6830 | }, |
6831 | ||
6832 | /* X86_64_61 */ | |
6833 | { | |
bf890a93 | 6834 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6835 | }, |
6836 | ||
6837 | /* X86_64_62 */ | |
6838 | { | |
6839 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6840 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6841 | }, |
6842 | ||
6843 | /* X86_64_63 */ | |
6844 | { | |
bf890a93 IT |
6845 | { "arpl", { Ew, Gw }, 0 }, |
6846 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6847 | }, |
6848 | ||
6849 | /* X86_64_6D */ | |
6850 | { | |
bf890a93 IT |
6851 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6852 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6853 | }, |
6854 | ||
6855 | /* X86_64_6F */ | |
6856 | { | |
bf890a93 IT |
6857 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6858 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6859 | }, |
6860 | ||
d039fef3 | 6861 | /* X86_64_82 */ |
8b89fe14 | 6862 | { |
de194d85 | 6863 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6864 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6865 | }, |
6866 | ||
c0f3af97 L |
6867 | /* X86_64_9A */ |
6868 | { | |
bf890a93 | 6869 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6870 | }, |
6871 | ||
6872 | /* X86_64_C4 */ | |
6873 | { | |
6874 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6875 | { VEX_C4_TABLE (VEX_0F) }, | |
6876 | }, | |
6877 | ||
6878 | /* X86_64_C5 */ | |
6879 | { | |
6880 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6881 | { VEX_C5_TABLE (VEX_0F) }, | |
6882 | }, | |
6883 | ||
6884 | /* X86_64_CE */ | |
6885 | { | |
bf890a93 | 6886 | { "into", { XX }, 0 }, |
c0f3af97 L |
6887 | }, |
6888 | ||
6889 | /* X86_64_D4 */ | |
6890 | { | |
bf890a93 | 6891 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6892 | }, |
6893 | ||
6894 | /* X86_64_D5 */ | |
6895 | { | |
bf890a93 | 6896 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6897 | }, |
6898 | ||
a72d2af2 L |
6899 | /* X86_64_E8 */ |
6900 | { | |
6901 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6902 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6903 | }, |
6904 | ||
6905 | /* X86_64_E9 */ | |
6906 | { | |
6907 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6908 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6909 | }, |
6910 | ||
c0f3af97 L |
6911 | /* X86_64_EA */ |
6912 | { | |
bf890a93 | 6913 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6914 | }, |
6915 | ||
6916 | /* X86_64_0F01_REG_0 */ | |
6917 | { | |
bf890a93 IT |
6918 | { "sgdt{Q|IQ}", { M }, 0 }, |
6919 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6920 | }, |
6921 | ||
6922 | /* X86_64_0F01_REG_1 */ | |
6923 | { | |
bf890a93 IT |
6924 | { "sidt{Q|IQ}", { M }, 0 }, |
6925 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6926 | }, |
6927 | ||
6928 | /* X86_64_0F01_REG_2 */ | |
6929 | { | |
bf890a93 IT |
6930 | { "lgdt{Q|Q}", { M }, 0 }, |
6931 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6932 | }, |
6933 | ||
6934 | /* X86_64_0F01_REG_3 */ | |
6935 | { | |
bf890a93 IT |
6936 | { "lidt{Q|Q}", { M }, 0 }, |
6937 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6938 | }, |
6939 | }; | |
6940 | ||
6941 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6942 | |
6943 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6944 | { |
6945 | /* 00 */ | |
507bd325 L |
6946 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6947 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6948 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6949 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6950 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6951 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6952 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6953 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6954 | /* 08 */ |
507bd325 L |
6955 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6956 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6957 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6958 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6959 | { Bad_Opcode }, |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
f88c9eb0 SP |
6963 | /* 10 */ |
6964 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6965 | { Bad_Opcode }, |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
f88c9eb0 SP |
6968 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6969 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6970 | { Bad_Opcode }, |
f88c9eb0 SP |
6971 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6972 | /* 18 */ | |
592d1631 L |
6973 | { Bad_Opcode }, |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
507bd325 L |
6977 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6978 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6979 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6980 | { Bad_Opcode }, |
f88c9eb0 SP |
6981 | /* 20 */ |
6982 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6983 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6984 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6985 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6986 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6987 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
f88c9eb0 SP |
6990 | /* 28 */ |
6991 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6992 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6993 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6994 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6995 | { Bad_Opcode }, |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
f88c9eb0 SP |
6999 | /* 30 */ |
7000 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7001 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7002 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7003 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7004 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7005 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7006 | { Bad_Opcode }, |
f88c9eb0 SP |
7007 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7008 | /* 38 */ | |
7009 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7010 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7011 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7017 | /* 40 */ | |
7018 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7019 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7020 | { Bad_Opcode }, |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
f88c9eb0 | 7026 | /* 48 */ |
592d1631 L |
7027 | { Bad_Opcode }, |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
f88c9eb0 | 7035 | /* 50 */ |
592d1631 L |
7036 | { Bad_Opcode }, |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
f88c9eb0 | 7044 | /* 58 */ |
592d1631 L |
7045 | { Bad_Opcode }, |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
f88c9eb0 | 7053 | /* 60 */ |
592d1631 L |
7054 | { Bad_Opcode }, |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
f88c9eb0 | 7062 | /* 68 */ |
592d1631 L |
7063 | { Bad_Opcode }, |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
f88c9eb0 | 7071 | /* 70 */ |
592d1631 L |
7072 | { Bad_Opcode }, |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
f88c9eb0 | 7080 | /* 78 */ |
592d1631 L |
7081 | { Bad_Opcode }, |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
f88c9eb0 SP |
7089 | /* 80 */ |
7090 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7091 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7092 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7093 | { Bad_Opcode }, |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
f88c9eb0 | 7098 | /* 88 */ |
592d1631 L |
7099 | { Bad_Opcode }, |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
f88c9eb0 | 7107 | /* 90 */ |
592d1631 L |
7108 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
f88c9eb0 | 7116 | /* 98 */ |
592d1631 L |
7117 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
f88c9eb0 | 7125 | /* a0 */ |
592d1631 L |
7126 | { Bad_Opcode }, |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
f88c9eb0 | 7134 | /* a8 */ |
592d1631 L |
7135 | { Bad_Opcode }, |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
f88c9eb0 | 7143 | /* b0 */ |
592d1631 L |
7144 | { Bad_Opcode }, |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
f88c9eb0 | 7152 | /* b8 */ |
592d1631 L |
7153 | { Bad_Opcode }, |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
f88c9eb0 | 7161 | /* c0 */ |
592d1631 L |
7162 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
f88c9eb0 | 7170 | /* c8 */ |
a0046408 L |
7171 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7172 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7173 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7174 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7175 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7176 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7177 | { Bad_Opcode }, |
48521003 | 7178 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7179 | /* d0 */ |
592d1631 L |
7180 | { Bad_Opcode }, |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
f88c9eb0 | 7188 | /* d8 */ |
592d1631 L |
7189 | { Bad_Opcode }, |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
f88c9eb0 SP |
7192 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7193 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7194 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7195 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7196 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7197 | /* e0 */ | |
592d1631 L |
7198 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
f88c9eb0 | 7206 | /* e8 */ |
592d1631 L |
7207 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
f88c9eb0 SP |
7215 | /* f0 */ |
7216 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7217 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7218 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
603555e5 | 7221 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7222 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7223 | { Bad_Opcode }, |
f88c9eb0 | 7224 | /* f8 */ |
c0a30a9f L |
7225 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7226 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7227 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
f88c9eb0 SP |
7233 | }, |
7234 | /* THREE_BYTE_0F3A */ | |
7235 | { | |
7236 | /* 00 */ | |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
f88c9eb0 SP |
7245 | /* 08 */ |
7246 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7247 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7248 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7251 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7253 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7254 | /* 10 */ |
592d1631 L |
7255 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
f88c9eb0 SP |
7259 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7260 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7261 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7263 | /* 18 */ | |
592d1631 L |
7264 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
f88c9eb0 SP |
7272 | /* 20 */ |
7273 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7274 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7275 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7276 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
f88c9eb0 | 7281 | /* 28 */ |
592d1631 L |
7282 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
f88c9eb0 | 7290 | /* 30 */ |
592d1631 L |
7291 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
f88c9eb0 | 7299 | /* 38 */ |
592d1631 L |
7300 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
f88c9eb0 SP |
7308 | /* 40 */ |
7309 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7310 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7311 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7312 | { Bad_Opcode }, |
f88c9eb0 | 7313 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
f88c9eb0 | 7317 | /* 48 */ |
592d1631 L |
7318 | { Bad_Opcode }, |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
f88c9eb0 | 7326 | /* 50 */ |
592d1631 L |
7327 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
f88c9eb0 | 7335 | /* 58 */ |
592d1631 L |
7336 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
f88c9eb0 SP |
7344 | /* 60 */ |
7345 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7346 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7347 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7348 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7349 | { Bad_Opcode }, |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
f88c9eb0 | 7353 | /* 68 */ |
592d1631 L |
7354 | { Bad_Opcode }, |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
f88c9eb0 | 7362 | /* 70 */ |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
f88c9eb0 | 7371 | /* 78 */ |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
f88c9eb0 | 7380 | /* 80 */ |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
f88c9eb0 | 7389 | /* 88 */ |
592d1631 L |
7390 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
f88c9eb0 | 7398 | /* 90 */ |
592d1631 L |
7399 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
f88c9eb0 | 7407 | /* 98 */ |
592d1631 L |
7408 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
f88c9eb0 | 7416 | /* a0 */ |
592d1631 L |
7417 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
f88c9eb0 | 7425 | /* a8 */ |
592d1631 L |
7426 | { Bad_Opcode }, |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
f88c9eb0 | 7434 | /* b0 */ |
592d1631 L |
7435 | { Bad_Opcode }, |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
f88c9eb0 | 7443 | /* b8 */ |
592d1631 L |
7444 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
f88c9eb0 | 7452 | /* c0 */ |
592d1631 L |
7453 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
f88c9eb0 | 7461 | /* c8 */ |
592d1631 L |
7462 | { Bad_Opcode }, |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
a0046408 | 7466 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7467 | { Bad_Opcode }, |
48521003 IT |
7468 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7469 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7470 | /* d0 */ |
592d1631 L |
7471 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
f88c9eb0 | 7479 | /* d8 */ |
592d1631 L |
7480 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
f88c9eb0 SP |
7487 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7488 | /* e0 */ | |
592d1631 L |
7489 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
592d1631 L |
7494 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
85f10a01 | 7497 | /* e8 */ |
592d1631 L |
7498 | { Bad_Opcode }, |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
85f10a01 | 7506 | /* f0 */ |
592d1631 L |
7507 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
85f10a01 | 7515 | /* f8 */ |
592d1631 L |
7516 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
85f10a01 | 7524 | }, |
f88c9eb0 SP |
7525 | }; |
7526 | ||
7527 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7528 | /* XOP_08 */ |
85f10a01 MM |
7529 | { |
7530 | /* 00 */ | |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
85f10a01 | 7539 | /* 08 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
85f10a01 | 7548 | /* 10 */ |
3929df09 | 7549 | { Bad_Opcode }, |
592d1631 L |
7550 | { Bad_Opcode }, |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
85f10a01 | 7557 | /* 18 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
85f10a01 | 7566 | /* 20 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
85f10a01 | 7575 | /* 28 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
c0f3af97 | 7584 | /* 30 */ |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
c0f3af97 | 7593 | /* 38 */ |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
c0f3af97 | 7602 | /* 40 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | /* 48 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
c0f3af97 | 7620 | /* 50 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
85f10a01 | 7629 | /* 58 */ |
592d1631 L |
7630 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
c1e679ec | 7638 | /* 60 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
c0f3af97 | 7647 | /* 68 */ |
592d1631 L |
7648 | { Bad_Opcode }, |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
85f10a01 | 7656 | /* 70 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
85f10a01 | 7665 | /* 78 */ |
592d1631 L |
7666 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
85f10a01 | 7674 | /* 80 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
3a2430e0 JB |
7680 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7681 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7682 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7683 | /* 88 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
3a2430e0 JB |
7690 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7691 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7692 | /* 90 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
3a2430e0 JB |
7698 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7699 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7700 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7701 | /* 98 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
3a2430e0 JB |
7708 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7709 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7710 | /* a0 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
3a2430e0 JB |
7713 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7714 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7715 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, | |
3a2430e0 | 7717 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7718 | { Bad_Opcode }, |
5dd85c99 | 7719 | /* a8 */ |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
5dd85c99 | 7728 | /* b0 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
3a2430e0 | 7735 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7736 | { Bad_Opcode }, |
5dd85c99 | 7737 | /* b8 */ |
592d1631 L |
7738 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
5dd85c99 | 7746 | /* c0 */ |
bf890a93 IT |
7747 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7748 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7749 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7750 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7751 | { Bad_Opcode }, |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
5dd85c99 | 7755 | /* c8 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
ff688e1f L |
7760 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7761 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7762 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7763 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7764 | /* d0 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
5dd85c99 | 7773 | /* d8 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
5dd85c99 | 7782 | /* e0 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
5dd85c99 | 7791 | /* e8 */ |
592d1631 L |
7792 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
ff688e1f L |
7796 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7797 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7798 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7799 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7800 | /* f0 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
5dd85c99 | 7809 | /* f8 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
5dd85c99 SP |
7818 | }, |
7819 | /* XOP_09 */ | |
7820 | { | |
7821 | /* 00 */ | |
592d1631 | 7822 | { Bad_Opcode }, |
2a2a0f38 QN |
7823 | { REG_TABLE (REG_XOP_TBM_01) }, |
7824 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7825 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
5dd85c99 | 7830 | /* 08 */ |
592d1631 L |
7831 | { Bad_Opcode }, |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
5dd85c99 | 7839 | /* 10 */ |
592d1631 L |
7840 | { Bad_Opcode }, |
7841 | { Bad_Opcode }, | |
5dd85c99 | 7842 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7843 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
5dd85c99 | 7848 | /* 18 */ |
592d1631 L |
7849 | { Bad_Opcode }, |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
5dd85c99 | 7857 | /* 20 */ |
592d1631 L |
7858 | { Bad_Opcode }, |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
5dd85c99 | 7866 | /* 28 */ |
592d1631 L |
7867 | { Bad_Opcode }, |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
5dd85c99 | 7875 | /* 30 */ |
592d1631 L |
7876 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
5dd85c99 | 7884 | /* 38 */ |
592d1631 L |
7885 | { Bad_Opcode }, |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
5dd85c99 | 7893 | /* 40 */ |
592d1631 L |
7894 | { Bad_Opcode }, |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
5dd85c99 | 7902 | /* 48 */ |
592d1631 L |
7903 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
5dd85c99 | 7911 | /* 50 */ |
592d1631 L |
7912 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
5dd85c99 | 7920 | /* 58 */ |
592d1631 L |
7921 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
5dd85c99 | 7929 | /* 60 */ |
592d1631 L |
7930 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
5dd85c99 | 7938 | /* 68 */ |
592d1631 L |
7939 | { Bad_Opcode }, |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
5dd85c99 | 7947 | /* 70 */ |
592d1631 L |
7948 | { Bad_Opcode }, |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
5dd85c99 | 7956 | /* 78 */ |
592d1631 L |
7957 | { Bad_Opcode }, |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
5dd85c99 | 7965 | /* 80 */ |
592a252b L |
7966 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7967 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7968 | { "vfrczss", { XM, EXd }, 0 }, |
7969 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7970 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
5dd85c99 | 7974 | /* 88 */ |
592d1631 L |
7975 | { Bad_Opcode }, |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
5dd85c99 | 7983 | /* 90 */ |
bf890a93 IT |
7984 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7985 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7986 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7987 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7988 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7989 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7990 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7991 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7992 | /* 98 */ |
bf890a93 IT |
7993 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7994 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7995 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7996 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7997 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
5dd85c99 | 8001 | /* a0 */ |
592d1631 L |
8002 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
5dd85c99 | 8010 | /* a8 */ |
592d1631 L |
8011 | { Bad_Opcode }, |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
5dd85c99 | 8019 | /* b0 */ |
592d1631 L |
8020 | { Bad_Opcode }, |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
5dd85c99 | 8028 | /* b8 */ |
592d1631 L |
8029 | { Bad_Opcode }, |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
5dd85c99 | 8037 | /* c0 */ |
592d1631 | 8038 | { Bad_Opcode }, |
bf890a93 IT |
8039 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8040 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8041 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8042 | { Bad_Opcode }, |
8043 | { Bad_Opcode }, | |
bf890a93 IT |
8044 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8045 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8046 | /* c8 */ |
592d1631 L |
8047 | { Bad_Opcode }, |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
bf890a93 | 8050 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8051 | { Bad_Opcode }, |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
5dd85c99 | 8055 | /* d0 */ |
592d1631 | 8056 | { Bad_Opcode }, |
bf890a93 IT |
8057 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8058 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8059 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8060 | { Bad_Opcode }, |
8061 | { Bad_Opcode }, | |
bf890a93 IT |
8062 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8063 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8064 | /* d8 */ |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
bf890a93 | 8068 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8069 | { Bad_Opcode }, |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
5dd85c99 | 8073 | /* e0 */ |
592d1631 | 8074 | { Bad_Opcode }, |
bf890a93 IT |
8075 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8076 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8077 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8078 | { Bad_Opcode }, |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
4e7d34a6 | 8082 | /* e8 */ |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
4e7d34a6 | 8091 | /* f0 */ |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
4e7d34a6 | 8100 | /* f8 */ |
592d1631 L |
8101 | { Bad_Opcode }, |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
4e7d34a6 | 8109 | }, |
f88c9eb0 | 8110 | /* XOP_0A */ |
4e7d34a6 L |
8111 | { |
8112 | /* 00 */ | |
592d1631 L |
8113 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
4e7d34a6 | 8121 | /* 08 */ |
592d1631 L |
8122 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
4e7d34a6 | 8130 | /* 10 */ |
bf890a93 | 8131 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8132 | { Bad_Opcode }, |
f88c9eb0 | 8133 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8134 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
4e7d34a6 | 8139 | /* 18 */ |
592d1631 L |
8140 | { Bad_Opcode }, |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
4e7d34a6 | 8148 | /* 20 */ |
592d1631 L |
8149 | { Bad_Opcode }, |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
4e7d34a6 | 8157 | /* 28 */ |
592d1631 L |
8158 | { Bad_Opcode }, |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
4e7d34a6 | 8166 | /* 30 */ |
592d1631 L |
8167 | { Bad_Opcode }, |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
c0f3af97 | 8175 | /* 38 */ |
592d1631 L |
8176 | { Bad_Opcode }, |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
c0f3af97 | 8184 | /* 40 */ |
592d1631 L |
8185 | { Bad_Opcode }, |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
c1e679ec | 8193 | /* 48 */ |
592d1631 L |
8194 | { Bad_Opcode }, |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
c1e679ec | 8202 | /* 50 */ |
592d1631 L |
8203 | { Bad_Opcode }, |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
4e7d34a6 | 8211 | /* 58 */ |
592d1631 L |
8212 | { Bad_Opcode }, |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
4e7d34a6 | 8220 | /* 60 */ |
592d1631 L |
8221 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
4e7d34a6 | 8229 | /* 68 */ |
592d1631 L |
8230 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
4e7d34a6 | 8238 | /* 70 */ |
592d1631 L |
8239 | { Bad_Opcode }, |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
4e7d34a6 | 8247 | /* 78 */ |
592d1631 L |
8248 | { Bad_Opcode }, |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
4e7d34a6 | 8256 | /* 80 */ |
592d1631 L |
8257 | { Bad_Opcode }, |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
4e7d34a6 | 8265 | /* 88 */ |
592d1631 L |
8266 | { Bad_Opcode }, |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
4e7d34a6 | 8274 | /* 90 */ |
592d1631 L |
8275 | { Bad_Opcode }, |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
4e7d34a6 | 8283 | /* 98 */ |
592d1631 L |
8284 | { Bad_Opcode }, |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
4e7d34a6 | 8292 | /* a0 */ |
592d1631 L |
8293 | { Bad_Opcode }, |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
4e7d34a6 | 8301 | /* a8 */ |
592d1631 L |
8302 | { Bad_Opcode }, |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
d5d7db8e | 8310 | /* b0 */ |
592d1631 L |
8311 | { Bad_Opcode }, |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
85f10a01 | 8319 | /* b8 */ |
592d1631 L |
8320 | { Bad_Opcode }, |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
85f10a01 | 8328 | /* c0 */ |
592d1631 L |
8329 | { Bad_Opcode }, |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
85f10a01 | 8337 | /* c8 */ |
592d1631 L |
8338 | { Bad_Opcode }, |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
85f10a01 | 8346 | /* d0 */ |
592d1631 L |
8347 | { Bad_Opcode }, |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
85f10a01 | 8355 | /* d8 */ |
592d1631 L |
8356 | { Bad_Opcode }, |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
85f10a01 | 8364 | /* e0 */ |
592d1631 L |
8365 | { Bad_Opcode }, |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
85f10a01 | 8373 | /* e8 */ |
592d1631 L |
8374 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
85f10a01 | 8382 | /* f0 */ |
592d1631 L |
8383 | { Bad_Opcode }, |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
85f10a01 | 8391 | /* f8 */ |
592d1631 L |
8392 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
85f10a01 | 8400 | }, |
c0f3af97 L |
8401 | }; |
8402 | ||
8403 | static const struct dis386 vex_table[][256] = { | |
8404 | /* VEX_0F */ | |
85f10a01 MM |
8405 | { |
8406 | /* 00 */ | |
592d1631 L |
8407 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
85f10a01 | 8415 | /* 08 */ |
592d1631 L |
8416 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
c0f3af97 | 8424 | /* 10 */ |
592a252b L |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8428 | { MOD_TABLE (MOD_VEX_0F13) }, | |
ec6f095a L |
8429 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
8430 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, | |
592a252b L |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8432 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8433 | /* 18 */ |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
c0f3af97 | 8442 | /* 20 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
c0f3af97 | 8451 | /* 28 */ |
ec6f095a L |
8452 | { "vmovapX", { XM, EXx }, 0 }, |
8453 | { "vmovapX", { EXxS, XM }, 0 }, | |
592a252b L |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8455 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8458 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8460 | /* 30 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
4e7d34a6 | 8469 | /* 38 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
d5d7db8e | 8478 | /* 40 */ |
592d1631 | 8479 | { Bad_Opcode }, |
43234a1e L |
8480 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8481 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8482 | { Bad_Opcode }, |
43234a1e L |
8483 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8487 | /* 48 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
1ba585e8 | 8490 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8491 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8492 | { Bad_Opcode }, |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
d5d7db8e | 8496 | /* 50 */ |
592a252b L |
8497 | { MOD_TABLE (MOD_VEX_0F50) }, |
8498 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8499 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8500 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8501 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8502 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8503 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8504 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8505 | /* 58 */ |
592a252b L |
8506 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8507 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8508 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8509 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8510 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8514 | /* 60 */ |
592a252b L |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8516 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8517 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8519 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8520 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8521 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8523 | /* 68 */ |
592a252b L |
8524 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8525 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8532 | /* 70 */ |
592a252b L |
8533 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8534 | { REG_TABLE (REG_VEX_0F71) }, | |
8535 | { REG_TABLE (REG_VEX_0F72) }, | |
8536 | { REG_TABLE (REG_VEX_0F73) }, | |
8537 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8541 | /* 78 */ |
592d1631 L |
8542 | { Bad_Opcode }, |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
592a252b L |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8550 | /* 80 */ |
592d1631 L |
8551 | { Bad_Opcode }, |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
c0f3af97 | 8559 | /* 88 */ |
592d1631 L |
8560 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
c0f3af97 | 8568 | /* 90 */ |
43234a1e L |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8573 | { Bad_Opcode }, |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
c0f3af97 | 8577 | /* 98 */ |
43234a1e | 8578 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8579 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8580 | { Bad_Opcode }, |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
c0f3af97 | 8586 | /* a0 */ |
592d1631 L |
8587 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
c0f3af97 | 8595 | /* a8 */ |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
592a252b | 8602 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8603 | { Bad_Opcode }, |
c0f3af97 | 8604 | /* b0 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
c0f3af97 | 8613 | /* b8 */ |
592d1631 L |
8614 | { Bad_Opcode }, |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
c0f3af97 | 8622 | /* c0 */ |
592d1631 L |
8623 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, | |
592a252b | 8625 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8626 | { Bad_Opcode }, |
592a252b L |
8627 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8628 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8629 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8630 | { Bad_Opcode }, |
c0f3af97 | 8631 | /* c8 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
c0f3af97 | 8640 | /* d0 */ |
592a252b L |
8641 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8642 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8649 | /* d8 */ |
592a252b L |
8650 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8651 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8658 | /* e0 */ |
592a252b L |
8659 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8660 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8667 | /* e8 */ |
592a252b L |
8668 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8669 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8676 | /* f0 */ |
592a252b L |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8685 | /* f8 */ |
592a252b L |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8693 | { Bad_Opcode }, |
c0f3af97 L |
8694 | }, |
8695 | /* VEX_0F38 */ | |
8696 | { | |
8697 | /* 00 */ | |
592a252b L |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8706 | /* 08 */ |
592a252b L |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8715 | /* 10 */ |
592d1631 L |
8716 | { Bad_Opcode }, |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
592a252b | 8719 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8720 | { Bad_Opcode }, |
8721 | { Bad_Opcode }, | |
6c30d220 | 8722 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8723 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8724 | /* 18 */ |
592a252b L |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8728 | { Bad_Opcode }, |
592a252b L |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8732 | { Bad_Opcode }, |
c0f3af97 | 8733 | /* 20 */ |
592a252b L |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8740 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, | |
c0f3af97 | 8742 | /* 28 */ |
592a252b L |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8751 | /* 30 */ |
592a252b L |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8758 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8759 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8760 | /* 38 */ |
592a252b L |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8769 | /* 40 */ |
592a252b L |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8772 | { Bad_Opcode }, |
8773 | { Bad_Opcode }, | |
8774 | { Bad_Opcode }, | |
6c30d220 L |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8778 | /* 48 */ |
592d1631 L |
8779 | { Bad_Opcode }, |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
c0f3af97 | 8787 | /* 50 */ |
592d1631 L |
8788 | { Bad_Opcode }, |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
c0f3af97 | 8796 | /* 58 */ |
6c30d220 L |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8800 | { Bad_Opcode }, |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
c0f3af97 | 8805 | /* 60 */ |
592d1631 L |
8806 | { Bad_Opcode }, |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
c0f3af97 | 8814 | /* 68 */ |
592d1631 L |
8815 | { Bad_Opcode }, |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
c0f3af97 | 8823 | /* 70 */ |
592d1631 L |
8824 | { Bad_Opcode }, |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
c0f3af97 | 8832 | /* 78 */ |
6c30d220 L |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8835 | { Bad_Opcode }, |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
c0f3af97 | 8841 | /* 80 */ |
592d1631 L |
8842 | { Bad_Opcode }, |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
c0f3af97 | 8850 | /* 88 */ |
592d1631 L |
8851 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
6c30d220 | 8855 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8856 | { Bad_Opcode }, |
6c30d220 | 8857 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8858 | { Bad_Opcode }, |
c0f3af97 | 8859 | /* 90 */ |
6c30d220 L |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8864 | { Bad_Opcode }, |
8865 | { Bad_Opcode }, | |
592a252b L |
8866 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8868 | /* 98 */ |
592a252b L |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8870 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8875 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8876 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8877 | /* a0 */ |
592d1631 L |
8878 | { Bad_Opcode }, |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
592a252b L |
8884 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8886 | /* a8 */ |
592a252b L |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8895 | /* b0 */ |
592d1631 L |
8896 | { Bad_Opcode }, |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
8901 | { Bad_Opcode }, | |
592a252b L |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8904 | /* b8 */ |
592a252b L |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8913 | /* c0 */ |
592d1631 L |
8914 | { Bad_Opcode }, |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
c0f3af97 | 8922 | /* c8 */ |
592d1631 L |
8923 | { Bad_Opcode }, |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
48521003 | 8930 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8931 | /* d0 */ |
592d1631 L |
8932 | { Bad_Opcode }, |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
c0f3af97 | 8940 | /* d8 */ |
592d1631 L |
8941 | { Bad_Opcode }, |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
592a252b L |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8949 | /* e0 */ |
592d1631 L |
8950 | { Bad_Opcode }, |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
c0f3af97 | 8958 | /* e8 */ |
592d1631 L |
8959 | { Bad_Opcode }, |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
c0f3af97 | 8967 | /* f0 */ |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
f12dc422 L |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8971 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8972 | { Bad_Opcode }, |
6c30d220 L |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8975 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8976 | /* f8 */ |
592d1631 L |
8977 | { Bad_Opcode }, |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
c0f3af97 L |
8985 | }, |
8986 | /* VEX_0F3A */ | |
8987 | { | |
8988 | /* 00 */ | |
6c30d220 L |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8992 | { Bad_Opcode }, |
592a252b L |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8996 | { Bad_Opcode }, |
c0f3af97 | 8997 | /* 08 */ |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9006 | /* 10 */ |
592d1631 L |
9007 | { Bad_Opcode }, |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
592a252b L |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9015 | /* 18 */ |
592a252b L |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9018 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
592a252b | 9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9022 | { Bad_Opcode }, |
9023 | { Bad_Opcode }, | |
c0f3af97 | 9024 | /* 20 */ |
592a252b L |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9028 | { Bad_Opcode }, |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
c0f3af97 | 9033 | /* 28 */ |
592d1631 L |
9034 | { Bad_Opcode }, |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
c0f3af97 | 9042 | /* 30 */ |
43234a1e | 9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9047 | { Bad_Opcode }, |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
c0f3af97 | 9051 | /* 38 */ |
6c30d220 L |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9053 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9054 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
c0f3af97 | 9060 | /* 40 */ |
592a252b L |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9064 | { Bad_Opcode }, |
592a252b | 9065 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9066 | { Bad_Opcode }, |
6c30d220 | 9067 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9068 | { Bad_Opcode }, |
c0f3af97 | 9069 | /* 48 */ |
592a252b L |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
c0f3af97 | 9078 | /* 50 */ |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
c0f3af97 | 9087 | /* 58 */ |
592d1631 L |
9088 | { Bad_Opcode }, |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
592a252b L |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9096 | /* 60 */ |
592a252b L |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9101 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
c0f3af97 | 9105 | /* 68 */ |
592a252b L |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9114 | /* 70 */ |
592d1631 L |
9115 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
c0f3af97 | 9123 | /* 78 */ |
592a252b L |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9132 | /* 80 */ |
592d1631 L |
9133 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
c0f3af97 | 9141 | /* 88 */ |
592d1631 L |
9142 | { Bad_Opcode }, |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
c0f3af97 | 9150 | /* 90 */ |
592d1631 L |
9151 | { Bad_Opcode }, |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
c0f3af97 | 9159 | /* 98 */ |
592d1631 L |
9160 | { Bad_Opcode }, |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
c0f3af97 | 9168 | /* a0 */ |
592d1631 L |
9169 | { Bad_Opcode }, |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
c0f3af97 | 9177 | /* a8 */ |
592d1631 L |
9178 | { Bad_Opcode }, |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
c0f3af97 | 9186 | /* b0 */ |
592d1631 L |
9187 | { Bad_Opcode }, |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
c0f3af97 | 9195 | /* b8 */ |
592d1631 L |
9196 | { Bad_Opcode }, |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
c0f3af97 | 9204 | /* c0 */ |
592d1631 L |
9205 | { Bad_Opcode }, |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
c0f3af97 | 9213 | /* c8 */ |
592d1631 L |
9214 | { Bad_Opcode }, |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
48521003 IT |
9220 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9221 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9222 | /* d0 */ |
592d1631 L |
9223 | { Bad_Opcode }, |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
c0f3af97 | 9231 | /* d8 */ |
592d1631 L |
9232 | { Bad_Opcode }, |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
592a252b | 9239 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9240 | /* e0 */ |
592d1631 L |
9241 | { Bad_Opcode }, |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
c0f3af97 | 9249 | /* e8 */ |
592d1631 L |
9250 | { Bad_Opcode }, |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
c0f3af97 | 9258 | /* f0 */ |
6c30d220 | 9259 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9260 | { Bad_Opcode }, |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
c0f3af97 | 9267 | /* f8 */ |
592d1631 L |
9268 | { Bad_Opcode }, |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
c0f3af97 L |
9276 | }, |
9277 | }; | |
9278 | ||
43234a1e L |
9279 | #define NEED_OPCODE_TABLE |
9280 | #include "i386-dis-evex.h" | |
9281 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9282 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9283 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9284 | { |
ec6f095a | 9285 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9286 | }, |
9287 | ||
592a252b | 9288 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9289 | { |
ec6f095a | 9290 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9291 | }, |
9292 | ||
592a252b | 9293 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9294 | { |
ec6f095a | 9295 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9296 | }, |
9297 | ||
592a252b | 9298 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9299 | { |
ec6f095a | 9300 | { "vmovlpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9301 | }, |
9302 | ||
592a252b | 9303 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9304 | { |
ec6f095a | 9305 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9306 | }, |
9307 | ||
592a252b | 9308 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9309 | { |
ec6f095a | 9310 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9311 | }, |
9312 | ||
592a252b | 9313 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9314 | { |
ec6f095a | 9315 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9316 | }, |
9317 | ||
592a252b | 9318 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9319 | { |
ec6f095a | 9320 | { "vmovhpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9321 | }, |
9322 | ||
592a252b | 9323 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9324 | { |
bf890a93 IT |
9325 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9326 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9327 | }, |
9328 | ||
592a252b | 9329 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9330 | { |
bf890a93 IT |
9331 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9332 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9333 | }, |
9334 | ||
592a252b | 9335 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9336 | { |
9646c87b JB |
9337 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, |
9338 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9339 | }, |
9340 | ||
592a252b | 9341 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9342 | { |
9646c87b JB |
9343 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, |
9344 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9345 | }, |
9346 | ||
592a252b | 9347 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9348 | { |
9646c87b JB |
9349 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, |
9350 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9351 | }, |
9352 | ||
592a252b | 9353 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9354 | { |
9646c87b JB |
9355 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, |
9356 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9357 | }, |
9358 | ||
43234a1e L |
9359 | /* VEX_LEN_0F41_P_0 */ |
9360 | { | |
9361 | { Bad_Opcode }, | |
9362 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9363 | }, | |
1ba585e8 IT |
9364 | /* VEX_LEN_0F41_P_2 */ |
9365 | { | |
9366 | { Bad_Opcode }, | |
9367 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9368 | }, | |
43234a1e L |
9369 | /* VEX_LEN_0F42_P_0 */ |
9370 | { | |
9371 | { Bad_Opcode }, | |
9372 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9373 | }, | |
1ba585e8 IT |
9374 | /* VEX_LEN_0F42_P_2 */ |
9375 | { | |
9376 | { Bad_Opcode }, | |
9377 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9378 | }, | |
43234a1e L |
9379 | /* VEX_LEN_0F44_P_0 */ |
9380 | { | |
9381 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9382 | }, | |
1ba585e8 IT |
9383 | /* VEX_LEN_0F44_P_2 */ |
9384 | { | |
9385 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9386 | }, | |
43234a1e L |
9387 | /* VEX_LEN_0F45_P_0 */ |
9388 | { | |
9389 | { Bad_Opcode }, | |
9390 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9391 | }, | |
1ba585e8 IT |
9392 | /* VEX_LEN_0F45_P_2 */ |
9393 | { | |
9394 | { Bad_Opcode }, | |
9395 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9396 | }, | |
43234a1e L |
9397 | /* VEX_LEN_0F46_P_0 */ |
9398 | { | |
9399 | { Bad_Opcode }, | |
9400 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9401 | }, | |
1ba585e8 IT |
9402 | /* VEX_LEN_0F46_P_2 */ |
9403 | { | |
9404 | { Bad_Opcode }, | |
9405 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9406 | }, | |
43234a1e L |
9407 | /* VEX_LEN_0F47_P_0 */ |
9408 | { | |
9409 | { Bad_Opcode }, | |
9410 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9411 | }, | |
1ba585e8 IT |
9412 | /* VEX_LEN_0F47_P_2 */ |
9413 | { | |
9414 | { Bad_Opcode }, | |
9415 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9416 | }, | |
9417 | /* VEX_LEN_0F4A_P_0 */ | |
9418 | { | |
9419 | { Bad_Opcode }, | |
9420 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9421 | }, | |
9422 | /* VEX_LEN_0F4A_P_2 */ | |
9423 | { | |
9424 | { Bad_Opcode }, | |
9425 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9426 | }, | |
9427 | /* VEX_LEN_0F4B_P_0 */ | |
9428 | { | |
9429 | { Bad_Opcode }, | |
9430 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9431 | }, | |
43234a1e L |
9432 | /* VEX_LEN_0F4B_P_2 */ |
9433 | { | |
9434 | { Bad_Opcode }, | |
9435 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9436 | }, | |
9437 | ||
ec6f095a | 9438 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9439 | { |
ec6f095a | 9440 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9441 | }, |
9442 | ||
ec6f095a | 9443 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9444 | { |
ec6f095a L |
9445 | { "vzeroupper", { XX }, 0 }, |
9446 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9447 | }, |
9448 | ||
ec6f095a | 9449 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9450 | { |
ec6f095a | 9451 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9452 | }, |
9453 | ||
ec6f095a | 9454 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9455 | { |
ec6f095a | 9456 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9457 | }, |
9458 | ||
ec6f095a | 9459 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9460 | { |
ec6f095a | 9461 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9462 | }, |
9463 | ||
ec6f095a | 9464 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9465 | { |
ec6f095a | 9466 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9467 | }, |
9468 | ||
ec6f095a | 9469 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9470 | { |
ec6f095a | 9471 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9472 | }, |
9473 | ||
ec6f095a | 9474 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9475 | { |
ec6f095a | 9476 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9477 | }, |
9478 | ||
ec6f095a | 9479 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9480 | { |
ec6f095a | 9481 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9482 | }, |
9483 | ||
ec6f095a | 9484 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9485 | { |
ec6f095a | 9486 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9487 | }, |
9488 | ||
ec6f095a | 9489 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9490 | { |
58a211d2 | 9491 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9492 | }, |
9493 | ||
ec6f095a | 9494 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9495 | { |
ec6f095a | 9496 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9497 | }, |
9498 | ||
ec6f095a | 9499 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9500 | { |
ec6f095a | 9501 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9502 | }, |
9503 | ||
ec6f095a | 9504 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9505 | { |
58a211d2 | 9506 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9507 | }, |
9508 | ||
ec6f095a | 9509 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9510 | { |
9511 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9512 | }, | |
9513 | ||
1ba585e8 IT |
9514 | /* VEX_LEN_0F98_P_2 */ |
9515 | { | |
9516 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9517 | }, | |
9518 | ||
9519 | /* VEX_LEN_0F99_P_0 */ | |
9520 | { | |
9521 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9522 | }, | |
9523 | ||
9524 | /* VEX_LEN_0F99_P_2 */ | |
9525 | { | |
9526 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9527 | }, | |
9528 | ||
6c30d220 | 9529 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9530 | { |
ec6f095a | 9531 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9532 | }, |
9533 | ||
6c30d220 | 9534 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9535 | { |
ec6f095a | 9536 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9537 | }, |
9538 | ||
6c30d220 | 9539 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9540 | { |
b50c9f31 | 9541 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9542 | }, |
9543 | ||
6c30d220 | 9544 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9545 | { |
b50c9f31 | 9546 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9547 | }, |
9548 | ||
6c30d220 | 9549 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9550 | { |
ec6f095a | 9551 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9552 | }, |
9553 | ||
6c30d220 | 9554 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9555 | { |
ec6f095a | 9556 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9557 | }, |
9558 | ||
6c30d220 | 9559 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9560 | { |
6c30d220 L |
9561 | { Bad_Opcode }, |
9562 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9563 | }, |
9564 | ||
6c30d220 | 9565 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9566 | { |
6c30d220 L |
9567 | { Bad_Opcode }, |
9568 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9569 | }, |
9570 | ||
6c30d220 | 9571 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9572 | { |
6c30d220 L |
9573 | { Bad_Opcode }, |
9574 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9575 | }, |
9576 | ||
6c30d220 | 9577 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9578 | { |
6c30d220 L |
9579 | { Bad_Opcode }, |
9580 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9581 | }, |
9582 | ||
592a252b | 9583 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9584 | { |
ec6f095a | 9585 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9586 | }, |
9587 | ||
6c30d220 L |
9588 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9589 | { | |
9590 | { Bad_Opcode }, | |
9591 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9592 | }, | |
9593 | ||
592a252b | 9594 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9595 | { |
ec6f095a | 9596 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9597 | }, |
9598 | ||
f12dc422 L |
9599 | /* VEX_LEN_0F38F2_P_0 */ |
9600 | { | |
bf890a93 | 9601 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9602 | }, |
9603 | ||
9604 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9605 | { | |
bf890a93 | 9606 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9607 | }, |
9608 | ||
9609 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9610 | { | |
bf890a93 | 9611 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9612 | }, |
9613 | ||
9614 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9615 | { | |
bf890a93 | 9616 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9617 | }, |
9618 | ||
6c30d220 L |
9619 | /* VEX_LEN_0F38F5_P_0 */ |
9620 | { | |
bf890a93 | 9621 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9622 | }, |
9623 | ||
9624 | /* VEX_LEN_0F38F5_P_1 */ | |
9625 | { | |
bf890a93 | 9626 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9627 | }, |
9628 | ||
9629 | /* VEX_LEN_0F38F5_P_3 */ | |
9630 | { | |
bf890a93 | 9631 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9632 | }, |
9633 | ||
9634 | /* VEX_LEN_0F38F6_P_3 */ | |
9635 | { | |
bf890a93 | 9636 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9637 | }, |
9638 | ||
f12dc422 L |
9639 | /* VEX_LEN_0F38F7_P_0 */ |
9640 | { | |
bf890a93 | 9641 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9642 | }, |
9643 | ||
6c30d220 L |
9644 | /* VEX_LEN_0F38F7_P_1 */ |
9645 | { | |
bf890a93 | 9646 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9647 | }, |
9648 | ||
9649 | /* VEX_LEN_0F38F7_P_2 */ | |
9650 | { | |
bf890a93 | 9651 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9652 | }, |
9653 | ||
9654 | /* VEX_LEN_0F38F7_P_3 */ | |
9655 | { | |
bf890a93 | 9656 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9657 | }, |
9658 | ||
9659 | /* VEX_LEN_0F3A00_P_2 */ | |
9660 | { | |
9661 | { Bad_Opcode }, | |
9662 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9663 | }, | |
9664 | ||
9665 | /* VEX_LEN_0F3A01_P_2 */ | |
9666 | { | |
9667 | { Bad_Opcode }, | |
9668 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9669 | }, | |
9670 | ||
592a252b | 9671 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9672 | { |
592d1631 | 9673 | { Bad_Opcode }, |
592a252b | 9674 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9675 | }, |
9676 | ||
592a252b | 9677 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9678 | { |
b50c9f31 | 9679 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9680 | }, |
9681 | ||
592a252b | 9682 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9683 | { |
b50c9f31 | 9684 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9685 | }, |
9686 | ||
592a252b | 9687 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9688 | { |
bf890a93 | 9689 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9693 | { |
bf890a93 | 9694 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9695 | }, |
9696 | ||
592a252b | 9697 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9698 | { |
592d1631 | 9699 | { Bad_Opcode }, |
592a252b | 9700 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9701 | }, |
9702 | ||
592a252b | 9703 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9704 | { |
592d1631 | 9705 | { Bad_Opcode }, |
592a252b | 9706 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9707 | }, |
9708 | ||
592a252b | 9709 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9710 | { |
b50c9f31 | 9711 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9712 | }, |
9713 | ||
592a252b | 9714 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9715 | { |
ec6f095a | 9716 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9717 | }, |
9718 | ||
592a252b | 9719 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9720 | { |
bf890a93 | 9721 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9722 | }, |
9723 | ||
43234a1e L |
9724 | /* VEX_LEN_0F3A30_P_2 */ |
9725 | { | |
9726 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9727 | }, | |
9728 | ||
1ba585e8 IT |
9729 | /* VEX_LEN_0F3A31_P_2 */ |
9730 | { | |
9731 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9732 | }, | |
9733 | ||
43234a1e L |
9734 | /* VEX_LEN_0F3A32_P_2 */ |
9735 | { | |
9736 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9737 | }, | |
9738 | ||
1ba585e8 IT |
9739 | /* VEX_LEN_0F3A33_P_2 */ |
9740 | { | |
9741 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9742 | }, | |
9743 | ||
6c30d220 | 9744 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9745 | { |
6c30d220 L |
9746 | { Bad_Opcode }, |
9747 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9748 | }, |
9749 | ||
6c30d220 | 9750 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9751 | { |
6c30d220 L |
9752 | { Bad_Opcode }, |
9753 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9754 | }, | |
9755 | ||
9756 | /* VEX_LEN_0F3A41_P_2 */ | |
9757 | { | |
ec6f095a | 9758 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9759 | }, |
9760 | ||
6c30d220 | 9761 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9762 | { |
6c30d220 L |
9763 | { Bad_Opcode }, |
9764 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9765 | }, |
9766 | ||
592a252b | 9767 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9768 | { |
15c7c1d8 | 9769 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9770 | }, |
9771 | ||
592a252b | 9772 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9773 | { |
15c7c1d8 | 9774 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9778 | { |
ec6f095a | 9779 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9783 | { |
ec6f095a | 9784 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9785 | }, |
9786 | ||
592a252b | 9787 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9788 | { |
3a2430e0 | 9789 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9790 | }, |
9791 | ||
592a252b | 9792 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9793 | { |
3a2430e0 | 9794 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9795 | }, |
9796 | ||
592a252b | 9797 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9798 | { |
3a2430e0 | 9799 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9800 | }, |
9801 | ||
592a252b | 9802 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9803 | { |
3a2430e0 | 9804 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9805 | }, |
9806 | ||
592a252b | 9807 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9808 | { |
3a2430e0 | 9809 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9810 | }, |
9811 | ||
592a252b | 9812 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9813 | { |
3a2430e0 | 9814 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9815 | }, |
9816 | ||
592a252b | 9817 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9818 | { |
3a2430e0 | 9819 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9820 | }, |
9821 | ||
592a252b | 9822 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9823 | { |
3a2430e0 | 9824 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9825 | }, |
9826 | ||
592a252b | 9827 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9828 | { |
ec6f095a | 9829 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9830 | }, |
4c807e72 | 9831 | |
6c30d220 L |
9832 | /* VEX_LEN_0F3AF0_P_3 */ |
9833 | { | |
bf890a93 | 9834 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9835 | }, |
9836 | ||
ff688e1f L |
9837 | /* VEX_LEN_0FXOP_08_CC */ |
9838 | { | |
be92cb14 | 9839 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9840 | }, |
9841 | ||
9842 | /* VEX_LEN_0FXOP_08_CD */ | |
9843 | { | |
be92cb14 | 9844 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9845 | }, |
9846 | ||
9847 | /* VEX_LEN_0FXOP_08_CE */ | |
9848 | { | |
be92cb14 | 9849 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9850 | }, |
9851 | ||
9852 | /* VEX_LEN_0FXOP_08_CF */ | |
9853 | { | |
be92cb14 | 9854 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9855 | }, |
9856 | ||
9857 | /* VEX_LEN_0FXOP_08_EC */ | |
9858 | { | |
be92cb14 | 9859 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9860 | }, |
9861 | ||
9862 | /* VEX_LEN_0FXOP_08_ED */ | |
9863 | { | |
be92cb14 | 9864 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9865 | }, |
9866 | ||
9867 | /* VEX_LEN_0FXOP_08_EE */ | |
9868 | { | |
be92cb14 | 9869 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9870 | }, |
9871 | ||
9872 | /* VEX_LEN_0FXOP_08_EF */ | |
9873 | { | |
be92cb14 | 9874 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9875 | }, |
9876 | ||
592a252b | 9877 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9878 | { |
bf890a93 IT |
9879 | { "vfrczps", { XM, EXxmm }, 0 }, |
9880 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9881 | }, |
4c807e72 | 9882 | |
592a252b | 9883 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9884 | { |
bf890a93 IT |
9885 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9886 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9887 | }, |
331d2d0d L |
9888 | }; |
9889 | ||
04e2a182 L |
9890 | static const struct dis386 evex_len_table[][3] = { |
9891 | #define NEED_EVEX_LEN_TABLE | |
9892 | #include "i386-dis-evex.h" | |
9893 | #undef NEED_EVEX_LEN_TABLE | |
9894 | }; | |
9895 | ||
9e30b8e0 | 9896 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9897 | { |
9898 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9899 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9900 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9901 | }, |
9902 | { | |
9903 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9904 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9905 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9906 | }, |
9907 | { | |
9908 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9909 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9910 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9911 | }, |
9912 | { | |
9913 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9914 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9915 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9916 | }, |
9917 | { | |
9918 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9919 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9920 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9921 | }, |
9922 | { | |
9923 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9924 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9925 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9926 | }, |
9927 | { | |
ec6f095a L |
9928 | /* VEX_W_0F45_P_0_LEN_1 */ |
9929 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9930 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9931 | }, |
9932 | { | |
ec6f095a L |
9933 | /* VEX_W_0F45_P_2_LEN_1 */ |
9934 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9935 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9936 | }, |
9937 | { | |
ec6f095a L |
9938 | /* VEX_W_0F46_P_0_LEN_1 */ |
9939 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9940 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9941 | }, |
9942 | { | |
ec6f095a L |
9943 | /* VEX_W_0F46_P_2_LEN_1 */ |
9944 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9945 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9946 | }, |
9947 | { | |
ec6f095a L |
9948 | /* VEX_W_0F47_P_0_LEN_1 */ |
9949 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9950 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9951 | }, |
9952 | { | |
ec6f095a L |
9953 | /* VEX_W_0F47_P_2_LEN_1 */ |
9954 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9955 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9956 | }, |
9957 | { | |
ec6f095a L |
9958 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9959 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9960 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9961 | }, |
9962 | { | |
ec6f095a L |
9963 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9964 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9965 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9966 | }, |
9967 | { | |
ec6f095a L |
9968 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9969 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9970 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9971 | }, |
9972 | { | |
ec6f095a L |
9973 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9974 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9975 | }, |
9976 | { | |
ec6f095a L |
9977 | /* VEX_W_0F90_P_0_LEN_0 */ |
9978 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9979 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9980 | }, |
9981 | { | |
ec6f095a L |
9982 | /* VEX_W_0F90_P_2_LEN_0 */ |
9983 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9984 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9985 | }, |
9986 | { | |
ec6f095a L |
9987 | /* VEX_W_0F91_P_0_LEN_0 */ |
9988 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9989 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9990 | }, |
9991 | { | |
ec6f095a L |
9992 | /* VEX_W_0F91_P_2_LEN_0 */ |
9993 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9994 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9995 | }, |
9996 | { | |
ec6f095a L |
9997 | /* VEX_W_0F92_P_0_LEN_0 */ |
9998 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9999 | }, |
10000 | { | |
ec6f095a L |
10001 | /* VEX_W_0F92_P_2_LEN_0 */ |
10002 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 10003 | }, |
9e30b8e0 | 10004 | { |
ec6f095a L |
10005 | /* VEX_W_0F93_P_0_LEN_0 */ |
10006 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
10007 | }, |
10008 | { | |
ec6f095a L |
10009 | /* VEX_W_0F93_P_2_LEN_0 */ |
10010 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10011 | }, |
9e30b8e0 | 10012 | { |
ec6f095a L |
10013 | /* VEX_W_0F98_P_0_LEN_0 */ |
10014 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10015 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10016 | }, |
10017 | { | |
ec6f095a L |
10018 | /* VEX_W_0F98_P_2_LEN_0 */ |
10019 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10020 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10021 | }, |
10022 | { | |
ec6f095a L |
10023 | /* VEX_W_0F99_P_0_LEN_0 */ |
10024 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10025 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10026 | }, |
10027 | { | |
ec6f095a L |
10028 | /* VEX_W_0F99_P_2_LEN_0 */ |
10029 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10030 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10031 | }, |
9e30b8e0 | 10032 | { |
592a252b | 10033 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10034 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10035 | }, |
10036 | { | |
592a252b | 10037 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10038 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10039 | }, |
10040 | { | |
592a252b | 10041 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10042 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10043 | }, |
10044 | { | |
592a252b | 10045 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10046 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10047 | }, |
6c30d220 L |
10048 | { |
10049 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10050 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10051 | }, |
bcf2684f | 10052 | { |
6c30d220 | 10053 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10054 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10055 | }, |
9e30b8e0 | 10056 | { |
6c30d220 | 10057 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10058 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10059 | }, |
10060 | { | |
592a252b | 10061 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10062 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10063 | }, |
53aa04a0 | 10064 | { |
592a252b | 10065 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10066 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10067 | }, |
10068 | { | |
592a252b | 10069 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10070 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10071 | }, |
10072 | { | |
592a252b | 10073 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10074 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10075 | }, |
10076 | { | |
592a252b | 10077 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10078 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10079 | }, |
6c30d220 L |
10080 | { |
10081 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10082 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10083 | }, |
6c30d220 L |
10084 | { |
10085 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10086 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10087 | }, |
10088 | { | |
10089 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10090 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10091 | }, |
10092 | { | |
10093 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10094 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10095 | }, |
10096 | { | |
10097 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10098 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10099 | }, |
10100 | { | |
10101 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10102 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10103 | }, |
10104 | { | |
10105 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10106 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10107 | }, |
48521003 IT |
10108 | { |
10109 | /* VEX_W_0F38CF_P_2 */ | |
10110 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10111 | }, | |
6c30d220 L |
10112 | { |
10113 | /* VEX_W_0F3A00_P_2 */ | |
10114 | { Bad_Opcode }, | |
bf890a93 | 10115 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10116 | }, |
10117 | { | |
10118 | /* VEX_W_0F3A01_P_2 */ | |
10119 | { Bad_Opcode }, | |
bf890a93 | 10120 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10121 | }, |
10122 | { | |
10123 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10124 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10125 | }, |
9e30b8e0 | 10126 | { |
592a252b | 10127 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10128 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10129 | }, |
10130 | { | |
592a252b | 10131 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10132 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10133 | }, |
10134 | { | |
592a252b | 10135 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10136 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10137 | }, |
9e30b8e0 | 10138 | { |
592a252b | 10139 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10140 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10141 | }, |
10142 | { | |
592a252b | 10143 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10144 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10145 | }, |
43234a1e | 10146 | { |
1ba585e8 | 10147 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10148 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10149 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10150 | }, |
10151 | { | |
1ba585e8 | 10152 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10153 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10154 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10155 | }, |
10156 | { | |
10157 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10158 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10159 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10160 | }, |
1ba585e8 IT |
10161 | { |
10162 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10163 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10164 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10165 | }, |
6c30d220 L |
10166 | { |
10167 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10168 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10169 | }, |
10170 | { | |
10171 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10172 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10173 | }, |
6c30d220 L |
10174 | { |
10175 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10176 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10177 | }, |
a683cc34 | 10178 | { |
592a252b | 10179 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10180 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10181 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10182 | }, |
10183 | { | |
592a252b | 10184 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10185 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10186 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10187 | }, |
9e30b8e0 | 10188 | { |
592a252b | 10189 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10190 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10191 | }, |
10192 | { | |
592a252b | 10193 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10194 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10195 | }, |
10196 | { | |
592a252b | 10197 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10198 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10199 | }, |
48521003 IT |
10200 | { |
10201 | /* VEX_W_0F3ACE_P_2 */ | |
10202 | { Bad_Opcode }, | |
10203 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10204 | }, | |
10205 | { | |
10206 | /* VEX_W_0F3ACF_P_2 */ | |
10207 | { Bad_Opcode }, | |
10208 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10209 | }, | |
43234a1e L |
10210 | #define NEED_VEX_W_TABLE |
10211 | #include "i386-dis-evex.h" | |
10212 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
10213 | }; |
10214 | ||
10215 | static const struct dis386 mod_table[][2] = { | |
10216 | { | |
10217 | /* MOD_8D */ | |
bf890a93 | 10218 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10219 | }, |
42164a71 L |
10220 | { |
10221 | /* MOD_C6_REG_7 */ | |
10222 | { Bad_Opcode }, | |
10223 | { RM_TABLE (RM_C6_REG_7) }, | |
10224 | }, | |
10225 | { | |
10226 | /* MOD_C7_REG_7 */ | |
10227 | { Bad_Opcode }, | |
10228 | { RM_TABLE (RM_C7_REG_7) }, | |
10229 | }, | |
4a357820 MZ |
10230 | { |
10231 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 10232 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
10233 | }, |
10234 | { | |
10235 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 10236 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 10237 | }, |
9e30b8e0 L |
10238 | { |
10239 | /* MOD_0F01_REG_0 */ | |
10240 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10241 | { RM_TABLE (RM_0F01_REG_0) }, | |
10242 | }, | |
10243 | { | |
10244 | /* MOD_0F01_REG_1 */ | |
10245 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10246 | { RM_TABLE (RM_0F01_REG_1) }, | |
10247 | }, | |
10248 | { | |
10249 | /* MOD_0F01_REG_2 */ | |
10250 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10251 | { RM_TABLE (RM_0F01_REG_2) }, | |
10252 | }, | |
10253 | { | |
10254 | /* MOD_0F01_REG_3 */ | |
10255 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10256 | { RM_TABLE (RM_0F01_REG_3) }, | |
10257 | }, | |
8eab4136 L |
10258 | { |
10259 | /* MOD_0F01_REG_5 */ | |
603555e5 | 10260 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
10261 | { RM_TABLE (RM_0F01_REG_5) }, |
10262 | }, | |
9e30b8e0 L |
10263 | { |
10264 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10265 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
10266 | { RM_TABLE (RM_0F01_REG_7) }, |
10267 | }, | |
10268 | { | |
10269 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
10270 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
10271 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
10272 | }, |
10273 | { | |
10274 | /* MOD_0F13 */ | |
507bd325 | 10275 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10276 | }, |
10277 | { | |
10278 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
10279 | { "movhps", { XM, EXq }, 0 }, |
10280 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10281 | }, |
10282 | { | |
10283 | /* MOD_0F17 */ | |
507bd325 | 10284 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10285 | }, |
10286 | { | |
10287 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10288 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10289 | }, |
10290 | { | |
10291 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10292 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10293 | }, |
10294 | { | |
10295 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10296 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10297 | }, |
10298 | { | |
10299 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10300 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10301 | }, |
d7189fa5 RM |
10302 | { |
10303 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10304 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10305 | }, |
10306 | { | |
10307 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10308 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10309 | }, |
10310 | { | |
10311 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10312 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10313 | }, |
10314 | { | |
10315 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10316 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10317 | }, |
7e8b059b L |
10318 | { |
10319 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10320 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10321 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10322 | }, |
10323 | { | |
10324 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10325 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10326 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10327 | }, |
10328 | { | |
10329 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10330 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10331 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10332 | }, |
c48935d7 IT |
10333 | { |
10334 | /* MOD_0F1C_PREFIX_0 */ | |
10335 | { REG_TABLE (REG_0F1C_MOD_0) }, | |
10336 | { "nopQ", { Ev }, 0 }, | |
10337 | }, | |
603555e5 L |
10338 | { |
10339 | /* MOD_0F1E_PREFIX_1 */ | |
10340 | { "nopQ", { Ev }, 0 }, | |
10341 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
10342 | }, | |
b844680a | 10343 | { |
92fddf8e | 10344 | /* MOD_0F24 */ |
7bb15c6f | 10345 | { Bad_Opcode }, |
bf890a93 | 10346 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10347 | }, |
10348 | { | |
92fddf8e | 10349 | /* MOD_0F26 */ |
592d1631 | 10350 | { Bad_Opcode }, |
bf890a93 | 10351 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10352 | }, |
75c135a8 L |
10353 | { |
10354 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10355 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10356 | }, |
10357 | { | |
10358 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10359 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10360 | }, |
10361 | { | |
10362 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10363 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10364 | }, |
10365 | { | |
10366 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10367 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10368 | }, |
10369 | { | |
10370 | /* MOD_0F51 */ | |
592d1631 | 10371 | { Bad_Opcode }, |
507bd325 | 10372 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10373 | }, |
b844680a | 10374 | { |
1ceb70f8 | 10375 | /* MOD_0F71_REG_2 */ |
592d1631 | 10376 | { Bad_Opcode }, |
bf890a93 | 10377 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10378 | }, |
10379 | { | |
1ceb70f8 | 10380 | /* MOD_0F71_REG_4 */ |
592d1631 | 10381 | { Bad_Opcode }, |
bf890a93 | 10382 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10383 | }, |
10384 | { | |
1ceb70f8 | 10385 | /* MOD_0F71_REG_6 */ |
592d1631 | 10386 | { Bad_Opcode }, |
bf890a93 | 10387 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10388 | }, |
10389 | { | |
1ceb70f8 | 10390 | /* MOD_0F72_REG_2 */ |
592d1631 | 10391 | { Bad_Opcode }, |
bf890a93 | 10392 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10393 | }, |
10394 | { | |
1ceb70f8 | 10395 | /* MOD_0F72_REG_4 */ |
592d1631 | 10396 | { Bad_Opcode }, |
bf890a93 | 10397 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10398 | }, |
10399 | { | |
1ceb70f8 | 10400 | /* MOD_0F72_REG_6 */ |
592d1631 | 10401 | { Bad_Opcode }, |
bf890a93 | 10402 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10403 | }, |
10404 | { | |
1ceb70f8 | 10405 | /* MOD_0F73_REG_2 */ |
592d1631 | 10406 | { Bad_Opcode }, |
bf890a93 | 10407 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10408 | }, |
10409 | { | |
1ceb70f8 | 10410 | /* MOD_0F73_REG_3 */ |
592d1631 | 10411 | { Bad_Opcode }, |
c0f3af97 L |
10412 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10413 | }, | |
10414 | { | |
10415 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10416 | { Bad_Opcode }, |
bf890a93 | 10417 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10418 | }, |
10419 | { | |
10420 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10421 | { Bad_Opcode }, |
c0f3af97 L |
10422 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10423 | }, | |
10424 | { | |
10425 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10426 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 10427 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
10428 | }, |
10429 | { | |
10430 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10431 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 10432 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
10433 | }, |
10434 | { | |
10435 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10436 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 10437 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
10438 | }, |
10439 | { | |
10440 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10441 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 10442 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
10443 | }, |
10444 | { | |
10445 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
10446 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
10447 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
10448 | }, |
10449 | { | |
10450 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 10451 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 10452 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
10453 | }, |
10454 | { | |
10455 | /* MOD_0FAE_REG_6 */ | |
de89d0a3 IT |
10456 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, |
10457 | { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, | |
c0f3af97 L |
10458 | }, |
10459 | { | |
10460 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 10461 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
10462 | { RM_TABLE (RM_0FAE_REG_7) }, |
10463 | }, | |
10464 | { | |
10465 | /* MOD_0FB2 */ | |
bf890a93 | 10466 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10467 | }, |
10468 | { | |
10469 | /* MOD_0FB4 */ | |
bf890a93 | 10470 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10471 | }, |
10472 | { | |
10473 | /* MOD_0FB5 */ | |
bf890a93 | 10474 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10475 | }, |
a8484f96 L |
10476 | { |
10477 | /* MOD_0FC3 */ | |
10478 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
10479 | }, | |
963f3586 IT |
10480 | { |
10481 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10482 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10483 | }, |
10484 | { | |
10485 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10486 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10487 | }, |
10488 | { | |
10489 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10490 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10491 | }, |
c0f3af97 L |
10492 | { |
10493 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
10494 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
10495 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
10496 | }, |
10497 | { | |
10498 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10499 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 10500 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
10501 | }, |
10502 | { | |
10503 | /* MOD_0FD7 */ | |
592d1631 | 10504 | { Bad_Opcode }, |
bf890a93 | 10505 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10506 | }, |
10507 | { | |
10508 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10509 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10510 | }, |
10511 | { | |
10512 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10513 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10514 | }, |
10515 | { | |
10516 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10517 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10518 | }, |
603555e5 L |
10519 | { |
10520 | /* MOD_0F38F5_PREFIX_2 */ | |
10521 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10522 | }, | |
10523 | { | |
10524 | /* MOD_0F38F6_PREFIX_0 */ | |
10525 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10526 | }, | |
5d79adc4 L |
10527 | { |
10528 | /* MOD_0F38F8_PREFIX_1 */ | |
10529 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10530 | }, | |
c0a30a9f L |
10531 | { |
10532 | /* MOD_0F38F8_PREFIX_2 */ | |
10533 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10534 | }, | |
5d79adc4 L |
10535 | { |
10536 | /* MOD_0F38F8_PREFIX_3 */ | |
10537 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10538 | }, | |
c0a30a9f L |
10539 | { |
10540 | /* MOD_0F38F9_PREFIX_0 */ | |
10541 | { "movdiri", { Em, Gv }, PREFIX_OPCODE }, | |
10542 | }, | |
c0f3af97 L |
10543 | { |
10544 | /* MOD_62_32BIT */ | |
bf890a93 | 10545 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10546 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10547 | }, |
10548 | { | |
10549 | /* MOD_C4_32BIT */ | |
bf890a93 | 10550 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10551 | { VEX_C4_TABLE (VEX_0F) }, |
10552 | }, | |
10553 | { | |
10554 | /* MOD_C5_32BIT */ | |
bf890a93 | 10555 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10556 | { VEX_C5_TABLE (VEX_0F) }, |
10557 | }, | |
10558 | { | |
592a252b L |
10559 | /* MOD_VEX_0F12_PREFIX_0 */ |
10560 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10561 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10562 | }, |
10563 | { | |
592a252b L |
10564 | /* MOD_VEX_0F13 */ |
10565 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10566 | }, |
10567 | { | |
592a252b L |
10568 | /* MOD_VEX_0F16_PREFIX_0 */ |
10569 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10570 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10571 | }, |
10572 | { | |
592a252b L |
10573 | /* MOD_VEX_0F17 */ |
10574 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10575 | }, |
10576 | { | |
592a252b | 10577 | /* MOD_VEX_0F2B */ |
ec6f095a | 10578 | { "vmovntpX", { Mx, XM }, 0 }, |
c0f3af97 | 10579 | }, |
ab4e4ed5 AF |
10580 | { |
10581 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10582 | { Bad_Opcode }, | |
10583 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10584 | }, | |
10585 | { | |
10586 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10587 | { Bad_Opcode }, | |
10588 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10589 | }, | |
10590 | { | |
10591 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10592 | { Bad_Opcode }, | |
10593 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10594 | }, | |
10595 | { | |
10596 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10597 | { Bad_Opcode }, | |
10598 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10599 | }, | |
10600 | { | |
10601 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10602 | { Bad_Opcode }, | |
10603 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10604 | }, | |
10605 | { | |
10606 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10607 | { Bad_Opcode }, | |
10608 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10609 | }, | |
10610 | { | |
10611 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10612 | { Bad_Opcode }, | |
10613 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10614 | }, | |
10615 | { | |
10616 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10617 | { Bad_Opcode }, | |
10618 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10619 | }, | |
10620 | { | |
10621 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10622 | { Bad_Opcode }, | |
10623 | { "knotw", { MaskG, MaskR }, 0 }, | |
10624 | }, | |
10625 | { | |
10626 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10627 | { Bad_Opcode }, | |
10628 | { "knotq", { MaskG, MaskR }, 0 }, | |
10629 | }, | |
10630 | { | |
10631 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10632 | { Bad_Opcode }, | |
10633 | { "knotb", { MaskG, MaskR }, 0 }, | |
10634 | }, | |
10635 | { | |
10636 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10637 | { Bad_Opcode }, | |
10638 | { "knotd", { MaskG, MaskR }, 0 }, | |
10639 | }, | |
10640 | { | |
10641 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10642 | { Bad_Opcode }, | |
10643 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10644 | }, | |
10645 | { | |
10646 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10647 | { Bad_Opcode }, | |
10648 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10649 | }, | |
10650 | { | |
10651 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10652 | { Bad_Opcode }, | |
10653 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10654 | }, | |
10655 | { | |
10656 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10657 | { Bad_Opcode }, | |
10658 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10659 | }, | |
10660 | { | |
10661 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10662 | { Bad_Opcode }, | |
10663 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10664 | }, | |
10665 | { | |
10666 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10667 | { Bad_Opcode }, | |
10668 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10669 | }, | |
10670 | { | |
10671 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10672 | { Bad_Opcode }, | |
10673 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10674 | }, | |
10675 | { | |
10676 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10677 | { Bad_Opcode }, | |
10678 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10679 | }, | |
10680 | { | |
10681 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10682 | { Bad_Opcode }, | |
10683 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10684 | }, | |
10685 | { | |
10686 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10687 | { Bad_Opcode }, | |
10688 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10689 | }, | |
10690 | { | |
10691 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10692 | { Bad_Opcode }, | |
10693 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10694 | }, | |
10695 | { | |
10696 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10697 | { Bad_Opcode }, | |
10698 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10699 | }, | |
10700 | { | |
10701 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10702 | { Bad_Opcode }, | |
10703 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10704 | }, | |
10705 | { | |
10706 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10707 | { Bad_Opcode }, | |
10708 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10709 | }, | |
10710 | { | |
10711 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10712 | { Bad_Opcode }, | |
10713 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10714 | }, | |
10715 | { | |
10716 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10717 | { Bad_Opcode }, | |
10718 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10719 | }, | |
10720 | { | |
10721 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10722 | { Bad_Opcode }, | |
10723 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10724 | }, | |
10725 | { | |
10726 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10727 | { Bad_Opcode }, | |
10728 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10729 | }, | |
10730 | { | |
10731 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10732 | { Bad_Opcode }, | |
10733 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10734 | }, | |
c0f3af97 | 10735 | { |
592a252b | 10736 | /* MOD_VEX_0F50 */ |
592d1631 | 10737 | { Bad_Opcode }, |
ec6f095a | 10738 | { "vmovmskpX", { Gdq, XS }, 0 }, |
c0f3af97 L |
10739 | }, |
10740 | { | |
592a252b | 10741 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10742 | { Bad_Opcode }, |
592a252b | 10743 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10744 | }, |
10745 | { | |
592a252b | 10746 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10747 | { Bad_Opcode }, |
592a252b | 10748 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10749 | }, |
10750 | { | |
592a252b | 10751 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10752 | { Bad_Opcode }, |
592a252b | 10753 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10754 | }, |
10755 | { | |
592a252b | 10756 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10757 | { Bad_Opcode }, |
592a252b | 10758 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10759 | }, |
d8faab4e | 10760 | { |
592a252b | 10761 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10762 | { Bad_Opcode }, |
592a252b | 10763 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10764 | }, |
10765 | { | |
592a252b | 10766 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10767 | { Bad_Opcode }, |
592a252b | 10768 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10769 | }, |
876d4bfa | 10770 | { |
592a252b | 10771 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10772 | { Bad_Opcode }, |
592a252b | 10773 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10777 | { Bad_Opcode }, |
592a252b | 10778 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10779 | }, |
10780 | { | |
592a252b | 10781 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10782 | { Bad_Opcode }, |
592a252b | 10783 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10784 | }, |
10785 | { | |
592a252b | 10786 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10787 | { Bad_Opcode }, |
592a252b | 10788 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10789 | }, |
ab4e4ed5 AF |
10790 | { |
10791 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10792 | { "kmovw", { Ew, MaskG }, 0 }, | |
10793 | { Bad_Opcode }, | |
10794 | }, | |
10795 | { | |
10796 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10797 | { "kmovq", { Eq, MaskG }, 0 }, | |
10798 | { Bad_Opcode }, | |
10799 | }, | |
10800 | { | |
10801 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10802 | { "kmovb", { Eb, MaskG }, 0 }, | |
10803 | { Bad_Opcode }, | |
10804 | }, | |
10805 | { | |
10806 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10807 | { "kmovd", { Ed, MaskG }, 0 }, | |
10808 | { Bad_Opcode }, | |
10809 | }, | |
10810 | { | |
10811 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10812 | { Bad_Opcode }, | |
10813 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10814 | }, | |
10815 | { | |
10816 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10817 | { Bad_Opcode }, | |
10818 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10819 | }, | |
10820 | { | |
58a211d2 | 10821 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10822 | { Bad_Opcode }, |
58a211d2 | 10823 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10824 | }, |
10825 | { | |
10826 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10827 | { Bad_Opcode }, | |
10828 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10829 | }, | |
10830 | { | |
10831 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10832 | { Bad_Opcode }, | |
10833 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10834 | }, | |
10835 | { | |
58a211d2 | 10836 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10837 | { Bad_Opcode }, |
58a211d2 | 10838 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10839 | }, |
10840 | { | |
10841 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10842 | { Bad_Opcode }, | |
10843 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10844 | }, | |
10845 | { | |
10846 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10847 | { Bad_Opcode }, | |
10848 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10849 | }, | |
10850 | { | |
10851 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10852 | { Bad_Opcode }, | |
10853 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10854 | }, | |
10855 | { | |
10856 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10857 | { Bad_Opcode }, | |
10858 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10859 | }, | |
10860 | { | |
10861 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10862 | { Bad_Opcode }, | |
10863 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10864 | }, | |
10865 | { | |
10866 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10867 | { Bad_Opcode }, | |
10868 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10869 | }, | |
10870 | { | |
10871 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10872 | { Bad_Opcode }, | |
10873 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10874 | }, | |
10875 | { | |
10876 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10877 | { Bad_Opcode }, | |
10878 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10879 | }, | |
876d4bfa | 10880 | { |
592a252b L |
10881 | /* MOD_VEX_0FAE_REG_2 */ |
10882 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10883 | }, |
bbedc832 | 10884 | { |
592a252b L |
10885 | /* MOD_VEX_0FAE_REG_3 */ |
10886 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10887 | }, |
144c41d9 | 10888 | { |
592a252b | 10889 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10890 | { Bad_Opcode }, |
ec6f095a | 10891 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10892 | }, |
1afd85e3 | 10893 | { |
592a252b | 10894 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10895 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10896 | }, |
10897 | { | |
592a252b | 10898 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10899 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10900 | }, |
75c135a8 | 10901 | { |
592a252b L |
10902 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10903 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10904 | }, |
1afd85e3 | 10905 | { |
592a252b | 10906 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10907 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10908 | }, |
75c135a8 | 10909 | { |
592a252b L |
10910 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10911 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10912 | }, |
1afd85e3 | 10913 | { |
592a252b L |
10914 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10915 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10916 | }, |
10917 | { | |
592a252b L |
10918 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10919 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10920 | }, |
10921 | { | |
592a252b L |
10922 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10923 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10924 | }, |
6c30d220 L |
10925 | { |
10926 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10927 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10928 | }, | |
10929 | { | |
10930 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10931 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10932 | }, |
10933 | { | |
10934 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10935 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10936 | }, |
ab4e4ed5 AF |
10937 | { |
10938 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10939 | { Bad_Opcode }, | |
10940 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10941 | }, | |
10942 | { | |
10943 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10944 | { Bad_Opcode }, | |
10945 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10946 | }, | |
10947 | { | |
10948 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10949 | { Bad_Opcode }, | |
10950 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10951 | }, | |
10952 | { | |
10953 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10954 | { Bad_Opcode }, | |
10955 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10956 | }, | |
10957 | { | |
10958 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10959 | { Bad_Opcode }, | |
10960 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10961 | }, | |
10962 | { | |
10963 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10964 | { Bad_Opcode }, | |
10965 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10966 | }, | |
10967 | { | |
10968 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10969 | { Bad_Opcode }, | |
10970 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10971 | }, | |
10972 | { | |
10973 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10974 | { Bad_Opcode }, | |
10975 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10976 | }, | |
43234a1e L |
10977 | #define NEED_MOD_TABLE |
10978 | #include "i386-dis-evex.h" | |
10979 | #undef NEED_MOD_TABLE | |
b844680a L |
10980 | }; |
10981 | ||
1ceb70f8 | 10982 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10983 | { |
10984 | /* RM_C6_REG_7 */ | |
bf890a93 | 10985 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10986 | }, |
10987 | { | |
10988 | /* RM_C7_REG_7 */ | |
bf890a93 | 10989 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 10990 | }, |
b844680a | 10991 | { |
1ceb70f8 | 10992 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10993 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10994 | { "vmcall", { Skip_MODRM }, 0 }, |
10995 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10996 | { "vmresume", { Skip_MODRM }, 0 }, | |
10997 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10998 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10999 | }, |
11000 | { | |
1ceb70f8 | 11001 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
11002 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11003 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
11004 | { "clac", { Skip_MODRM }, 0 }, | |
11005 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
11006 | { Bad_Opcode }, |
11007 | { Bad_Opcode }, | |
11008 | { Bad_Opcode }, | |
bf890a93 | 11009 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 11010 | }, |
475a2301 L |
11011 | { |
11012 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11013 | { "xgetbv", { Skip_MODRM }, 0 }, |
11014 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11015 | { Bad_Opcode }, |
11016 | { Bad_Opcode }, | |
bf890a93 IT |
11017 | { "vmfunc", { Skip_MODRM }, 0 }, |
11018 | { "xend", { Skip_MODRM }, 0 }, | |
11019 | { "xtest", { Skip_MODRM }, 0 }, | |
11020 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11021 | }, |
b844680a | 11022 | { |
1ceb70f8 | 11023 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
11024 | { "vmrun", { Skip_MODRM }, 0 }, |
11025 | { "vmmcall", { Skip_MODRM }, 0 }, | |
11026 | { "vmload", { Skip_MODRM }, 0 }, | |
11027 | { "vmsave", { Skip_MODRM }, 0 }, | |
11028 | { "stgi", { Skip_MODRM }, 0 }, | |
11029 | { "clgi", { Skip_MODRM }, 0 }, | |
11030 | { "skinit", { Skip_MODRM }, 0 }, | |
11031 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11032 | }, |
8eab4136 L |
11033 | { |
11034 | /* RM_0F01_REG_5 */ | |
2234eee6 | 11035 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 11036 | { Bad_Opcode }, |
603555e5 | 11037 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
11038 | { Bad_Opcode }, |
11039 | { Bad_Opcode }, | |
11040 | { Bad_Opcode }, | |
11041 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11042 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11043 | }, | |
4e7d34a6 | 11044 | { |
1ceb70f8 | 11045 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
11046 | { "swapgs", { Skip_MODRM }, 0 }, |
11047 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
11048 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
11049 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 11050 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 11051 | }, |
603555e5 L |
11052 | { |
11053 | /* RM_0F1E_MOD_3_REG_7 */ | |
11054 | { "nopQ", { Ev }, 0 }, | |
11055 | { "nopQ", { Ev }, 0 }, | |
11056 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11057 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11058 | { "nopQ", { Ev }, 0 }, | |
11059 | { "nopQ", { Ev }, 0 }, | |
11060 | { "nopQ", { Ev }, 0 }, | |
11061 | { "nopQ", { Ev }, 0 }, | |
11062 | }, | |
b844680a | 11063 | { |
1ceb70f8 | 11064 | /* RM_0FAE_REG_6 */ |
bf890a93 | 11065 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11066 | }, |
bbedc832 | 11067 | { |
1ceb70f8 | 11068 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
11069 | { "sfence", { Skip_MODRM }, 0 }, |
11070 | ||
144c41d9 | 11071 | }, |
b844680a L |
11072 | }; |
11073 | ||
c608c12e AM |
11074 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11075 | ||
f16cd0d5 L |
11076 | /* We use the high bit to indicate different name for the same |
11077 | prefix. */ | |
f16cd0d5 | 11078 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11079 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11080 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11081 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11082 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
11083 | |
11084 | static int | |
26ca5450 | 11085 | ckprefix (void) |
252b5132 | 11086 | { |
f16cd0d5 | 11087 | int newrex, i, length; |
52b15da3 | 11088 | rex = 0; |
c0f3af97 | 11089 | rex_ignored = 0; |
252b5132 | 11090 | prefixes = 0; |
7d421014 | 11091 | used_prefixes = 0; |
52b15da3 | 11092 | rex_used = 0; |
f16cd0d5 L |
11093 | last_lock_prefix = -1; |
11094 | last_repz_prefix = -1; | |
11095 | last_repnz_prefix = -1; | |
11096 | last_data_prefix = -1; | |
11097 | last_addr_prefix = -1; | |
11098 | last_rex_prefix = -1; | |
11099 | last_seg_prefix = -1; | |
d9949a36 | 11100 | fwait_prefix = -1; |
285ca992 | 11101 | active_seg_prefix = 0; |
f310f33d L |
11102 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11103 | all_prefixes[i] = 0; | |
11104 | i = 0; | |
f16cd0d5 L |
11105 | length = 0; |
11106 | /* The maximum instruction length is 15bytes. */ | |
11107 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11108 | { |
11109 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11110 | newrex = 0; |
252b5132 RH |
11111 | switch (*codep) |
11112 | { | |
52b15da3 JH |
11113 | /* REX prefixes family. */ |
11114 | case 0x40: | |
11115 | case 0x41: | |
11116 | case 0x42: | |
11117 | case 0x43: | |
11118 | case 0x44: | |
11119 | case 0x45: | |
11120 | case 0x46: | |
11121 | case 0x47: | |
11122 | case 0x48: | |
11123 | case 0x49: | |
11124 | case 0x4a: | |
11125 | case 0x4b: | |
11126 | case 0x4c: | |
11127 | case 0x4d: | |
11128 | case 0x4e: | |
11129 | case 0x4f: | |
f16cd0d5 L |
11130 | if (address_mode == mode_64bit) |
11131 | newrex = *codep; | |
11132 | else | |
11133 | return 1; | |
11134 | last_rex_prefix = i; | |
52b15da3 | 11135 | break; |
252b5132 RH |
11136 | case 0xf3: |
11137 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11138 | last_repz_prefix = i; |
252b5132 RH |
11139 | break; |
11140 | case 0xf2: | |
11141 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11142 | last_repnz_prefix = i; |
252b5132 RH |
11143 | break; |
11144 | case 0xf0: | |
11145 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11146 | last_lock_prefix = i; |
252b5132 RH |
11147 | break; |
11148 | case 0x2e: | |
11149 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11150 | last_seg_prefix = i; |
285ca992 | 11151 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11152 | break; |
11153 | case 0x36: | |
11154 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11155 | last_seg_prefix = i; |
285ca992 | 11156 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11157 | break; |
11158 | case 0x3e: | |
11159 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11160 | last_seg_prefix = i; |
285ca992 | 11161 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11162 | break; |
11163 | case 0x26: | |
11164 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11165 | last_seg_prefix = i; |
285ca992 | 11166 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11167 | break; |
11168 | case 0x64: | |
11169 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11170 | last_seg_prefix = i; |
285ca992 | 11171 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11172 | break; |
11173 | case 0x65: | |
11174 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11175 | last_seg_prefix = i; |
285ca992 | 11176 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11177 | break; |
11178 | case 0x66: | |
11179 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11180 | last_data_prefix = i; |
252b5132 RH |
11181 | break; |
11182 | case 0x67: | |
11183 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11184 | last_addr_prefix = i; |
252b5132 | 11185 | break; |
5076851f | 11186 | case FWAIT_OPCODE: |
252b5132 RH |
11187 | /* fwait is really an instruction. If there are prefixes |
11188 | before the fwait, they belong to the fwait, *not* to the | |
11189 | following instruction. */ | |
d9949a36 | 11190 | fwait_prefix = i; |
3e7d61b2 | 11191 | if (prefixes || rex) |
252b5132 RH |
11192 | { |
11193 | prefixes |= PREFIX_FWAIT; | |
11194 | codep++; | |
6c067bbb RM |
11195 | /* This ensures that the previous REX prefixes are noticed |
11196 | as unused prefixes, as in the return case below. */ | |
11197 | rex_used = rex; | |
f16cd0d5 | 11198 | return 1; |
252b5132 RH |
11199 | } |
11200 | prefixes = PREFIX_FWAIT; | |
11201 | break; | |
11202 | default: | |
f16cd0d5 | 11203 | return 1; |
252b5132 | 11204 | } |
52b15da3 JH |
11205 | /* Rex is ignored when followed by another prefix. */ |
11206 | if (rex) | |
11207 | { | |
3e7d61b2 | 11208 | rex_used = rex; |
f16cd0d5 | 11209 | return 1; |
52b15da3 | 11210 | } |
f16cd0d5 | 11211 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11212 | all_prefixes[i++] = *codep; |
52b15da3 | 11213 | rex = newrex; |
252b5132 | 11214 | codep++; |
f16cd0d5 L |
11215 | length++; |
11216 | } | |
11217 | return 0; | |
11218 | } | |
11219 | ||
7d421014 ILT |
11220 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11221 | prefix byte. */ | |
11222 | ||
11223 | static const char * | |
26ca5450 | 11224 | prefix_name (int pref, int sizeflag) |
7d421014 | 11225 | { |
0003779b L |
11226 | static const char *rexes [16] = |
11227 | { | |
11228 | "rex", /* 0x40 */ | |
11229 | "rex.B", /* 0x41 */ | |
11230 | "rex.X", /* 0x42 */ | |
11231 | "rex.XB", /* 0x43 */ | |
11232 | "rex.R", /* 0x44 */ | |
11233 | "rex.RB", /* 0x45 */ | |
11234 | "rex.RX", /* 0x46 */ | |
11235 | "rex.RXB", /* 0x47 */ | |
11236 | "rex.W", /* 0x48 */ | |
11237 | "rex.WB", /* 0x49 */ | |
11238 | "rex.WX", /* 0x4a */ | |
11239 | "rex.WXB", /* 0x4b */ | |
11240 | "rex.WR", /* 0x4c */ | |
11241 | "rex.WRB", /* 0x4d */ | |
11242 | "rex.WRX", /* 0x4e */ | |
11243 | "rex.WRXB", /* 0x4f */ | |
11244 | }; | |
11245 | ||
7d421014 ILT |
11246 | switch (pref) |
11247 | { | |
52b15da3 JH |
11248 | /* REX prefixes family. */ |
11249 | case 0x40: | |
52b15da3 | 11250 | case 0x41: |
52b15da3 | 11251 | case 0x42: |
52b15da3 | 11252 | case 0x43: |
52b15da3 | 11253 | case 0x44: |
52b15da3 | 11254 | case 0x45: |
52b15da3 | 11255 | case 0x46: |
52b15da3 | 11256 | case 0x47: |
52b15da3 | 11257 | case 0x48: |
52b15da3 | 11258 | case 0x49: |
52b15da3 | 11259 | case 0x4a: |
52b15da3 | 11260 | case 0x4b: |
52b15da3 | 11261 | case 0x4c: |
52b15da3 | 11262 | case 0x4d: |
52b15da3 | 11263 | case 0x4e: |
52b15da3 | 11264 | case 0x4f: |
0003779b | 11265 | return rexes [pref - 0x40]; |
7d421014 ILT |
11266 | case 0xf3: |
11267 | return "repz"; | |
11268 | case 0xf2: | |
11269 | return "repnz"; | |
11270 | case 0xf0: | |
11271 | return "lock"; | |
11272 | case 0x2e: | |
11273 | return "cs"; | |
11274 | case 0x36: | |
11275 | return "ss"; | |
11276 | case 0x3e: | |
11277 | return "ds"; | |
11278 | case 0x26: | |
11279 | return "es"; | |
11280 | case 0x64: | |
11281 | return "fs"; | |
11282 | case 0x65: | |
11283 | return "gs"; | |
11284 | case 0x66: | |
11285 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11286 | case 0x67: | |
cb712a9e | 11287 | if (address_mode == mode_64bit) |
db6eb5be | 11288 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11289 | else |
2888cb7a | 11290 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11291 | case FWAIT_OPCODE: |
11292 | return "fwait"; | |
f16cd0d5 L |
11293 | case REP_PREFIX: |
11294 | return "rep"; | |
42164a71 L |
11295 | case XACQUIRE_PREFIX: |
11296 | return "xacquire"; | |
11297 | case XRELEASE_PREFIX: | |
11298 | return "xrelease"; | |
7e8b059b L |
11299 | case BND_PREFIX: |
11300 | return "bnd"; | |
04ef582a L |
11301 | case NOTRACK_PREFIX: |
11302 | return "notrack"; | |
7d421014 ILT |
11303 | default: |
11304 | return NULL; | |
11305 | } | |
11306 | } | |
11307 | ||
ce518a5f L |
11308 | static char op_out[MAX_OPERANDS][100]; |
11309 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11310 | static int two_source_ops; |
ce518a5f L |
11311 | static bfd_vma op_address[MAX_OPERANDS]; |
11312 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11313 | static bfd_vma start_pc; |
ce518a5f | 11314 | |
252b5132 RH |
11315 | /* |
11316 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11317 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11318 | * section of the "Virtual 8086 Mode" chapter.) | |
11319 | * 'pc' should be the address of this instruction, it will | |
11320 | * be used to print the target address if this is a relative jump or call | |
11321 | * The function returns the length of this instruction in bytes. | |
11322 | */ | |
11323 | ||
252b5132 | 11324 | static char intel_syntax; |
9d141669 | 11325 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11326 | static char open_char; |
11327 | static char close_char; | |
11328 | static char separator_char; | |
11329 | static char scale_char; | |
11330 | ||
5db04b09 L |
11331 | enum x86_64_isa |
11332 | { | |
11333 | amd64 = 0, | |
11334 | intel64 | |
11335 | }; | |
11336 | ||
11337 | static enum x86_64_isa isa64; | |
11338 | ||
e396998b AM |
11339 | /* Here for backwards compatibility. When gdb stops using |
11340 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11341 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11342 | int |
26ca5450 | 11343 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11344 | { |
11345 | intel_syntax = 0; | |
e396998b AM |
11346 | |
11347 | return print_insn (pc, info); | |
252b5132 RH |
11348 | } |
11349 | ||
11350 | int | |
26ca5450 | 11351 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11352 | { |
11353 | intel_syntax = 1; | |
e396998b AM |
11354 | |
11355 | return print_insn (pc, info); | |
252b5132 RH |
11356 | } |
11357 | ||
e396998b | 11358 | int |
26ca5450 | 11359 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11360 | { |
11361 | intel_syntax = -1; | |
11362 | ||
11363 | return print_insn (pc, info); | |
11364 | } | |
11365 | ||
f59a29b9 L |
11366 | void |
11367 | print_i386_disassembler_options (FILE *stream) | |
11368 | { | |
11369 | fprintf (stream, _("\n\ | |
11370 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11371 | with the -M switch (multiple options should be separated by commas):\n")); | |
11372 | ||
11373 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11374 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11375 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11376 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11377 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11378 | fprintf (stream, _(" att-mnemonic\n" |
11379 | " Display instruction in AT&T mnemonic\n")); | |
11380 | fprintf (stream, _(" intel-mnemonic\n" | |
11381 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11382 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11383 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11384 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11385 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11386 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11387 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11388 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11389 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11390 | } |
11391 | ||
592d1631 | 11392 | /* Bad opcode. */ |
bf890a93 | 11393 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11394 | |
b844680a L |
11395 | /* Get a pointer to struct dis386 with a valid name. */ |
11396 | ||
11397 | static const struct dis386 * | |
8bb15339 | 11398 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11399 | { |
91d6fa6a | 11400 | int vindex, vex_table_index; |
b844680a L |
11401 | |
11402 | if (dp->name != NULL) | |
11403 | return dp; | |
11404 | ||
11405 | switch (dp->op[0].bytemode) | |
11406 | { | |
1ceb70f8 L |
11407 | case USE_REG_TABLE: |
11408 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11409 | break; | |
11410 | ||
11411 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11412 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11413 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11414 | break; |
11415 | ||
11416 | case USE_RM_TABLE: | |
11417 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11418 | break; |
11419 | ||
4e7d34a6 | 11420 | case USE_PREFIX_TABLE: |
c0f3af97 | 11421 | if (need_vex) |
b844680a | 11422 | { |
c0f3af97 L |
11423 | /* The prefix in VEX is implicit. */ |
11424 | switch (vex.prefix) | |
11425 | { | |
11426 | case 0: | |
91d6fa6a | 11427 | vindex = 0; |
c0f3af97 L |
11428 | break; |
11429 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11430 | vindex = 1; |
c0f3af97 L |
11431 | break; |
11432 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11433 | vindex = 2; |
c0f3af97 L |
11434 | break; |
11435 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11436 | vindex = 3; |
c0f3af97 L |
11437 | break; |
11438 | default: | |
11439 | abort (); | |
11440 | break; | |
11441 | } | |
b844680a | 11442 | } |
7bb15c6f | 11443 | else |
b844680a | 11444 | { |
285ca992 L |
11445 | int last_prefix = -1; |
11446 | int prefix = 0; | |
91d6fa6a | 11447 | vindex = 0; |
285ca992 L |
11448 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11449 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11450 | last one wins. */ | |
11451 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11452 | { |
285ca992 | 11453 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11454 | { |
285ca992 L |
11455 | vindex = 1; |
11456 | prefix = PREFIX_REPZ; | |
11457 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11458 | } |
11459 | else | |
b844680a | 11460 | { |
285ca992 L |
11461 | vindex = 3; |
11462 | prefix = PREFIX_REPNZ; | |
11463 | last_prefix = last_repnz_prefix; | |
b844680a | 11464 | } |
285ca992 | 11465 | |
507bd325 L |
11466 | /* Check if prefix should be ignored. */ |
11467 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11468 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11469 | & prefix) != 0) | |
285ca992 L |
11470 | vindex = 0; |
11471 | } | |
11472 | ||
11473 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11474 | { | |
11475 | vindex = 2; | |
11476 | prefix = PREFIX_DATA; | |
11477 | last_prefix = last_data_prefix; | |
11478 | } | |
11479 | ||
11480 | if (vindex != 0) | |
11481 | { | |
11482 | used_prefixes |= prefix; | |
11483 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11484 | } |
11485 | } | |
91d6fa6a | 11486 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11487 | break; |
11488 | ||
4e7d34a6 | 11489 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11490 | vindex = address_mode == mode_64bit ? 1 : 0; |
11491 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11492 | break; |
11493 | ||
4e7d34a6 | 11494 | case USE_3BYTE_TABLE: |
8bb15339 | 11495 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11496 | vindex = *codep++; |
11497 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11498 | end_codep = codep; |
8bb15339 L |
11499 | modrm.mod = (*codep >> 6) & 3; |
11500 | modrm.reg = (*codep >> 3) & 7; | |
11501 | modrm.rm = *codep & 7; | |
11502 | break; | |
11503 | ||
c0f3af97 L |
11504 | case USE_VEX_LEN_TABLE: |
11505 | if (!need_vex) | |
11506 | abort (); | |
11507 | ||
11508 | switch (vex.length) | |
11509 | { | |
11510 | case 128: | |
91d6fa6a | 11511 | vindex = 0; |
c0f3af97 L |
11512 | break; |
11513 | case 256: | |
91d6fa6a | 11514 | vindex = 1; |
c0f3af97 L |
11515 | break; |
11516 | default: | |
11517 | abort (); | |
11518 | break; | |
11519 | } | |
11520 | ||
91d6fa6a | 11521 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11522 | break; |
11523 | ||
04e2a182 L |
11524 | case USE_EVEX_LEN_TABLE: |
11525 | if (!vex.evex) | |
11526 | abort (); | |
11527 | ||
11528 | switch (vex.length) | |
11529 | { | |
11530 | case 128: | |
11531 | vindex = 0; | |
11532 | break; | |
11533 | case 256: | |
11534 | vindex = 1; | |
11535 | break; | |
11536 | case 512: | |
11537 | vindex = 2; | |
11538 | break; | |
11539 | default: | |
11540 | abort (); | |
11541 | break; | |
11542 | } | |
11543 | ||
11544 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11545 | break; | |
11546 | ||
f88c9eb0 SP |
11547 | case USE_XOP_8F_TABLE: |
11548 | FETCH_DATA (info, codep + 3); | |
11549 | /* All bits in the REX prefix are ignored. */ | |
11550 | rex_ignored = rex; | |
11551 | rex = ~(*codep >> 5) & 0x7; | |
11552 | ||
11553 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11554 | switch ((*codep & 0x1f)) | |
11555 | { | |
11556 | default: | |
f07af43e L |
11557 | dp = &bad_opcode; |
11558 | return dp; | |
5dd85c99 SP |
11559 | case 0x8: |
11560 | vex_table_index = XOP_08; | |
11561 | break; | |
f88c9eb0 SP |
11562 | case 0x9: |
11563 | vex_table_index = XOP_09; | |
11564 | break; | |
11565 | case 0xa: | |
11566 | vex_table_index = XOP_0A; | |
11567 | break; | |
11568 | } | |
11569 | codep++; | |
11570 | vex.w = *codep & 0x80; | |
11571 | if (vex.w && address_mode == mode_64bit) | |
11572 | rex |= REX_W; | |
11573 | ||
11574 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11575 | if (address_mode != mode_64bit) |
f07af43e | 11576 | { |
abfcb414 AP |
11577 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11578 | rex &= ~REX_B; | |
f07af43e | 11579 | } |
f88c9eb0 SP |
11580 | |
11581 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11582 | switch ((*codep & 0x3)) | |
11583 | { | |
11584 | case 0: | |
f88c9eb0 SP |
11585 | break; |
11586 | case 1: | |
11587 | vex.prefix = DATA_PREFIX_OPCODE; | |
11588 | break; | |
11589 | case 2: | |
11590 | vex.prefix = REPE_PREFIX_OPCODE; | |
11591 | break; | |
11592 | case 3: | |
11593 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11594 | break; | |
11595 | } | |
11596 | need_vex = 1; | |
11597 | need_vex_reg = 1; | |
11598 | codep++; | |
91d6fa6a NC |
11599 | vindex = *codep++; |
11600 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11601 | |
285ca992 | 11602 | end_codep = codep; |
c48244a5 SP |
11603 | FETCH_DATA (info, codep + 1); |
11604 | modrm.mod = (*codep >> 6) & 3; | |
11605 | modrm.reg = (*codep >> 3) & 7; | |
11606 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11607 | break; |
11608 | ||
c0f3af97 | 11609 | case USE_VEX_C4_TABLE: |
43234a1e | 11610 | /* VEX prefix. */ |
c0f3af97 L |
11611 | FETCH_DATA (info, codep + 3); |
11612 | /* All bits in the REX prefix are ignored. */ | |
11613 | rex_ignored = rex; | |
11614 | rex = ~(*codep >> 5) & 0x7; | |
11615 | switch ((*codep & 0x1f)) | |
11616 | { | |
11617 | default: | |
f07af43e L |
11618 | dp = &bad_opcode; |
11619 | return dp; | |
c0f3af97 | 11620 | case 0x1: |
f88c9eb0 | 11621 | vex_table_index = VEX_0F; |
c0f3af97 L |
11622 | break; |
11623 | case 0x2: | |
f88c9eb0 | 11624 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11625 | break; |
11626 | case 0x3: | |
f88c9eb0 | 11627 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11628 | break; |
11629 | } | |
11630 | codep++; | |
11631 | vex.w = *codep & 0x80; | |
9889cbb1 | 11632 | if (address_mode == mode_64bit) |
f07af43e | 11633 | { |
9889cbb1 L |
11634 | if (vex.w) |
11635 | rex |= REX_W; | |
9889cbb1 L |
11636 | } |
11637 | else | |
11638 | { | |
11639 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11640 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11641 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11642 | rex = 0; |
f07af43e | 11643 | } |
5f847646 | 11644 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11645 | vex.length = (*codep & 0x4) ? 256 : 128; |
11646 | switch ((*codep & 0x3)) | |
11647 | { | |
11648 | case 0: | |
c0f3af97 L |
11649 | break; |
11650 | case 1: | |
11651 | vex.prefix = DATA_PREFIX_OPCODE; | |
11652 | break; | |
11653 | case 2: | |
11654 | vex.prefix = REPE_PREFIX_OPCODE; | |
11655 | break; | |
11656 | case 3: | |
11657 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11658 | break; | |
11659 | } | |
11660 | need_vex = 1; | |
11661 | need_vex_reg = 1; | |
11662 | codep++; | |
91d6fa6a NC |
11663 | vindex = *codep++; |
11664 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11665 | end_codep = codep; |
53c4d625 JB |
11666 | /* There is no MODRM byte for VEX0F 77. */ |
11667 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11668 | { |
11669 | FETCH_DATA (info, codep + 1); | |
11670 | modrm.mod = (*codep >> 6) & 3; | |
11671 | modrm.reg = (*codep >> 3) & 7; | |
11672 | modrm.rm = *codep & 7; | |
11673 | } | |
11674 | break; | |
11675 | ||
11676 | case USE_VEX_C5_TABLE: | |
43234a1e | 11677 | /* VEX prefix. */ |
c0f3af97 L |
11678 | FETCH_DATA (info, codep + 2); |
11679 | /* All bits in the REX prefix are ignored. */ | |
11680 | rex_ignored = rex; | |
11681 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11682 | ||
9889cbb1 L |
11683 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11684 | VEX.vvvv is 1. */ | |
c0f3af97 | 11685 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11686 | vex.length = (*codep & 0x4) ? 256 : 128; |
11687 | switch ((*codep & 0x3)) | |
11688 | { | |
11689 | case 0: | |
c0f3af97 L |
11690 | break; |
11691 | case 1: | |
11692 | vex.prefix = DATA_PREFIX_OPCODE; | |
11693 | break; | |
11694 | case 2: | |
11695 | vex.prefix = REPE_PREFIX_OPCODE; | |
11696 | break; | |
11697 | case 3: | |
11698 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11699 | break; | |
11700 | } | |
11701 | need_vex = 1; | |
11702 | need_vex_reg = 1; | |
11703 | codep++; | |
91d6fa6a NC |
11704 | vindex = *codep++; |
11705 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11706 | end_codep = codep; |
53c4d625 JB |
11707 | /* There is no MODRM byte for VEX 77. */ |
11708 | if (vindex != 0x77) | |
c0f3af97 L |
11709 | { |
11710 | FETCH_DATA (info, codep + 1); | |
11711 | modrm.mod = (*codep >> 6) & 3; | |
11712 | modrm.reg = (*codep >> 3) & 7; | |
11713 | modrm.rm = *codep & 7; | |
11714 | } | |
11715 | break; | |
11716 | ||
9e30b8e0 L |
11717 | case USE_VEX_W_TABLE: |
11718 | if (!need_vex) | |
11719 | abort (); | |
11720 | ||
11721 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11722 | break; | |
11723 | ||
43234a1e L |
11724 | case USE_EVEX_TABLE: |
11725 | two_source_ops = 0; | |
11726 | /* EVEX prefix. */ | |
11727 | vex.evex = 1; | |
11728 | FETCH_DATA (info, codep + 4); | |
11729 | /* All bits in the REX prefix are ignored. */ | |
11730 | rex_ignored = rex; | |
11731 | /* The first byte after 0x62. */ | |
11732 | rex = ~(*codep >> 5) & 0x7; | |
11733 | vex.r = *codep & 0x10; | |
11734 | switch ((*codep & 0xf)) | |
11735 | { | |
11736 | default: | |
11737 | return &bad_opcode; | |
11738 | case 0x1: | |
11739 | vex_table_index = EVEX_0F; | |
11740 | break; | |
11741 | case 0x2: | |
11742 | vex_table_index = EVEX_0F38; | |
11743 | break; | |
11744 | case 0x3: | |
11745 | vex_table_index = EVEX_0F3A; | |
11746 | break; | |
11747 | } | |
11748 | ||
11749 | /* The second byte after 0x62. */ | |
11750 | codep++; | |
11751 | vex.w = *codep & 0x80; | |
11752 | if (vex.w && address_mode == mode_64bit) | |
11753 | rex |= REX_W; | |
11754 | ||
11755 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11756 | |
11757 | /* The U bit. */ | |
11758 | if (!(*codep & 0x4)) | |
11759 | return &bad_opcode; | |
11760 | ||
11761 | switch ((*codep & 0x3)) | |
11762 | { | |
11763 | case 0: | |
43234a1e L |
11764 | break; |
11765 | case 1: | |
11766 | vex.prefix = DATA_PREFIX_OPCODE; | |
11767 | break; | |
11768 | case 2: | |
11769 | vex.prefix = REPE_PREFIX_OPCODE; | |
11770 | break; | |
11771 | case 3: | |
11772 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11773 | break; | |
11774 | } | |
11775 | ||
11776 | /* The third byte after 0x62. */ | |
11777 | codep++; | |
11778 | ||
11779 | /* Remember the static rounding bits. */ | |
11780 | vex.ll = (*codep >> 5) & 3; | |
11781 | vex.b = (*codep & 0x10) != 0; | |
11782 | ||
11783 | vex.v = *codep & 0x8; | |
11784 | vex.mask_register_specifier = *codep & 0x7; | |
11785 | vex.zeroing = *codep & 0x80; | |
11786 | ||
5f847646 JB |
11787 | if (address_mode != mode_64bit) |
11788 | { | |
11789 | /* In 16/32-bit mode silently ignore following bits. */ | |
11790 | rex &= ~REX_B; | |
11791 | vex.r = 1; | |
11792 | vex.v = 1; | |
11793 | } | |
11794 | ||
43234a1e L |
11795 | need_vex = 1; |
11796 | need_vex_reg = 1; | |
11797 | codep++; | |
11798 | vindex = *codep++; | |
11799 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11800 | end_codep = codep; |
43234a1e L |
11801 | FETCH_DATA (info, codep + 1); |
11802 | modrm.mod = (*codep >> 6) & 3; | |
11803 | modrm.reg = (*codep >> 3) & 7; | |
11804 | modrm.rm = *codep & 7; | |
11805 | ||
11806 | /* Set vector length. */ | |
11807 | if (modrm.mod == 3 && vex.b) | |
11808 | vex.length = 512; | |
11809 | else | |
11810 | { | |
11811 | switch (vex.ll) | |
11812 | { | |
11813 | case 0x0: | |
11814 | vex.length = 128; | |
11815 | break; | |
11816 | case 0x1: | |
11817 | vex.length = 256; | |
11818 | break; | |
11819 | case 0x2: | |
11820 | vex.length = 512; | |
11821 | break; | |
11822 | default: | |
11823 | return &bad_opcode; | |
11824 | } | |
11825 | } | |
11826 | break; | |
11827 | ||
592d1631 L |
11828 | case 0: |
11829 | dp = &bad_opcode; | |
11830 | break; | |
11831 | ||
b844680a | 11832 | default: |
d34b5006 | 11833 | abort (); |
b844680a L |
11834 | } |
11835 | ||
11836 | if (dp->name != NULL) | |
11837 | return dp; | |
11838 | else | |
8bb15339 | 11839 | return get_valid_dis386 (dp, info); |
b844680a L |
11840 | } |
11841 | ||
dfc8cf43 | 11842 | static void |
55cf16e1 | 11843 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11844 | { |
11845 | /* If modrm.mod == 3, operand must be register. */ | |
11846 | if (need_modrm | |
55cf16e1 | 11847 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11848 | && modrm.mod != 3 |
11849 | && modrm.rm == 4) | |
11850 | { | |
11851 | FETCH_DATA (info, codep + 2); | |
11852 | sib.index = (codep [1] >> 3) & 7; | |
11853 | sib.scale = (codep [1] >> 6) & 3; | |
11854 | sib.base = codep [1] & 7; | |
11855 | } | |
11856 | } | |
11857 | ||
e396998b | 11858 | static int |
26ca5450 | 11859 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11860 | { |
2da11e11 | 11861 | const struct dis386 *dp; |
252b5132 | 11862 | int i; |
ce518a5f | 11863 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11864 | int needcomma; |
df18fdba | 11865 | int sizeflag, orig_sizeflag; |
e396998b | 11866 | const char *p; |
252b5132 | 11867 | struct dis_private priv; |
f16cd0d5 | 11868 | int prefix_length; |
252b5132 | 11869 | |
d7921315 L |
11870 | priv.orig_sizeflag = AFLAG | DFLAG; |
11871 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11872 | address_mode = mode_32bit; |
2da11e11 | 11873 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11874 | { |
11875 | address_mode = mode_16bit; | |
11876 | priv.orig_sizeflag = 0; | |
11877 | } | |
2da11e11 | 11878 | else |
d7921315 L |
11879 | address_mode = mode_64bit; |
11880 | ||
11881 | if (intel_syntax == (char) -1) | |
11882 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11883 | |
11884 | for (p = info->disassembler_options; p != NULL; ) | |
11885 | { | |
5db04b09 L |
11886 | if (CONST_STRNEQ (p, "amd64")) |
11887 | isa64 = amd64; | |
11888 | else if (CONST_STRNEQ (p, "intel64")) | |
11889 | isa64 = intel64; | |
11890 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11891 | { |
cb712a9e | 11892 | address_mode = mode_64bit; |
e396998b AM |
11893 | priv.orig_sizeflag = AFLAG | DFLAG; |
11894 | } | |
0112cd26 | 11895 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11896 | { |
cb712a9e | 11897 | address_mode = mode_32bit; |
e396998b AM |
11898 | priv.orig_sizeflag = AFLAG | DFLAG; |
11899 | } | |
0112cd26 | 11900 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11901 | { |
cb712a9e | 11902 | address_mode = mode_16bit; |
e396998b AM |
11903 | priv.orig_sizeflag = 0; |
11904 | } | |
0112cd26 | 11905 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11906 | { |
11907 | intel_syntax = 1; | |
9d141669 L |
11908 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11909 | intel_mnemonic = 1; | |
e396998b | 11910 | } |
0112cd26 | 11911 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11912 | { |
11913 | intel_syntax = 0; | |
9d141669 L |
11914 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11915 | intel_mnemonic = 0; | |
e396998b | 11916 | } |
0112cd26 | 11917 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11918 | { |
f59a29b9 L |
11919 | if (address_mode == mode_64bit) |
11920 | { | |
11921 | if (p[4] == '3' && p[5] == '2') | |
11922 | priv.orig_sizeflag &= ~AFLAG; | |
11923 | else if (p[4] == '6' && p[5] == '4') | |
11924 | priv.orig_sizeflag |= AFLAG; | |
11925 | } | |
11926 | else | |
11927 | { | |
11928 | if (p[4] == '1' && p[5] == '6') | |
11929 | priv.orig_sizeflag &= ~AFLAG; | |
11930 | else if (p[4] == '3' && p[5] == '2') | |
11931 | priv.orig_sizeflag |= AFLAG; | |
11932 | } | |
e396998b | 11933 | } |
0112cd26 | 11934 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11935 | { |
11936 | if (p[4] == '1' && p[5] == '6') | |
11937 | priv.orig_sizeflag &= ~DFLAG; | |
11938 | else if (p[4] == '3' && p[5] == '2') | |
11939 | priv.orig_sizeflag |= DFLAG; | |
11940 | } | |
0112cd26 | 11941 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11942 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11943 | ||
11944 | p = strchr (p, ','); | |
11945 | if (p != NULL) | |
11946 | p++; | |
11947 | } | |
11948 | ||
c0f92bf9 L |
11949 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11950 | { | |
11951 | (*info->fprintf_func) (info->stream, | |
11952 | _("64-bit address is disabled")); | |
11953 | return -1; | |
11954 | } | |
11955 | ||
e396998b AM |
11956 | if (intel_syntax) |
11957 | { | |
11958 | names64 = intel_names64; | |
11959 | names32 = intel_names32; | |
11960 | names16 = intel_names16; | |
11961 | names8 = intel_names8; | |
11962 | names8rex = intel_names8rex; | |
11963 | names_seg = intel_names_seg; | |
b9733481 | 11964 | names_mm = intel_names_mm; |
7e8b059b | 11965 | names_bnd = intel_names_bnd; |
b9733481 L |
11966 | names_xmm = intel_names_xmm; |
11967 | names_ymm = intel_names_ymm; | |
43234a1e | 11968 | names_zmm = intel_names_zmm; |
db51cc60 L |
11969 | index64 = intel_index64; |
11970 | index32 = intel_index32; | |
43234a1e | 11971 | names_mask = intel_names_mask; |
e396998b AM |
11972 | index16 = intel_index16; |
11973 | open_char = '['; | |
11974 | close_char = ']'; | |
11975 | separator_char = '+'; | |
11976 | scale_char = '*'; | |
11977 | } | |
11978 | else | |
11979 | { | |
11980 | names64 = att_names64; | |
11981 | names32 = att_names32; | |
11982 | names16 = att_names16; | |
11983 | names8 = att_names8; | |
11984 | names8rex = att_names8rex; | |
11985 | names_seg = att_names_seg; | |
b9733481 | 11986 | names_mm = att_names_mm; |
7e8b059b | 11987 | names_bnd = att_names_bnd; |
b9733481 L |
11988 | names_xmm = att_names_xmm; |
11989 | names_ymm = att_names_ymm; | |
43234a1e | 11990 | names_zmm = att_names_zmm; |
db51cc60 L |
11991 | index64 = att_index64; |
11992 | index32 = att_index32; | |
43234a1e | 11993 | names_mask = att_names_mask; |
e396998b AM |
11994 | index16 = att_index16; |
11995 | open_char = '('; | |
11996 | close_char = ')'; | |
11997 | separator_char = ','; | |
11998 | scale_char = ','; | |
11999 | } | |
2da11e11 | 12000 | |
4fe53c98 | 12001 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12002 | puts most long word instructions on a single line. Use 8 bytes |
12003 | for Intel L1OM. */ | |
d7921315 | 12004 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12005 | info->bytes_per_line = 8; |
12006 | else | |
12007 | info->bytes_per_line = 7; | |
252b5132 | 12008 | |
26ca5450 | 12009 | info->private_data = &priv; |
252b5132 RH |
12010 | priv.max_fetched = priv.the_buffer; |
12011 | priv.insn_start = pc; | |
252b5132 RH |
12012 | |
12013 | obuf[0] = 0; | |
ce518a5f L |
12014 | for (i = 0; i < MAX_OPERANDS; ++i) |
12015 | { | |
12016 | op_out[i][0] = 0; | |
12017 | op_index[i] = -1; | |
12018 | } | |
252b5132 RH |
12019 | |
12020 | the_info = info; | |
12021 | start_pc = pc; | |
e396998b AM |
12022 | start_codep = priv.the_buffer; |
12023 | codep = priv.the_buffer; | |
252b5132 | 12024 | |
8df14d78 | 12025 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12026 | { |
7d421014 ILT |
12027 | const char *name; |
12028 | ||
5076851f | 12029 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12030 | means we have an incomplete instruction of some sort. Just |
12031 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12032 | if (codep > priv.the_buffer) | |
5076851f | 12033 | { |
e396998b | 12034 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12035 | if (name != NULL) |
12036 | (*info->fprintf_func) (info->stream, "%s", name); | |
12037 | else | |
5076851f | 12038 | { |
7d421014 ILT |
12039 | /* Just print the first byte as a .byte instruction. */ |
12040 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12041 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12042 | } |
5076851f | 12043 | |
7d421014 | 12044 | return 1; |
5076851f ILT |
12045 | } |
12046 | ||
12047 | return -1; | |
12048 | } | |
12049 | ||
52b15da3 | 12050 | obufp = obuf; |
f16cd0d5 L |
12051 | sizeflag = priv.orig_sizeflag; |
12052 | ||
12053 | if (!ckprefix () || rex_used) | |
12054 | { | |
12055 | /* Too many prefixes or unused REX prefixes. */ | |
12056 | for (i = 0; | |
f6dd4781 | 12057 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12058 | i++) |
de882298 | 12059 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12060 | i == 0 ? "" : " ", |
f16cd0d5 | 12061 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12062 | return i; |
f16cd0d5 | 12063 | } |
252b5132 RH |
12064 | |
12065 | insn_codep = codep; | |
12066 | ||
12067 | FETCH_DATA (info, codep + 1); | |
12068 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12069 | ||
3e7d61b2 | 12070 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12071 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12072 | { |
86a80a50 | 12073 | /* Handle prefixes before fwait. */ |
d9949a36 | 12074 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12075 | i++) |
12076 | (*info->fprintf_func) (info->stream, "%s ", | |
12077 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12078 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12079 | return i + 1; |
252b5132 RH |
12080 | } |
12081 | ||
252b5132 RH |
12082 | if (*codep == 0x0f) |
12083 | { | |
eec0f4ca | 12084 | unsigned char threebyte; |
5f40e14d JS |
12085 | |
12086 | codep++; | |
12087 | FETCH_DATA (info, codep + 1); | |
12088 | threebyte = *codep; | |
eec0f4ca | 12089 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12090 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12091 | codep++; |
252b5132 RH |
12092 | } |
12093 | else | |
12094 | { | |
6439fc28 | 12095 | dp = &dis386[*codep]; |
252b5132 | 12096 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12097 | codep++; |
252b5132 | 12098 | } |
246c51aa | 12099 | |
df18fdba L |
12100 | /* Save sizeflag for printing the extra prefixes later before updating |
12101 | it for mnemonic and operand processing. The prefix names depend | |
12102 | only on the address mode. */ | |
12103 | orig_sizeflag = sizeflag; | |
c608c12e | 12104 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12105 | sizeflag ^= AFLAG; |
b844680a | 12106 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12107 | sizeflag ^= DFLAG; |
3ffd33cf | 12108 | |
285ca992 | 12109 | end_codep = codep; |
8bb15339 | 12110 | if (need_modrm) |
252b5132 RH |
12111 | { |
12112 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12113 | modrm.mod = (*codep >> 6) & 3; |
12114 | modrm.reg = (*codep >> 3) & 7; | |
12115 | modrm.rm = *codep & 7; | |
252b5132 RH |
12116 | } |
12117 | ||
42d5f9c6 MS |
12118 | need_vex = 0; |
12119 | need_vex_reg = 0; | |
12120 | vex_w_done = 0; | |
caf0678c | 12121 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12122 | |
ce518a5f | 12123 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12124 | { |
55cf16e1 | 12125 | get_sib (info, sizeflag); |
252b5132 RH |
12126 | dofloat (sizeflag); |
12127 | } | |
12128 | else | |
12129 | { | |
8bb15339 | 12130 | dp = get_valid_dis386 (dp, info); |
b844680a | 12131 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12132 | { |
55cf16e1 | 12133 | get_sib (info, sizeflag); |
ce518a5f L |
12134 | for (i = 0; i < MAX_OPERANDS; ++i) |
12135 | { | |
246c51aa | 12136 | obufp = op_out[i]; |
ce518a5f L |
12137 | op_ad = MAX_OPERANDS - 1 - i; |
12138 | if (dp->op[i].rtn) | |
12139 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12140 | /* For EVEX instruction after the last operand masking |
12141 | should be printed. */ | |
12142 | if (i == 0 && vex.evex) | |
12143 | { | |
12144 | /* Don't print {%k0}. */ | |
12145 | if (vex.mask_register_specifier) | |
12146 | { | |
12147 | oappend ("{"); | |
12148 | oappend (names_mask[vex.mask_register_specifier]); | |
12149 | oappend ("}"); | |
12150 | } | |
12151 | if (vex.zeroing) | |
12152 | oappend ("{z}"); | |
12153 | } | |
ce518a5f | 12154 | } |
6439fc28 | 12155 | } |
252b5132 RH |
12156 | } |
12157 | ||
63c6fc6c L |
12158 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12159 | are all 0s in inverted form. */ | |
12160 | if (need_vex && vex.register_specifier != 0) | |
12161 | { | |
12162 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12163 | return end_codep - priv.the_buffer; | |
12164 | } | |
12165 | ||
d869730d | 12166 | /* Check if the REX prefix is used. */ |
e2e6193d | 12167 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12168 | all_prefixes[last_rex_prefix] = 0; |
12169 | ||
5e6718e4 | 12170 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12171 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12172 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12173 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12174 | all_prefixes[last_seg_prefix] = 0; |
12175 | ||
5e6718e4 | 12176 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12177 | if ((prefixes & PREFIX_ADDR) != 0 |
12178 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12179 | all_prefixes[last_addr_prefix] = 0; | |
12180 | ||
df18fdba L |
12181 | /* Check if the DATA prefix is used. */ |
12182 | if ((prefixes & PREFIX_DATA) != 0 | |
12183 | && (used_prefixes & PREFIX_DATA) != 0) | |
12184 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 12185 | |
df18fdba | 12186 | /* Print the extra prefixes. */ |
f16cd0d5 | 12187 | prefix_length = 0; |
f310f33d | 12188 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12189 | if (all_prefixes[i]) |
12190 | { | |
12191 | const char *name; | |
df18fdba | 12192 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12193 | if (name == NULL) |
12194 | abort (); | |
12195 | prefix_length += strlen (name) + 1; | |
12196 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12197 | } | |
b844680a | 12198 | |
285ca992 L |
12199 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12200 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12201 | used by putop and MMX/SSE operand and may be overriden by the | |
12202 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12203 | separately. */ | |
3888916d | 12204 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
12205 | && dp != &bad_opcode |
12206 | && (((prefixes | |
12207 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
12208 | && (used_prefixes | |
12209 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
12210 | || ((((prefixes | |
12211 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12212 | == PREFIX_DATA) | |
12213 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
12214 | { | |
12215 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12216 | return end_codep - priv.the_buffer; | |
12217 | } | |
12218 | ||
f16cd0d5 L |
12219 | /* Check maximum code length. */ |
12220 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12221 | { | |
12222 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12223 | return MAX_CODE_LENGTH; | |
12224 | } | |
b844680a | 12225 | |
ea397f5b | 12226 | obufp = mnemonicendp; |
f16cd0d5 | 12227 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12228 | oappend (" "); |
12229 | oappend (" "); | |
12230 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12231 | ||
12232 | /* The enter and bound instructions are printed with operands in the same | |
12233 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12234 | if (intel_syntax || two_source_ops) |
252b5132 | 12235 | { |
185b1163 L |
12236 | bfd_vma riprel; |
12237 | ||
ce518a5f | 12238 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12239 | op_txt[i] = op_out[i]; |
246c51aa | 12240 | |
3a8547d2 JB |
12241 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12242 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12243 | { | |
12244 | op_txt[2] = op_out[3]; | |
12245 | op_txt[3] = op_out[2]; | |
12246 | } | |
12247 | ||
ce518a5f L |
12248 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12249 | { | |
6c067bbb RM |
12250 | op_ad = op_index[i]; |
12251 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12252 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12253 | riprel = op_riprel[i]; |
12254 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12255 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12256 | } |
252b5132 RH |
12257 | } |
12258 | else | |
12259 | { | |
ce518a5f | 12260 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12261 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12262 | } |
12263 | ||
ce518a5f L |
12264 | needcomma = 0; |
12265 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12266 | if (*op_txt[i]) | |
12267 | { | |
12268 | if (needcomma) | |
12269 | (*info->fprintf_func) (info->stream, ","); | |
12270 | if (op_index[i] != -1 && !op_riprel[i]) | |
12271 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
12272 | else | |
12273 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12274 | needcomma = 1; | |
12275 | } | |
050dfa73 | 12276 | |
ce518a5f | 12277 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12278 | if (op_index[i] != -1 && op_riprel[i]) |
12279 | { | |
12280 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12281 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12282 | + op_address[op_index[i]]), info); |
185b1163 | 12283 | break; |
52b15da3 | 12284 | } |
e396998b | 12285 | return codep - priv.the_buffer; |
252b5132 RH |
12286 | } |
12287 | ||
6439fc28 | 12288 | static const char *float_mem[] = { |
252b5132 | 12289 | /* d8 */ |
7c52e0e8 L |
12290 | "fadd{s|}", |
12291 | "fmul{s|}", | |
12292 | "fcom{s|}", | |
12293 | "fcomp{s|}", | |
12294 | "fsub{s|}", | |
12295 | "fsubr{s|}", | |
12296 | "fdiv{s|}", | |
12297 | "fdivr{s|}", | |
db6eb5be | 12298 | /* d9 */ |
7c52e0e8 | 12299 | "fld{s|}", |
252b5132 | 12300 | "(bad)", |
7c52e0e8 L |
12301 | "fst{s|}", |
12302 | "fstp{s|}", | |
9306ca4a | 12303 | "fldenvIC", |
252b5132 | 12304 | "fldcw", |
9306ca4a | 12305 | "fNstenvIC", |
252b5132 RH |
12306 | "fNstcw", |
12307 | /* da */ | |
7c52e0e8 L |
12308 | "fiadd{l|}", |
12309 | "fimul{l|}", | |
12310 | "ficom{l|}", | |
12311 | "ficomp{l|}", | |
12312 | "fisub{l|}", | |
12313 | "fisubr{l|}", | |
12314 | "fidiv{l|}", | |
12315 | "fidivr{l|}", | |
252b5132 | 12316 | /* db */ |
7c52e0e8 L |
12317 | "fild{l|}", |
12318 | "fisttp{l|}", | |
12319 | "fist{l|}", | |
12320 | "fistp{l|}", | |
252b5132 | 12321 | "(bad)", |
6439fc28 | 12322 | "fld{t||t|}", |
252b5132 | 12323 | "(bad)", |
6439fc28 | 12324 | "fstp{t||t|}", |
252b5132 | 12325 | /* dc */ |
7c52e0e8 L |
12326 | "fadd{l|}", |
12327 | "fmul{l|}", | |
12328 | "fcom{l|}", | |
12329 | "fcomp{l|}", | |
12330 | "fsub{l|}", | |
12331 | "fsubr{l|}", | |
12332 | "fdiv{l|}", | |
12333 | "fdivr{l|}", | |
252b5132 | 12334 | /* dd */ |
7c52e0e8 L |
12335 | "fld{l|}", |
12336 | "fisttp{ll|}", | |
12337 | "fst{l||}", | |
12338 | "fstp{l|}", | |
9306ca4a | 12339 | "frstorIC", |
252b5132 | 12340 | "(bad)", |
9306ca4a | 12341 | "fNsaveIC", |
252b5132 RH |
12342 | "fNstsw", |
12343 | /* de */ | |
ac465521 JB |
12344 | "fiadd{s|}", |
12345 | "fimul{s|}", | |
12346 | "ficom{s|}", | |
12347 | "ficomp{s|}", | |
12348 | "fisub{s|}", | |
12349 | "fisubr{s|}", | |
12350 | "fidiv{s|}", | |
12351 | "fidivr{s|}", | |
252b5132 | 12352 | /* df */ |
ac465521 JB |
12353 | "fild{s|}", |
12354 | "fisttp{s|}", | |
12355 | "fist{s|}", | |
12356 | "fistp{s|}", | |
252b5132 | 12357 | "fbld", |
7c52e0e8 | 12358 | "fild{ll|}", |
252b5132 | 12359 | "fbstp", |
7c52e0e8 | 12360 | "fistp{ll|}", |
1d9f512f AM |
12361 | }; |
12362 | ||
12363 | static const unsigned char float_mem_mode[] = { | |
12364 | /* d8 */ | |
12365 | d_mode, | |
12366 | d_mode, | |
12367 | d_mode, | |
12368 | d_mode, | |
12369 | d_mode, | |
12370 | d_mode, | |
12371 | d_mode, | |
12372 | d_mode, | |
12373 | /* d9 */ | |
12374 | d_mode, | |
12375 | 0, | |
12376 | d_mode, | |
12377 | d_mode, | |
12378 | 0, | |
12379 | w_mode, | |
12380 | 0, | |
12381 | w_mode, | |
12382 | /* da */ | |
12383 | d_mode, | |
12384 | d_mode, | |
12385 | d_mode, | |
12386 | d_mode, | |
12387 | d_mode, | |
12388 | d_mode, | |
12389 | d_mode, | |
12390 | d_mode, | |
12391 | /* db */ | |
12392 | d_mode, | |
12393 | d_mode, | |
12394 | d_mode, | |
12395 | d_mode, | |
12396 | 0, | |
9306ca4a | 12397 | t_mode, |
1d9f512f | 12398 | 0, |
9306ca4a | 12399 | t_mode, |
1d9f512f AM |
12400 | /* dc */ |
12401 | q_mode, | |
12402 | q_mode, | |
12403 | q_mode, | |
12404 | q_mode, | |
12405 | q_mode, | |
12406 | q_mode, | |
12407 | q_mode, | |
12408 | q_mode, | |
12409 | /* dd */ | |
12410 | q_mode, | |
12411 | q_mode, | |
12412 | q_mode, | |
12413 | q_mode, | |
12414 | 0, | |
12415 | 0, | |
12416 | 0, | |
12417 | w_mode, | |
12418 | /* de */ | |
12419 | w_mode, | |
12420 | w_mode, | |
12421 | w_mode, | |
12422 | w_mode, | |
12423 | w_mode, | |
12424 | w_mode, | |
12425 | w_mode, | |
12426 | w_mode, | |
12427 | /* df */ | |
12428 | w_mode, | |
12429 | w_mode, | |
12430 | w_mode, | |
12431 | w_mode, | |
9306ca4a | 12432 | t_mode, |
1d9f512f | 12433 | q_mode, |
9306ca4a | 12434 | t_mode, |
1d9f512f | 12435 | q_mode |
252b5132 RH |
12436 | }; |
12437 | ||
ce518a5f L |
12438 | #define ST { OP_ST, 0 } |
12439 | #define STi { OP_STi, 0 } | |
252b5132 | 12440 | |
48c97fa1 L |
12441 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12442 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12443 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12444 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12445 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12446 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12447 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12448 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12449 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12450 | |
2da11e11 | 12451 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12452 | /* d8 */ |
12453 | { | |
bf890a93 IT |
12454 | { "fadd", { ST, STi }, 0 }, |
12455 | { "fmul", { ST, STi }, 0 }, | |
12456 | { "fcom", { STi }, 0 }, | |
12457 | { "fcomp", { STi }, 0 }, | |
12458 | { "fsub", { ST, STi }, 0 }, | |
12459 | { "fsubr", { ST, STi }, 0 }, | |
12460 | { "fdiv", { ST, STi }, 0 }, | |
12461 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12462 | }, |
12463 | /* d9 */ | |
12464 | { | |
bf890a93 IT |
12465 | { "fld", { STi }, 0 }, |
12466 | { "fxch", { STi }, 0 }, | |
252b5132 | 12467 | { FGRPd9_2 }, |
592d1631 | 12468 | { Bad_Opcode }, |
252b5132 RH |
12469 | { FGRPd9_4 }, |
12470 | { FGRPd9_5 }, | |
12471 | { FGRPd9_6 }, | |
12472 | { FGRPd9_7 }, | |
12473 | }, | |
12474 | /* da */ | |
12475 | { | |
bf890a93 IT |
12476 | { "fcmovb", { ST, STi }, 0 }, |
12477 | { "fcmove", { ST, STi }, 0 }, | |
12478 | { "fcmovbe",{ ST, STi }, 0 }, | |
12479 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12480 | { Bad_Opcode }, |
252b5132 | 12481 | { FGRPda_5 }, |
592d1631 L |
12482 | { Bad_Opcode }, |
12483 | { Bad_Opcode }, | |
252b5132 RH |
12484 | }, |
12485 | /* db */ | |
12486 | { | |
bf890a93 IT |
12487 | { "fcmovnb",{ ST, STi }, 0 }, |
12488 | { "fcmovne",{ ST, STi }, 0 }, | |
12489 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12490 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12491 | { FGRPdb_4 }, |
bf890a93 IT |
12492 | { "fucomi", { ST, STi }, 0 }, |
12493 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12494 | { Bad_Opcode }, |
252b5132 RH |
12495 | }, |
12496 | /* dc */ | |
12497 | { | |
bf890a93 IT |
12498 | { "fadd", { STi, ST }, 0 }, |
12499 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12500 | { Bad_Opcode }, |
12501 | { Bad_Opcode }, | |
d53e6b98 JB |
12502 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12503 | { "fsub{M|}", { STi, ST }, 0 }, | |
12504 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12505 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12506 | }, |
12507 | /* dd */ | |
12508 | { | |
bf890a93 | 12509 | { "ffree", { STi }, 0 }, |
592d1631 | 12510 | { Bad_Opcode }, |
bf890a93 IT |
12511 | { "fst", { STi }, 0 }, |
12512 | { "fstp", { STi }, 0 }, | |
12513 | { "fucom", { STi }, 0 }, | |
12514 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12515 | { Bad_Opcode }, |
12516 | { Bad_Opcode }, | |
252b5132 RH |
12517 | }, |
12518 | /* de */ | |
12519 | { | |
bf890a93 IT |
12520 | { "faddp", { STi, ST }, 0 }, |
12521 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12522 | { Bad_Opcode }, |
252b5132 | 12523 | { FGRPde_3 }, |
d53e6b98 JB |
12524 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12525 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12526 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12527 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12528 | }, |
12529 | /* df */ | |
12530 | { | |
bf890a93 | 12531 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12532 | { Bad_Opcode }, |
12533 | { Bad_Opcode }, | |
12534 | { Bad_Opcode }, | |
252b5132 | 12535 | { FGRPdf_4 }, |
bf890a93 IT |
12536 | { "fucomip", { ST, STi }, 0 }, |
12537 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12538 | { Bad_Opcode }, |
252b5132 RH |
12539 | }, |
12540 | }; | |
12541 | ||
252b5132 | 12542 | static char *fgrps[][8] = { |
48c97fa1 L |
12543 | /* Bad opcode 0 */ |
12544 | { | |
12545 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12546 | }, | |
12547 | ||
12548 | /* d9_2 1 */ | |
252b5132 RH |
12549 | { |
12550 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12551 | }, | |
12552 | ||
48c97fa1 | 12553 | /* d9_4 2 */ |
252b5132 RH |
12554 | { |
12555 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12556 | }, | |
12557 | ||
48c97fa1 | 12558 | /* d9_5 3 */ |
252b5132 RH |
12559 | { |
12560 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12561 | }, | |
12562 | ||
48c97fa1 | 12563 | /* d9_6 4 */ |
252b5132 RH |
12564 | { |
12565 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12566 | }, | |
12567 | ||
48c97fa1 | 12568 | /* d9_7 5 */ |
252b5132 RH |
12569 | { |
12570 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12571 | }, | |
12572 | ||
48c97fa1 | 12573 | /* da_5 6 */ |
252b5132 RH |
12574 | { |
12575 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12576 | }, | |
12577 | ||
48c97fa1 | 12578 | /* db_4 7 */ |
252b5132 | 12579 | { |
309d3373 JB |
12580 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12581 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12582 | }, |
12583 | ||
48c97fa1 | 12584 | /* de_3 8 */ |
252b5132 RH |
12585 | { |
12586 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12587 | }, | |
12588 | ||
48c97fa1 | 12589 | /* df_4 9 */ |
252b5132 RH |
12590 | { |
12591 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12592 | }, | |
12593 | }; | |
12594 | ||
b6169b20 L |
12595 | static void |
12596 | swap_operand (void) | |
12597 | { | |
12598 | mnemonicendp[0] = '.'; | |
12599 | mnemonicendp[1] = 's'; | |
12600 | mnemonicendp += 2; | |
12601 | } | |
12602 | ||
b844680a L |
12603 | static void |
12604 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12605 | int sizeflag ATTRIBUTE_UNUSED) | |
12606 | { | |
12607 | /* Skip mod/rm byte. */ | |
12608 | MODRM_CHECK; | |
12609 | codep++; | |
12610 | } | |
12611 | ||
252b5132 | 12612 | static void |
26ca5450 | 12613 | dofloat (int sizeflag) |
252b5132 | 12614 | { |
2da11e11 | 12615 | const struct dis386 *dp; |
252b5132 RH |
12616 | unsigned char floatop; |
12617 | ||
12618 | floatop = codep[-1]; | |
12619 | ||
7967e09e | 12620 | if (modrm.mod != 3) |
252b5132 | 12621 | { |
7967e09e | 12622 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12623 | |
12624 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12625 | obufp = op_out[0]; |
6e50d963 | 12626 | op_ad = 2; |
1d9f512f | 12627 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12628 | return; |
12629 | } | |
6608db57 | 12630 | /* Skip mod/rm byte. */ |
4bba6815 | 12631 | MODRM_CHECK; |
252b5132 RH |
12632 | codep++; |
12633 | ||
7967e09e | 12634 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12635 | if (dp->name == NULL) |
12636 | { | |
7967e09e | 12637 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12638 | |
6608db57 | 12639 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12640 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12641 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12642 | } |
12643 | else | |
12644 | { | |
12645 | putop (dp->name, sizeflag); | |
12646 | ||
ce518a5f | 12647 | obufp = op_out[0]; |
6e50d963 | 12648 | op_ad = 2; |
ce518a5f L |
12649 | if (dp->op[0].rtn) |
12650 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12651 | |
ce518a5f | 12652 | obufp = op_out[1]; |
6e50d963 | 12653 | op_ad = 1; |
ce518a5f L |
12654 | if (dp->op[1].rtn) |
12655 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12656 | } |
12657 | } | |
12658 | ||
9ce09ba2 RM |
12659 | /* Like oappend (below), but S is a string starting with '%'. |
12660 | In Intel syntax, the '%' is elided. */ | |
12661 | static void | |
12662 | oappend_maybe_intel (const char *s) | |
12663 | { | |
12664 | oappend (s + intel_syntax); | |
12665 | } | |
12666 | ||
252b5132 | 12667 | static void |
26ca5450 | 12668 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12669 | { |
9ce09ba2 | 12670 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12671 | } |
12672 | ||
252b5132 | 12673 | static void |
26ca5450 | 12674 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12675 | { |
7967e09e | 12676 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12677 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12678 | } |
12679 | ||
6608db57 | 12680 | /* Capital letters in template are macros. */ |
6439fc28 | 12681 | static int |
d3ce72d0 | 12682 | putop (const char *in_template, int sizeflag) |
252b5132 | 12683 | { |
2da11e11 | 12684 | const char *p; |
9306ca4a | 12685 | int alt = 0; |
9d141669 | 12686 | int cond = 1; |
98b528ac L |
12687 | unsigned int l = 0, len = 1; |
12688 | char last[4]; | |
12689 | ||
12690 | #define SAVE_LAST(c) \ | |
12691 | if (l < len && l < sizeof (last)) \ | |
12692 | last[l++] = c; \ | |
12693 | else \ | |
12694 | abort (); | |
252b5132 | 12695 | |
d3ce72d0 | 12696 | for (p = in_template; *p; p++) |
252b5132 RH |
12697 | { |
12698 | switch (*p) | |
12699 | { | |
12700 | default: | |
12701 | *obufp++ = *p; | |
12702 | break; | |
98b528ac L |
12703 | case '%': |
12704 | len++; | |
12705 | break; | |
9d141669 L |
12706 | case '!': |
12707 | cond = 0; | |
12708 | break; | |
6439fc28 | 12709 | case '{': |
6439fc28 | 12710 | if (intel_syntax) |
6439fc28 AM |
12711 | { |
12712 | while (*++p != '|') | |
7c52e0e8 L |
12713 | if (*p == '}' || *p == '\0') |
12714 | abort (); | |
6439fc28 | 12715 | } |
9306ca4a JB |
12716 | /* Fall through. */ |
12717 | case 'I': | |
12718 | alt = 1; | |
12719 | continue; | |
6439fc28 AM |
12720 | case '|': |
12721 | while (*++p != '}') | |
12722 | { | |
12723 | if (*p == '\0') | |
12724 | abort (); | |
12725 | } | |
12726 | break; | |
12727 | case '}': | |
12728 | break; | |
252b5132 | 12729 | case 'A': |
db6eb5be AM |
12730 | if (intel_syntax) |
12731 | break; | |
7967e09e | 12732 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12733 | *obufp++ = 'b'; |
12734 | break; | |
12735 | case 'B': | |
4b06377f L |
12736 | if (l == 0 && len == 1) |
12737 | { | |
12738 | case_B: | |
12739 | if (intel_syntax) | |
12740 | break; | |
12741 | if (sizeflag & SUFFIX_ALWAYS) | |
12742 | *obufp++ = 'b'; | |
12743 | } | |
12744 | else | |
12745 | { | |
12746 | if (l != 1 | |
12747 | || len != 2 | |
12748 | || last[0] != 'L') | |
12749 | { | |
12750 | SAVE_LAST (*p); | |
12751 | break; | |
12752 | } | |
12753 | ||
12754 | if (address_mode == mode_64bit | |
12755 | && !(prefixes & PREFIX_ADDR)) | |
12756 | { | |
12757 | *obufp++ = 'a'; | |
12758 | *obufp++ = 'b'; | |
12759 | *obufp++ = 's'; | |
12760 | } | |
12761 | ||
12762 | goto case_B; | |
12763 | } | |
252b5132 | 12764 | break; |
9306ca4a JB |
12765 | case 'C': |
12766 | if (intel_syntax && !alt) | |
12767 | break; | |
12768 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12769 | { | |
12770 | if (sizeflag & DFLAG) | |
12771 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12772 | else | |
12773 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12774 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12775 | } | |
12776 | break; | |
ed7841b3 JB |
12777 | case 'D': |
12778 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12779 | break; | |
161a04f6 | 12780 | USED_REX (REX_W); |
7967e09e | 12781 | if (modrm.mod == 3) |
ed7841b3 | 12782 | { |
161a04f6 | 12783 | if (rex & REX_W) |
ed7841b3 | 12784 | *obufp++ = 'q'; |
ed7841b3 | 12785 | else |
f16cd0d5 L |
12786 | { |
12787 | if (sizeflag & DFLAG) | |
12788 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12789 | else | |
12790 | *obufp++ = 'w'; | |
12791 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12792 | } | |
ed7841b3 JB |
12793 | } |
12794 | else | |
12795 | *obufp++ = 'w'; | |
12796 | break; | |
252b5132 | 12797 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12798 | if (address_mode == mode_64bit) |
c1a64871 JH |
12799 | { |
12800 | if (sizeflag & AFLAG) | |
12801 | *obufp++ = 'r'; | |
12802 | else | |
12803 | *obufp++ = 'e'; | |
12804 | } | |
12805 | else | |
12806 | if (sizeflag & AFLAG) | |
12807 | *obufp++ = 'e'; | |
3ffd33cf AM |
12808 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12809 | break; | |
12810 | case 'F': | |
db6eb5be AM |
12811 | if (intel_syntax) |
12812 | break; | |
e396998b | 12813 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12814 | { |
12815 | if (sizeflag & AFLAG) | |
cb712a9e | 12816 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12817 | else |
cb712a9e | 12818 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12819 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12820 | } | |
252b5132 | 12821 | break; |
52fd6d94 JB |
12822 | case 'G': |
12823 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12824 | break; | |
161a04f6 | 12825 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12826 | *obufp++ = 'l'; |
12827 | else | |
12828 | *obufp++ = 'w'; | |
161a04f6 | 12829 | if (!(rex & REX_W)) |
52fd6d94 JB |
12830 | used_prefixes |= (prefixes & PREFIX_DATA); |
12831 | break; | |
5dd0794d | 12832 | case 'H': |
db6eb5be AM |
12833 | if (intel_syntax) |
12834 | break; | |
5dd0794d AM |
12835 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12836 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12837 | { | |
12838 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12839 | *obufp++ = ','; | |
12840 | *obufp++ = 'p'; | |
12841 | if (prefixes & PREFIX_DS) | |
12842 | *obufp++ = 't'; | |
12843 | else | |
12844 | *obufp++ = 'n'; | |
12845 | } | |
12846 | break; | |
9306ca4a JB |
12847 | case 'J': |
12848 | if (intel_syntax) | |
12849 | break; | |
12850 | *obufp++ = 'l'; | |
12851 | break; | |
42903f7f L |
12852 | case 'K': |
12853 | USED_REX (REX_W); | |
12854 | if (rex & REX_W) | |
12855 | *obufp++ = 'q'; | |
12856 | else | |
12857 | *obufp++ = 'd'; | |
12858 | break; | |
6dd5059a | 12859 | case 'Z': |
04d824a4 JB |
12860 | if (l != 0 || len != 1) |
12861 | { | |
12862 | if (l != 1 || len != 2 || last[0] != 'X') | |
12863 | { | |
12864 | SAVE_LAST (*p); | |
12865 | break; | |
12866 | } | |
12867 | if (!need_vex || !vex.evex) | |
12868 | abort (); | |
12869 | if (intel_syntax | |
12870 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12871 | break; | |
12872 | switch (vex.length) | |
12873 | { | |
12874 | case 128: | |
12875 | *obufp++ = 'x'; | |
12876 | break; | |
12877 | case 256: | |
12878 | *obufp++ = 'y'; | |
12879 | break; | |
12880 | case 512: | |
12881 | *obufp++ = 'z'; | |
12882 | break; | |
12883 | default: | |
12884 | abort (); | |
12885 | } | |
12886 | break; | |
12887 | } | |
6dd5059a L |
12888 | if (intel_syntax) |
12889 | break; | |
12890 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12891 | { | |
12892 | *obufp++ = 'q'; | |
12893 | break; | |
12894 | } | |
12895 | /* Fall through. */ | |
98b528ac | 12896 | goto case_L; |
252b5132 | 12897 | case 'L': |
98b528ac L |
12898 | if (l != 0 || len != 1) |
12899 | { | |
12900 | SAVE_LAST (*p); | |
12901 | break; | |
12902 | } | |
12903 | case_L: | |
db6eb5be AM |
12904 | if (intel_syntax) |
12905 | break; | |
252b5132 RH |
12906 | if (sizeflag & SUFFIX_ALWAYS) |
12907 | *obufp++ = 'l'; | |
252b5132 | 12908 | break; |
9d141669 L |
12909 | case 'M': |
12910 | if (intel_mnemonic != cond) | |
12911 | *obufp++ = 'r'; | |
12912 | break; | |
252b5132 RH |
12913 | case 'N': |
12914 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12915 | *obufp++ = 'n'; | |
7d421014 ILT |
12916 | else |
12917 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12918 | break; |
52b15da3 | 12919 | case 'O': |
161a04f6 L |
12920 | USED_REX (REX_W); |
12921 | if (rex & REX_W) | |
6439fc28 | 12922 | *obufp++ = 'o'; |
a35ca55a JB |
12923 | else if (intel_syntax && (sizeflag & DFLAG)) |
12924 | *obufp++ = 'q'; | |
52b15da3 JH |
12925 | else |
12926 | *obufp++ = 'd'; | |
161a04f6 | 12927 | if (!(rex & REX_W)) |
a35ca55a | 12928 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12929 | break; |
07f5af7d L |
12930 | case '&': |
12931 | if (!intel_syntax | |
12932 | && address_mode == mode_64bit | |
12933 | && isa64 == intel64) | |
12934 | { | |
12935 | *obufp++ = 'q'; | |
12936 | break; | |
12937 | } | |
12938 | /* Fall through. */ | |
6439fc28 | 12939 | case 'T': |
d9e3625e L |
12940 | if (!intel_syntax |
12941 | && address_mode == mode_64bit | |
7bb15c6f | 12942 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12943 | { |
12944 | *obufp++ = 'q'; | |
12945 | break; | |
12946 | } | |
6608db57 | 12947 | /* Fall through. */ |
4b4c407a | 12948 | goto case_P; |
252b5132 | 12949 | case 'P': |
4b4c407a | 12950 | if (l == 0 && len == 1) |
d9e3625e | 12951 | { |
4b4c407a L |
12952 | case_P: |
12953 | if (intel_syntax) | |
d9e3625e | 12954 | { |
4b4c407a L |
12955 | if ((rex & REX_W) == 0 |
12956 | && (prefixes & PREFIX_DATA)) | |
12957 | { | |
12958 | if ((sizeflag & DFLAG) == 0) | |
12959 | *obufp++ = 'w'; | |
12960 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12961 | } | |
12962 | break; | |
12963 | } | |
12964 | if ((prefixes & PREFIX_DATA) | |
12965 | || (rex & REX_W) | |
12966 | || (sizeflag & SUFFIX_ALWAYS)) | |
12967 | { | |
12968 | USED_REX (REX_W); | |
12969 | if (rex & REX_W) | |
12970 | *obufp++ = 'q'; | |
12971 | else | |
12972 | { | |
12973 | if (sizeflag & DFLAG) | |
12974 | *obufp++ = 'l'; | |
12975 | else | |
12976 | *obufp++ = 'w'; | |
12977 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12978 | } | |
d9e3625e | 12979 | } |
d9e3625e | 12980 | } |
4b4c407a | 12981 | else |
252b5132 | 12982 | { |
4b4c407a L |
12983 | if (l != 1 || len != 2 || last[0] != 'L') |
12984 | { | |
12985 | SAVE_LAST (*p); | |
12986 | break; | |
12987 | } | |
12988 | ||
12989 | if ((prefixes & PREFIX_DATA) | |
12990 | || (rex & REX_W) | |
12991 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12992 | { |
4b4c407a L |
12993 | USED_REX (REX_W); |
12994 | if (rex & REX_W) | |
12995 | *obufp++ = 'q'; | |
12996 | else | |
12997 | { | |
12998 | if (sizeflag & DFLAG) | |
12999 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13000 | else | |
13001 | *obufp++ = 'w'; | |
13002 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13003 | } | |
52b15da3 | 13004 | } |
252b5132 RH |
13005 | } |
13006 | break; | |
6439fc28 | 13007 | case 'U': |
db6eb5be AM |
13008 | if (intel_syntax) |
13009 | break; | |
7bb15c6f | 13010 | if (address_mode == mode_64bit |
6c067bbb | 13011 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13012 | { |
7967e09e | 13013 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13014 | *obufp++ = 'q'; |
6439fc28 AM |
13015 | break; |
13016 | } | |
6608db57 | 13017 | /* Fall through. */ |
98b528ac | 13018 | goto case_Q; |
252b5132 | 13019 | case 'Q': |
98b528ac | 13020 | if (l == 0 && len == 1) |
252b5132 | 13021 | { |
98b528ac L |
13022 | case_Q: |
13023 | if (intel_syntax && !alt) | |
13024 | break; | |
13025 | USED_REX (REX_W); | |
13026 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13027 | { |
98b528ac L |
13028 | if (rex & REX_W) |
13029 | *obufp++ = 'q'; | |
52b15da3 | 13030 | else |
98b528ac L |
13031 | { |
13032 | if (sizeflag & DFLAG) | |
13033 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13034 | else | |
13035 | *obufp++ = 'w'; | |
f16cd0d5 | 13036 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13037 | } |
52b15da3 | 13038 | } |
98b528ac L |
13039 | } |
13040 | else | |
13041 | { | |
13042 | if (l != 1 || len != 2 || last[0] != 'L') | |
13043 | { | |
13044 | SAVE_LAST (*p); | |
13045 | break; | |
13046 | } | |
13047 | if (intel_syntax | |
13048 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13049 | break; | |
13050 | if ((rex & REX_W)) | |
13051 | { | |
13052 | USED_REX (REX_W); | |
13053 | *obufp++ = 'q'; | |
13054 | } | |
13055 | else | |
13056 | *obufp++ = 'l'; | |
252b5132 RH |
13057 | } |
13058 | break; | |
13059 | case 'R': | |
161a04f6 L |
13060 | USED_REX (REX_W); |
13061 | if (rex & REX_W) | |
a35ca55a JB |
13062 | *obufp++ = 'q'; |
13063 | else if (sizeflag & DFLAG) | |
c608c12e | 13064 | { |
a35ca55a | 13065 | if (intel_syntax) |
c608c12e | 13066 | *obufp++ = 'd'; |
c608c12e | 13067 | else |
a35ca55a | 13068 | *obufp++ = 'l'; |
c608c12e | 13069 | } |
252b5132 | 13070 | else |
a35ca55a JB |
13071 | *obufp++ = 'w'; |
13072 | if (intel_syntax && !p[1] | |
161a04f6 | 13073 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13074 | *obufp++ = 'e'; |
161a04f6 | 13075 | if (!(rex & REX_W)) |
52b15da3 | 13076 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13077 | break; |
1a114b12 | 13078 | case 'V': |
4b06377f | 13079 | if (l == 0 && len == 1) |
1a114b12 | 13080 | { |
4b06377f L |
13081 | if (intel_syntax) |
13082 | break; | |
7bb15c6f | 13083 | if (address_mode == mode_64bit |
6c067bbb | 13084 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13085 | { |
13086 | if (sizeflag & SUFFIX_ALWAYS) | |
13087 | *obufp++ = 'q'; | |
13088 | break; | |
13089 | } | |
13090 | } | |
13091 | else | |
13092 | { | |
13093 | if (l != 1 | |
13094 | || len != 2 | |
13095 | || last[0] != 'L') | |
13096 | { | |
13097 | SAVE_LAST (*p); | |
13098 | break; | |
13099 | } | |
13100 | ||
13101 | if (rex & REX_W) | |
13102 | { | |
13103 | *obufp++ = 'a'; | |
13104 | *obufp++ = 'b'; | |
13105 | *obufp++ = 's'; | |
13106 | } | |
1a114b12 JB |
13107 | } |
13108 | /* Fall through. */ | |
4b06377f | 13109 | goto case_S; |
252b5132 | 13110 | case 'S': |
4b06377f | 13111 | if (l == 0 && len == 1) |
252b5132 | 13112 | { |
4b06377f L |
13113 | case_S: |
13114 | if (intel_syntax) | |
13115 | break; | |
13116 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13117 | { |
4b06377f L |
13118 | if (rex & REX_W) |
13119 | *obufp++ = 'q'; | |
52b15da3 | 13120 | else |
4b06377f L |
13121 | { |
13122 | if (sizeflag & DFLAG) | |
13123 | *obufp++ = 'l'; | |
13124 | else | |
13125 | *obufp++ = 'w'; | |
13126 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13127 | } | |
13128 | } | |
13129 | } | |
13130 | else | |
13131 | { | |
13132 | if (l != 1 | |
13133 | || len != 2 | |
13134 | || last[0] != 'L') | |
13135 | { | |
13136 | SAVE_LAST (*p); | |
13137 | break; | |
52b15da3 | 13138 | } |
4b06377f L |
13139 | |
13140 | if (address_mode == mode_64bit | |
13141 | && !(prefixes & PREFIX_ADDR)) | |
13142 | { | |
13143 | *obufp++ = 'a'; | |
13144 | *obufp++ = 'b'; | |
13145 | *obufp++ = 's'; | |
13146 | } | |
13147 | ||
13148 | goto case_S; | |
252b5132 | 13149 | } |
252b5132 | 13150 | break; |
041bd2e0 | 13151 | case 'X': |
c0f3af97 L |
13152 | if (l != 0 || len != 1) |
13153 | { | |
13154 | SAVE_LAST (*p); | |
13155 | break; | |
13156 | } | |
13157 | if (need_vex && vex.prefix) | |
13158 | { | |
13159 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13160 | *obufp++ = 'd'; | |
13161 | else | |
13162 | *obufp++ = 's'; | |
13163 | } | |
041bd2e0 | 13164 | else |
f16cd0d5 L |
13165 | { |
13166 | if (prefixes & PREFIX_DATA) | |
13167 | *obufp++ = 'd'; | |
13168 | else | |
13169 | *obufp++ = 's'; | |
13170 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13171 | } | |
041bd2e0 | 13172 | break; |
76f227a5 | 13173 | case 'Y': |
c0f3af97 | 13174 | if (l == 0 && len == 1) |
9646c87b | 13175 | abort (); |
c0f3af97 L |
13176 | else |
13177 | { | |
13178 | if (l != 1 || len != 2 || last[0] != 'X') | |
13179 | { | |
13180 | SAVE_LAST (*p); | |
13181 | break; | |
13182 | } | |
13183 | if (!need_vex) | |
13184 | abort (); | |
13185 | if (intel_syntax | |
04d824a4 | 13186 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13187 | break; |
13188 | switch (vex.length) | |
13189 | { | |
13190 | case 128: | |
13191 | *obufp++ = 'x'; | |
13192 | break; | |
13193 | case 256: | |
13194 | *obufp++ = 'y'; | |
13195 | break; | |
04d824a4 JB |
13196 | case 512: |
13197 | if (!vex.evex) | |
c0f3af97 | 13198 | default: |
04d824a4 | 13199 | abort (); |
c0f3af97 | 13200 | } |
76f227a5 JH |
13201 | } |
13202 | break; | |
252b5132 | 13203 | case 'W': |
0bfee649 | 13204 | if (l == 0 && len == 1) |
a35ca55a | 13205 | { |
0bfee649 L |
13206 | /* operand size flag for cwtl, cbtw */ |
13207 | USED_REX (REX_W); | |
13208 | if (rex & REX_W) | |
13209 | { | |
13210 | if (intel_syntax) | |
13211 | *obufp++ = 'd'; | |
13212 | else | |
13213 | *obufp++ = 'l'; | |
13214 | } | |
13215 | else if (sizeflag & DFLAG) | |
13216 | *obufp++ = 'w'; | |
a35ca55a | 13217 | else |
0bfee649 L |
13218 | *obufp++ = 'b'; |
13219 | if (!(rex & REX_W)) | |
13220 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13221 | } |
252b5132 | 13222 | else |
0bfee649 | 13223 | { |
6c30d220 L |
13224 | if (l != 1 |
13225 | || len != 2 | |
13226 | || (last[0] != 'X' | |
13227 | && last[0] != 'L')) | |
0bfee649 L |
13228 | { |
13229 | SAVE_LAST (*p); | |
13230 | break; | |
13231 | } | |
13232 | if (!need_vex) | |
13233 | abort (); | |
6c30d220 L |
13234 | if (last[0] == 'X') |
13235 | *obufp++ = vex.w ? 'd': 's'; | |
13236 | else | |
13237 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13238 | } |
252b5132 | 13239 | break; |
a72d2af2 L |
13240 | case '^': |
13241 | if (intel_syntax) | |
13242 | break; | |
13243 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13244 | { | |
13245 | if (sizeflag & DFLAG) | |
13246 | *obufp++ = 'l'; | |
13247 | else | |
13248 | *obufp++ = 'w'; | |
13249 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13250 | } | |
13251 | break; | |
5db04b09 L |
13252 | case '@': |
13253 | if (intel_syntax) | |
13254 | break; | |
13255 | if (address_mode == mode_64bit | |
13256 | && (isa64 == intel64 | |
13257 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13258 | *obufp++ = 'q'; | |
13259 | else if ((prefixes & PREFIX_DATA)) | |
13260 | { | |
13261 | if (!(sizeflag & DFLAG)) | |
13262 | *obufp++ = 'w'; | |
13263 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13264 | } | |
13265 | break; | |
252b5132 | 13266 | } |
9306ca4a | 13267 | alt = 0; |
252b5132 RH |
13268 | } |
13269 | *obufp = 0; | |
ea397f5b | 13270 | mnemonicendp = obufp; |
6439fc28 | 13271 | return 0; |
252b5132 RH |
13272 | } |
13273 | ||
13274 | static void | |
26ca5450 | 13275 | oappend (const char *s) |
252b5132 | 13276 | { |
ea397f5b | 13277 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13278 | } |
13279 | ||
13280 | static void | |
26ca5450 | 13281 | append_seg (void) |
252b5132 | 13282 | { |
285ca992 L |
13283 | /* Only print the active segment register. */ |
13284 | if (!active_seg_prefix) | |
13285 | return; | |
13286 | ||
13287 | used_prefixes |= active_seg_prefix; | |
13288 | switch (active_seg_prefix) | |
7d421014 | 13289 | { |
285ca992 | 13290 | case PREFIX_CS: |
9ce09ba2 | 13291 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13292 | break; |
13293 | case PREFIX_DS: | |
9ce09ba2 | 13294 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13295 | break; |
13296 | case PREFIX_SS: | |
9ce09ba2 | 13297 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13298 | break; |
13299 | case PREFIX_ES: | |
9ce09ba2 | 13300 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13301 | break; |
13302 | case PREFIX_FS: | |
9ce09ba2 | 13303 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13304 | break; |
13305 | case PREFIX_GS: | |
9ce09ba2 | 13306 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13307 | break; |
13308 | default: | |
13309 | break; | |
7d421014 | 13310 | } |
252b5132 RH |
13311 | } |
13312 | ||
13313 | static void | |
26ca5450 | 13314 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13315 | { |
13316 | if (!intel_syntax) | |
13317 | oappend ("*"); | |
13318 | OP_E (bytemode, sizeflag); | |
13319 | } | |
13320 | ||
52b15da3 | 13321 | static void |
26ca5450 | 13322 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13323 | { |
cb712a9e | 13324 | if (address_mode == mode_64bit) |
52b15da3 JH |
13325 | { |
13326 | if (hex) | |
13327 | { | |
13328 | char tmp[30]; | |
13329 | int i; | |
13330 | buf[0] = '0'; | |
13331 | buf[1] = 'x'; | |
13332 | sprintf_vma (tmp, disp); | |
6608db57 | 13333 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13334 | strcpy (buf + 2, tmp + i); |
13335 | } | |
13336 | else | |
13337 | { | |
13338 | bfd_signed_vma v = disp; | |
13339 | char tmp[30]; | |
13340 | int i; | |
13341 | if (v < 0) | |
13342 | { | |
13343 | *(buf++) = '-'; | |
13344 | v = -disp; | |
6608db57 | 13345 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13346 | if (v < 0) |
13347 | { | |
13348 | strcpy (buf, "9223372036854775808"); | |
13349 | return; | |
13350 | } | |
13351 | } | |
13352 | if (!v) | |
13353 | { | |
13354 | strcpy (buf, "0"); | |
13355 | return; | |
13356 | } | |
13357 | ||
13358 | i = 0; | |
13359 | tmp[29] = 0; | |
13360 | while (v) | |
13361 | { | |
6608db57 | 13362 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13363 | v /= 10; |
13364 | i++; | |
13365 | } | |
13366 | strcpy (buf, tmp + 29 - i); | |
13367 | } | |
13368 | } | |
13369 | else | |
13370 | { | |
13371 | if (hex) | |
13372 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13373 | else | |
13374 | sprintf (buf, "%d", (int) disp); | |
13375 | } | |
13376 | } | |
13377 | ||
5d669648 L |
13378 | /* Put DISP in BUF as signed hex number. */ |
13379 | ||
13380 | static void | |
13381 | print_displacement (char *buf, bfd_vma disp) | |
13382 | { | |
13383 | bfd_signed_vma val = disp; | |
13384 | char tmp[30]; | |
13385 | int i, j = 0; | |
13386 | ||
13387 | if (val < 0) | |
13388 | { | |
13389 | buf[j++] = '-'; | |
13390 | val = -disp; | |
13391 | ||
13392 | /* Check for possible overflow. */ | |
13393 | if (val < 0) | |
13394 | { | |
13395 | switch (address_mode) | |
13396 | { | |
13397 | case mode_64bit: | |
13398 | strcpy (buf + j, "0x8000000000000000"); | |
13399 | break; | |
13400 | case mode_32bit: | |
13401 | strcpy (buf + j, "0x80000000"); | |
13402 | break; | |
13403 | case mode_16bit: | |
13404 | strcpy (buf + j, "0x8000"); | |
13405 | break; | |
13406 | } | |
13407 | return; | |
13408 | } | |
13409 | } | |
13410 | ||
13411 | buf[j++] = '0'; | |
13412 | buf[j++] = 'x'; | |
13413 | ||
0af1713e | 13414 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13415 | for (i = 0; tmp[i] == '0'; i++) |
13416 | continue; | |
13417 | if (tmp[i] == '\0') | |
13418 | i--; | |
13419 | strcpy (buf + j, tmp + i); | |
13420 | } | |
13421 | ||
3f31e633 JB |
13422 | static void |
13423 | intel_operand_size (int bytemode, int sizeflag) | |
13424 | { | |
43234a1e L |
13425 | if (vex.evex |
13426 | && vex.b | |
13427 | && (bytemode == x_mode | |
13428 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13429 | { | |
13430 | if (vex.w) | |
13431 | oappend ("QWORD PTR "); | |
13432 | else | |
13433 | oappend ("DWORD PTR "); | |
13434 | return; | |
13435 | } | |
3f31e633 JB |
13436 | switch (bytemode) |
13437 | { | |
13438 | case b_mode: | |
b6169b20 | 13439 | case b_swap_mode: |
42903f7f | 13440 | case dqb_mode: |
1ba585e8 | 13441 | case db_mode: |
3f31e633 JB |
13442 | oappend ("BYTE PTR "); |
13443 | break; | |
13444 | case w_mode: | |
1ba585e8 | 13445 | case dw_mode: |
3f31e633 JB |
13446 | case dqw_mode: |
13447 | oappend ("WORD PTR "); | |
13448 | break; | |
07f5af7d L |
13449 | case indir_v_mode: |
13450 | if (address_mode == mode_64bit && isa64 == intel64) | |
13451 | { | |
13452 | oappend ("QWORD PTR "); | |
13453 | break; | |
13454 | } | |
1a0670f3 | 13455 | /* Fall through. */ |
1a114b12 | 13456 | case stack_v_mode: |
7bb15c6f | 13457 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13458 | { |
13459 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13460 | break; |
13461 | } | |
1a0670f3 | 13462 | /* Fall through. */ |
3f31e633 | 13463 | case v_mode: |
b6169b20 | 13464 | case v_swap_mode: |
3f31e633 | 13465 | case dq_mode: |
161a04f6 L |
13466 | USED_REX (REX_W); |
13467 | if (rex & REX_W) | |
3f31e633 | 13468 | oappend ("QWORD PTR "); |
3f31e633 | 13469 | else |
f16cd0d5 L |
13470 | { |
13471 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13472 | oappend ("DWORD PTR "); | |
13473 | else | |
13474 | oappend ("WORD PTR "); | |
13475 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13476 | } | |
3f31e633 | 13477 | break; |
52fd6d94 | 13478 | case z_mode: |
161a04f6 | 13479 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13480 | *obufp++ = 'D'; |
13481 | oappend ("WORD PTR "); | |
161a04f6 | 13482 | if (!(rex & REX_W)) |
52fd6d94 JB |
13483 | used_prefixes |= (prefixes & PREFIX_DATA); |
13484 | break; | |
34b772a6 JB |
13485 | case a_mode: |
13486 | if (sizeflag & DFLAG) | |
13487 | oappend ("QWORD PTR "); | |
13488 | else | |
13489 | oappend ("DWORD PTR "); | |
13490 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13491 | break; | |
3f31e633 | 13492 | case d_mode: |
539f890d L |
13493 | case d_scalar_mode: |
13494 | case d_scalar_swap_mode: | |
fa99fab2 | 13495 | case d_swap_mode: |
42903f7f | 13496 | case dqd_mode: |
3f31e633 JB |
13497 | oappend ("DWORD PTR "); |
13498 | break; | |
13499 | case q_mode: | |
539f890d L |
13500 | case q_scalar_mode: |
13501 | case q_scalar_swap_mode: | |
b6169b20 | 13502 | case q_swap_mode: |
3f31e633 JB |
13503 | oappend ("QWORD PTR "); |
13504 | break; | |
d20dee9e | 13505 | case dqa_mode: |
3f31e633 | 13506 | case m_mode: |
cb712a9e | 13507 | if (address_mode == mode_64bit) |
3f31e633 JB |
13508 | oappend ("QWORD PTR "); |
13509 | else | |
13510 | oappend ("DWORD PTR "); | |
13511 | break; | |
13512 | case f_mode: | |
13513 | if (sizeflag & DFLAG) | |
13514 | oappend ("FWORD PTR "); | |
13515 | else | |
13516 | oappend ("DWORD PTR "); | |
13517 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13518 | break; | |
13519 | case t_mode: | |
13520 | oappend ("TBYTE PTR "); | |
13521 | break; | |
13522 | case x_mode: | |
b6169b20 | 13523 | case x_swap_mode: |
43234a1e L |
13524 | case evex_x_gscat_mode: |
13525 | case evex_x_nobcst_mode: | |
53467f57 IT |
13526 | case b_scalar_mode: |
13527 | case w_scalar_mode: | |
c0f3af97 L |
13528 | if (need_vex) |
13529 | { | |
13530 | switch (vex.length) | |
13531 | { | |
13532 | case 128: | |
13533 | oappend ("XMMWORD PTR "); | |
13534 | break; | |
13535 | case 256: | |
13536 | oappend ("YMMWORD PTR "); | |
13537 | break; | |
43234a1e L |
13538 | case 512: |
13539 | oappend ("ZMMWORD PTR "); | |
13540 | break; | |
c0f3af97 L |
13541 | default: |
13542 | abort (); | |
13543 | } | |
13544 | } | |
13545 | else | |
13546 | oappend ("XMMWORD PTR "); | |
13547 | break; | |
13548 | case xmm_mode: | |
3f31e633 JB |
13549 | oappend ("XMMWORD PTR "); |
13550 | break; | |
43234a1e L |
13551 | case ymm_mode: |
13552 | oappend ("YMMWORD PTR "); | |
13553 | break; | |
c0f3af97 | 13554 | case xmmq_mode: |
43234a1e | 13555 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13556 | if (!need_vex) |
13557 | abort (); | |
13558 | ||
13559 | switch (vex.length) | |
13560 | { | |
13561 | case 128: | |
13562 | oappend ("QWORD PTR "); | |
13563 | break; | |
13564 | case 256: | |
13565 | oappend ("XMMWORD PTR "); | |
13566 | break; | |
43234a1e L |
13567 | case 512: |
13568 | oappend ("YMMWORD PTR "); | |
13569 | break; | |
c0f3af97 L |
13570 | default: |
13571 | abort (); | |
13572 | } | |
13573 | break; | |
6c30d220 L |
13574 | case xmm_mb_mode: |
13575 | if (!need_vex) | |
13576 | abort (); | |
13577 | ||
13578 | switch (vex.length) | |
13579 | { | |
13580 | case 128: | |
13581 | case 256: | |
43234a1e | 13582 | case 512: |
6c30d220 L |
13583 | oappend ("BYTE PTR "); |
13584 | break; | |
13585 | default: | |
13586 | abort (); | |
13587 | } | |
13588 | break; | |
13589 | case xmm_mw_mode: | |
13590 | if (!need_vex) | |
13591 | abort (); | |
13592 | ||
13593 | switch (vex.length) | |
13594 | { | |
13595 | case 128: | |
13596 | case 256: | |
43234a1e | 13597 | case 512: |
6c30d220 L |
13598 | oappend ("WORD PTR "); |
13599 | break; | |
13600 | default: | |
13601 | abort (); | |
13602 | } | |
13603 | break; | |
13604 | case xmm_md_mode: | |
13605 | if (!need_vex) | |
13606 | abort (); | |
13607 | ||
13608 | switch (vex.length) | |
13609 | { | |
13610 | case 128: | |
13611 | case 256: | |
43234a1e | 13612 | case 512: |
6c30d220 L |
13613 | oappend ("DWORD PTR "); |
13614 | break; | |
13615 | default: | |
13616 | abort (); | |
13617 | } | |
13618 | break; | |
13619 | case xmm_mq_mode: | |
13620 | if (!need_vex) | |
13621 | abort (); | |
13622 | ||
13623 | switch (vex.length) | |
13624 | { | |
13625 | case 128: | |
13626 | case 256: | |
43234a1e | 13627 | case 512: |
6c30d220 L |
13628 | oappend ("QWORD PTR "); |
13629 | break; | |
13630 | default: | |
13631 | abort (); | |
13632 | } | |
13633 | break; | |
13634 | case xmmdw_mode: | |
13635 | if (!need_vex) | |
13636 | abort (); | |
13637 | ||
13638 | switch (vex.length) | |
13639 | { | |
13640 | case 128: | |
13641 | oappend ("WORD PTR "); | |
13642 | break; | |
13643 | case 256: | |
13644 | oappend ("DWORD PTR "); | |
13645 | break; | |
43234a1e L |
13646 | case 512: |
13647 | oappend ("QWORD PTR "); | |
13648 | break; | |
6c30d220 L |
13649 | default: |
13650 | abort (); | |
13651 | } | |
13652 | break; | |
13653 | case xmmqd_mode: | |
13654 | if (!need_vex) | |
13655 | abort (); | |
13656 | ||
13657 | switch (vex.length) | |
13658 | { | |
13659 | case 128: | |
13660 | oappend ("DWORD PTR "); | |
13661 | break; | |
13662 | case 256: | |
13663 | oappend ("QWORD PTR "); | |
13664 | break; | |
43234a1e L |
13665 | case 512: |
13666 | oappend ("XMMWORD PTR "); | |
13667 | break; | |
6c30d220 L |
13668 | default: |
13669 | abort (); | |
13670 | } | |
13671 | break; | |
c0f3af97 L |
13672 | case ymmq_mode: |
13673 | if (!need_vex) | |
13674 | abort (); | |
13675 | ||
13676 | switch (vex.length) | |
13677 | { | |
13678 | case 128: | |
13679 | oappend ("QWORD PTR "); | |
13680 | break; | |
13681 | case 256: | |
13682 | oappend ("YMMWORD PTR "); | |
13683 | break; | |
43234a1e L |
13684 | case 512: |
13685 | oappend ("ZMMWORD PTR "); | |
13686 | break; | |
c0f3af97 L |
13687 | default: |
13688 | abort (); | |
13689 | } | |
13690 | break; | |
6c30d220 L |
13691 | case ymmxmm_mode: |
13692 | if (!need_vex) | |
13693 | abort (); | |
13694 | ||
13695 | switch (vex.length) | |
13696 | { | |
13697 | case 128: | |
13698 | case 256: | |
13699 | oappend ("XMMWORD PTR "); | |
13700 | break; | |
13701 | default: | |
13702 | abort (); | |
13703 | } | |
13704 | break; | |
fb9c77c7 L |
13705 | case o_mode: |
13706 | oappend ("OWORD PTR "); | |
13707 | break; | |
43234a1e | 13708 | case xmm_mdq_mode: |
0bfee649 | 13709 | case vex_w_dq_mode: |
1c480963 | 13710 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13711 | if (!need_vex) |
13712 | abort (); | |
13713 | ||
13714 | if (vex.w) | |
13715 | oappend ("QWORD PTR "); | |
13716 | else | |
13717 | oappend ("DWORD PTR "); | |
13718 | break; | |
43234a1e L |
13719 | case vex_vsib_d_w_dq_mode: |
13720 | case vex_vsib_q_w_dq_mode: | |
13721 | if (!need_vex) | |
13722 | abort (); | |
13723 | ||
13724 | if (!vex.evex) | |
13725 | { | |
13726 | if (vex.w) | |
13727 | oappend ("QWORD PTR "); | |
13728 | else | |
13729 | oappend ("DWORD PTR "); | |
13730 | } | |
13731 | else | |
13732 | { | |
b28d1bda IT |
13733 | switch (vex.length) |
13734 | { | |
13735 | case 128: | |
13736 | oappend ("XMMWORD PTR "); | |
13737 | break; | |
13738 | case 256: | |
13739 | oappend ("YMMWORD PTR "); | |
13740 | break; | |
13741 | case 512: | |
13742 | oappend ("ZMMWORD PTR "); | |
13743 | break; | |
13744 | default: | |
13745 | abort (); | |
13746 | } | |
43234a1e L |
13747 | } |
13748 | break; | |
5fc35d96 IT |
13749 | case vex_vsib_q_w_d_mode: |
13750 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13751 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13752 | abort (); |
13753 | ||
b28d1bda IT |
13754 | switch (vex.length) |
13755 | { | |
13756 | case 128: | |
13757 | oappend ("QWORD PTR "); | |
13758 | break; | |
13759 | case 256: | |
13760 | oappend ("XMMWORD PTR "); | |
13761 | break; | |
13762 | case 512: | |
13763 | oappend ("YMMWORD PTR "); | |
13764 | break; | |
13765 | default: | |
13766 | abort (); | |
13767 | } | |
5fc35d96 IT |
13768 | |
13769 | break; | |
1ba585e8 IT |
13770 | case mask_bd_mode: |
13771 | if (!need_vex || vex.length != 128) | |
13772 | abort (); | |
13773 | if (vex.w) | |
13774 | oappend ("DWORD PTR "); | |
13775 | else | |
13776 | oappend ("BYTE PTR "); | |
13777 | break; | |
43234a1e L |
13778 | case mask_mode: |
13779 | if (!need_vex) | |
13780 | abort (); | |
1ba585e8 IT |
13781 | if (vex.w) |
13782 | oappend ("QWORD PTR "); | |
13783 | else | |
13784 | oappend ("WORD PTR "); | |
43234a1e | 13785 | break; |
6c75cc62 | 13786 | case v_bnd_mode: |
d276ec69 | 13787 | case v_bndmk_mode: |
3f31e633 JB |
13788 | default: |
13789 | break; | |
13790 | } | |
13791 | } | |
13792 | ||
252b5132 | 13793 | static void |
c0f3af97 | 13794 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13795 | { |
c0f3af97 L |
13796 | int reg = modrm.rm; |
13797 | const char **names; | |
252b5132 | 13798 | |
c0f3af97 L |
13799 | USED_REX (REX_B); |
13800 | if ((rex & REX_B)) | |
13801 | reg += 8; | |
252b5132 | 13802 | |
b6169b20 | 13803 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13804 | && (bytemode == b_swap_mode |
9f79e886 | 13805 | || bytemode == bnd_swap_mode |
60227d64 | 13806 | || bytemode == v_swap_mode)) |
b6169b20 L |
13807 | swap_operand (); |
13808 | ||
c0f3af97 | 13809 | switch (bytemode) |
252b5132 | 13810 | { |
c0f3af97 | 13811 | case b_mode: |
b6169b20 | 13812 | case b_swap_mode: |
c0f3af97 L |
13813 | USED_REX (0); |
13814 | if (rex) | |
13815 | names = names8rex; | |
13816 | else | |
13817 | names = names8; | |
13818 | break; | |
13819 | case w_mode: | |
13820 | names = names16; | |
13821 | break; | |
13822 | case d_mode: | |
1ba585e8 IT |
13823 | case dw_mode: |
13824 | case db_mode: | |
c0f3af97 L |
13825 | names = names32; |
13826 | break; | |
13827 | case q_mode: | |
13828 | names = names64; | |
13829 | break; | |
13830 | case m_mode: | |
6c75cc62 | 13831 | case v_bnd_mode: |
c0f3af97 L |
13832 | names = address_mode == mode_64bit ? names64 : names32; |
13833 | break; | |
7e8b059b | 13834 | case bnd_mode: |
9f79e886 | 13835 | case bnd_swap_mode: |
0d96e4df L |
13836 | if (reg > 0x3) |
13837 | { | |
13838 | oappend ("(bad)"); | |
13839 | return; | |
13840 | } | |
7e8b059b L |
13841 | names = names_bnd; |
13842 | break; | |
07f5af7d L |
13843 | case indir_v_mode: |
13844 | if (address_mode == mode_64bit && isa64 == intel64) | |
13845 | { | |
13846 | names = names64; | |
13847 | break; | |
13848 | } | |
1a0670f3 | 13849 | /* Fall through. */ |
c0f3af97 | 13850 | case stack_v_mode: |
7bb15c6f | 13851 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13852 | { |
c0f3af97 | 13853 | names = names64; |
252b5132 | 13854 | break; |
252b5132 | 13855 | } |
c0f3af97 | 13856 | bytemode = v_mode; |
1a0670f3 | 13857 | /* Fall through. */ |
c0f3af97 | 13858 | case v_mode: |
b6169b20 | 13859 | case v_swap_mode: |
c0f3af97 L |
13860 | case dq_mode: |
13861 | case dqb_mode: | |
13862 | case dqd_mode: | |
13863 | case dqw_mode: | |
d20dee9e | 13864 | case dqa_mode: |
c0f3af97 L |
13865 | USED_REX (REX_W); |
13866 | if (rex & REX_W) | |
13867 | names = names64; | |
c0f3af97 | 13868 | else |
f16cd0d5 | 13869 | { |
7bb15c6f | 13870 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13871 | || (bytemode != v_mode |
13872 | && bytemode != v_swap_mode)) | |
13873 | names = names32; | |
13874 | else | |
13875 | names = names16; | |
13876 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13877 | } | |
c0f3af97 | 13878 | break; |
de89d0a3 IT |
13879 | case va_mode: |
13880 | names = (address_mode == mode_64bit | |
13881 | ? names64 : names32); | |
13882 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13883 | names = (address_mode == mode_16bit |
13884 | ? names16 : names); | |
de89d0a3 IT |
13885 | else |
13886 | { | |
13887 | /* Remove "addr16/addr32". */ | |
13888 | all_prefixes[last_addr_prefix] = 0; | |
13889 | names = (address_mode != mode_32bit | |
13890 | ? names32 : names16); | |
13891 | used_prefixes |= PREFIX_ADDR; | |
13892 | } | |
13893 | break; | |
1ba585e8 | 13894 | case mask_bd_mode: |
43234a1e | 13895 | case mask_mode: |
9889cbb1 L |
13896 | if (reg > 0x7) |
13897 | { | |
13898 | oappend ("(bad)"); | |
13899 | return; | |
13900 | } | |
43234a1e L |
13901 | names = names_mask; |
13902 | break; | |
c0f3af97 L |
13903 | case 0: |
13904 | return; | |
13905 | default: | |
13906 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13907 | return; |
13908 | } | |
c0f3af97 L |
13909 | oappend (names[reg]); |
13910 | } | |
13911 | ||
13912 | static void | |
c1e679ec | 13913 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13914 | { |
13915 | bfd_vma disp = 0; | |
13916 | int add = (rex & REX_B) ? 8 : 0; | |
13917 | int riprel = 0; | |
43234a1e L |
13918 | int shift; |
13919 | ||
13920 | if (vex.evex) | |
13921 | { | |
13922 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13923 | if (vex.b | |
13924 | && bytemode != x_mode | |
90a915bf | 13925 | && bytemode != xmmq_mode |
43234a1e L |
13926 | && bytemode != evex_half_bcst_xmmq_mode) |
13927 | { | |
13928 | BadOp (); | |
13929 | return; | |
13930 | } | |
13931 | switch (bytemode) | |
13932 | { | |
1ba585e8 IT |
13933 | case dqw_mode: |
13934 | case dw_mode: | |
1ba585e8 IT |
13935 | shift = 1; |
13936 | break; | |
13937 | case dqb_mode: | |
13938 | case db_mode: | |
13939 | shift = 0; | |
13940 | break; | |
b50c9f31 JB |
13941 | case dq_mode: |
13942 | if (address_mode != mode_64bit) | |
13943 | { | |
13944 | shift = 2; | |
13945 | break; | |
13946 | } | |
13947 | /* fall through */ | |
43234a1e | 13948 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13949 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13950 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13951 | case vex_vsib_q_w_d_mode: |
43234a1e L |
13952 | case evex_x_gscat_mode: |
13953 | case xmm_mdq_mode: | |
13954 | shift = vex.w ? 3 : 2; | |
13955 | break; | |
43234a1e L |
13956 | case x_mode: |
13957 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13958 | case xmmq_mode: |
43234a1e L |
13959 | if (vex.b) |
13960 | { | |
13961 | shift = vex.w ? 3 : 2; | |
13962 | break; | |
13963 | } | |
1a0670f3 | 13964 | /* Fall through. */ |
43234a1e L |
13965 | case xmmqd_mode: |
13966 | case xmmdw_mode: | |
43234a1e L |
13967 | case ymmq_mode: |
13968 | case evex_x_nobcst_mode: | |
13969 | case x_swap_mode: | |
13970 | switch (vex.length) | |
13971 | { | |
13972 | case 128: | |
13973 | shift = 4; | |
13974 | break; | |
13975 | case 256: | |
13976 | shift = 5; | |
13977 | break; | |
13978 | case 512: | |
13979 | shift = 6; | |
13980 | break; | |
13981 | default: | |
13982 | abort (); | |
13983 | } | |
13984 | break; | |
13985 | case ymm_mode: | |
13986 | shift = 5; | |
13987 | break; | |
13988 | case xmm_mode: | |
13989 | shift = 4; | |
13990 | break; | |
13991 | case xmm_mq_mode: | |
13992 | case q_mode: | |
13993 | case q_scalar_mode: | |
13994 | case q_swap_mode: | |
13995 | case q_scalar_swap_mode: | |
13996 | shift = 3; | |
13997 | break; | |
13998 | case dqd_mode: | |
13999 | case xmm_md_mode: | |
14000 | case d_mode: | |
14001 | case d_scalar_mode: | |
14002 | case d_swap_mode: | |
14003 | case d_scalar_swap_mode: | |
14004 | shift = 2; | |
14005 | break; | |
5074ad8a | 14006 | case w_scalar_mode: |
43234a1e L |
14007 | case xmm_mw_mode: |
14008 | shift = 1; | |
14009 | break; | |
5074ad8a | 14010 | case b_scalar_mode: |
43234a1e L |
14011 | case xmm_mb_mode: |
14012 | shift = 0; | |
14013 | break; | |
d20dee9e L |
14014 | case dqa_mode: |
14015 | shift = address_mode == mode_64bit ? 3 : 2; | |
14016 | break; | |
43234a1e L |
14017 | default: |
14018 | abort (); | |
14019 | } | |
14020 | /* Make necessary corrections to shift for modes that need it. | |
14021 | For these modes we currently have shift 4, 5 or 6 depending on | |
14022 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14023 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14024 | xmmq_mode). In case of broadcast enabled the corrections | |
14025 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14026 | if (!vex.b |
14027 | && (bytemode == xmmq_mode | |
14028 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14029 | shift -= 1; |
14030 | else if (bytemode == xmmqd_mode) | |
14031 | shift -= 2; | |
14032 | else if (bytemode == xmmdw_mode) | |
14033 | shift -= 3; | |
b28d1bda IT |
14034 | else if (bytemode == ymmq_mode && vex.length == 128) |
14035 | shift -= 1; | |
43234a1e L |
14036 | } |
14037 | else | |
14038 | shift = 0; | |
252b5132 | 14039 | |
c0f3af97 | 14040 | USED_REX (REX_B); |
3f31e633 JB |
14041 | if (intel_syntax) |
14042 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14043 | append_seg (); |
14044 | ||
5d669648 | 14045 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14046 | { |
5d669648 L |
14047 | /* 32/64 bit address mode */ |
14048 | int havedisp; | |
252b5132 RH |
14049 | int havesib; |
14050 | int havebase; | |
0f7da397 | 14051 | int haveindex; |
20afcfb7 | 14052 | int needindex; |
1bc60e56 | 14053 | int needaddr32; |
82c18208 | 14054 | int base, rbase; |
91d6fa6a | 14055 | int vindex = 0; |
252b5132 | 14056 | int scale = 0; |
7e8b059b L |
14057 | int addr32flag = !((sizeflag & AFLAG) |
14058 | || bytemode == v_bnd_mode | |
d276ec69 | 14059 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14060 | || bytemode == bnd_mode |
14061 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14062 | const char **indexes64 = names64; |
14063 | const char **indexes32 = names32; | |
252b5132 RH |
14064 | |
14065 | havesib = 0; | |
14066 | havebase = 1; | |
0f7da397 | 14067 | haveindex = 0; |
7967e09e | 14068 | base = modrm.rm; |
252b5132 RH |
14069 | |
14070 | if (base == 4) | |
14071 | { | |
14072 | havesib = 1; | |
dfc8cf43 | 14073 | vindex = sib.index; |
161a04f6 L |
14074 | USED_REX (REX_X); |
14075 | if (rex & REX_X) | |
91d6fa6a | 14076 | vindex += 8; |
6c30d220 L |
14077 | switch (bytemode) |
14078 | { | |
14079 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14080 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14081 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14082 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14083 | if (!need_vex) |
14084 | abort (); | |
43234a1e L |
14085 | if (vex.evex) |
14086 | { | |
14087 | if (!vex.v) | |
14088 | vindex += 16; | |
14089 | } | |
6c30d220 L |
14090 | |
14091 | haveindex = 1; | |
14092 | switch (vex.length) | |
14093 | { | |
14094 | case 128: | |
7bb15c6f | 14095 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14096 | break; |
14097 | case 256: | |
5fc35d96 IT |
14098 | if (!vex.w |
14099 | || bytemode == vex_vsib_q_w_dq_mode | |
14100 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14101 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14102 | else |
7bb15c6f | 14103 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14104 | break; |
43234a1e | 14105 | case 512: |
5fc35d96 IT |
14106 | if (!vex.w |
14107 | || bytemode == vex_vsib_q_w_dq_mode | |
14108 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14109 | indexes64 = indexes32 = names_zmm; |
14110 | else | |
14111 | indexes64 = indexes32 = names_ymm; | |
14112 | break; | |
6c30d220 L |
14113 | default: |
14114 | abort (); | |
14115 | } | |
14116 | break; | |
14117 | default: | |
14118 | haveindex = vindex != 4; | |
14119 | break; | |
14120 | } | |
14121 | scale = sib.scale; | |
14122 | base = sib.base; | |
252b5132 RH |
14123 | codep++; |
14124 | } | |
82c18208 | 14125 | rbase = base + add; |
252b5132 | 14126 | |
7967e09e | 14127 | switch (modrm.mod) |
252b5132 RH |
14128 | { |
14129 | case 0: | |
82c18208 | 14130 | if (base == 5) |
252b5132 RH |
14131 | { |
14132 | havebase = 0; | |
cb712a9e | 14133 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14134 | riprel = 1; |
14135 | disp = get32s (); | |
d276ec69 JB |
14136 | if (riprel && bytemode == v_bndmk_mode) |
14137 | { | |
14138 | oappend ("(bad)"); | |
14139 | return; | |
14140 | } | |
252b5132 RH |
14141 | } |
14142 | break; | |
14143 | case 1: | |
14144 | FETCH_DATA (the_info, codep + 1); | |
14145 | disp = *codep++; | |
14146 | if ((disp & 0x80) != 0) | |
14147 | disp -= 0x100; | |
43234a1e L |
14148 | if (vex.evex && shift > 0) |
14149 | disp <<= shift; | |
252b5132 RH |
14150 | break; |
14151 | case 2: | |
52b15da3 | 14152 | disp = get32s (); |
252b5132 RH |
14153 | break; |
14154 | } | |
14155 | ||
1bc60e56 L |
14156 | needindex = 0; |
14157 | needaddr32 = 0; | |
14158 | if (havesib | |
14159 | && !havebase | |
14160 | && !haveindex | |
14161 | && address_mode != mode_16bit) | |
14162 | { | |
14163 | if (address_mode == mode_64bit) | |
14164 | { | |
14165 | /* Display eiz instead of addr32. */ | |
14166 | needindex = addr32flag; | |
14167 | needaddr32 = 1; | |
14168 | } | |
14169 | else | |
14170 | { | |
14171 | /* In 32-bit mode, we need index register to tell [offset] | |
14172 | from [eiz*1 + offset]. */ | |
14173 | needindex = 1; | |
14174 | } | |
14175 | } | |
14176 | ||
20afcfb7 L |
14177 | havedisp = (havebase |
14178 | || needindex | |
14179 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14180 | |
252b5132 | 14181 | if (!intel_syntax) |
82c18208 | 14182 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14183 | { |
5d669648 L |
14184 | if (havedisp || riprel) |
14185 | print_displacement (scratchbuf, disp); | |
14186 | else | |
14187 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14188 | oappend (scratchbuf); |
52b15da3 JH |
14189 | if (riprel) |
14190 | { | |
14191 | set_op (disp, 1); | |
28596323 | 14192 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14193 | } |
db6eb5be | 14194 | } |
2da11e11 | 14195 | |
1bc60e56 | 14196 | if ((havebase || haveindex || needaddr32 || riprel) |
7e8b059b | 14197 | && (bytemode != v_bnd_mode) |
d276ec69 | 14198 | && (bytemode != v_bndmk_mode) |
9f79e886 JB |
14199 | && (bytemode != bnd_mode) |
14200 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
14201 | used_prefixes |= PREFIX_ADDR; |
14202 | ||
5d669648 | 14203 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14204 | { |
252b5132 | 14205 | *obufp++ = open_char; |
52b15da3 | 14206 | if (intel_syntax && riprel) |
185b1163 L |
14207 | { |
14208 | set_op (disp, 1); | |
28596323 | 14209 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14210 | } |
db6eb5be | 14211 | *obufp = '\0'; |
252b5132 | 14212 | if (havebase) |
7e8b059b | 14213 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14214 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14215 | if (havesib) |
14216 | { | |
db51cc60 L |
14217 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14218 | print index to tell base + index from base. */ | |
14219 | if (scale != 0 | |
20afcfb7 | 14220 | || needindex |
db51cc60 L |
14221 | || haveindex |
14222 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14223 | { |
9306ca4a | 14224 | if (!intel_syntax || havebase) |
db6eb5be | 14225 | { |
9306ca4a JB |
14226 | *obufp++ = separator_char; |
14227 | *obufp = '\0'; | |
db6eb5be | 14228 | } |
db51cc60 | 14229 | if (haveindex) |
7e8b059b | 14230 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14231 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14232 | else |
7e8b059b | 14233 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14234 | ? index64 : index32); |
14235 | ||
db6eb5be AM |
14236 | *obufp++ = scale_char; |
14237 | *obufp = '\0'; | |
14238 | sprintf (scratchbuf, "%d", 1 << scale); | |
14239 | oappend (scratchbuf); | |
14240 | } | |
252b5132 | 14241 | } |
185b1163 | 14242 | if (intel_syntax |
82c18208 | 14243 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14244 | { |
db51cc60 | 14245 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14246 | { |
14247 | *obufp++ = '+'; | |
14248 | *obufp = '\0'; | |
14249 | } | |
05203043 | 14250 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14251 | { |
14252 | *obufp++ = '-'; | |
14253 | *obufp = '\0'; | |
14254 | disp = - (bfd_signed_vma) disp; | |
14255 | } | |
14256 | ||
db51cc60 L |
14257 | if (havedisp) |
14258 | print_displacement (scratchbuf, disp); | |
14259 | else | |
14260 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14261 | oappend (scratchbuf); |
14262 | } | |
252b5132 RH |
14263 | |
14264 | *obufp++ = close_char; | |
db6eb5be | 14265 | *obufp = '\0'; |
252b5132 RH |
14266 | } |
14267 | else if (intel_syntax) | |
db6eb5be | 14268 | { |
82c18208 | 14269 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14270 | { |
285ca992 | 14271 | if (!active_seg_prefix) |
252b5132 | 14272 | { |
d708bcba | 14273 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14274 | oappend (":"); |
14275 | } | |
52b15da3 | 14276 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14277 | oappend (scratchbuf); |
14278 | } | |
14279 | } | |
252b5132 RH |
14280 | } |
14281 | else | |
f16cd0d5 L |
14282 | { |
14283 | /* 16 bit address mode */ | |
14284 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14285 | switch (modrm.mod) |
252b5132 RH |
14286 | { |
14287 | case 0: | |
7967e09e | 14288 | if (modrm.rm == 6) |
252b5132 RH |
14289 | { |
14290 | disp = get16 (); | |
14291 | if ((disp & 0x8000) != 0) | |
14292 | disp -= 0x10000; | |
14293 | } | |
14294 | break; | |
14295 | case 1: | |
14296 | FETCH_DATA (the_info, codep + 1); | |
14297 | disp = *codep++; | |
14298 | if ((disp & 0x80) != 0) | |
14299 | disp -= 0x100; | |
65f3ed04 JB |
14300 | if (vex.evex && shift > 0) |
14301 | disp <<= shift; | |
252b5132 RH |
14302 | break; |
14303 | case 2: | |
14304 | disp = get16 (); | |
14305 | if ((disp & 0x8000) != 0) | |
14306 | disp -= 0x10000; | |
14307 | break; | |
14308 | } | |
14309 | ||
14310 | if (!intel_syntax) | |
7967e09e | 14311 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14312 | { |
5d669648 | 14313 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14314 | oappend (scratchbuf); |
14315 | } | |
252b5132 | 14316 | |
7967e09e | 14317 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14318 | { |
14319 | *obufp++ = open_char; | |
db6eb5be | 14320 | *obufp = '\0'; |
7967e09e | 14321 | oappend (index16[modrm.rm]); |
5d669648 L |
14322 | if (intel_syntax |
14323 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14324 | { |
5d669648 | 14325 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14326 | { |
14327 | *obufp++ = '+'; | |
14328 | *obufp = '\0'; | |
14329 | } | |
7967e09e | 14330 | else if (modrm.mod != 1) |
3d456fa1 JB |
14331 | { |
14332 | *obufp++ = '-'; | |
14333 | *obufp = '\0'; | |
14334 | disp = - (bfd_signed_vma) disp; | |
14335 | } | |
14336 | ||
5d669648 | 14337 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14338 | oappend (scratchbuf); |
14339 | } | |
14340 | ||
db6eb5be AM |
14341 | *obufp++ = close_char; |
14342 | *obufp = '\0'; | |
252b5132 | 14343 | } |
3d456fa1 JB |
14344 | else if (intel_syntax) |
14345 | { | |
285ca992 | 14346 | if (!active_seg_prefix) |
3d456fa1 JB |
14347 | { |
14348 | oappend (names_seg[ds_reg - es_reg]); | |
14349 | oappend (":"); | |
14350 | } | |
14351 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14352 | oappend (scratchbuf); | |
14353 | } | |
252b5132 | 14354 | } |
43234a1e L |
14355 | if (vex.evex && vex.b |
14356 | && (bytemode == x_mode | |
90a915bf | 14357 | || bytemode == xmmq_mode |
43234a1e L |
14358 | || bytemode == evex_half_bcst_xmmq_mode)) |
14359 | { | |
90a915bf IT |
14360 | if (vex.w |
14361 | || bytemode == xmmq_mode | |
14362 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14363 | { |
14364 | switch (vex.length) | |
14365 | { | |
14366 | case 128: | |
14367 | oappend ("{1to2}"); | |
14368 | break; | |
14369 | case 256: | |
14370 | oappend ("{1to4}"); | |
14371 | break; | |
14372 | case 512: | |
14373 | oappend ("{1to8}"); | |
14374 | break; | |
14375 | default: | |
14376 | abort (); | |
14377 | } | |
14378 | } | |
43234a1e | 14379 | else |
b28d1bda IT |
14380 | { |
14381 | switch (vex.length) | |
14382 | { | |
14383 | case 128: | |
14384 | oappend ("{1to4}"); | |
14385 | break; | |
14386 | case 256: | |
14387 | oappend ("{1to8}"); | |
14388 | break; | |
14389 | case 512: | |
14390 | oappend ("{1to16}"); | |
14391 | break; | |
14392 | default: | |
14393 | abort (); | |
14394 | } | |
14395 | } | |
43234a1e | 14396 | } |
252b5132 RH |
14397 | } |
14398 | ||
c0f3af97 | 14399 | static void |
8b3f93e7 | 14400 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14401 | { |
14402 | /* Skip mod/rm byte. */ | |
14403 | MODRM_CHECK; | |
14404 | codep++; | |
14405 | ||
14406 | if (modrm.mod == 3) | |
14407 | OP_E_register (bytemode, sizeflag); | |
14408 | else | |
c1e679ec | 14409 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14410 | } |
14411 | ||
252b5132 | 14412 | static void |
26ca5450 | 14413 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14414 | { |
52b15da3 | 14415 | int add = 0; |
c0a30a9f | 14416 | const char **names; |
161a04f6 L |
14417 | USED_REX (REX_R); |
14418 | if (rex & REX_R) | |
52b15da3 | 14419 | add += 8; |
252b5132 RH |
14420 | switch (bytemode) |
14421 | { | |
14422 | case b_mode: | |
52b15da3 JH |
14423 | USED_REX (0); |
14424 | if (rex) | |
7967e09e | 14425 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14426 | else |
7967e09e | 14427 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14428 | break; |
14429 | case w_mode: | |
7967e09e | 14430 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14431 | break; |
14432 | case d_mode: | |
1ba585e8 IT |
14433 | case db_mode: |
14434 | case dw_mode: | |
7967e09e | 14435 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14436 | break; |
14437 | case q_mode: | |
7967e09e | 14438 | oappend (names64[modrm.reg + add]); |
252b5132 | 14439 | break; |
7e8b059b | 14440 | case bnd_mode: |
0d96e4df L |
14441 | if (modrm.reg > 0x3) |
14442 | { | |
14443 | oappend ("(bad)"); | |
14444 | return; | |
14445 | } | |
7e8b059b L |
14446 | oappend (names_bnd[modrm.reg]); |
14447 | break; | |
252b5132 | 14448 | case v_mode: |
9306ca4a | 14449 | case dq_mode: |
42903f7f L |
14450 | case dqb_mode: |
14451 | case dqd_mode: | |
9306ca4a | 14452 | case dqw_mode: |
161a04f6 L |
14453 | USED_REX (REX_W); |
14454 | if (rex & REX_W) | |
7967e09e | 14455 | oappend (names64[modrm.reg + add]); |
252b5132 | 14456 | else |
f16cd0d5 L |
14457 | { |
14458 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
14459 | oappend (names32[modrm.reg + add]); | |
14460 | else | |
14461 | oappend (names16[modrm.reg + add]); | |
14462 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14463 | } | |
252b5132 | 14464 | break; |
c0a30a9f L |
14465 | case va_mode: |
14466 | names = (address_mode == mode_64bit | |
14467 | ? names64 : names32); | |
14468 | if (!(prefixes & PREFIX_ADDR)) | |
14469 | { | |
14470 | if (address_mode == mode_16bit) | |
14471 | names = names16; | |
14472 | } | |
14473 | else | |
14474 | { | |
14475 | /* Remove "addr16/addr32". */ | |
14476 | all_prefixes[last_addr_prefix] = 0; | |
14477 | names = (address_mode != mode_32bit | |
14478 | ? names32 : names16); | |
14479 | used_prefixes |= PREFIX_ADDR; | |
14480 | } | |
14481 | oappend (names[modrm.reg + add]); | |
14482 | break; | |
90700ea2 | 14483 | case m_mode: |
cb712a9e | 14484 | if (address_mode == mode_64bit) |
7967e09e | 14485 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14486 | else |
7967e09e | 14487 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14488 | break; |
1ba585e8 | 14489 | case mask_bd_mode: |
43234a1e | 14490 | case mask_mode: |
9889cbb1 L |
14491 | if ((modrm.reg + add) > 0x7) |
14492 | { | |
14493 | oappend ("(bad)"); | |
14494 | return; | |
14495 | } | |
43234a1e L |
14496 | oappend (names_mask[modrm.reg + add]); |
14497 | break; | |
252b5132 RH |
14498 | default: |
14499 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14500 | break; | |
14501 | } | |
14502 | } | |
14503 | ||
52b15da3 | 14504 | static bfd_vma |
26ca5450 | 14505 | get64 (void) |
52b15da3 | 14506 | { |
5dd0794d | 14507 | bfd_vma x; |
52b15da3 | 14508 | #ifdef BFD64 |
5dd0794d AM |
14509 | unsigned int a; |
14510 | unsigned int b; | |
14511 | ||
52b15da3 JH |
14512 | FETCH_DATA (the_info, codep + 8); |
14513 | a = *codep++ & 0xff; | |
14514 | a |= (*codep++ & 0xff) << 8; | |
14515 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14516 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14517 | b = *codep++ & 0xff; |
52b15da3 JH |
14518 | b |= (*codep++ & 0xff) << 8; |
14519 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14520 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14521 | x = a + ((bfd_vma) b << 32); |
14522 | #else | |
6608db57 | 14523 | abort (); |
5dd0794d | 14524 | x = 0; |
52b15da3 JH |
14525 | #endif |
14526 | return x; | |
14527 | } | |
14528 | ||
14529 | static bfd_signed_vma | |
26ca5450 | 14530 | get32 (void) |
252b5132 | 14531 | { |
52b15da3 | 14532 | bfd_signed_vma x = 0; |
252b5132 RH |
14533 | |
14534 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14535 | x = *codep++ & (bfd_signed_vma) 0xff; |
14536 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14537 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14538 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14539 | return x; | |
14540 | } | |
14541 | ||
14542 | static bfd_signed_vma | |
26ca5450 | 14543 | get32s (void) |
52b15da3 JH |
14544 | { |
14545 | bfd_signed_vma x = 0; | |
14546 | ||
14547 | FETCH_DATA (the_info, codep + 4); | |
14548 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14549 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14550 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14551 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14552 | ||
14553 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14554 | ||
252b5132 RH |
14555 | return x; |
14556 | } | |
14557 | ||
14558 | static int | |
26ca5450 | 14559 | get16 (void) |
252b5132 RH |
14560 | { |
14561 | int x = 0; | |
14562 | ||
14563 | FETCH_DATA (the_info, codep + 2); | |
14564 | x = *codep++ & 0xff; | |
14565 | x |= (*codep++ & 0xff) << 8; | |
14566 | return x; | |
14567 | } | |
14568 | ||
14569 | static void | |
26ca5450 | 14570 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14571 | { |
14572 | op_index[op_ad] = op_ad; | |
cb712a9e | 14573 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14574 | { |
14575 | op_address[op_ad] = op; | |
14576 | op_riprel[op_ad] = riprel; | |
14577 | } | |
14578 | else | |
14579 | { | |
14580 | /* Mask to get a 32-bit address. */ | |
14581 | op_address[op_ad] = op & 0xffffffff; | |
14582 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14583 | } | |
252b5132 RH |
14584 | } |
14585 | ||
14586 | static void | |
26ca5450 | 14587 | OP_REG (int code, int sizeflag) |
252b5132 | 14588 | { |
2da11e11 | 14589 | const char *s; |
9b60702d | 14590 | int add; |
de882298 RM |
14591 | |
14592 | switch (code) | |
14593 | { | |
14594 | case es_reg: case ss_reg: case cs_reg: | |
14595 | case ds_reg: case fs_reg: case gs_reg: | |
14596 | oappend (names_seg[code - es_reg]); | |
14597 | return; | |
14598 | } | |
14599 | ||
161a04f6 L |
14600 | USED_REX (REX_B); |
14601 | if (rex & REX_B) | |
52b15da3 | 14602 | add = 8; |
9b60702d L |
14603 | else |
14604 | add = 0; | |
52b15da3 JH |
14605 | |
14606 | switch (code) | |
14607 | { | |
52b15da3 JH |
14608 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14609 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14610 | s = names16[code - ax_reg + add]; | |
14611 | break; | |
52b15da3 JH |
14612 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14613 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14614 | USED_REX (0); | |
14615 | if (rex) | |
14616 | s = names8rex[code - al_reg + add]; | |
14617 | else | |
14618 | s = names8[code - al_reg]; | |
14619 | break; | |
6439fc28 AM |
14620 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14621 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14622 | if (address_mode == mode_64bit |
6c067bbb | 14623 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14624 | { |
14625 | s = names64[code - rAX_reg + add]; | |
14626 | break; | |
14627 | } | |
14628 | code += eAX_reg - rAX_reg; | |
6608db57 | 14629 | /* Fall through. */ |
52b15da3 JH |
14630 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14631 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14632 | USED_REX (REX_W); |
14633 | if (rex & REX_W) | |
52b15da3 | 14634 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14635 | else |
f16cd0d5 L |
14636 | { |
14637 | if (sizeflag & DFLAG) | |
14638 | s = names32[code - eAX_reg + add]; | |
14639 | else | |
14640 | s = names16[code - eAX_reg + add]; | |
14641 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14642 | } | |
52b15da3 | 14643 | break; |
52b15da3 JH |
14644 | default: |
14645 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14646 | break; | |
14647 | } | |
14648 | oappend (s); | |
14649 | } | |
14650 | ||
14651 | static void | |
26ca5450 | 14652 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14653 | { |
14654 | const char *s; | |
252b5132 RH |
14655 | |
14656 | switch (code) | |
14657 | { | |
14658 | case indir_dx_reg: | |
d708bcba | 14659 | if (intel_syntax) |
52fd6d94 | 14660 | s = "dx"; |
d708bcba | 14661 | else |
db6eb5be | 14662 | s = "(%dx)"; |
252b5132 RH |
14663 | break; |
14664 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14665 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14666 | s = names16[code - ax_reg]; | |
14667 | break; | |
14668 | case es_reg: case ss_reg: case cs_reg: | |
14669 | case ds_reg: case fs_reg: case gs_reg: | |
14670 | s = names_seg[code - es_reg]; | |
14671 | break; | |
14672 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14673 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14674 | USED_REX (0); |
14675 | if (rex) | |
14676 | s = names8rex[code - al_reg]; | |
14677 | else | |
14678 | s = names8[code - al_reg]; | |
252b5132 RH |
14679 | break; |
14680 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14681 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14682 | USED_REX (REX_W); |
14683 | if (rex & REX_W) | |
52b15da3 | 14684 | s = names64[code - eAX_reg]; |
252b5132 | 14685 | else |
f16cd0d5 L |
14686 | { |
14687 | if (sizeflag & DFLAG) | |
14688 | s = names32[code - eAX_reg]; | |
14689 | else | |
14690 | s = names16[code - eAX_reg]; | |
14691 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14692 | } | |
252b5132 | 14693 | break; |
52fd6d94 | 14694 | case z_mode_ax_reg: |
161a04f6 | 14695 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14696 | s = *names32; |
14697 | else | |
14698 | s = *names16; | |
161a04f6 | 14699 | if (!(rex & REX_W)) |
52fd6d94 JB |
14700 | used_prefixes |= (prefixes & PREFIX_DATA); |
14701 | break; | |
252b5132 RH |
14702 | default: |
14703 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14704 | break; | |
14705 | } | |
14706 | oappend (s); | |
14707 | } | |
14708 | ||
14709 | static void | |
26ca5450 | 14710 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14711 | { |
52b15da3 JH |
14712 | bfd_signed_vma op; |
14713 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14714 | |
14715 | switch (bytemode) | |
14716 | { | |
14717 | case b_mode: | |
14718 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14719 | op = *codep++; |
14720 | mask = 0xff; | |
14721 | break; | |
14722 | case q_mode: | |
cb712a9e | 14723 | if (address_mode == mode_64bit) |
6439fc28 AM |
14724 | { |
14725 | op = get32s (); | |
14726 | break; | |
14727 | } | |
6608db57 | 14728 | /* Fall through. */ |
252b5132 | 14729 | case v_mode: |
161a04f6 L |
14730 | USED_REX (REX_W); |
14731 | if (rex & REX_W) | |
52b15da3 | 14732 | op = get32s (); |
252b5132 | 14733 | else |
52b15da3 | 14734 | { |
f16cd0d5 L |
14735 | if (sizeflag & DFLAG) |
14736 | { | |
14737 | op = get32 (); | |
14738 | mask = 0xffffffff; | |
14739 | } | |
14740 | else | |
14741 | { | |
14742 | op = get16 (); | |
14743 | mask = 0xfffff; | |
14744 | } | |
14745 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14746 | } |
252b5132 RH |
14747 | break; |
14748 | case w_mode: | |
52b15da3 | 14749 | mask = 0xfffff; |
252b5132 RH |
14750 | op = get16 (); |
14751 | break; | |
9306ca4a JB |
14752 | case const_1_mode: |
14753 | if (intel_syntax) | |
6c067bbb | 14754 | oappend ("1"); |
9306ca4a | 14755 | return; |
252b5132 RH |
14756 | default: |
14757 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14758 | return; | |
14759 | } | |
14760 | ||
52b15da3 JH |
14761 | op &= mask; |
14762 | scratchbuf[0] = '$'; | |
d708bcba | 14763 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14764 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14765 | scratchbuf[0] = '\0'; |
14766 | } | |
14767 | ||
14768 | static void | |
26ca5450 | 14769 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
14770 | { |
14771 | bfd_signed_vma op; | |
14772 | bfd_signed_vma mask = -1; | |
14773 | ||
cb712a9e | 14774 | if (address_mode != mode_64bit) |
6439fc28 AM |
14775 | { |
14776 | OP_I (bytemode, sizeflag); | |
14777 | return; | |
14778 | } | |
14779 | ||
52b15da3 JH |
14780 | switch (bytemode) |
14781 | { | |
14782 | case b_mode: | |
14783 | FETCH_DATA (the_info, codep + 1); | |
14784 | op = *codep++; | |
14785 | mask = 0xff; | |
14786 | break; | |
14787 | case v_mode: | |
161a04f6 L |
14788 | USED_REX (REX_W); |
14789 | if (rex & REX_W) | |
52b15da3 | 14790 | op = get64 (); |
52b15da3 JH |
14791 | else |
14792 | { | |
f16cd0d5 L |
14793 | if (sizeflag & DFLAG) |
14794 | { | |
14795 | op = get32 (); | |
14796 | mask = 0xffffffff; | |
14797 | } | |
14798 | else | |
14799 | { | |
14800 | op = get16 (); | |
14801 | mask = 0xfffff; | |
14802 | } | |
14803 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14804 | } |
52b15da3 JH |
14805 | break; |
14806 | case w_mode: | |
14807 | mask = 0xfffff; | |
14808 | op = get16 (); | |
14809 | break; | |
14810 | default: | |
14811 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14812 | return; | |
14813 | } | |
14814 | ||
14815 | op &= mask; | |
14816 | scratchbuf[0] = '$'; | |
d708bcba | 14817 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14818 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14819 | scratchbuf[0] = '\0'; |
14820 | } | |
14821 | ||
14822 | static void | |
26ca5450 | 14823 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14824 | { |
52b15da3 | 14825 | bfd_signed_vma op; |
252b5132 RH |
14826 | |
14827 | switch (bytemode) | |
14828 | { | |
14829 | case b_mode: | |
e3949f17 | 14830 | case b_T_mode: |
252b5132 RH |
14831 | FETCH_DATA (the_info, codep + 1); |
14832 | op = *codep++; | |
14833 | if ((op & 0x80) != 0) | |
14834 | op -= 0x100; | |
e3949f17 L |
14835 | if (bytemode == b_T_mode) |
14836 | { | |
14837 | if (address_mode != mode_64bit | |
7bb15c6f | 14838 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14839 | { |
6c067bbb RM |
14840 | /* The operand-size prefix is overridden by a REX prefix. */ |
14841 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14842 | op &= 0xffffffff; |
14843 | else | |
14844 | op &= 0xffff; | |
14845 | } | |
14846 | } | |
14847 | else | |
14848 | { | |
14849 | if (!(rex & REX_W)) | |
14850 | { | |
14851 | if (sizeflag & DFLAG) | |
14852 | op &= 0xffffffff; | |
14853 | else | |
14854 | op &= 0xffff; | |
14855 | } | |
14856 | } | |
252b5132 RH |
14857 | break; |
14858 | case v_mode: | |
7bb15c6f RM |
14859 | /* The operand-size prefix is overridden by a REX prefix. */ |
14860 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14861 | op = get32s (); |
252b5132 | 14862 | else |
d9e3625e | 14863 | op = get16 (); |
252b5132 RH |
14864 | break; |
14865 | default: | |
14866 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14867 | return; | |
14868 | } | |
52b15da3 JH |
14869 | |
14870 | scratchbuf[0] = '$'; | |
14871 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14872 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14873 | } |
14874 | ||
14875 | static void | |
26ca5450 | 14876 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14877 | { |
52b15da3 | 14878 | bfd_vma disp; |
7081ff04 | 14879 | bfd_vma mask = -1; |
65ca155d | 14880 | bfd_vma segment = 0; |
252b5132 RH |
14881 | |
14882 | switch (bytemode) | |
14883 | { | |
14884 | case b_mode: | |
14885 | FETCH_DATA (the_info, codep + 1); | |
14886 | disp = *codep++; | |
14887 | if ((disp & 0x80) != 0) | |
14888 | disp -= 0x100; | |
14889 | break; | |
14890 | case v_mode: | |
5db04b09 L |
14891 | if (isa64 == amd64) |
14892 | USED_REX (REX_W); | |
14893 | if ((sizeflag & DFLAG) | |
14894 | || (address_mode == mode_64bit | |
14895 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 14896 | disp = get32s (); |
252b5132 RH |
14897 | else |
14898 | { | |
14899 | disp = get16 (); | |
206717e8 L |
14900 | if ((disp & 0x8000) != 0) |
14901 | disp -= 0x10000; | |
65ca155d L |
14902 | /* In 16bit mode, address is wrapped around at 64k within |
14903 | the same segment. Otherwise, a data16 prefix on a jump | |
14904 | instruction means that the pc is masked to 16 bits after | |
14905 | the displacement is added! */ | |
14906 | mask = 0xffff; | |
14907 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14908 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14909 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14910 | } |
5db04b09 L |
14911 | if (address_mode != mode_64bit |
14912 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 14913 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14914 | break; |
14915 | default: | |
14916 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14917 | return; | |
14918 | } | |
42d5f9c6 | 14919 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14920 | set_op (disp, 0); |
14921 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14922 | oappend (scratchbuf); |
14923 | } | |
14924 | ||
252b5132 | 14925 | static void |
ed7841b3 | 14926 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14927 | { |
ed7841b3 | 14928 | if (bytemode == w_mode) |
7967e09e | 14929 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14930 | else |
7967e09e | 14931 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14932 | } |
14933 | ||
14934 | static void | |
26ca5450 | 14935 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14936 | { |
14937 | int seg, offset; | |
14938 | ||
c608c12e | 14939 | if (sizeflag & DFLAG) |
252b5132 | 14940 | { |
c608c12e AM |
14941 | offset = get32 (); |
14942 | seg = get16 (); | |
252b5132 | 14943 | } |
c608c12e AM |
14944 | else |
14945 | { | |
14946 | offset = get16 (); | |
14947 | seg = get16 (); | |
14948 | } | |
7d421014 | 14949 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14950 | if (intel_syntax) |
3f31e633 | 14951 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14952 | else |
14953 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14954 | oappend (scratchbuf); |
252b5132 RH |
14955 | } |
14956 | ||
252b5132 | 14957 | static void |
3f31e633 | 14958 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14959 | { |
52b15da3 | 14960 | bfd_vma off; |
252b5132 | 14961 | |
3f31e633 JB |
14962 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14963 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14964 | append_seg (); |
14965 | ||
cb712a9e | 14966 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14967 | off = get32 (); |
14968 | else | |
14969 | off = get16 (); | |
14970 | ||
14971 | if (intel_syntax) | |
14972 | { | |
285ca992 | 14973 | if (!active_seg_prefix) |
252b5132 | 14974 | { |
d708bcba | 14975 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14976 | oappend (":"); |
14977 | } | |
14978 | } | |
52b15da3 JH |
14979 | print_operand_value (scratchbuf, 1, off); |
14980 | oappend (scratchbuf); | |
14981 | } | |
6439fc28 | 14982 | |
52b15da3 | 14983 | static void |
3f31e633 | 14984 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14985 | { |
14986 | bfd_vma off; | |
14987 | ||
539e75ad L |
14988 | if (address_mode != mode_64bit |
14989 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14990 | { |
14991 | OP_OFF (bytemode, sizeflag); | |
14992 | return; | |
14993 | } | |
14994 | ||
3f31e633 JB |
14995 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14996 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14997 | append_seg (); |
14998 | ||
6608db57 | 14999 | off = get64 (); |
52b15da3 JH |
15000 | |
15001 | if (intel_syntax) | |
15002 | { | |
285ca992 | 15003 | if (!active_seg_prefix) |
52b15da3 | 15004 | { |
d708bcba | 15005 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15006 | oappend (":"); |
15007 | } | |
15008 | } | |
15009 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15010 | oappend (scratchbuf); |
15011 | } | |
15012 | ||
15013 | static void | |
26ca5450 | 15014 | ptr_reg (int code, int sizeflag) |
252b5132 | 15015 | { |
2da11e11 | 15016 | const char *s; |
d708bcba | 15017 | |
1d9f512f | 15018 | *obufp++ = open_char; |
20f0a1fc | 15019 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15020 | if (address_mode == mode_64bit) |
c1a64871 JH |
15021 | { |
15022 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15023 | s = names32[code - eAX_reg]; |
c1a64871 | 15024 | else |
db6eb5be | 15025 | s = names64[code - eAX_reg]; |
c1a64871 | 15026 | } |
52b15da3 | 15027 | else if (sizeflag & AFLAG) |
252b5132 RH |
15028 | s = names32[code - eAX_reg]; |
15029 | else | |
15030 | s = names16[code - eAX_reg]; | |
15031 | oappend (s); | |
1d9f512f AM |
15032 | *obufp++ = close_char; |
15033 | *obufp = 0; | |
252b5132 RH |
15034 | } |
15035 | ||
15036 | static void | |
26ca5450 | 15037 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15038 | { |
9306ca4a | 15039 | if (intel_syntax) |
52fd6d94 JB |
15040 | { |
15041 | switch (codep[-1]) | |
15042 | { | |
15043 | case 0x6d: /* insw/insl */ | |
15044 | intel_operand_size (z_mode, sizeflag); | |
15045 | break; | |
15046 | case 0xa5: /* movsw/movsl/movsq */ | |
15047 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15048 | case 0xab: /* stosw/stosl */ | |
15049 | case 0xaf: /* scasw/scasl */ | |
15050 | intel_operand_size (v_mode, sizeflag); | |
15051 | break; | |
15052 | default: | |
15053 | intel_operand_size (b_mode, sizeflag); | |
15054 | } | |
15055 | } | |
9ce09ba2 | 15056 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15057 | ptr_reg (code, sizeflag); |
15058 | } | |
15059 | ||
15060 | static void | |
26ca5450 | 15061 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15062 | { |
9306ca4a | 15063 | if (intel_syntax) |
52fd6d94 JB |
15064 | { |
15065 | switch (codep[-1]) | |
15066 | { | |
15067 | case 0x6f: /* outsw/outsl */ | |
15068 | intel_operand_size (z_mode, sizeflag); | |
15069 | break; | |
15070 | case 0xa5: /* movsw/movsl/movsq */ | |
15071 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15072 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15073 | intel_operand_size (v_mode, sizeflag); | |
15074 | break; | |
15075 | default: | |
15076 | intel_operand_size (b_mode, sizeflag); | |
15077 | } | |
15078 | } | |
285ca992 L |
15079 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15080 | default segment register DS is printed. */ | |
15081 | if (!active_seg_prefix) | |
15082 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15083 | append_seg (); |
252b5132 RH |
15084 | ptr_reg (code, sizeflag); |
15085 | } | |
15086 | ||
252b5132 | 15087 | static void |
26ca5450 | 15088 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15089 | { |
9b60702d | 15090 | int add; |
161a04f6 | 15091 | if (rex & REX_R) |
c4a530c5 | 15092 | { |
161a04f6 | 15093 | USED_REX (REX_R); |
c4a530c5 JB |
15094 | add = 8; |
15095 | } | |
cb712a9e | 15096 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15097 | { |
f16cd0d5 | 15098 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15099 | used_prefixes |= PREFIX_LOCK; |
15100 | add = 8; | |
15101 | } | |
9b60702d L |
15102 | else |
15103 | add = 0; | |
7967e09e | 15104 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15105 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15106 | } |
15107 | ||
252b5132 | 15108 | static void |
26ca5450 | 15109 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15110 | { |
9b60702d | 15111 | int add; |
161a04f6 L |
15112 | USED_REX (REX_R); |
15113 | if (rex & REX_R) | |
52b15da3 | 15114 | add = 8; |
9b60702d L |
15115 | else |
15116 | add = 0; | |
d708bcba | 15117 | if (intel_syntax) |
7967e09e | 15118 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15119 | else |
7967e09e | 15120 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15121 | oappend (scratchbuf); |
15122 | } | |
15123 | ||
252b5132 | 15124 | static void |
26ca5450 | 15125 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15126 | { |
7967e09e | 15127 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15128 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15129 | } |
15130 | ||
15131 | static void | |
6f74c397 | 15132 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15133 | { |
68f34464 L |
15134 | /* Skip mod/rm byte. */ |
15135 | MODRM_CHECK; | |
15136 | codep++; | |
15137 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15138 | } |
15139 | ||
15140 | static void | |
26ca5450 | 15141 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15142 | { |
b9733481 L |
15143 | int reg = modrm.reg; |
15144 | const char **names; | |
15145 | ||
041bd2e0 JH |
15146 | used_prefixes |= (prefixes & PREFIX_DATA); |
15147 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15148 | { |
b9733481 | 15149 | names = names_xmm; |
161a04f6 L |
15150 | USED_REX (REX_R); |
15151 | if (rex & REX_R) | |
b9733481 | 15152 | reg += 8; |
20f0a1fc | 15153 | } |
041bd2e0 | 15154 | else |
b9733481 L |
15155 | names = names_mm; |
15156 | oappend (names[reg]); | |
252b5132 RH |
15157 | } |
15158 | ||
c608c12e | 15159 | static void |
c0f3af97 | 15160 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15161 | { |
b9733481 L |
15162 | int reg = modrm.reg; |
15163 | const char **names; | |
15164 | ||
161a04f6 L |
15165 | USED_REX (REX_R); |
15166 | if (rex & REX_R) | |
b9733481 | 15167 | reg += 8; |
43234a1e L |
15168 | if (vex.evex) |
15169 | { | |
15170 | if (!vex.r) | |
15171 | reg += 16; | |
15172 | } | |
15173 | ||
539f890d L |
15174 | if (need_vex |
15175 | && bytemode != xmm_mode | |
43234a1e L |
15176 | && bytemode != xmmq_mode |
15177 | && bytemode != evex_half_bcst_xmmq_mode | |
15178 | && bytemode != ymm_mode | |
539f890d | 15179 | && bytemode != scalar_mode) |
c0f3af97 L |
15180 | { |
15181 | switch (vex.length) | |
15182 | { | |
15183 | case 128: | |
b9733481 | 15184 | names = names_xmm; |
c0f3af97 L |
15185 | break; |
15186 | case 256: | |
5fc35d96 IT |
15187 | if (vex.w |
15188 | || (bytemode != vex_vsib_q_w_dq_mode | |
15189 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15190 | names = names_ymm; |
15191 | else | |
15192 | names = names_xmm; | |
c0f3af97 | 15193 | break; |
43234a1e L |
15194 | case 512: |
15195 | names = names_zmm; | |
15196 | break; | |
c0f3af97 L |
15197 | default: |
15198 | abort (); | |
15199 | } | |
15200 | } | |
43234a1e L |
15201 | else if (bytemode == xmmq_mode |
15202 | || bytemode == evex_half_bcst_xmmq_mode) | |
15203 | { | |
15204 | switch (vex.length) | |
15205 | { | |
15206 | case 128: | |
15207 | case 256: | |
15208 | names = names_xmm; | |
15209 | break; | |
15210 | case 512: | |
15211 | names = names_ymm; | |
15212 | break; | |
15213 | default: | |
15214 | abort (); | |
15215 | } | |
15216 | } | |
15217 | else if (bytemode == ymm_mode) | |
15218 | names = names_ymm; | |
c0f3af97 | 15219 | else |
b9733481 L |
15220 | names = names_xmm; |
15221 | oappend (names[reg]); | |
c608c12e AM |
15222 | } |
15223 | ||
252b5132 | 15224 | static void |
26ca5450 | 15225 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15226 | { |
b9733481 L |
15227 | int reg; |
15228 | const char **names; | |
15229 | ||
7967e09e | 15230 | if (modrm.mod != 3) |
252b5132 | 15231 | { |
b6169b20 L |
15232 | if (intel_syntax |
15233 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15234 | { |
15235 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15236 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15237 | } |
252b5132 RH |
15238 | OP_E (bytemode, sizeflag); |
15239 | return; | |
15240 | } | |
15241 | ||
b6169b20 L |
15242 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15243 | swap_operand (); | |
15244 | ||
6608db57 | 15245 | /* Skip mod/rm byte. */ |
4bba6815 | 15246 | MODRM_CHECK; |
252b5132 | 15247 | codep++; |
041bd2e0 | 15248 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15249 | reg = modrm.rm; |
041bd2e0 | 15250 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15251 | { |
b9733481 | 15252 | names = names_xmm; |
161a04f6 L |
15253 | USED_REX (REX_B); |
15254 | if (rex & REX_B) | |
b9733481 | 15255 | reg += 8; |
20f0a1fc | 15256 | } |
041bd2e0 | 15257 | else |
b9733481 L |
15258 | names = names_mm; |
15259 | oappend (names[reg]); | |
252b5132 RH |
15260 | } |
15261 | ||
246c51aa L |
15262 | /* cvt* are the only instructions in sse2 which have |
15263 | both SSE and MMX operands and also have 0x66 prefix | |
15264 | in their opcode. 0x66 was originally used to differentiate | |
15265 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15266 | cvt* separately using OP_EMC and OP_MXC */ |
15267 | static void | |
15268 | OP_EMC (int bytemode, int sizeflag) | |
15269 | { | |
7967e09e | 15270 | if (modrm.mod != 3) |
4d9567e0 MM |
15271 | { |
15272 | if (intel_syntax && bytemode == v_mode) | |
15273 | { | |
15274 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15275 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15276 | } |
4d9567e0 MM |
15277 | OP_E (bytemode, sizeflag); |
15278 | return; | |
15279 | } | |
246c51aa | 15280 | |
4d9567e0 MM |
15281 | /* Skip mod/rm byte. */ |
15282 | MODRM_CHECK; | |
15283 | codep++; | |
15284 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15285 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15286 | } |
15287 | ||
15288 | static void | |
15289 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15290 | { | |
15291 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15292 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15293 | } |
15294 | ||
c608c12e | 15295 | static void |
26ca5450 | 15296 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15297 | { |
b9733481 L |
15298 | int reg; |
15299 | const char **names; | |
d6f574e0 L |
15300 | |
15301 | /* Skip mod/rm byte. */ | |
15302 | MODRM_CHECK; | |
15303 | codep++; | |
15304 | ||
7967e09e | 15305 | if (modrm.mod != 3) |
c608c12e | 15306 | { |
c1e679ec | 15307 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15308 | return; |
15309 | } | |
d6f574e0 | 15310 | |
b9733481 | 15311 | reg = modrm.rm; |
161a04f6 L |
15312 | USED_REX (REX_B); |
15313 | if (rex & REX_B) | |
b9733481 | 15314 | reg += 8; |
43234a1e L |
15315 | if (vex.evex) |
15316 | { | |
15317 | USED_REX (REX_X); | |
15318 | if ((rex & REX_X)) | |
15319 | reg += 16; | |
15320 | } | |
c608c12e | 15321 | |
b6169b20 | 15322 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15323 | && (bytemode == x_swap_mode |
15324 | || bytemode == d_swap_mode | |
7bb15c6f | 15325 | || bytemode == d_scalar_swap_mode |
539f890d L |
15326 | || bytemode == q_swap_mode |
15327 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15328 | swap_operand (); |
15329 | ||
c0f3af97 L |
15330 | if (need_vex |
15331 | && bytemode != xmm_mode | |
6c30d220 L |
15332 | && bytemode != xmmdw_mode |
15333 | && bytemode != xmmqd_mode | |
15334 | && bytemode != xmm_mb_mode | |
15335 | && bytemode != xmm_mw_mode | |
15336 | && bytemode != xmm_md_mode | |
15337 | && bytemode != xmm_mq_mode | |
43234a1e | 15338 | && bytemode != xmm_mdq_mode |
539f890d | 15339 | && bytemode != xmmq_mode |
43234a1e L |
15340 | && bytemode != evex_half_bcst_xmmq_mode |
15341 | && bytemode != ymm_mode | |
539f890d | 15342 | && bytemode != d_scalar_mode |
7bb15c6f | 15343 | && bytemode != d_scalar_swap_mode |
539f890d | 15344 | && bytemode != q_scalar_mode |
1c480963 L |
15345 | && bytemode != q_scalar_swap_mode |
15346 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15347 | { |
15348 | switch (vex.length) | |
15349 | { | |
15350 | case 128: | |
b9733481 | 15351 | names = names_xmm; |
c0f3af97 L |
15352 | break; |
15353 | case 256: | |
b9733481 | 15354 | names = names_ymm; |
c0f3af97 | 15355 | break; |
43234a1e L |
15356 | case 512: |
15357 | names = names_zmm; | |
15358 | break; | |
c0f3af97 L |
15359 | default: |
15360 | abort (); | |
15361 | } | |
15362 | } | |
43234a1e L |
15363 | else if (bytemode == xmmq_mode |
15364 | || bytemode == evex_half_bcst_xmmq_mode) | |
15365 | { | |
15366 | switch (vex.length) | |
15367 | { | |
15368 | case 128: | |
15369 | case 256: | |
15370 | names = names_xmm; | |
15371 | break; | |
15372 | case 512: | |
15373 | names = names_ymm; | |
15374 | break; | |
15375 | default: | |
15376 | abort (); | |
15377 | } | |
15378 | } | |
15379 | else if (bytemode == ymm_mode) | |
15380 | names = names_ymm; | |
c0f3af97 | 15381 | else |
b9733481 L |
15382 | names = names_xmm; |
15383 | oappend (names[reg]); | |
c608c12e AM |
15384 | } |
15385 | ||
252b5132 | 15386 | static void |
26ca5450 | 15387 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15388 | { |
7967e09e | 15389 | if (modrm.mod == 3) |
2da11e11 AM |
15390 | OP_EM (bytemode, sizeflag); |
15391 | else | |
6608db57 | 15392 | BadOp (); |
252b5132 RH |
15393 | } |
15394 | ||
992aaec9 | 15395 | static void |
26ca5450 | 15396 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15397 | { |
7967e09e | 15398 | if (modrm.mod == 3) |
992aaec9 AM |
15399 | OP_EX (bytemode, sizeflag); |
15400 | else | |
6608db57 | 15401 | BadOp (); |
992aaec9 AM |
15402 | } |
15403 | ||
cc0ec051 AM |
15404 | static void |
15405 | OP_M (int bytemode, int sizeflag) | |
15406 | { | |
7967e09e | 15407 | if (modrm.mod == 3) |
75413a22 L |
15408 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15409 | BadOp (); | |
cc0ec051 AM |
15410 | else |
15411 | OP_E (bytemode, sizeflag); | |
15412 | } | |
15413 | ||
15414 | static void | |
15415 | OP_0f07 (int bytemode, int sizeflag) | |
15416 | { | |
7967e09e | 15417 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15418 | BadOp (); |
15419 | else | |
15420 | OP_E (bytemode, sizeflag); | |
15421 | } | |
15422 | ||
46e883c5 | 15423 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15424 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15425 | |
cc0ec051 | 15426 | static void |
46e883c5 | 15427 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15428 | { |
8b38ad71 L |
15429 | if ((prefixes & PREFIX_DATA) != 0 |
15430 | || (rex != 0 | |
15431 | && rex != 0x48 | |
15432 | && address_mode == mode_64bit)) | |
46e883c5 L |
15433 | OP_REG (bytemode, sizeflag); |
15434 | else | |
15435 | strcpy (obuf, "nop"); | |
15436 | } | |
15437 | ||
15438 | static void | |
15439 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15440 | { | |
8b38ad71 L |
15441 | if ((prefixes & PREFIX_DATA) != 0 |
15442 | || (rex != 0 | |
15443 | && rex != 0x48 | |
15444 | && address_mode == mode_64bit)) | |
46e883c5 | 15445 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15446 | } |
15447 | ||
84037f8c | 15448 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15449 | /* 00 */ NULL, NULL, NULL, NULL, |
15450 | /* 04 */ NULL, NULL, NULL, NULL, | |
15451 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15452 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15453 | /* 10 */ NULL, NULL, NULL, NULL, |
15454 | /* 14 */ NULL, NULL, NULL, NULL, | |
15455 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15456 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15457 | /* 20 */ NULL, NULL, NULL, NULL, |
15458 | /* 24 */ NULL, NULL, NULL, NULL, | |
15459 | /* 28 */ NULL, NULL, NULL, NULL, | |
15460 | /* 2C */ NULL, NULL, NULL, NULL, | |
15461 | /* 30 */ NULL, NULL, NULL, NULL, | |
15462 | /* 34 */ NULL, NULL, NULL, NULL, | |
15463 | /* 38 */ NULL, NULL, NULL, NULL, | |
15464 | /* 3C */ NULL, NULL, NULL, NULL, | |
15465 | /* 40 */ NULL, NULL, NULL, NULL, | |
15466 | /* 44 */ NULL, NULL, NULL, NULL, | |
15467 | /* 48 */ NULL, NULL, NULL, NULL, | |
15468 | /* 4C */ NULL, NULL, NULL, NULL, | |
15469 | /* 50 */ NULL, NULL, NULL, NULL, | |
15470 | /* 54 */ NULL, NULL, NULL, NULL, | |
15471 | /* 58 */ NULL, NULL, NULL, NULL, | |
15472 | /* 5C */ NULL, NULL, NULL, NULL, | |
15473 | /* 60 */ NULL, NULL, NULL, NULL, | |
15474 | /* 64 */ NULL, NULL, NULL, NULL, | |
15475 | /* 68 */ NULL, NULL, NULL, NULL, | |
15476 | /* 6C */ NULL, NULL, NULL, NULL, | |
15477 | /* 70 */ NULL, NULL, NULL, NULL, | |
15478 | /* 74 */ NULL, NULL, NULL, NULL, | |
15479 | /* 78 */ NULL, NULL, NULL, NULL, | |
15480 | /* 7C */ NULL, NULL, NULL, NULL, | |
15481 | /* 80 */ NULL, NULL, NULL, NULL, | |
15482 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15483 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15484 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15485 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15486 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15487 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15488 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15489 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15490 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15491 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15492 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15493 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15494 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15495 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15496 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15497 | /* C0 */ NULL, NULL, NULL, NULL, | |
15498 | /* C4 */ NULL, NULL, NULL, NULL, | |
15499 | /* C8 */ NULL, NULL, NULL, NULL, | |
15500 | /* CC */ NULL, NULL, NULL, NULL, | |
15501 | /* D0 */ NULL, NULL, NULL, NULL, | |
15502 | /* D4 */ NULL, NULL, NULL, NULL, | |
15503 | /* D8 */ NULL, NULL, NULL, NULL, | |
15504 | /* DC */ NULL, NULL, NULL, NULL, | |
15505 | /* E0 */ NULL, NULL, NULL, NULL, | |
15506 | /* E4 */ NULL, NULL, NULL, NULL, | |
15507 | /* E8 */ NULL, NULL, NULL, NULL, | |
15508 | /* EC */ NULL, NULL, NULL, NULL, | |
15509 | /* F0 */ NULL, NULL, NULL, NULL, | |
15510 | /* F4 */ NULL, NULL, NULL, NULL, | |
15511 | /* F8 */ NULL, NULL, NULL, NULL, | |
15512 | /* FC */ NULL, NULL, NULL, NULL, | |
15513 | }; | |
15514 | ||
15515 | static void | |
26ca5450 | 15516 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15517 | { |
15518 | const char *mnemonic; | |
15519 | ||
15520 | FETCH_DATA (the_info, codep + 1); | |
15521 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15522 | place where an 8-bit immediate would normally go. ie. the last | |
15523 | byte of the instruction. */ | |
ea397f5b | 15524 | obufp = mnemonicendp; |
c608c12e | 15525 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15526 | if (mnemonic) |
2da11e11 | 15527 | oappend (mnemonic); |
252b5132 RH |
15528 | else |
15529 | { | |
15530 | /* Since a variable sized modrm/sib chunk is between the start | |
15531 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15532 | all the modrm processing first, and don't know until now that | |
15533 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15534 | op_out[0][0] = '\0'; |
15535 | op_out[1][0] = '\0'; | |
6608db57 | 15536 | BadOp (); |
252b5132 | 15537 | } |
ea397f5b | 15538 | mnemonicendp = obufp; |
252b5132 | 15539 | } |
c608c12e | 15540 | |
ea397f5b L |
15541 | static struct op simd_cmp_op[] = |
15542 | { | |
15543 | { STRING_COMMA_LEN ("eq") }, | |
15544 | { STRING_COMMA_LEN ("lt") }, | |
15545 | { STRING_COMMA_LEN ("le") }, | |
15546 | { STRING_COMMA_LEN ("unord") }, | |
15547 | { STRING_COMMA_LEN ("neq") }, | |
15548 | { STRING_COMMA_LEN ("nlt") }, | |
15549 | { STRING_COMMA_LEN ("nle") }, | |
15550 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15551 | }; |
15552 | ||
15553 | static void | |
ad19981d | 15554 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15555 | { |
15556 | unsigned int cmp_type; | |
15557 | ||
15558 | FETCH_DATA (the_info, codep + 1); | |
15559 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15560 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15561 | { |
ad19981d | 15562 | char suffix [3]; |
ea397f5b | 15563 | char *p = mnemonicendp - 2; |
ad19981d L |
15564 | suffix[0] = p[0]; |
15565 | suffix[1] = p[1]; | |
15566 | suffix[2] = '\0'; | |
ea397f5b L |
15567 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15568 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15569 | } |
15570 | else | |
15571 | { | |
ad19981d L |
15572 | /* We have a reserved extension byte. Output it directly. */ |
15573 | scratchbuf[0] = '$'; | |
15574 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15575 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15576 | scratchbuf[0] = '\0'; |
c608c12e AM |
15577 | } |
15578 | } | |
15579 | ||
9916071f AP |
15580 | static void |
15581 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
15582 | int sizeflag ATTRIBUTE_UNUSED) | |
15583 | { | |
15584 | /* mwaitx %eax,%ecx,%ebx */ | |
15585 | if (!intel_syntax) | |
15586 | { | |
15587 | const char **names = (address_mode == mode_64bit | |
15588 | ? names64 : names32); | |
15589 | strcpy (op_out[0], names[0]); | |
15590 | strcpy (op_out[1], names[1]); | |
15591 | strcpy (op_out[2], names[3]); | |
15592 | two_source_ops = 1; | |
15593 | } | |
15594 | /* Skip mod/rm byte. */ | |
15595 | MODRM_CHECK; | |
15596 | codep++; | |
15597 | } | |
15598 | ||
ca164297 | 15599 | static void |
b844680a L |
15600 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15601 | int sizeflag ATTRIBUTE_UNUSED) | |
15602 | { | |
15603 | /* mwait %eax,%ecx */ | |
15604 | if (!intel_syntax) | |
15605 | { | |
15606 | const char **names = (address_mode == mode_64bit | |
15607 | ? names64 : names32); | |
15608 | strcpy (op_out[0], names[0]); | |
15609 | strcpy (op_out[1], names[1]); | |
15610 | two_source_ops = 1; | |
15611 | } | |
15612 | /* Skip mod/rm byte. */ | |
15613 | MODRM_CHECK; | |
15614 | codep++; | |
15615 | } | |
15616 | ||
15617 | static void | |
15618 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15619 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15620 | { |
b844680a L |
15621 | /* monitor %eax,%ecx,%edx" */ |
15622 | if (!intel_syntax) | |
ca164297 | 15623 | { |
b844680a | 15624 | const char **op1_names; |
cb712a9e L |
15625 | const char **names = (address_mode == mode_64bit |
15626 | ? names64 : names32); | |
1d9f512f | 15627 | |
b844680a L |
15628 | if (!(prefixes & PREFIX_ADDR)) |
15629 | op1_names = (address_mode == mode_16bit | |
15630 | ? names16 : names); | |
ca164297 L |
15631 | else |
15632 | { | |
b844680a | 15633 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15634 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
15635 | op1_names = (address_mode != mode_32bit |
15636 | ? names32 : names16); | |
15637 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 15638 | } |
b844680a L |
15639 | strcpy (op_out[0], op1_names[0]); |
15640 | strcpy (op_out[1], names[1]); | |
15641 | strcpy (op_out[2], names[2]); | |
15642 | two_source_ops = 1; | |
ca164297 | 15643 | } |
b844680a L |
15644 | /* Skip mod/rm byte. */ |
15645 | MODRM_CHECK; | |
15646 | codep++; | |
30123838 JB |
15647 | } |
15648 | ||
6608db57 KH |
15649 | static void |
15650 | BadOp (void) | |
2da11e11 | 15651 | { |
6608db57 KH |
15652 | /* Throw away prefixes and 1st. opcode byte. */ |
15653 | codep = insn_codep + 1; | |
2da11e11 AM |
15654 | oappend ("(bad)"); |
15655 | } | |
4cc91dba | 15656 | |
35c52694 L |
15657 | static void |
15658 | REP_Fixup (int bytemode, int sizeflag) | |
15659 | { | |
15660 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15661 | lods and stos. */ | |
35c52694 | 15662 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15663 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15664 | |
15665 | switch (bytemode) | |
15666 | { | |
15667 | case al_reg: | |
15668 | case eAX_reg: | |
15669 | case indir_dx_reg: | |
15670 | OP_IMREG (bytemode, sizeflag); | |
15671 | break; | |
15672 | case eDI_reg: | |
15673 | OP_ESreg (bytemode, sizeflag); | |
15674 | break; | |
15675 | case eSI_reg: | |
15676 | OP_DSreg (bytemode, sizeflag); | |
15677 | break; | |
15678 | default: | |
15679 | abort (); | |
15680 | break; | |
15681 | } | |
15682 | } | |
f5804c90 | 15683 | |
7e8b059b L |
15684 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15685 | "bnd". */ | |
15686 | ||
15687 | static void | |
15688 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15689 | { | |
15690 | if (prefixes & PREFIX_REPNZ) | |
15691 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15692 | } | |
15693 | ||
04ef582a L |
15694 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15695 | "notrack". */ | |
15696 | ||
15697 | static void | |
15698 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15699 | int sizeflag ATTRIBUTE_UNUSED) | |
15700 | { | |
9fef80d6 | 15701 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15702 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15703 | { | |
4e9ac44a | 15704 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15705 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15706 | active_seg_prefix = 0; |
15707 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15708 | } | |
15709 | } | |
15710 | ||
42164a71 L |
15711 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15712 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15713 | */ | |
15714 | ||
15715 | static void | |
15716 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15717 | { | |
15718 | if (modrm.mod != 3 | |
15719 | && (prefixes & PREFIX_LOCK) != 0) | |
15720 | { | |
15721 | if (prefixes & PREFIX_REPZ) | |
15722 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15723 | if (prefixes & PREFIX_REPNZ) | |
15724 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15725 | } | |
15726 | ||
15727 | OP_E (bytemode, sizeflag); | |
15728 | } | |
15729 | ||
15730 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15731 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15732 | */ | |
15733 | ||
15734 | static void | |
15735 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15736 | { | |
15737 | if (modrm.mod != 3) | |
15738 | { | |
15739 | if (prefixes & PREFIX_REPZ) | |
15740 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15741 | if (prefixes & PREFIX_REPNZ) | |
15742 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15743 | } | |
15744 | ||
15745 | OP_E (bytemode, sizeflag); | |
15746 | } | |
15747 | ||
15748 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15749 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15750 | ||
15751 | static void | |
15752 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15753 | { | |
15754 | if (modrm.mod != 3 | |
15755 | && last_repz_prefix > last_repnz_prefix | |
15756 | && (prefixes & PREFIX_REPZ) != 0) | |
15757 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15758 | ||
15759 | OP_E (bytemode, sizeflag); | |
15760 | } | |
15761 | ||
f5804c90 L |
15762 | static void |
15763 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15764 | { | |
161a04f6 L |
15765 | USED_REX (REX_W); |
15766 | if (rex & REX_W) | |
f5804c90 L |
15767 | { |
15768 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15769 | char *p = mnemonicendp - 2; |
15770 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15771 | bytemode = o_mode; |
f5804c90 | 15772 | } |
42164a71 L |
15773 | else if ((prefixes & PREFIX_LOCK) != 0) |
15774 | { | |
15775 | if (prefixes & PREFIX_REPZ) | |
15776 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15777 | if (prefixes & PREFIX_REPNZ) | |
15778 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15779 | } | |
15780 | ||
f5804c90 L |
15781 | OP_M (bytemode, sizeflag); |
15782 | } | |
42903f7f L |
15783 | |
15784 | static void | |
15785 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15786 | { | |
b9733481 L |
15787 | const char **names; |
15788 | ||
c0f3af97 L |
15789 | if (need_vex) |
15790 | { | |
15791 | switch (vex.length) | |
15792 | { | |
15793 | case 128: | |
b9733481 | 15794 | names = names_xmm; |
c0f3af97 L |
15795 | break; |
15796 | case 256: | |
b9733481 | 15797 | names = names_ymm; |
c0f3af97 L |
15798 | break; |
15799 | default: | |
15800 | abort (); | |
15801 | } | |
15802 | } | |
15803 | else | |
b9733481 L |
15804 | names = names_xmm; |
15805 | oappend (names[reg]); | |
42903f7f | 15806 | } |
381d071f L |
15807 | |
15808 | static void | |
15809 | CRC32_Fixup (int bytemode, int sizeflag) | |
15810 | { | |
15811 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15812 | char *p = mnemonicendp; |
381d071f L |
15813 | |
15814 | switch (bytemode) | |
15815 | { | |
15816 | case b_mode: | |
20592a94 | 15817 | if (intel_syntax) |
ea397f5b | 15818 | goto skip; |
20592a94 | 15819 | |
381d071f L |
15820 | *p++ = 'b'; |
15821 | break; | |
15822 | case v_mode: | |
20592a94 | 15823 | if (intel_syntax) |
ea397f5b | 15824 | goto skip; |
20592a94 | 15825 | |
381d071f L |
15826 | USED_REX (REX_W); |
15827 | if (rex & REX_W) | |
15828 | *p++ = 'q'; | |
7bb15c6f | 15829 | else |
f16cd0d5 L |
15830 | { |
15831 | if (sizeflag & DFLAG) | |
15832 | *p++ = 'l'; | |
15833 | else | |
15834 | *p++ = 'w'; | |
15835 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15836 | } | |
381d071f L |
15837 | break; |
15838 | default: | |
15839 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15840 | break; | |
15841 | } | |
ea397f5b | 15842 | mnemonicendp = p; |
381d071f L |
15843 | *p = '\0'; |
15844 | ||
ea397f5b | 15845 | skip: |
381d071f L |
15846 | if (modrm.mod == 3) |
15847 | { | |
15848 | int add; | |
15849 | ||
15850 | /* Skip mod/rm byte. */ | |
15851 | MODRM_CHECK; | |
15852 | codep++; | |
15853 | ||
15854 | USED_REX (REX_B); | |
15855 | add = (rex & REX_B) ? 8 : 0; | |
15856 | if (bytemode == b_mode) | |
15857 | { | |
15858 | USED_REX (0); | |
15859 | if (rex) | |
15860 | oappend (names8rex[modrm.rm + add]); | |
15861 | else | |
15862 | oappend (names8[modrm.rm + add]); | |
15863 | } | |
15864 | else | |
15865 | { | |
15866 | USED_REX (REX_W); | |
15867 | if (rex & REX_W) | |
15868 | oappend (names64[modrm.rm + add]); | |
15869 | else if ((prefixes & PREFIX_DATA)) | |
15870 | oappend (names16[modrm.rm + add]); | |
15871 | else | |
15872 | oappend (names32[modrm.rm + add]); | |
15873 | } | |
15874 | } | |
15875 | else | |
9344ff29 | 15876 | OP_E (bytemode, sizeflag); |
381d071f | 15877 | } |
85f10a01 | 15878 | |
eacc9c89 L |
15879 | static void |
15880 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15881 | { | |
15882 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15883 | USED_REX (REX_W); | |
15884 | if (rex & REX_W) | |
15885 | { | |
15886 | char *p = mnemonicendp; | |
15887 | *p++ = '6'; | |
15888 | *p++ = '4'; | |
15889 | *p = '\0'; | |
15890 | mnemonicendp = p; | |
15891 | } | |
15892 | OP_M (bytemode, sizeflag); | |
15893 | } | |
15894 | ||
15c7c1d8 JB |
15895 | static void |
15896 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15897 | { | |
15898 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15899 | if (!intel_syntax) | |
15900 | { | |
15901 | char *p = mnemonicendp; | |
15902 | ||
15903 | USED_REX (REX_W); | |
15904 | if (rex & REX_W) | |
15905 | *p++ = 'q'; | |
15906 | else if (sizeflag & SUFFIX_ALWAYS) | |
15907 | *p++ = 'l'; | |
15908 | ||
15909 | *p = '\0'; | |
15910 | mnemonicendp = p; | |
15911 | } | |
15912 | ||
15913 | OP_EX (bytemode, sizeflag); | |
15914 | } | |
15915 | ||
c0f3af97 L |
15916 | /* Display the destination register operand for instructions with |
15917 | VEX. */ | |
15918 | ||
15919 | static void | |
15920 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15921 | { | |
539f890d | 15922 | int reg; |
b9733481 L |
15923 | const char **names; |
15924 | ||
c0f3af97 L |
15925 | if (!need_vex) |
15926 | abort (); | |
15927 | ||
15928 | if (!need_vex_reg) | |
15929 | return; | |
15930 | ||
539f890d | 15931 | reg = vex.register_specifier; |
63c6fc6c | 15932 | vex.register_specifier = 0; |
5f847646 JB |
15933 | if (address_mode != mode_64bit) |
15934 | reg &= 7; | |
15935 | else if (vex.evex && !vex.v) | |
15936 | reg += 16; | |
43234a1e | 15937 | |
539f890d L |
15938 | if (bytemode == vex_scalar_mode) |
15939 | { | |
15940 | oappend (names_xmm[reg]); | |
15941 | return; | |
15942 | } | |
15943 | ||
c0f3af97 L |
15944 | switch (vex.length) |
15945 | { | |
15946 | case 128: | |
15947 | switch (bytemode) | |
15948 | { | |
15949 | case vex_mode: | |
15950 | case vex128_mode: | |
6c30d220 | 15951 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15952 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15953 | names = names_xmm; |
15954 | break; | |
15955 | case dq_mode: | |
390a6789 | 15956 | if (rex & REX_W) |
cb21baef L |
15957 | names = names64; |
15958 | else | |
15959 | names = names32; | |
c0f3af97 | 15960 | break; |
1ba585e8 | 15961 | case mask_bd_mode: |
43234a1e | 15962 | case mask_mode: |
9889cbb1 L |
15963 | if (reg > 0x7) |
15964 | { | |
15965 | oappend ("(bad)"); | |
15966 | return; | |
15967 | } | |
43234a1e L |
15968 | names = names_mask; |
15969 | break; | |
c0f3af97 L |
15970 | default: |
15971 | abort (); | |
15972 | return; | |
15973 | } | |
c0f3af97 L |
15974 | break; |
15975 | case 256: | |
15976 | switch (bytemode) | |
15977 | { | |
15978 | case vex_mode: | |
15979 | case vex256_mode: | |
6c30d220 L |
15980 | names = names_ymm; |
15981 | break; | |
15982 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15983 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15984 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15985 | break; |
1ba585e8 | 15986 | case mask_bd_mode: |
43234a1e | 15987 | case mask_mode: |
9889cbb1 L |
15988 | if (reg > 0x7) |
15989 | { | |
15990 | oappend ("(bad)"); | |
15991 | return; | |
15992 | } | |
43234a1e L |
15993 | names = names_mask; |
15994 | break; | |
c0f3af97 | 15995 | default: |
a37a2806 NC |
15996 | /* See PR binutils/20893 for a reproducer. */ |
15997 | oappend ("(bad)"); | |
c0f3af97 L |
15998 | return; |
15999 | } | |
c0f3af97 | 16000 | break; |
43234a1e L |
16001 | case 512: |
16002 | names = names_zmm; | |
16003 | break; | |
c0f3af97 L |
16004 | default: |
16005 | abort (); | |
16006 | break; | |
16007 | } | |
539f890d | 16008 | oappend (names[reg]); |
c0f3af97 L |
16009 | } |
16010 | ||
922d8de8 DR |
16011 | /* Get the VEX immediate byte without moving codep. */ |
16012 | ||
16013 | static unsigned char | |
ccc5981b | 16014 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16015 | { |
16016 | int bytes_before_imm = 0; | |
16017 | ||
922d8de8 DR |
16018 | if (modrm.mod != 3) |
16019 | { | |
16020 | /* There are SIB/displacement bytes. */ | |
16021 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16022 | { |
922d8de8 | 16023 | /* 32/64 bit address mode */ |
6c067bbb | 16024 | int base = modrm.rm; |
922d8de8 DR |
16025 | |
16026 | /* Check SIB byte. */ | |
6c067bbb RM |
16027 | if (base == 4) |
16028 | { | |
16029 | FETCH_DATA (the_info, codep + 1); | |
16030 | base = *codep & 7; | |
16031 | /* When decoding the third source, don't increase | |
16032 | bytes_before_imm as this has already been incremented | |
16033 | by one in OP_E_memory while decoding the second | |
16034 | source operand. */ | |
16035 | if (opnum == 0) | |
16036 | bytes_before_imm++; | |
16037 | } | |
16038 | ||
16039 | /* Don't increase bytes_before_imm when decoding the third source, | |
16040 | it has already been incremented by OP_E_memory while decoding | |
16041 | the second source operand. */ | |
16042 | if (opnum == 0) | |
16043 | { | |
16044 | switch (modrm.mod) | |
16045 | { | |
16046 | case 0: | |
16047 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16048 | SIB == 5, there is a 4 byte displacement. */ | |
16049 | if (base != 5) | |
16050 | /* No displacement. */ | |
16051 | break; | |
1a0670f3 | 16052 | /* Fall through. */ |
6c067bbb RM |
16053 | case 2: |
16054 | /* 4 byte displacement. */ | |
16055 | bytes_before_imm += 4; | |
16056 | break; | |
16057 | case 1: | |
16058 | /* 1 byte displacement. */ | |
16059 | bytes_before_imm++; | |
16060 | break; | |
16061 | } | |
16062 | } | |
16063 | } | |
922d8de8 | 16064 | else |
02e647f9 SP |
16065 | { |
16066 | /* 16 bit address mode */ | |
6c067bbb RM |
16067 | /* Don't increase bytes_before_imm when decoding the third source, |
16068 | it has already been incremented by OP_E_memory while decoding | |
16069 | the second source operand. */ | |
16070 | if (opnum == 0) | |
16071 | { | |
02e647f9 SP |
16072 | switch (modrm.mod) |
16073 | { | |
16074 | case 0: | |
16075 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16076 | if (modrm.rm != 6) | |
16077 | /* No displacement. */ | |
16078 | break; | |
1a0670f3 | 16079 | /* Fall through. */ |
02e647f9 SP |
16080 | case 2: |
16081 | /* 2 byte displacement. */ | |
16082 | bytes_before_imm += 2; | |
16083 | break; | |
16084 | case 1: | |
16085 | /* 1 byte displacement: when decoding the third source, | |
16086 | don't increase bytes_before_imm as this has already | |
16087 | been incremented by one in OP_E_memory while decoding | |
16088 | the second source operand. */ | |
16089 | if (opnum == 0) | |
16090 | bytes_before_imm++; | |
ccc5981b | 16091 | |
02e647f9 SP |
16092 | break; |
16093 | } | |
922d8de8 DR |
16094 | } |
16095 | } | |
16096 | } | |
16097 | ||
16098 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16099 | return codep [bytes_before_imm]; | |
16100 | } | |
16101 | ||
16102 | static void | |
16103 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16104 | { | |
b9733481 L |
16105 | const char **names; |
16106 | ||
922d8de8 DR |
16107 | if (reg == -1 && modrm.mod != 3) |
16108 | { | |
16109 | OP_E_memory (bytemode, sizeflag); | |
16110 | return; | |
16111 | } | |
16112 | else | |
16113 | { | |
16114 | if (reg == -1) | |
16115 | { | |
16116 | reg = modrm.rm; | |
16117 | USED_REX (REX_B); | |
16118 | if (rex & REX_B) | |
16119 | reg += 8; | |
16120 | } | |
5f847646 JB |
16121 | if (address_mode != mode_64bit) |
16122 | reg &= 7; | |
922d8de8 DR |
16123 | } |
16124 | ||
16125 | switch (vex.length) | |
16126 | { | |
16127 | case 128: | |
b9733481 | 16128 | names = names_xmm; |
922d8de8 DR |
16129 | break; |
16130 | case 256: | |
b9733481 | 16131 | names = names_ymm; |
922d8de8 DR |
16132 | break; |
16133 | default: | |
16134 | abort (); | |
16135 | } | |
b9733481 | 16136 | oappend (names[reg]); |
922d8de8 DR |
16137 | } |
16138 | ||
a683cc34 SP |
16139 | static void |
16140 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16141 | { | |
16142 | int reg = -1; | |
16143 | static unsigned char vex_imm8; | |
16144 | ||
16145 | if (vex_w_done == 0) | |
16146 | { | |
16147 | vex_w_done = 1; | |
16148 | ||
16149 | /* Skip mod/rm byte. */ | |
16150 | MODRM_CHECK; | |
16151 | codep++; | |
16152 | ||
16153 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16154 | ||
16155 | if (vex.w) | |
16156 | reg = vex_imm8 >> 4; | |
16157 | ||
16158 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16159 | } | |
16160 | else if (vex_w_done == 1) | |
16161 | { | |
16162 | vex_w_done = 2; | |
16163 | ||
16164 | if (!vex.w) | |
16165 | reg = vex_imm8 >> 4; | |
16166 | ||
16167 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16168 | } | |
16169 | else | |
16170 | { | |
16171 | /* Output the imm8 directly. */ | |
16172 | scratchbuf[0] = '$'; | |
16173 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16174 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16175 | scratchbuf[0] = '\0'; |
16176 | codep++; | |
16177 | } | |
16178 | } | |
16179 | ||
5dd85c99 SP |
16180 | static void |
16181 | OP_Vex_2src (int bytemode, int sizeflag) | |
16182 | { | |
16183 | if (modrm.mod == 3) | |
16184 | { | |
b9733481 | 16185 | int reg = modrm.rm; |
5dd85c99 | 16186 | USED_REX (REX_B); |
b9733481 L |
16187 | if (rex & REX_B) |
16188 | reg += 8; | |
16189 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16190 | } |
16191 | else | |
16192 | { | |
16193 | if (intel_syntax | |
16194 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16195 | { | |
16196 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16197 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16198 | } | |
16199 | OP_E (bytemode, sizeflag); | |
16200 | } | |
16201 | } | |
16202 | ||
16203 | static void | |
16204 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16205 | { | |
16206 | if (modrm.mod == 3) | |
16207 | { | |
16208 | /* Skip mod/rm byte. */ | |
16209 | MODRM_CHECK; | |
16210 | codep++; | |
16211 | } | |
16212 | ||
16213 | if (vex.w) | |
5f847646 JB |
16214 | { |
16215 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16216 | vex.register_specifier = 0; |
5f847646 JB |
16217 | |
16218 | if (address_mode != mode_64bit) | |
16219 | reg &= 7; | |
16220 | oappend (names_xmm[reg]); | |
16221 | } | |
5dd85c99 SP |
16222 | else |
16223 | OP_Vex_2src (bytemode, sizeflag); | |
16224 | } | |
16225 | ||
16226 | static void | |
16227 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16228 | { | |
16229 | if (vex.w) | |
16230 | OP_Vex_2src (bytemode, sizeflag); | |
16231 | else | |
5f847646 JB |
16232 | { |
16233 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16234 | vex.register_specifier = 0; |
5f847646 JB |
16235 | |
16236 | if (address_mode != mode_64bit) | |
16237 | reg &= 7; | |
16238 | oappend (names_xmm[reg]); | |
16239 | } | |
5dd85c99 SP |
16240 | } |
16241 | ||
922d8de8 DR |
16242 | static void |
16243 | OP_EX_VexW (int bytemode, int sizeflag) | |
16244 | { | |
16245 | int reg = -1; | |
16246 | ||
16247 | if (!vex_w_done) | |
16248 | { | |
41effecb SP |
16249 | /* Skip mod/rm byte. */ |
16250 | MODRM_CHECK; | |
16251 | codep++; | |
16252 | ||
922d8de8 | 16253 | if (vex.w) |
ccc5981b | 16254 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16255 | } |
16256 | else | |
16257 | { | |
16258 | if (!vex.w) | |
ccc5981b | 16259 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16260 | } |
16261 | ||
16262 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16263 | |
3a2430e0 JB |
16264 | if (vex_w_done) |
16265 | codep++; | |
16266 | vex_w_done = 1; | |
922d8de8 DR |
16267 | } |
16268 | ||
c0f3af97 L |
16269 | static void |
16270 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16271 | { | |
16272 | int reg; | |
b9733481 L |
16273 | const char **names; |
16274 | ||
c0f3af97 L |
16275 | FETCH_DATA (the_info, codep + 1); |
16276 | reg = *codep++; | |
16277 | ||
16278 | if (bytemode != x_mode) | |
16279 | abort (); | |
16280 | ||
c0f3af97 | 16281 | reg >>= 4; |
5f847646 JB |
16282 | if (address_mode != mode_64bit) |
16283 | reg &= 7; | |
dae39acc | 16284 | |
c0f3af97 L |
16285 | switch (vex.length) |
16286 | { | |
16287 | case 128: | |
b9733481 | 16288 | names = names_xmm; |
c0f3af97 L |
16289 | break; |
16290 | case 256: | |
b9733481 | 16291 | names = names_ymm; |
c0f3af97 L |
16292 | break; |
16293 | default: | |
16294 | abort (); | |
16295 | } | |
b9733481 | 16296 | oappend (names[reg]); |
c0f3af97 L |
16297 | } |
16298 | ||
922d8de8 DR |
16299 | static void |
16300 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16301 | { | |
16302 | /* Turn off the REX.W bit since it is used for swapping operands | |
16303 | now. */ | |
16304 | rex &= ~REX_W; | |
16305 | OP_XMM (bytemode, sizeflag); | |
16306 | } | |
16307 | ||
c0f3af97 L |
16308 | static void |
16309 | OP_EX_Vex (int bytemode, int sizeflag) | |
16310 | { | |
16311 | if (modrm.mod != 3) | |
63c6fc6c | 16312 | need_vex_reg = 0; |
c0f3af97 L |
16313 | OP_EX (bytemode, sizeflag); |
16314 | } | |
16315 | ||
16316 | static void | |
16317 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16318 | { | |
16319 | if (modrm.mod != 3) | |
63c6fc6c | 16320 | need_vex_reg = 0; |
c0f3af97 L |
16321 | OP_XMM (bytemode, sizeflag); |
16322 | } | |
16323 | ||
ea397f5b L |
16324 | static struct op vex_cmp_op[] = |
16325 | { | |
16326 | { STRING_COMMA_LEN ("eq") }, | |
16327 | { STRING_COMMA_LEN ("lt") }, | |
16328 | { STRING_COMMA_LEN ("le") }, | |
16329 | { STRING_COMMA_LEN ("unord") }, | |
16330 | { STRING_COMMA_LEN ("neq") }, | |
16331 | { STRING_COMMA_LEN ("nlt") }, | |
16332 | { STRING_COMMA_LEN ("nle") }, | |
16333 | { STRING_COMMA_LEN ("ord") }, | |
16334 | { STRING_COMMA_LEN ("eq_uq") }, | |
16335 | { STRING_COMMA_LEN ("nge") }, | |
16336 | { STRING_COMMA_LEN ("ngt") }, | |
16337 | { STRING_COMMA_LEN ("false") }, | |
16338 | { STRING_COMMA_LEN ("neq_oq") }, | |
16339 | { STRING_COMMA_LEN ("ge") }, | |
16340 | { STRING_COMMA_LEN ("gt") }, | |
16341 | { STRING_COMMA_LEN ("true") }, | |
16342 | { STRING_COMMA_LEN ("eq_os") }, | |
16343 | { STRING_COMMA_LEN ("lt_oq") }, | |
16344 | { STRING_COMMA_LEN ("le_oq") }, | |
16345 | { STRING_COMMA_LEN ("unord_s") }, | |
16346 | { STRING_COMMA_LEN ("neq_us") }, | |
16347 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16348 | { STRING_COMMA_LEN ("nle_uq") }, | |
16349 | { STRING_COMMA_LEN ("ord_s") }, | |
16350 | { STRING_COMMA_LEN ("eq_us") }, | |
16351 | { STRING_COMMA_LEN ("nge_uq") }, | |
16352 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16353 | { STRING_COMMA_LEN ("false_os") }, | |
16354 | { STRING_COMMA_LEN ("neq_os") }, | |
16355 | { STRING_COMMA_LEN ("ge_oq") }, | |
16356 | { STRING_COMMA_LEN ("gt_oq") }, | |
16357 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16358 | }; |
16359 | ||
16360 | static void | |
16361 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16362 | { | |
16363 | unsigned int cmp_type; | |
16364 | ||
16365 | FETCH_DATA (the_info, codep + 1); | |
16366 | cmp_type = *codep++ & 0xff; | |
16367 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16368 | { | |
16369 | char suffix [3]; | |
ea397f5b | 16370 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16371 | suffix[0] = p[0]; |
16372 | suffix[1] = p[1]; | |
16373 | suffix[2] = '\0'; | |
ea397f5b L |
16374 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16375 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16376 | } |
16377 | else | |
16378 | { | |
16379 | /* We have a reserved extension byte. Output it directly. */ | |
16380 | scratchbuf[0] = '$'; | |
16381 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16382 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16383 | scratchbuf[0] = '\0'; |
16384 | } | |
16385 | } | |
16386 | ||
43234a1e L |
16387 | static void |
16388 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16389 | int sizeflag ATTRIBUTE_UNUSED) | |
16390 | { | |
16391 | unsigned int cmp_type; | |
16392 | ||
16393 | if (!vex.evex) | |
16394 | abort (); | |
16395 | ||
16396 | FETCH_DATA (the_info, codep + 1); | |
16397 | cmp_type = *codep++ & 0xff; | |
16398 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16399 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16400 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16401 | && cmp_type != 3 | |
16402 | && cmp_type != 7) | |
16403 | { | |
16404 | char suffix [3]; | |
16405 | char *p = mnemonicendp - 2; | |
16406 | ||
16407 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16408 | if (p[0] == 'p') | |
16409 | { | |
16410 | p++; | |
16411 | suffix[0] = p[0]; | |
16412 | suffix[1] = '\0'; | |
16413 | } | |
16414 | else | |
16415 | { | |
16416 | suffix[0] = p[0]; | |
16417 | suffix[1] = p[1]; | |
16418 | suffix[2] = '\0'; | |
16419 | } | |
16420 | ||
16421 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16422 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16423 | } | |
be92cb14 JB |
16424 | else |
16425 | { | |
16426 | /* We have a reserved extension byte. Output it directly. */ | |
16427 | scratchbuf[0] = '$'; | |
16428 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16429 | oappend_maybe_intel (scratchbuf); | |
16430 | scratchbuf[0] = '\0'; | |
16431 | } | |
16432 | } | |
16433 | ||
16434 | static const struct op xop_cmp_op[] = | |
16435 | { | |
16436 | { STRING_COMMA_LEN ("lt") }, | |
16437 | { STRING_COMMA_LEN ("le") }, | |
16438 | { STRING_COMMA_LEN ("gt") }, | |
16439 | { STRING_COMMA_LEN ("ge") }, | |
16440 | { STRING_COMMA_LEN ("eq") }, | |
16441 | { STRING_COMMA_LEN ("neq") }, | |
16442 | { STRING_COMMA_LEN ("false") }, | |
16443 | { STRING_COMMA_LEN ("true") } | |
16444 | }; | |
16445 | ||
16446 | static void | |
16447 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16448 | int sizeflag ATTRIBUTE_UNUSED) | |
16449 | { | |
16450 | unsigned int cmp_type; | |
16451 | ||
16452 | FETCH_DATA (the_info, codep + 1); | |
16453 | cmp_type = *codep++ & 0xff; | |
16454 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16455 | { | |
16456 | char suffix[3]; | |
16457 | char *p = mnemonicendp - 2; | |
16458 | ||
16459 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16460 | if (p[0] == 'm') | |
16461 | { | |
16462 | p++; | |
16463 | suffix[0] = p[0]; | |
16464 | suffix[1] = '\0'; | |
16465 | } | |
16466 | else | |
16467 | { | |
16468 | suffix[0] = p[0]; | |
16469 | suffix[1] = p[1]; | |
16470 | suffix[2] = '\0'; | |
16471 | } | |
16472 | ||
16473 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16474 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16475 | } | |
43234a1e L |
16476 | else |
16477 | { | |
16478 | /* We have a reserved extension byte. Output it directly. */ | |
16479 | scratchbuf[0] = '$'; | |
16480 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16481 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16482 | scratchbuf[0] = '\0'; |
16483 | } | |
16484 | } | |
16485 | ||
ea397f5b L |
16486 | static const struct op pclmul_op[] = |
16487 | { | |
16488 | { STRING_COMMA_LEN ("lql") }, | |
16489 | { STRING_COMMA_LEN ("hql") }, | |
16490 | { STRING_COMMA_LEN ("lqh") }, | |
16491 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16492 | }; |
16493 | ||
16494 | static void | |
16495 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16496 | int sizeflag ATTRIBUTE_UNUSED) | |
16497 | { | |
16498 | unsigned int pclmul_type; | |
16499 | ||
16500 | FETCH_DATA (the_info, codep + 1); | |
16501 | pclmul_type = *codep++ & 0xff; | |
16502 | switch (pclmul_type) | |
16503 | { | |
16504 | case 0x10: | |
16505 | pclmul_type = 2; | |
16506 | break; | |
16507 | case 0x11: | |
16508 | pclmul_type = 3; | |
16509 | break; | |
16510 | default: | |
16511 | break; | |
7bb15c6f | 16512 | } |
c0f3af97 L |
16513 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16514 | { | |
16515 | char suffix [4]; | |
ea397f5b | 16516 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16517 | suffix[0] = p[0]; |
16518 | suffix[1] = p[1]; | |
16519 | suffix[2] = p[2]; | |
16520 | suffix[3] = '\0'; | |
ea397f5b L |
16521 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16522 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16523 | } |
16524 | else | |
16525 | { | |
16526 | /* We have a reserved extension byte. Output it directly. */ | |
16527 | scratchbuf[0] = '$'; | |
16528 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16529 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16530 | scratchbuf[0] = '\0'; |
16531 | } | |
16532 | } | |
16533 | ||
f1f8f695 L |
16534 | static void |
16535 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16536 | { | |
16537 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16538 | char *p = mnemonicendp; |
f1f8f695 L |
16539 | |
16540 | switch (bytemode) | |
16541 | { | |
16542 | case v_mode: | |
16543 | if (intel_syntax) | |
ea397f5b | 16544 | goto skip; |
f1f8f695 L |
16545 | |
16546 | USED_REX (REX_W); | |
16547 | if (sizeflag & SUFFIX_ALWAYS) | |
16548 | { | |
16549 | if (rex & REX_W) | |
16550 | *p++ = 'q'; | |
f1f8f695 | 16551 | else |
f16cd0d5 L |
16552 | { |
16553 | if (sizeflag & DFLAG) | |
16554 | *p++ = 'l'; | |
16555 | else | |
16556 | *p++ = 'w'; | |
16557 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16558 | } | |
f1f8f695 | 16559 | } |
f1f8f695 L |
16560 | break; |
16561 | default: | |
16562 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16563 | break; | |
16564 | } | |
ea397f5b | 16565 | mnemonicendp = p; |
f1f8f695 L |
16566 | *p = '\0'; |
16567 | ||
ea397f5b | 16568 | skip: |
f1f8f695 L |
16569 | OP_M (bytemode, sizeflag); |
16570 | } | |
f88c9eb0 SP |
16571 | |
16572 | static void | |
16573 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16574 | { | |
16575 | int reg; | |
16576 | const char **names; | |
16577 | ||
16578 | /* Skip mod/rm byte. */ | |
16579 | MODRM_CHECK; | |
16580 | codep++; | |
16581 | ||
390a6789 | 16582 | if (rex & REX_W) |
f88c9eb0 | 16583 | names = names64; |
f88c9eb0 | 16584 | else |
ce7d077e | 16585 | names = names32; |
f88c9eb0 SP |
16586 | |
16587 | reg = modrm.rm; | |
16588 | USED_REX (REX_B); | |
16589 | if (rex & REX_B) | |
16590 | reg += 8; | |
16591 | ||
16592 | oappend (names[reg]); | |
16593 | } | |
16594 | ||
16595 | static void | |
16596 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16597 | { | |
16598 | const char **names; | |
5f847646 | 16599 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16600 | vex.register_specifier = 0; |
f88c9eb0 | 16601 | |
390a6789 | 16602 | if (rex & REX_W) |
f88c9eb0 | 16603 | names = names64; |
f88c9eb0 | 16604 | else |
ce7d077e | 16605 | names = names32; |
f88c9eb0 | 16606 | |
5f847646 JB |
16607 | if (address_mode != mode_64bit) |
16608 | reg &= 7; | |
16609 | oappend (names[reg]); | |
f88c9eb0 | 16610 | } |
43234a1e L |
16611 | |
16612 | static void | |
16613 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16614 | { | |
16615 | if (!vex.evex | |
1ba585e8 | 16616 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16617 | abort (); |
16618 | ||
16619 | USED_REX (REX_R); | |
16620 | if ((rex & REX_R) != 0 || !vex.r) | |
16621 | { | |
16622 | BadOp (); | |
16623 | return; | |
16624 | } | |
16625 | ||
16626 | oappend (names_mask [modrm.reg]); | |
16627 | } | |
16628 | ||
16629 | static void | |
16630 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16631 | { | |
16632 | if (!vex.evex | |
16633 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16634 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16635 | && bytemode != evex_sae_mode)) |
16636 | abort (); | |
16637 | if (modrm.mod == 3 && vex.b) | |
16638 | switch (bytemode) | |
16639 | { | |
70df6fc9 L |
16640 | case evex_rounding_64_mode: |
16641 | if (address_mode != mode_64bit) | |
16642 | { | |
16643 | oappend ("(bad)"); | |
16644 | break; | |
16645 | } | |
16646 | /* Fall through. */ | |
43234a1e L |
16647 | case evex_rounding_mode: |
16648 | oappend (names_rounding[vex.ll]); | |
16649 | break; | |
16650 | case evex_sae_mode: | |
16651 | oappend ("{sae}"); | |
16652 | break; | |
16653 | default: | |
16654 | break; | |
16655 | } | |
16656 | } |