Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
6f2750fe | 2 | Copyright (C) 1988-2016 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
120 | static void OP_LWPCB_E (int, int); |
121 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
122 | static void OP_Vex_2src_1 (int, int); |
123 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 124 | |
f1f8f695 | 125 | static void MOVBE_Fixup (int, int); |
252b5132 | 126 | |
43234a1e L |
127 | static void OP_Mask (int, int); |
128 | ||
6608db57 | 129 | struct dis_private { |
252b5132 RH |
130 | /* Points to first byte not fetched. */ |
131 | bfd_byte *max_fetched; | |
0b1cf022 | 132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 133 | bfd_vma insn_start; |
e396998b | 134 | int orig_sizeflag; |
8df14d78 | 135 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
136 | }; |
137 | ||
cb712a9e L |
138 | enum address_mode |
139 | { | |
140 | mode_16bit, | |
141 | mode_32bit, | |
142 | mode_64bit | |
143 | }; | |
144 | ||
145 | enum address_mode address_mode; | |
52b15da3 | 146 | |
5076851f ILT |
147 | /* Flags for the prefixes for the current instruction. See below. */ |
148 | static int prefixes; | |
149 | ||
52b15da3 JH |
150 | /* REX prefix the current instruction. See below. */ |
151 | static int rex; | |
152 | /* Bits of REX we've already used. */ | |
153 | static int rex_used; | |
d869730d | 154 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 155 | static int rex_ignored; |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 249 | #define Ev { OP_E, v_mode } |
7e8b059b | 250 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 251 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
252 | #define Ed { OP_E, d_mode } |
253 | #define Edq { OP_E, dq_mode } | |
254 | #define Edqw { OP_E, dqw_mode } | |
1ba585e8 | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
42903f7f | 256 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
257 | #define Edb { OP_E, db_mode } |
258 | #define Edw { OP_E, dw_mode } | |
42903f7f | 259 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 260 | #define Eq { OP_E, q_mode } |
07f5af7d | 261 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
262 | #define indirEp { OP_indirE, f_mode } |
263 | #define stackEv { OP_E, stack_v_mode } | |
264 | #define Em { OP_E, m_mode } | |
265 | #define Ew { OP_E, w_mode } | |
266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 267 | #define Ma { OP_M, a_mode } |
b844680a | 268 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 269 | #define Md { OP_M, d_mode } |
f1f8f695 | 270 | #define Mo { OP_M, o_mode } |
ce518a5f L |
271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
272 | #define Mq { OP_M, q_mode } | |
4ee52178 | 273 | #define Mx { OP_M, x_mode } |
c0f3af97 | 274 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 275 | #define Gb { OP_G, b_mode } |
7e8b059b | 276 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
277 | #define Gv { OP_G, v_mode } |
278 | #define Gd { OP_G, d_mode } | |
279 | #define Gdq { OP_G, dq_mode } | |
280 | #define Gm { OP_G, m_mode } | |
281 | #define Gw { OP_G, w_mode } | |
6f74c397 | 282 | #define Rd { OP_R, d_mode } |
43234a1e | 283 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 284 | #define Rm { OP_R, m_mode } |
ce518a5f L |
285 | #define Ib { OP_I, b_mode } |
286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 288 | #define Iv { OP_I, v_mode } |
7bb15c6f | 289 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
290 | #define Iq { OP_I, q_mode } |
291 | #define Iv64 { OP_I64, v_mode } | |
292 | #define Iw { OP_I, w_mode } | |
293 | #define I1 { OP_I, const_1_mode } | |
294 | #define Jb { OP_J, b_mode } | |
295 | #define Jv { OP_J, v_mode } | |
296 | #define Cm { OP_C, m_mode } | |
297 | #define Dm { OP_D, m_mode } | |
298 | #define Td { OP_T, d_mode } | |
b844680a | 299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
300 | |
301 | #define RMeAX { OP_REG, eAX_reg } | |
302 | #define RMeBX { OP_REG, eBX_reg } | |
303 | #define RMeCX { OP_REG, eCX_reg } | |
304 | #define RMeDX { OP_REG, eDX_reg } | |
305 | #define RMeSP { OP_REG, eSP_reg } | |
306 | #define RMeBP { OP_REG, eBP_reg } | |
307 | #define RMeSI { OP_REG, eSI_reg } | |
308 | #define RMeDI { OP_REG, eDI_reg } | |
309 | #define RMrAX { OP_REG, rAX_reg } | |
310 | #define RMrBX { OP_REG, rBX_reg } | |
311 | #define RMrCX { OP_REG, rCX_reg } | |
312 | #define RMrDX { OP_REG, rDX_reg } | |
313 | #define RMrSP { OP_REG, rSP_reg } | |
314 | #define RMrBP { OP_REG, rBP_reg } | |
315 | #define RMrSI { OP_REG, rSI_reg } | |
316 | #define RMrDI { OP_REG, rDI_reg } | |
317 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
318 | #define RMCL { OP_REG, cl_reg } |
319 | #define RMDL { OP_REG, dl_reg } | |
320 | #define RMBL { OP_REG, bl_reg } | |
321 | #define RMAH { OP_REG, ah_reg } | |
322 | #define RMCH { OP_REG, ch_reg } | |
323 | #define RMDH { OP_REG, dh_reg } | |
324 | #define RMBH { OP_REG, bh_reg } | |
325 | #define RMAX { OP_REG, ax_reg } | |
326 | #define RMDX { OP_REG, dx_reg } | |
327 | ||
328 | #define eAX { OP_IMREG, eAX_reg } | |
329 | #define eBX { OP_IMREG, eBX_reg } | |
330 | #define eCX { OP_IMREG, eCX_reg } | |
331 | #define eDX { OP_IMREG, eDX_reg } | |
332 | #define eSP { OP_IMREG, eSP_reg } | |
333 | #define eBP { OP_IMREG, eBP_reg } | |
334 | #define eSI { OP_IMREG, eSI_reg } | |
335 | #define eDI { OP_IMREG, eDI_reg } | |
336 | #define AL { OP_IMREG, al_reg } | |
337 | #define CL { OP_IMREG, cl_reg } | |
338 | #define DL { OP_IMREG, dl_reg } | |
339 | #define BL { OP_IMREG, bl_reg } | |
340 | #define AH { OP_IMREG, ah_reg } | |
341 | #define CH { OP_IMREG, ch_reg } | |
342 | #define DH { OP_IMREG, dh_reg } | |
343 | #define BH { OP_IMREG, bh_reg } | |
344 | #define AX { OP_IMREG, ax_reg } | |
345 | #define DX { OP_IMREG, dx_reg } | |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
347 | #define indirDX { OP_IMREG, indir_dx_reg } | |
348 | ||
349 | #define Sw { OP_SEG, w_mode } | |
350 | #define Sv { OP_SEG, v_mode } | |
351 | #define Ap { OP_DIR, 0 } | |
352 | #define Ob { OP_OFF64, b_mode } | |
353 | #define Ov { OP_OFF64, v_mode } | |
354 | #define Xb { OP_DSreg, eSI_reg } | |
355 | #define Xv { OP_DSreg, eSI_reg } | |
356 | #define Xz { OP_DSreg, eSI_reg } | |
357 | #define Yb { OP_ESreg, eDI_reg } | |
358 | #define Yv { OP_ESreg, eDI_reg } | |
359 | #define DSBX { OP_DSreg, eBX_reg } | |
360 | ||
361 | #define es { OP_REG, es_reg } | |
362 | #define ss { OP_REG, ss_reg } | |
363 | #define cs { OP_REG, cs_reg } | |
364 | #define ds { OP_REG, ds_reg } | |
365 | #define fs { OP_REG, fs_reg } | |
366 | #define gs { OP_REG, gs_reg } | |
367 | ||
368 | #define MX { OP_MMX, 0 } | |
369 | #define XM { OP_XMM, 0 } | |
539f890d | 370 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 372 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 373 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 374 | #define EM { OP_EM, v_mode } |
b6169b20 | 375 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 376 | #define EMd { OP_EM, d_mode } |
14051056 | 377 | #define EMx { OP_EM, x_mode } |
8976381e | 378 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 379 | #define EXd { OP_EX, d_mode } |
539f890d | 380 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 381 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 383 | #define EXq { OP_EX, q_mode } |
539f890d L |
384 | #define EXqScalar { OP_EX, q_scalar_mode } |
385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 386 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 387 | #define EXx { OP_EX, x_mode } |
b6169b20 | 388 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 389 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 390 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 391 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
399 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 400 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
405 | #define MS { OP_MS, v_mode } |
406 | #define XS { OP_XS, v_mode } | |
09335d05 | 407 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 408 | #define MXC { OP_MXC, 0 } |
ce518a5f | 409 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 410 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 411 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 415 | |
c0f3af97 | 416 | #define Vex { OP_VEX, vex_mode } |
539f890d | 417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
419 | #define Vex128 { OP_VEX, vex128_mode } |
420 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 421 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 422 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 423 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 426 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
429 | #define EXVexW { OP_EX_VexW, x_mode } |
430 | #define EXdVexW { OP_EX_VexW, d_mode } | |
431 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 433 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 435 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
437 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
438 | #define VZERO { VZERO_Fixup, 0 } | |
439 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
440 | #define VPCMP { VPCMP_Fixup, 0 } |
441 | ||
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
444 | ||
445 | #define XMask { OP_Mask, mask_mode } | |
446 | #define MaskG { OP_G, mask_mode } | |
447 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
449 | #define MaskR { OP_R, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 451 | |
6c30d220 | 452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 456 | |
35c52694 | 457 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
458 | #define Xbr { REP_Fixup, eSI_reg } |
459 | #define Xvr { REP_Fixup, eSI_reg } | |
460 | #define Ybr { REP_Fixup, eDI_reg } | |
461 | #define Yvr { REP_Fixup, eDI_reg } | |
462 | #define Yzr { REP_Fixup, eDI_reg } | |
463 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
464 | #define ALr { REP_Fixup, al_reg } | |
465 | #define eAXr { REP_Fixup, eAX_reg } | |
466 | ||
42164a71 L |
467 | /* Used handle HLE prefix for lockable instructions. */ |
468 | #define Ebh1 { HLE_Fixup1, b_mode } | |
469 | #define Evh1 { HLE_Fixup1, v_mode } | |
470 | #define Ebh2 { HLE_Fixup2, b_mode } | |
471 | #define Evh2 { HLE_Fixup2, v_mode } | |
472 | #define Ebh3 { HLE_Fixup3, b_mode } | |
473 | #define Evh3 { HLE_Fixup3, v_mode } | |
474 | ||
7e8b059b L |
475 | #define BND { BND_Fixup, 0 } |
476 | ||
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e L |
535 | /* XMM register or double/quad word memory operand, depending on |
536 | VEX.W. */ | |
537 | xmm_mdq_mode, | |
538 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 539 | xmmdw_mode, |
43234a1e | 540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 541 | xmmqd_mode, |
43234a1e L |
542 | /* 32-byte YMM operand */ |
543 | ymm_mode, | |
544 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 545 | ymmq_mode, |
6c30d220 L |
546 | /* 32-byte YMM or 16-byte word operand */ |
547 | ymmxmm_mode, | |
51e7da1b | 548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 549 | m_mode, |
51e7da1b | 550 | /* pair of v_mode operands */ |
3873ba12 L |
551 | a_mode, |
552 | cond_jump_mode, | |
553 | loop_jcxz_mode, | |
7e8b059b | 554 | v_bnd_mode, |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
51e7da1b | 557 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 558 | dqw_mode, |
1ba585e8 | 559 | dqw_swap_mode, |
7e8b059b | 560 | bnd_mode, |
51e7da1b | 561 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
562 | f_mode, |
563 | const_1_mode, | |
07f5af7d L |
564 | /* v_mode for indirect branch opcodes. */ |
565 | indir_v_mode, | |
51e7da1b | 566 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 567 | stack_v_mode, |
51e7da1b | 568 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 569 | z_mode, |
51e7da1b | 570 | /* 16-byte operand */ |
3873ba12 | 571 | o_mode, |
51e7da1b | 572 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 573 | dqb_mode, |
1ba585e8 IT |
574 | /* registers like d_mode, memory like b_mode. */ |
575 | db_mode, | |
576 | /* registers like d_mode, memory like w_mode. */ | |
577 | dw_mode, | |
51e7da1b | 578 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 579 | dqd_mode, |
51e7da1b | 580 | /* normal vex mode */ |
3873ba12 | 581 | vex_mode, |
51e7da1b | 582 | /* 128bit vex mode */ |
3873ba12 | 583 | vex128_mode, |
51e7da1b | 584 | /* 256bit vex mode */ |
3873ba12 | 585 | vex256_mode, |
51e7da1b | 586 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 587 | vex_w_dq_mode, |
d55ee72f | 588 | |
6c30d220 L |
589 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
590 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
591 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
592 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
593 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
594 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
595 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
596 | vex_vsib_q_w_d_mode, | |
6c30d220 | 597 | |
539f890d L |
598 | /* scalar, ignore vector length. */ |
599 | scalar_mode, | |
600 | /* like d_mode, ignore vector length. */ | |
601 | d_scalar_mode, | |
602 | /* like d_swap_mode, ignore vector length. */ | |
603 | d_scalar_swap_mode, | |
604 | /* like q_mode, ignore vector length. */ | |
605 | q_scalar_mode, | |
606 | /* like q_swap_mode, ignore vector length. */ | |
607 | q_scalar_swap_mode, | |
608 | /* like vex_mode, ignore vector length. */ | |
609 | vex_scalar_mode, | |
1c480963 L |
610 | /* like vex_w_dq_mode, ignore vector length. */ |
611 | vex_scalar_w_dq_mode, | |
539f890d | 612 | |
43234a1e L |
613 | /* Static rounding. */ |
614 | evex_rounding_mode, | |
615 | /* Supress all exceptions. */ | |
616 | evex_sae_mode, | |
617 | ||
618 | /* Mask register operand. */ | |
619 | mask_mode, | |
1ba585e8 IT |
620 | /* Mask register operand. */ |
621 | mask_bd_mode, | |
43234a1e | 622 | |
3873ba12 L |
623 | es_reg, |
624 | cs_reg, | |
625 | ss_reg, | |
626 | ds_reg, | |
627 | fs_reg, | |
628 | gs_reg, | |
d55ee72f | 629 | |
3873ba12 L |
630 | eAX_reg, |
631 | eCX_reg, | |
632 | eDX_reg, | |
633 | eBX_reg, | |
634 | eSP_reg, | |
635 | eBP_reg, | |
636 | eSI_reg, | |
637 | eDI_reg, | |
d55ee72f | 638 | |
3873ba12 L |
639 | al_reg, |
640 | cl_reg, | |
641 | dl_reg, | |
642 | bl_reg, | |
643 | ah_reg, | |
644 | ch_reg, | |
645 | dh_reg, | |
646 | bh_reg, | |
d55ee72f | 647 | |
3873ba12 L |
648 | ax_reg, |
649 | cx_reg, | |
650 | dx_reg, | |
651 | bx_reg, | |
652 | sp_reg, | |
653 | bp_reg, | |
654 | si_reg, | |
655 | di_reg, | |
d55ee72f | 656 | |
3873ba12 L |
657 | rAX_reg, |
658 | rCX_reg, | |
659 | rDX_reg, | |
660 | rBX_reg, | |
661 | rSP_reg, | |
662 | rBP_reg, | |
663 | rSI_reg, | |
664 | rDI_reg, | |
d55ee72f | 665 | |
3873ba12 L |
666 | z_mode_ax_reg, |
667 | indir_dx_reg | |
51e7da1b | 668 | }; |
252b5132 | 669 | |
51e7da1b L |
670 | enum |
671 | { | |
672 | FLOATCODE = 1, | |
3873ba12 L |
673 | USE_REG_TABLE, |
674 | USE_MOD_TABLE, | |
675 | USE_RM_TABLE, | |
676 | USE_PREFIX_TABLE, | |
677 | USE_X86_64_TABLE, | |
678 | USE_3BYTE_TABLE, | |
f88c9eb0 | 679 | USE_XOP_8F_TABLE, |
3873ba12 L |
680 | USE_VEX_C4_TABLE, |
681 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 682 | USE_VEX_LEN_TABLE, |
43234a1e L |
683 | USE_VEX_W_TABLE, |
684 | USE_EVEX_TABLE | |
51e7da1b | 685 | }; |
6439fc28 | 686 | |
bf890a93 | 687 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 688 | |
bf890a93 IT |
689 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
690 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
691 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
692 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
693 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
694 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
695 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
696 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 697 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 698 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
699 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
700 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
701 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 702 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 703 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 704 | |
51e7da1b L |
705 | enum |
706 | { | |
707 | REG_80 = 0, | |
3873ba12 L |
708 | REG_81, |
709 | REG_82, | |
710 | REG_8F, | |
711 | REG_C0, | |
712 | REG_C1, | |
713 | REG_C6, | |
714 | REG_C7, | |
715 | REG_D0, | |
716 | REG_D1, | |
717 | REG_D2, | |
718 | REG_D3, | |
719 | REG_F6, | |
720 | REG_F7, | |
721 | REG_FE, | |
722 | REG_FF, | |
723 | REG_0F00, | |
724 | REG_0F01, | |
725 | REG_0F0D, | |
726 | REG_0F18, | |
727 | REG_0F71, | |
728 | REG_0F72, | |
729 | REG_0F73, | |
730 | REG_0FA6, | |
731 | REG_0FA7, | |
732 | REG_0FAE, | |
733 | REG_0FBA, | |
734 | REG_0FC7, | |
592a252b L |
735 | REG_VEX_0F71, |
736 | REG_VEX_0F72, | |
737 | REG_VEX_0F73, | |
738 | REG_VEX_0FAE, | |
f12dc422 | 739 | REG_VEX_0F38F3, |
f88c9eb0 | 740 | REG_XOP_LWPCB, |
2a2a0f38 QN |
741 | REG_XOP_LWP, |
742 | REG_XOP_TBM_01, | |
43234a1e L |
743 | REG_XOP_TBM_02, |
744 | ||
1ba585e8 | 745 | REG_EVEX_0F71, |
43234a1e L |
746 | REG_EVEX_0F72, |
747 | REG_EVEX_0F73, | |
748 | REG_EVEX_0F38C6, | |
749 | REG_EVEX_0F38C7 | |
51e7da1b | 750 | }; |
1ceb70f8 | 751 | |
51e7da1b L |
752 | enum |
753 | { | |
754 | MOD_8D = 0, | |
42164a71 L |
755 | MOD_C6_REG_7, |
756 | MOD_C7_REG_7, | |
4a357820 MZ |
757 | MOD_FF_REG_3, |
758 | MOD_FF_REG_5, | |
3873ba12 L |
759 | MOD_0F01_REG_0, |
760 | MOD_0F01_REG_1, | |
761 | MOD_0F01_REG_2, | |
762 | MOD_0F01_REG_3, | |
8eab4136 | 763 | MOD_0F01_REG_5, |
3873ba12 L |
764 | MOD_0F01_REG_7, |
765 | MOD_0F12_PREFIX_0, | |
766 | MOD_0F13, | |
767 | MOD_0F16_PREFIX_0, | |
768 | MOD_0F17, | |
769 | MOD_0F18_REG_0, | |
770 | MOD_0F18_REG_1, | |
771 | MOD_0F18_REG_2, | |
772 | MOD_0F18_REG_3, | |
d7189fa5 RM |
773 | MOD_0F18_REG_4, |
774 | MOD_0F18_REG_5, | |
775 | MOD_0F18_REG_6, | |
776 | MOD_0F18_REG_7, | |
7e8b059b L |
777 | MOD_0F1A_PREFIX_0, |
778 | MOD_0F1B_PREFIX_0, | |
779 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
780 | MOD_0F24, |
781 | MOD_0F26, | |
782 | MOD_0F2B_PREFIX_0, | |
783 | MOD_0F2B_PREFIX_1, | |
784 | MOD_0F2B_PREFIX_2, | |
785 | MOD_0F2B_PREFIX_3, | |
786 | MOD_0F51, | |
787 | MOD_0F71_REG_2, | |
788 | MOD_0F71_REG_4, | |
789 | MOD_0F71_REG_6, | |
790 | MOD_0F72_REG_2, | |
791 | MOD_0F72_REG_4, | |
792 | MOD_0F72_REG_6, | |
793 | MOD_0F73_REG_2, | |
794 | MOD_0F73_REG_3, | |
795 | MOD_0F73_REG_6, | |
796 | MOD_0F73_REG_7, | |
797 | MOD_0FAE_REG_0, | |
798 | MOD_0FAE_REG_1, | |
799 | MOD_0FAE_REG_2, | |
800 | MOD_0FAE_REG_3, | |
801 | MOD_0FAE_REG_4, | |
802 | MOD_0FAE_REG_5, | |
803 | MOD_0FAE_REG_6, | |
804 | MOD_0FAE_REG_7, | |
805 | MOD_0FB2, | |
806 | MOD_0FB4, | |
807 | MOD_0FB5, | |
a8484f96 | 808 | MOD_0FC3, |
963f3586 IT |
809 | MOD_0FC7_REG_3, |
810 | MOD_0FC7_REG_4, | |
811 | MOD_0FC7_REG_5, | |
3873ba12 L |
812 | MOD_0FC7_REG_6, |
813 | MOD_0FC7_REG_7, | |
814 | MOD_0FD7, | |
815 | MOD_0FE7_PREFIX_2, | |
816 | MOD_0FF0_PREFIX_3, | |
817 | MOD_0F382A_PREFIX_2, | |
818 | MOD_62_32BIT, | |
819 | MOD_C4_32BIT, | |
820 | MOD_C5_32BIT, | |
592a252b L |
821 | MOD_VEX_0F12_PREFIX_0, |
822 | MOD_VEX_0F13, | |
823 | MOD_VEX_0F16_PREFIX_0, | |
824 | MOD_VEX_0F17, | |
825 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
826 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
827 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
828 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
829 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
830 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
831 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
832 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
833 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
834 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
835 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
836 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
837 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
838 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
839 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
840 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
841 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
842 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
843 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
844 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
845 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
846 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
847 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
848 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
849 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
850 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
851 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
852 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
853 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
854 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
855 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
856 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
857 | MOD_VEX_0F50, |
858 | MOD_VEX_0F71_REG_2, | |
859 | MOD_VEX_0F71_REG_4, | |
860 | MOD_VEX_0F71_REG_6, | |
861 | MOD_VEX_0F72_REG_2, | |
862 | MOD_VEX_0F72_REG_4, | |
863 | MOD_VEX_0F72_REG_6, | |
864 | MOD_VEX_0F73_REG_2, | |
865 | MOD_VEX_0F73_REG_3, | |
866 | MOD_VEX_0F73_REG_6, | |
867 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
868 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
869 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
870 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
871 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
872 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
873 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
874 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
875 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
876 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
877 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
878 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
879 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
880 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
881 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
882 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
883 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
884 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
885 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
886 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
887 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
888 | MOD_VEX_0FAE_REG_2, |
889 | MOD_VEX_0FAE_REG_3, | |
890 | MOD_VEX_0FD7_PREFIX_2, | |
891 | MOD_VEX_0FE7_PREFIX_2, | |
892 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
893 | MOD_VEX_0F381A_PREFIX_2, |
894 | MOD_VEX_0F382A_PREFIX_2, | |
895 | MOD_VEX_0F382C_PREFIX_2, | |
896 | MOD_VEX_0F382D_PREFIX_2, | |
897 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
898 | MOD_VEX_0F382F_PREFIX_2, |
899 | MOD_VEX_0F385A_PREFIX_2, | |
900 | MOD_VEX_0F388C_PREFIX_2, | |
901 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
902 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
903 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
904 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
905 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
906 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
907 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
908 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
909 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
910 | |
911 | MOD_EVEX_0F10_PREFIX_1, | |
912 | MOD_EVEX_0F10_PREFIX_3, | |
913 | MOD_EVEX_0F11_PREFIX_1, | |
914 | MOD_EVEX_0F11_PREFIX_3, | |
915 | MOD_EVEX_0F12_PREFIX_0, | |
916 | MOD_EVEX_0F16_PREFIX_0, | |
917 | MOD_EVEX_0F38C6_REG_1, | |
918 | MOD_EVEX_0F38C6_REG_2, | |
919 | MOD_EVEX_0F38C6_REG_5, | |
920 | MOD_EVEX_0F38C6_REG_6, | |
921 | MOD_EVEX_0F38C7_REG_1, | |
922 | MOD_EVEX_0F38C7_REG_2, | |
923 | MOD_EVEX_0F38C7_REG_5, | |
924 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 925 | }; |
1ceb70f8 | 926 | |
51e7da1b L |
927 | enum |
928 | { | |
42164a71 L |
929 | RM_C6_REG_7 = 0, |
930 | RM_C7_REG_7, | |
931 | RM_0F01_REG_0, | |
3873ba12 L |
932 | RM_0F01_REG_1, |
933 | RM_0F01_REG_2, | |
934 | RM_0F01_REG_3, | |
8eab4136 | 935 | RM_0F01_REG_5, |
3873ba12 L |
936 | RM_0F01_REG_7, |
937 | RM_0FAE_REG_5, | |
938 | RM_0FAE_REG_6, | |
939 | RM_0FAE_REG_7 | |
51e7da1b | 940 | }; |
1ceb70f8 | 941 | |
51e7da1b L |
942 | enum |
943 | { | |
944 | PREFIX_90 = 0, | |
3873ba12 L |
945 | PREFIX_0F10, |
946 | PREFIX_0F11, | |
947 | PREFIX_0F12, | |
948 | PREFIX_0F16, | |
7e8b059b L |
949 | PREFIX_0F1A, |
950 | PREFIX_0F1B, | |
3873ba12 L |
951 | PREFIX_0F2A, |
952 | PREFIX_0F2B, | |
953 | PREFIX_0F2C, | |
954 | PREFIX_0F2D, | |
955 | PREFIX_0F2E, | |
956 | PREFIX_0F2F, | |
957 | PREFIX_0F51, | |
958 | PREFIX_0F52, | |
959 | PREFIX_0F53, | |
960 | PREFIX_0F58, | |
961 | PREFIX_0F59, | |
962 | PREFIX_0F5A, | |
963 | PREFIX_0F5B, | |
964 | PREFIX_0F5C, | |
965 | PREFIX_0F5D, | |
966 | PREFIX_0F5E, | |
967 | PREFIX_0F5F, | |
968 | PREFIX_0F60, | |
969 | PREFIX_0F61, | |
970 | PREFIX_0F62, | |
971 | PREFIX_0F6C, | |
972 | PREFIX_0F6D, | |
973 | PREFIX_0F6F, | |
974 | PREFIX_0F70, | |
975 | PREFIX_0F73_REG_3, | |
976 | PREFIX_0F73_REG_7, | |
977 | PREFIX_0F78, | |
978 | PREFIX_0F79, | |
979 | PREFIX_0F7C, | |
980 | PREFIX_0F7D, | |
981 | PREFIX_0F7E, | |
982 | PREFIX_0F7F, | |
c7b8aa3a L |
983 | PREFIX_0FAE_REG_0, |
984 | PREFIX_0FAE_REG_1, | |
985 | PREFIX_0FAE_REG_2, | |
986 | PREFIX_0FAE_REG_3, | |
c5e7287a | 987 | PREFIX_0FAE_REG_6, |
963f3586 | 988 | PREFIX_0FAE_REG_7, |
9d8596f0 | 989 | PREFIX_RM_0_0FAE_REG_7, |
3873ba12 | 990 | PREFIX_0FB8, |
f12dc422 | 991 | PREFIX_0FBC, |
3873ba12 L |
992 | PREFIX_0FBD, |
993 | PREFIX_0FC2, | |
a8484f96 | 994 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
995 | PREFIX_MOD_0_0FC7_REG_6, |
996 | PREFIX_MOD_3_0FC7_REG_6, | |
997 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
998 | PREFIX_0FD0, |
999 | PREFIX_0FD6, | |
1000 | PREFIX_0FE6, | |
1001 | PREFIX_0FE7, | |
1002 | PREFIX_0FF0, | |
1003 | PREFIX_0FF7, | |
1004 | PREFIX_0F3810, | |
1005 | PREFIX_0F3814, | |
1006 | PREFIX_0F3815, | |
1007 | PREFIX_0F3817, | |
1008 | PREFIX_0F3820, | |
1009 | PREFIX_0F3821, | |
1010 | PREFIX_0F3822, | |
1011 | PREFIX_0F3823, | |
1012 | PREFIX_0F3824, | |
1013 | PREFIX_0F3825, | |
1014 | PREFIX_0F3828, | |
1015 | PREFIX_0F3829, | |
1016 | PREFIX_0F382A, | |
1017 | PREFIX_0F382B, | |
1018 | PREFIX_0F3830, | |
1019 | PREFIX_0F3831, | |
1020 | PREFIX_0F3832, | |
1021 | PREFIX_0F3833, | |
1022 | PREFIX_0F3834, | |
1023 | PREFIX_0F3835, | |
1024 | PREFIX_0F3837, | |
1025 | PREFIX_0F3838, | |
1026 | PREFIX_0F3839, | |
1027 | PREFIX_0F383A, | |
1028 | PREFIX_0F383B, | |
1029 | PREFIX_0F383C, | |
1030 | PREFIX_0F383D, | |
1031 | PREFIX_0F383E, | |
1032 | PREFIX_0F383F, | |
1033 | PREFIX_0F3840, | |
1034 | PREFIX_0F3841, | |
1035 | PREFIX_0F3880, | |
1036 | PREFIX_0F3881, | |
6c30d220 | 1037 | PREFIX_0F3882, |
a0046408 L |
1038 | PREFIX_0F38C8, |
1039 | PREFIX_0F38C9, | |
1040 | PREFIX_0F38CA, | |
1041 | PREFIX_0F38CB, | |
1042 | PREFIX_0F38CC, | |
1043 | PREFIX_0F38CD, | |
3873ba12 L |
1044 | PREFIX_0F38DB, |
1045 | PREFIX_0F38DC, | |
1046 | PREFIX_0F38DD, | |
1047 | PREFIX_0F38DE, | |
1048 | PREFIX_0F38DF, | |
1049 | PREFIX_0F38F0, | |
1050 | PREFIX_0F38F1, | |
e2e1fcde | 1051 | PREFIX_0F38F6, |
3873ba12 L |
1052 | PREFIX_0F3A08, |
1053 | PREFIX_0F3A09, | |
1054 | PREFIX_0F3A0A, | |
1055 | PREFIX_0F3A0B, | |
1056 | PREFIX_0F3A0C, | |
1057 | PREFIX_0F3A0D, | |
1058 | PREFIX_0F3A0E, | |
1059 | PREFIX_0F3A14, | |
1060 | PREFIX_0F3A15, | |
1061 | PREFIX_0F3A16, | |
1062 | PREFIX_0F3A17, | |
1063 | PREFIX_0F3A20, | |
1064 | PREFIX_0F3A21, | |
1065 | PREFIX_0F3A22, | |
1066 | PREFIX_0F3A40, | |
1067 | PREFIX_0F3A41, | |
1068 | PREFIX_0F3A42, | |
1069 | PREFIX_0F3A44, | |
1070 | PREFIX_0F3A60, | |
1071 | PREFIX_0F3A61, | |
1072 | PREFIX_0F3A62, | |
1073 | PREFIX_0F3A63, | |
a0046408 | 1074 | PREFIX_0F3ACC, |
3873ba12 | 1075 | PREFIX_0F3ADF, |
592a252b L |
1076 | PREFIX_VEX_0F10, |
1077 | PREFIX_VEX_0F11, | |
1078 | PREFIX_VEX_0F12, | |
1079 | PREFIX_VEX_0F16, | |
1080 | PREFIX_VEX_0F2A, | |
1081 | PREFIX_VEX_0F2C, | |
1082 | PREFIX_VEX_0F2D, | |
1083 | PREFIX_VEX_0F2E, | |
1084 | PREFIX_VEX_0F2F, | |
43234a1e L |
1085 | PREFIX_VEX_0F41, |
1086 | PREFIX_VEX_0F42, | |
1087 | PREFIX_VEX_0F44, | |
1088 | PREFIX_VEX_0F45, | |
1089 | PREFIX_VEX_0F46, | |
1090 | PREFIX_VEX_0F47, | |
1ba585e8 | 1091 | PREFIX_VEX_0F4A, |
43234a1e | 1092 | PREFIX_VEX_0F4B, |
592a252b L |
1093 | PREFIX_VEX_0F51, |
1094 | PREFIX_VEX_0F52, | |
1095 | PREFIX_VEX_0F53, | |
1096 | PREFIX_VEX_0F58, | |
1097 | PREFIX_VEX_0F59, | |
1098 | PREFIX_VEX_0F5A, | |
1099 | PREFIX_VEX_0F5B, | |
1100 | PREFIX_VEX_0F5C, | |
1101 | PREFIX_VEX_0F5D, | |
1102 | PREFIX_VEX_0F5E, | |
1103 | PREFIX_VEX_0F5F, | |
1104 | PREFIX_VEX_0F60, | |
1105 | PREFIX_VEX_0F61, | |
1106 | PREFIX_VEX_0F62, | |
1107 | PREFIX_VEX_0F63, | |
1108 | PREFIX_VEX_0F64, | |
1109 | PREFIX_VEX_0F65, | |
1110 | PREFIX_VEX_0F66, | |
1111 | PREFIX_VEX_0F67, | |
1112 | PREFIX_VEX_0F68, | |
1113 | PREFIX_VEX_0F69, | |
1114 | PREFIX_VEX_0F6A, | |
1115 | PREFIX_VEX_0F6B, | |
1116 | PREFIX_VEX_0F6C, | |
1117 | PREFIX_VEX_0F6D, | |
1118 | PREFIX_VEX_0F6E, | |
1119 | PREFIX_VEX_0F6F, | |
1120 | PREFIX_VEX_0F70, | |
1121 | PREFIX_VEX_0F71_REG_2, | |
1122 | PREFIX_VEX_0F71_REG_4, | |
1123 | PREFIX_VEX_0F71_REG_6, | |
1124 | PREFIX_VEX_0F72_REG_2, | |
1125 | PREFIX_VEX_0F72_REG_4, | |
1126 | PREFIX_VEX_0F72_REG_6, | |
1127 | PREFIX_VEX_0F73_REG_2, | |
1128 | PREFIX_VEX_0F73_REG_3, | |
1129 | PREFIX_VEX_0F73_REG_6, | |
1130 | PREFIX_VEX_0F73_REG_7, | |
1131 | PREFIX_VEX_0F74, | |
1132 | PREFIX_VEX_0F75, | |
1133 | PREFIX_VEX_0F76, | |
1134 | PREFIX_VEX_0F77, | |
1135 | PREFIX_VEX_0F7C, | |
1136 | PREFIX_VEX_0F7D, | |
1137 | PREFIX_VEX_0F7E, | |
1138 | PREFIX_VEX_0F7F, | |
43234a1e L |
1139 | PREFIX_VEX_0F90, |
1140 | PREFIX_VEX_0F91, | |
1141 | PREFIX_VEX_0F92, | |
1142 | PREFIX_VEX_0F93, | |
1143 | PREFIX_VEX_0F98, | |
1ba585e8 | 1144 | PREFIX_VEX_0F99, |
592a252b L |
1145 | PREFIX_VEX_0FC2, |
1146 | PREFIX_VEX_0FC4, | |
1147 | PREFIX_VEX_0FC5, | |
1148 | PREFIX_VEX_0FD0, | |
1149 | PREFIX_VEX_0FD1, | |
1150 | PREFIX_VEX_0FD2, | |
1151 | PREFIX_VEX_0FD3, | |
1152 | PREFIX_VEX_0FD4, | |
1153 | PREFIX_VEX_0FD5, | |
1154 | PREFIX_VEX_0FD6, | |
1155 | PREFIX_VEX_0FD7, | |
1156 | PREFIX_VEX_0FD8, | |
1157 | PREFIX_VEX_0FD9, | |
1158 | PREFIX_VEX_0FDA, | |
1159 | PREFIX_VEX_0FDB, | |
1160 | PREFIX_VEX_0FDC, | |
1161 | PREFIX_VEX_0FDD, | |
1162 | PREFIX_VEX_0FDE, | |
1163 | PREFIX_VEX_0FDF, | |
1164 | PREFIX_VEX_0FE0, | |
1165 | PREFIX_VEX_0FE1, | |
1166 | PREFIX_VEX_0FE2, | |
1167 | PREFIX_VEX_0FE3, | |
1168 | PREFIX_VEX_0FE4, | |
1169 | PREFIX_VEX_0FE5, | |
1170 | PREFIX_VEX_0FE6, | |
1171 | PREFIX_VEX_0FE7, | |
1172 | PREFIX_VEX_0FE8, | |
1173 | PREFIX_VEX_0FE9, | |
1174 | PREFIX_VEX_0FEA, | |
1175 | PREFIX_VEX_0FEB, | |
1176 | PREFIX_VEX_0FEC, | |
1177 | PREFIX_VEX_0FED, | |
1178 | PREFIX_VEX_0FEE, | |
1179 | PREFIX_VEX_0FEF, | |
1180 | PREFIX_VEX_0FF0, | |
1181 | PREFIX_VEX_0FF1, | |
1182 | PREFIX_VEX_0FF2, | |
1183 | PREFIX_VEX_0FF3, | |
1184 | PREFIX_VEX_0FF4, | |
1185 | PREFIX_VEX_0FF5, | |
1186 | PREFIX_VEX_0FF6, | |
1187 | PREFIX_VEX_0FF7, | |
1188 | PREFIX_VEX_0FF8, | |
1189 | PREFIX_VEX_0FF9, | |
1190 | PREFIX_VEX_0FFA, | |
1191 | PREFIX_VEX_0FFB, | |
1192 | PREFIX_VEX_0FFC, | |
1193 | PREFIX_VEX_0FFD, | |
1194 | PREFIX_VEX_0FFE, | |
1195 | PREFIX_VEX_0F3800, | |
1196 | PREFIX_VEX_0F3801, | |
1197 | PREFIX_VEX_0F3802, | |
1198 | PREFIX_VEX_0F3803, | |
1199 | PREFIX_VEX_0F3804, | |
1200 | PREFIX_VEX_0F3805, | |
1201 | PREFIX_VEX_0F3806, | |
1202 | PREFIX_VEX_0F3807, | |
1203 | PREFIX_VEX_0F3808, | |
1204 | PREFIX_VEX_0F3809, | |
1205 | PREFIX_VEX_0F380A, | |
1206 | PREFIX_VEX_0F380B, | |
1207 | PREFIX_VEX_0F380C, | |
1208 | PREFIX_VEX_0F380D, | |
1209 | PREFIX_VEX_0F380E, | |
1210 | PREFIX_VEX_0F380F, | |
1211 | PREFIX_VEX_0F3813, | |
6c30d220 | 1212 | PREFIX_VEX_0F3816, |
592a252b L |
1213 | PREFIX_VEX_0F3817, |
1214 | PREFIX_VEX_0F3818, | |
1215 | PREFIX_VEX_0F3819, | |
1216 | PREFIX_VEX_0F381A, | |
1217 | PREFIX_VEX_0F381C, | |
1218 | PREFIX_VEX_0F381D, | |
1219 | PREFIX_VEX_0F381E, | |
1220 | PREFIX_VEX_0F3820, | |
1221 | PREFIX_VEX_0F3821, | |
1222 | PREFIX_VEX_0F3822, | |
1223 | PREFIX_VEX_0F3823, | |
1224 | PREFIX_VEX_0F3824, | |
1225 | PREFIX_VEX_0F3825, | |
1226 | PREFIX_VEX_0F3828, | |
1227 | PREFIX_VEX_0F3829, | |
1228 | PREFIX_VEX_0F382A, | |
1229 | PREFIX_VEX_0F382B, | |
1230 | PREFIX_VEX_0F382C, | |
1231 | PREFIX_VEX_0F382D, | |
1232 | PREFIX_VEX_0F382E, | |
1233 | PREFIX_VEX_0F382F, | |
1234 | PREFIX_VEX_0F3830, | |
1235 | PREFIX_VEX_0F3831, | |
1236 | PREFIX_VEX_0F3832, | |
1237 | PREFIX_VEX_0F3833, | |
1238 | PREFIX_VEX_0F3834, | |
1239 | PREFIX_VEX_0F3835, | |
6c30d220 | 1240 | PREFIX_VEX_0F3836, |
592a252b L |
1241 | PREFIX_VEX_0F3837, |
1242 | PREFIX_VEX_0F3838, | |
1243 | PREFIX_VEX_0F3839, | |
1244 | PREFIX_VEX_0F383A, | |
1245 | PREFIX_VEX_0F383B, | |
1246 | PREFIX_VEX_0F383C, | |
1247 | PREFIX_VEX_0F383D, | |
1248 | PREFIX_VEX_0F383E, | |
1249 | PREFIX_VEX_0F383F, | |
1250 | PREFIX_VEX_0F3840, | |
1251 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1252 | PREFIX_VEX_0F3845, |
1253 | PREFIX_VEX_0F3846, | |
1254 | PREFIX_VEX_0F3847, | |
1255 | PREFIX_VEX_0F3858, | |
1256 | PREFIX_VEX_0F3859, | |
1257 | PREFIX_VEX_0F385A, | |
1258 | PREFIX_VEX_0F3878, | |
1259 | PREFIX_VEX_0F3879, | |
1260 | PREFIX_VEX_0F388C, | |
1261 | PREFIX_VEX_0F388E, | |
1262 | PREFIX_VEX_0F3890, | |
1263 | PREFIX_VEX_0F3891, | |
1264 | PREFIX_VEX_0F3892, | |
1265 | PREFIX_VEX_0F3893, | |
592a252b L |
1266 | PREFIX_VEX_0F3896, |
1267 | PREFIX_VEX_0F3897, | |
1268 | PREFIX_VEX_0F3898, | |
1269 | PREFIX_VEX_0F3899, | |
1270 | PREFIX_VEX_0F389A, | |
1271 | PREFIX_VEX_0F389B, | |
1272 | PREFIX_VEX_0F389C, | |
1273 | PREFIX_VEX_0F389D, | |
1274 | PREFIX_VEX_0F389E, | |
1275 | PREFIX_VEX_0F389F, | |
1276 | PREFIX_VEX_0F38A6, | |
1277 | PREFIX_VEX_0F38A7, | |
1278 | PREFIX_VEX_0F38A8, | |
1279 | PREFIX_VEX_0F38A9, | |
1280 | PREFIX_VEX_0F38AA, | |
1281 | PREFIX_VEX_0F38AB, | |
1282 | PREFIX_VEX_0F38AC, | |
1283 | PREFIX_VEX_0F38AD, | |
1284 | PREFIX_VEX_0F38AE, | |
1285 | PREFIX_VEX_0F38AF, | |
1286 | PREFIX_VEX_0F38B6, | |
1287 | PREFIX_VEX_0F38B7, | |
1288 | PREFIX_VEX_0F38B8, | |
1289 | PREFIX_VEX_0F38B9, | |
1290 | PREFIX_VEX_0F38BA, | |
1291 | PREFIX_VEX_0F38BB, | |
1292 | PREFIX_VEX_0F38BC, | |
1293 | PREFIX_VEX_0F38BD, | |
1294 | PREFIX_VEX_0F38BE, | |
1295 | PREFIX_VEX_0F38BF, | |
1296 | PREFIX_VEX_0F38DB, | |
1297 | PREFIX_VEX_0F38DC, | |
1298 | PREFIX_VEX_0F38DD, | |
1299 | PREFIX_VEX_0F38DE, | |
1300 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1301 | PREFIX_VEX_0F38F2, |
1302 | PREFIX_VEX_0F38F3_REG_1, | |
1303 | PREFIX_VEX_0F38F3_REG_2, | |
1304 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1305 | PREFIX_VEX_0F38F5, |
1306 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1307 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1308 | PREFIX_VEX_0F3A00, |
1309 | PREFIX_VEX_0F3A01, | |
1310 | PREFIX_VEX_0F3A02, | |
592a252b L |
1311 | PREFIX_VEX_0F3A04, |
1312 | PREFIX_VEX_0F3A05, | |
1313 | PREFIX_VEX_0F3A06, | |
1314 | PREFIX_VEX_0F3A08, | |
1315 | PREFIX_VEX_0F3A09, | |
1316 | PREFIX_VEX_0F3A0A, | |
1317 | PREFIX_VEX_0F3A0B, | |
1318 | PREFIX_VEX_0F3A0C, | |
1319 | PREFIX_VEX_0F3A0D, | |
1320 | PREFIX_VEX_0F3A0E, | |
1321 | PREFIX_VEX_0F3A0F, | |
1322 | PREFIX_VEX_0F3A14, | |
1323 | PREFIX_VEX_0F3A15, | |
1324 | PREFIX_VEX_0F3A16, | |
1325 | PREFIX_VEX_0F3A17, | |
1326 | PREFIX_VEX_0F3A18, | |
1327 | PREFIX_VEX_0F3A19, | |
1328 | PREFIX_VEX_0F3A1D, | |
1329 | PREFIX_VEX_0F3A20, | |
1330 | PREFIX_VEX_0F3A21, | |
1331 | PREFIX_VEX_0F3A22, | |
43234a1e | 1332 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1333 | PREFIX_VEX_0F3A31, |
43234a1e | 1334 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1335 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1336 | PREFIX_VEX_0F3A38, |
1337 | PREFIX_VEX_0F3A39, | |
592a252b L |
1338 | PREFIX_VEX_0F3A40, |
1339 | PREFIX_VEX_0F3A41, | |
1340 | PREFIX_VEX_0F3A42, | |
1341 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1342 | PREFIX_VEX_0F3A46, |
592a252b L |
1343 | PREFIX_VEX_0F3A48, |
1344 | PREFIX_VEX_0F3A49, | |
1345 | PREFIX_VEX_0F3A4A, | |
1346 | PREFIX_VEX_0F3A4B, | |
1347 | PREFIX_VEX_0F3A4C, | |
1348 | PREFIX_VEX_0F3A5C, | |
1349 | PREFIX_VEX_0F3A5D, | |
1350 | PREFIX_VEX_0F3A5E, | |
1351 | PREFIX_VEX_0F3A5F, | |
1352 | PREFIX_VEX_0F3A60, | |
1353 | PREFIX_VEX_0F3A61, | |
1354 | PREFIX_VEX_0F3A62, | |
1355 | PREFIX_VEX_0F3A63, | |
1356 | PREFIX_VEX_0F3A68, | |
1357 | PREFIX_VEX_0F3A69, | |
1358 | PREFIX_VEX_0F3A6A, | |
1359 | PREFIX_VEX_0F3A6B, | |
1360 | PREFIX_VEX_0F3A6C, | |
1361 | PREFIX_VEX_0F3A6D, | |
1362 | PREFIX_VEX_0F3A6E, | |
1363 | PREFIX_VEX_0F3A6F, | |
1364 | PREFIX_VEX_0F3A78, | |
1365 | PREFIX_VEX_0F3A79, | |
1366 | PREFIX_VEX_0F3A7A, | |
1367 | PREFIX_VEX_0F3A7B, | |
1368 | PREFIX_VEX_0F3A7C, | |
1369 | PREFIX_VEX_0F3A7D, | |
1370 | PREFIX_VEX_0F3A7E, | |
1371 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1372 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1373 | PREFIX_VEX_0F3AF0, |
1374 | ||
1375 | PREFIX_EVEX_0F10, | |
1376 | PREFIX_EVEX_0F11, | |
1377 | PREFIX_EVEX_0F12, | |
1378 | PREFIX_EVEX_0F13, | |
1379 | PREFIX_EVEX_0F14, | |
1380 | PREFIX_EVEX_0F15, | |
1381 | PREFIX_EVEX_0F16, | |
1382 | PREFIX_EVEX_0F17, | |
1383 | PREFIX_EVEX_0F28, | |
1384 | PREFIX_EVEX_0F29, | |
1385 | PREFIX_EVEX_0F2A, | |
1386 | PREFIX_EVEX_0F2B, | |
1387 | PREFIX_EVEX_0F2C, | |
1388 | PREFIX_EVEX_0F2D, | |
1389 | PREFIX_EVEX_0F2E, | |
1390 | PREFIX_EVEX_0F2F, | |
1391 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1392 | PREFIX_EVEX_0F54, |
1393 | PREFIX_EVEX_0F55, | |
1394 | PREFIX_EVEX_0F56, | |
1395 | PREFIX_EVEX_0F57, | |
43234a1e L |
1396 | PREFIX_EVEX_0F58, |
1397 | PREFIX_EVEX_0F59, | |
1398 | PREFIX_EVEX_0F5A, | |
1399 | PREFIX_EVEX_0F5B, | |
1400 | PREFIX_EVEX_0F5C, | |
1401 | PREFIX_EVEX_0F5D, | |
1402 | PREFIX_EVEX_0F5E, | |
1403 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1404 | PREFIX_EVEX_0F60, |
1405 | PREFIX_EVEX_0F61, | |
43234a1e | 1406 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1407 | PREFIX_EVEX_0F63, |
1408 | PREFIX_EVEX_0F64, | |
1409 | PREFIX_EVEX_0F65, | |
43234a1e | 1410 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1411 | PREFIX_EVEX_0F67, |
1412 | PREFIX_EVEX_0F68, | |
1413 | PREFIX_EVEX_0F69, | |
43234a1e | 1414 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1415 | PREFIX_EVEX_0F6B, |
43234a1e L |
1416 | PREFIX_EVEX_0F6C, |
1417 | PREFIX_EVEX_0F6D, | |
1418 | PREFIX_EVEX_0F6E, | |
1419 | PREFIX_EVEX_0F6F, | |
1420 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1421 | PREFIX_EVEX_0F71_REG_2, |
1422 | PREFIX_EVEX_0F71_REG_4, | |
1423 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1424 | PREFIX_EVEX_0F72_REG_0, |
1425 | PREFIX_EVEX_0F72_REG_1, | |
1426 | PREFIX_EVEX_0F72_REG_2, | |
1427 | PREFIX_EVEX_0F72_REG_4, | |
1428 | PREFIX_EVEX_0F72_REG_6, | |
1429 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1430 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1431 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1432 | PREFIX_EVEX_0F73_REG_7, |
1433 | PREFIX_EVEX_0F74, | |
1434 | PREFIX_EVEX_0F75, | |
43234a1e L |
1435 | PREFIX_EVEX_0F76, |
1436 | PREFIX_EVEX_0F78, | |
1437 | PREFIX_EVEX_0F79, | |
1438 | PREFIX_EVEX_0F7A, | |
1439 | PREFIX_EVEX_0F7B, | |
1440 | PREFIX_EVEX_0F7E, | |
1441 | PREFIX_EVEX_0F7F, | |
1442 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1443 | PREFIX_EVEX_0FC4, |
1444 | PREFIX_EVEX_0FC5, | |
43234a1e | 1445 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1446 | PREFIX_EVEX_0FD1, |
43234a1e L |
1447 | PREFIX_EVEX_0FD2, |
1448 | PREFIX_EVEX_0FD3, | |
1449 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1450 | PREFIX_EVEX_0FD5, |
43234a1e | 1451 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1452 | PREFIX_EVEX_0FD8, |
1453 | PREFIX_EVEX_0FD9, | |
1454 | PREFIX_EVEX_0FDA, | |
43234a1e | 1455 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1456 | PREFIX_EVEX_0FDC, |
1457 | PREFIX_EVEX_0FDD, | |
1458 | PREFIX_EVEX_0FDE, | |
43234a1e | 1459 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1460 | PREFIX_EVEX_0FE0, |
1461 | PREFIX_EVEX_0FE1, | |
43234a1e | 1462 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1463 | PREFIX_EVEX_0FE3, |
1464 | PREFIX_EVEX_0FE4, | |
1465 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1466 | PREFIX_EVEX_0FE6, |
1467 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1468 | PREFIX_EVEX_0FE8, |
1469 | PREFIX_EVEX_0FE9, | |
1470 | PREFIX_EVEX_0FEA, | |
43234a1e | 1471 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1472 | PREFIX_EVEX_0FEC, |
1473 | PREFIX_EVEX_0FED, | |
1474 | PREFIX_EVEX_0FEE, | |
43234a1e | 1475 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1476 | PREFIX_EVEX_0FF1, |
43234a1e L |
1477 | PREFIX_EVEX_0FF2, |
1478 | PREFIX_EVEX_0FF3, | |
1479 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1480 | PREFIX_EVEX_0FF5, |
1481 | PREFIX_EVEX_0FF6, | |
1482 | PREFIX_EVEX_0FF8, | |
1483 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1484 | PREFIX_EVEX_0FFA, |
1485 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1486 | PREFIX_EVEX_0FFC, |
1487 | PREFIX_EVEX_0FFD, | |
43234a1e | 1488 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1489 | PREFIX_EVEX_0F3800, |
1490 | PREFIX_EVEX_0F3804, | |
1491 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1492 | PREFIX_EVEX_0F380C, |
1493 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1494 | PREFIX_EVEX_0F3810, |
43234a1e L |
1495 | PREFIX_EVEX_0F3811, |
1496 | PREFIX_EVEX_0F3812, | |
1497 | PREFIX_EVEX_0F3813, | |
1498 | PREFIX_EVEX_0F3814, | |
1499 | PREFIX_EVEX_0F3815, | |
1500 | PREFIX_EVEX_0F3816, | |
1501 | PREFIX_EVEX_0F3818, | |
1502 | PREFIX_EVEX_0F3819, | |
1503 | PREFIX_EVEX_0F381A, | |
1504 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1505 | PREFIX_EVEX_0F381C, |
1506 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1507 | PREFIX_EVEX_0F381E, |
1508 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1509 | PREFIX_EVEX_0F3820, |
43234a1e L |
1510 | PREFIX_EVEX_0F3821, |
1511 | PREFIX_EVEX_0F3822, | |
1512 | PREFIX_EVEX_0F3823, | |
1513 | PREFIX_EVEX_0F3824, | |
1514 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1515 | PREFIX_EVEX_0F3826, |
43234a1e L |
1516 | PREFIX_EVEX_0F3827, |
1517 | PREFIX_EVEX_0F3828, | |
1518 | PREFIX_EVEX_0F3829, | |
1519 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1520 | PREFIX_EVEX_0F382B, |
43234a1e L |
1521 | PREFIX_EVEX_0F382C, |
1522 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1523 | PREFIX_EVEX_0F3830, |
43234a1e L |
1524 | PREFIX_EVEX_0F3831, |
1525 | PREFIX_EVEX_0F3832, | |
1526 | PREFIX_EVEX_0F3833, | |
1527 | PREFIX_EVEX_0F3834, | |
1528 | PREFIX_EVEX_0F3835, | |
1529 | PREFIX_EVEX_0F3836, | |
1530 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1531 | PREFIX_EVEX_0F3838, |
43234a1e L |
1532 | PREFIX_EVEX_0F3839, |
1533 | PREFIX_EVEX_0F383A, | |
1534 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1535 | PREFIX_EVEX_0F383C, |
43234a1e | 1536 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1537 | PREFIX_EVEX_0F383E, |
43234a1e L |
1538 | PREFIX_EVEX_0F383F, |
1539 | PREFIX_EVEX_0F3840, | |
1540 | PREFIX_EVEX_0F3842, | |
1541 | PREFIX_EVEX_0F3843, | |
1542 | PREFIX_EVEX_0F3844, | |
1543 | PREFIX_EVEX_0F3845, | |
1544 | PREFIX_EVEX_0F3846, | |
1545 | PREFIX_EVEX_0F3847, | |
1546 | PREFIX_EVEX_0F384C, | |
1547 | PREFIX_EVEX_0F384D, | |
1548 | PREFIX_EVEX_0F384E, | |
1549 | PREFIX_EVEX_0F384F, | |
1550 | PREFIX_EVEX_0F3858, | |
1551 | PREFIX_EVEX_0F3859, | |
1552 | PREFIX_EVEX_0F385A, | |
1553 | PREFIX_EVEX_0F385B, | |
1554 | PREFIX_EVEX_0F3864, | |
1555 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1556 | PREFIX_EVEX_0F3866, |
1557 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1558 | PREFIX_EVEX_0F3876, |
1559 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1560 | PREFIX_EVEX_0F3878, |
1561 | PREFIX_EVEX_0F3879, | |
1562 | PREFIX_EVEX_0F387A, | |
1563 | PREFIX_EVEX_0F387B, | |
43234a1e | 1564 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1565 | PREFIX_EVEX_0F387D, |
43234a1e L |
1566 | PREFIX_EVEX_0F387E, |
1567 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1568 | PREFIX_EVEX_0F3883, |
43234a1e L |
1569 | PREFIX_EVEX_0F3888, |
1570 | PREFIX_EVEX_0F3889, | |
1571 | PREFIX_EVEX_0F388A, | |
1572 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1573 | PREFIX_EVEX_0F388D, |
43234a1e L |
1574 | PREFIX_EVEX_0F3890, |
1575 | PREFIX_EVEX_0F3891, | |
1576 | PREFIX_EVEX_0F3892, | |
1577 | PREFIX_EVEX_0F3893, | |
1578 | PREFIX_EVEX_0F3896, | |
1579 | PREFIX_EVEX_0F3897, | |
1580 | PREFIX_EVEX_0F3898, | |
1581 | PREFIX_EVEX_0F3899, | |
1582 | PREFIX_EVEX_0F389A, | |
1583 | PREFIX_EVEX_0F389B, | |
1584 | PREFIX_EVEX_0F389C, | |
1585 | PREFIX_EVEX_0F389D, | |
1586 | PREFIX_EVEX_0F389E, | |
1587 | PREFIX_EVEX_0F389F, | |
1588 | PREFIX_EVEX_0F38A0, | |
1589 | PREFIX_EVEX_0F38A1, | |
1590 | PREFIX_EVEX_0F38A2, | |
1591 | PREFIX_EVEX_0F38A3, | |
1592 | PREFIX_EVEX_0F38A6, | |
1593 | PREFIX_EVEX_0F38A7, | |
1594 | PREFIX_EVEX_0F38A8, | |
1595 | PREFIX_EVEX_0F38A9, | |
1596 | PREFIX_EVEX_0F38AA, | |
1597 | PREFIX_EVEX_0F38AB, | |
1598 | PREFIX_EVEX_0F38AC, | |
1599 | PREFIX_EVEX_0F38AD, | |
1600 | PREFIX_EVEX_0F38AE, | |
1601 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1602 | PREFIX_EVEX_0F38B4, |
1603 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1604 | PREFIX_EVEX_0F38B6, |
1605 | PREFIX_EVEX_0F38B7, | |
1606 | PREFIX_EVEX_0F38B8, | |
1607 | PREFIX_EVEX_0F38B9, | |
1608 | PREFIX_EVEX_0F38BA, | |
1609 | PREFIX_EVEX_0F38BB, | |
1610 | PREFIX_EVEX_0F38BC, | |
1611 | PREFIX_EVEX_0F38BD, | |
1612 | PREFIX_EVEX_0F38BE, | |
1613 | PREFIX_EVEX_0F38BF, | |
1614 | PREFIX_EVEX_0F38C4, | |
1615 | PREFIX_EVEX_0F38C6_REG_1, | |
1616 | PREFIX_EVEX_0F38C6_REG_2, | |
1617 | PREFIX_EVEX_0F38C6_REG_5, | |
1618 | PREFIX_EVEX_0F38C6_REG_6, | |
1619 | PREFIX_EVEX_0F38C7_REG_1, | |
1620 | PREFIX_EVEX_0F38C7_REG_2, | |
1621 | PREFIX_EVEX_0F38C7_REG_5, | |
1622 | PREFIX_EVEX_0F38C7_REG_6, | |
1623 | PREFIX_EVEX_0F38C8, | |
1624 | PREFIX_EVEX_0F38CA, | |
1625 | PREFIX_EVEX_0F38CB, | |
1626 | PREFIX_EVEX_0F38CC, | |
1627 | PREFIX_EVEX_0F38CD, | |
1628 | ||
1629 | PREFIX_EVEX_0F3A00, | |
1630 | PREFIX_EVEX_0F3A01, | |
1631 | PREFIX_EVEX_0F3A03, | |
1632 | PREFIX_EVEX_0F3A04, | |
1633 | PREFIX_EVEX_0F3A05, | |
1634 | PREFIX_EVEX_0F3A08, | |
1635 | PREFIX_EVEX_0F3A09, | |
1636 | PREFIX_EVEX_0F3A0A, | |
1637 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1638 | PREFIX_EVEX_0F3A0F, |
1639 | PREFIX_EVEX_0F3A14, | |
1640 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1641 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1642 | PREFIX_EVEX_0F3A17, |
1643 | PREFIX_EVEX_0F3A18, | |
1644 | PREFIX_EVEX_0F3A19, | |
1645 | PREFIX_EVEX_0F3A1A, | |
1646 | PREFIX_EVEX_0F3A1B, | |
1647 | PREFIX_EVEX_0F3A1D, | |
1648 | PREFIX_EVEX_0F3A1E, | |
1649 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1650 | PREFIX_EVEX_0F3A20, |
43234a1e | 1651 | PREFIX_EVEX_0F3A21, |
90a915bf | 1652 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1653 | PREFIX_EVEX_0F3A23, |
1654 | PREFIX_EVEX_0F3A25, | |
1655 | PREFIX_EVEX_0F3A26, | |
1656 | PREFIX_EVEX_0F3A27, | |
1657 | PREFIX_EVEX_0F3A38, | |
1658 | PREFIX_EVEX_0F3A39, | |
1659 | PREFIX_EVEX_0F3A3A, | |
1660 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1661 | PREFIX_EVEX_0F3A3E, |
1662 | PREFIX_EVEX_0F3A3F, | |
1663 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1664 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1665 | PREFIX_EVEX_0F3A50, |
1666 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1667 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1668 | PREFIX_EVEX_0F3A55, |
1669 | PREFIX_EVEX_0F3A56, | |
1670 | PREFIX_EVEX_0F3A57, | |
1671 | PREFIX_EVEX_0F3A66, | |
1672 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1673 | }; |
4e7d34a6 | 1674 | |
51e7da1b L |
1675 | enum |
1676 | { | |
1677 | X86_64_06 = 0, | |
3873ba12 L |
1678 | X86_64_07, |
1679 | X86_64_0D, | |
1680 | X86_64_16, | |
1681 | X86_64_17, | |
1682 | X86_64_1E, | |
1683 | X86_64_1F, | |
1684 | X86_64_27, | |
1685 | X86_64_2F, | |
1686 | X86_64_37, | |
1687 | X86_64_3F, | |
1688 | X86_64_60, | |
1689 | X86_64_61, | |
1690 | X86_64_62, | |
1691 | X86_64_63, | |
1692 | X86_64_6D, | |
1693 | X86_64_6F, | |
1694 | X86_64_9A, | |
1695 | X86_64_C4, | |
1696 | X86_64_C5, | |
1697 | X86_64_CE, | |
1698 | X86_64_D4, | |
1699 | X86_64_D5, | |
a72d2af2 L |
1700 | X86_64_E8, |
1701 | X86_64_E9, | |
3873ba12 L |
1702 | X86_64_EA, |
1703 | X86_64_0F01_REG_0, | |
1704 | X86_64_0F01_REG_1, | |
1705 | X86_64_0F01_REG_2, | |
1706 | X86_64_0F01_REG_3 | |
51e7da1b | 1707 | }; |
4e7d34a6 | 1708 | |
51e7da1b L |
1709 | enum |
1710 | { | |
1711 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1712 | THREE_BYTE_0F3A, |
1713 | THREE_BYTE_0F7A | |
51e7da1b | 1714 | }; |
4e7d34a6 | 1715 | |
f88c9eb0 SP |
1716 | enum |
1717 | { | |
5dd85c99 SP |
1718 | XOP_08 = 0, |
1719 | XOP_09, | |
f88c9eb0 SP |
1720 | XOP_0A |
1721 | }; | |
1722 | ||
51e7da1b L |
1723 | enum |
1724 | { | |
1725 | VEX_0F = 0, | |
3873ba12 L |
1726 | VEX_0F38, |
1727 | VEX_0F3A | |
51e7da1b | 1728 | }; |
c0f3af97 | 1729 | |
43234a1e L |
1730 | enum |
1731 | { | |
1732 | EVEX_0F = 0, | |
1733 | EVEX_0F38, | |
1734 | EVEX_0F3A | |
1735 | }; | |
1736 | ||
51e7da1b L |
1737 | enum |
1738 | { | |
592a252b L |
1739 | VEX_LEN_0F10_P_1 = 0, |
1740 | VEX_LEN_0F10_P_3, | |
1741 | VEX_LEN_0F11_P_1, | |
1742 | VEX_LEN_0F11_P_3, | |
1743 | VEX_LEN_0F12_P_0_M_0, | |
1744 | VEX_LEN_0F12_P_0_M_1, | |
1745 | VEX_LEN_0F12_P_2, | |
1746 | VEX_LEN_0F13_M_0, | |
1747 | VEX_LEN_0F16_P_0_M_0, | |
1748 | VEX_LEN_0F16_P_0_M_1, | |
1749 | VEX_LEN_0F16_P_2, | |
1750 | VEX_LEN_0F17_M_0, | |
1751 | VEX_LEN_0F2A_P_1, | |
1752 | VEX_LEN_0F2A_P_3, | |
1753 | VEX_LEN_0F2C_P_1, | |
1754 | VEX_LEN_0F2C_P_3, | |
1755 | VEX_LEN_0F2D_P_1, | |
1756 | VEX_LEN_0F2D_P_3, | |
1757 | VEX_LEN_0F2E_P_0, | |
1758 | VEX_LEN_0F2E_P_2, | |
1759 | VEX_LEN_0F2F_P_0, | |
1760 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1761 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1762 | VEX_LEN_0F41_P_2, |
43234a1e | 1763 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1764 | VEX_LEN_0F42_P_2, |
43234a1e | 1765 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1766 | VEX_LEN_0F44_P_2, |
43234a1e | 1767 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1768 | VEX_LEN_0F45_P_2, |
43234a1e | 1769 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1770 | VEX_LEN_0F46_P_2, |
43234a1e | 1771 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1772 | VEX_LEN_0F47_P_2, |
1773 | VEX_LEN_0F4A_P_0, | |
1774 | VEX_LEN_0F4A_P_2, | |
1775 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1776 | VEX_LEN_0F4B_P_2, |
592a252b L |
1777 | VEX_LEN_0F51_P_1, |
1778 | VEX_LEN_0F51_P_3, | |
1779 | VEX_LEN_0F52_P_1, | |
1780 | VEX_LEN_0F53_P_1, | |
1781 | VEX_LEN_0F58_P_1, | |
1782 | VEX_LEN_0F58_P_3, | |
1783 | VEX_LEN_0F59_P_1, | |
1784 | VEX_LEN_0F59_P_3, | |
1785 | VEX_LEN_0F5A_P_1, | |
1786 | VEX_LEN_0F5A_P_3, | |
1787 | VEX_LEN_0F5C_P_1, | |
1788 | VEX_LEN_0F5C_P_3, | |
1789 | VEX_LEN_0F5D_P_1, | |
1790 | VEX_LEN_0F5D_P_3, | |
1791 | VEX_LEN_0F5E_P_1, | |
1792 | VEX_LEN_0F5E_P_3, | |
1793 | VEX_LEN_0F5F_P_1, | |
1794 | VEX_LEN_0F5F_P_3, | |
592a252b | 1795 | VEX_LEN_0F6E_P_2, |
592a252b L |
1796 | VEX_LEN_0F7E_P_1, |
1797 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1798 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1799 | VEX_LEN_0F90_P_2, |
43234a1e | 1800 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1801 | VEX_LEN_0F91_P_2, |
43234a1e | 1802 | VEX_LEN_0F92_P_0, |
90a915bf | 1803 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1804 | VEX_LEN_0F92_P_3, |
43234a1e | 1805 | VEX_LEN_0F93_P_0, |
90a915bf | 1806 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1807 | VEX_LEN_0F93_P_3, |
43234a1e | 1808 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1809 | VEX_LEN_0F98_P_2, |
1810 | VEX_LEN_0F99_P_0, | |
1811 | VEX_LEN_0F99_P_2, | |
592a252b L |
1812 | VEX_LEN_0FAE_R_2_M_0, |
1813 | VEX_LEN_0FAE_R_3_M_0, | |
1814 | VEX_LEN_0FC2_P_1, | |
1815 | VEX_LEN_0FC2_P_3, | |
1816 | VEX_LEN_0FC4_P_2, | |
1817 | VEX_LEN_0FC5_P_2, | |
592a252b | 1818 | VEX_LEN_0FD6_P_2, |
592a252b | 1819 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1820 | VEX_LEN_0F3816_P_2, |
1821 | VEX_LEN_0F3819_P_2, | |
592a252b | 1822 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1823 | VEX_LEN_0F3836_P_2, |
592a252b | 1824 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1825 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1826 | VEX_LEN_0F38DB_P_2, |
1827 | VEX_LEN_0F38DC_P_2, | |
1828 | VEX_LEN_0F38DD_P_2, | |
1829 | VEX_LEN_0F38DE_P_2, | |
1830 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1831 | VEX_LEN_0F38F2_P_0, |
1832 | VEX_LEN_0F38F3_R_1_P_0, | |
1833 | VEX_LEN_0F38F3_R_2_P_0, | |
1834 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1835 | VEX_LEN_0F38F5_P_0, |
1836 | VEX_LEN_0F38F5_P_1, | |
1837 | VEX_LEN_0F38F5_P_3, | |
1838 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1839 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1840 | VEX_LEN_0F38F7_P_1, |
1841 | VEX_LEN_0F38F7_P_2, | |
1842 | VEX_LEN_0F38F7_P_3, | |
1843 | VEX_LEN_0F3A00_P_2, | |
1844 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1845 | VEX_LEN_0F3A06_P_2, |
1846 | VEX_LEN_0F3A0A_P_2, | |
1847 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1848 | VEX_LEN_0F3A14_P_2, |
1849 | VEX_LEN_0F3A15_P_2, | |
1850 | VEX_LEN_0F3A16_P_2, | |
1851 | VEX_LEN_0F3A17_P_2, | |
1852 | VEX_LEN_0F3A18_P_2, | |
1853 | VEX_LEN_0F3A19_P_2, | |
1854 | VEX_LEN_0F3A20_P_2, | |
1855 | VEX_LEN_0F3A21_P_2, | |
1856 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1857 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1858 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1859 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1860 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1861 | VEX_LEN_0F3A38_P_2, |
1862 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1863 | VEX_LEN_0F3A41_P_2, |
592a252b | 1864 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1865 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1866 | VEX_LEN_0F3A60_P_2, |
1867 | VEX_LEN_0F3A61_P_2, | |
1868 | VEX_LEN_0F3A62_P_2, | |
1869 | VEX_LEN_0F3A63_P_2, | |
1870 | VEX_LEN_0F3A6A_P_2, | |
1871 | VEX_LEN_0F3A6B_P_2, | |
1872 | VEX_LEN_0F3A6E_P_2, | |
1873 | VEX_LEN_0F3A6F_P_2, | |
1874 | VEX_LEN_0F3A7A_P_2, | |
1875 | VEX_LEN_0F3A7B_P_2, | |
1876 | VEX_LEN_0F3A7E_P_2, | |
1877 | VEX_LEN_0F3A7F_P_2, | |
1878 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1879 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1880 | VEX_LEN_0FXOP_08_CC, |
1881 | VEX_LEN_0FXOP_08_CD, | |
1882 | VEX_LEN_0FXOP_08_CE, | |
1883 | VEX_LEN_0FXOP_08_CF, | |
1884 | VEX_LEN_0FXOP_08_EC, | |
1885 | VEX_LEN_0FXOP_08_ED, | |
1886 | VEX_LEN_0FXOP_08_EE, | |
1887 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1888 | VEX_LEN_0FXOP_09_80, |
1889 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1890 | }; |
c0f3af97 | 1891 | |
9e30b8e0 L |
1892 | enum |
1893 | { | |
592a252b L |
1894 | VEX_W_0F10_P_0 = 0, |
1895 | VEX_W_0F10_P_1, | |
1896 | VEX_W_0F10_P_2, | |
1897 | VEX_W_0F10_P_3, | |
1898 | VEX_W_0F11_P_0, | |
1899 | VEX_W_0F11_P_1, | |
1900 | VEX_W_0F11_P_2, | |
1901 | VEX_W_0F11_P_3, | |
1902 | VEX_W_0F12_P_0_M_0, | |
1903 | VEX_W_0F12_P_0_M_1, | |
1904 | VEX_W_0F12_P_1, | |
1905 | VEX_W_0F12_P_2, | |
1906 | VEX_W_0F12_P_3, | |
1907 | VEX_W_0F13_M_0, | |
1908 | VEX_W_0F14, | |
1909 | VEX_W_0F15, | |
1910 | VEX_W_0F16_P_0_M_0, | |
1911 | VEX_W_0F16_P_0_M_1, | |
1912 | VEX_W_0F16_P_1, | |
1913 | VEX_W_0F16_P_2, | |
1914 | VEX_W_0F17_M_0, | |
1915 | VEX_W_0F28, | |
1916 | VEX_W_0F29, | |
1917 | VEX_W_0F2B_M_0, | |
1918 | VEX_W_0F2E_P_0, | |
1919 | VEX_W_0F2E_P_2, | |
1920 | VEX_W_0F2F_P_0, | |
1921 | VEX_W_0F2F_P_2, | |
43234a1e | 1922 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1923 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1924 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1925 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1926 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1927 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1928 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1929 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1930 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1931 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1932 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1933 | VEX_W_0F47_P_2_LEN_1, |
1934 | VEX_W_0F4A_P_0_LEN_1, | |
1935 | VEX_W_0F4A_P_2_LEN_1, | |
1936 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1937 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1938 | VEX_W_0F50_M_0, |
1939 | VEX_W_0F51_P_0, | |
1940 | VEX_W_0F51_P_1, | |
1941 | VEX_W_0F51_P_2, | |
1942 | VEX_W_0F51_P_3, | |
1943 | VEX_W_0F52_P_0, | |
1944 | VEX_W_0F52_P_1, | |
1945 | VEX_W_0F53_P_0, | |
1946 | VEX_W_0F53_P_1, | |
1947 | VEX_W_0F58_P_0, | |
1948 | VEX_W_0F58_P_1, | |
1949 | VEX_W_0F58_P_2, | |
1950 | VEX_W_0F58_P_3, | |
1951 | VEX_W_0F59_P_0, | |
1952 | VEX_W_0F59_P_1, | |
1953 | VEX_W_0F59_P_2, | |
1954 | VEX_W_0F59_P_3, | |
1955 | VEX_W_0F5A_P_0, | |
1956 | VEX_W_0F5A_P_1, | |
1957 | VEX_W_0F5A_P_3, | |
1958 | VEX_W_0F5B_P_0, | |
1959 | VEX_W_0F5B_P_1, | |
1960 | VEX_W_0F5B_P_2, | |
1961 | VEX_W_0F5C_P_0, | |
1962 | VEX_W_0F5C_P_1, | |
1963 | VEX_W_0F5C_P_2, | |
1964 | VEX_W_0F5C_P_3, | |
1965 | VEX_W_0F5D_P_0, | |
1966 | VEX_W_0F5D_P_1, | |
1967 | VEX_W_0F5D_P_2, | |
1968 | VEX_W_0F5D_P_3, | |
1969 | VEX_W_0F5E_P_0, | |
1970 | VEX_W_0F5E_P_1, | |
1971 | VEX_W_0F5E_P_2, | |
1972 | VEX_W_0F5E_P_3, | |
1973 | VEX_W_0F5F_P_0, | |
1974 | VEX_W_0F5F_P_1, | |
1975 | VEX_W_0F5F_P_2, | |
1976 | VEX_W_0F5F_P_3, | |
1977 | VEX_W_0F60_P_2, | |
1978 | VEX_W_0F61_P_2, | |
1979 | VEX_W_0F62_P_2, | |
1980 | VEX_W_0F63_P_2, | |
1981 | VEX_W_0F64_P_2, | |
1982 | VEX_W_0F65_P_2, | |
1983 | VEX_W_0F66_P_2, | |
1984 | VEX_W_0F67_P_2, | |
1985 | VEX_W_0F68_P_2, | |
1986 | VEX_W_0F69_P_2, | |
1987 | VEX_W_0F6A_P_2, | |
1988 | VEX_W_0F6B_P_2, | |
1989 | VEX_W_0F6C_P_2, | |
1990 | VEX_W_0F6D_P_2, | |
1991 | VEX_W_0F6F_P_1, | |
1992 | VEX_W_0F6F_P_2, | |
1993 | VEX_W_0F70_P_1, | |
1994 | VEX_W_0F70_P_2, | |
1995 | VEX_W_0F70_P_3, | |
1996 | VEX_W_0F71_R_2_P_2, | |
1997 | VEX_W_0F71_R_4_P_2, | |
1998 | VEX_W_0F71_R_6_P_2, | |
1999 | VEX_W_0F72_R_2_P_2, | |
2000 | VEX_W_0F72_R_4_P_2, | |
2001 | VEX_W_0F72_R_6_P_2, | |
2002 | VEX_W_0F73_R_2_P_2, | |
2003 | VEX_W_0F73_R_3_P_2, | |
2004 | VEX_W_0F73_R_6_P_2, | |
2005 | VEX_W_0F73_R_7_P_2, | |
2006 | VEX_W_0F74_P_2, | |
2007 | VEX_W_0F75_P_2, | |
2008 | VEX_W_0F76_P_2, | |
2009 | VEX_W_0F77_P_0, | |
2010 | VEX_W_0F7C_P_2, | |
2011 | VEX_W_0F7C_P_3, | |
2012 | VEX_W_0F7D_P_2, | |
2013 | VEX_W_0F7D_P_3, | |
2014 | VEX_W_0F7E_P_1, | |
2015 | VEX_W_0F7F_P_1, | |
2016 | VEX_W_0F7F_P_2, | |
43234a1e | 2017 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2018 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2019 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2020 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2021 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2022 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2023 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2024 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2025 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2026 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2027 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2028 | VEX_W_0F98_P_2_LEN_0, |
2029 | VEX_W_0F99_P_0_LEN_0, | |
2030 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2031 | VEX_W_0FAE_R_2_M_0, |
2032 | VEX_W_0FAE_R_3_M_0, | |
2033 | VEX_W_0FC2_P_0, | |
2034 | VEX_W_0FC2_P_1, | |
2035 | VEX_W_0FC2_P_2, | |
2036 | VEX_W_0FC2_P_3, | |
2037 | VEX_W_0FC4_P_2, | |
2038 | VEX_W_0FC5_P_2, | |
2039 | VEX_W_0FD0_P_2, | |
2040 | VEX_W_0FD0_P_3, | |
2041 | VEX_W_0FD1_P_2, | |
2042 | VEX_W_0FD2_P_2, | |
2043 | VEX_W_0FD3_P_2, | |
2044 | VEX_W_0FD4_P_2, | |
2045 | VEX_W_0FD5_P_2, | |
2046 | VEX_W_0FD6_P_2, | |
2047 | VEX_W_0FD7_P_2_M_1, | |
2048 | VEX_W_0FD8_P_2, | |
2049 | VEX_W_0FD9_P_2, | |
2050 | VEX_W_0FDA_P_2, | |
2051 | VEX_W_0FDB_P_2, | |
2052 | VEX_W_0FDC_P_2, | |
2053 | VEX_W_0FDD_P_2, | |
2054 | VEX_W_0FDE_P_2, | |
2055 | VEX_W_0FDF_P_2, | |
2056 | VEX_W_0FE0_P_2, | |
2057 | VEX_W_0FE1_P_2, | |
2058 | VEX_W_0FE2_P_2, | |
2059 | VEX_W_0FE3_P_2, | |
2060 | VEX_W_0FE4_P_2, | |
2061 | VEX_W_0FE5_P_2, | |
2062 | VEX_W_0FE6_P_1, | |
2063 | VEX_W_0FE6_P_2, | |
2064 | VEX_W_0FE6_P_3, | |
2065 | VEX_W_0FE7_P_2_M_0, | |
2066 | VEX_W_0FE8_P_2, | |
2067 | VEX_W_0FE9_P_2, | |
2068 | VEX_W_0FEA_P_2, | |
2069 | VEX_W_0FEB_P_2, | |
2070 | VEX_W_0FEC_P_2, | |
2071 | VEX_W_0FED_P_2, | |
2072 | VEX_W_0FEE_P_2, | |
2073 | VEX_W_0FEF_P_2, | |
2074 | VEX_W_0FF0_P_3_M_0, | |
2075 | VEX_W_0FF1_P_2, | |
2076 | VEX_W_0FF2_P_2, | |
2077 | VEX_W_0FF3_P_2, | |
2078 | VEX_W_0FF4_P_2, | |
2079 | VEX_W_0FF5_P_2, | |
2080 | VEX_W_0FF6_P_2, | |
2081 | VEX_W_0FF7_P_2, | |
2082 | VEX_W_0FF8_P_2, | |
2083 | VEX_W_0FF9_P_2, | |
2084 | VEX_W_0FFA_P_2, | |
2085 | VEX_W_0FFB_P_2, | |
2086 | VEX_W_0FFC_P_2, | |
2087 | VEX_W_0FFD_P_2, | |
2088 | VEX_W_0FFE_P_2, | |
2089 | VEX_W_0F3800_P_2, | |
2090 | VEX_W_0F3801_P_2, | |
2091 | VEX_W_0F3802_P_2, | |
2092 | VEX_W_0F3803_P_2, | |
2093 | VEX_W_0F3804_P_2, | |
2094 | VEX_W_0F3805_P_2, | |
2095 | VEX_W_0F3806_P_2, | |
2096 | VEX_W_0F3807_P_2, | |
2097 | VEX_W_0F3808_P_2, | |
2098 | VEX_W_0F3809_P_2, | |
2099 | VEX_W_0F380A_P_2, | |
2100 | VEX_W_0F380B_P_2, | |
2101 | VEX_W_0F380C_P_2, | |
2102 | VEX_W_0F380D_P_2, | |
2103 | VEX_W_0F380E_P_2, | |
2104 | VEX_W_0F380F_P_2, | |
6c30d220 | 2105 | VEX_W_0F3816_P_2, |
592a252b | 2106 | VEX_W_0F3817_P_2, |
6c30d220 L |
2107 | VEX_W_0F3818_P_2, |
2108 | VEX_W_0F3819_P_2, | |
592a252b L |
2109 | VEX_W_0F381A_P_2_M_0, |
2110 | VEX_W_0F381C_P_2, | |
2111 | VEX_W_0F381D_P_2, | |
2112 | VEX_W_0F381E_P_2, | |
2113 | VEX_W_0F3820_P_2, | |
2114 | VEX_W_0F3821_P_2, | |
2115 | VEX_W_0F3822_P_2, | |
2116 | VEX_W_0F3823_P_2, | |
2117 | VEX_W_0F3824_P_2, | |
2118 | VEX_W_0F3825_P_2, | |
2119 | VEX_W_0F3828_P_2, | |
2120 | VEX_W_0F3829_P_2, | |
2121 | VEX_W_0F382A_P_2_M_0, | |
2122 | VEX_W_0F382B_P_2, | |
2123 | VEX_W_0F382C_P_2_M_0, | |
2124 | VEX_W_0F382D_P_2_M_0, | |
2125 | VEX_W_0F382E_P_2_M_0, | |
2126 | VEX_W_0F382F_P_2_M_0, | |
2127 | VEX_W_0F3830_P_2, | |
2128 | VEX_W_0F3831_P_2, | |
2129 | VEX_W_0F3832_P_2, | |
2130 | VEX_W_0F3833_P_2, | |
2131 | VEX_W_0F3834_P_2, | |
2132 | VEX_W_0F3835_P_2, | |
6c30d220 | 2133 | VEX_W_0F3836_P_2, |
592a252b L |
2134 | VEX_W_0F3837_P_2, |
2135 | VEX_W_0F3838_P_2, | |
2136 | VEX_W_0F3839_P_2, | |
2137 | VEX_W_0F383A_P_2, | |
2138 | VEX_W_0F383B_P_2, | |
2139 | VEX_W_0F383C_P_2, | |
2140 | VEX_W_0F383D_P_2, | |
2141 | VEX_W_0F383E_P_2, | |
2142 | VEX_W_0F383F_P_2, | |
2143 | VEX_W_0F3840_P_2, | |
2144 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2145 | VEX_W_0F3846_P_2, |
2146 | VEX_W_0F3858_P_2, | |
2147 | VEX_W_0F3859_P_2, | |
2148 | VEX_W_0F385A_P_2_M_0, | |
2149 | VEX_W_0F3878_P_2, | |
2150 | VEX_W_0F3879_P_2, | |
592a252b L |
2151 | VEX_W_0F38DB_P_2, |
2152 | VEX_W_0F38DC_P_2, | |
2153 | VEX_W_0F38DD_P_2, | |
2154 | VEX_W_0F38DE_P_2, | |
2155 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2156 | VEX_W_0F3A00_P_2, |
2157 | VEX_W_0F3A01_P_2, | |
2158 | VEX_W_0F3A02_P_2, | |
592a252b L |
2159 | VEX_W_0F3A04_P_2, |
2160 | VEX_W_0F3A05_P_2, | |
2161 | VEX_W_0F3A06_P_2, | |
2162 | VEX_W_0F3A08_P_2, | |
2163 | VEX_W_0F3A09_P_2, | |
2164 | VEX_W_0F3A0A_P_2, | |
2165 | VEX_W_0F3A0B_P_2, | |
2166 | VEX_W_0F3A0C_P_2, | |
2167 | VEX_W_0F3A0D_P_2, | |
2168 | VEX_W_0F3A0E_P_2, | |
2169 | VEX_W_0F3A0F_P_2, | |
2170 | VEX_W_0F3A14_P_2, | |
2171 | VEX_W_0F3A15_P_2, | |
2172 | VEX_W_0F3A18_P_2, | |
2173 | VEX_W_0F3A19_P_2, | |
2174 | VEX_W_0F3A20_P_2, | |
2175 | VEX_W_0F3A21_P_2, | |
43234a1e | 2176 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2177 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2178 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2179 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2180 | VEX_W_0F3A38_P_2, |
2181 | VEX_W_0F3A39_P_2, | |
592a252b L |
2182 | VEX_W_0F3A40_P_2, |
2183 | VEX_W_0F3A41_P_2, | |
2184 | VEX_W_0F3A42_P_2, | |
2185 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2186 | VEX_W_0F3A46_P_2, |
592a252b L |
2187 | VEX_W_0F3A48_P_2, |
2188 | VEX_W_0F3A49_P_2, | |
2189 | VEX_W_0F3A4A_P_2, | |
2190 | VEX_W_0F3A4B_P_2, | |
2191 | VEX_W_0F3A4C_P_2, | |
2192 | VEX_W_0F3A60_P_2, | |
2193 | VEX_W_0F3A61_P_2, | |
2194 | VEX_W_0F3A62_P_2, | |
2195 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2196 | VEX_W_0F3ADF_P_2, |
2197 | ||
2198 | EVEX_W_0F10_P_0, | |
2199 | EVEX_W_0F10_P_1_M_0, | |
2200 | EVEX_W_0F10_P_1_M_1, | |
2201 | EVEX_W_0F10_P_2, | |
2202 | EVEX_W_0F10_P_3_M_0, | |
2203 | EVEX_W_0F10_P_3_M_1, | |
2204 | EVEX_W_0F11_P_0, | |
2205 | EVEX_W_0F11_P_1_M_0, | |
2206 | EVEX_W_0F11_P_1_M_1, | |
2207 | EVEX_W_0F11_P_2, | |
2208 | EVEX_W_0F11_P_3_M_0, | |
2209 | EVEX_W_0F11_P_3_M_1, | |
2210 | EVEX_W_0F12_P_0_M_0, | |
2211 | EVEX_W_0F12_P_0_M_1, | |
2212 | EVEX_W_0F12_P_1, | |
2213 | EVEX_W_0F12_P_2, | |
2214 | EVEX_W_0F12_P_3, | |
2215 | EVEX_W_0F13_P_0, | |
2216 | EVEX_W_0F13_P_2, | |
2217 | EVEX_W_0F14_P_0, | |
2218 | EVEX_W_0F14_P_2, | |
2219 | EVEX_W_0F15_P_0, | |
2220 | EVEX_W_0F15_P_2, | |
2221 | EVEX_W_0F16_P_0_M_0, | |
2222 | EVEX_W_0F16_P_0_M_1, | |
2223 | EVEX_W_0F16_P_1, | |
2224 | EVEX_W_0F16_P_2, | |
2225 | EVEX_W_0F17_P_0, | |
2226 | EVEX_W_0F17_P_2, | |
2227 | EVEX_W_0F28_P_0, | |
2228 | EVEX_W_0F28_P_2, | |
2229 | EVEX_W_0F29_P_0, | |
2230 | EVEX_W_0F29_P_2, | |
2231 | EVEX_W_0F2A_P_1, | |
2232 | EVEX_W_0F2A_P_3, | |
2233 | EVEX_W_0F2B_P_0, | |
2234 | EVEX_W_0F2B_P_2, | |
2235 | EVEX_W_0F2E_P_0, | |
2236 | EVEX_W_0F2E_P_2, | |
2237 | EVEX_W_0F2F_P_0, | |
2238 | EVEX_W_0F2F_P_2, | |
2239 | EVEX_W_0F51_P_0, | |
2240 | EVEX_W_0F51_P_1, | |
2241 | EVEX_W_0F51_P_2, | |
2242 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2243 | EVEX_W_0F54_P_0, |
2244 | EVEX_W_0F54_P_2, | |
2245 | EVEX_W_0F55_P_0, | |
2246 | EVEX_W_0F55_P_2, | |
2247 | EVEX_W_0F56_P_0, | |
2248 | EVEX_W_0F56_P_2, | |
2249 | EVEX_W_0F57_P_0, | |
2250 | EVEX_W_0F57_P_2, | |
43234a1e L |
2251 | EVEX_W_0F58_P_0, |
2252 | EVEX_W_0F58_P_1, | |
2253 | EVEX_W_0F58_P_2, | |
2254 | EVEX_W_0F58_P_3, | |
2255 | EVEX_W_0F59_P_0, | |
2256 | EVEX_W_0F59_P_1, | |
2257 | EVEX_W_0F59_P_2, | |
2258 | EVEX_W_0F59_P_3, | |
2259 | EVEX_W_0F5A_P_0, | |
2260 | EVEX_W_0F5A_P_1, | |
2261 | EVEX_W_0F5A_P_2, | |
2262 | EVEX_W_0F5A_P_3, | |
2263 | EVEX_W_0F5B_P_0, | |
2264 | EVEX_W_0F5B_P_1, | |
2265 | EVEX_W_0F5B_P_2, | |
2266 | EVEX_W_0F5C_P_0, | |
2267 | EVEX_W_0F5C_P_1, | |
2268 | EVEX_W_0F5C_P_2, | |
2269 | EVEX_W_0F5C_P_3, | |
2270 | EVEX_W_0F5D_P_0, | |
2271 | EVEX_W_0F5D_P_1, | |
2272 | EVEX_W_0F5D_P_2, | |
2273 | EVEX_W_0F5D_P_3, | |
2274 | EVEX_W_0F5E_P_0, | |
2275 | EVEX_W_0F5E_P_1, | |
2276 | EVEX_W_0F5E_P_2, | |
2277 | EVEX_W_0F5E_P_3, | |
2278 | EVEX_W_0F5F_P_0, | |
2279 | EVEX_W_0F5F_P_1, | |
2280 | EVEX_W_0F5F_P_2, | |
2281 | EVEX_W_0F5F_P_3, | |
2282 | EVEX_W_0F62_P_2, | |
2283 | EVEX_W_0F66_P_2, | |
2284 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2285 | EVEX_W_0F6B_P_2, |
43234a1e L |
2286 | EVEX_W_0F6C_P_2, |
2287 | EVEX_W_0F6D_P_2, | |
2288 | EVEX_W_0F6E_P_2, | |
2289 | EVEX_W_0F6F_P_1, | |
2290 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2291 | EVEX_W_0F6F_P_3, |
43234a1e L |
2292 | EVEX_W_0F70_P_2, |
2293 | EVEX_W_0F72_R_2_P_2, | |
2294 | EVEX_W_0F72_R_6_P_2, | |
2295 | EVEX_W_0F73_R_2_P_2, | |
2296 | EVEX_W_0F73_R_6_P_2, | |
2297 | EVEX_W_0F76_P_2, | |
2298 | EVEX_W_0F78_P_0, | |
90a915bf | 2299 | EVEX_W_0F78_P_2, |
43234a1e | 2300 | EVEX_W_0F79_P_0, |
90a915bf | 2301 | EVEX_W_0F79_P_2, |
43234a1e | 2302 | EVEX_W_0F7A_P_1, |
90a915bf | 2303 | EVEX_W_0F7A_P_2, |
43234a1e L |
2304 | EVEX_W_0F7A_P_3, |
2305 | EVEX_W_0F7B_P_1, | |
90a915bf | 2306 | EVEX_W_0F7B_P_2, |
43234a1e L |
2307 | EVEX_W_0F7B_P_3, |
2308 | EVEX_W_0F7E_P_1, | |
2309 | EVEX_W_0F7E_P_2, | |
2310 | EVEX_W_0F7F_P_1, | |
2311 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2312 | EVEX_W_0F7F_P_3, |
43234a1e L |
2313 | EVEX_W_0FC2_P_0, |
2314 | EVEX_W_0FC2_P_1, | |
2315 | EVEX_W_0FC2_P_2, | |
2316 | EVEX_W_0FC2_P_3, | |
2317 | EVEX_W_0FC6_P_0, | |
2318 | EVEX_W_0FC6_P_2, | |
2319 | EVEX_W_0FD2_P_2, | |
2320 | EVEX_W_0FD3_P_2, | |
2321 | EVEX_W_0FD4_P_2, | |
2322 | EVEX_W_0FD6_P_2, | |
2323 | EVEX_W_0FE6_P_1, | |
2324 | EVEX_W_0FE6_P_2, | |
2325 | EVEX_W_0FE6_P_3, | |
2326 | EVEX_W_0FE7_P_2, | |
2327 | EVEX_W_0FF2_P_2, | |
2328 | EVEX_W_0FF3_P_2, | |
2329 | EVEX_W_0FF4_P_2, | |
2330 | EVEX_W_0FFA_P_2, | |
2331 | EVEX_W_0FFB_P_2, | |
2332 | EVEX_W_0FFE_P_2, | |
2333 | EVEX_W_0F380C_P_2, | |
2334 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2335 | EVEX_W_0F3810_P_1, |
2336 | EVEX_W_0F3810_P_2, | |
43234a1e | 2337 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2338 | EVEX_W_0F3811_P_2, |
43234a1e | 2339 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2340 | EVEX_W_0F3812_P_2, |
43234a1e L |
2341 | EVEX_W_0F3813_P_1, |
2342 | EVEX_W_0F3813_P_2, | |
2343 | EVEX_W_0F3814_P_1, | |
2344 | EVEX_W_0F3815_P_1, | |
2345 | EVEX_W_0F3818_P_2, | |
2346 | EVEX_W_0F3819_P_2, | |
2347 | EVEX_W_0F381A_P_2, | |
2348 | EVEX_W_0F381B_P_2, | |
2349 | EVEX_W_0F381E_P_2, | |
2350 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2351 | EVEX_W_0F3820_P_1, |
43234a1e L |
2352 | EVEX_W_0F3821_P_1, |
2353 | EVEX_W_0F3822_P_1, | |
2354 | EVEX_W_0F3823_P_1, | |
2355 | EVEX_W_0F3824_P_1, | |
2356 | EVEX_W_0F3825_P_1, | |
2357 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2358 | EVEX_W_0F3826_P_1, |
2359 | EVEX_W_0F3826_P_2, | |
2360 | EVEX_W_0F3828_P_1, | |
43234a1e | 2361 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2362 | EVEX_W_0F3829_P_1, |
43234a1e L |
2363 | EVEX_W_0F3829_P_2, |
2364 | EVEX_W_0F382A_P_1, | |
2365 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2366 | EVEX_W_0F382B_P_2, |
2367 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2368 | EVEX_W_0F3831_P_1, |
2369 | EVEX_W_0F3832_P_1, | |
2370 | EVEX_W_0F3833_P_1, | |
2371 | EVEX_W_0F3834_P_1, | |
2372 | EVEX_W_0F3835_P_1, | |
2373 | EVEX_W_0F3835_P_2, | |
2374 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2375 | EVEX_W_0F3838_P_1, |
2376 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2377 | EVEX_W_0F383A_P_1, |
2378 | EVEX_W_0F3840_P_2, | |
2379 | EVEX_W_0F3858_P_2, | |
2380 | EVEX_W_0F3859_P_2, | |
2381 | EVEX_W_0F385A_P_2, | |
2382 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2383 | EVEX_W_0F3866_P_2, |
2384 | EVEX_W_0F3875_P_2, | |
2385 | EVEX_W_0F3878_P_2, | |
2386 | EVEX_W_0F3879_P_2, | |
2387 | EVEX_W_0F387A_P_2, | |
2388 | EVEX_W_0F387B_P_2, | |
2389 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2390 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2391 | EVEX_W_0F388D_P_2, |
43234a1e L |
2392 | EVEX_W_0F3891_P_2, |
2393 | EVEX_W_0F3893_P_2, | |
2394 | EVEX_W_0F38A1_P_2, | |
2395 | EVEX_W_0F38A3_P_2, | |
2396 | EVEX_W_0F38C7_R_1_P_2, | |
2397 | EVEX_W_0F38C7_R_2_P_2, | |
2398 | EVEX_W_0F38C7_R_5_P_2, | |
2399 | EVEX_W_0F38C7_R_6_P_2, | |
2400 | ||
2401 | EVEX_W_0F3A00_P_2, | |
2402 | EVEX_W_0F3A01_P_2, | |
2403 | EVEX_W_0F3A04_P_2, | |
2404 | EVEX_W_0F3A05_P_2, | |
2405 | EVEX_W_0F3A08_P_2, | |
2406 | EVEX_W_0F3A09_P_2, | |
2407 | EVEX_W_0F3A0A_P_2, | |
2408 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2409 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2410 | EVEX_W_0F3A18_P_2, |
2411 | EVEX_W_0F3A19_P_2, | |
2412 | EVEX_W_0F3A1A_P_2, | |
2413 | EVEX_W_0F3A1B_P_2, | |
2414 | EVEX_W_0F3A1D_P_2, | |
2415 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2416 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2417 | EVEX_W_0F3A23_P_2, |
2418 | EVEX_W_0F3A38_P_2, | |
2419 | EVEX_W_0F3A39_P_2, | |
2420 | EVEX_W_0F3A3A_P_2, | |
2421 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2422 | EVEX_W_0F3A3E_P_2, |
2423 | EVEX_W_0F3A3F_P_2, | |
2424 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2425 | EVEX_W_0F3A43_P_2, |
2426 | EVEX_W_0F3A50_P_2, | |
2427 | EVEX_W_0F3A51_P_2, | |
2428 | EVEX_W_0F3A56_P_2, | |
2429 | EVEX_W_0F3A57_P_2, | |
2430 | EVEX_W_0F3A66_P_2, | |
2431 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2432 | }; |
2433 | ||
26ca5450 | 2434 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2435 | |
2436 | struct dis386 { | |
2da11e11 | 2437 | const char *name; |
ce518a5f L |
2438 | struct |
2439 | { | |
2440 | op_rtn rtn; | |
2441 | int bytemode; | |
2442 | } op[MAX_OPERANDS]; | |
bf890a93 | 2443 | unsigned int prefix_requirement; |
252b5132 RH |
2444 | }; |
2445 | ||
2446 | /* Upper case letters in the instruction names here are macros. | |
2447 | 'A' => print 'b' if no register operands or suffix_always is true | |
2448 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2449 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2450 | size prefix |
ed7841b3 | 2451 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2452 | suffix_always is true |
252b5132 | 2453 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2454 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2455 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2456 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2457 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2458 | for some of the macro letters) |
9306ca4a | 2459 | 'J' => print 'l' |
42903f7f | 2460 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2461 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2462 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2463 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2464 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2465 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2466 | or suffix_always is true. print 'q' if rex prefix is present. |
2467 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2468 | is true | |
a35ca55a | 2469 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2470 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2471 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2472 | prefix and behave as 'P' otherwise | |
2473 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2474 | prefix and behave as 'Q' otherwise | |
2475 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2476 | prefix and behave as 'S' otherwise | |
a35ca55a | 2477 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2478 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2479 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2480 | suffix_always is true. | |
6dd5059a | 2481 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2482 | '!' => change condition from true to false or from false to true. |
98b528ac | 2483 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2484 | '^' => print 'w' or 'l' depending on operand size prefix or |
2485 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2486 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2487 | on operand size prefix. | |
07f5af7d L |
2488 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2489 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2490 | otherwise | |
98b528ac L |
2491 | |
2492 | 2 upper case letter macros: | |
04d824a4 JB |
2493 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2494 | operands and no broadcast. | |
2495 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2496 | register operands and no broadcast. | |
4b06377f L |
2497 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2498 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2499 | or suffix_always is true |
4b06377f L |
2500 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2501 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2502 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2503 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2504 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2505 | an operand size prefix, or suffix_always is true. print | |
2506 | 'q' if rex prefix is present. | |
52b15da3 | 2507 | |
6439fc28 AM |
2508 | Many of the above letters print nothing in Intel mode. See "putop" |
2509 | for the details. | |
52b15da3 | 2510 | |
6439fc28 | 2511 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2512 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2513 | |
6439fc28 | 2514 | static const struct dis386 dis386[] = { |
252b5132 | 2515 | /* 00 */ |
bf890a93 IT |
2516 | { "addB", { Ebh1, Gb }, 0 }, |
2517 | { "addS", { Evh1, Gv }, 0 }, | |
2518 | { "addB", { Gb, EbS }, 0 }, | |
2519 | { "addS", { Gv, EvS }, 0 }, | |
2520 | { "addB", { AL, Ib }, 0 }, | |
2521 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2522 | { X86_64_TABLE (X86_64_06) }, |
2523 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2524 | /* 08 */ |
bf890a93 IT |
2525 | { "orB", { Ebh1, Gb }, 0 }, |
2526 | { "orS", { Evh1, Gv }, 0 }, | |
2527 | { "orB", { Gb, EbS }, 0 }, | |
2528 | { "orS", { Gv, EvS }, 0 }, | |
2529 | { "orB", { AL, Ib }, 0 }, | |
2530 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2531 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2532 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2533 | /* 10 */ |
bf890a93 IT |
2534 | { "adcB", { Ebh1, Gb }, 0 }, |
2535 | { "adcS", { Evh1, Gv }, 0 }, | |
2536 | { "adcB", { Gb, EbS }, 0 }, | |
2537 | { "adcS", { Gv, EvS }, 0 }, | |
2538 | { "adcB", { AL, Ib }, 0 }, | |
2539 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2540 | { X86_64_TABLE (X86_64_16) }, |
2541 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2542 | /* 18 */ |
bf890a93 IT |
2543 | { "sbbB", { Ebh1, Gb }, 0 }, |
2544 | { "sbbS", { Evh1, Gv }, 0 }, | |
2545 | { "sbbB", { Gb, EbS }, 0 }, | |
2546 | { "sbbS", { Gv, EvS }, 0 }, | |
2547 | { "sbbB", { AL, Ib }, 0 }, | |
2548 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2549 | { X86_64_TABLE (X86_64_1E) }, |
2550 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2551 | /* 20 */ |
bf890a93 IT |
2552 | { "andB", { Ebh1, Gb }, 0 }, |
2553 | { "andS", { Evh1, Gv }, 0 }, | |
2554 | { "andB", { Gb, EbS }, 0 }, | |
2555 | { "andS", { Gv, EvS }, 0 }, | |
2556 | { "andB", { AL, Ib }, 0 }, | |
2557 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2558 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2559 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2560 | /* 28 */ |
bf890a93 IT |
2561 | { "subB", { Ebh1, Gb }, 0 }, |
2562 | { "subS", { Evh1, Gv }, 0 }, | |
2563 | { "subB", { Gb, EbS }, 0 }, | |
2564 | { "subS", { Gv, EvS }, 0 }, | |
2565 | { "subB", { AL, Ib }, 0 }, | |
2566 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2567 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2568 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2569 | /* 30 */ |
bf890a93 IT |
2570 | { "xorB", { Ebh1, Gb }, 0 }, |
2571 | { "xorS", { Evh1, Gv }, 0 }, | |
2572 | { "xorB", { Gb, EbS }, 0 }, | |
2573 | { "xorS", { Gv, EvS }, 0 }, | |
2574 | { "xorB", { AL, Ib }, 0 }, | |
2575 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2576 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2577 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2578 | /* 38 */ |
bf890a93 IT |
2579 | { "cmpB", { Eb, Gb }, 0 }, |
2580 | { "cmpS", { Ev, Gv }, 0 }, | |
2581 | { "cmpB", { Gb, EbS }, 0 }, | |
2582 | { "cmpS", { Gv, EvS }, 0 }, | |
2583 | { "cmpB", { AL, Ib }, 0 }, | |
2584 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2585 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2586 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2587 | /* 40 */ |
bf890a93 IT |
2588 | { "inc{S|}", { RMeAX }, 0 }, |
2589 | { "inc{S|}", { RMeCX }, 0 }, | |
2590 | { "inc{S|}", { RMeDX }, 0 }, | |
2591 | { "inc{S|}", { RMeBX }, 0 }, | |
2592 | { "inc{S|}", { RMeSP }, 0 }, | |
2593 | { "inc{S|}", { RMeBP }, 0 }, | |
2594 | { "inc{S|}", { RMeSI }, 0 }, | |
2595 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2596 | /* 48 */ |
bf890a93 IT |
2597 | { "dec{S|}", { RMeAX }, 0 }, |
2598 | { "dec{S|}", { RMeCX }, 0 }, | |
2599 | { "dec{S|}", { RMeDX }, 0 }, | |
2600 | { "dec{S|}", { RMeBX }, 0 }, | |
2601 | { "dec{S|}", { RMeSP }, 0 }, | |
2602 | { "dec{S|}", { RMeBP }, 0 }, | |
2603 | { "dec{S|}", { RMeSI }, 0 }, | |
2604 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2605 | /* 50 */ |
bf890a93 IT |
2606 | { "pushV", { RMrAX }, 0 }, |
2607 | { "pushV", { RMrCX }, 0 }, | |
2608 | { "pushV", { RMrDX }, 0 }, | |
2609 | { "pushV", { RMrBX }, 0 }, | |
2610 | { "pushV", { RMrSP }, 0 }, | |
2611 | { "pushV", { RMrBP }, 0 }, | |
2612 | { "pushV", { RMrSI }, 0 }, | |
2613 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2614 | /* 58 */ |
bf890a93 IT |
2615 | { "popV", { RMrAX }, 0 }, |
2616 | { "popV", { RMrCX }, 0 }, | |
2617 | { "popV", { RMrDX }, 0 }, | |
2618 | { "popV", { RMrBX }, 0 }, | |
2619 | { "popV", { RMrSP }, 0 }, | |
2620 | { "popV", { RMrBP }, 0 }, | |
2621 | { "popV", { RMrSI }, 0 }, | |
2622 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2623 | /* 60 */ |
4e7d34a6 L |
2624 | { X86_64_TABLE (X86_64_60) }, |
2625 | { X86_64_TABLE (X86_64_61) }, | |
2626 | { X86_64_TABLE (X86_64_62) }, | |
2627 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2628 | { Bad_Opcode }, /* seg fs */ |
2629 | { Bad_Opcode }, /* seg gs */ | |
2630 | { Bad_Opcode }, /* op size prefix */ | |
2631 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2632 | /* 68 */ |
bf890a93 IT |
2633 | { "pushT", { sIv }, 0 }, |
2634 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2635 | { "pushT", { sIbT }, 0 }, | |
2636 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2637 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2638 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2639 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2640 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2641 | /* 70 */ |
bf890a93 IT |
2642 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2643 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2644 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2645 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2646 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2647 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2648 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2649 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2650 | /* 78 */ |
bf890a93 IT |
2651 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2652 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2653 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2654 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2655 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2656 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2657 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2658 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2659 | /* 80 */ |
1ceb70f8 L |
2660 | { REG_TABLE (REG_80) }, |
2661 | { REG_TABLE (REG_81) }, | |
592d1631 | 2662 | { Bad_Opcode }, |
1ceb70f8 | 2663 | { REG_TABLE (REG_82) }, |
bf890a93 IT |
2664 | { "testB", { Eb, Gb }, 0 }, |
2665 | { "testS", { Ev, Gv }, 0 }, | |
2666 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2667 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2668 | /* 88 */ |
bf890a93 IT |
2669 | { "movB", { Ebh3, Gb }, 0 }, |
2670 | { "movS", { Evh3, Gv }, 0 }, | |
2671 | { "movB", { Gb, EbS }, 0 }, | |
2672 | { "movS", { Gv, EvS }, 0 }, | |
2673 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2674 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2675 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2676 | { REG_TABLE (REG_8F) }, |
252b5132 | 2677 | /* 90 */ |
1ceb70f8 | 2678 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2679 | { "xchgS", { RMeCX, eAX }, 0 }, |
2680 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2681 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2682 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2683 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2684 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2685 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2686 | /* 98 */ |
bf890a93 IT |
2687 | { "cW{t|}R", { XX }, 0 }, |
2688 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2689 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2690 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2691 | { "pushfT", { XX }, 0 }, |
2692 | { "popfT", { XX }, 0 }, | |
2693 | { "sahf", { XX }, 0 }, | |
2694 | { "lahf", { XX }, 0 }, | |
252b5132 | 2695 | /* a0 */ |
bf890a93 IT |
2696 | { "mov%LB", { AL, Ob }, 0 }, |
2697 | { "mov%LS", { eAX, Ov }, 0 }, | |
2698 | { "mov%LB", { Ob, AL }, 0 }, | |
2699 | { "mov%LS", { Ov, eAX }, 0 }, | |
2700 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2701 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2702 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2703 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2704 | /* a8 */ |
bf890a93 IT |
2705 | { "testB", { AL, Ib }, 0 }, |
2706 | { "testS", { eAX, Iv }, 0 }, | |
2707 | { "stosB", { Ybr, AL }, 0 }, | |
2708 | { "stosS", { Yvr, eAX }, 0 }, | |
2709 | { "lodsB", { ALr, Xb }, 0 }, | |
2710 | { "lodsS", { eAXr, Xv }, 0 }, | |
2711 | { "scasB", { AL, Yb }, 0 }, | |
2712 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2713 | /* b0 */ |
bf890a93 IT |
2714 | { "movB", { RMAL, Ib }, 0 }, |
2715 | { "movB", { RMCL, Ib }, 0 }, | |
2716 | { "movB", { RMDL, Ib }, 0 }, | |
2717 | { "movB", { RMBL, Ib }, 0 }, | |
2718 | { "movB", { RMAH, Ib }, 0 }, | |
2719 | { "movB", { RMCH, Ib }, 0 }, | |
2720 | { "movB", { RMDH, Ib }, 0 }, | |
2721 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2722 | /* b8 */ |
bf890a93 IT |
2723 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2724 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2725 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2726 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2727 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2728 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2729 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2730 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2731 | /* c0 */ |
1ceb70f8 L |
2732 | { REG_TABLE (REG_C0) }, |
2733 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2734 | { "retT", { Iw, BND }, 0 }, |
2735 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2736 | { X86_64_TABLE (X86_64_C4) }, |
2737 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2738 | { REG_TABLE (REG_C6) }, |
2739 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2740 | /* c8 */ |
bf890a93 IT |
2741 | { "enterT", { Iw, Ib }, 0 }, |
2742 | { "leaveT", { XX }, 0 }, | |
2743 | { "Jret{|f}P", { Iw }, 0 }, | |
2744 | { "Jret{|f}P", { XX }, 0 }, | |
2745 | { "int3", { XX }, 0 }, | |
2746 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2747 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2748 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2749 | /* d0 */ |
1ceb70f8 L |
2750 | { REG_TABLE (REG_D0) }, |
2751 | { REG_TABLE (REG_D1) }, | |
2752 | { REG_TABLE (REG_D2) }, | |
2753 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2754 | { X86_64_TABLE (X86_64_D4) }, |
2755 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2756 | { Bad_Opcode }, |
bf890a93 | 2757 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2758 | /* d8 */ |
2759 | { FLOAT }, | |
2760 | { FLOAT }, | |
2761 | { FLOAT }, | |
2762 | { FLOAT }, | |
2763 | { FLOAT }, | |
2764 | { FLOAT }, | |
2765 | { FLOAT }, | |
2766 | { FLOAT }, | |
2767 | /* e0 */ | |
bf890a93 IT |
2768 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2769 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2770 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2771 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2772 | { "inB", { AL, Ib }, 0 }, | |
2773 | { "inG", { zAX, Ib }, 0 }, | |
2774 | { "outB", { Ib, AL }, 0 }, | |
2775 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2776 | /* e8 */ |
a72d2af2 L |
2777 | { X86_64_TABLE (X86_64_E8) }, |
2778 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2779 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2780 | { "jmp", { Jb, BND }, 0 }, |
2781 | { "inB", { AL, indirDX }, 0 }, | |
2782 | { "inG", { zAX, indirDX }, 0 }, | |
2783 | { "outB", { indirDX, AL }, 0 }, | |
2784 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2785 | /* f0 */ |
592d1631 | 2786 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2787 | { "icebp", { XX }, 0 }, |
592d1631 L |
2788 | { Bad_Opcode }, /* repne */ |
2789 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2790 | { "hlt", { XX }, 0 }, |
2791 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2792 | { REG_TABLE (REG_F6) }, |
2793 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2794 | /* f8 */ |
bf890a93 IT |
2795 | { "clc", { XX }, 0 }, |
2796 | { "stc", { XX }, 0 }, | |
2797 | { "cli", { XX }, 0 }, | |
2798 | { "sti", { XX }, 0 }, | |
2799 | { "cld", { XX }, 0 }, | |
2800 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2801 | { REG_TABLE (REG_FE) }, |
2802 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2803 | }; |
2804 | ||
6439fc28 | 2805 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2806 | /* 00 */ |
1ceb70f8 L |
2807 | { REG_TABLE (REG_0F00 ) }, |
2808 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2809 | { "larS", { Gv, Ew }, 0 }, |
2810 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2811 | { Bad_Opcode }, |
bf890a93 IT |
2812 | { "syscall", { XX }, 0 }, |
2813 | { "clts", { XX }, 0 }, | |
2814 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2815 | /* 08 */ |
bf890a93 IT |
2816 | { "invd", { XX }, 0 }, |
2817 | { "wbinvd", { XX }, 0 }, | |
592d1631 | 2818 | { Bad_Opcode }, |
bf890a93 | 2819 | { "ud2", { XX }, 0 }, |
592d1631 | 2820 | { Bad_Opcode }, |
b5b1fc4f | 2821 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2822 | { "femms", { XX }, 0 }, |
2823 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2824 | /* 10 */ |
1ceb70f8 L |
2825 | { PREFIX_TABLE (PREFIX_0F10) }, |
2826 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2827 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2828 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2829 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2830 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2831 | { PREFIX_TABLE (PREFIX_0F16) }, |
2832 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2833 | /* 18 */ |
1ceb70f8 | 2834 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2835 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2836 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2837 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2838 | { "nopQ", { Ev }, 0 }, |
2839 | { "nopQ", { Ev }, 0 }, | |
2840 | { "nopQ", { Ev }, 0 }, | |
2841 | { "nopQ", { Ev }, 0 }, | |
252b5132 | 2842 | /* 20 */ |
bf890a93 IT |
2843 | { "movZ", { Rm, Cm }, 0 }, |
2844 | { "movZ", { Rm, Dm }, 0 }, | |
2845 | { "movZ", { Cm, Rm }, 0 }, | |
2846 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2847 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2848 | { Bad_Opcode }, |
1ceb70f8 | 2849 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2850 | { Bad_Opcode }, |
252b5132 | 2851 | /* 28 */ |
507bd325 L |
2852 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2853 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2854 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2855 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2856 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2857 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2858 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2859 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2860 | /* 30 */ |
bf890a93 IT |
2861 | { "wrmsr", { XX }, 0 }, |
2862 | { "rdtsc", { XX }, 0 }, | |
2863 | { "rdmsr", { XX }, 0 }, | |
2864 | { "rdpmc", { XX }, 0 }, | |
2865 | { "sysenter", { XX }, 0 }, | |
2866 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2867 | { Bad_Opcode }, |
bf890a93 | 2868 | { "getsec", { XX }, 0 }, |
252b5132 | 2869 | /* 38 */ |
507bd325 | 2870 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2871 | { Bad_Opcode }, |
507bd325 | 2872 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2873 | { Bad_Opcode }, |
2874 | { Bad_Opcode }, | |
2875 | { Bad_Opcode }, | |
2876 | { Bad_Opcode }, | |
2877 | { Bad_Opcode }, | |
252b5132 | 2878 | /* 40 */ |
bf890a93 IT |
2879 | { "cmovoS", { Gv, Ev }, 0 }, |
2880 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2881 | { "cmovbS", { Gv, Ev }, 0 }, | |
2882 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2883 | { "cmoveS", { Gv, Ev }, 0 }, | |
2884 | { "cmovneS", { Gv, Ev }, 0 }, | |
2885 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2886 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2887 | /* 48 */ |
bf890a93 IT |
2888 | { "cmovsS", { Gv, Ev }, 0 }, |
2889 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2890 | { "cmovpS", { Gv, Ev }, 0 }, | |
2891 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2892 | { "cmovlS", { Gv, Ev }, 0 }, | |
2893 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2894 | { "cmovleS", { Gv, Ev }, 0 }, | |
2895 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2896 | /* 50 */ |
75c135a8 | 2897 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2898 | { PREFIX_TABLE (PREFIX_0F51) }, |
2899 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2900 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2901 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2902 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2903 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2904 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2905 | /* 58 */ |
1ceb70f8 L |
2906 | { PREFIX_TABLE (PREFIX_0F58) }, |
2907 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2908 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2909 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2910 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2911 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2912 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2913 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2914 | /* 60 */ |
1ceb70f8 L |
2915 | { PREFIX_TABLE (PREFIX_0F60) }, |
2916 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2917 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2918 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2919 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2920 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2921 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2922 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2923 | /* 68 */ |
507bd325 L |
2924 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2925 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2926 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2927 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2928 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2929 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2930 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2931 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2932 | /* 70 */ |
1ceb70f8 L |
2933 | { PREFIX_TABLE (PREFIX_0F70) }, |
2934 | { REG_TABLE (REG_0F71) }, | |
2935 | { REG_TABLE (REG_0F72) }, | |
2936 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2937 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2938 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2939 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2940 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2941 | /* 78 */ |
1ceb70f8 L |
2942 | { PREFIX_TABLE (PREFIX_0F78) }, |
2943 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2944 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2945 | { Bad_Opcode }, |
1ceb70f8 L |
2946 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2947 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2948 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2949 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2950 | /* 80 */ |
bf890a93 IT |
2951 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2952 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2953 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2954 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2955 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2956 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2957 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2958 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2959 | /* 88 */ |
bf890a93 IT |
2960 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2961 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2962 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2963 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2964 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2965 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2966 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2967 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2968 | /* 90 */ |
bf890a93 IT |
2969 | { "seto", { Eb }, 0 }, |
2970 | { "setno", { Eb }, 0 }, | |
2971 | { "setb", { Eb }, 0 }, | |
2972 | { "setae", { Eb }, 0 }, | |
2973 | { "sete", { Eb }, 0 }, | |
2974 | { "setne", { Eb }, 0 }, | |
2975 | { "setbe", { Eb }, 0 }, | |
2976 | { "seta", { Eb }, 0 }, | |
252b5132 | 2977 | /* 98 */ |
bf890a93 IT |
2978 | { "sets", { Eb }, 0 }, |
2979 | { "setns", { Eb }, 0 }, | |
2980 | { "setp", { Eb }, 0 }, | |
2981 | { "setnp", { Eb }, 0 }, | |
2982 | { "setl", { Eb }, 0 }, | |
2983 | { "setge", { Eb }, 0 }, | |
2984 | { "setle", { Eb }, 0 }, | |
2985 | { "setg", { Eb }, 0 }, | |
252b5132 | 2986 | /* a0 */ |
bf890a93 IT |
2987 | { "pushT", { fs }, 0 }, |
2988 | { "popT", { fs }, 0 }, | |
2989 | { "cpuid", { XX }, 0 }, | |
2990 | { "btS", { Ev, Gv }, 0 }, | |
2991 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2992 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2993 | { REG_TABLE (REG_0FA6) }, |
2994 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2995 | /* a8 */ |
bf890a93 IT |
2996 | { "pushT", { gs }, 0 }, |
2997 | { "popT", { gs }, 0 }, | |
2998 | { "rsm", { XX }, 0 }, | |
2999 | { "btsS", { Evh1, Gv }, 0 }, | |
3000 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3001 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3002 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3003 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3004 | /* b0 */ |
bf890a93 IT |
3005 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3006 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3007 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3008 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3009 | { MOD_TABLE (MOD_0FB4) }, |
3010 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3011 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3012 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3013 | /* b8 */ |
1ceb70f8 | 3014 | { PREFIX_TABLE (PREFIX_0FB8) }, |
bf890a93 | 3015 | { "ud1", { XX }, 0 }, |
1ceb70f8 | 3016 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3017 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3018 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3019 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3020 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3021 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3022 | /* c0 */ |
bf890a93 IT |
3023 | { "xaddB", { Ebh1, Gb }, 0 }, |
3024 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3025 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3026 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3027 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3028 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3029 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3030 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3031 | /* c8 */ |
bf890a93 IT |
3032 | { "bswap", { RMeAX }, 0 }, |
3033 | { "bswap", { RMeCX }, 0 }, | |
3034 | { "bswap", { RMeDX }, 0 }, | |
3035 | { "bswap", { RMeBX }, 0 }, | |
3036 | { "bswap", { RMeSP }, 0 }, | |
3037 | { "bswap", { RMeBP }, 0 }, | |
3038 | { "bswap", { RMeSI }, 0 }, | |
3039 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3040 | /* d0 */ |
1ceb70f8 | 3041 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3042 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3043 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3044 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3045 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3046 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3047 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3048 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3049 | /* d8 */ |
507bd325 L |
3050 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3051 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3052 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3053 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3054 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3055 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3056 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3057 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3058 | /* e0 */ |
507bd325 L |
3059 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3060 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3061 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3062 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3063 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3064 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3065 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3066 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3067 | /* e8 */ |
507bd325 L |
3068 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3069 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3070 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3071 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3072 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3073 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3074 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3075 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3076 | /* f0 */ |
1ceb70f8 | 3077 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3078 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3079 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3080 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3081 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3082 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3083 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3084 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3085 | /* f8 */ |
507bd325 L |
3086 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3087 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3088 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3089 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3090 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3091 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3092 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 3093 | { Bad_Opcode }, |
252b5132 RH |
3094 | }; |
3095 | ||
3096 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3097 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3098 | /* ------------------------------- */ | |
3099 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3100 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3101 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3102 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3103 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3104 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3105 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3106 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3107 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3108 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3109 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3110 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3111 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3112 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3113 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3114 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3115 | /* ------------------------------- */ | |
3116 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3117 | }; |
3118 | ||
3119 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3120 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3121 | /* ------------------------------- */ | |
252b5132 | 3122 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3123 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3124 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3125 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3126 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3127 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3128 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3129 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3130 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3131 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3132 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3133 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3134 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3135 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3136 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3137 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3138 | /* ------------------------------- */ |
3139 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3140 | }; | |
3141 | ||
252b5132 RH |
3142 | static char obuf[100]; |
3143 | static char *obufp; | |
ea397f5b | 3144 | static char *mnemonicendp; |
252b5132 RH |
3145 | static char scratchbuf[100]; |
3146 | static unsigned char *start_codep; | |
3147 | static unsigned char *insn_codep; | |
3148 | static unsigned char *codep; | |
285ca992 | 3149 | static unsigned char *end_codep; |
f16cd0d5 L |
3150 | static int last_lock_prefix; |
3151 | static int last_repz_prefix; | |
3152 | static int last_repnz_prefix; | |
3153 | static int last_data_prefix; | |
3154 | static int last_addr_prefix; | |
3155 | static int last_rex_prefix; | |
3156 | static int last_seg_prefix; | |
d9949a36 | 3157 | static int fwait_prefix; |
285ca992 L |
3158 | /* The active segment register prefix. */ |
3159 | static int active_seg_prefix; | |
f16cd0d5 L |
3160 | #define MAX_CODE_LENGTH 15 |
3161 | /* We can up to 14 prefixes since the maximum instruction length is | |
3162 | 15bytes. */ | |
3163 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3164 | static disassemble_info *the_info; |
7967e09e L |
3165 | static struct |
3166 | { | |
3167 | int mod; | |
7967e09e | 3168 | int reg; |
484c222e | 3169 | int rm; |
7967e09e L |
3170 | } |
3171 | modrm; | |
4bba6815 | 3172 | static unsigned char need_modrm; |
dfc8cf43 L |
3173 | static struct |
3174 | { | |
3175 | int scale; | |
3176 | int index; | |
3177 | int base; | |
3178 | } | |
3179 | sib; | |
c0f3af97 L |
3180 | static struct |
3181 | { | |
3182 | int register_specifier; | |
3183 | int length; | |
3184 | int prefix; | |
3185 | int w; | |
43234a1e L |
3186 | int evex; |
3187 | int r; | |
3188 | int v; | |
3189 | int mask_register_specifier; | |
3190 | int zeroing; | |
3191 | int ll; | |
3192 | int b; | |
c0f3af97 L |
3193 | } |
3194 | vex; | |
3195 | static unsigned char need_vex; | |
3196 | static unsigned char need_vex_reg; | |
dae39acc | 3197 | static unsigned char vex_w_done; |
252b5132 | 3198 | |
ea397f5b L |
3199 | struct op |
3200 | { | |
3201 | const char *name; | |
3202 | unsigned int len; | |
3203 | }; | |
3204 | ||
4bba6815 AM |
3205 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3206 | values are stale. Hitting this abort likely indicates that you | |
3207 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3208 | #define MODRM_CHECK if (!need_modrm) abort () | |
3209 | ||
d708bcba AM |
3210 | static const char **names64; |
3211 | static const char **names32; | |
3212 | static const char **names16; | |
3213 | static const char **names8; | |
3214 | static const char **names8rex; | |
3215 | static const char **names_seg; | |
db51cc60 L |
3216 | static const char *index64; |
3217 | static const char *index32; | |
d708bcba | 3218 | static const char **index16; |
7e8b059b | 3219 | static const char **names_bnd; |
d708bcba AM |
3220 | |
3221 | static const char *intel_names64[] = { | |
3222 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3223 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3224 | }; | |
3225 | static const char *intel_names32[] = { | |
3226 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3227 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3228 | }; | |
3229 | static const char *intel_names16[] = { | |
3230 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3231 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3232 | }; | |
3233 | static const char *intel_names8[] = { | |
3234 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3235 | }; | |
3236 | static const char *intel_names8rex[] = { | |
3237 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3238 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3239 | }; | |
3240 | static const char *intel_names_seg[] = { | |
3241 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3242 | }; | |
db51cc60 L |
3243 | static const char *intel_index64 = "riz"; |
3244 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3245 | static const char *intel_index16[] = { |
3246 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3247 | }; | |
3248 | ||
3249 | static const char *att_names64[] = { | |
3250 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3251 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3252 | }; | |
d708bcba AM |
3253 | static const char *att_names32[] = { |
3254 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3255 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3256 | }; |
d708bcba AM |
3257 | static const char *att_names16[] = { |
3258 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3259 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3260 | }; |
d708bcba AM |
3261 | static const char *att_names8[] = { |
3262 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3263 | }; |
d708bcba AM |
3264 | static const char *att_names8rex[] = { |
3265 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3266 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3267 | }; | |
d708bcba AM |
3268 | static const char *att_names_seg[] = { |
3269 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3270 | }; |
db51cc60 L |
3271 | static const char *att_index64 = "%riz"; |
3272 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3273 | static const char *att_index16[] = { |
3274 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3275 | }; |
3276 | ||
b9733481 L |
3277 | static const char **names_mm; |
3278 | static const char *intel_names_mm[] = { | |
3279 | "mm0", "mm1", "mm2", "mm3", | |
3280 | "mm4", "mm5", "mm6", "mm7" | |
3281 | }; | |
3282 | static const char *att_names_mm[] = { | |
3283 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3284 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3285 | }; | |
3286 | ||
7e8b059b L |
3287 | static const char *intel_names_bnd[] = { |
3288 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3289 | }; | |
3290 | ||
3291 | static const char *att_names_bnd[] = { | |
3292 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3293 | }; | |
3294 | ||
b9733481 L |
3295 | static const char **names_xmm; |
3296 | static const char *intel_names_xmm[] = { | |
3297 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3298 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3299 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3300 | "xmm12", "xmm13", "xmm14", "xmm15", |
3301 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3302 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3303 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3304 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3305 | }; |
3306 | static const char *att_names_xmm[] = { | |
3307 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3308 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3309 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3310 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3311 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3312 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3313 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3314 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3315 | }; |
3316 | ||
3317 | static const char **names_ymm; | |
3318 | static const char *intel_names_ymm[] = { | |
3319 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3320 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3321 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3322 | "ymm12", "ymm13", "ymm14", "ymm15", |
3323 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3324 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3325 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3326 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3327 | }; |
3328 | static const char *att_names_ymm[] = { | |
3329 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3330 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3331 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3332 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3333 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3334 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3335 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3336 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3337 | }; | |
3338 | ||
3339 | static const char **names_zmm; | |
3340 | static const char *intel_names_zmm[] = { | |
3341 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3342 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3343 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3344 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3345 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3346 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3347 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3348 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3349 | }; | |
3350 | static const char *att_names_zmm[] = { | |
3351 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3352 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3353 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3354 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3355 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3356 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3357 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3358 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3359 | }; | |
3360 | ||
3361 | static const char **names_mask; | |
3362 | static const char *intel_names_mask[] = { | |
3363 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3364 | }; | |
3365 | static const char *att_names_mask[] = { | |
3366 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3367 | }; | |
3368 | ||
3369 | static const char *names_rounding[] = | |
3370 | { | |
3371 | "{rn-sae}", | |
3372 | "{rd-sae}", | |
3373 | "{ru-sae}", | |
3374 | "{rz-sae}" | |
b9733481 L |
3375 | }; |
3376 | ||
1ceb70f8 L |
3377 | static const struct dis386 reg_table[][8] = { |
3378 | /* REG_80 */ | |
252b5132 | 3379 | { |
bf890a93 IT |
3380 | { "addA", { Ebh1, Ib }, 0 }, |
3381 | { "orA", { Ebh1, Ib }, 0 }, | |
3382 | { "adcA", { Ebh1, Ib }, 0 }, | |
3383 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3384 | { "andA", { Ebh1, Ib }, 0 }, | |
3385 | { "subA", { Ebh1, Ib }, 0 }, | |
3386 | { "xorA", { Ebh1, Ib }, 0 }, | |
3387 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3388 | }, |
1ceb70f8 | 3389 | /* REG_81 */ |
252b5132 | 3390 | { |
bf890a93 IT |
3391 | { "addQ", { Evh1, Iv }, 0 }, |
3392 | { "orQ", { Evh1, Iv }, 0 }, | |
3393 | { "adcQ", { Evh1, Iv }, 0 }, | |
3394 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3395 | { "andQ", { Evh1, Iv }, 0 }, | |
3396 | { "subQ", { Evh1, Iv }, 0 }, | |
3397 | { "xorQ", { Evh1, Iv }, 0 }, | |
3398 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3399 | }, |
1ceb70f8 | 3400 | /* REG_82 */ |
252b5132 | 3401 | { |
bf890a93 IT |
3402 | { "addQ", { Evh1, sIb }, 0 }, |
3403 | { "orQ", { Evh1, sIb }, 0 }, | |
3404 | { "adcQ", { Evh1, sIb }, 0 }, | |
3405 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3406 | { "andQ", { Evh1, sIb }, 0 }, | |
3407 | { "subQ", { Evh1, sIb }, 0 }, | |
3408 | { "xorQ", { Evh1, sIb }, 0 }, | |
3409 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3410 | }, |
1ceb70f8 | 3411 | /* REG_8F */ |
4e7d34a6 | 3412 | { |
bf890a93 | 3413 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3414 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3415 | { Bad_Opcode }, |
3416 | { Bad_Opcode }, | |
3417 | { Bad_Opcode }, | |
f88c9eb0 | 3418 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3419 | }, |
1ceb70f8 | 3420 | /* REG_C0 */ |
252b5132 | 3421 | { |
bf890a93 IT |
3422 | { "rolA", { Eb, Ib }, 0 }, |
3423 | { "rorA", { Eb, Ib }, 0 }, | |
3424 | { "rclA", { Eb, Ib }, 0 }, | |
3425 | { "rcrA", { Eb, Ib }, 0 }, | |
3426 | { "shlA", { Eb, Ib }, 0 }, | |
3427 | { "shrA", { Eb, Ib }, 0 }, | |
592d1631 | 3428 | { Bad_Opcode }, |
bf890a93 | 3429 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3430 | }, |
1ceb70f8 | 3431 | /* REG_C1 */ |
252b5132 | 3432 | { |
bf890a93 IT |
3433 | { "rolQ", { Ev, Ib }, 0 }, |
3434 | { "rorQ", { Ev, Ib }, 0 }, | |
3435 | { "rclQ", { Ev, Ib }, 0 }, | |
3436 | { "rcrQ", { Ev, Ib }, 0 }, | |
3437 | { "shlQ", { Ev, Ib }, 0 }, | |
3438 | { "shrQ", { Ev, Ib }, 0 }, | |
592d1631 | 3439 | { Bad_Opcode }, |
bf890a93 | 3440 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3441 | }, |
1ceb70f8 | 3442 | /* REG_C6 */ |
4e7d34a6 | 3443 | { |
bf890a93 | 3444 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3445 | { Bad_Opcode }, |
3446 | { Bad_Opcode }, | |
3447 | { Bad_Opcode }, | |
3448 | { Bad_Opcode }, | |
3449 | { Bad_Opcode }, | |
3450 | { Bad_Opcode }, | |
3451 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3452 | }, |
1ceb70f8 | 3453 | /* REG_C7 */ |
4e7d34a6 | 3454 | { |
bf890a93 | 3455 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3456 | { Bad_Opcode }, |
3457 | { Bad_Opcode }, | |
3458 | { Bad_Opcode }, | |
3459 | { Bad_Opcode }, | |
3460 | { Bad_Opcode }, | |
3461 | { Bad_Opcode }, | |
3462 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3463 | }, |
1ceb70f8 | 3464 | /* REG_D0 */ |
252b5132 | 3465 | { |
bf890a93 IT |
3466 | { "rolA", { Eb, I1 }, 0 }, |
3467 | { "rorA", { Eb, I1 }, 0 }, | |
3468 | { "rclA", { Eb, I1 }, 0 }, | |
3469 | { "rcrA", { Eb, I1 }, 0 }, | |
3470 | { "shlA", { Eb, I1 }, 0 }, | |
3471 | { "shrA", { Eb, I1 }, 0 }, | |
592d1631 | 3472 | { Bad_Opcode }, |
bf890a93 | 3473 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3474 | }, |
1ceb70f8 | 3475 | /* REG_D1 */ |
252b5132 | 3476 | { |
bf890a93 IT |
3477 | { "rolQ", { Ev, I1 }, 0 }, |
3478 | { "rorQ", { Ev, I1 }, 0 }, | |
3479 | { "rclQ", { Ev, I1 }, 0 }, | |
3480 | { "rcrQ", { Ev, I1 }, 0 }, | |
3481 | { "shlQ", { Ev, I1 }, 0 }, | |
3482 | { "shrQ", { Ev, I1 }, 0 }, | |
592d1631 | 3483 | { Bad_Opcode }, |
bf890a93 | 3484 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3485 | }, |
1ceb70f8 | 3486 | /* REG_D2 */ |
252b5132 | 3487 | { |
bf890a93 IT |
3488 | { "rolA", { Eb, CL }, 0 }, |
3489 | { "rorA", { Eb, CL }, 0 }, | |
3490 | { "rclA", { Eb, CL }, 0 }, | |
3491 | { "rcrA", { Eb, CL }, 0 }, | |
3492 | { "shlA", { Eb, CL }, 0 }, | |
3493 | { "shrA", { Eb, CL }, 0 }, | |
592d1631 | 3494 | { Bad_Opcode }, |
bf890a93 | 3495 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3496 | }, |
1ceb70f8 | 3497 | /* REG_D3 */ |
252b5132 | 3498 | { |
bf890a93 IT |
3499 | { "rolQ", { Ev, CL }, 0 }, |
3500 | { "rorQ", { Ev, CL }, 0 }, | |
3501 | { "rclQ", { Ev, CL }, 0 }, | |
3502 | { "rcrQ", { Ev, CL }, 0 }, | |
3503 | { "shlQ", { Ev, CL }, 0 }, | |
3504 | { "shrQ", { Ev, CL }, 0 }, | |
592d1631 | 3505 | { Bad_Opcode }, |
bf890a93 | 3506 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3507 | }, |
1ceb70f8 | 3508 | /* REG_F6 */ |
252b5132 | 3509 | { |
bf890a93 | 3510 | { "testA", { Eb, Ib }, 0 }, |
592d1631 | 3511 | { Bad_Opcode }, |
bf890a93 IT |
3512 | { "notA", { Ebh1 }, 0 }, |
3513 | { "negA", { Ebh1 }, 0 }, | |
3514 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3515 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3516 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3517 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3518 | }, |
1ceb70f8 | 3519 | /* REG_F7 */ |
252b5132 | 3520 | { |
bf890a93 | 3521 | { "testQ", { Ev, Iv }, 0 }, |
592d1631 | 3522 | { Bad_Opcode }, |
bf890a93 IT |
3523 | { "notQ", { Evh1 }, 0 }, |
3524 | { "negQ", { Evh1 }, 0 }, | |
3525 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3526 | { "imulQ", { Ev }, 0 }, | |
3527 | { "divQ", { Ev }, 0 }, | |
3528 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3529 | }, |
1ceb70f8 | 3530 | /* REG_FE */ |
252b5132 | 3531 | { |
bf890a93 IT |
3532 | { "incA", { Ebh1 }, 0 }, |
3533 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3534 | }, |
1ceb70f8 | 3535 | /* REG_FF */ |
252b5132 | 3536 | { |
bf890a93 IT |
3537 | { "incQ", { Evh1 }, 0 }, |
3538 | { "decQ", { Evh1 }, 0 }, | |
07f5af7d | 3539 | { "call{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3540 | { MOD_TABLE (MOD_FF_REG_3) }, |
07f5af7d | 3541 | { "jmp{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3542 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3543 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3544 | { Bad_Opcode }, |
252b5132 | 3545 | }, |
1ceb70f8 | 3546 | /* REG_0F00 */ |
252b5132 | 3547 | { |
bf890a93 IT |
3548 | { "sldtD", { Sv }, 0 }, |
3549 | { "strD", { Sv }, 0 }, | |
3550 | { "lldt", { Ew }, 0 }, | |
3551 | { "ltr", { Ew }, 0 }, | |
3552 | { "verr", { Ew }, 0 }, | |
3553 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3554 | { Bad_Opcode }, |
3555 | { Bad_Opcode }, | |
252b5132 | 3556 | }, |
1ceb70f8 | 3557 | /* REG_0F01 */ |
252b5132 | 3558 | { |
1ceb70f8 L |
3559 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3560 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3561 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3562 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3563 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3564 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3565 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3566 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3567 | }, |
b5b1fc4f | 3568 | /* REG_0F0D */ |
252b5132 | 3569 | { |
bf890a93 IT |
3570 | { "prefetch", { Mb }, 0 }, |
3571 | { "prefetchw", { Mb }, 0 }, | |
3572 | { "prefetchwt1", { Mb }, 0 }, | |
3573 | { "prefetch", { Mb }, 0 }, | |
3574 | { "prefetch", { Mb }, 0 }, | |
3575 | { "prefetch", { Mb }, 0 }, | |
3576 | { "prefetch", { Mb }, 0 }, | |
3577 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3578 | }, |
1ceb70f8 | 3579 | /* REG_0F18 */ |
252b5132 | 3580 | { |
1ceb70f8 L |
3581 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3582 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3583 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3584 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3585 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3586 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3587 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3588 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3589 | }, |
1ceb70f8 | 3590 | /* REG_0F71 */ |
a6bd098c | 3591 | { |
592d1631 L |
3592 | { Bad_Opcode }, |
3593 | { Bad_Opcode }, | |
1ceb70f8 | 3594 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3595 | { Bad_Opcode }, |
1ceb70f8 | 3596 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3597 | { Bad_Opcode }, |
1ceb70f8 | 3598 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3599 | }, |
1ceb70f8 | 3600 | /* REG_0F72 */ |
a6bd098c | 3601 | { |
592d1631 L |
3602 | { Bad_Opcode }, |
3603 | { Bad_Opcode }, | |
1ceb70f8 | 3604 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3605 | { Bad_Opcode }, |
1ceb70f8 | 3606 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3607 | { Bad_Opcode }, |
1ceb70f8 | 3608 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3609 | }, |
1ceb70f8 | 3610 | /* REG_0F73 */ |
252b5132 | 3611 | { |
592d1631 L |
3612 | { Bad_Opcode }, |
3613 | { Bad_Opcode }, | |
1ceb70f8 L |
3614 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3615 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3616 | { Bad_Opcode }, |
3617 | { Bad_Opcode }, | |
1ceb70f8 L |
3618 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3619 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3620 | }, |
1ceb70f8 | 3621 | /* REG_0FA6 */ |
252b5132 | 3622 | { |
bf890a93 IT |
3623 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3624 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3625 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3626 | }, |
1ceb70f8 | 3627 | /* REG_0FA7 */ |
4e7d34a6 | 3628 | { |
bf890a93 IT |
3629 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3630 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3631 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3632 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3633 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3634 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3635 | }, |
1ceb70f8 | 3636 | /* REG_0FAE */ |
4e7d34a6 | 3637 | { |
1ceb70f8 L |
3638 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3639 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3640 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3641 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3642 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3643 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3644 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3645 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3646 | }, |
1ceb70f8 | 3647 | /* REG_0FBA */ |
252b5132 | 3648 | { |
592d1631 L |
3649 | { Bad_Opcode }, |
3650 | { Bad_Opcode }, | |
3651 | { Bad_Opcode }, | |
3652 | { Bad_Opcode }, | |
bf890a93 IT |
3653 | { "btQ", { Ev, Ib }, 0 }, |
3654 | { "btsQ", { Evh1, Ib }, 0 }, | |
3655 | { "btrQ", { Evh1, Ib }, 0 }, | |
3656 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3657 | }, |
1ceb70f8 | 3658 | /* REG_0FC7 */ |
c608c12e | 3659 | { |
592d1631 | 3660 | { Bad_Opcode }, |
bf890a93 | 3661 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3662 | { Bad_Opcode }, |
963f3586 IT |
3663 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3664 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3665 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3666 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3667 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3668 | }, |
592a252b | 3669 | /* REG_VEX_0F71 */ |
c0f3af97 | 3670 | { |
592d1631 L |
3671 | { Bad_Opcode }, |
3672 | { Bad_Opcode }, | |
592a252b | 3673 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3674 | { Bad_Opcode }, |
592a252b | 3675 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3676 | { Bad_Opcode }, |
592a252b | 3677 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3678 | }, |
592a252b | 3679 | /* REG_VEX_0F72 */ |
c0f3af97 | 3680 | { |
592d1631 L |
3681 | { Bad_Opcode }, |
3682 | { Bad_Opcode }, | |
592a252b | 3683 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3684 | { Bad_Opcode }, |
592a252b | 3685 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3686 | { Bad_Opcode }, |
592a252b | 3687 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3688 | }, |
592a252b | 3689 | /* REG_VEX_0F73 */ |
c0f3af97 | 3690 | { |
592d1631 L |
3691 | { Bad_Opcode }, |
3692 | { Bad_Opcode }, | |
592a252b L |
3693 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3694 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3695 | { Bad_Opcode }, |
3696 | { Bad_Opcode }, | |
592a252b L |
3697 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3698 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3699 | }, |
592a252b | 3700 | /* REG_VEX_0FAE */ |
c0f3af97 | 3701 | { |
592d1631 L |
3702 | { Bad_Opcode }, |
3703 | { Bad_Opcode }, | |
592a252b L |
3704 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3705 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3706 | }, |
f12dc422 L |
3707 | /* REG_VEX_0F38F3 */ |
3708 | { | |
3709 | { Bad_Opcode }, | |
3710 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3711 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3712 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3713 | }, | |
f88c9eb0 SP |
3714 | /* REG_XOP_LWPCB */ |
3715 | { | |
bf890a93 IT |
3716 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3717 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3718 | }, |
3719 | /* REG_XOP_LWP */ | |
3720 | { | |
bf890a93 IT |
3721 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3722 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3723 | }, |
2a2a0f38 QN |
3724 | /* REG_XOP_TBM_01 */ |
3725 | { | |
3726 | { Bad_Opcode }, | |
bf890a93 IT |
3727 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3728 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3729 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3730 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3731 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3732 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3733 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3734 | }, |
3735 | /* REG_XOP_TBM_02 */ | |
3736 | { | |
3737 | { Bad_Opcode }, | |
bf890a93 | 3738 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3739 | { Bad_Opcode }, |
3740 | { Bad_Opcode }, | |
3741 | { Bad_Opcode }, | |
3742 | { Bad_Opcode }, | |
bf890a93 | 3743 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3744 | }, |
43234a1e L |
3745 | #define NEED_REG_TABLE |
3746 | #include "i386-dis-evex.h" | |
3747 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3748 | }; |
3749 | ||
1ceb70f8 L |
3750 | static const struct dis386 prefix_table[][4] = { |
3751 | /* PREFIX_90 */ | |
252b5132 | 3752 | { |
bf890a93 IT |
3753 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3754 | { "pause", { XX }, 0 }, | |
3755 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3756 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3757 | }, |
4e7d34a6 | 3758 | |
1ceb70f8 | 3759 | /* PREFIX_0F10 */ |
cc0ec051 | 3760 | { |
507bd325 L |
3761 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3762 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3763 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3764 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3765 | }, |
4e7d34a6 | 3766 | |
1ceb70f8 | 3767 | /* PREFIX_0F11 */ |
30d1c836 | 3768 | { |
507bd325 L |
3769 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3770 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3771 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3772 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3773 | }, |
252b5132 | 3774 | |
1ceb70f8 | 3775 | /* PREFIX_0F12 */ |
c608c12e | 3776 | { |
1ceb70f8 | 3777 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3778 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3779 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3780 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3781 | }, |
4e7d34a6 | 3782 | |
1ceb70f8 | 3783 | /* PREFIX_0F16 */ |
c608c12e | 3784 | { |
1ceb70f8 | 3785 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3786 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3787 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3788 | }, |
4e7d34a6 | 3789 | |
7e8b059b L |
3790 | /* PREFIX_0F1A */ |
3791 | { | |
3792 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3793 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3794 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3795 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3796 | }, |
3797 | ||
3798 | /* PREFIX_0F1B */ | |
3799 | { | |
3800 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3801 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
bf890a93 IT |
3802 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3803 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3804 | }, |
3805 | ||
1ceb70f8 | 3806 | /* PREFIX_0F2A */ |
c608c12e | 3807 | { |
507bd325 L |
3808 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3809 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3810 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3811 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3812 | }, |
4e7d34a6 | 3813 | |
1ceb70f8 | 3814 | /* PREFIX_0F2B */ |
c608c12e | 3815 | { |
75c135a8 L |
3816 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3817 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3818 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3819 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3820 | }, |
4e7d34a6 | 3821 | |
1ceb70f8 | 3822 | /* PREFIX_0F2C */ |
c608c12e | 3823 | { |
507bd325 L |
3824 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3825 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3826 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3827 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3828 | }, |
4e7d34a6 | 3829 | |
1ceb70f8 | 3830 | /* PREFIX_0F2D */ |
c608c12e | 3831 | { |
507bd325 L |
3832 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3833 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3834 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3835 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3836 | }, |
4e7d34a6 | 3837 | |
1ceb70f8 | 3838 | /* PREFIX_0F2E */ |
c608c12e | 3839 | { |
bf890a93 | 3840 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3841 | { Bad_Opcode }, |
bf890a93 | 3842 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3843 | }, |
4e7d34a6 | 3844 | |
1ceb70f8 | 3845 | /* PREFIX_0F2F */ |
c608c12e | 3846 | { |
bf890a93 | 3847 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3848 | { Bad_Opcode }, |
bf890a93 | 3849 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3850 | }, |
4e7d34a6 | 3851 | |
1ceb70f8 | 3852 | /* PREFIX_0F51 */ |
c608c12e | 3853 | { |
507bd325 L |
3854 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3855 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3856 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3857 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3858 | }, |
4e7d34a6 | 3859 | |
1ceb70f8 | 3860 | /* PREFIX_0F52 */ |
c608c12e | 3861 | { |
507bd325 L |
3862 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3863 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3864 | }, |
4e7d34a6 | 3865 | |
1ceb70f8 | 3866 | /* PREFIX_0F53 */ |
c608c12e | 3867 | { |
507bd325 L |
3868 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3869 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3870 | }, |
4e7d34a6 | 3871 | |
1ceb70f8 | 3872 | /* PREFIX_0F58 */ |
c608c12e | 3873 | { |
507bd325 L |
3874 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3875 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3876 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3877 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3878 | }, |
4e7d34a6 | 3879 | |
1ceb70f8 | 3880 | /* PREFIX_0F59 */ |
c608c12e | 3881 | { |
507bd325 L |
3882 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3883 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3884 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3885 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3886 | }, |
4e7d34a6 | 3887 | |
1ceb70f8 | 3888 | /* PREFIX_0F5A */ |
041bd2e0 | 3889 | { |
507bd325 L |
3890 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3891 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3892 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3893 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3894 | }, |
4e7d34a6 | 3895 | |
1ceb70f8 | 3896 | /* PREFIX_0F5B */ |
041bd2e0 | 3897 | { |
507bd325 L |
3898 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3899 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3900 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3901 | }, |
4e7d34a6 | 3902 | |
1ceb70f8 | 3903 | /* PREFIX_0F5C */ |
041bd2e0 | 3904 | { |
507bd325 L |
3905 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3906 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3907 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3908 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3909 | }, |
4e7d34a6 | 3910 | |
1ceb70f8 | 3911 | /* PREFIX_0F5D */ |
041bd2e0 | 3912 | { |
507bd325 L |
3913 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3914 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3915 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3916 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3917 | }, |
4e7d34a6 | 3918 | |
1ceb70f8 | 3919 | /* PREFIX_0F5E */ |
041bd2e0 | 3920 | { |
507bd325 L |
3921 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3922 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3923 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3924 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3925 | }, |
4e7d34a6 | 3926 | |
1ceb70f8 | 3927 | /* PREFIX_0F5F */ |
041bd2e0 | 3928 | { |
507bd325 L |
3929 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3930 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3931 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3932 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3933 | }, |
4e7d34a6 | 3934 | |
1ceb70f8 | 3935 | /* PREFIX_0F60 */ |
041bd2e0 | 3936 | { |
507bd325 | 3937 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3938 | { Bad_Opcode }, |
507bd325 | 3939 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3940 | }, |
4e7d34a6 | 3941 | |
1ceb70f8 | 3942 | /* PREFIX_0F61 */ |
041bd2e0 | 3943 | { |
507bd325 | 3944 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3945 | { Bad_Opcode }, |
507bd325 | 3946 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3947 | }, |
4e7d34a6 | 3948 | |
1ceb70f8 | 3949 | /* PREFIX_0F62 */ |
041bd2e0 | 3950 | { |
507bd325 | 3951 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3952 | { Bad_Opcode }, |
507bd325 | 3953 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3954 | }, |
4e7d34a6 | 3955 | |
1ceb70f8 | 3956 | /* PREFIX_0F6C */ |
041bd2e0 | 3957 | { |
592d1631 L |
3958 | { Bad_Opcode }, |
3959 | { Bad_Opcode }, | |
507bd325 | 3960 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3961 | }, |
4e7d34a6 | 3962 | |
1ceb70f8 | 3963 | /* PREFIX_0F6D */ |
0f17484f | 3964 | { |
592d1631 L |
3965 | { Bad_Opcode }, |
3966 | { Bad_Opcode }, | |
507bd325 | 3967 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3968 | }, |
4e7d34a6 | 3969 | |
1ceb70f8 | 3970 | /* PREFIX_0F6F */ |
ca164297 | 3971 | { |
507bd325 L |
3972 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3973 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3974 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3975 | }, |
4e7d34a6 | 3976 | |
1ceb70f8 | 3977 | /* PREFIX_0F70 */ |
4e7d34a6 | 3978 | { |
507bd325 L |
3979 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3980 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3981 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3982 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3983 | }, |
3984 | ||
92fddf8e L |
3985 | /* PREFIX_0F73_REG_3 */ |
3986 | { | |
592d1631 L |
3987 | { Bad_Opcode }, |
3988 | { Bad_Opcode }, | |
bf890a93 | 3989 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3990 | }, |
3991 | ||
3992 | /* PREFIX_0F73_REG_7 */ | |
3993 | { | |
592d1631 L |
3994 | { Bad_Opcode }, |
3995 | { Bad_Opcode }, | |
bf890a93 | 3996 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3997 | }, |
3998 | ||
1ceb70f8 | 3999 | /* PREFIX_0F78 */ |
4e7d34a6 | 4000 | { |
bf890a93 | 4001 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4002 | { Bad_Opcode }, |
bf890a93 IT |
4003 | {"extrq", { XS, Ib, Ib }, 0 }, |
4004 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4005 | }, |
4006 | ||
1ceb70f8 | 4007 | /* PREFIX_0F79 */ |
4e7d34a6 | 4008 | { |
bf890a93 | 4009 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4010 | { Bad_Opcode }, |
bf890a93 IT |
4011 | {"extrq", { XM, XS }, 0 }, |
4012 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4013 | }, |
4014 | ||
1ceb70f8 | 4015 | /* PREFIX_0F7C */ |
ca164297 | 4016 | { |
592d1631 L |
4017 | { Bad_Opcode }, |
4018 | { Bad_Opcode }, | |
507bd325 L |
4019 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4020 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4021 | }, |
4e7d34a6 | 4022 | |
1ceb70f8 | 4023 | /* PREFIX_0F7D */ |
ca164297 | 4024 | { |
592d1631 L |
4025 | { Bad_Opcode }, |
4026 | { Bad_Opcode }, | |
507bd325 L |
4027 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4028 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4029 | }, |
4e7d34a6 | 4030 | |
1ceb70f8 | 4031 | /* PREFIX_0F7E */ |
ca164297 | 4032 | { |
507bd325 L |
4033 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4034 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4035 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4036 | }, |
4e7d34a6 | 4037 | |
1ceb70f8 | 4038 | /* PREFIX_0F7F */ |
ca164297 | 4039 | { |
507bd325 L |
4040 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4041 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4042 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4043 | }, |
4e7d34a6 | 4044 | |
c7b8aa3a L |
4045 | /* PREFIX_0FAE_REG_0 */ |
4046 | { | |
4047 | { Bad_Opcode }, | |
bf890a93 | 4048 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4049 | }, |
4050 | ||
4051 | /* PREFIX_0FAE_REG_1 */ | |
4052 | { | |
4053 | { Bad_Opcode }, | |
bf890a93 | 4054 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4055 | }, |
4056 | ||
4057 | /* PREFIX_0FAE_REG_2 */ | |
4058 | { | |
4059 | { Bad_Opcode }, | |
bf890a93 | 4060 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4061 | }, |
4062 | ||
4063 | /* PREFIX_0FAE_REG_3 */ | |
4064 | { | |
4065 | { Bad_Opcode }, | |
bf890a93 | 4066 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4067 | }, |
4068 | ||
c5e7287a IT |
4069 | /* PREFIX_0FAE_REG_6 */ |
4070 | { | |
bf890a93 | 4071 | { "xsaveopt", { FXSAVE }, 0 }, |
c5e7287a | 4072 | { Bad_Opcode }, |
bf890a93 | 4073 | { "clwb", { Mb }, 0 }, |
c5e7287a IT |
4074 | }, |
4075 | ||
963f3586 IT |
4076 | /* PREFIX_0FAE_REG_7 */ |
4077 | { | |
bf890a93 | 4078 | { "clflush", { Mb }, 0 }, |
963f3586 | 4079 | { Bad_Opcode }, |
bf890a93 | 4080 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4081 | }, |
4082 | ||
9d8596f0 IT |
4083 | /* PREFIX_RM_0_0FAE_REG_7 */ |
4084 | { | |
bf890a93 | 4085 | { "sfence", { Skip_MODRM }, 0 }, |
9d8596f0 | 4086 | { Bad_Opcode }, |
bf890a93 | 4087 | { "pcommit", { Skip_MODRM }, 0 }, |
9d8596f0 IT |
4088 | }, |
4089 | ||
1ceb70f8 | 4090 | /* PREFIX_0FB8 */ |
ca164297 | 4091 | { |
592d1631 | 4092 | { Bad_Opcode }, |
bf890a93 | 4093 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4094 | }, |
4e7d34a6 | 4095 | |
f12dc422 L |
4096 | /* PREFIX_0FBC */ |
4097 | { | |
bf890a93 IT |
4098 | { "bsfS", { Gv, Ev }, 0 }, |
4099 | { "tzcntS", { Gv, Ev }, 0 }, | |
4100 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4101 | }, |
4102 | ||
1ceb70f8 | 4103 | /* PREFIX_0FBD */ |
050dfa73 | 4104 | { |
bf890a93 IT |
4105 | { "bsrS", { Gv, Ev }, 0 }, |
4106 | { "lzcntS", { Gv, Ev }, 0 }, | |
4107 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4108 | }, |
4109 | ||
1ceb70f8 | 4110 | /* PREFIX_0FC2 */ |
050dfa73 | 4111 | { |
507bd325 L |
4112 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4113 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4114 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4115 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4116 | }, |
246c51aa | 4117 | |
a8484f96 | 4118 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4119 | { |
a8484f96 | 4120 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4121 | }, |
4122 | ||
f24bcbaa | 4123 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4124 | { |
bf890a93 IT |
4125 | { "vmptrld",{ Mq }, 0 }, |
4126 | { "vmxon", { Mq }, 0 }, | |
4127 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4128 | }, |
4129 | ||
f24bcbaa L |
4130 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4131 | { | |
4132 | { "rdrand", { Ev }, 0 }, | |
4133 | { Bad_Opcode }, | |
4134 | { "rdrand", { Ev }, 0 } | |
4135 | }, | |
4136 | ||
4137 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4138 | { | |
4139 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4140 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4141 | { "rdseed", { Ev }, 0 }, |
4142 | }, | |
4143 | ||
1ceb70f8 | 4144 | /* PREFIX_0FD0 */ |
050dfa73 | 4145 | { |
592d1631 L |
4146 | { Bad_Opcode }, |
4147 | { Bad_Opcode }, | |
bf890a93 IT |
4148 | { "addsubpd", { XM, EXx }, 0 }, |
4149 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4150 | }, |
050dfa73 | 4151 | |
1ceb70f8 | 4152 | /* PREFIX_0FD6 */ |
050dfa73 | 4153 | { |
592d1631 | 4154 | { Bad_Opcode }, |
bf890a93 IT |
4155 | { "movq2dq",{ XM, MS }, 0 }, |
4156 | { "movq", { EXqS, XM }, 0 }, | |
4157 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4158 | }, |
4159 | ||
1ceb70f8 | 4160 | /* PREFIX_0FE6 */ |
7918206c | 4161 | { |
592d1631 | 4162 | { Bad_Opcode }, |
507bd325 L |
4163 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4164 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4165 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4166 | }, |
8b38ad71 | 4167 | |
1ceb70f8 | 4168 | /* PREFIX_0FE7 */ |
8b38ad71 | 4169 | { |
507bd325 | 4170 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4171 | { Bad_Opcode }, |
75c135a8 | 4172 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4173 | }, |
4174 | ||
1ceb70f8 | 4175 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4176 | { |
592d1631 L |
4177 | { Bad_Opcode }, |
4178 | { Bad_Opcode }, | |
4179 | { Bad_Opcode }, | |
1ceb70f8 | 4180 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4181 | }, |
4182 | ||
1ceb70f8 | 4183 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4184 | { |
507bd325 | 4185 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4186 | { Bad_Opcode }, |
507bd325 | 4187 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4188 | }, |
42903f7f | 4189 | |
1ceb70f8 | 4190 | /* PREFIX_0F3810 */ |
42903f7f | 4191 | { |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
507bd325 | 4194 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0F3814 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
507bd325 | 4201 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4202 | }, |
4203 | ||
1ceb70f8 | 4204 | /* PREFIX_0F3815 */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3817 */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3820 */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F3821 */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
507bd325 | 4229 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F3822 */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
507bd325 | 4236 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3823 */ |
42903f7f | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
507bd325 | 4243 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3824 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
507bd325 | 4250 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3825 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
507bd325 | 4257 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F3828 */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
507bd325 | 4264 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F3829 */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
507bd325 | 4271 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F382A */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
75c135a8 | 4278 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F382B */ |
42903f7f | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
507bd325 | 4285 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F3830 */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
507bd325 | 4292 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F3831 */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
507bd325 | 4299 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F3832 */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
507bd325 | 4306 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4307 | }, |
4308 | ||
1ceb70f8 | 4309 | /* PREFIX_0F3833 */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F3834 */ |
42903f7f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F3835 */ |
42903f7f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F3838 */ |
42903f7f | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
507bd325 | 4341 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4342 | }, |
4343 | ||
1ceb70f8 | 4344 | /* PREFIX_0F3839 */ |
42903f7f | 4345 | { |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
507bd325 | 4348 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4349 | }, |
4350 | ||
1ceb70f8 | 4351 | /* PREFIX_0F383A */ |
42903f7f | 4352 | { |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
507bd325 | 4355 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4356 | }, |
4357 | ||
1ceb70f8 | 4358 | /* PREFIX_0F383B */ |
42903f7f | 4359 | { |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
507bd325 | 4362 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4363 | }, |
4364 | ||
1ceb70f8 | 4365 | /* PREFIX_0F383C */ |
42903f7f | 4366 | { |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4370 | }, |
4371 | ||
1ceb70f8 | 4372 | /* PREFIX_0F383D */ |
42903f7f | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4377 | }, |
4378 | ||
1ceb70f8 | 4379 | /* PREFIX_0F383E */ |
42903f7f | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4384 | }, |
4385 | ||
1ceb70f8 | 4386 | /* PREFIX_0F383F */ |
42903f7f | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F3840 */ |
42903f7f | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
507bd325 | 4397 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4398 | }, |
4399 | ||
1ceb70f8 | 4400 | /* PREFIX_0F3841 */ |
42903f7f | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4405 | }, |
4406 | ||
f1f8f695 L |
4407 | /* PREFIX_0F3880 */ |
4408 | { | |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
507bd325 | 4411 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4412 | }, |
4413 | ||
4414 | /* PREFIX_0F3881 */ | |
4415 | { | |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4419 | }, |
4420 | ||
6c30d220 L |
4421 | /* PREFIX_0F3882 */ |
4422 | { | |
4423 | { Bad_Opcode }, | |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4426 | }, |
4427 | ||
a0046408 L |
4428 | /* PREFIX_0F38C8 */ |
4429 | { | |
507bd325 | 4430 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4431 | }, |
4432 | ||
4433 | /* PREFIX_0F38C9 */ | |
4434 | { | |
507bd325 | 4435 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4436 | }, |
4437 | ||
4438 | /* PREFIX_0F38CA */ | |
4439 | { | |
507bd325 | 4440 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4441 | }, |
4442 | ||
4443 | /* PREFIX_0F38CB */ | |
4444 | { | |
507bd325 | 4445 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4446 | }, |
4447 | ||
4448 | /* PREFIX_0F38CC */ | |
4449 | { | |
507bd325 | 4450 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4451 | }, |
4452 | ||
4453 | /* PREFIX_0F38CD */ | |
4454 | { | |
507bd325 | 4455 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4456 | }, |
4457 | ||
c0f3af97 L |
4458 | /* PREFIX_0F38DB */ |
4459 | { | |
592d1631 L |
4460 | { Bad_Opcode }, |
4461 | { Bad_Opcode }, | |
507bd325 | 4462 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4463 | }, |
4464 | ||
4465 | /* PREFIX_0F38DC */ | |
4466 | { | |
592d1631 L |
4467 | { Bad_Opcode }, |
4468 | { Bad_Opcode }, | |
507bd325 | 4469 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4470 | }, |
4471 | ||
4472 | /* PREFIX_0F38DD */ | |
4473 | { | |
592d1631 L |
4474 | { Bad_Opcode }, |
4475 | { Bad_Opcode }, | |
507bd325 | 4476 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4477 | }, |
4478 | ||
4479 | /* PREFIX_0F38DE */ | |
4480 | { | |
592d1631 L |
4481 | { Bad_Opcode }, |
4482 | { Bad_Opcode }, | |
507bd325 | 4483 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4484 | }, |
4485 | ||
4486 | /* PREFIX_0F38DF */ | |
4487 | { | |
592d1631 L |
4488 | { Bad_Opcode }, |
4489 | { Bad_Opcode }, | |
507bd325 | 4490 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4491 | }, |
4492 | ||
1ceb70f8 | 4493 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4494 | { |
507bd325 | 4495 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4496 | { Bad_Opcode }, |
507bd325 L |
4497 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4498 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4499 | }, |
4500 | ||
1ceb70f8 | 4501 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4502 | { |
507bd325 | 4503 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4504 | { Bad_Opcode }, |
507bd325 L |
4505 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4506 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4507 | }, |
4508 | ||
e2e1fcde L |
4509 | /* PREFIX_0F38F6 */ |
4510 | { | |
4511 | { Bad_Opcode }, | |
507bd325 L |
4512 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4513 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4514 | { Bad_Opcode }, |
4515 | }, | |
4516 | ||
1ceb70f8 | 4517 | /* PREFIX_0F3A08 */ |
42903f7f | 4518 | { |
592d1631 L |
4519 | { Bad_Opcode }, |
4520 | { Bad_Opcode }, | |
507bd325 | 4521 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4522 | }, |
4523 | ||
1ceb70f8 | 4524 | /* PREFIX_0F3A09 */ |
42903f7f | 4525 | { |
592d1631 L |
4526 | { Bad_Opcode }, |
4527 | { Bad_Opcode }, | |
507bd325 | 4528 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4529 | }, |
4530 | ||
1ceb70f8 | 4531 | /* PREFIX_0F3A0A */ |
42903f7f | 4532 | { |
592d1631 L |
4533 | { Bad_Opcode }, |
4534 | { Bad_Opcode }, | |
507bd325 | 4535 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4536 | }, |
4537 | ||
1ceb70f8 | 4538 | /* PREFIX_0F3A0B */ |
42903f7f | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4543 | }, |
4544 | ||
1ceb70f8 | 4545 | /* PREFIX_0F3A0C */ |
42903f7f | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
507bd325 | 4549 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4550 | }, |
4551 | ||
1ceb70f8 | 4552 | /* PREFIX_0F3A0D */ |
42903f7f | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
507bd325 | 4556 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4557 | }, |
4558 | ||
1ceb70f8 | 4559 | /* PREFIX_0F3A0E */ |
42903f7f | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
507bd325 | 4563 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4564 | }, |
4565 | ||
1ceb70f8 | 4566 | /* PREFIX_0F3A14 */ |
42903f7f | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
507bd325 | 4570 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4571 | }, |
4572 | ||
1ceb70f8 | 4573 | /* PREFIX_0F3A15 */ |
42903f7f | 4574 | { |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
507bd325 | 4577 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4578 | }, |
4579 | ||
1ceb70f8 | 4580 | /* PREFIX_0F3A16 */ |
42903f7f | 4581 | { |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
507bd325 | 4584 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4585 | }, |
4586 | ||
1ceb70f8 | 4587 | /* PREFIX_0F3A17 */ |
42903f7f | 4588 | { |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
507bd325 | 4591 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4592 | }, |
4593 | ||
1ceb70f8 | 4594 | /* PREFIX_0F3A20 */ |
42903f7f | 4595 | { |
592d1631 L |
4596 | { Bad_Opcode }, |
4597 | { Bad_Opcode }, | |
507bd325 | 4598 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4599 | }, |
4600 | ||
1ceb70f8 | 4601 | /* PREFIX_0F3A21 */ |
42903f7f | 4602 | { |
592d1631 L |
4603 | { Bad_Opcode }, |
4604 | { Bad_Opcode }, | |
507bd325 | 4605 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4606 | }, |
4607 | ||
1ceb70f8 | 4608 | /* PREFIX_0F3A22 */ |
42903f7f | 4609 | { |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
507bd325 | 4612 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4613 | }, |
4614 | ||
1ceb70f8 | 4615 | /* PREFIX_0F3A40 */ |
42903f7f | 4616 | { |
592d1631 L |
4617 | { Bad_Opcode }, |
4618 | { Bad_Opcode }, | |
507bd325 | 4619 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4620 | }, |
4621 | ||
1ceb70f8 | 4622 | /* PREFIX_0F3A41 */ |
42903f7f | 4623 | { |
592d1631 L |
4624 | { Bad_Opcode }, |
4625 | { Bad_Opcode }, | |
507bd325 | 4626 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4627 | }, |
4628 | ||
1ceb70f8 | 4629 | /* PREFIX_0F3A42 */ |
42903f7f | 4630 | { |
592d1631 L |
4631 | { Bad_Opcode }, |
4632 | { Bad_Opcode }, | |
507bd325 | 4633 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4634 | }, |
381d071f | 4635 | |
c0f3af97 L |
4636 | /* PREFIX_0F3A44 */ |
4637 | { | |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
507bd325 | 4640 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4641 | }, |
4642 | ||
1ceb70f8 | 4643 | /* PREFIX_0F3A60 */ |
381d071f | 4644 | { |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
507bd325 | 4647 | { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4648 | }, |
4649 | ||
1ceb70f8 | 4650 | /* PREFIX_0F3A61 */ |
381d071f | 4651 | { |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
507bd325 | 4654 | { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4655 | }, |
4656 | ||
1ceb70f8 | 4657 | /* PREFIX_0F3A62 */ |
381d071f | 4658 | { |
592d1631 L |
4659 | { Bad_Opcode }, |
4660 | { Bad_Opcode }, | |
507bd325 | 4661 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4662 | }, |
4663 | ||
1ceb70f8 | 4664 | /* PREFIX_0F3A63 */ |
381d071f | 4665 | { |
592d1631 L |
4666 | { Bad_Opcode }, |
4667 | { Bad_Opcode }, | |
507bd325 | 4668 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4669 | }, |
09a2c6cf | 4670 | |
a0046408 L |
4671 | /* PREFIX_0F3ACC */ |
4672 | { | |
507bd325 | 4673 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4674 | }, |
4675 | ||
c0f3af97 | 4676 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4677 | { |
592d1631 L |
4678 | { Bad_Opcode }, |
4679 | { Bad_Opcode }, | |
507bd325 | 4680 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4681 | }, |
4682 | ||
592a252b | 4683 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4684 | { |
592a252b L |
4685 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4686 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4687 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4688 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4689 | }, |
4690 | ||
592a252b | 4691 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4692 | { |
592a252b L |
4693 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4694 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4695 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4696 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4697 | }, |
4698 | ||
592a252b | 4699 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4700 | { |
592a252b L |
4701 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4702 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4703 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4704 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4705 | }, |
4706 | ||
592a252b | 4707 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4708 | { |
592a252b L |
4709 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4710 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4711 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4712 | }, |
7c52e0e8 | 4713 | |
592a252b | 4714 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4715 | { |
592d1631 | 4716 | { Bad_Opcode }, |
592a252b | 4717 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4718 | { Bad_Opcode }, |
592a252b | 4719 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4720 | }, |
7c52e0e8 | 4721 | |
592a252b | 4722 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4723 | { |
592d1631 | 4724 | { Bad_Opcode }, |
592a252b | 4725 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4726 | { Bad_Opcode }, |
592a252b | 4727 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4728 | }, |
7c52e0e8 | 4729 | |
592a252b | 4730 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4731 | { |
592d1631 | 4732 | { Bad_Opcode }, |
592a252b | 4733 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4734 | { Bad_Opcode }, |
592a252b | 4735 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4736 | }, |
4737 | ||
592a252b | 4738 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4739 | { |
592a252b | 4740 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4741 | { Bad_Opcode }, |
592a252b | 4742 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4743 | }, |
4744 | ||
592a252b | 4745 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4746 | { |
592a252b | 4747 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4748 | { Bad_Opcode }, |
592a252b | 4749 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4750 | }, |
4751 | ||
43234a1e L |
4752 | /* PREFIX_VEX_0F41 */ |
4753 | { | |
4754 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4755 | { Bad_Opcode }, |
4756 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4757 | }, |
4758 | ||
4759 | /* PREFIX_VEX_0F42 */ | |
4760 | { | |
4761 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4762 | { Bad_Opcode }, |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4764 | }, |
4765 | ||
4766 | /* PREFIX_VEX_0F44 */ | |
4767 | { | |
4768 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4769 | { Bad_Opcode }, |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4771 | }, |
4772 | ||
4773 | /* PREFIX_VEX_0F45 */ | |
4774 | { | |
4775 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4776 | { Bad_Opcode }, |
4777 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4778 | }, |
4779 | ||
4780 | /* PREFIX_VEX_0F46 */ | |
4781 | { | |
4782 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4783 | { Bad_Opcode }, |
4784 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4785 | }, |
4786 | ||
4787 | /* PREFIX_VEX_0F47 */ | |
4788 | { | |
4789 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4790 | { Bad_Opcode }, |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4792 | }, |
4793 | ||
1ba585e8 | 4794 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4795 | { |
1ba585e8 | 4796 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4797 | { Bad_Opcode }, |
1ba585e8 IT |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4799 | }, | |
4800 | ||
4801 | /* PREFIX_VEX_0F4B */ | |
4802 | { | |
4803 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4804 | { Bad_Opcode }, |
4805 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4806 | }, | |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4809 | { |
592a252b L |
4810 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4811 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4812 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4813 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4814 | }, |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4817 | { |
592a252b L |
4818 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4819 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4820 | }, |
4821 | ||
592a252b | 4822 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4823 | { |
592a252b L |
4824 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4825 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4826 | }, |
4827 | ||
592a252b | 4828 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4829 | { |
592a252b L |
4830 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4831 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4832 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4833 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4837 | { |
592a252b L |
4838 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4839 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4840 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4841 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4842 | }, |
4843 | ||
592a252b | 4844 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4845 | { |
592a252b L |
4846 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4847 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4848 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4849 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4850 | }, |
4851 | ||
592a252b | 4852 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4853 | { |
592a252b L |
4854 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4855 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4856 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4860 | { |
592a252b L |
4861 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4862 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4863 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4864 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4865 | }, |
4866 | ||
592a252b | 4867 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4868 | { |
592a252b L |
4869 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4870 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4871 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4872 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4873 | }, |
4874 | ||
592a252b | 4875 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4876 | { |
592a252b L |
4877 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4878 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4879 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4880 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4881 | }, |
4882 | ||
592a252b | 4883 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4884 | { |
592a252b L |
4885 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4886 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4887 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4888 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4889 | }, |
4890 | ||
592a252b | 4891 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4892 | { |
592d1631 L |
4893 | { Bad_Opcode }, |
4894 | { Bad_Opcode }, | |
6c30d220 | 4895 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4896 | }, |
4897 | ||
592a252b | 4898 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4899 | { |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
6c30d220 | 4902 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
6c30d220 | 4909 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4910 | }, |
4911 | ||
592a252b | 4912 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
6c30d220 | 4916 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
6c30d220 | 4923 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4924 | }, |
4925 | ||
592a252b | 4926 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
6c30d220 | 4930 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4931 | }, |
4932 | ||
592a252b | 4933 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
6c30d220 | 4937 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4938 | }, |
6439fc28 | 4939 | |
592a252b | 4940 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4941 | { |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
6c30d220 | 4944 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4945 | }, |
4946 | ||
592a252b | 4947 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4948 | { |
592d1631 L |
4949 | { Bad_Opcode }, |
4950 | { Bad_Opcode }, | |
6c30d220 | 4951 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4952 | }, |
4953 | ||
592a252b | 4954 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4955 | { |
592d1631 L |
4956 | { Bad_Opcode }, |
4957 | { Bad_Opcode }, | |
6c30d220 | 4958 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4962 | { |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
6c30d220 | 4965 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4966 | }, |
4967 | ||
592a252b | 4968 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4969 | { |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
6c30d220 | 4972 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4973 | }, |
4974 | ||
592a252b | 4975 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4976 | { |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
6c30d220 | 4979 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4980 | }, |
4981 | ||
592a252b | 4982 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4983 | { |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
6c30d220 | 4986 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4987 | }, |
4988 | ||
592a252b | 4989 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4990 | { |
592d1631 L |
4991 | { Bad_Opcode }, |
4992 | { Bad_Opcode }, | |
592a252b | 4993 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4994 | }, |
4995 | ||
592a252b | 4996 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4997 | { |
592d1631 | 4998 | { Bad_Opcode }, |
592a252b L |
4999 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5000 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5001 | }, |
5002 | ||
592a252b | 5003 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5004 | { |
592d1631 | 5005 | { Bad_Opcode }, |
6c30d220 L |
5006 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5007 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5008 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5009 | }, |
5010 | ||
592a252b | 5011 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5012 | { |
592d1631 L |
5013 | { Bad_Opcode }, |
5014 | { Bad_Opcode }, | |
6c30d220 | 5015 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5016 | }, |
5017 | ||
592a252b | 5018 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5019 | { |
592d1631 L |
5020 | { Bad_Opcode }, |
5021 | { Bad_Opcode }, | |
6c30d220 | 5022 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5026 | { |
592d1631 L |
5027 | { Bad_Opcode }, |
5028 | { Bad_Opcode }, | |
6c30d220 | 5029 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5030 | }, |
5031 | ||
592a252b | 5032 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5033 | { |
592d1631 L |
5034 | { Bad_Opcode }, |
5035 | { Bad_Opcode }, | |
6c30d220 | 5036 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5037 | }, |
5038 | ||
592a252b | 5039 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5040 | { |
592d1631 L |
5041 | { Bad_Opcode }, |
5042 | { Bad_Opcode }, | |
6c30d220 | 5043 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5044 | }, |
5045 | ||
592a252b | 5046 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5047 | { |
592d1631 L |
5048 | { Bad_Opcode }, |
5049 | { Bad_Opcode }, | |
6c30d220 | 5050 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5051 | }, |
5052 | ||
592a252b | 5053 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5054 | { |
592d1631 L |
5055 | { Bad_Opcode }, |
5056 | { Bad_Opcode }, | |
6c30d220 | 5057 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5058 | }, |
5059 | ||
592a252b | 5060 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5061 | { |
592d1631 L |
5062 | { Bad_Opcode }, |
5063 | { Bad_Opcode }, | |
6c30d220 | 5064 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5065 | }, |
5066 | ||
592a252b | 5067 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5068 | { |
592d1631 L |
5069 | { Bad_Opcode }, |
5070 | { Bad_Opcode }, | |
6c30d220 | 5071 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5072 | }, |
5073 | ||
592a252b | 5074 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5075 | { |
592d1631 L |
5076 | { Bad_Opcode }, |
5077 | { Bad_Opcode }, | |
6c30d220 | 5078 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5082 | { |
592d1631 L |
5083 | { Bad_Opcode }, |
5084 | { Bad_Opcode }, | |
6c30d220 | 5085 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5089 | { |
592d1631 L |
5090 | { Bad_Opcode }, |
5091 | { Bad_Opcode }, | |
6c30d220 | 5092 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
6c30d220 | 5099 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5100 | }, |
5101 | ||
592a252b | 5102 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5103 | { |
592a252b | 5104 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5105 | }, |
5106 | ||
592a252b | 5107 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5108 | { |
592d1631 L |
5109 | { Bad_Opcode }, |
5110 | { Bad_Opcode }, | |
592a252b L |
5111 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5112 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5113 | }, |
5114 | ||
592a252b | 5115 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5116 | { |
592d1631 L |
5117 | { Bad_Opcode }, |
5118 | { Bad_Opcode }, | |
592a252b L |
5119 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5120 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5121 | }, |
5122 | ||
592a252b | 5123 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5124 | { |
592d1631 | 5125 | { Bad_Opcode }, |
592a252b L |
5126 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5127 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5128 | }, |
5129 | ||
592a252b | 5130 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5131 | { |
592d1631 | 5132 | { Bad_Opcode }, |
592a252b L |
5133 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5134 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5135 | }, |
5136 | ||
43234a1e L |
5137 | /* PREFIX_VEX_0F90 */ |
5138 | { | |
5139 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5140 | { Bad_Opcode }, |
5141 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5142 | }, |
5143 | ||
5144 | /* PREFIX_VEX_0F91 */ | |
5145 | { | |
5146 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5147 | { Bad_Opcode }, |
5148 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5149 | }, |
5150 | ||
5151 | /* PREFIX_VEX_0F92 */ | |
5152 | { | |
5153 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5154 | { Bad_Opcode }, |
90a915bf | 5155 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5156 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5157 | }, |
5158 | ||
5159 | /* PREFIX_VEX_0F93 */ | |
5160 | { | |
5161 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5162 | { Bad_Opcode }, |
90a915bf | 5163 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5164 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5165 | }, |
5166 | ||
5167 | /* PREFIX_VEX_0F98 */ | |
5168 | { | |
5169 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5170 | { Bad_Opcode }, |
5171 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5172 | }, | |
5173 | ||
5174 | /* PREFIX_VEX_0F99 */ | |
5175 | { | |
5176 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5177 | { Bad_Opcode }, | |
5178 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5179 | }, |
5180 | ||
592a252b | 5181 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5182 | { |
592a252b L |
5183 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5184 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5185 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5186 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5187 | }, |
5188 | ||
592a252b | 5189 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5190 | { |
592d1631 L |
5191 | { Bad_Opcode }, |
5192 | { Bad_Opcode }, | |
592a252b | 5193 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5194 | }, |
5195 | ||
592a252b | 5196 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5197 | { |
592d1631 L |
5198 | { Bad_Opcode }, |
5199 | { Bad_Opcode }, | |
592a252b | 5200 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5201 | }, |
5202 | ||
592a252b | 5203 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5204 | { |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
592a252b L |
5207 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5208 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5209 | }, |
5210 | ||
592a252b | 5211 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5212 | { |
592d1631 L |
5213 | { Bad_Opcode }, |
5214 | { Bad_Opcode }, | |
6c30d220 | 5215 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
6c30d220 | 5222 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
6c30d220 | 5229 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
6c30d220 | 5236 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
6c30d220 | 5243 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
592a252b | 5250 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
592a252b | 5257 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
6c30d220 | 5264 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5268 | { |
592d1631 L |
5269 | { Bad_Opcode }, |
5270 | { Bad_Opcode }, | |
6c30d220 | 5271 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5272 | }, |
5273 | ||
592a252b | 5274 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5275 | { |
592d1631 L |
5276 | { Bad_Opcode }, |
5277 | { Bad_Opcode }, | |
6c30d220 | 5278 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5279 | }, |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5282 | { |
592d1631 L |
5283 | { Bad_Opcode }, |
5284 | { Bad_Opcode }, | |
6c30d220 | 5285 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5289 | { |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
6c30d220 | 5292 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5293 | }, |
5294 | ||
592a252b | 5295 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5296 | { |
592d1631 L |
5297 | { Bad_Opcode }, |
5298 | { Bad_Opcode }, | |
6c30d220 | 5299 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
6c30d220 | 5306 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
6c30d220 | 5313 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
6c30d220 | 5320 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
6c30d220 | 5327 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
6c30d220 | 5334 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
6c30d220 | 5341 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
6c30d220 | 5348 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
6c30d220 | 5355 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5359 | { |
592d1631 | 5360 | { Bad_Opcode }, |
592a252b L |
5361 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5362 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5363 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5364 | }, |
5365 | ||
592a252b | 5366 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5367 | { |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
592a252b | 5370 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
6c30d220 | 5377 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
6c30d220 | 5384 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
6c30d220 | 5391 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
6c30d220 | 5398 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
6c30d220 | 5405 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
6c30d220 | 5412 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
6c30d220 | 5419 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
6c30d220 | 5426 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
5433 | { Bad_Opcode }, | |
592a252b | 5434 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5435 | }, |
5436 | ||
592a252b | 5437 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5438 | { |
592d1631 L |
5439 | { Bad_Opcode }, |
5440 | { Bad_Opcode }, | |
6c30d220 | 5441 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5442 | }, |
5443 | ||
592a252b | 5444 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5445 | { |
592d1631 L |
5446 | { Bad_Opcode }, |
5447 | { Bad_Opcode }, | |
6c30d220 | 5448 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5449 | }, |
5450 | ||
592a252b | 5451 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5452 | { |
592d1631 L |
5453 | { Bad_Opcode }, |
5454 | { Bad_Opcode }, | |
6c30d220 | 5455 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5456 | }, |
5457 | ||
592a252b | 5458 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5459 | { |
592d1631 L |
5460 | { Bad_Opcode }, |
5461 | { Bad_Opcode }, | |
6c30d220 | 5462 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5463 | }, |
5464 | ||
592a252b | 5465 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5466 | { |
592d1631 L |
5467 | { Bad_Opcode }, |
5468 | { Bad_Opcode }, | |
6c30d220 | 5469 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5470 | }, |
5471 | ||
592a252b | 5472 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5473 | { |
592d1631 L |
5474 | { Bad_Opcode }, |
5475 | { Bad_Opcode }, | |
6c30d220 | 5476 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5477 | }, |
5478 | ||
592a252b | 5479 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5480 | { |
592d1631 L |
5481 | { Bad_Opcode }, |
5482 | { Bad_Opcode }, | |
592a252b | 5483 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5484 | }, |
5485 | ||
592a252b | 5486 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5487 | { |
592d1631 L |
5488 | { Bad_Opcode }, |
5489 | { Bad_Opcode }, | |
6c30d220 | 5490 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5491 | }, |
5492 | ||
592a252b | 5493 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5494 | { |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
6c30d220 | 5497 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5498 | }, |
5499 | ||
592a252b | 5500 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5501 | { |
592d1631 L |
5502 | { Bad_Opcode }, |
5503 | { Bad_Opcode }, | |
6c30d220 | 5504 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5505 | }, |
5506 | ||
592a252b | 5507 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5508 | { |
592d1631 L |
5509 | { Bad_Opcode }, |
5510 | { Bad_Opcode }, | |
6c30d220 | 5511 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5512 | }, |
5513 | ||
592a252b | 5514 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5515 | { |
592d1631 L |
5516 | { Bad_Opcode }, |
5517 | { Bad_Opcode }, | |
6c30d220 | 5518 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5519 | }, |
5520 | ||
592a252b | 5521 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5522 | { |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
6c30d220 | 5525 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5526 | }, |
5527 | ||
592a252b | 5528 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5529 | { |
592d1631 L |
5530 | { Bad_Opcode }, |
5531 | { Bad_Opcode }, | |
6c30d220 | 5532 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5533 | }, |
5534 | ||
592a252b | 5535 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5536 | { |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
6c30d220 | 5539 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5540 | }, |
5541 | ||
592a252b | 5542 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5543 | { |
592d1631 L |
5544 | { Bad_Opcode }, |
5545 | { Bad_Opcode }, | |
6c30d220 | 5546 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5547 | }, |
5548 | ||
592a252b | 5549 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5550 | { |
592d1631 L |
5551 | { Bad_Opcode }, |
5552 | { Bad_Opcode }, | |
6c30d220 | 5553 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5554 | }, |
5555 | ||
592a252b | 5556 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5557 | { |
592d1631 L |
5558 | { Bad_Opcode }, |
5559 | { Bad_Opcode }, | |
6c30d220 | 5560 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
6c30d220 | 5567 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
6c30d220 | 5574 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
6c30d220 | 5581 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
6c30d220 | 5588 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
6c30d220 | 5595 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
6c30d220 | 5602 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
6c30d220 | 5609 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
6c30d220 | 5616 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5617 | }, |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
592a252b | 5623 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
592a252b | 5630 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5631 | }, |
5632 | ||
592a252b | 5633 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5634 | { |
592d1631 L |
5635 | { Bad_Opcode }, |
5636 | { Bad_Opcode }, | |
592a252b | 5637 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5638 | }, |
5639 | ||
592a252b | 5640 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5641 | { |
592d1631 L |
5642 | { Bad_Opcode }, |
5643 | { Bad_Opcode }, | |
592a252b | 5644 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5645 | }, |
5646 | ||
592a252b | 5647 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5648 | { |
5649 | { Bad_Opcode }, | |
5650 | { Bad_Opcode }, | |
bf890a93 | 5651 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5652 | }, |
5653 | ||
6c30d220 L |
5654 | /* PREFIX_VEX_0F3816 */ |
5655 | { | |
5656 | { Bad_Opcode }, | |
5657 | { Bad_Opcode }, | |
5658 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5659 | }, | |
5660 | ||
592a252b | 5661 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5662 | { |
592d1631 L |
5663 | { Bad_Opcode }, |
5664 | { Bad_Opcode }, | |
592a252b | 5665 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5666 | }, |
5667 | ||
592a252b | 5668 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5669 | { |
592d1631 L |
5670 | { Bad_Opcode }, |
5671 | { Bad_Opcode }, | |
6c30d220 | 5672 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5673 | }, |
5674 | ||
592a252b | 5675 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5676 | { |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
6c30d220 | 5679 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5680 | }, |
5681 | ||
592a252b | 5682 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5683 | { |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
592a252b | 5686 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5687 | }, |
5688 | ||
592a252b | 5689 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5690 | { |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
6c30d220 | 5693 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5694 | }, |
5695 | ||
592a252b | 5696 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5697 | { |
592d1631 L |
5698 | { Bad_Opcode }, |
5699 | { Bad_Opcode }, | |
6c30d220 | 5700 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5701 | }, |
5702 | ||
592a252b | 5703 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5704 | { |
592d1631 L |
5705 | { Bad_Opcode }, |
5706 | { Bad_Opcode }, | |
6c30d220 | 5707 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5708 | }, |
5709 | ||
592a252b | 5710 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5711 | { |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
6c30d220 | 5714 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5715 | }, |
5716 | ||
592a252b | 5717 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5718 | { |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
6c30d220 | 5721 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5722 | }, |
5723 | ||
592a252b | 5724 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5725 | { |
592d1631 L |
5726 | { Bad_Opcode }, |
5727 | { Bad_Opcode }, | |
6c30d220 | 5728 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5729 | }, |
5730 | ||
592a252b | 5731 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5732 | { |
592d1631 L |
5733 | { Bad_Opcode }, |
5734 | { Bad_Opcode }, | |
6c30d220 | 5735 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5736 | }, |
5737 | ||
592a252b | 5738 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5739 | { |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
6c30d220 | 5742 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
6c30d220 | 5749 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
6c30d220 | 5756 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
6c30d220 | 5763 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
592a252b | 5770 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
6c30d220 | 5777 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
592a252b | 5784 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
592a252b | 5791 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5795 | { |
592d1631 L |
5796 | { Bad_Opcode }, |
5797 | { Bad_Opcode }, | |
592a252b | 5798 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5799 | }, |
5800 | ||
592a252b | 5801 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5802 | { |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
592a252b | 5805 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5806 | }, |
5807 | ||
592a252b | 5808 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5809 | { |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
6c30d220 | 5812 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
6c30d220 | 5819 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
6c30d220 | 5826 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
6c30d220 | 5833 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
6c30d220 | 5840 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
6c30d220 L |
5847 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5848 | }, | |
5849 | ||
5850 | /* PREFIX_VEX_0F3836 */ | |
5851 | { | |
5852 | { Bad_Opcode }, | |
5853 | { Bad_Opcode }, | |
5854 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5855 | }, |
5856 | ||
592a252b | 5857 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5858 | { |
592d1631 L |
5859 | { Bad_Opcode }, |
5860 | { Bad_Opcode }, | |
6c30d220 | 5861 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5862 | }, |
5863 | ||
592a252b | 5864 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5865 | { |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
6c30d220 | 5868 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
6c30d220 | 5875 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
6c30d220 | 5882 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
6c30d220 | 5889 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
592a252b | 5892 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5893 | { |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
6c30d220 | 5896 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5897 | }, |
5898 | ||
592a252b | 5899 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5900 | { |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
6c30d220 | 5903 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5904 | }, |
5905 | ||
592a252b | 5906 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5907 | { |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
6c30d220 | 5910 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5911 | }, |
5912 | ||
592a252b | 5913 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5914 | { |
592d1631 L |
5915 | { Bad_Opcode }, |
5916 | { Bad_Opcode }, | |
6c30d220 | 5917 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5918 | }, |
5919 | ||
592a252b | 5920 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5921 | { |
592d1631 L |
5922 | { Bad_Opcode }, |
5923 | { Bad_Opcode }, | |
6c30d220 | 5924 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5925 | }, |
5926 | ||
592a252b | 5927 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5928 | { |
592d1631 L |
5929 | { Bad_Opcode }, |
5930 | { Bad_Opcode }, | |
592a252b | 5931 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5932 | }, |
5933 | ||
6c30d220 L |
5934 | /* PREFIX_VEX_0F3845 */ |
5935 | { | |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
bf890a93 | 5938 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5939 | }, |
5940 | ||
5941 | /* PREFIX_VEX_0F3846 */ | |
5942 | { | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
5945 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5946 | }, | |
5947 | ||
5948 | /* PREFIX_VEX_0F3847 */ | |
5949 | { | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
bf890a93 | 5952 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5953 | }, |
5954 | ||
5955 | /* PREFIX_VEX_0F3858 */ | |
5956 | { | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
5959 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5960 | }, | |
5961 | ||
5962 | /* PREFIX_VEX_0F3859 */ | |
5963 | { | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
5966 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5967 | }, | |
5968 | ||
5969 | /* PREFIX_VEX_0F385A */ | |
5970 | { | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
5973 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5974 | }, | |
5975 | ||
5976 | /* PREFIX_VEX_0F3878 */ | |
5977 | { | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5981 | }, | |
5982 | ||
5983 | /* PREFIX_VEX_0F3879 */ | |
5984 | { | |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5988 | }, | |
5989 | ||
5990 | /* PREFIX_VEX_0F388C */ | |
5991 | { | |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
f7002f42 | 5994 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5995 | }, |
5996 | ||
5997 | /* PREFIX_VEX_0F388E */ | |
5998 | { | |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
f7002f42 | 6001 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6002 | }, |
6003 | ||
6004 | /* PREFIX_VEX_0F3890 */ | |
6005 | { | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
bf890a93 | 6008 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6009 | }, |
6010 | ||
6011 | /* PREFIX_VEX_0F3891 */ | |
6012 | { | |
6013 | { Bad_Opcode }, | |
6014 | { Bad_Opcode }, | |
bf890a93 | 6015 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6016 | }, |
6017 | ||
6018 | /* PREFIX_VEX_0F3892 */ | |
6019 | { | |
6020 | { Bad_Opcode }, | |
6021 | { Bad_Opcode }, | |
bf890a93 | 6022 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6023 | }, |
6024 | ||
6025 | /* PREFIX_VEX_0F3893 */ | |
6026 | { | |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
bf890a93 | 6029 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6030 | }, |
6031 | ||
592a252b | 6032 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6033 | { |
592d1631 L |
6034 | { Bad_Opcode }, |
6035 | { Bad_Opcode }, | |
bf890a93 | 6036 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6037 | }, |
6038 | ||
592a252b | 6039 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6040 | { |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
bf890a93 | 6043 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
bf890a93 | 6050 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
bf890a93 | 6057 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
bf890a93 | 6064 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
bf890a93 | 6071 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
bf890a93 | 6078 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6079 | }, |
6080 | ||
592a252b | 6081 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6082 | { |
592d1631 L |
6083 | { Bad_Opcode }, |
6084 | { Bad_Opcode }, | |
bf890a93 | 6085 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6086 | }, |
6087 | ||
592a252b | 6088 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6089 | { |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
bf890a93 | 6092 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6093 | }, |
6094 | ||
592a252b | 6095 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6096 | { |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
bf890a93 | 6099 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
bf890a93 | 6106 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6107 | { Bad_Opcode }, |
c0f3af97 L |
6108 | }, |
6109 | ||
592a252b | 6110 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6111 | { |
592d1631 L |
6112 | { Bad_Opcode }, |
6113 | { Bad_Opcode }, | |
bf890a93 | 6114 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6115 | }, |
6116 | ||
592a252b | 6117 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6118 | { |
592d1631 L |
6119 | { Bad_Opcode }, |
6120 | { Bad_Opcode }, | |
bf890a93 | 6121 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6122 | }, |
6123 | ||
592a252b | 6124 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6125 | { |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
bf890a93 | 6128 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6129 | }, |
6130 | ||
592a252b | 6131 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6132 | { |
592d1631 L |
6133 | { Bad_Opcode }, |
6134 | { Bad_Opcode }, | |
bf890a93 | 6135 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6136 | }, |
6137 | ||
592a252b | 6138 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6139 | { |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
bf890a93 | 6142 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6143 | }, |
6144 | ||
592a252b | 6145 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6146 | { |
592d1631 L |
6147 | { Bad_Opcode }, |
6148 | { Bad_Opcode }, | |
bf890a93 | 6149 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6150 | }, |
6151 | ||
592a252b | 6152 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6153 | { |
592d1631 L |
6154 | { Bad_Opcode }, |
6155 | { Bad_Opcode }, | |
bf890a93 | 6156 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6157 | }, |
6158 | ||
592a252b | 6159 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6160 | { |
592d1631 L |
6161 | { Bad_Opcode }, |
6162 | { Bad_Opcode }, | |
bf890a93 | 6163 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6164 | }, |
6165 | ||
592a252b | 6166 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6167 | { |
592d1631 L |
6168 | { Bad_Opcode }, |
6169 | { Bad_Opcode }, | |
bf890a93 | 6170 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6171 | }, |
6172 | ||
592a252b | 6173 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6174 | { |
592d1631 L |
6175 | { Bad_Opcode }, |
6176 | { Bad_Opcode }, | |
bf890a93 | 6177 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6178 | }, |
6179 | ||
592a252b | 6180 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6181 | { |
592d1631 L |
6182 | { Bad_Opcode }, |
6183 | { Bad_Opcode }, | |
bf890a93 | 6184 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6185 | }, |
6186 | ||
592a252b | 6187 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6188 | { |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
bf890a93 | 6191 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6192 | }, |
6193 | ||
592a252b | 6194 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6195 | { |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
bf890a93 | 6198 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6199 | }, |
6200 | ||
592a252b | 6201 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6202 | { |
592d1631 L |
6203 | { Bad_Opcode }, |
6204 | { Bad_Opcode }, | |
bf890a93 | 6205 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6206 | }, |
6207 | ||
592a252b | 6208 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6209 | { |
592d1631 L |
6210 | { Bad_Opcode }, |
6211 | { Bad_Opcode }, | |
bf890a93 | 6212 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
bf890a93 | 6219 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
bf890a93 | 6226 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
bf890a93 | 6233 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
bf890a93 | 6240 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6241 | }, |
6242 | ||
592a252b | 6243 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6244 | { |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
592a252b | 6247 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6248 | }, |
6249 | ||
592a252b | 6250 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6251 | { |
592d1631 L |
6252 | { Bad_Opcode }, |
6253 | { Bad_Opcode }, | |
592a252b | 6254 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
592a252b | 6261 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
592a252b | 6268 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
592a252b | 6275 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6276 | }, |
6277 | ||
f12dc422 L |
6278 | /* PREFIX_VEX_0F38F2 */ |
6279 | { | |
6280 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6281 | }, | |
6282 | ||
6283 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6284 | { | |
6285 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6286 | }, | |
6287 | ||
6288 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6289 | { | |
6290 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6291 | }, | |
6292 | ||
6293 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6294 | { | |
6295 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6296 | }, | |
6297 | ||
6c30d220 L |
6298 | /* PREFIX_VEX_0F38F5 */ |
6299 | { | |
6300 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6301 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6302 | { Bad_Opcode }, | |
6303 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6304 | }, | |
6305 | ||
6306 | /* PREFIX_VEX_0F38F6 */ | |
6307 | { | |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { Bad_Opcode }, | |
6311 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6312 | }, | |
6313 | ||
f12dc422 L |
6314 | /* PREFIX_VEX_0F38F7 */ |
6315 | { | |
6316 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6317 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6318 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6319 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6320 | }, | |
6321 | ||
6322 | /* PREFIX_VEX_0F3A00 */ | |
6323 | { | |
6324 | { Bad_Opcode }, | |
6325 | { Bad_Opcode }, | |
6326 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6327 | }, | |
6328 | ||
6329 | /* PREFIX_VEX_0F3A01 */ | |
6330 | { | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
6333 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6334 | }, | |
6335 | ||
6336 | /* PREFIX_VEX_0F3A02 */ | |
6337 | { | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
6340 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6341 | }, |
6342 | ||
592a252b | 6343 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6344 | { |
592d1631 L |
6345 | { Bad_Opcode }, |
6346 | { Bad_Opcode }, | |
592a252b | 6347 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6348 | }, |
6349 | ||
592a252b | 6350 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6351 | { |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
592a252b | 6354 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
592a252b | 6361 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
592a252b | 6368 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6369 | }, |
6370 | ||
592a252b | 6371 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6372 | { |
592d1631 L |
6373 | { Bad_Opcode }, |
6374 | { Bad_Opcode }, | |
592a252b | 6375 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6376 | }, |
6377 | ||
592a252b | 6378 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6379 | { |
592d1631 L |
6380 | { Bad_Opcode }, |
6381 | { Bad_Opcode }, | |
592a252b | 6382 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6383 | }, |
6384 | ||
592a252b | 6385 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6386 | { |
592d1631 L |
6387 | { Bad_Opcode }, |
6388 | { Bad_Opcode }, | |
592a252b | 6389 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6390 | }, |
6391 | ||
592a252b | 6392 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6393 | { |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
592a252b | 6396 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6397 | }, |
6398 | ||
592a252b | 6399 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6400 | { |
592d1631 L |
6401 | { Bad_Opcode }, |
6402 | { Bad_Opcode }, | |
592a252b | 6403 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6404 | }, |
6405 | ||
592a252b | 6406 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6407 | { |
592d1631 L |
6408 | { Bad_Opcode }, |
6409 | { Bad_Opcode }, | |
6c30d220 | 6410 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6411 | }, |
6412 | ||
592a252b | 6413 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6414 | { |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
6c30d220 | 6417 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6418 | }, |
6419 | ||
592a252b | 6420 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6421 | { |
592d1631 L |
6422 | { Bad_Opcode }, |
6423 | { Bad_Opcode }, | |
592a252b | 6424 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6425 | }, |
6426 | ||
592a252b | 6427 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6428 | { |
592d1631 L |
6429 | { Bad_Opcode }, |
6430 | { Bad_Opcode }, | |
592a252b | 6431 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6432 | }, |
6433 | ||
592a252b | 6434 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6435 | { |
592d1631 L |
6436 | { Bad_Opcode }, |
6437 | { Bad_Opcode }, | |
592a252b | 6438 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6439 | }, |
6440 | ||
592a252b | 6441 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6442 | { |
592d1631 L |
6443 | { Bad_Opcode }, |
6444 | { Bad_Opcode }, | |
592a252b | 6445 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6446 | }, |
6447 | ||
592a252b | 6448 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6449 | { |
592d1631 L |
6450 | { Bad_Opcode }, |
6451 | { Bad_Opcode }, | |
592a252b | 6452 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6453 | }, |
6454 | ||
592a252b | 6455 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6456 | { |
592d1631 L |
6457 | { Bad_Opcode }, |
6458 | { Bad_Opcode }, | |
592a252b | 6459 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6460 | }, |
6461 | ||
592a252b | 6462 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6463 | { |
6464 | { Bad_Opcode }, | |
6465 | { Bad_Opcode }, | |
bf890a93 | 6466 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6467 | }, |
6468 | ||
592a252b | 6469 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6470 | { |
592d1631 L |
6471 | { Bad_Opcode }, |
6472 | { Bad_Opcode }, | |
592a252b | 6473 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6474 | }, |
6475 | ||
592a252b | 6476 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6477 | { |
592d1631 L |
6478 | { Bad_Opcode }, |
6479 | { Bad_Opcode }, | |
592a252b | 6480 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6481 | }, |
6482 | ||
592a252b | 6483 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6484 | { |
592d1631 L |
6485 | { Bad_Opcode }, |
6486 | { Bad_Opcode }, | |
592a252b | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6488 | }, |
6489 | ||
43234a1e L |
6490 | /* PREFIX_VEX_0F3A30 */ |
6491 | { | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6495 | }, | |
6496 | ||
1ba585e8 IT |
6497 | /* PREFIX_VEX_0F3A31 */ |
6498 | { | |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6502 | }, | |
6503 | ||
43234a1e L |
6504 | /* PREFIX_VEX_0F3A32 */ |
6505 | { | |
6506 | { Bad_Opcode }, | |
6507 | { Bad_Opcode }, | |
6508 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6509 | }, | |
6510 | ||
1ba585e8 IT |
6511 | /* PREFIX_VEX_0F3A33 */ |
6512 | { | |
6513 | { Bad_Opcode }, | |
6514 | { Bad_Opcode }, | |
6515 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6516 | }, | |
6517 | ||
6c30d220 L |
6518 | /* PREFIX_VEX_0F3A38 */ |
6519 | { | |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
6522 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6523 | }, | |
6524 | ||
6525 | /* PREFIX_VEX_0F3A39 */ | |
6526 | { | |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6530 | }, | |
6531 | ||
592a252b | 6532 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6533 | { |
592d1631 L |
6534 | { Bad_Opcode }, |
6535 | { Bad_Opcode }, | |
592a252b | 6536 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6537 | }, |
6538 | ||
592a252b | 6539 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6540 | { |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
592a252b | 6543 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6544 | }, |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
6c30d220 | 6550 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
592a252b | 6557 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6558 | }, |
6559 | ||
6c30d220 L |
6560 | /* PREFIX_VEX_0F3A46 */ |
6561 | { | |
6562 | { Bad_Opcode }, | |
6563 | { Bad_Opcode }, | |
6564 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6565 | }, | |
6566 | ||
592a252b | 6567 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6568 | { |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
592a252b | 6571 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6572 | }, |
6573 | ||
592a252b | 6574 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6575 | { |
6576 | { Bad_Opcode }, | |
6577 | { Bad_Opcode }, | |
592a252b | 6578 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6579 | }, |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6582 | { |
592d1631 L |
6583 | { Bad_Opcode }, |
6584 | { Bad_Opcode }, | |
592a252b | 6585 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6589 | { |
592d1631 L |
6590 | { Bad_Opcode }, |
6591 | { Bad_Opcode }, | |
592a252b | 6592 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
6c30d220 | 6599 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6600 | }, |
6601 | ||
592a252b | 6602 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6603 | { |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
bf890a93 | 6606 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6607 | }, |
6608 | ||
592a252b | 6609 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6610 | { |
592d1631 L |
6611 | { Bad_Opcode }, |
6612 | { Bad_Opcode }, | |
bf890a93 | 6613 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6614 | }, |
6615 | ||
592a252b | 6616 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6617 | { |
592d1631 L |
6618 | { Bad_Opcode }, |
6619 | { Bad_Opcode }, | |
bf890a93 | 6620 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
bf890a93 | 6627 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
592a252b | 6634 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6635 | { Bad_Opcode }, |
c0f3af97 L |
6636 | }, |
6637 | ||
592a252b | 6638 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6639 | { |
592d1631 L |
6640 | { Bad_Opcode }, |
6641 | { Bad_Opcode }, | |
592a252b | 6642 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6643 | }, |
6644 | ||
592a252b | 6645 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6646 | { |
592d1631 L |
6647 | { Bad_Opcode }, |
6648 | { Bad_Opcode }, | |
592a252b | 6649 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6650 | }, |
6651 | ||
592a252b | 6652 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6653 | { |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
592a252b | 6656 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6657 | }, |
a5ff0eb2 | 6658 | |
592a252b | 6659 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6660 | { |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
bf890a93 | 6663 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6664 | }, |
6665 | ||
592a252b | 6666 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6667 | { |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
bf890a93 | 6670 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6671 | }, |
6672 | ||
592a252b | 6673 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6674 | { |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
592a252b | 6677 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6678 | }, |
6679 | ||
592a252b | 6680 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6681 | { |
592d1631 L |
6682 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, | |
592a252b | 6684 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6685 | }, |
6686 | ||
592a252b | 6687 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6688 | { |
592d1631 L |
6689 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, | |
bf890a93 | 6691 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6692 | }, |
6693 | ||
592a252b | 6694 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6695 | { |
592d1631 L |
6696 | { Bad_Opcode }, |
6697 | { Bad_Opcode }, | |
bf890a93 | 6698 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6699 | }, |
6700 | ||
592a252b | 6701 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6702 | { |
592d1631 L |
6703 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, | |
592a252b | 6705 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6706 | }, |
6707 | ||
592a252b | 6708 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6709 | { |
592d1631 L |
6710 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, | |
592a252b | 6712 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6713 | }, |
6714 | ||
592a252b | 6715 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6716 | { |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
bf890a93 | 6719 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6720 | }, |
6721 | ||
592a252b | 6722 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6723 | { |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
bf890a93 | 6726 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6727 | }, |
6728 | ||
592a252b | 6729 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6730 | { |
592d1631 L |
6731 | { Bad_Opcode }, |
6732 | { Bad_Opcode }, | |
592a252b | 6733 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6734 | }, |
6735 | ||
592a252b | 6736 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6737 | { |
592d1631 L |
6738 | { Bad_Opcode }, |
6739 | { Bad_Opcode }, | |
592a252b | 6740 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6741 | }, |
6742 | ||
592a252b | 6743 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6744 | { |
592d1631 L |
6745 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, | |
bf890a93 | 6747 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 6748 | { Bad_Opcode }, |
922d8de8 DR |
6749 | }, |
6750 | ||
592a252b | 6751 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6752 | { |
592d1631 L |
6753 | { Bad_Opcode }, |
6754 | { Bad_Opcode }, | |
bf890a93 | 6755 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6756 | }, |
6757 | ||
592a252b | 6758 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6759 | { |
592d1631 L |
6760 | { Bad_Opcode }, |
6761 | { Bad_Opcode }, | |
592a252b | 6762 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6763 | }, |
6764 | ||
592a252b | 6765 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6766 | { |
592d1631 L |
6767 | { Bad_Opcode }, |
6768 | { Bad_Opcode }, | |
592a252b | 6769 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6770 | }, |
6771 | ||
592a252b | 6772 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6773 | { |
592d1631 L |
6774 | { Bad_Opcode }, |
6775 | { Bad_Opcode }, | |
592a252b | 6776 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6777 | }, |
6c30d220 L |
6778 | |
6779 | /* PREFIX_VEX_0F3AF0 */ | |
6780 | { | |
6781 | { Bad_Opcode }, | |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
6784 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6785 | }, | |
43234a1e L |
6786 | |
6787 | #define NEED_PREFIX_TABLE | |
6788 | #include "i386-dis-evex.h" | |
6789 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6790 | }; |
6791 | ||
6792 | static const struct dis386 x86_64_table[][2] = { | |
6793 | /* X86_64_06 */ | |
6794 | { | |
bf890a93 | 6795 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6796 | }, |
6797 | ||
6798 | /* X86_64_07 */ | |
6799 | { | |
bf890a93 | 6800 | { "popP", { es }, 0 }, |
c0f3af97 L |
6801 | }, |
6802 | ||
6803 | /* X86_64_0D */ | |
6804 | { | |
bf890a93 | 6805 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6806 | }, |
6807 | ||
6808 | /* X86_64_16 */ | |
6809 | { | |
bf890a93 | 6810 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6811 | }, |
6812 | ||
6813 | /* X86_64_17 */ | |
6814 | { | |
bf890a93 | 6815 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6816 | }, |
6817 | ||
6818 | /* X86_64_1E */ | |
6819 | { | |
bf890a93 | 6820 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6821 | }, |
6822 | ||
6823 | /* X86_64_1F */ | |
6824 | { | |
bf890a93 | 6825 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6826 | }, |
6827 | ||
6828 | /* X86_64_27 */ | |
6829 | { | |
bf890a93 | 6830 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6831 | }, |
6832 | ||
6833 | /* X86_64_2F */ | |
6834 | { | |
bf890a93 | 6835 | { "das", { XX }, 0 }, |
c0f3af97 L |
6836 | }, |
6837 | ||
6838 | /* X86_64_37 */ | |
6839 | { | |
bf890a93 | 6840 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6841 | }, |
6842 | ||
6843 | /* X86_64_3F */ | |
6844 | { | |
bf890a93 | 6845 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6846 | }, |
6847 | ||
6848 | /* X86_64_60 */ | |
6849 | { | |
bf890a93 | 6850 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6851 | }, |
6852 | ||
6853 | /* X86_64_61 */ | |
6854 | { | |
bf890a93 | 6855 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6856 | }, |
6857 | ||
6858 | /* X86_64_62 */ | |
6859 | { | |
6860 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6861 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6862 | }, |
6863 | ||
6864 | /* X86_64_63 */ | |
6865 | { | |
bf890a93 IT |
6866 | { "arpl", { Ew, Gw }, 0 }, |
6867 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6868 | }, |
6869 | ||
6870 | /* X86_64_6D */ | |
6871 | { | |
bf890a93 IT |
6872 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6873 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6874 | }, |
6875 | ||
6876 | /* X86_64_6F */ | |
6877 | { | |
bf890a93 IT |
6878 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6879 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6880 | }, |
6881 | ||
6882 | /* X86_64_9A */ | |
6883 | { | |
bf890a93 | 6884 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6885 | }, |
6886 | ||
6887 | /* X86_64_C4 */ | |
6888 | { | |
6889 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6890 | { VEX_C4_TABLE (VEX_0F) }, | |
6891 | }, | |
6892 | ||
6893 | /* X86_64_C5 */ | |
6894 | { | |
6895 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6896 | { VEX_C5_TABLE (VEX_0F) }, | |
6897 | }, | |
6898 | ||
6899 | /* X86_64_CE */ | |
6900 | { | |
bf890a93 | 6901 | { "into", { XX }, 0 }, |
c0f3af97 L |
6902 | }, |
6903 | ||
6904 | /* X86_64_D4 */ | |
6905 | { | |
bf890a93 | 6906 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6907 | }, |
6908 | ||
6909 | /* X86_64_D5 */ | |
6910 | { | |
bf890a93 | 6911 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6912 | }, |
6913 | ||
a72d2af2 L |
6914 | /* X86_64_E8 */ |
6915 | { | |
6916 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6917 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6918 | }, |
6919 | ||
6920 | /* X86_64_E9 */ | |
6921 | { | |
6922 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6923 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6924 | }, |
6925 | ||
c0f3af97 L |
6926 | /* X86_64_EA */ |
6927 | { | |
bf890a93 | 6928 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6929 | }, |
6930 | ||
6931 | /* X86_64_0F01_REG_0 */ | |
6932 | { | |
bf890a93 IT |
6933 | { "sgdt{Q|IQ}", { M }, 0 }, |
6934 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6935 | }, |
6936 | ||
6937 | /* X86_64_0F01_REG_1 */ | |
6938 | { | |
bf890a93 IT |
6939 | { "sidt{Q|IQ}", { M }, 0 }, |
6940 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6941 | }, |
6942 | ||
6943 | /* X86_64_0F01_REG_2 */ | |
6944 | { | |
bf890a93 IT |
6945 | { "lgdt{Q|Q}", { M }, 0 }, |
6946 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6947 | }, |
6948 | ||
6949 | /* X86_64_0F01_REG_3 */ | |
6950 | { | |
bf890a93 IT |
6951 | { "lidt{Q|Q}", { M }, 0 }, |
6952 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6953 | }, |
6954 | }; | |
6955 | ||
6956 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6957 | |
6958 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6959 | { |
6960 | /* 00 */ | |
507bd325 L |
6961 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6962 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6963 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6964 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6965 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6966 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6967 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6968 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6969 | /* 08 */ |
507bd325 L |
6970 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6971 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6972 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6973 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6974 | { Bad_Opcode }, |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
f88c9eb0 SP |
6978 | /* 10 */ |
6979 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6980 | { Bad_Opcode }, |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
f88c9eb0 SP |
6983 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6984 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6985 | { Bad_Opcode }, |
f88c9eb0 SP |
6986 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6987 | /* 18 */ | |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
507bd325 L |
6992 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6993 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6994 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6995 | { Bad_Opcode }, |
f88c9eb0 SP |
6996 | /* 20 */ |
6997 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6998 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6999 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7000 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7001 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7002 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7003 | { Bad_Opcode }, |
7004 | { Bad_Opcode }, | |
f88c9eb0 SP |
7005 | /* 28 */ |
7006 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7007 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7008 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7009 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7010 | { Bad_Opcode }, |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
f88c9eb0 SP |
7014 | /* 30 */ |
7015 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7017 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7018 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7019 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7020 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7021 | { Bad_Opcode }, |
f88c9eb0 SP |
7022 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7023 | /* 38 */ | |
7024 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7025 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7026 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7027 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7028 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7029 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7030 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7031 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7032 | /* 40 */ | |
7033 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7034 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7035 | { Bad_Opcode }, |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
f88c9eb0 | 7041 | /* 48 */ |
592d1631 L |
7042 | { Bad_Opcode }, |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
f88c9eb0 | 7050 | /* 50 */ |
592d1631 L |
7051 | { Bad_Opcode }, |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
f88c9eb0 | 7059 | /* 58 */ |
592d1631 L |
7060 | { Bad_Opcode }, |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
f88c9eb0 | 7068 | /* 60 */ |
592d1631 L |
7069 | { Bad_Opcode }, |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
f88c9eb0 | 7077 | /* 68 */ |
592d1631 L |
7078 | { Bad_Opcode }, |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
f88c9eb0 | 7086 | /* 70 */ |
592d1631 L |
7087 | { Bad_Opcode }, |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
f88c9eb0 | 7095 | /* 78 */ |
592d1631 L |
7096 | { Bad_Opcode }, |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
f88c9eb0 SP |
7104 | /* 80 */ |
7105 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7106 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7107 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7108 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
f88c9eb0 | 7113 | /* 88 */ |
592d1631 L |
7114 | { Bad_Opcode }, |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
f88c9eb0 | 7122 | /* 90 */ |
592d1631 L |
7123 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
f88c9eb0 | 7131 | /* 98 */ |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
f88c9eb0 | 7140 | /* a0 */ |
592d1631 L |
7141 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
f88c9eb0 | 7149 | /* a8 */ |
592d1631 L |
7150 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
f88c9eb0 | 7158 | /* b0 */ |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
f88c9eb0 | 7167 | /* b8 */ |
592d1631 L |
7168 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
f88c9eb0 | 7176 | /* c0 */ |
592d1631 L |
7177 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
f88c9eb0 | 7185 | /* c8 */ |
a0046408 L |
7186 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7187 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7188 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7189 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7190 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7191 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7192 | { Bad_Opcode }, |
7193 | { Bad_Opcode }, | |
f88c9eb0 | 7194 | /* d0 */ |
592d1631 L |
7195 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
f88c9eb0 | 7203 | /* d8 */ |
592d1631 L |
7204 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
f88c9eb0 SP |
7207 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7208 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7209 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7210 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7211 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7212 | /* e0 */ | |
592d1631 L |
7213 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
f88c9eb0 | 7221 | /* e8 */ |
592d1631 L |
7222 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
f88c9eb0 SP |
7230 | /* f0 */ |
7231 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7232 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7233 | { Bad_Opcode }, |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
e2e1fcde | 7237 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7238 | { Bad_Opcode }, |
f88c9eb0 | 7239 | /* f8 */ |
592d1631 L |
7240 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
f88c9eb0 SP |
7248 | }, |
7249 | /* THREE_BYTE_0F3A */ | |
7250 | { | |
7251 | /* 00 */ | |
592d1631 L |
7252 | { Bad_Opcode }, |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
f88c9eb0 SP |
7260 | /* 08 */ |
7261 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7264 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7265 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7266 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7267 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7268 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7269 | /* 10 */ |
592d1631 L |
7270 | { Bad_Opcode }, |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 SP |
7274 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7275 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7276 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7277 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7278 | /* 18 */ | |
592d1631 L |
7279 | { Bad_Opcode }, |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
f88c9eb0 SP |
7287 | /* 20 */ |
7288 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7289 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7290 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7291 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
f88c9eb0 | 7296 | /* 28 */ |
592d1631 L |
7297 | { Bad_Opcode }, |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
f88c9eb0 | 7305 | /* 30 */ |
592d1631 L |
7306 | { Bad_Opcode }, |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
f88c9eb0 | 7314 | /* 38 */ |
592d1631 L |
7315 | { Bad_Opcode }, |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
f88c9eb0 SP |
7323 | /* 40 */ |
7324 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7325 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7326 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7327 | { Bad_Opcode }, |
f88c9eb0 | 7328 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7329 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
f88c9eb0 | 7332 | /* 48 */ |
592d1631 L |
7333 | { Bad_Opcode }, |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
f88c9eb0 | 7341 | /* 50 */ |
592d1631 L |
7342 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
f88c9eb0 | 7350 | /* 58 */ |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
f88c9eb0 SP |
7359 | /* 60 */ |
7360 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7361 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7362 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7363 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7364 | { Bad_Opcode }, |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
f88c9eb0 | 7368 | /* 68 */ |
592d1631 L |
7369 | { Bad_Opcode }, |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
f88c9eb0 | 7377 | /* 70 */ |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
f88c9eb0 | 7386 | /* 78 */ |
592d1631 L |
7387 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
f88c9eb0 | 7395 | /* 80 */ |
592d1631 L |
7396 | { Bad_Opcode }, |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
f88c9eb0 | 7404 | /* 88 */ |
592d1631 L |
7405 | { Bad_Opcode }, |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
f88c9eb0 | 7413 | /* 90 */ |
592d1631 L |
7414 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
f88c9eb0 | 7422 | /* 98 */ |
592d1631 L |
7423 | { Bad_Opcode }, |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
f88c9eb0 | 7431 | /* a0 */ |
592d1631 L |
7432 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
f88c9eb0 | 7440 | /* a8 */ |
592d1631 L |
7441 | { Bad_Opcode }, |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
f88c9eb0 | 7449 | /* b0 */ |
592d1631 L |
7450 | { Bad_Opcode }, |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
f88c9eb0 | 7458 | /* b8 */ |
592d1631 L |
7459 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
f88c9eb0 | 7467 | /* c0 */ |
592d1631 L |
7468 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
f88c9eb0 | 7476 | /* c8 */ |
592d1631 L |
7477 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
a0046408 | 7481 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7482 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
f88c9eb0 | 7485 | /* d0 */ |
592d1631 L |
7486 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
f88c9eb0 | 7494 | /* d8 */ |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
f88c9eb0 SP |
7502 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7503 | /* e0 */ | |
592d1631 L |
7504 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
f88c9eb0 | 7512 | /* e8 */ |
592d1631 L |
7513 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
f88c9eb0 | 7521 | /* f0 */ |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
f88c9eb0 | 7530 | /* f8 */ |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
f88c9eb0 SP |
7539 | }, |
7540 | ||
7541 | /* THREE_BYTE_0F7A */ | |
7542 | { | |
7543 | /* 00 */ | |
592d1631 L |
7544 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
f88c9eb0 | 7552 | /* 08 */ |
592d1631 L |
7553 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
f88c9eb0 | 7561 | /* 10 */ |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
f88c9eb0 | 7570 | /* 18 */ |
592d1631 L |
7571 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
f88c9eb0 | 7579 | /* 20 */ |
507bd325 | 7580 | { "ptest", { XX }, PREFIX_OPCODE }, |
592d1631 L |
7581 | { Bad_Opcode }, |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
f88c9eb0 | 7588 | /* 28 */ |
592d1631 L |
7589 | { Bad_Opcode }, |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
f88c9eb0 | 7597 | /* 30 */ |
592d1631 L |
7598 | { Bad_Opcode }, |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
f88c9eb0 | 7606 | /* 38 */ |
592d1631 L |
7607 | { Bad_Opcode }, |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
f88c9eb0 | 7615 | /* 40 */ |
592d1631 | 7616 | { Bad_Opcode }, |
507bd325 L |
7617 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7618 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, | |
7619 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7620 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, | |
507bd325 L |
7622 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7623 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7624 | /* 48 */ |
592d1631 L |
7625 | { Bad_Opcode }, |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
507bd325 | 7628 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7629 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
f88c9eb0 | 7633 | /* 50 */ |
592d1631 | 7634 | { Bad_Opcode }, |
507bd325 L |
7635 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7636 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, | |
7637 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7638 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, | |
507bd325 L |
7640 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7641 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7642 | /* 58 */ |
592d1631 L |
7643 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
507bd325 | 7646 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7647 | { Bad_Opcode }, |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
f88c9eb0 | 7651 | /* 60 */ |
592d1631 | 7652 | { Bad_Opcode }, |
507bd325 L |
7653 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7654 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, | |
7655 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7656 | { Bad_Opcode }, |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
4e7d34a6 | 7660 | /* 68 */ |
592d1631 L |
7661 | { Bad_Opcode }, |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
85f10a01 | 7669 | /* 70 */ |
592d1631 L |
7670 | { Bad_Opcode }, |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
85f10a01 | 7678 | /* 78 */ |
592d1631 L |
7679 | { Bad_Opcode }, |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
85f10a01 | 7687 | /* 80 */ |
592d1631 L |
7688 | { Bad_Opcode }, |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
85f10a01 | 7696 | /* 88 */ |
592d1631 L |
7697 | { Bad_Opcode }, |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
85f10a01 | 7705 | /* 90 */ |
592d1631 L |
7706 | { Bad_Opcode }, |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
85f10a01 | 7714 | /* 98 */ |
592d1631 L |
7715 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
85f10a01 | 7723 | /* a0 */ |
592d1631 L |
7724 | { Bad_Opcode }, |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
85f10a01 | 7732 | /* a8 */ |
592d1631 L |
7733 | { Bad_Opcode }, |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
85f10a01 | 7741 | /* b0 */ |
592d1631 L |
7742 | { Bad_Opcode }, |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
85f10a01 | 7750 | /* b8 */ |
592d1631 L |
7751 | { Bad_Opcode }, |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
85f10a01 | 7759 | /* c0 */ |
592d1631 L |
7760 | { Bad_Opcode }, |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
85f10a01 | 7768 | /* c8 */ |
592d1631 L |
7769 | { Bad_Opcode }, |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
85f10a01 | 7777 | /* d0 */ |
592d1631 L |
7778 | { Bad_Opcode }, |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
85f10a01 | 7786 | /* d8 */ |
592d1631 L |
7787 | { Bad_Opcode }, |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
85f10a01 | 7795 | /* e0 */ |
592d1631 L |
7796 | { Bad_Opcode }, |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
85f10a01 | 7804 | /* e8 */ |
592d1631 L |
7805 | { Bad_Opcode }, |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
85f10a01 | 7813 | /* f0 */ |
592d1631 L |
7814 | { Bad_Opcode }, |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
85f10a01 | 7822 | /* f8 */ |
592d1631 L |
7823 | { Bad_Opcode }, |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
85f10a01 | 7831 | }, |
f88c9eb0 SP |
7832 | }; |
7833 | ||
7834 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7835 | /* XOP_08 */ |
85f10a01 MM |
7836 | { |
7837 | /* 00 */ | |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
85f10a01 | 7846 | /* 08 */ |
592d1631 L |
7847 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
85f10a01 | 7855 | /* 10 */ |
3929df09 | 7856 | { Bad_Opcode }, |
592d1631 L |
7857 | { Bad_Opcode }, |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
85f10a01 | 7864 | /* 18 */ |
592d1631 L |
7865 | { Bad_Opcode }, |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
85f10a01 | 7873 | /* 20 */ |
592d1631 L |
7874 | { Bad_Opcode }, |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
85f10a01 | 7882 | /* 28 */ |
592d1631 L |
7883 | { Bad_Opcode }, |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
c0f3af97 | 7891 | /* 30 */ |
592d1631 L |
7892 | { Bad_Opcode }, |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
c0f3af97 | 7900 | /* 38 */ |
592d1631 L |
7901 | { Bad_Opcode }, |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
c0f3af97 | 7909 | /* 40 */ |
592d1631 L |
7910 | { Bad_Opcode }, |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
85f10a01 | 7918 | /* 48 */ |
592d1631 L |
7919 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
c0f3af97 | 7927 | /* 50 */ |
592d1631 L |
7928 | { Bad_Opcode }, |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
85f10a01 | 7936 | /* 58 */ |
592d1631 L |
7937 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
c1e679ec | 7945 | /* 60 */ |
592d1631 L |
7946 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
c0f3af97 | 7954 | /* 68 */ |
592d1631 L |
7955 | { Bad_Opcode }, |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
85f10a01 | 7963 | /* 70 */ |
592d1631 L |
7964 | { Bad_Opcode }, |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
85f10a01 | 7972 | /* 78 */ |
592d1631 L |
7973 | { Bad_Opcode }, |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
85f10a01 | 7981 | /* 80 */ |
592d1631 L |
7982 | { Bad_Opcode }, |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
bf890a93 IT |
7987 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7988 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7989 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7990 | /* 88 */ |
592d1631 L |
7991 | { Bad_Opcode }, |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
bf890a93 IT |
7997 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7998 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7999 | /* 90 */ |
592d1631 L |
8000 | { Bad_Opcode }, |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
bf890a93 IT |
8005 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8006 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
8007 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8008 | /* 98 */ |
592d1631 L |
8009 | { Bad_Opcode }, |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
bf890a93 IT |
8015 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8016 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8017 | /* a0 */ |
592d1631 L |
8018 | { Bad_Opcode }, |
8019 | { Bad_Opcode }, | |
bf890a93 IT |
8020 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8021 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
592d1631 L |
8022 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, | |
bf890a93 | 8024 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 8025 | { Bad_Opcode }, |
5dd85c99 | 8026 | /* a8 */ |
592d1631 L |
8027 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
5dd85c99 | 8035 | /* b0 */ |
592d1631 L |
8036 | { Bad_Opcode }, |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
bf890a93 | 8042 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 8043 | { Bad_Opcode }, |
5dd85c99 | 8044 | /* b8 */ |
592d1631 L |
8045 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
5dd85c99 | 8053 | /* c0 */ |
bf890a93 IT |
8054 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
8055 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
8056 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
8057 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
8058 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
5dd85c99 | 8062 | /* c8 */ |
592d1631 L |
8063 | { Bad_Opcode }, |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
ff688e1f L |
8067 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8068 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
8069 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
8070 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 8071 | /* d0 */ |
592d1631 L |
8072 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
5dd85c99 | 8080 | /* d8 */ |
592d1631 L |
8081 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
5dd85c99 | 8089 | /* e0 */ |
592d1631 L |
8090 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
5dd85c99 | 8098 | /* e8 */ |
592d1631 L |
8099 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
ff688e1f L |
8103 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8104 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
8105 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
8106 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8107 | /* f0 */ |
592d1631 L |
8108 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
5dd85c99 | 8116 | /* f8 */ |
592d1631 L |
8117 | { Bad_Opcode }, |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
5dd85c99 SP |
8125 | }, |
8126 | /* XOP_09 */ | |
8127 | { | |
8128 | /* 00 */ | |
592d1631 | 8129 | { Bad_Opcode }, |
2a2a0f38 QN |
8130 | { REG_TABLE (REG_XOP_TBM_01) }, |
8131 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8132 | { Bad_Opcode }, |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
5dd85c99 | 8137 | /* 08 */ |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
5dd85c99 | 8146 | /* 10 */ |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
5dd85c99 | 8149 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8150 | { Bad_Opcode }, |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
5dd85c99 | 8155 | /* 18 */ |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
5dd85c99 | 8164 | /* 20 */ |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
5dd85c99 | 8173 | /* 28 */ |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
5dd85c99 | 8182 | /* 30 */ |
592d1631 L |
8183 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
5dd85c99 | 8191 | /* 38 */ |
592d1631 L |
8192 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
5dd85c99 | 8200 | /* 40 */ |
592d1631 L |
8201 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
5dd85c99 | 8209 | /* 48 */ |
592d1631 L |
8210 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
5dd85c99 | 8218 | /* 50 */ |
592d1631 L |
8219 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
5dd85c99 | 8227 | /* 58 */ |
592d1631 L |
8228 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
5dd85c99 | 8236 | /* 60 */ |
592d1631 L |
8237 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
5dd85c99 | 8245 | /* 68 */ |
592d1631 L |
8246 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
5dd85c99 | 8254 | /* 70 */ |
592d1631 L |
8255 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
5dd85c99 | 8263 | /* 78 */ |
592d1631 L |
8264 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
5dd85c99 | 8272 | /* 80 */ |
592a252b L |
8273 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8274 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8275 | { "vfrczss", { XM, EXd }, 0 }, |
8276 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8277 | { Bad_Opcode }, |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
5dd85c99 | 8281 | /* 88 */ |
592d1631 L |
8282 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
5dd85c99 | 8290 | /* 90 */ |
bf890a93 IT |
8291 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8292 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8293 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8294 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8295 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8296 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8297 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8298 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8299 | /* 98 */ |
bf890a93 IT |
8300 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8301 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8302 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8303 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8304 | { Bad_Opcode }, |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
5dd85c99 | 8308 | /* a0 */ |
592d1631 L |
8309 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
5dd85c99 | 8317 | /* a8 */ |
592d1631 L |
8318 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
5dd85c99 | 8326 | /* b0 */ |
592d1631 L |
8327 | { Bad_Opcode }, |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
5dd85c99 | 8335 | /* b8 */ |
592d1631 L |
8336 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
5dd85c99 | 8344 | /* c0 */ |
592d1631 | 8345 | { Bad_Opcode }, |
bf890a93 IT |
8346 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8347 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8348 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8349 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, | |
bf890a93 IT |
8351 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8352 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8353 | /* c8 */ |
592d1631 L |
8354 | { Bad_Opcode }, |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
bf890a93 | 8357 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8358 | { Bad_Opcode }, |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
5dd85c99 | 8362 | /* d0 */ |
592d1631 | 8363 | { Bad_Opcode }, |
bf890a93 IT |
8364 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8365 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8366 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8367 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, | |
bf890a93 IT |
8369 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8370 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8371 | /* d8 */ |
592d1631 L |
8372 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
bf890a93 | 8375 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8376 | { Bad_Opcode }, |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
5dd85c99 | 8380 | /* e0 */ |
592d1631 | 8381 | { Bad_Opcode }, |
bf890a93 IT |
8382 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8383 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8384 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8385 | { Bad_Opcode }, |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
4e7d34a6 | 8389 | /* e8 */ |
592d1631 L |
8390 | { Bad_Opcode }, |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
4e7d34a6 | 8398 | /* f0 */ |
592d1631 L |
8399 | { Bad_Opcode }, |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
4e7d34a6 | 8407 | /* f8 */ |
592d1631 L |
8408 | { Bad_Opcode }, |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
4e7d34a6 | 8416 | }, |
f88c9eb0 | 8417 | /* XOP_0A */ |
4e7d34a6 L |
8418 | { |
8419 | /* 00 */ | |
592d1631 L |
8420 | { Bad_Opcode }, |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
4e7d34a6 | 8428 | /* 08 */ |
592d1631 L |
8429 | { Bad_Opcode }, |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
4e7d34a6 | 8437 | /* 10 */ |
bf890a93 | 8438 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8439 | { Bad_Opcode }, |
f88c9eb0 | 8440 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8441 | { Bad_Opcode }, |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
4e7d34a6 | 8446 | /* 18 */ |
592d1631 L |
8447 | { Bad_Opcode }, |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
4e7d34a6 | 8455 | /* 20 */ |
592d1631 L |
8456 | { Bad_Opcode }, |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
4e7d34a6 | 8464 | /* 28 */ |
592d1631 L |
8465 | { Bad_Opcode }, |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
4e7d34a6 | 8473 | /* 30 */ |
592d1631 L |
8474 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
c0f3af97 | 8482 | /* 38 */ |
592d1631 L |
8483 | { Bad_Opcode }, |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
c0f3af97 | 8491 | /* 40 */ |
592d1631 L |
8492 | { Bad_Opcode }, |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
c1e679ec | 8500 | /* 48 */ |
592d1631 L |
8501 | { Bad_Opcode }, |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
c1e679ec | 8509 | /* 50 */ |
592d1631 L |
8510 | { Bad_Opcode }, |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
4e7d34a6 | 8518 | /* 58 */ |
592d1631 L |
8519 | { Bad_Opcode }, |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
4e7d34a6 | 8527 | /* 60 */ |
592d1631 L |
8528 | { Bad_Opcode }, |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
4e7d34a6 | 8536 | /* 68 */ |
592d1631 L |
8537 | { Bad_Opcode }, |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
4e7d34a6 | 8545 | /* 70 */ |
592d1631 L |
8546 | { Bad_Opcode }, |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
4e7d34a6 | 8554 | /* 78 */ |
592d1631 L |
8555 | { Bad_Opcode }, |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
4e7d34a6 | 8563 | /* 80 */ |
592d1631 L |
8564 | { Bad_Opcode }, |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
4e7d34a6 | 8572 | /* 88 */ |
592d1631 L |
8573 | { Bad_Opcode }, |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
8578 | { Bad_Opcode }, | |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
4e7d34a6 | 8581 | /* 90 */ |
592d1631 L |
8582 | { Bad_Opcode }, |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
4e7d34a6 | 8590 | /* 98 */ |
592d1631 L |
8591 | { Bad_Opcode }, |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
4e7d34a6 | 8599 | /* a0 */ |
592d1631 L |
8600 | { Bad_Opcode }, |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
8604 | { Bad_Opcode }, | |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
4e7d34a6 | 8608 | /* a8 */ |
592d1631 L |
8609 | { Bad_Opcode }, |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
d5d7db8e | 8617 | /* b0 */ |
592d1631 L |
8618 | { Bad_Opcode }, |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
85f10a01 | 8626 | /* b8 */ |
592d1631 L |
8627 | { Bad_Opcode }, |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
85f10a01 | 8635 | /* c0 */ |
592d1631 L |
8636 | { Bad_Opcode }, |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
85f10a01 | 8644 | /* c8 */ |
592d1631 L |
8645 | { Bad_Opcode }, |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
85f10a01 | 8653 | /* d0 */ |
592d1631 L |
8654 | { Bad_Opcode }, |
8655 | { Bad_Opcode }, | |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
85f10a01 | 8662 | /* d8 */ |
592d1631 L |
8663 | { Bad_Opcode }, |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
8670 | { Bad_Opcode }, | |
85f10a01 | 8671 | /* e0 */ |
592d1631 L |
8672 | { Bad_Opcode }, |
8673 | { Bad_Opcode }, | |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
85f10a01 | 8680 | /* e8 */ |
592d1631 L |
8681 | { Bad_Opcode }, |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
85f10a01 | 8689 | /* f0 */ |
592d1631 L |
8690 | { Bad_Opcode }, |
8691 | { Bad_Opcode }, | |
8692 | { Bad_Opcode }, | |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
85f10a01 | 8698 | /* f8 */ |
592d1631 L |
8699 | { Bad_Opcode }, |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
85f10a01 | 8707 | }, |
c0f3af97 L |
8708 | }; |
8709 | ||
8710 | static const struct dis386 vex_table[][256] = { | |
8711 | /* VEX_0F */ | |
85f10a01 MM |
8712 | { |
8713 | /* 00 */ | |
592d1631 L |
8714 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
85f10a01 | 8722 | /* 08 */ |
592d1631 L |
8723 | { Bad_Opcode }, |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
c0f3af97 | 8731 | /* 10 */ |
592a252b L |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8735 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8736 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8737 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8739 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8740 | /* 18 */ |
592d1631 L |
8741 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
8747 | { Bad_Opcode }, | |
8748 | { Bad_Opcode }, | |
c0f3af97 | 8749 | /* 20 */ |
592d1631 L |
8750 | { Bad_Opcode }, |
8751 | { Bad_Opcode }, | |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
8756 | { Bad_Opcode }, | |
8757 | { Bad_Opcode }, | |
c0f3af97 | 8758 | /* 28 */ |
592a252b L |
8759 | { VEX_W_TABLE (VEX_W_0F28) }, |
8760 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8762 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8767 | /* 30 */ |
592d1631 L |
8768 | { Bad_Opcode }, |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
8772 | { Bad_Opcode }, | |
8773 | { Bad_Opcode }, | |
8774 | { Bad_Opcode }, | |
8775 | { Bad_Opcode }, | |
4e7d34a6 | 8776 | /* 38 */ |
592d1631 L |
8777 | { Bad_Opcode }, |
8778 | { Bad_Opcode }, | |
8779 | { Bad_Opcode }, | |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
d5d7db8e | 8785 | /* 40 */ |
592d1631 | 8786 | { Bad_Opcode }, |
43234a1e L |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8789 | { Bad_Opcode }, |
43234a1e L |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8794 | /* 48 */ |
592d1631 L |
8795 | { Bad_Opcode }, |
8796 | { Bad_Opcode }, | |
1ba585e8 | 8797 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8798 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8799 | { Bad_Opcode }, |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
d5d7db8e | 8803 | /* 50 */ |
592a252b L |
8804 | { MOD_TABLE (MOD_VEX_0F50) }, |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8808 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8809 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8810 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8811 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8812 | /* 58 */ |
592a252b L |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8814 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8815 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8821 | /* 60 */ |
592a252b L |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8830 | /* 68 */ |
592a252b L |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8837 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8838 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8839 | /* 70 */ |
592a252b L |
8840 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8841 | { REG_TABLE (REG_VEX_0F71) }, | |
8842 | { REG_TABLE (REG_VEX_0F72) }, | |
8843 | { REG_TABLE (REG_VEX_0F73) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8846 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8847 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8848 | /* 78 */ |
592d1631 L |
8849 | { Bad_Opcode }, |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
592a252b L |
8853 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8854 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8855 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8856 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8857 | /* 80 */ |
592d1631 L |
8858 | { Bad_Opcode }, |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
c0f3af97 | 8866 | /* 88 */ |
592d1631 L |
8867 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
c0f3af97 | 8875 | /* 90 */ |
43234a1e L |
8876 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8877 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8878 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8879 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8880 | { Bad_Opcode }, |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
c0f3af97 | 8884 | /* 98 */ |
43234a1e | 8885 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8886 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8887 | { Bad_Opcode }, |
8888 | { Bad_Opcode }, | |
8889 | { Bad_Opcode }, | |
8890 | { Bad_Opcode }, | |
8891 | { Bad_Opcode }, | |
8892 | { Bad_Opcode }, | |
c0f3af97 | 8893 | /* a0 */ |
592d1631 L |
8894 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
8901 | { Bad_Opcode }, | |
c0f3af97 | 8902 | /* a8 */ |
592d1631 L |
8903 | { Bad_Opcode }, |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
8906 | { Bad_Opcode }, | |
8907 | { Bad_Opcode }, | |
8908 | { Bad_Opcode }, | |
592a252b | 8909 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8910 | { Bad_Opcode }, |
c0f3af97 | 8911 | /* b0 */ |
592d1631 L |
8912 | { Bad_Opcode }, |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
c0f3af97 | 8920 | /* b8 */ |
592d1631 L |
8921 | { Bad_Opcode }, |
8922 | { Bad_Opcode }, | |
8923 | { Bad_Opcode }, | |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
c0f3af97 | 8929 | /* c0 */ |
592d1631 L |
8930 | { Bad_Opcode }, |
8931 | { Bad_Opcode }, | |
592a252b | 8932 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8933 | { Bad_Opcode }, |
592a252b L |
8934 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8935 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8936 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8937 | { Bad_Opcode }, |
c0f3af97 | 8938 | /* c8 */ |
592d1631 L |
8939 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
c0f3af97 | 8947 | /* d0 */ |
592a252b L |
8948 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8949 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8951 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8955 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8956 | /* d8 */ |
592a252b L |
8957 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8958 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8959 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8960 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8961 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8962 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8963 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8965 | /* e0 */ |
592a252b L |
8966 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8967 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8968 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8969 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8970 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8971 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8972 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8973 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8974 | /* e8 */ |
592a252b L |
8975 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8976 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8981 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8982 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8983 | /* f0 */ |
592a252b L |
8984 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8985 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8992 | /* f8 */ |
592a252b L |
8993 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8997 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8998 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8999 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 9000 | { Bad_Opcode }, |
c0f3af97 L |
9001 | }, |
9002 | /* VEX_0F38 */ | |
9003 | { | |
9004 | /* 00 */ | |
592a252b L |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 9013 | /* 08 */ |
592a252b L |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 9022 | /* 10 */ |
592d1631 L |
9023 | { Bad_Opcode }, |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
592a252b | 9026 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
9027 | { Bad_Opcode }, |
9028 | { Bad_Opcode }, | |
6c30d220 | 9029 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 9030 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 9031 | /* 18 */ |
592a252b L |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 9035 | { Bad_Opcode }, |
592a252b L |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 9039 | { Bad_Opcode }, |
c0f3af97 | 9040 | /* 20 */ |
592a252b L |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
9047 | { Bad_Opcode }, |
9048 | { Bad_Opcode }, | |
c0f3af97 | 9049 | /* 28 */ |
592a252b L |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
9051 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
9053 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
9054 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 9058 | /* 30 */ |
592a252b L |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
9064 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 9065 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 9066 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 9067 | /* 38 */ |
592a252b L |
9068 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
9075 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 9076 | /* 40 */ |
592a252b L |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
6c30d220 L |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9083 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
9084 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 9085 | /* 48 */ |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
c0f3af97 | 9094 | /* 50 */ |
592d1631 L |
9095 | { Bad_Opcode }, |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
c0f3af97 | 9103 | /* 58 */ |
6c30d220 L |
9104 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9105 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9107 | { Bad_Opcode }, |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
c0f3af97 | 9112 | /* 60 */ |
592d1631 L |
9113 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
c0f3af97 | 9121 | /* 68 */ |
592d1631 L |
9122 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
c0f3af97 | 9130 | /* 70 */ |
592d1631 L |
9131 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
c0f3af97 | 9139 | /* 78 */ |
6c30d220 L |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9142 | { Bad_Opcode }, |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
c0f3af97 | 9148 | /* 80 */ |
592d1631 L |
9149 | { Bad_Opcode }, |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
c0f3af97 | 9157 | /* 88 */ |
592d1631 L |
9158 | { Bad_Opcode }, |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
6c30d220 | 9162 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9163 | { Bad_Opcode }, |
6c30d220 | 9164 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9165 | { Bad_Opcode }, |
c0f3af97 | 9166 | /* 90 */ |
6c30d220 L |
9167 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9168 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9169 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9170 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9171 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, | |
592a252b L |
9173 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9174 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9175 | /* 98 */ |
592a252b L |
9176 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9177 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9178 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9179 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9180 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9181 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9182 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9183 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9184 | /* a0 */ |
592d1631 L |
9185 | { Bad_Opcode }, |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
592a252b L |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9193 | /* a8 */ |
592a252b L |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9197 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9198 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9199 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9200 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9201 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9202 | /* b0 */ |
592d1631 L |
9203 | { Bad_Opcode }, |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
592a252b L |
9209 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9210 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9211 | /* b8 */ |
592a252b L |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9215 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9216 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9217 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9218 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9219 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9220 | /* c0 */ |
592d1631 L |
9221 | { Bad_Opcode }, |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
c0f3af97 | 9229 | /* c8 */ |
592d1631 L |
9230 | { Bad_Opcode }, |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
c0f3af97 | 9238 | /* d0 */ |
592d1631 L |
9239 | { Bad_Opcode }, |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
c0f3af97 | 9247 | /* d8 */ |
592d1631 L |
9248 | { Bad_Opcode }, |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
592a252b L |
9251 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9253 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9254 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9255 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9256 | /* e0 */ |
592d1631 L |
9257 | { Bad_Opcode }, |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
c0f3af97 | 9265 | /* e8 */ |
592d1631 L |
9266 | { Bad_Opcode }, |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
c0f3af97 | 9274 | /* f0 */ |
592d1631 L |
9275 | { Bad_Opcode }, |
9276 | { Bad_Opcode }, | |
f12dc422 L |
9277 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9278 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9279 | { Bad_Opcode }, |
6c30d220 L |
9280 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9281 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9282 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9283 | /* f8 */ |
592d1631 L |
9284 | { Bad_Opcode }, |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
9291 | { Bad_Opcode }, | |
c0f3af97 L |
9292 | }, |
9293 | /* VEX_0F3A */ | |
9294 | { | |
9295 | /* 00 */ | |
6c30d220 L |
9296 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9298 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9299 | { Bad_Opcode }, |
592a252b L |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9303 | { Bad_Opcode }, |
c0f3af97 | 9304 | /* 08 */ |
592a252b L |
9305 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9306 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9307 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9308 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9309 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9313 | /* 10 */ |
592d1631 L |
9314 | { Bad_Opcode }, |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
592a252b L |
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9320 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9321 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9322 | /* 18 */ |
592a252b L |
9323 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9324 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9325 | { Bad_Opcode }, |
9326 | { Bad_Opcode }, | |
9327 | { Bad_Opcode }, | |
592a252b | 9328 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9329 | { Bad_Opcode }, |
9330 | { Bad_Opcode }, | |
c0f3af97 | 9331 | /* 20 */ |
592a252b L |
9332 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9333 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9334 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9335 | { Bad_Opcode }, |
9336 | { Bad_Opcode }, | |
9337 | { Bad_Opcode }, | |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
c0f3af97 | 9340 | /* 28 */ |
592d1631 L |
9341 | { Bad_Opcode }, |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
9345 | { Bad_Opcode }, | |
9346 | { Bad_Opcode }, | |
9347 | { Bad_Opcode }, | |
9348 | { Bad_Opcode }, | |
c0f3af97 | 9349 | /* 30 */ |
43234a1e | 9350 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9351 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9352 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9353 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9354 | { Bad_Opcode }, |
9355 | { Bad_Opcode }, | |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
c0f3af97 | 9358 | /* 38 */ |
6c30d220 L |
9359 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9360 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9361 | { Bad_Opcode }, |
9362 | { Bad_Opcode }, | |
9363 | { Bad_Opcode }, | |
9364 | { Bad_Opcode }, | |
9365 | { Bad_Opcode }, | |
9366 | { Bad_Opcode }, | |
c0f3af97 | 9367 | /* 40 */ |
592a252b L |
9368 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9369 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9370 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9371 | { Bad_Opcode }, |
592a252b | 9372 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9373 | { Bad_Opcode }, |
6c30d220 | 9374 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9375 | { Bad_Opcode }, |
c0f3af97 | 9376 | /* 48 */ |
592a252b L |
9377 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9378 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9379 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9380 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9381 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9382 | { Bad_Opcode }, |
9383 | { Bad_Opcode }, | |
9384 | { Bad_Opcode }, | |
c0f3af97 | 9385 | /* 50 */ |
592d1631 L |
9386 | { Bad_Opcode }, |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
9389 | { Bad_Opcode }, | |
9390 | { Bad_Opcode }, | |
9391 | { Bad_Opcode }, | |
9392 | { Bad_Opcode }, | |
9393 | { Bad_Opcode }, | |
c0f3af97 | 9394 | /* 58 */ |
592d1631 L |
9395 | { Bad_Opcode }, |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
592a252b L |
9399 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9400 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9401 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9402 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9403 | /* 60 */ |
592a252b L |
9404 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9405 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9406 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9407 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9408 | { Bad_Opcode }, |
9409 | { Bad_Opcode }, | |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
c0f3af97 | 9412 | /* 68 */ |
592a252b L |
9413 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9414 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9415 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9416 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9417 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9418 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9419 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9420 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9421 | /* 70 */ |
592d1631 L |
9422 | { Bad_Opcode }, |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
9426 | { Bad_Opcode }, | |
9427 | { Bad_Opcode }, | |
9428 | { Bad_Opcode }, | |
9429 | { Bad_Opcode }, | |
c0f3af97 | 9430 | /* 78 */ |
592a252b L |
9431 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9432 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9433 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9434 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9435 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9436 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9437 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9438 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9439 | /* 80 */ |
592d1631 L |
9440 | { Bad_Opcode }, |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
9444 | { Bad_Opcode }, | |
9445 | { Bad_Opcode }, | |
9446 | { Bad_Opcode }, | |
9447 | { Bad_Opcode }, | |
c0f3af97 | 9448 | /* 88 */ |
592d1631 L |
9449 | { Bad_Opcode }, |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
9452 | { Bad_Opcode }, | |
9453 | { Bad_Opcode }, | |
9454 | { Bad_Opcode }, | |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
c0f3af97 | 9457 | /* 90 */ |
592d1631 L |
9458 | { Bad_Opcode }, |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
9461 | { Bad_Opcode }, | |
9462 | { Bad_Opcode }, | |
9463 | { Bad_Opcode }, | |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
c0f3af97 | 9466 | /* 98 */ |
592d1631 L |
9467 | { Bad_Opcode }, |
9468 | { Bad_Opcode }, | |
9469 | { Bad_Opcode }, | |
9470 | { Bad_Opcode }, | |
9471 | { Bad_Opcode }, | |
9472 | { Bad_Opcode }, | |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
c0f3af97 | 9475 | /* a0 */ |
592d1631 L |
9476 | { Bad_Opcode }, |
9477 | { Bad_Opcode }, | |
9478 | { Bad_Opcode }, | |
9479 | { Bad_Opcode }, | |
9480 | { Bad_Opcode }, | |
9481 | { Bad_Opcode }, | |
9482 | { Bad_Opcode }, | |
9483 | { Bad_Opcode }, | |
c0f3af97 | 9484 | /* a8 */ |
592d1631 L |
9485 | { Bad_Opcode }, |
9486 | { Bad_Opcode }, | |
9487 | { Bad_Opcode }, | |
9488 | { Bad_Opcode }, | |
9489 | { Bad_Opcode }, | |
9490 | { Bad_Opcode }, | |
9491 | { Bad_Opcode }, | |
9492 | { Bad_Opcode }, | |
c0f3af97 | 9493 | /* b0 */ |
592d1631 L |
9494 | { Bad_Opcode }, |
9495 | { Bad_Opcode }, | |
9496 | { Bad_Opcode }, | |
9497 | { Bad_Opcode }, | |
9498 | { Bad_Opcode }, | |
9499 | { Bad_Opcode }, | |
9500 | { Bad_Opcode }, | |
9501 | { Bad_Opcode }, | |
c0f3af97 | 9502 | /* b8 */ |
592d1631 L |
9503 | { Bad_Opcode }, |
9504 | { Bad_Opcode }, | |
9505 | { Bad_Opcode }, | |
9506 | { Bad_Opcode }, | |
9507 | { Bad_Opcode }, | |
9508 | { Bad_Opcode }, | |
9509 | { Bad_Opcode }, | |
9510 | { Bad_Opcode }, | |
c0f3af97 | 9511 | /* c0 */ |
592d1631 L |
9512 | { Bad_Opcode }, |
9513 | { Bad_Opcode }, | |
9514 | { Bad_Opcode }, | |
9515 | { Bad_Opcode }, | |
9516 | { Bad_Opcode }, | |
9517 | { Bad_Opcode }, | |
9518 | { Bad_Opcode }, | |
9519 | { Bad_Opcode }, | |
c0f3af97 | 9520 | /* c8 */ |
592d1631 L |
9521 | { Bad_Opcode }, |
9522 | { Bad_Opcode }, | |
9523 | { Bad_Opcode }, | |
9524 | { Bad_Opcode }, | |
9525 | { Bad_Opcode }, | |
9526 | { Bad_Opcode }, | |
9527 | { Bad_Opcode }, | |
9528 | { Bad_Opcode }, | |
c0f3af97 | 9529 | /* d0 */ |
592d1631 L |
9530 | { Bad_Opcode }, |
9531 | { Bad_Opcode }, | |
9532 | { Bad_Opcode }, | |
9533 | { Bad_Opcode }, | |
9534 | { Bad_Opcode }, | |
9535 | { Bad_Opcode }, | |
9536 | { Bad_Opcode }, | |
9537 | { Bad_Opcode }, | |
c0f3af97 | 9538 | /* d8 */ |
592d1631 L |
9539 | { Bad_Opcode }, |
9540 | { Bad_Opcode }, | |
9541 | { Bad_Opcode }, | |
9542 | { Bad_Opcode }, | |
9543 | { Bad_Opcode }, | |
9544 | { Bad_Opcode }, | |
9545 | { Bad_Opcode }, | |
592a252b | 9546 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9547 | /* e0 */ |
592d1631 L |
9548 | { Bad_Opcode }, |
9549 | { Bad_Opcode }, | |
9550 | { Bad_Opcode }, | |
9551 | { Bad_Opcode }, | |
9552 | { Bad_Opcode }, | |
9553 | { Bad_Opcode }, | |
9554 | { Bad_Opcode }, | |
9555 | { Bad_Opcode }, | |
c0f3af97 | 9556 | /* e8 */ |
592d1631 L |
9557 | { Bad_Opcode }, |
9558 | { Bad_Opcode }, | |
9559 | { Bad_Opcode }, | |
9560 | { Bad_Opcode }, | |
9561 | { Bad_Opcode }, | |
9562 | { Bad_Opcode }, | |
9563 | { Bad_Opcode }, | |
9564 | { Bad_Opcode }, | |
c0f3af97 | 9565 | /* f0 */ |
6c30d220 | 9566 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9567 | { Bad_Opcode }, |
9568 | { Bad_Opcode }, | |
9569 | { Bad_Opcode }, | |
9570 | { Bad_Opcode }, | |
9571 | { Bad_Opcode }, | |
9572 | { Bad_Opcode }, | |
9573 | { Bad_Opcode }, | |
c0f3af97 | 9574 | /* f8 */ |
592d1631 L |
9575 | { Bad_Opcode }, |
9576 | { Bad_Opcode }, | |
9577 | { Bad_Opcode }, | |
9578 | { Bad_Opcode }, | |
9579 | { Bad_Opcode }, | |
9580 | { Bad_Opcode }, | |
9581 | { Bad_Opcode }, | |
9582 | { Bad_Opcode }, | |
c0f3af97 L |
9583 | }, |
9584 | }; | |
9585 | ||
43234a1e L |
9586 | #define NEED_OPCODE_TABLE |
9587 | #include "i386-dis-evex.h" | |
9588 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9589 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9590 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9591 | { |
592a252b L |
9592 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9593 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9594 | }, |
9595 | ||
592a252b | 9596 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9597 | { |
592a252b L |
9598 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9599 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9600 | }, |
9601 | ||
592a252b | 9602 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9603 | { |
592a252b L |
9604 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9605 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9606 | }, |
9607 | ||
592a252b | 9608 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9609 | { |
592a252b L |
9610 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9611 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9612 | }, |
9613 | ||
592a252b | 9614 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9615 | { |
592a252b | 9616 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9617 | }, |
9618 | ||
592a252b | 9619 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9620 | { |
592a252b | 9621 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9622 | }, |
9623 | ||
592a252b | 9624 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9625 | { |
592a252b | 9626 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9627 | }, |
9628 | ||
592a252b | 9629 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9630 | { |
592a252b | 9631 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9632 | }, |
9633 | ||
592a252b | 9634 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9635 | { |
592a252b | 9636 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9637 | }, |
9638 | ||
592a252b | 9639 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9640 | { |
592a252b | 9641 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9642 | }, |
9643 | ||
592a252b | 9644 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9645 | { |
592a252b | 9646 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9647 | }, |
9648 | ||
592a252b | 9649 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9650 | { |
592a252b | 9651 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9652 | }, |
9653 | ||
592a252b | 9654 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9655 | { |
bf890a93 IT |
9656 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9657 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9658 | }, |
9659 | ||
592a252b | 9660 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9661 | { |
bf890a93 IT |
9662 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9663 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9664 | }, |
9665 | ||
592a252b | 9666 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9667 | { |
bf890a93 IT |
9668 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9669 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9670 | }, |
9671 | ||
592a252b | 9672 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9673 | { |
bf890a93 IT |
9674 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9675 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9676 | }, |
9677 | ||
592a252b | 9678 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9679 | { |
bf890a93 IT |
9680 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9681 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9682 | }, |
9683 | ||
592a252b | 9684 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9685 | { |
bf890a93 IT |
9686 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9687 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9688 | }, |
9689 | ||
592a252b | 9690 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9691 | { |
592a252b L |
9692 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9693 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9694 | }, |
9695 | ||
592a252b | 9696 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9697 | { |
592a252b L |
9698 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9699 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9700 | }, |
9701 | ||
592a252b | 9702 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9703 | { |
592a252b L |
9704 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9705 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9706 | }, |
9707 | ||
592a252b | 9708 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9709 | { |
592a252b L |
9710 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9711 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9712 | }, |
9713 | ||
43234a1e L |
9714 | /* VEX_LEN_0F41_P_0 */ |
9715 | { | |
9716 | { Bad_Opcode }, | |
9717 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9718 | }, | |
1ba585e8 IT |
9719 | /* VEX_LEN_0F41_P_2 */ |
9720 | { | |
9721 | { Bad_Opcode }, | |
9722 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9723 | }, | |
43234a1e L |
9724 | /* VEX_LEN_0F42_P_0 */ |
9725 | { | |
9726 | { Bad_Opcode }, | |
9727 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9728 | }, | |
1ba585e8 IT |
9729 | /* VEX_LEN_0F42_P_2 */ |
9730 | { | |
9731 | { Bad_Opcode }, | |
9732 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9733 | }, | |
43234a1e L |
9734 | /* VEX_LEN_0F44_P_0 */ |
9735 | { | |
9736 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9737 | }, | |
1ba585e8 IT |
9738 | /* VEX_LEN_0F44_P_2 */ |
9739 | { | |
9740 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9741 | }, | |
43234a1e L |
9742 | /* VEX_LEN_0F45_P_0 */ |
9743 | { | |
9744 | { Bad_Opcode }, | |
9745 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9746 | }, | |
1ba585e8 IT |
9747 | /* VEX_LEN_0F45_P_2 */ |
9748 | { | |
9749 | { Bad_Opcode }, | |
9750 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9751 | }, | |
43234a1e L |
9752 | /* VEX_LEN_0F46_P_0 */ |
9753 | { | |
9754 | { Bad_Opcode }, | |
9755 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9756 | }, | |
1ba585e8 IT |
9757 | /* VEX_LEN_0F46_P_2 */ |
9758 | { | |
9759 | { Bad_Opcode }, | |
9760 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9761 | }, | |
43234a1e L |
9762 | /* VEX_LEN_0F47_P_0 */ |
9763 | { | |
9764 | { Bad_Opcode }, | |
9765 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9766 | }, | |
1ba585e8 IT |
9767 | /* VEX_LEN_0F47_P_2 */ |
9768 | { | |
9769 | { Bad_Opcode }, | |
9770 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9771 | }, | |
9772 | /* VEX_LEN_0F4A_P_0 */ | |
9773 | { | |
9774 | { Bad_Opcode }, | |
9775 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9776 | }, | |
9777 | /* VEX_LEN_0F4A_P_2 */ | |
9778 | { | |
9779 | { Bad_Opcode }, | |
9780 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9781 | }, | |
9782 | /* VEX_LEN_0F4B_P_0 */ | |
9783 | { | |
9784 | { Bad_Opcode }, | |
9785 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9786 | }, | |
43234a1e L |
9787 | /* VEX_LEN_0F4B_P_2 */ |
9788 | { | |
9789 | { Bad_Opcode }, | |
9790 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9791 | }, | |
9792 | ||
592a252b | 9793 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9794 | { |
592a252b L |
9795 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9796 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9797 | }, |
9798 | ||
592a252b | 9799 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9800 | { |
592a252b L |
9801 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9802 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9803 | }, |
9804 | ||
592a252b | 9805 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9806 | { |
592a252b L |
9807 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9808 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9809 | }, |
9810 | ||
592a252b | 9811 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9812 | { |
592a252b L |
9813 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9814 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9815 | }, |
9816 | ||
592a252b | 9817 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9818 | { |
592a252b L |
9819 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9820 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9821 | }, |
9822 | ||
592a252b | 9823 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9824 | { |
592a252b L |
9825 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9826 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9827 | }, |
9828 | ||
592a252b | 9829 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9830 | { |
592a252b L |
9831 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9832 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9833 | }, |
9834 | ||
592a252b | 9835 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9836 | { |
592a252b L |
9837 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9838 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9839 | }, |
9840 | ||
592a252b | 9841 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9842 | { |
592a252b L |
9843 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9844 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9845 | }, |
9846 | ||
592a252b | 9847 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9848 | { |
592a252b L |
9849 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9850 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9851 | }, |
9852 | ||
592a252b | 9853 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9854 | { |
592a252b L |
9855 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9856 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9857 | }, |
9858 | ||
592a252b | 9859 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9860 | { |
592a252b L |
9861 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9862 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9863 | }, |
9864 | ||
592a252b | 9865 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9866 | { |
592a252b L |
9867 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9868 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9869 | }, |
9870 | ||
592a252b | 9871 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9872 | { |
592a252b L |
9873 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9874 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9875 | }, |
9876 | ||
592a252b | 9877 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9878 | { |
592a252b L |
9879 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9880 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9881 | }, |
9882 | ||
592a252b | 9883 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9884 | { |
592a252b L |
9885 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9886 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9887 | }, |
9888 | ||
592a252b | 9889 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9890 | { |
592a252b L |
9891 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9892 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9893 | }, |
9894 | ||
592a252b | 9895 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9896 | { |
592a252b L |
9897 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9898 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9899 | }, |
9900 | ||
592a252b | 9901 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9902 | { |
bf890a93 IT |
9903 | { "vmovK", { XMScalar, Edq }, 0 }, |
9904 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9905 | }, |
9906 | ||
592a252b | 9907 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9908 | { |
592a252b L |
9909 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9910 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9911 | }, |
9912 | ||
592a252b | 9913 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9914 | { |
bf890a93 IT |
9915 | { "vmovK", { Edq, XMScalar }, 0 }, |
9916 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9917 | }, |
9918 | ||
43234a1e L |
9919 | /* VEX_LEN_0F90_P_0 */ |
9920 | { | |
9921 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9922 | }, | |
9923 | ||
1ba585e8 IT |
9924 | /* VEX_LEN_0F90_P_2 */ |
9925 | { | |
9926 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9927 | }, | |
9928 | ||
43234a1e L |
9929 | /* VEX_LEN_0F91_P_0 */ |
9930 | { | |
9931 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9932 | }, | |
9933 | ||
1ba585e8 IT |
9934 | /* VEX_LEN_0F91_P_2 */ |
9935 | { | |
9936 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9937 | }, | |
9938 | ||
43234a1e L |
9939 | /* VEX_LEN_0F92_P_0 */ |
9940 | { | |
9941 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9942 | }, | |
9943 | ||
90a915bf IT |
9944 | /* VEX_LEN_0F92_P_2 */ |
9945 | { | |
9946 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9947 | }, | |
9948 | ||
1ba585e8 IT |
9949 | /* VEX_LEN_0F92_P_3 */ |
9950 | { | |
9951 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9952 | }, | |
9953 | ||
43234a1e L |
9954 | /* VEX_LEN_0F93_P_0 */ |
9955 | { | |
9956 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9957 | }, | |
9958 | ||
90a915bf IT |
9959 | /* VEX_LEN_0F93_P_2 */ |
9960 | { | |
9961 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9962 | }, | |
9963 | ||
1ba585e8 IT |
9964 | /* VEX_LEN_0F93_P_3 */ |
9965 | { | |
9966 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9967 | }, | |
9968 | ||
43234a1e L |
9969 | /* VEX_LEN_0F98_P_0 */ |
9970 | { | |
9971 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9972 | }, | |
9973 | ||
1ba585e8 IT |
9974 | /* VEX_LEN_0F98_P_2 */ |
9975 | { | |
9976 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9977 | }, | |
9978 | ||
9979 | /* VEX_LEN_0F99_P_0 */ | |
9980 | { | |
9981 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9982 | }, | |
9983 | ||
9984 | /* VEX_LEN_0F99_P_2 */ | |
9985 | { | |
9986 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9987 | }, | |
9988 | ||
6c30d220 | 9989 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9990 | { |
6c30d220 | 9991 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9992 | }, |
9993 | ||
6c30d220 | 9994 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9995 | { |
6c30d220 | 9996 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9997 | }, |
9998 | ||
6c30d220 | 9999 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 10000 | { |
6c30d220 L |
10001 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
10002 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
10003 | }, |
10004 | ||
6c30d220 | 10005 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 10006 | { |
6c30d220 L |
10007 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
10008 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
10009 | }, |
10010 | ||
6c30d220 | 10011 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 10012 | { |
6c30d220 | 10013 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
10014 | }, |
10015 | ||
6c30d220 | 10016 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 10017 | { |
6c30d220 | 10018 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
10019 | }, |
10020 | ||
6c30d220 | 10021 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 10022 | { |
6c30d220 L |
10023 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
10024 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
10025 | }, |
10026 | ||
6c30d220 | 10027 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 10028 | { |
6c30d220 | 10029 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
10030 | }, |
10031 | ||
6c30d220 | 10032 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 10033 | { |
6c30d220 L |
10034 | { Bad_Opcode }, |
10035 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
10036 | }, |
10037 | ||
6c30d220 | 10038 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 10039 | { |
6c30d220 L |
10040 | { Bad_Opcode }, |
10041 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
10042 | }, |
10043 | ||
6c30d220 | 10044 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 10045 | { |
6c30d220 L |
10046 | { Bad_Opcode }, |
10047 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
10048 | }, |
10049 | ||
6c30d220 | 10050 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 10051 | { |
6c30d220 L |
10052 | { Bad_Opcode }, |
10053 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
10054 | }, |
10055 | ||
592a252b | 10056 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 10057 | { |
592a252b | 10058 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
10059 | }, |
10060 | ||
6c30d220 L |
10061 | /* VEX_LEN_0F385A_P_2_M_0 */ |
10062 | { | |
10063 | { Bad_Opcode }, | |
10064 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
10065 | }, | |
10066 | ||
592a252b | 10067 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 10068 | { |
592a252b | 10069 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
10070 | }, |
10071 | ||
592a252b | 10072 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 10073 | { |
592a252b | 10074 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
10075 | }, |
10076 | ||
592a252b | 10077 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 10078 | { |
592a252b | 10079 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
10080 | }, |
10081 | ||
592a252b | 10082 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 10083 | { |
592a252b | 10084 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
10085 | }, |
10086 | ||
592a252b | 10087 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 10088 | { |
592a252b | 10089 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
10090 | }, |
10091 | ||
f12dc422 L |
10092 | /* VEX_LEN_0F38F2_P_0 */ |
10093 | { | |
bf890a93 | 10094 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
10095 | }, |
10096 | ||
10097 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
10098 | { | |
bf890a93 | 10099 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10100 | }, |
10101 | ||
10102 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
10103 | { | |
bf890a93 | 10104 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10105 | }, |
10106 | ||
10107 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
10108 | { | |
bf890a93 | 10109 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10110 | }, |
10111 | ||
6c30d220 L |
10112 | /* VEX_LEN_0F38F5_P_0 */ |
10113 | { | |
bf890a93 | 10114 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10115 | }, |
10116 | ||
10117 | /* VEX_LEN_0F38F5_P_1 */ | |
10118 | { | |
bf890a93 | 10119 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10120 | }, |
10121 | ||
10122 | /* VEX_LEN_0F38F5_P_3 */ | |
10123 | { | |
bf890a93 | 10124 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10125 | }, |
10126 | ||
10127 | /* VEX_LEN_0F38F6_P_3 */ | |
10128 | { | |
bf890a93 | 10129 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10130 | }, |
10131 | ||
f12dc422 L |
10132 | /* VEX_LEN_0F38F7_P_0 */ |
10133 | { | |
bf890a93 | 10134 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10135 | }, |
10136 | ||
6c30d220 L |
10137 | /* VEX_LEN_0F38F7_P_1 */ |
10138 | { | |
bf890a93 | 10139 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10140 | }, |
10141 | ||
10142 | /* VEX_LEN_0F38F7_P_2 */ | |
10143 | { | |
bf890a93 | 10144 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10145 | }, |
10146 | ||
10147 | /* VEX_LEN_0F38F7_P_3 */ | |
10148 | { | |
bf890a93 | 10149 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10150 | }, |
10151 | ||
10152 | /* VEX_LEN_0F3A00_P_2 */ | |
10153 | { | |
10154 | { Bad_Opcode }, | |
10155 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10156 | }, | |
10157 | ||
10158 | /* VEX_LEN_0F3A01_P_2 */ | |
10159 | { | |
10160 | { Bad_Opcode }, | |
10161 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10162 | }, | |
10163 | ||
592a252b | 10164 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10165 | { |
592d1631 | 10166 | { Bad_Opcode }, |
592a252b | 10167 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10168 | }, |
10169 | ||
592a252b | 10170 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10171 | { |
592a252b L |
10172 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10173 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10174 | }, |
10175 | ||
592a252b | 10176 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10177 | { |
592a252b L |
10178 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10179 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10180 | }, |
10181 | ||
592a252b | 10182 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10183 | { |
592a252b | 10184 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10185 | }, |
10186 | ||
592a252b | 10187 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10188 | { |
592a252b | 10189 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10190 | }, |
10191 | ||
592a252b | 10192 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10193 | { |
bf890a93 | 10194 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10195 | }, |
10196 | ||
592a252b | 10197 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10198 | { |
bf890a93 | 10199 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10200 | }, |
10201 | ||
592a252b | 10202 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10203 | { |
592d1631 | 10204 | { Bad_Opcode }, |
592a252b | 10205 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10206 | }, |
10207 | ||
592a252b | 10208 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10209 | { |
592d1631 | 10210 | { Bad_Opcode }, |
592a252b | 10211 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10212 | }, |
10213 | ||
592a252b | 10214 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10215 | { |
592a252b | 10216 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10217 | }, |
10218 | ||
592a252b | 10219 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10220 | { |
592a252b | 10221 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10222 | }, |
10223 | ||
592a252b | 10224 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10225 | { |
bf890a93 | 10226 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10227 | }, |
10228 | ||
43234a1e L |
10229 | /* VEX_LEN_0F3A30_P_2 */ |
10230 | { | |
10231 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10232 | }, | |
10233 | ||
1ba585e8 IT |
10234 | /* VEX_LEN_0F3A31_P_2 */ |
10235 | { | |
10236 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10237 | }, | |
10238 | ||
43234a1e L |
10239 | /* VEX_LEN_0F3A32_P_2 */ |
10240 | { | |
10241 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10242 | }, | |
10243 | ||
1ba585e8 IT |
10244 | /* VEX_LEN_0F3A33_P_2 */ |
10245 | { | |
10246 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10247 | }, | |
10248 | ||
6c30d220 | 10249 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10250 | { |
6c30d220 L |
10251 | { Bad_Opcode }, |
10252 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10253 | }, |
10254 | ||
6c30d220 | 10255 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10256 | { |
6c30d220 L |
10257 | { Bad_Opcode }, |
10258 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10259 | }, | |
10260 | ||
10261 | /* VEX_LEN_0F3A41_P_2 */ | |
10262 | { | |
10263 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10264 | }, |
10265 | ||
592a252b | 10266 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 10267 | { |
592a252b | 10268 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
10269 | }, |
10270 | ||
6c30d220 | 10271 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10272 | { |
6c30d220 L |
10273 | { Bad_Opcode }, |
10274 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10275 | }, |
10276 | ||
592a252b | 10277 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10278 | { |
592a252b | 10279 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
10280 | }, |
10281 | ||
592a252b | 10282 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10283 | { |
592a252b | 10284 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
10285 | }, |
10286 | ||
592a252b | 10287 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10288 | { |
592a252b | 10289 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10290 | }, |
10291 | ||
592a252b | 10292 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10293 | { |
592a252b | 10294 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10295 | }, |
10296 | ||
592a252b | 10297 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10298 | { |
bf890a93 | 10299 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10300 | }, |
10301 | ||
592a252b | 10302 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10303 | { |
bf890a93 | 10304 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10305 | }, |
10306 | ||
592a252b | 10307 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10308 | { |
bf890a93 | 10309 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10310 | }, |
10311 | ||
592a252b | 10312 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10313 | { |
bf890a93 | 10314 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10315 | }, |
10316 | ||
592a252b | 10317 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10318 | { |
bf890a93 | 10319 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10320 | }, |
10321 | ||
592a252b | 10322 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10323 | { |
bf890a93 | 10324 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10325 | }, |
10326 | ||
592a252b | 10327 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10328 | { |
bf890a93 | 10329 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10330 | }, |
10331 | ||
592a252b | 10332 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10333 | { |
bf890a93 | 10334 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10335 | }, |
10336 | ||
592a252b | 10337 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10338 | { |
592a252b | 10339 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10340 | }, |
4c807e72 | 10341 | |
6c30d220 L |
10342 | /* VEX_LEN_0F3AF0_P_3 */ |
10343 | { | |
bf890a93 | 10344 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10345 | }, |
10346 | ||
ff688e1f L |
10347 | /* VEX_LEN_0FXOP_08_CC */ |
10348 | { | |
bf890a93 | 10349 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10350 | }, |
10351 | ||
10352 | /* VEX_LEN_0FXOP_08_CD */ | |
10353 | { | |
bf890a93 | 10354 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10355 | }, |
10356 | ||
10357 | /* VEX_LEN_0FXOP_08_CE */ | |
10358 | { | |
bf890a93 | 10359 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10360 | }, |
10361 | ||
10362 | /* VEX_LEN_0FXOP_08_CF */ | |
10363 | { | |
bf890a93 | 10364 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10365 | }, |
10366 | ||
10367 | /* VEX_LEN_0FXOP_08_EC */ | |
10368 | { | |
bf890a93 | 10369 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10370 | }, |
10371 | ||
10372 | /* VEX_LEN_0FXOP_08_ED */ | |
10373 | { | |
bf890a93 | 10374 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10375 | }, |
10376 | ||
10377 | /* VEX_LEN_0FXOP_08_EE */ | |
10378 | { | |
bf890a93 | 10379 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10380 | }, |
10381 | ||
10382 | /* VEX_LEN_0FXOP_08_EF */ | |
10383 | { | |
bf890a93 | 10384 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10385 | }, |
10386 | ||
592a252b | 10387 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10388 | { |
bf890a93 IT |
10389 | { "vfrczps", { XM, EXxmm }, 0 }, |
10390 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10391 | }, |
4c807e72 | 10392 | |
592a252b | 10393 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10394 | { |
bf890a93 IT |
10395 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10396 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10397 | }, |
331d2d0d L |
10398 | }; |
10399 | ||
9e30b8e0 | 10400 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10401 | { |
592a252b | 10402 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10403 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10404 | }, |
10405 | { | |
592a252b | 10406 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10407 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10408 | }, |
10409 | { | |
592a252b | 10410 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10411 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10412 | }, |
10413 | { | |
592a252b | 10414 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10415 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10416 | }, |
10417 | { | |
592a252b | 10418 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10419 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10420 | }, |
10421 | { | |
592a252b | 10422 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10423 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10424 | }, |
10425 | { | |
592a252b | 10426 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10427 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10428 | }, |
10429 | { | |
592a252b | 10430 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10431 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10432 | }, |
10433 | { | |
592a252b | 10434 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10435 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10436 | }, |
10437 | { | |
592a252b | 10438 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10439 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10440 | }, |
10441 | { | |
592a252b | 10442 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10443 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10444 | }, |
10445 | { | |
592a252b | 10446 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10447 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10448 | }, |
10449 | { | |
592a252b | 10450 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10451 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10452 | }, |
10453 | { | |
592a252b | 10454 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10455 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10456 | }, |
10457 | { | |
592a252b | 10458 | /* VEX_W_0F14 */ |
bf890a93 | 10459 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10460 | }, |
10461 | { | |
592a252b | 10462 | /* VEX_W_0F15 */ |
bf890a93 | 10463 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10464 | }, |
10465 | { | |
592a252b | 10466 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10467 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10468 | }, |
10469 | { | |
592a252b | 10470 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10471 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10472 | }, |
10473 | { | |
592a252b | 10474 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10475 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10476 | }, |
10477 | { | |
592a252b | 10478 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10479 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10480 | }, |
10481 | { | |
592a252b | 10482 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10483 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10484 | }, |
10485 | { | |
592a252b | 10486 | /* VEX_W_0F28 */ |
bf890a93 | 10487 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10488 | }, |
10489 | { | |
592a252b | 10490 | /* VEX_W_0F29 */ |
bf890a93 | 10491 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10492 | }, |
10493 | { | |
592a252b | 10494 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10495 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10496 | }, |
10497 | { | |
592a252b | 10498 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10499 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10500 | }, |
10501 | { | |
592a252b | 10502 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10503 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10504 | }, |
10505 | { | |
592a252b | 10506 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10507 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10508 | }, |
10509 | { | |
592a252b | 10510 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10511 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10512 | }, |
43234a1e L |
10513 | { |
10514 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10515 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10516 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10517 | }, |
10518 | { | |
10519 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10520 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10521 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10522 | }, |
10523 | { | |
10524 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10525 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10526 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10527 | }, |
10528 | { | |
10529 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10530 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10531 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10532 | }, |
10533 | { | |
10534 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10535 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10536 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10537 | }, |
10538 | { | |
10539 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10540 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10541 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10542 | }, |
10543 | { | |
10544 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10545 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10546 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10547 | }, |
10548 | { | |
10549 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10550 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10551 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10552 | }, |
10553 | { | |
10554 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10555 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10556 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10557 | }, |
10558 | { | |
10559 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10560 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10561 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10562 | }, |
10563 | { | |
10564 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10565 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10566 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10567 | }, |
10568 | { | |
10569 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10570 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10571 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10572 | }, |
10573 | { | |
10574 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10575 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10576 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10577 | }, |
10578 | { | |
10579 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10580 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10581 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10582 | }, |
10583 | { | |
10584 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10585 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10586 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10587 | }, |
10588 | { | |
10589 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10590 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10591 | }, |
9e30b8e0 | 10592 | { |
592a252b | 10593 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10594 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10595 | }, |
10596 | { | |
592a252b | 10597 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10598 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10599 | }, |
10600 | { | |
592a252b | 10601 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10602 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10603 | }, |
10604 | { | |
592a252b | 10605 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10606 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10607 | }, |
10608 | { | |
592a252b | 10609 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10610 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10611 | }, |
10612 | { | |
592a252b | 10613 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10614 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10615 | }, |
10616 | { | |
592a252b | 10617 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10618 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10619 | }, |
10620 | { | |
592a252b | 10621 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10622 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10623 | }, |
10624 | { | |
592a252b | 10625 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10626 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10627 | }, |
10628 | { | |
592a252b | 10629 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10630 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10631 | }, |
10632 | { | |
592a252b | 10633 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10634 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10635 | }, |
10636 | { | |
592a252b | 10637 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10638 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10639 | }, |
10640 | { | |
592a252b | 10641 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10642 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10643 | }, |
10644 | { | |
592a252b | 10645 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10646 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10647 | }, |
10648 | { | |
592a252b | 10649 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10650 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10651 | }, |
10652 | { | |
592a252b | 10653 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10654 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10655 | }, |
10656 | { | |
592a252b | 10657 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10658 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10659 | }, |
10660 | { | |
592a252b | 10661 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10662 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10663 | }, |
10664 | { | |
592a252b | 10665 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10666 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10667 | }, |
10668 | { | |
592a252b | 10669 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10670 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10671 | }, |
10672 | { | |
592a252b | 10673 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10674 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10675 | }, |
10676 | { | |
592a252b | 10677 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10678 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10679 | }, |
10680 | { | |
592a252b | 10681 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10682 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10683 | }, |
10684 | { | |
592a252b | 10685 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10686 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10687 | }, |
10688 | { | |
592a252b | 10689 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10690 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10691 | }, |
10692 | { | |
592a252b | 10693 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10694 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10695 | }, |
10696 | { | |
592a252b | 10697 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10698 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10699 | }, |
10700 | { | |
592a252b | 10701 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10702 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10703 | }, |
10704 | { | |
592a252b | 10705 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10706 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10707 | }, |
10708 | { | |
592a252b | 10709 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10710 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10711 | }, |
10712 | { | |
592a252b | 10713 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10714 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10715 | }, |
10716 | { | |
592a252b | 10717 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10718 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10719 | }, |
10720 | { | |
592a252b | 10721 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10722 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10723 | }, |
10724 | { | |
592a252b | 10725 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10726 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10727 | }, |
10728 | { | |
592a252b | 10729 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10730 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10731 | }, |
10732 | { | |
592a252b | 10733 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10734 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10735 | }, |
10736 | { | |
592a252b | 10737 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10738 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10739 | }, |
10740 | { | |
592a252b | 10741 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10742 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10743 | }, |
10744 | { | |
592a252b | 10745 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10746 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10747 | }, |
10748 | { | |
592a252b | 10749 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10750 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10751 | }, |
10752 | { | |
592a252b | 10753 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10754 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10755 | }, |
10756 | { | |
592a252b | 10757 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10758 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10759 | }, |
10760 | { | |
592a252b | 10761 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10762 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10763 | }, |
10764 | { | |
592a252b | 10765 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10766 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10767 | }, |
10768 | { | |
592a252b | 10769 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10770 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10771 | }, |
10772 | { | |
592a252b | 10773 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10774 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10775 | }, |
10776 | { | |
592a252b | 10777 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10778 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10779 | }, |
10780 | { | |
592a252b | 10781 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10782 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10783 | }, |
10784 | { | |
592a252b | 10785 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10786 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10787 | }, |
10788 | { | |
592a252b | 10789 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10790 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10791 | }, |
10792 | { | |
592a252b | 10793 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10794 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10795 | }, |
10796 | { | |
592a252b | 10797 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10798 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10799 | }, |
10800 | { | |
592a252b | 10801 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10802 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10803 | }, |
10804 | { | |
592a252b | 10805 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10806 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10807 | }, |
10808 | { | |
592a252b | 10809 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10810 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10811 | }, |
10812 | { | |
592a252b | 10813 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10814 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10815 | }, |
10816 | { | |
592a252b | 10817 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10818 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10819 | }, |
10820 | { | |
592a252b | 10821 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10822 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10823 | }, |
10824 | { | |
592a252b | 10825 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10826 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10827 | }, |
10828 | { | |
592a252b | 10829 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10830 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10831 | }, |
10832 | { | |
592a252b | 10833 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10834 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10835 | }, |
10836 | { | |
592a252b | 10837 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10838 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10839 | }, |
10840 | { | |
592a252b | 10841 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10842 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10843 | }, |
10844 | { | |
592a252b | 10845 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10846 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10847 | }, |
10848 | { | |
592a252b | 10849 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10850 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10851 | }, |
10852 | { | |
592a252b | 10853 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10854 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10855 | }, |
10856 | { | |
592a252b | 10857 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10858 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10859 | }, |
10860 | { | |
592a252b | 10861 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10862 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10863 | }, |
10864 | { | |
592a252b | 10865 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10866 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10867 | }, |
10868 | { | |
592a252b | 10869 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10870 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10871 | }, |
10872 | { | |
592a252b | 10873 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10874 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10875 | }, |
10876 | { | |
592a252b | 10877 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10878 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10879 | }, |
10880 | { | |
592a252b | 10881 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10882 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10883 | }, |
10884 | { | |
592a252b | 10885 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10886 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10887 | }, |
10888 | { | |
592a252b | 10889 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10890 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10891 | }, |
10892 | { | |
592a252b | 10893 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10894 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10895 | }, |
10896 | { | |
592a252b | 10897 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10898 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10899 | }, |
10900 | { | |
592a252b | 10901 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10902 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10903 | }, |
10904 | { | |
592a252b | 10905 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10906 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10907 | }, |
43234a1e L |
10908 | { |
10909 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10910 | { "kmovw", { MaskG, MaskE }, 0 }, |
10911 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10912 | }, |
10913 | { | |
10914 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10915 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10916 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10917 | }, |
10918 | { | |
10919 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10920 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10921 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10922 | }, |
10923 | { | |
10924 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10925 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10926 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10927 | }, |
10928 | { | |
10929 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10930 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10931 | }, |
90a915bf IT |
10932 | { |
10933 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10934 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10935 | }, |
1ba585e8 IT |
10936 | { |
10937 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10938 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10939 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10940 | }, |
43234a1e L |
10941 | { |
10942 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10943 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10944 | }, |
90a915bf IT |
10945 | { |
10946 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10947 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10948 | }, |
1ba585e8 IT |
10949 | { |
10950 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10951 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10952 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10953 | }, |
43234a1e L |
10954 | { |
10955 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10956 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10957 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10958 | }, |
10959 | { | |
10960 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10961 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10962 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10963 | }, |
10964 | { | |
10965 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10966 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10967 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10968 | }, |
10969 | { | |
10970 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10971 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10972 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10973 | }, |
9e30b8e0 | 10974 | { |
592a252b | 10975 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10976 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10977 | }, |
10978 | { | |
592a252b | 10979 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10980 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10981 | }, |
10982 | { | |
592a252b | 10983 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10984 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10985 | }, |
10986 | { | |
592a252b | 10987 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10988 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10989 | }, |
10990 | { | |
592a252b | 10991 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10992 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10993 | }, |
10994 | { | |
592a252b | 10995 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10996 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10997 | }, |
10998 | { | |
592a252b | 10999 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 11000 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
11001 | }, |
11002 | { | |
592a252b | 11003 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 11004 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
11005 | }, |
11006 | { | |
592a252b | 11007 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 11008 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11009 | }, |
11010 | { | |
592a252b | 11011 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 11012 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11013 | }, |
11014 | { | |
592a252b | 11015 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 11016 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11017 | }, |
11018 | { | |
592a252b | 11019 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 11020 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11021 | }, |
11022 | { | |
592a252b | 11023 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 11024 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11025 | }, |
11026 | { | |
592a252b | 11027 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 11028 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11029 | }, |
11030 | { | |
592a252b | 11031 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 11032 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11033 | }, |
11034 | { | |
592a252b | 11035 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 11036 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
11037 | }, |
11038 | { | |
592a252b | 11039 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 11040 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
11041 | }, |
11042 | { | |
592a252b | 11043 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 11044 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11045 | }, |
11046 | { | |
592a252b | 11047 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 11048 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11049 | }, |
11050 | { | |
592a252b | 11051 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 11052 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11053 | }, |
11054 | { | |
592a252b | 11055 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 11056 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11057 | }, |
11058 | { | |
592a252b | 11059 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 11060 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11061 | }, |
11062 | { | |
592a252b | 11063 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 11064 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11065 | }, |
11066 | { | |
592a252b | 11067 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 11068 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11069 | }, |
11070 | { | |
592a252b | 11071 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 11072 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11073 | }, |
11074 | { | |
592a252b | 11075 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 11076 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11077 | }, |
11078 | { | |
592a252b | 11079 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 11080 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11081 | }, |
11082 | { | |
592a252b | 11083 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 11084 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11085 | }, |
11086 | { | |
592a252b | 11087 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 11088 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11089 | }, |
11090 | { | |
592a252b | 11091 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 11092 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11093 | }, |
11094 | { | |
592a252b | 11095 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 11096 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11097 | }, |
11098 | { | |
592a252b | 11099 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 11100 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11101 | }, |
11102 | { | |
592a252b | 11103 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 11104 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11105 | }, |
11106 | { | |
592a252b | 11107 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 11108 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11109 | }, |
11110 | { | |
592a252b | 11111 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 11112 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
11113 | }, |
11114 | { | |
592a252b | 11115 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 11116 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11117 | }, |
11118 | { | |
592a252b | 11119 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 11120 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11121 | }, |
11122 | { | |
592a252b | 11123 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 11124 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11125 | }, |
11126 | { | |
592a252b | 11127 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 11128 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11129 | }, |
11130 | { | |
592a252b | 11131 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11132 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11133 | }, |
11134 | { | |
592a252b | 11135 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11136 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11137 | }, |
11138 | { | |
592a252b | 11139 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11140 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11141 | }, |
11142 | { | |
592a252b | 11143 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11144 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11145 | }, |
11146 | { | |
592a252b | 11147 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11148 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11149 | }, |
11150 | { | |
592a252b | 11151 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11152 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11153 | }, |
11154 | { | |
592a252b | 11155 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11156 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11157 | }, |
11158 | { | |
592a252b | 11159 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11160 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11161 | }, |
11162 | { | |
592a252b | 11163 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11164 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11165 | }, |
11166 | { | |
592a252b | 11167 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11168 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11169 | }, |
11170 | { | |
592a252b | 11171 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11172 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11173 | }, |
11174 | { | |
592a252b | 11175 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11176 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11177 | }, |
11178 | { | |
592a252b | 11179 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11180 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11181 | }, |
11182 | { | |
592a252b | 11183 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11184 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11185 | }, |
11186 | { | |
592a252b | 11187 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11188 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11189 | }, |
11190 | { | |
592a252b | 11191 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11192 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11193 | }, |
11194 | { | |
592a252b | 11195 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11196 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11197 | }, |
11198 | { | |
592a252b | 11199 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11200 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11201 | }, |
11202 | { | |
592a252b | 11203 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11204 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11205 | }, |
11206 | { | |
592a252b | 11207 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11208 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11209 | }, |
11210 | { | |
592a252b | 11211 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11212 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11213 | }, |
11214 | { | |
592a252b | 11215 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11216 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11217 | }, |
11218 | { | |
592a252b | 11219 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11220 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11221 | }, |
11222 | { | |
592a252b | 11223 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11224 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11225 | }, |
11226 | { | |
592a252b | 11227 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11228 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11229 | }, |
11230 | { | |
592a252b | 11231 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11232 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11233 | }, |
11234 | { | |
592a252b | 11235 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11236 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11237 | }, |
11238 | { | |
592a252b | 11239 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11240 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11241 | }, |
11242 | { | |
592a252b | 11243 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11244 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11245 | }, |
11246 | { | |
592a252b | 11247 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11248 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11249 | }, |
11250 | { | |
592a252b | 11251 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11252 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11253 | }, |
11254 | { | |
592a252b | 11255 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11256 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11257 | }, |
11258 | { | |
592a252b | 11259 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11260 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11261 | }, |
11262 | { | |
592a252b | 11263 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11264 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11265 | }, |
11266 | { | |
592a252b | 11267 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11268 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11269 | }, |
6c30d220 L |
11270 | { |
11271 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11272 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11273 | }, |
9e30b8e0 | 11274 | { |
592a252b | 11275 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11276 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11277 | }, |
bcf2684f | 11278 | { |
6c30d220 | 11279 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11280 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11281 | }, |
9e30b8e0 | 11282 | { |
6c30d220 | 11283 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11284 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11285 | }, |
11286 | { | |
592a252b | 11287 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11288 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11289 | }, |
11290 | { | |
592a252b | 11291 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11292 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11293 | }, |
11294 | { | |
592a252b | 11295 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11296 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11297 | }, |
11298 | { | |
592a252b | 11299 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11300 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11301 | }, |
11302 | { | |
592a252b | 11303 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11304 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11305 | }, |
11306 | { | |
592a252b | 11307 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11308 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11309 | }, |
11310 | { | |
592a252b | 11311 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11312 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11313 | }, |
11314 | { | |
592a252b | 11315 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11316 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11317 | }, |
11318 | { | |
592a252b | 11319 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11320 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11321 | }, |
11322 | { | |
592a252b | 11323 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11324 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11325 | }, |
11326 | { | |
592a252b | 11327 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11328 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11329 | }, |
11330 | { | |
592a252b | 11331 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11332 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11333 | }, |
11334 | { | |
592a252b | 11335 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11336 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11337 | }, |
11338 | { | |
592a252b | 11339 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11340 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11341 | }, |
53aa04a0 | 11342 | { |
592a252b | 11343 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11344 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11345 | }, |
11346 | { | |
592a252b | 11347 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11348 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11349 | }, |
11350 | { | |
592a252b | 11351 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11352 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11353 | }, |
11354 | { | |
592a252b | 11355 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11356 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11357 | }, |
9e30b8e0 | 11358 | { |
592a252b | 11359 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11360 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11361 | }, |
11362 | { | |
592a252b | 11363 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11364 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11365 | }, |
11366 | { | |
592a252b | 11367 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11368 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11369 | }, |
11370 | { | |
592a252b | 11371 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11372 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11373 | }, |
11374 | { | |
592a252b | 11375 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11376 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11377 | }, |
11378 | { | |
592a252b | 11379 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11380 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11381 | }, |
11382 | { | |
11383 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11384 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11385 | }, |
11386 | { | |
592a252b | 11387 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11388 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11389 | }, |
11390 | { | |
592a252b | 11391 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11392 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11393 | }, |
11394 | { | |
592a252b | 11395 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11396 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11397 | }, |
11398 | { | |
592a252b | 11399 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11400 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11401 | }, |
11402 | { | |
592a252b | 11403 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11404 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11405 | }, |
11406 | { | |
592a252b | 11407 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11408 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11409 | }, |
11410 | { | |
592a252b | 11411 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11412 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11413 | }, |
11414 | { | |
592a252b | 11415 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11416 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11417 | }, |
11418 | { | |
592a252b | 11419 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11420 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11421 | }, |
11422 | { | |
592a252b | 11423 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11424 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11425 | }, |
11426 | { | |
592a252b | 11427 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11428 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11429 | }, |
6c30d220 L |
11430 | { |
11431 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11432 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11433 | }, |
11434 | { | |
11435 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11436 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11437 | }, |
11438 | { | |
11439 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11440 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11441 | }, |
11442 | { | |
11443 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11444 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11445 | }, |
11446 | { | |
11447 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11448 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11449 | }, |
11450 | { | |
11451 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11452 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11453 | }, |
9e30b8e0 | 11454 | { |
592a252b | 11455 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11456 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 L |
11457 | }, |
11458 | { | |
592a252b | 11459 | /* VEX_W_0F38DC_P_2 */ |
bf890a93 | 11460 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11461 | }, |
11462 | { | |
592a252b | 11463 | /* VEX_W_0F38DD_P_2 */ |
bf890a93 | 11464 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11465 | }, |
11466 | { | |
592a252b | 11467 | /* VEX_W_0F38DE_P_2 */ |
bf890a93 | 11468 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11469 | }, |
11470 | { | |
592a252b | 11471 | /* VEX_W_0F38DF_P_2 */ |
bf890a93 | 11472 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 | 11473 | }, |
6c30d220 L |
11474 | { |
11475 | /* VEX_W_0F3A00_P_2 */ | |
11476 | { Bad_Opcode }, | |
bf890a93 | 11477 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11478 | }, |
11479 | { | |
11480 | /* VEX_W_0F3A01_P_2 */ | |
11481 | { Bad_Opcode }, | |
bf890a93 | 11482 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11483 | }, |
11484 | { | |
11485 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11486 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11487 | }, |
9e30b8e0 | 11488 | { |
592a252b | 11489 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11490 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11491 | }, |
11492 | { | |
592a252b | 11493 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11494 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11495 | }, |
11496 | { | |
592a252b | 11497 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11498 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11499 | }, |
11500 | { | |
592a252b | 11501 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11502 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11503 | }, |
11504 | { | |
592a252b | 11505 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11506 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11507 | }, |
11508 | { | |
592a252b | 11509 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11510 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11511 | }, |
11512 | { | |
592a252b | 11513 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11514 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11515 | }, |
11516 | { | |
592a252b | 11517 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11518 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11519 | }, |
11520 | { | |
592a252b | 11521 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11522 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11523 | }, |
11524 | { | |
592a252b | 11525 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11526 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11527 | }, |
11528 | { | |
592a252b | 11529 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11530 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11531 | }, |
11532 | { | |
592a252b | 11533 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11534 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11535 | }, |
11536 | { | |
592a252b | 11537 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11538 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11539 | }, |
11540 | { | |
592a252b | 11541 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11542 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11543 | }, |
11544 | { | |
592a252b | 11545 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11546 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11547 | }, |
11548 | { | |
592a252b | 11549 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11550 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11551 | }, |
11552 | { | |
592a252b | 11553 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11554 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11555 | }, |
43234a1e | 11556 | { |
1ba585e8 | 11557 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11558 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11559 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11560 | }, |
11561 | { | |
1ba585e8 | 11562 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11563 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11564 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11565 | }, |
11566 | { | |
11567 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11568 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11569 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11570 | }, |
1ba585e8 IT |
11571 | { |
11572 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11573 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11574 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11575 | }, |
6c30d220 L |
11576 | { |
11577 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11578 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11579 | }, |
11580 | { | |
11581 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11582 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11583 | }, |
9e30b8e0 | 11584 | { |
592a252b | 11585 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11586 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11587 | }, |
11588 | { | |
592a252b | 11589 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11590 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11591 | }, |
11592 | { | |
592a252b | 11593 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11594 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11595 | }, |
11596 | { | |
592a252b | 11597 | /* VEX_W_0F3A44_P_2 */ |
bf890a93 | 11598 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
9e30b8e0 | 11599 | }, |
6c30d220 L |
11600 | { |
11601 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11602 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11603 | }, |
a683cc34 | 11604 | { |
592a252b | 11605 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11606 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11607 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11608 | }, |
11609 | { | |
592a252b | 11610 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11611 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11612 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11613 | }, |
9e30b8e0 | 11614 | { |
592a252b | 11615 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11616 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11617 | }, |
11618 | { | |
592a252b | 11619 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11620 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11621 | }, |
11622 | { | |
592a252b | 11623 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11624 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11625 | }, |
11626 | { | |
592a252b | 11627 | /* VEX_W_0F3A60_P_2 */ |
bf890a93 | 11628 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11629 | }, |
11630 | { | |
592a252b | 11631 | /* VEX_W_0F3A61_P_2 */ |
bf890a93 | 11632 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11633 | }, |
11634 | { | |
592a252b | 11635 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11636 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11637 | }, |
11638 | { | |
592a252b | 11639 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11640 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11641 | }, |
11642 | { | |
592a252b | 11643 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11644 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11645 | }, |
43234a1e L |
11646 | #define NEED_VEX_W_TABLE |
11647 | #include "i386-dis-evex.h" | |
11648 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11649 | }; |
11650 | ||
11651 | static const struct dis386 mod_table[][2] = { | |
11652 | { | |
11653 | /* MOD_8D */ | |
bf890a93 | 11654 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11655 | }, |
42164a71 L |
11656 | { |
11657 | /* MOD_C6_REG_7 */ | |
11658 | { Bad_Opcode }, | |
11659 | { RM_TABLE (RM_C6_REG_7) }, | |
11660 | }, | |
11661 | { | |
11662 | /* MOD_C7_REG_7 */ | |
11663 | { Bad_Opcode }, | |
11664 | { RM_TABLE (RM_C7_REG_7) }, | |
11665 | }, | |
4a357820 MZ |
11666 | { |
11667 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11668 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11669 | }, |
11670 | { | |
11671 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11672 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11673 | }, |
9e30b8e0 L |
11674 | { |
11675 | /* MOD_0F01_REG_0 */ | |
11676 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11677 | { RM_TABLE (RM_0F01_REG_0) }, | |
11678 | }, | |
11679 | { | |
11680 | /* MOD_0F01_REG_1 */ | |
11681 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11682 | { RM_TABLE (RM_0F01_REG_1) }, | |
11683 | }, | |
11684 | { | |
11685 | /* MOD_0F01_REG_2 */ | |
11686 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11687 | { RM_TABLE (RM_0F01_REG_2) }, | |
11688 | }, | |
11689 | { | |
11690 | /* MOD_0F01_REG_3 */ | |
11691 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11692 | { RM_TABLE (RM_0F01_REG_3) }, | |
11693 | }, | |
8eab4136 L |
11694 | { |
11695 | /* MOD_0F01_REG_5 */ | |
11696 | { Bad_Opcode }, | |
11697 | { RM_TABLE (RM_0F01_REG_5) }, | |
11698 | }, | |
9e30b8e0 L |
11699 | { |
11700 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11701 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11702 | { RM_TABLE (RM_0F01_REG_7) }, |
11703 | }, | |
11704 | { | |
11705 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11706 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11707 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11708 | }, |
11709 | { | |
11710 | /* MOD_0F13 */ | |
507bd325 | 11711 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11712 | }, |
11713 | { | |
11714 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11715 | { "movhps", { XM, EXq }, 0 }, |
11716 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11717 | }, |
11718 | { | |
11719 | /* MOD_0F17 */ | |
507bd325 | 11720 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11721 | }, |
11722 | { | |
11723 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11724 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11725 | }, |
11726 | { | |
11727 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11728 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11729 | }, |
11730 | { | |
11731 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11732 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11733 | }, |
11734 | { | |
11735 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11736 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11737 | }, |
d7189fa5 RM |
11738 | { |
11739 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11740 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11741 | }, |
11742 | { | |
11743 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11744 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11745 | }, |
11746 | { | |
11747 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11748 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11749 | }, |
11750 | { | |
11751 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11752 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11753 | }, |
7e8b059b L |
11754 | { |
11755 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11756 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11757 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11758 | }, |
11759 | { | |
11760 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11761 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11762 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11763 | }, |
11764 | { | |
11765 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11766 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11767 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11768 | }, |
b844680a | 11769 | { |
92fddf8e | 11770 | /* MOD_0F24 */ |
7bb15c6f | 11771 | { Bad_Opcode }, |
bf890a93 | 11772 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11773 | }, |
11774 | { | |
92fddf8e | 11775 | /* MOD_0F26 */ |
592d1631 | 11776 | { Bad_Opcode }, |
bf890a93 | 11777 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11778 | }, |
75c135a8 L |
11779 | { |
11780 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11781 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11782 | }, |
11783 | { | |
11784 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11785 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11786 | }, |
11787 | { | |
11788 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11789 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11790 | }, |
11791 | { | |
11792 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11793 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11794 | }, |
11795 | { | |
11796 | /* MOD_0F51 */ | |
592d1631 | 11797 | { Bad_Opcode }, |
507bd325 | 11798 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11799 | }, |
b844680a | 11800 | { |
1ceb70f8 | 11801 | /* MOD_0F71_REG_2 */ |
592d1631 | 11802 | { Bad_Opcode }, |
bf890a93 | 11803 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11804 | }, |
11805 | { | |
1ceb70f8 | 11806 | /* MOD_0F71_REG_4 */ |
592d1631 | 11807 | { Bad_Opcode }, |
bf890a93 | 11808 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11809 | }, |
11810 | { | |
1ceb70f8 | 11811 | /* MOD_0F71_REG_6 */ |
592d1631 | 11812 | { Bad_Opcode }, |
bf890a93 | 11813 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11814 | }, |
11815 | { | |
1ceb70f8 | 11816 | /* MOD_0F72_REG_2 */ |
592d1631 | 11817 | { Bad_Opcode }, |
bf890a93 | 11818 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11819 | }, |
11820 | { | |
1ceb70f8 | 11821 | /* MOD_0F72_REG_4 */ |
592d1631 | 11822 | { Bad_Opcode }, |
bf890a93 | 11823 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11824 | }, |
11825 | { | |
1ceb70f8 | 11826 | /* MOD_0F72_REG_6 */ |
592d1631 | 11827 | { Bad_Opcode }, |
bf890a93 | 11828 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11829 | }, |
11830 | { | |
1ceb70f8 | 11831 | /* MOD_0F73_REG_2 */ |
592d1631 | 11832 | { Bad_Opcode }, |
bf890a93 | 11833 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11834 | }, |
11835 | { | |
1ceb70f8 | 11836 | /* MOD_0F73_REG_3 */ |
592d1631 | 11837 | { Bad_Opcode }, |
c0f3af97 L |
11838 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11839 | }, | |
11840 | { | |
11841 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11842 | { Bad_Opcode }, |
bf890a93 | 11843 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11844 | }, |
11845 | { | |
11846 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11847 | { Bad_Opcode }, |
c0f3af97 L |
11848 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11849 | }, | |
11850 | { | |
11851 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11852 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11853 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11854 | }, |
11855 | { | |
11856 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11857 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11858 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11859 | }, |
11860 | { | |
11861 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11862 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11863 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11864 | }, |
11865 | { | |
11866 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11867 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11868 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11869 | }, |
11870 | { | |
11871 | /* MOD_0FAE_REG_4 */ | |
bf890a93 | 11872 | { "xsave", { FXSAVE }, 0 }, |
c0f3af97 L |
11873 | }, |
11874 | { | |
11875 | /* MOD_0FAE_REG_5 */ | |
bf890a93 | 11876 | { "xrstor", { FXSAVE }, 0 }, |
c0f3af97 L |
11877 | { RM_TABLE (RM_0FAE_REG_5) }, |
11878 | }, | |
11879 | { | |
11880 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11881 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11882 | { RM_TABLE (RM_0FAE_REG_6) }, |
11883 | }, | |
11884 | { | |
11885 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11886 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11887 | { RM_TABLE (RM_0FAE_REG_7) }, |
11888 | }, | |
11889 | { | |
11890 | /* MOD_0FB2 */ | |
bf890a93 | 11891 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11892 | }, |
11893 | { | |
11894 | /* MOD_0FB4 */ | |
bf890a93 | 11895 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11896 | }, |
11897 | { | |
11898 | /* MOD_0FB5 */ | |
bf890a93 | 11899 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11900 | }, |
a8484f96 L |
11901 | { |
11902 | /* MOD_0FC3 */ | |
11903 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11904 | }, | |
963f3586 IT |
11905 | { |
11906 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11907 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11908 | }, |
11909 | { | |
11910 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11911 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11912 | }, |
11913 | { | |
11914 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11915 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11916 | }, |
c0f3af97 L |
11917 | { |
11918 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11919 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11920 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11921 | }, |
11922 | { | |
11923 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11924 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11925 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11926 | }, |
11927 | { | |
11928 | /* MOD_0FD7 */ | |
592d1631 | 11929 | { Bad_Opcode }, |
bf890a93 | 11930 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11931 | }, |
11932 | { | |
11933 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11934 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11935 | }, |
11936 | { | |
11937 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11938 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11939 | }, |
11940 | { | |
11941 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11942 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 L |
11943 | }, |
11944 | { | |
11945 | /* MOD_62_32BIT */ | |
bf890a93 | 11946 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11947 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11948 | }, |
11949 | { | |
11950 | /* MOD_C4_32BIT */ | |
bf890a93 | 11951 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11952 | { VEX_C4_TABLE (VEX_0F) }, |
11953 | }, | |
11954 | { | |
11955 | /* MOD_C5_32BIT */ | |
bf890a93 | 11956 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11957 | { VEX_C5_TABLE (VEX_0F) }, |
11958 | }, | |
11959 | { | |
592a252b L |
11960 | /* MOD_VEX_0F12_PREFIX_0 */ |
11961 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11962 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11963 | }, |
11964 | { | |
592a252b L |
11965 | /* MOD_VEX_0F13 */ |
11966 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11967 | }, |
11968 | { | |
592a252b L |
11969 | /* MOD_VEX_0F16_PREFIX_0 */ |
11970 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11971 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11972 | }, |
11973 | { | |
592a252b L |
11974 | /* MOD_VEX_0F17 */ |
11975 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11976 | }, |
11977 | { | |
592a252b L |
11978 | /* MOD_VEX_0F2B */ |
11979 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11980 | }, |
ab4e4ed5 AF |
11981 | { |
11982 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11983 | { Bad_Opcode }, | |
11984 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11985 | }, | |
11986 | { | |
11987 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11988 | { Bad_Opcode }, | |
11989 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11990 | }, | |
11991 | { | |
11992 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11993 | { Bad_Opcode }, | |
11994 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11995 | }, | |
11996 | { | |
11997 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11998 | { Bad_Opcode }, | |
11999 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
12000 | }, | |
12001 | { | |
12002 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
12003 | { Bad_Opcode }, | |
12004 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
12005 | }, | |
12006 | { | |
12007 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
12008 | { Bad_Opcode }, | |
12009 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
12010 | }, | |
12011 | { | |
12012 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
12013 | { Bad_Opcode }, | |
12014 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
12015 | }, | |
12016 | { | |
12017 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
12018 | { Bad_Opcode }, | |
12019 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
12020 | }, | |
12021 | { | |
12022 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
12023 | { Bad_Opcode }, | |
12024 | { "knotw", { MaskG, MaskR }, 0 }, | |
12025 | }, | |
12026 | { | |
12027 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
12028 | { Bad_Opcode }, | |
12029 | { "knotq", { MaskG, MaskR }, 0 }, | |
12030 | }, | |
12031 | { | |
12032 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
12033 | { Bad_Opcode }, | |
12034 | { "knotb", { MaskG, MaskR }, 0 }, | |
12035 | }, | |
12036 | { | |
12037 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
12038 | { Bad_Opcode }, | |
12039 | { "knotd", { MaskG, MaskR }, 0 }, | |
12040 | }, | |
12041 | { | |
12042 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
12043 | { Bad_Opcode }, | |
12044 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
12045 | }, | |
12046 | { | |
12047 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
12048 | { Bad_Opcode }, | |
12049 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
12050 | }, | |
12051 | { | |
12052 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
12053 | { Bad_Opcode }, | |
12054 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
12055 | }, | |
12056 | { | |
12057 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
12058 | { Bad_Opcode }, | |
12059 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
12060 | }, | |
12061 | { | |
12062 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
12063 | { Bad_Opcode }, | |
12064 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12065 | }, | |
12066 | { | |
12067 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
12068 | { Bad_Opcode }, | |
12069 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12070 | }, | |
12071 | { | |
12072 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
12073 | { Bad_Opcode }, | |
12074 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12075 | }, | |
12076 | { | |
12077 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
12078 | { Bad_Opcode }, | |
12079 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
12080 | }, | |
12081 | { | |
12082 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
12083 | { Bad_Opcode }, | |
12084 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12085 | }, | |
12086 | { | |
12087 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
12088 | { Bad_Opcode }, | |
12089 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12090 | }, | |
12091 | { | |
12092 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
12093 | { Bad_Opcode }, | |
12094 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12095 | }, | |
12096 | { | |
12097 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
12098 | { Bad_Opcode }, | |
12099 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
12100 | }, | |
12101 | { | |
12102 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
12103 | { Bad_Opcode }, | |
12104 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
12105 | }, | |
12106 | { | |
12107 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
12108 | { Bad_Opcode }, | |
12109 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
12110 | }, | |
12111 | { | |
12112 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
12113 | { Bad_Opcode }, | |
12114 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
12115 | }, | |
12116 | { | |
12117 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
12118 | { Bad_Opcode }, | |
12119 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
12120 | }, | |
12121 | { | |
12122 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
12123 | { Bad_Opcode }, | |
12124 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
12125 | }, | |
12126 | { | |
12127 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
12128 | { Bad_Opcode }, | |
12129 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
12130 | }, | |
12131 | { | |
12132 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
12133 | { Bad_Opcode }, | |
12134 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
12135 | }, | |
c0f3af97 | 12136 | { |
592a252b | 12137 | /* MOD_VEX_0F50 */ |
592d1631 | 12138 | { Bad_Opcode }, |
592a252b | 12139 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
12140 | }, |
12141 | { | |
592a252b | 12142 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12143 | { Bad_Opcode }, |
592a252b | 12144 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12145 | }, |
12146 | { | |
592a252b | 12147 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12148 | { Bad_Opcode }, |
592a252b | 12149 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12150 | }, |
12151 | { | |
592a252b | 12152 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12153 | { Bad_Opcode }, |
592a252b | 12154 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12155 | }, |
12156 | { | |
592a252b | 12157 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12158 | { Bad_Opcode }, |
592a252b | 12159 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12160 | }, |
d8faab4e | 12161 | { |
592a252b | 12162 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12163 | { Bad_Opcode }, |
592a252b | 12164 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12165 | }, |
12166 | { | |
592a252b | 12167 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12168 | { Bad_Opcode }, |
592a252b | 12169 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12170 | }, |
876d4bfa | 12171 | { |
592a252b | 12172 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12173 | { Bad_Opcode }, |
592a252b | 12174 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12175 | }, |
12176 | { | |
592a252b | 12177 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12178 | { Bad_Opcode }, |
592a252b | 12179 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12180 | }, |
12181 | { | |
592a252b | 12182 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12183 | { Bad_Opcode }, |
592a252b | 12184 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12185 | }, |
12186 | { | |
592a252b | 12187 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12188 | { Bad_Opcode }, |
592a252b | 12189 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12190 | }, |
ab4e4ed5 AF |
12191 | { |
12192 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12193 | { "kmovw", { Ew, MaskG }, 0 }, | |
12194 | { Bad_Opcode }, | |
12195 | }, | |
12196 | { | |
12197 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12198 | { "kmovq", { Eq, MaskG }, 0 }, | |
12199 | { Bad_Opcode }, | |
12200 | }, | |
12201 | { | |
12202 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12203 | { "kmovb", { Eb, MaskG }, 0 }, | |
12204 | { Bad_Opcode }, | |
12205 | }, | |
12206 | { | |
12207 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12208 | { "kmovd", { Ed, MaskG }, 0 }, | |
12209 | { Bad_Opcode }, | |
12210 | }, | |
12211 | { | |
12212 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12213 | { Bad_Opcode }, | |
12214 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12215 | }, | |
12216 | { | |
12217 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12218 | { Bad_Opcode }, | |
12219 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12220 | }, | |
12221 | { | |
12222 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12223 | { Bad_Opcode }, | |
12224 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12225 | }, | |
12226 | { | |
12227 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12228 | { Bad_Opcode }, | |
12229 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12230 | }, | |
12231 | { | |
12232 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12233 | { Bad_Opcode }, | |
12234 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12235 | }, | |
12236 | { | |
12237 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12238 | { Bad_Opcode }, | |
12239 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12240 | }, | |
12241 | { | |
12242 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12243 | { Bad_Opcode }, | |
12244 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12245 | }, | |
12246 | { | |
12247 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12248 | { Bad_Opcode }, | |
12249 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12250 | }, | |
12251 | { | |
12252 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12253 | { Bad_Opcode }, | |
12254 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12255 | }, | |
12256 | { | |
12257 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12258 | { Bad_Opcode }, | |
12259 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12260 | }, | |
12261 | { | |
12262 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12263 | { Bad_Opcode }, | |
12264 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12265 | }, | |
12266 | { | |
12267 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12268 | { Bad_Opcode }, | |
12269 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12270 | }, | |
12271 | { | |
12272 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12273 | { Bad_Opcode }, | |
12274 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12275 | }, | |
12276 | { | |
12277 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12278 | { Bad_Opcode }, | |
12279 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12280 | }, | |
12281 | { | |
12282 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12283 | { Bad_Opcode }, | |
12284 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12285 | }, | |
12286 | { | |
12287 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12288 | { Bad_Opcode }, | |
12289 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12290 | }, | |
876d4bfa | 12291 | { |
592a252b L |
12292 | /* MOD_VEX_0FAE_REG_2 */ |
12293 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12294 | }, |
bbedc832 | 12295 | { |
592a252b L |
12296 | /* MOD_VEX_0FAE_REG_3 */ |
12297 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12298 | }, |
144c41d9 | 12299 | { |
592a252b | 12300 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12301 | { Bad_Opcode }, |
6c30d220 | 12302 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12303 | }, |
1afd85e3 | 12304 | { |
592a252b L |
12305 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12306 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12307 | }, |
12308 | { | |
592a252b L |
12309 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12310 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12311 | }, |
75c135a8 | 12312 | { |
592a252b L |
12313 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12314 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12315 | }, |
1afd85e3 | 12316 | { |
592a252b | 12317 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12318 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12319 | }, |
75c135a8 | 12320 | { |
592a252b L |
12321 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12322 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12323 | }, |
1afd85e3 | 12324 | { |
592a252b L |
12325 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12326 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12327 | }, |
12328 | { | |
592a252b L |
12329 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12330 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12331 | }, |
12332 | { | |
592a252b L |
12333 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12334 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12335 | }, |
6c30d220 L |
12336 | { |
12337 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12338 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12339 | }, | |
12340 | { | |
12341 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12342 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12343 | }, |
12344 | { | |
12345 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12346 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12347 | }, |
ab4e4ed5 AF |
12348 | { |
12349 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12350 | { Bad_Opcode }, | |
12351 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12352 | }, | |
12353 | { | |
12354 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12355 | { Bad_Opcode }, | |
12356 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12357 | }, | |
12358 | { | |
12359 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12360 | { Bad_Opcode }, | |
12361 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12362 | }, | |
12363 | { | |
12364 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12365 | { Bad_Opcode }, | |
12366 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12367 | }, | |
12368 | { | |
12369 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12370 | { Bad_Opcode }, | |
12371 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12372 | }, | |
12373 | { | |
12374 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12375 | { Bad_Opcode }, | |
12376 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12377 | }, | |
12378 | { | |
12379 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12380 | { Bad_Opcode }, | |
12381 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12382 | }, | |
12383 | { | |
12384 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12385 | { Bad_Opcode }, | |
12386 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12387 | }, | |
43234a1e L |
12388 | #define NEED_MOD_TABLE |
12389 | #include "i386-dis-evex.h" | |
12390 | #undef NEED_MOD_TABLE | |
b844680a L |
12391 | }; |
12392 | ||
1ceb70f8 | 12393 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12394 | { |
12395 | /* RM_C6_REG_7 */ | |
bf890a93 | 12396 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12397 | }, |
12398 | { | |
12399 | /* RM_C7_REG_7 */ | |
bf890a93 | 12400 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12401 | }, |
b844680a | 12402 | { |
1ceb70f8 | 12403 | /* RM_0F01_REG_0 */ |
592d1631 | 12404 | { Bad_Opcode }, |
bf890a93 IT |
12405 | { "vmcall", { Skip_MODRM }, 0 }, |
12406 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12407 | { "vmresume", { Skip_MODRM }, 0 }, | |
12408 | { "vmxoff", { Skip_MODRM }, 0 }, | |
b844680a L |
12409 | }, |
12410 | { | |
1ceb70f8 | 12411 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12412 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12413 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12414 | { "clac", { Skip_MODRM }, 0 }, | |
12415 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12416 | { Bad_Opcode }, |
12417 | { Bad_Opcode }, | |
12418 | { Bad_Opcode }, | |
bf890a93 | 12419 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12420 | }, |
475a2301 L |
12421 | { |
12422 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12423 | { "xgetbv", { Skip_MODRM }, 0 }, |
12424 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12425 | { Bad_Opcode }, |
12426 | { Bad_Opcode }, | |
bf890a93 IT |
12427 | { "vmfunc", { Skip_MODRM }, 0 }, |
12428 | { "xend", { Skip_MODRM }, 0 }, | |
12429 | { "xtest", { Skip_MODRM }, 0 }, | |
12430 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12431 | }, |
b844680a | 12432 | { |
1ceb70f8 | 12433 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12434 | { "vmrun", { Skip_MODRM }, 0 }, |
12435 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12436 | { "vmload", { Skip_MODRM }, 0 }, | |
12437 | { "vmsave", { Skip_MODRM }, 0 }, | |
12438 | { "stgi", { Skip_MODRM }, 0 }, | |
12439 | { "clgi", { Skip_MODRM }, 0 }, | |
12440 | { "skinit", { Skip_MODRM }, 0 }, | |
12441 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12442 | }, |
8eab4136 L |
12443 | { |
12444 | /* RM_0F01_REG_5 */ | |
12445 | { Bad_Opcode }, | |
12446 | { Bad_Opcode }, | |
12447 | { Bad_Opcode }, | |
12448 | { Bad_Opcode }, | |
12449 | { Bad_Opcode }, | |
12450 | { Bad_Opcode }, | |
12451 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12452 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12453 | }, | |
4e7d34a6 | 12454 | { |
1ceb70f8 | 12455 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12456 | { "swapgs", { Skip_MODRM }, 0 }, |
12457 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12458 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12459 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12460 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a L |
12461 | }, |
12462 | { | |
1ceb70f8 | 12463 | /* RM_0FAE_REG_5 */ |
bf890a93 | 12464 | { "lfence", { Skip_MODRM }, 0 }, |
b844680a L |
12465 | }, |
12466 | { | |
1ceb70f8 | 12467 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12468 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12469 | }, |
bbedc832 | 12470 | { |
1ceb70f8 | 12471 | /* RM_0FAE_REG_7 */ |
9d8596f0 | 12472 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
144c41d9 | 12473 | }, |
b844680a L |
12474 | }; |
12475 | ||
c608c12e AM |
12476 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12477 | ||
f16cd0d5 L |
12478 | /* We use the high bit to indicate different name for the same |
12479 | prefix. */ | |
f16cd0d5 | 12480 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12481 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12482 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12483 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
12484 | |
12485 | static int | |
26ca5450 | 12486 | ckprefix (void) |
252b5132 | 12487 | { |
f16cd0d5 | 12488 | int newrex, i, length; |
52b15da3 | 12489 | rex = 0; |
c0f3af97 | 12490 | rex_ignored = 0; |
252b5132 | 12491 | prefixes = 0; |
7d421014 | 12492 | used_prefixes = 0; |
52b15da3 | 12493 | rex_used = 0; |
f16cd0d5 L |
12494 | last_lock_prefix = -1; |
12495 | last_repz_prefix = -1; | |
12496 | last_repnz_prefix = -1; | |
12497 | last_data_prefix = -1; | |
12498 | last_addr_prefix = -1; | |
12499 | last_rex_prefix = -1; | |
12500 | last_seg_prefix = -1; | |
d9949a36 | 12501 | fwait_prefix = -1; |
285ca992 | 12502 | active_seg_prefix = 0; |
f310f33d L |
12503 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12504 | all_prefixes[i] = 0; | |
12505 | i = 0; | |
f16cd0d5 L |
12506 | length = 0; |
12507 | /* The maximum instruction length is 15bytes. */ | |
12508 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12509 | { |
12510 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12511 | newrex = 0; |
252b5132 RH |
12512 | switch (*codep) |
12513 | { | |
52b15da3 JH |
12514 | /* REX prefixes family. */ |
12515 | case 0x40: | |
12516 | case 0x41: | |
12517 | case 0x42: | |
12518 | case 0x43: | |
12519 | case 0x44: | |
12520 | case 0x45: | |
12521 | case 0x46: | |
12522 | case 0x47: | |
12523 | case 0x48: | |
12524 | case 0x49: | |
12525 | case 0x4a: | |
12526 | case 0x4b: | |
12527 | case 0x4c: | |
12528 | case 0x4d: | |
12529 | case 0x4e: | |
12530 | case 0x4f: | |
f16cd0d5 L |
12531 | if (address_mode == mode_64bit) |
12532 | newrex = *codep; | |
12533 | else | |
12534 | return 1; | |
12535 | last_rex_prefix = i; | |
52b15da3 | 12536 | break; |
252b5132 RH |
12537 | case 0xf3: |
12538 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12539 | last_repz_prefix = i; |
252b5132 RH |
12540 | break; |
12541 | case 0xf2: | |
12542 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12543 | last_repnz_prefix = i; |
252b5132 RH |
12544 | break; |
12545 | case 0xf0: | |
12546 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12547 | last_lock_prefix = i; |
252b5132 RH |
12548 | break; |
12549 | case 0x2e: | |
12550 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12551 | last_seg_prefix = i; |
285ca992 | 12552 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12553 | break; |
12554 | case 0x36: | |
12555 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12556 | last_seg_prefix = i; |
285ca992 | 12557 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12558 | break; |
12559 | case 0x3e: | |
12560 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12561 | last_seg_prefix = i; |
285ca992 | 12562 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12563 | break; |
12564 | case 0x26: | |
12565 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12566 | last_seg_prefix = i; |
285ca992 | 12567 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12568 | break; |
12569 | case 0x64: | |
12570 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12571 | last_seg_prefix = i; |
285ca992 | 12572 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12573 | break; |
12574 | case 0x65: | |
12575 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12576 | last_seg_prefix = i; |
285ca992 | 12577 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12578 | break; |
12579 | case 0x66: | |
12580 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12581 | last_data_prefix = i; |
252b5132 RH |
12582 | break; |
12583 | case 0x67: | |
12584 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12585 | last_addr_prefix = i; |
252b5132 | 12586 | break; |
5076851f | 12587 | case FWAIT_OPCODE: |
252b5132 RH |
12588 | /* fwait is really an instruction. If there are prefixes |
12589 | before the fwait, they belong to the fwait, *not* to the | |
12590 | following instruction. */ | |
d9949a36 | 12591 | fwait_prefix = i; |
3e7d61b2 | 12592 | if (prefixes || rex) |
252b5132 RH |
12593 | { |
12594 | prefixes |= PREFIX_FWAIT; | |
12595 | codep++; | |
6c067bbb RM |
12596 | /* This ensures that the previous REX prefixes are noticed |
12597 | as unused prefixes, as in the return case below. */ | |
12598 | rex_used = rex; | |
f16cd0d5 | 12599 | return 1; |
252b5132 RH |
12600 | } |
12601 | prefixes = PREFIX_FWAIT; | |
12602 | break; | |
12603 | default: | |
f16cd0d5 | 12604 | return 1; |
252b5132 | 12605 | } |
52b15da3 JH |
12606 | /* Rex is ignored when followed by another prefix. */ |
12607 | if (rex) | |
12608 | { | |
3e7d61b2 | 12609 | rex_used = rex; |
f16cd0d5 | 12610 | return 1; |
52b15da3 | 12611 | } |
f16cd0d5 L |
12612 | if (*codep != FWAIT_OPCODE) |
12613 | all_prefixes[i++] = *codep; | |
52b15da3 | 12614 | rex = newrex; |
252b5132 | 12615 | codep++; |
f16cd0d5 L |
12616 | length++; |
12617 | } | |
12618 | return 0; | |
12619 | } | |
12620 | ||
7d421014 ILT |
12621 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12622 | prefix byte. */ | |
12623 | ||
12624 | static const char * | |
26ca5450 | 12625 | prefix_name (int pref, int sizeflag) |
7d421014 | 12626 | { |
0003779b L |
12627 | static const char *rexes [16] = |
12628 | { | |
12629 | "rex", /* 0x40 */ | |
12630 | "rex.B", /* 0x41 */ | |
12631 | "rex.X", /* 0x42 */ | |
12632 | "rex.XB", /* 0x43 */ | |
12633 | "rex.R", /* 0x44 */ | |
12634 | "rex.RB", /* 0x45 */ | |
12635 | "rex.RX", /* 0x46 */ | |
12636 | "rex.RXB", /* 0x47 */ | |
12637 | "rex.W", /* 0x48 */ | |
12638 | "rex.WB", /* 0x49 */ | |
12639 | "rex.WX", /* 0x4a */ | |
12640 | "rex.WXB", /* 0x4b */ | |
12641 | "rex.WR", /* 0x4c */ | |
12642 | "rex.WRB", /* 0x4d */ | |
12643 | "rex.WRX", /* 0x4e */ | |
12644 | "rex.WRXB", /* 0x4f */ | |
12645 | }; | |
12646 | ||
7d421014 ILT |
12647 | switch (pref) |
12648 | { | |
52b15da3 JH |
12649 | /* REX prefixes family. */ |
12650 | case 0x40: | |
52b15da3 | 12651 | case 0x41: |
52b15da3 | 12652 | case 0x42: |
52b15da3 | 12653 | case 0x43: |
52b15da3 | 12654 | case 0x44: |
52b15da3 | 12655 | case 0x45: |
52b15da3 | 12656 | case 0x46: |
52b15da3 | 12657 | case 0x47: |
52b15da3 | 12658 | case 0x48: |
52b15da3 | 12659 | case 0x49: |
52b15da3 | 12660 | case 0x4a: |
52b15da3 | 12661 | case 0x4b: |
52b15da3 | 12662 | case 0x4c: |
52b15da3 | 12663 | case 0x4d: |
52b15da3 | 12664 | case 0x4e: |
52b15da3 | 12665 | case 0x4f: |
0003779b | 12666 | return rexes [pref - 0x40]; |
7d421014 ILT |
12667 | case 0xf3: |
12668 | return "repz"; | |
12669 | case 0xf2: | |
12670 | return "repnz"; | |
12671 | case 0xf0: | |
12672 | return "lock"; | |
12673 | case 0x2e: | |
12674 | return "cs"; | |
12675 | case 0x36: | |
12676 | return "ss"; | |
12677 | case 0x3e: | |
12678 | return "ds"; | |
12679 | case 0x26: | |
12680 | return "es"; | |
12681 | case 0x64: | |
12682 | return "fs"; | |
12683 | case 0x65: | |
12684 | return "gs"; | |
12685 | case 0x66: | |
12686 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12687 | case 0x67: | |
cb712a9e | 12688 | if (address_mode == mode_64bit) |
db6eb5be | 12689 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12690 | else |
2888cb7a | 12691 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12692 | case FWAIT_OPCODE: |
12693 | return "fwait"; | |
f16cd0d5 L |
12694 | case REP_PREFIX: |
12695 | return "rep"; | |
42164a71 L |
12696 | case XACQUIRE_PREFIX: |
12697 | return "xacquire"; | |
12698 | case XRELEASE_PREFIX: | |
12699 | return "xrelease"; | |
7e8b059b L |
12700 | case BND_PREFIX: |
12701 | return "bnd"; | |
7d421014 ILT |
12702 | default: |
12703 | return NULL; | |
12704 | } | |
12705 | } | |
12706 | ||
ce518a5f L |
12707 | static char op_out[MAX_OPERANDS][100]; |
12708 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12709 | static int two_source_ops; |
ce518a5f L |
12710 | static bfd_vma op_address[MAX_OPERANDS]; |
12711 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12712 | static bfd_vma start_pc; |
ce518a5f | 12713 | |
252b5132 RH |
12714 | /* |
12715 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12716 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12717 | * section of the "Virtual 8086 Mode" chapter.) | |
12718 | * 'pc' should be the address of this instruction, it will | |
12719 | * be used to print the target address if this is a relative jump or call | |
12720 | * The function returns the length of this instruction in bytes. | |
12721 | */ | |
12722 | ||
252b5132 | 12723 | static char intel_syntax; |
9d141669 | 12724 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12725 | static char open_char; |
12726 | static char close_char; | |
12727 | static char separator_char; | |
12728 | static char scale_char; | |
12729 | ||
5db04b09 L |
12730 | enum x86_64_isa |
12731 | { | |
12732 | amd64 = 0, | |
12733 | intel64 | |
12734 | }; | |
12735 | ||
12736 | static enum x86_64_isa isa64; | |
12737 | ||
e396998b AM |
12738 | /* Here for backwards compatibility. When gdb stops using |
12739 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12740 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12741 | int |
26ca5450 | 12742 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12743 | { |
12744 | intel_syntax = 0; | |
e396998b AM |
12745 | |
12746 | return print_insn (pc, info); | |
252b5132 RH |
12747 | } |
12748 | ||
12749 | int | |
26ca5450 | 12750 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12751 | { |
12752 | intel_syntax = 1; | |
e396998b AM |
12753 | |
12754 | return print_insn (pc, info); | |
252b5132 RH |
12755 | } |
12756 | ||
e396998b | 12757 | int |
26ca5450 | 12758 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12759 | { |
12760 | intel_syntax = -1; | |
12761 | ||
12762 | return print_insn (pc, info); | |
12763 | } | |
12764 | ||
f59a29b9 L |
12765 | void |
12766 | print_i386_disassembler_options (FILE *stream) | |
12767 | { | |
12768 | fprintf (stream, _("\n\ | |
12769 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12770 | with the -M switch (multiple options should be separated by commas):\n")); | |
12771 | ||
12772 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12773 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12774 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12775 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12776 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12777 | fprintf (stream, _(" att-mnemonic\n" |
12778 | " Display instruction in AT&T mnemonic\n")); | |
12779 | fprintf (stream, _(" intel-mnemonic\n" | |
12780 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12781 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12782 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12783 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12784 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12785 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12786 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12787 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12788 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12789 | } |
12790 | ||
592d1631 | 12791 | /* Bad opcode. */ |
bf890a93 | 12792 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12793 | |
b844680a L |
12794 | /* Get a pointer to struct dis386 with a valid name. */ |
12795 | ||
12796 | static const struct dis386 * | |
8bb15339 | 12797 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12798 | { |
91d6fa6a | 12799 | int vindex, vex_table_index; |
b844680a L |
12800 | |
12801 | if (dp->name != NULL) | |
12802 | return dp; | |
12803 | ||
12804 | switch (dp->op[0].bytemode) | |
12805 | { | |
1ceb70f8 L |
12806 | case USE_REG_TABLE: |
12807 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12808 | break; | |
12809 | ||
12810 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12811 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12812 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12813 | break; |
12814 | ||
12815 | case USE_RM_TABLE: | |
12816 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12817 | break; |
12818 | ||
4e7d34a6 | 12819 | case USE_PREFIX_TABLE: |
c0f3af97 | 12820 | if (need_vex) |
b844680a | 12821 | { |
c0f3af97 L |
12822 | /* The prefix in VEX is implicit. */ |
12823 | switch (vex.prefix) | |
12824 | { | |
12825 | case 0: | |
91d6fa6a | 12826 | vindex = 0; |
c0f3af97 L |
12827 | break; |
12828 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12829 | vindex = 1; |
c0f3af97 L |
12830 | break; |
12831 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12832 | vindex = 2; |
c0f3af97 L |
12833 | break; |
12834 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12835 | vindex = 3; |
c0f3af97 L |
12836 | break; |
12837 | default: | |
12838 | abort (); | |
12839 | break; | |
12840 | } | |
b844680a | 12841 | } |
7bb15c6f | 12842 | else |
b844680a | 12843 | { |
285ca992 L |
12844 | int last_prefix = -1; |
12845 | int prefix = 0; | |
91d6fa6a | 12846 | vindex = 0; |
285ca992 L |
12847 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12848 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12849 | last one wins. */ | |
12850 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12851 | { |
285ca992 | 12852 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12853 | { |
285ca992 L |
12854 | vindex = 1; |
12855 | prefix = PREFIX_REPZ; | |
12856 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12857 | } |
12858 | else | |
b844680a | 12859 | { |
285ca992 L |
12860 | vindex = 3; |
12861 | prefix = PREFIX_REPNZ; | |
12862 | last_prefix = last_repnz_prefix; | |
b844680a | 12863 | } |
285ca992 | 12864 | |
507bd325 L |
12865 | /* Check if prefix should be ignored. */ |
12866 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12867 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12868 | & prefix) != 0) | |
285ca992 L |
12869 | vindex = 0; |
12870 | } | |
12871 | ||
12872 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12873 | { | |
12874 | vindex = 2; | |
12875 | prefix = PREFIX_DATA; | |
12876 | last_prefix = last_data_prefix; | |
12877 | } | |
12878 | ||
12879 | if (vindex != 0) | |
12880 | { | |
12881 | used_prefixes |= prefix; | |
12882 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12883 | } |
12884 | } | |
91d6fa6a | 12885 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12886 | break; |
12887 | ||
4e7d34a6 | 12888 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12889 | vindex = address_mode == mode_64bit ? 1 : 0; |
12890 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12891 | break; |
12892 | ||
4e7d34a6 | 12893 | case USE_3BYTE_TABLE: |
8bb15339 | 12894 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12895 | vindex = *codep++; |
12896 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12897 | end_codep = codep; |
8bb15339 L |
12898 | modrm.mod = (*codep >> 6) & 3; |
12899 | modrm.reg = (*codep >> 3) & 7; | |
12900 | modrm.rm = *codep & 7; | |
12901 | break; | |
12902 | ||
c0f3af97 L |
12903 | case USE_VEX_LEN_TABLE: |
12904 | if (!need_vex) | |
12905 | abort (); | |
12906 | ||
12907 | switch (vex.length) | |
12908 | { | |
12909 | case 128: | |
91d6fa6a | 12910 | vindex = 0; |
c0f3af97 L |
12911 | break; |
12912 | case 256: | |
91d6fa6a | 12913 | vindex = 1; |
c0f3af97 L |
12914 | break; |
12915 | default: | |
12916 | abort (); | |
12917 | break; | |
12918 | } | |
12919 | ||
91d6fa6a | 12920 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12921 | break; |
12922 | ||
f88c9eb0 SP |
12923 | case USE_XOP_8F_TABLE: |
12924 | FETCH_DATA (info, codep + 3); | |
12925 | /* All bits in the REX prefix are ignored. */ | |
12926 | rex_ignored = rex; | |
12927 | rex = ~(*codep >> 5) & 0x7; | |
12928 | ||
12929 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12930 | switch ((*codep & 0x1f)) | |
12931 | { | |
12932 | default: | |
f07af43e L |
12933 | dp = &bad_opcode; |
12934 | return dp; | |
5dd85c99 SP |
12935 | case 0x8: |
12936 | vex_table_index = XOP_08; | |
12937 | break; | |
f88c9eb0 SP |
12938 | case 0x9: |
12939 | vex_table_index = XOP_09; | |
12940 | break; | |
12941 | case 0xa: | |
12942 | vex_table_index = XOP_0A; | |
12943 | break; | |
12944 | } | |
12945 | codep++; | |
12946 | vex.w = *codep & 0x80; | |
12947 | if (vex.w && address_mode == mode_64bit) | |
12948 | rex |= REX_W; | |
12949 | ||
12950 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12951 | if (address_mode != mode_64bit | |
12952 | && vex.register_specifier > 0x7) | |
f07af43e L |
12953 | { |
12954 | dp = &bad_opcode; | |
12955 | return dp; | |
12956 | } | |
f88c9eb0 SP |
12957 | |
12958 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12959 | switch ((*codep & 0x3)) | |
12960 | { | |
12961 | case 0: | |
12962 | vex.prefix = 0; | |
12963 | break; | |
12964 | case 1: | |
12965 | vex.prefix = DATA_PREFIX_OPCODE; | |
12966 | break; | |
12967 | case 2: | |
12968 | vex.prefix = REPE_PREFIX_OPCODE; | |
12969 | break; | |
12970 | case 3: | |
12971 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12972 | break; | |
12973 | } | |
12974 | need_vex = 1; | |
12975 | need_vex_reg = 1; | |
12976 | codep++; | |
91d6fa6a NC |
12977 | vindex = *codep++; |
12978 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12979 | |
285ca992 | 12980 | end_codep = codep; |
c48244a5 SP |
12981 | FETCH_DATA (info, codep + 1); |
12982 | modrm.mod = (*codep >> 6) & 3; | |
12983 | modrm.reg = (*codep >> 3) & 7; | |
12984 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12985 | break; |
12986 | ||
c0f3af97 | 12987 | case USE_VEX_C4_TABLE: |
43234a1e | 12988 | /* VEX prefix. */ |
c0f3af97 L |
12989 | FETCH_DATA (info, codep + 3); |
12990 | /* All bits in the REX prefix are ignored. */ | |
12991 | rex_ignored = rex; | |
12992 | rex = ~(*codep >> 5) & 0x7; | |
12993 | switch ((*codep & 0x1f)) | |
12994 | { | |
12995 | default: | |
f07af43e L |
12996 | dp = &bad_opcode; |
12997 | return dp; | |
c0f3af97 | 12998 | case 0x1: |
f88c9eb0 | 12999 | vex_table_index = VEX_0F; |
c0f3af97 L |
13000 | break; |
13001 | case 0x2: | |
f88c9eb0 | 13002 | vex_table_index = VEX_0F38; |
c0f3af97 L |
13003 | break; |
13004 | case 0x3: | |
f88c9eb0 | 13005 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
13006 | break; |
13007 | } | |
13008 | codep++; | |
13009 | vex.w = *codep & 0x80; | |
13010 | if (vex.w && address_mode == mode_64bit) | |
13011 | rex |= REX_W; | |
13012 | ||
13013 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13014 | if (address_mode != mode_64bit | |
13015 | && vex.register_specifier > 0x7) | |
f07af43e L |
13016 | { |
13017 | dp = &bad_opcode; | |
13018 | return dp; | |
13019 | } | |
c0f3af97 L |
13020 | |
13021 | vex.length = (*codep & 0x4) ? 256 : 128; | |
13022 | switch ((*codep & 0x3)) | |
13023 | { | |
13024 | case 0: | |
13025 | vex.prefix = 0; | |
13026 | break; | |
13027 | case 1: | |
13028 | vex.prefix = DATA_PREFIX_OPCODE; | |
13029 | break; | |
13030 | case 2: | |
13031 | vex.prefix = REPE_PREFIX_OPCODE; | |
13032 | break; | |
13033 | case 3: | |
13034 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13035 | break; | |
13036 | } | |
13037 | need_vex = 1; | |
13038 | need_vex_reg = 1; | |
13039 | codep++; | |
91d6fa6a NC |
13040 | vindex = *codep++; |
13041 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 13042 | end_codep = codep; |
c0f3af97 | 13043 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 13044 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
13045 | { |
13046 | FETCH_DATA (info, codep + 1); | |
13047 | modrm.mod = (*codep >> 6) & 3; | |
13048 | modrm.reg = (*codep >> 3) & 7; | |
13049 | modrm.rm = *codep & 7; | |
13050 | } | |
13051 | break; | |
13052 | ||
13053 | case USE_VEX_C5_TABLE: | |
43234a1e | 13054 | /* VEX prefix. */ |
c0f3af97 L |
13055 | FETCH_DATA (info, codep + 2); |
13056 | /* All bits in the REX prefix are ignored. */ | |
13057 | rex_ignored = rex; | |
13058 | rex = (*codep & 0x80) ? 0 : REX_R; | |
13059 | ||
13060 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13061 | if (address_mode != mode_64bit | |
13062 | && vex.register_specifier > 0x7) | |
f07af43e L |
13063 | { |
13064 | dp = &bad_opcode; | |
13065 | return dp; | |
13066 | } | |
c0f3af97 | 13067 | |
759a05ce L |
13068 | vex.w = 0; |
13069 | ||
c0f3af97 L |
13070 | vex.length = (*codep & 0x4) ? 256 : 128; |
13071 | switch ((*codep & 0x3)) | |
13072 | { | |
13073 | case 0: | |
13074 | vex.prefix = 0; | |
13075 | break; | |
13076 | case 1: | |
13077 | vex.prefix = DATA_PREFIX_OPCODE; | |
13078 | break; | |
13079 | case 2: | |
13080 | vex.prefix = REPE_PREFIX_OPCODE; | |
13081 | break; | |
13082 | case 3: | |
13083 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13084 | break; | |
13085 | } | |
13086 | need_vex = 1; | |
13087 | need_vex_reg = 1; | |
13088 | codep++; | |
91d6fa6a NC |
13089 | vindex = *codep++; |
13090 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 13091 | end_codep = codep; |
c0f3af97 | 13092 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 13093 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
13094 | { |
13095 | FETCH_DATA (info, codep + 1); | |
13096 | modrm.mod = (*codep >> 6) & 3; | |
13097 | modrm.reg = (*codep >> 3) & 7; | |
13098 | modrm.rm = *codep & 7; | |
13099 | } | |
13100 | break; | |
13101 | ||
9e30b8e0 L |
13102 | case USE_VEX_W_TABLE: |
13103 | if (!need_vex) | |
13104 | abort (); | |
13105 | ||
13106 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
13107 | break; | |
13108 | ||
43234a1e L |
13109 | case USE_EVEX_TABLE: |
13110 | two_source_ops = 0; | |
13111 | /* EVEX prefix. */ | |
13112 | vex.evex = 1; | |
13113 | FETCH_DATA (info, codep + 4); | |
13114 | /* All bits in the REX prefix are ignored. */ | |
13115 | rex_ignored = rex; | |
13116 | /* The first byte after 0x62. */ | |
13117 | rex = ~(*codep >> 5) & 0x7; | |
13118 | vex.r = *codep & 0x10; | |
13119 | switch ((*codep & 0xf)) | |
13120 | { | |
13121 | default: | |
13122 | return &bad_opcode; | |
13123 | case 0x1: | |
13124 | vex_table_index = EVEX_0F; | |
13125 | break; | |
13126 | case 0x2: | |
13127 | vex_table_index = EVEX_0F38; | |
13128 | break; | |
13129 | case 0x3: | |
13130 | vex_table_index = EVEX_0F3A; | |
13131 | break; | |
13132 | } | |
13133 | ||
13134 | /* The second byte after 0x62. */ | |
13135 | codep++; | |
13136 | vex.w = *codep & 0x80; | |
13137 | if (vex.w && address_mode == mode_64bit) | |
13138 | rex |= REX_W; | |
13139 | ||
13140 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13141 | if (address_mode != mode_64bit) | |
13142 | { | |
13143 | /* In 16/32-bit mode silently ignore following bits. */ | |
13144 | rex &= ~REX_B; | |
13145 | vex.r = 1; | |
13146 | vex.v = 1; | |
13147 | vex.register_specifier &= 0x7; | |
13148 | } | |
13149 | ||
13150 | /* The U bit. */ | |
13151 | if (!(*codep & 0x4)) | |
13152 | return &bad_opcode; | |
13153 | ||
13154 | switch ((*codep & 0x3)) | |
13155 | { | |
13156 | case 0: | |
13157 | vex.prefix = 0; | |
13158 | break; | |
13159 | case 1: | |
13160 | vex.prefix = DATA_PREFIX_OPCODE; | |
13161 | break; | |
13162 | case 2: | |
13163 | vex.prefix = REPE_PREFIX_OPCODE; | |
13164 | break; | |
13165 | case 3: | |
13166 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13167 | break; | |
13168 | } | |
13169 | ||
13170 | /* The third byte after 0x62. */ | |
13171 | codep++; | |
13172 | ||
13173 | /* Remember the static rounding bits. */ | |
13174 | vex.ll = (*codep >> 5) & 3; | |
13175 | vex.b = (*codep & 0x10) != 0; | |
13176 | ||
13177 | vex.v = *codep & 0x8; | |
13178 | vex.mask_register_specifier = *codep & 0x7; | |
13179 | vex.zeroing = *codep & 0x80; | |
13180 | ||
13181 | need_vex = 1; | |
13182 | need_vex_reg = 1; | |
13183 | codep++; | |
13184 | vindex = *codep++; | |
13185 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13186 | end_codep = codep; |
43234a1e L |
13187 | FETCH_DATA (info, codep + 1); |
13188 | modrm.mod = (*codep >> 6) & 3; | |
13189 | modrm.reg = (*codep >> 3) & 7; | |
13190 | modrm.rm = *codep & 7; | |
13191 | ||
13192 | /* Set vector length. */ | |
13193 | if (modrm.mod == 3 && vex.b) | |
13194 | vex.length = 512; | |
13195 | else | |
13196 | { | |
13197 | switch (vex.ll) | |
13198 | { | |
13199 | case 0x0: | |
13200 | vex.length = 128; | |
13201 | break; | |
13202 | case 0x1: | |
13203 | vex.length = 256; | |
13204 | break; | |
13205 | case 0x2: | |
13206 | vex.length = 512; | |
13207 | break; | |
13208 | default: | |
13209 | return &bad_opcode; | |
13210 | } | |
13211 | } | |
13212 | break; | |
13213 | ||
592d1631 L |
13214 | case 0: |
13215 | dp = &bad_opcode; | |
13216 | break; | |
13217 | ||
b844680a | 13218 | default: |
d34b5006 | 13219 | abort (); |
b844680a L |
13220 | } |
13221 | ||
13222 | if (dp->name != NULL) | |
13223 | return dp; | |
13224 | else | |
8bb15339 | 13225 | return get_valid_dis386 (dp, info); |
b844680a L |
13226 | } |
13227 | ||
dfc8cf43 | 13228 | static void |
55cf16e1 | 13229 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13230 | { |
13231 | /* If modrm.mod == 3, operand must be register. */ | |
13232 | if (need_modrm | |
55cf16e1 | 13233 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13234 | && modrm.mod != 3 |
13235 | && modrm.rm == 4) | |
13236 | { | |
13237 | FETCH_DATA (info, codep + 2); | |
13238 | sib.index = (codep [1] >> 3) & 7; | |
13239 | sib.scale = (codep [1] >> 6) & 3; | |
13240 | sib.base = codep [1] & 7; | |
13241 | } | |
13242 | } | |
13243 | ||
e396998b | 13244 | static int |
26ca5450 | 13245 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13246 | { |
2da11e11 | 13247 | const struct dis386 *dp; |
252b5132 | 13248 | int i; |
ce518a5f | 13249 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13250 | int needcomma; |
df18fdba | 13251 | int sizeflag, orig_sizeflag; |
e396998b | 13252 | const char *p; |
252b5132 | 13253 | struct dis_private priv; |
f16cd0d5 | 13254 | int prefix_length; |
252b5132 | 13255 | |
d7921315 L |
13256 | priv.orig_sizeflag = AFLAG | DFLAG; |
13257 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13258 | address_mode = mode_32bit; |
2da11e11 | 13259 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13260 | { |
13261 | address_mode = mode_16bit; | |
13262 | priv.orig_sizeflag = 0; | |
13263 | } | |
2da11e11 | 13264 | else |
d7921315 L |
13265 | address_mode = mode_64bit; |
13266 | ||
13267 | if (intel_syntax == (char) -1) | |
13268 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13269 | |
13270 | for (p = info->disassembler_options; p != NULL; ) | |
13271 | { | |
5db04b09 L |
13272 | if (CONST_STRNEQ (p, "amd64")) |
13273 | isa64 = amd64; | |
13274 | else if (CONST_STRNEQ (p, "intel64")) | |
13275 | isa64 = intel64; | |
13276 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13277 | { |
cb712a9e | 13278 | address_mode = mode_64bit; |
e396998b AM |
13279 | priv.orig_sizeflag = AFLAG | DFLAG; |
13280 | } | |
0112cd26 | 13281 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13282 | { |
cb712a9e | 13283 | address_mode = mode_32bit; |
e396998b AM |
13284 | priv.orig_sizeflag = AFLAG | DFLAG; |
13285 | } | |
0112cd26 | 13286 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13287 | { |
cb712a9e | 13288 | address_mode = mode_16bit; |
e396998b AM |
13289 | priv.orig_sizeflag = 0; |
13290 | } | |
0112cd26 | 13291 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13292 | { |
13293 | intel_syntax = 1; | |
9d141669 L |
13294 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13295 | intel_mnemonic = 1; | |
e396998b | 13296 | } |
0112cd26 | 13297 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13298 | { |
13299 | intel_syntax = 0; | |
9d141669 L |
13300 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13301 | intel_mnemonic = 0; | |
e396998b | 13302 | } |
0112cd26 | 13303 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13304 | { |
f59a29b9 L |
13305 | if (address_mode == mode_64bit) |
13306 | { | |
13307 | if (p[4] == '3' && p[5] == '2') | |
13308 | priv.orig_sizeflag &= ~AFLAG; | |
13309 | else if (p[4] == '6' && p[5] == '4') | |
13310 | priv.orig_sizeflag |= AFLAG; | |
13311 | } | |
13312 | else | |
13313 | { | |
13314 | if (p[4] == '1' && p[5] == '6') | |
13315 | priv.orig_sizeflag &= ~AFLAG; | |
13316 | else if (p[4] == '3' && p[5] == '2') | |
13317 | priv.orig_sizeflag |= AFLAG; | |
13318 | } | |
e396998b | 13319 | } |
0112cd26 | 13320 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13321 | { |
13322 | if (p[4] == '1' && p[5] == '6') | |
13323 | priv.orig_sizeflag &= ~DFLAG; | |
13324 | else if (p[4] == '3' && p[5] == '2') | |
13325 | priv.orig_sizeflag |= DFLAG; | |
13326 | } | |
0112cd26 | 13327 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13328 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13329 | ||
13330 | p = strchr (p, ','); | |
13331 | if (p != NULL) | |
13332 | p++; | |
13333 | } | |
13334 | ||
c0f92bf9 L |
13335 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13336 | { | |
13337 | (*info->fprintf_func) (info->stream, | |
13338 | _("64-bit address is disabled")); | |
13339 | return -1; | |
13340 | } | |
13341 | ||
e396998b AM |
13342 | if (intel_syntax) |
13343 | { | |
13344 | names64 = intel_names64; | |
13345 | names32 = intel_names32; | |
13346 | names16 = intel_names16; | |
13347 | names8 = intel_names8; | |
13348 | names8rex = intel_names8rex; | |
13349 | names_seg = intel_names_seg; | |
b9733481 | 13350 | names_mm = intel_names_mm; |
7e8b059b | 13351 | names_bnd = intel_names_bnd; |
b9733481 L |
13352 | names_xmm = intel_names_xmm; |
13353 | names_ymm = intel_names_ymm; | |
43234a1e | 13354 | names_zmm = intel_names_zmm; |
db51cc60 L |
13355 | index64 = intel_index64; |
13356 | index32 = intel_index32; | |
43234a1e | 13357 | names_mask = intel_names_mask; |
e396998b AM |
13358 | index16 = intel_index16; |
13359 | open_char = '['; | |
13360 | close_char = ']'; | |
13361 | separator_char = '+'; | |
13362 | scale_char = '*'; | |
13363 | } | |
13364 | else | |
13365 | { | |
13366 | names64 = att_names64; | |
13367 | names32 = att_names32; | |
13368 | names16 = att_names16; | |
13369 | names8 = att_names8; | |
13370 | names8rex = att_names8rex; | |
13371 | names_seg = att_names_seg; | |
b9733481 | 13372 | names_mm = att_names_mm; |
7e8b059b | 13373 | names_bnd = att_names_bnd; |
b9733481 L |
13374 | names_xmm = att_names_xmm; |
13375 | names_ymm = att_names_ymm; | |
43234a1e | 13376 | names_zmm = att_names_zmm; |
db51cc60 L |
13377 | index64 = att_index64; |
13378 | index32 = att_index32; | |
43234a1e | 13379 | names_mask = att_names_mask; |
e396998b AM |
13380 | index16 = att_index16; |
13381 | open_char = '('; | |
13382 | close_char = ')'; | |
13383 | separator_char = ','; | |
13384 | scale_char = ','; | |
13385 | } | |
2da11e11 | 13386 | |
4fe53c98 | 13387 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13388 | puts most long word instructions on a single line. Use 8 bytes |
13389 | for Intel L1OM. */ | |
d7921315 | 13390 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13391 | info->bytes_per_line = 8; |
13392 | else | |
13393 | info->bytes_per_line = 7; | |
252b5132 | 13394 | |
26ca5450 | 13395 | info->private_data = &priv; |
252b5132 RH |
13396 | priv.max_fetched = priv.the_buffer; |
13397 | priv.insn_start = pc; | |
252b5132 RH |
13398 | |
13399 | obuf[0] = 0; | |
ce518a5f L |
13400 | for (i = 0; i < MAX_OPERANDS; ++i) |
13401 | { | |
13402 | op_out[i][0] = 0; | |
13403 | op_index[i] = -1; | |
13404 | } | |
252b5132 RH |
13405 | |
13406 | the_info = info; | |
13407 | start_pc = pc; | |
e396998b AM |
13408 | start_codep = priv.the_buffer; |
13409 | codep = priv.the_buffer; | |
252b5132 | 13410 | |
8df14d78 | 13411 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13412 | { |
7d421014 ILT |
13413 | const char *name; |
13414 | ||
5076851f | 13415 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13416 | means we have an incomplete instruction of some sort. Just |
13417 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13418 | if (codep > priv.the_buffer) | |
5076851f | 13419 | { |
e396998b | 13420 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13421 | if (name != NULL) |
13422 | (*info->fprintf_func) (info->stream, "%s", name); | |
13423 | else | |
5076851f | 13424 | { |
7d421014 ILT |
13425 | /* Just print the first byte as a .byte instruction. */ |
13426 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13427 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13428 | } |
5076851f | 13429 | |
7d421014 | 13430 | return 1; |
5076851f ILT |
13431 | } |
13432 | ||
13433 | return -1; | |
13434 | } | |
13435 | ||
52b15da3 | 13436 | obufp = obuf; |
f16cd0d5 L |
13437 | sizeflag = priv.orig_sizeflag; |
13438 | ||
13439 | if (!ckprefix () || rex_used) | |
13440 | { | |
13441 | /* Too many prefixes or unused REX prefixes. */ | |
13442 | for (i = 0; | |
f6dd4781 | 13443 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13444 | i++) |
de882298 | 13445 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13446 | i == 0 ? "" : " ", |
f16cd0d5 | 13447 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13448 | return i; |
f16cd0d5 | 13449 | } |
252b5132 RH |
13450 | |
13451 | insn_codep = codep; | |
13452 | ||
13453 | FETCH_DATA (info, codep + 1); | |
13454 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13455 | ||
3e7d61b2 | 13456 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13457 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13458 | { |
86a80a50 | 13459 | /* Handle prefixes before fwait. */ |
d9949a36 | 13460 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13461 | i++) |
13462 | (*info->fprintf_func) (info->stream, "%s ", | |
13463 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13464 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13465 | return i + 1; |
252b5132 RH |
13466 | } |
13467 | ||
252b5132 RH |
13468 | if (*codep == 0x0f) |
13469 | { | |
eec0f4ca | 13470 | unsigned char threebyte; |
5f40e14d JS |
13471 | |
13472 | codep++; | |
13473 | FETCH_DATA (info, codep + 1); | |
13474 | threebyte = *codep; | |
eec0f4ca | 13475 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13476 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13477 | codep++; |
252b5132 RH |
13478 | } |
13479 | else | |
13480 | { | |
6439fc28 | 13481 | dp = &dis386[*codep]; |
252b5132 | 13482 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13483 | codep++; |
252b5132 | 13484 | } |
246c51aa | 13485 | |
df18fdba L |
13486 | /* Save sizeflag for printing the extra prefixes later before updating |
13487 | it for mnemonic and operand processing. The prefix names depend | |
13488 | only on the address mode. */ | |
13489 | orig_sizeflag = sizeflag; | |
c608c12e | 13490 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13491 | sizeflag ^= AFLAG; |
b844680a | 13492 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13493 | sizeflag ^= DFLAG; |
3ffd33cf | 13494 | |
285ca992 | 13495 | end_codep = codep; |
8bb15339 | 13496 | if (need_modrm) |
252b5132 RH |
13497 | { |
13498 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13499 | modrm.mod = (*codep >> 6) & 3; |
13500 | modrm.reg = (*codep >> 3) & 7; | |
13501 | modrm.rm = *codep & 7; | |
252b5132 RH |
13502 | } |
13503 | ||
42d5f9c6 MS |
13504 | need_vex = 0; |
13505 | need_vex_reg = 0; | |
13506 | vex_w_done = 0; | |
43234a1e | 13507 | vex.evex = 0; |
55b126d4 | 13508 | |
ce518a5f | 13509 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13510 | { |
55cf16e1 | 13511 | get_sib (info, sizeflag); |
252b5132 RH |
13512 | dofloat (sizeflag); |
13513 | } | |
13514 | else | |
13515 | { | |
8bb15339 | 13516 | dp = get_valid_dis386 (dp, info); |
b844680a | 13517 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13518 | { |
55cf16e1 | 13519 | get_sib (info, sizeflag); |
ce518a5f L |
13520 | for (i = 0; i < MAX_OPERANDS; ++i) |
13521 | { | |
246c51aa | 13522 | obufp = op_out[i]; |
ce518a5f L |
13523 | op_ad = MAX_OPERANDS - 1 - i; |
13524 | if (dp->op[i].rtn) | |
13525 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13526 | /* For EVEX instruction after the last operand masking |
13527 | should be printed. */ | |
13528 | if (i == 0 && vex.evex) | |
13529 | { | |
13530 | /* Don't print {%k0}. */ | |
13531 | if (vex.mask_register_specifier) | |
13532 | { | |
13533 | oappend ("{"); | |
13534 | oappend (names_mask[vex.mask_register_specifier]); | |
13535 | oappend ("}"); | |
13536 | } | |
13537 | if (vex.zeroing) | |
13538 | oappend ("{z}"); | |
13539 | } | |
ce518a5f | 13540 | } |
6439fc28 | 13541 | } |
252b5132 RH |
13542 | } |
13543 | ||
d869730d | 13544 | /* Check if the REX prefix is used. */ |
e2e6193d | 13545 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13546 | all_prefixes[last_rex_prefix] = 0; |
13547 | ||
5e6718e4 | 13548 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13549 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13550 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13551 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13552 | all_prefixes[last_seg_prefix] = 0; |
13553 | ||
5e6718e4 | 13554 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13555 | if ((prefixes & PREFIX_ADDR) != 0 |
13556 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13557 | all_prefixes[last_addr_prefix] = 0; | |
13558 | ||
df18fdba L |
13559 | /* Check if the DATA prefix is used. */ |
13560 | if ((prefixes & PREFIX_DATA) != 0 | |
13561 | && (used_prefixes & PREFIX_DATA) != 0) | |
13562 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13563 | |
df18fdba | 13564 | /* Print the extra prefixes. */ |
f16cd0d5 | 13565 | prefix_length = 0; |
f310f33d | 13566 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13567 | if (all_prefixes[i]) |
13568 | { | |
13569 | const char *name; | |
df18fdba | 13570 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13571 | if (name == NULL) |
13572 | abort (); | |
13573 | prefix_length += strlen (name) + 1; | |
13574 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13575 | } | |
b844680a | 13576 | |
285ca992 L |
13577 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13578 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13579 | used by putop and MMX/SSE operand and may be overriden by the | |
13580 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13581 | separately. */ | |
3888916d | 13582 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13583 | && dp != &bad_opcode |
13584 | && (((prefixes | |
13585 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13586 | && (used_prefixes | |
13587 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13588 | || ((((prefixes | |
13589 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13590 | == PREFIX_DATA) | |
13591 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13592 | { | |
13593 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13594 | return end_codep - priv.the_buffer; | |
13595 | } | |
13596 | ||
f16cd0d5 L |
13597 | /* Check maximum code length. */ |
13598 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13599 | { | |
13600 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13601 | return MAX_CODE_LENGTH; | |
13602 | } | |
b844680a | 13603 | |
ea397f5b | 13604 | obufp = mnemonicendp; |
f16cd0d5 | 13605 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13606 | oappend (" "); |
13607 | oappend (" "); | |
13608 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13609 | ||
13610 | /* The enter and bound instructions are printed with operands in the same | |
13611 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13612 | if (intel_syntax || two_source_ops) |
252b5132 | 13613 | { |
185b1163 L |
13614 | bfd_vma riprel; |
13615 | ||
ce518a5f | 13616 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13617 | op_txt[i] = op_out[i]; |
246c51aa | 13618 | |
3a8547d2 JB |
13619 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13620 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13621 | { | |
13622 | op_txt[2] = op_out[3]; | |
13623 | op_txt[3] = op_out[2]; | |
13624 | } | |
13625 | ||
ce518a5f L |
13626 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13627 | { | |
6c067bbb RM |
13628 | op_ad = op_index[i]; |
13629 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13630 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13631 | riprel = op_riprel[i]; |
13632 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13633 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13634 | } |
252b5132 RH |
13635 | } |
13636 | else | |
13637 | { | |
ce518a5f | 13638 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13639 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13640 | } |
13641 | ||
ce518a5f L |
13642 | needcomma = 0; |
13643 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13644 | if (*op_txt[i]) | |
13645 | { | |
13646 | if (needcomma) | |
13647 | (*info->fprintf_func) (info->stream, ","); | |
13648 | if (op_index[i] != -1 && !op_riprel[i]) | |
13649 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13650 | else | |
13651 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13652 | needcomma = 1; | |
13653 | } | |
050dfa73 | 13654 | |
ce518a5f | 13655 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13656 | if (op_index[i] != -1 && op_riprel[i]) |
13657 | { | |
13658 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13659 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13660 | + op_address[op_index[i]]), info); |
185b1163 | 13661 | break; |
52b15da3 | 13662 | } |
e396998b | 13663 | return codep - priv.the_buffer; |
252b5132 RH |
13664 | } |
13665 | ||
6439fc28 | 13666 | static const char *float_mem[] = { |
252b5132 | 13667 | /* d8 */ |
7c52e0e8 L |
13668 | "fadd{s|}", |
13669 | "fmul{s|}", | |
13670 | "fcom{s|}", | |
13671 | "fcomp{s|}", | |
13672 | "fsub{s|}", | |
13673 | "fsubr{s|}", | |
13674 | "fdiv{s|}", | |
13675 | "fdivr{s|}", | |
db6eb5be | 13676 | /* d9 */ |
7c52e0e8 | 13677 | "fld{s|}", |
252b5132 | 13678 | "(bad)", |
7c52e0e8 L |
13679 | "fst{s|}", |
13680 | "fstp{s|}", | |
9306ca4a | 13681 | "fldenvIC", |
252b5132 | 13682 | "fldcw", |
9306ca4a | 13683 | "fNstenvIC", |
252b5132 RH |
13684 | "fNstcw", |
13685 | /* da */ | |
7c52e0e8 L |
13686 | "fiadd{l|}", |
13687 | "fimul{l|}", | |
13688 | "ficom{l|}", | |
13689 | "ficomp{l|}", | |
13690 | "fisub{l|}", | |
13691 | "fisubr{l|}", | |
13692 | "fidiv{l|}", | |
13693 | "fidivr{l|}", | |
252b5132 | 13694 | /* db */ |
7c52e0e8 L |
13695 | "fild{l|}", |
13696 | "fisttp{l|}", | |
13697 | "fist{l|}", | |
13698 | "fistp{l|}", | |
252b5132 | 13699 | "(bad)", |
6439fc28 | 13700 | "fld{t||t|}", |
252b5132 | 13701 | "(bad)", |
6439fc28 | 13702 | "fstp{t||t|}", |
252b5132 | 13703 | /* dc */ |
7c52e0e8 L |
13704 | "fadd{l|}", |
13705 | "fmul{l|}", | |
13706 | "fcom{l|}", | |
13707 | "fcomp{l|}", | |
13708 | "fsub{l|}", | |
13709 | "fsubr{l|}", | |
13710 | "fdiv{l|}", | |
13711 | "fdivr{l|}", | |
252b5132 | 13712 | /* dd */ |
7c52e0e8 L |
13713 | "fld{l|}", |
13714 | "fisttp{ll|}", | |
13715 | "fst{l||}", | |
13716 | "fstp{l|}", | |
9306ca4a | 13717 | "frstorIC", |
252b5132 | 13718 | "(bad)", |
9306ca4a | 13719 | "fNsaveIC", |
252b5132 RH |
13720 | "fNstsw", |
13721 | /* de */ | |
13722 | "fiadd", | |
13723 | "fimul", | |
13724 | "ficom", | |
13725 | "ficomp", | |
13726 | "fisub", | |
13727 | "fisubr", | |
13728 | "fidiv", | |
13729 | "fidivr", | |
13730 | /* df */ | |
13731 | "fild", | |
ca164297 | 13732 | "fisttp", |
252b5132 RH |
13733 | "fist", |
13734 | "fistp", | |
13735 | "fbld", | |
7c52e0e8 | 13736 | "fild{ll|}", |
252b5132 | 13737 | "fbstp", |
7c52e0e8 | 13738 | "fistp{ll|}", |
1d9f512f AM |
13739 | }; |
13740 | ||
13741 | static const unsigned char float_mem_mode[] = { | |
13742 | /* d8 */ | |
13743 | d_mode, | |
13744 | d_mode, | |
13745 | d_mode, | |
13746 | d_mode, | |
13747 | d_mode, | |
13748 | d_mode, | |
13749 | d_mode, | |
13750 | d_mode, | |
13751 | /* d9 */ | |
13752 | d_mode, | |
13753 | 0, | |
13754 | d_mode, | |
13755 | d_mode, | |
13756 | 0, | |
13757 | w_mode, | |
13758 | 0, | |
13759 | w_mode, | |
13760 | /* da */ | |
13761 | d_mode, | |
13762 | d_mode, | |
13763 | d_mode, | |
13764 | d_mode, | |
13765 | d_mode, | |
13766 | d_mode, | |
13767 | d_mode, | |
13768 | d_mode, | |
13769 | /* db */ | |
13770 | d_mode, | |
13771 | d_mode, | |
13772 | d_mode, | |
13773 | d_mode, | |
13774 | 0, | |
9306ca4a | 13775 | t_mode, |
1d9f512f | 13776 | 0, |
9306ca4a | 13777 | t_mode, |
1d9f512f AM |
13778 | /* dc */ |
13779 | q_mode, | |
13780 | q_mode, | |
13781 | q_mode, | |
13782 | q_mode, | |
13783 | q_mode, | |
13784 | q_mode, | |
13785 | q_mode, | |
13786 | q_mode, | |
13787 | /* dd */ | |
13788 | q_mode, | |
13789 | q_mode, | |
13790 | q_mode, | |
13791 | q_mode, | |
13792 | 0, | |
13793 | 0, | |
13794 | 0, | |
13795 | w_mode, | |
13796 | /* de */ | |
13797 | w_mode, | |
13798 | w_mode, | |
13799 | w_mode, | |
13800 | w_mode, | |
13801 | w_mode, | |
13802 | w_mode, | |
13803 | w_mode, | |
13804 | w_mode, | |
13805 | /* df */ | |
13806 | w_mode, | |
13807 | w_mode, | |
13808 | w_mode, | |
13809 | w_mode, | |
9306ca4a | 13810 | t_mode, |
1d9f512f | 13811 | q_mode, |
9306ca4a | 13812 | t_mode, |
1d9f512f | 13813 | q_mode |
252b5132 RH |
13814 | }; |
13815 | ||
ce518a5f L |
13816 | #define ST { OP_ST, 0 } |
13817 | #define STi { OP_STi, 0 } | |
252b5132 | 13818 | |
bf890a93 IT |
13819 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
13820 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 | |
13821 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 | |
13822 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 | |
13823 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 | |
13824 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 | |
13825 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 | |
13826 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 | |
13827 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 | |
252b5132 | 13828 | |
2da11e11 | 13829 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13830 | /* d8 */ |
13831 | { | |
bf890a93 IT |
13832 | { "fadd", { ST, STi }, 0 }, |
13833 | { "fmul", { ST, STi }, 0 }, | |
13834 | { "fcom", { STi }, 0 }, | |
13835 | { "fcomp", { STi }, 0 }, | |
13836 | { "fsub", { ST, STi }, 0 }, | |
13837 | { "fsubr", { ST, STi }, 0 }, | |
13838 | { "fdiv", { ST, STi }, 0 }, | |
13839 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13840 | }, |
13841 | /* d9 */ | |
13842 | { | |
bf890a93 IT |
13843 | { "fld", { STi }, 0 }, |
13844 | { "fxch", { STi }, 0 }, | |
252b5132 | 13845 | { FGRPd9_2 }, |
592d1631 | 13846 | { Bad_Opcode }, |
252b5132 RH |
13847 | { FGRPd9_4 }, |
13848 | { FGRPd9_5 }, | |
13849 | { FGRPd9_6 }, | |
13850 | { FGRPd9_7 }, | |
13851 | }, | |
13852 | /* da */ | |
13853 | { | |
bf890a93 IT |
13854 | { "fcmovb", { ST, STi }, 0 }, |
13855 | { "fcmove", { ST, STi }, 0 }, | |
13856 | { "fcmovbe",{ ST, STi }, 0 }, | |
13857 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13858 | { Bad_Opcode }, |
252b5132 | 13859 | { FGRPda_5 }, |
592d1631 L |
13860 | { Bad_Opcode }, |
13861 | { Bad_Opcode }, | |
252b5132 RH |
13862 | }, |
13863 | /* db */ | |
13864 | { | |
bf890a93 IT |
13865 | { "fcmovnb",{ ST, STi }, 0 }, |
13866 | { "fcmovne",{ ST, STi }, 0 }, | |
13867 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13868 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13869 | { FGRPdb_4 }, |
bf890a93 IT |
13870 | { "fucomi", { ST, STi }, 0 }, |
13871 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13872 | { Bad_Opcode }, |
252b5132 RH |
13873 | }, |
13874 | /* dc */ | |
13875 | { | |
bf890a93 IT |
13876 | { "fadd", { STi, ST }, 0 }, |
13877 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13878 | { Bad_Opcode }, |
13879 | { Bad_Opcode }, | |
bf890a93 IT |
13880 | { "fsub!M", { STi, ST }, 0 }, |
13881 | { "fsubM", { STi, ST }, 0 }, | |
13882 | { "fdiv!M", { STi, ST }, 0 }, | |
13883 | { "fdivM", { STi, ST }, 0 }, | |
252b5132 RH |
13884 | }, |
13885 | /* dd */ | |
13886 | { | |
bf890a93 | 13887 | { "ffree", { STi }, 0 }, |
592d1631 | 13888 | { Bad_Opcode }, |
bf890a93 IT |
13889 | { "fst", { STi }, 0 }, |
13890 | { "fstp", { STi }, 0 }, | |
13891 | { "fucom", { STi }, 0 }, | |
13892 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13893 | { Bad_Opcode }, |
13894 | { Bad_Opcode }, | |
252b5132 RH |
13895 | }, |
13896 | /* de */ | |
13897 | { | |
bf890a93 IT |
13898 | { "faddp", { STi, ST }, 0 }, |
13899 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13900 | { Bad_Opcode }, |
252b5132 | 13901 | { FGRPde_3 }, |
bf890a93 IT |
13902 | { "fsub!Mp", { STi, ST }, 0 }, |
13903 | { "fsubMp", { STi, ST }, 0 }, | |
13904 | { "fdiv!Mp", { STi, ST }, 0 }, | |
13905 | { "fdivMp", { STi, ST }, 0 }, | |
252b5132 RH |
13906 | }, |
13907 | /* df */ | |
13908 | { | |
bf890a93 | 13909 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13910 | { Bad_Opcode }, |
13911 | { Bad_Opcode }, | |
13912 | { Bad_Opcode }, | |
252b5132 | 13913 | { FGRPdf_4 }, |
bf890a93 IT |
13914 | { "fucomip", { ST, STi }, 0 }, |
13915 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13916 | { Bad_Opcode }, |
252b5132 RH |
13917 | }, |
13918 | }; | |
13919 | ||
252b5132 RH |
13920 | static char *fgrps[][8] = { |
13921 | /* d9_2 0 */ | |
13922 | { | |
13923 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13924 | }, | |
13925 | ||
13926 | /* d9_4 1 */ | |
13927 | { | |
13928 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13929 | }, | |
13930 | ||
13931 | /* d9_5 2 */ | |
13932 | { | |
13933 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13934 | }, | |
13935 | ||
13936 | /* d9_6 3 */ | |
13937 | { | |
13938 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13939 | }, | |
13940 | ||
13941 | /* d9_7 4 */ | |
13942 | { | |
13943 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13944 | }, | |
13945 | ||
13946 | /* da_5 5 */ | |
13947 | { | |
13948 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13949 | }, | |
13950 | ||
13951 | /* db_4 6 */ | |
13952 | { | |
309d3373 JB |
13953 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13954 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13955 | }, |
13956 | ||
13957 | /* de_3 7 */ | |
13958 | { | |
13959 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13960 | }, | |
13961 | ||
13962 | /* df_4 8 */ | |
13963 | { | |
13964 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13965 | }, | |
13966 | }; | |
13967 | ||
b6169b20 L |
13968 | static void |
13969 | swap_operand (void) | |
13970 | { | |
13971 | mnemonicendp[0] = '.'; | |
13972 | mnemonicendp[1] = 's'; | |
13973 | mnemonicendp += 2; | |
13974 | } | |
13975 | ||
b844680a L |
13976 | static void |
13977 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13978 | int sizeflag ATTRIBUTE_UNUSED) | |
13979 | { | |
13980 | /* Skip mod/rm byte. */ | |
13981 | MODRM_CHECK; | |
13982 | codep++; | |
13983 | } | |
13984 | ||
252b5132 | 13985 | static void |
26ca5450 | 13986 | dofloat (int sizeflag) |
252b5132 | 13987 | { |
2da11e11 | 13988 | const struct dis386 *dp; |
252b5132 RH |
13989 | unsigned char floatop; |
13990 | ||
13991 | floatop = codep[-1]; | |
13992 | ||
7967e09e | 13993 | if (modrm.mod != 3) |
252b5132 | 13994 | { |
7967e09e | 13995 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13996 | |
13997 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13998 | obufp = op_out[0]; |
6e50d963 | 13999 | op_ad = 2; |
1d9f512f | 14000 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
14001 | return; |
14002 | } | |
6608db57 | 14003 | /* Skip mod/rm byte. */ |
4bba6815 | 14004 | MODRM_CHECK; |
252b5132 RH |
14005 | codep++; |
14006 | ||
7967e09e | 14007 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
14008 | if (dp->name == NULL) |
14009 | { | |
7967e09e | 14010 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 14011 | |
6608db57 | 14012 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 14013 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 14014 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
14015 | } |
14016 | else | |
14017 | { | |
14018 | putop (dp->name, sizeflag); | |
14019 | ||
ce518a5f | 14020 | obufp = op_out[0]; |
6e50d963 | 14021 | op_ad = 2; |
ce518a5f L |
14022 | if (dp->op[0].rtn) |
14023 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 14024 | |
ce518a5f | 14025 | obufp = op_out[1]; |
6e50d963 | 14026 | op_ad = 1; |
ce518a5f L |
14027 | if (dp->op[1].rtn) |
14028 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
14029 | } |
14030 | } | |
14031 | ||
9ce09ba2 RM |
14032 | /* Like oappend (below), but S is a string starting with '%'. |
14033 | In Intel syntax, the '%' is elided. */ | |
14034 | static void | |
14035 | oappend_maybe_intel (const char *s) | |
14036 | { | |
14037 | oappend (s + intel_syntax); | |
14038 | } | |
14039 | ||
252b5132 | 14040 | static void |
26ca5450 | 14041 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14042 | { |
9ce09ba2 | 14043 | oappend_maybe_intel ("%st"); |
252b5132 RH |
14044 | } |
14045 | ||
252b5132 | 14046 | static void |
26ca5450 | 14047 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14048 | { |
7967e09e | 14049 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 14050 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14051 | } |
14052 | ||
6608db57 | 14053 | /* Capital letters in template are macros. */ |
6439fc28 | 14054 | static int |
d3ce72d0 | 14055 | putop (const char *in_template, int sizeflag) |
252b5132 | 14056 | { |
2da11e11 | 14057 | const char *p; |
9306ca4a | 14058 | int alt = 0; |
9d141669 | 14059 | int cond = 1; |
98b528ac L |
14060 | unsigned int l = 0, len = 1; |
14061 | char last[4]; | |
14062 | ||
14063 | #define SAVE_LAST(c) \ | |
14064 | if (l < len && l < sizeof (last)) \ | |
14065 | last[l++] = c; \ | |
14066 | else \ | |
14067 | abort (); | |
252b5132 | 14068 | |
d3ce72d0 | 14069 | for (p = in_template; *p; p++) |
252b5132 RH |
14070 | { |
14071 | switch (*p) | |
14072 | { | |
14073 | default: | |
14074 | *obufp++ = *p; | |
14075 | break; | |
98b528ac L |
14076 | case '%': |
14077 | len++; | |
14078 | break; | |
9d141669 L |
14079 | case '!': |
14080 | cond = 0; | |
14081 | break; | |
6439fc28 AM |
14082 | case '{': |
14083 | alt = 0; | |
14084 | if (intel_syntax) | |
6439fc28 AM |
14085 | { |
14086 | while (*++p != '|') | |
7c52e0e8 L |
14087 | if (*p == '}' || *p == '\0') |
14088 | abort (); | |
6439fc28 | 14089 | } |
9306ca4a JB |
14090 | /* Fall through. */ |
14091 | case 'I': | |
14092 | alt = 1; | |
14093 | continue; | |
6439fc28 AM |
14094 | case '|': |
14095 | while (*++p != '}') | |
14096 | { | |
14097 | if (*p == '\0') | |
14098 | abort (); | |
14099 | } | |
14100 | break; | |
14101 | case '}': | |
14102 | break; | |
252b5132 | 14103 | case 'A': |
db6eb5be AM |
14104 | if (intel_syntax) |
14105 | break; | |
7967e09e | 14106 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
14107 | *obufp++ = 'b'; |
14108 | break; | |
14109 | case 'B': | |
4b06377f L |
14110 | if (l == 0 && len == 1) |
14111 | { | |
14112 | case_B: | |
14113 | if (intel_syntax) | |
14114 | break; | |
14115 | if (sizeflag & SUFFIX_ALWAYS) | |
14116 | *obufp++ = 'b'; | |
14117 | } | |
14118 | else | |
14119 | { | |
14120 | if (l != 1 | |
14121 | || len != 2 | |
14122 | || last[0] != 'L') | |
14123 | { | |
14124 | SAVE_LAST (*p); | |
14125 | break; | |
14126 | } | |
14127 | ||
14128 | if (address_mode == mode_64bit | |
14129 | && !(prefixes & PREFIX_ADDR)) | |
14130 | { | |
14131 | *obufp++ = 'a'; | |
14132 | *obufp++ = 'b'; | |
14133 | *obufp++ = 's'; | |
14134 | } | |
14135 | ||
14136 | goto case_B; | |
14137 | } | |
252b5132 | 14138 | break; |
9306ca4a JB |
14139 | case 'C': |
14140 | if (intel_syntax && !alt) | |
14141 | break; | |
14142 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14143 | { | |
14144 | if (sizeflag & DFLAG) | |
14145 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14146 | else | |
14147 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14148 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14149 | } | |
14150 | break; | |
ed7841b3 JB |
14151 | case 'D': |
14152 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14153 | break; | |
161a04f6 | 14154 | USED_REX (REX_W); |
7967e09e | 14155 | if (modrm.mod == 3) |
ed7841b3 | 14156 | { |
161a04f6 | 14157 | if (rex & REX_W) |
ed7841b3 | 14158 | *obufp++ = 'q'; |
ed7841b3 | 14159 | else |
f16cd0d5 L |
14160 | { |
14161 | if (sizeflag & DFLAG) | |
14162 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14163 | else | |
14164 | *obufp++ = 'w'; | |
14165 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14166 | } | |
ed7841b3 JB |
14167 | } |
14168 | else | |
14169 | *obufp++ = 'w'; | |
14170 | break; | |
252b5132 | 14171 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14172 | if (address_mode == mode_64bit) |
c1a64871 JH |
14173 | { |
14174 | if (sizeflag & AFLAG) | |
14175 | *obufp++ = 'r'; | |
14176 | else | |
14177 | *obufp++ = 'e'; | |
14178 | } | |
14179 | else | |
14180 | if (sizeflag & AFLAG) | |
14181 | *obufp++ = 'e'; | |
3ffd33cf AM |
14182 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14183 | break; | |
14184 | case 'F': | |
db6eb5be AM |
14185 | if (intel_syntax) |
14186 | break; | |
e396998b | 14187 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14188 | { |
14189 | if (sizeflag & AFLAG) | |
cb712a9e | 14190 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14191 | else |
cb712a9e | 14192 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14193 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14194 | } | |
252b5132 | 14195 | break; |
52fd6d94 JB |
14196 | case 'G': |
14197 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14198 | break; | |
161a04f6 | 14199 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14200 | *obufp++ = 'l'; |
14201 | else | |
14202 | *obufp++ = 'w'; | |
161a04f6 | 14203 | if (!(rex & REX_W)) |
52fd6d94 JB |
14204 | used_prefixes |= (prefixes & PREFIX_DATA); |
14205 | break; | |
5dd0794d | 14206 | case 'H': |
db6eb5be AM |
14207 | if (intel_syntax) |
14208 | break; | |
5dd0794d AM |
14209 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14210 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14211 | { | |
14212 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14213 | *obufp++ = ','; | |
14214 | *obufp++ = 'p'; | |
14215 | if (prefixes & PREFIX_DS) | |
14216 | *obufp++ = 't'; | |
14217 | else | |
14218 | *obufp++ = 'n'; | |
14219 | } | |
14220 | break; | |
9306ca4a JB |
14221 | case 'J': |
14222 | if (intel_syntax) | |
14223 | break; | |
14224 | *obufp++ = 'l'; | |
14225 | break; | |
42903f7f L |
14226 | case 'K': |
14227 | USED_REX (REX_W); | |
14228 | if (rex & REX_W) | |
14229 | *obufp++ = 'q'; | |
14230 | else | |
14231 | *obufp++ = 'd'; | |
14232 | break; | |
6dd5059a | 14233 | case 'Z': |
04d824a4 JB |
14234 | if (l != 0 || len != 1) |
14235 | { | |
14236 | if (l != 1 || len != 2 || last[0] != 'X') | |
14237 | { | |
14238 | SAVE_LAST (*p); | |
14239 | break; | |
14240 | } | |
14241 | if (!need_vex || !vex.evex) | |
14242 | abort (); | |
14243 | if (intel_syntax | |
14244 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14245 | break; | |
14246 | switch (vex.length) | |
14247 | { | |
14248 | case 128: | |
14249 | *obufp++ = 'x'; | |
14250 | break; | |
14251 | case 256: | |
14252 | *obufp++ = 'y'; | |
14253 | break; | |
14254 | case 512: | |
14255 | *obufp++ = 'z'; | |
14256 | break; | |
14257 | default: | |
14258 | abort (); | |
14259 | } | |
14260 | break; | |
14261 | } | |
6dd5059a L |
14262 | if (intel_syntax) |
14263 | break; | |
14264 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14265 | { | |
14266 | *obufp++ = 'q'; | |
14267 | break; | |
14268 | } | |
14269 | /* Fall through. */ | |
98b528ac | 14270 | goto case_L; |
252b5132 | 14271 | case 'L': |
98b528ac L |
14272 | if (l != 0 || len != 1) |
14273 | { | |
14274 | SAVE_LAST (*p); | |
14275 | break; | |
14276 | } | |
14277 | case_L: | |
db6eb5be AM |
14278 | if (intel_syntax) |
14279 | break; | |
252b5132 RH |
14280 | if (sizeflag & SUFFIX_ALWAYS) |
14281 | *obufp++ = 'l'; | |
252b5132 | 14282 | break; |
9d141669 L |
14283 | case 'M': |
14284 | if (intel_mnemonic != cond) | |
14285 | *obufp++ = 'r'; | |
14286 | break; | |
252b5132 RH |
14287 | case 'N': |
14288 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14289 | *obufp++ = 'n'; | |
7d421014 ILT |
14290 | else |
14291 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14292 | break; |
52b15da3 | 14293 | case 'O': |
161a04f6 L |
14294 | USED_REX (REX_W); |
14295 | if (rex & REX_W) | |
6439fc28 | 14296 | *obufp++ = 'o'; |
a35ca55a JB |
14297 | else if (intel_syntax && (sizeflag & DFLAG)) |
14298 | *obufp++ = 'q'; | |
52b15da3 JH |
14299 | else |
14300 | *obufp++ = 'd'; | |
161a04f6 | 14301 | if (!(rex & REX_W)) |
a35ca55a | 14302 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14303 | break; |
07f5af7d L |
14304 | case '&': |
14305 | if (!intel_syntax | |
14306 | && address_mode == mode_64bit | |
14307 | && isa64 == intel64) | |
14308 | { | |
14309 | *obufp++ = 'q'; | |
14310 | break; | |
14311 | } | |
14312 | /* Fall through. */ | |
6439fc28 | 14313 | case 'T': |
d9e3625e L |
14314 | if (!intel_syntax |
14315 | && address_mode == mode_64bit | |
7bb15c6f | 14316 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14317 | { |
14318 | *obufp++ = 'q'; | |
14319 | break; | |
14320 | } | |
6608db57 | 14321 | /* Fall through. */ |
4b4c407a | 14322 | goto case_P; |
252b5132 | 14323 | case 'P': |
4b4c407a | 14324 | if (l == 0 && len == 1) |
d9e3625e | 14325 | { |
4b4c407a L |
14326 | case_P: |
14327 | if (intel_syntax) | |
d9e3625e | 14328 | { |
4b4c407a L |
14329 | if ((rex & REX_W) == 0 |
14330 | && (prefixes & PREFIX_DATA)) | |
14331 | { | |
14332 | if ((sizeflag & DFLAG) == 0) | |
14333 | *obufp++ = 'w'; | |
14334 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14335 | } | |
14336 | break; | |
14337 | } | |
14338 | if ((prefixes & PREFIX_DATA) | |
14339 | || (rex & REX_W) | |
14340 | || (sizeflag & SUFFIX_ALWAYS)) | |
14341 | { | |
14342 | USED_REX (REX_W); | |
14343 | if (rex & REX_W) | |
14344 | *obufp++ = 'q'; | |
14345 | else | |
14346 | { | |
14347 | if (sizeflag & DFLAG) | |
14348 | *obufp++ = 'l'; | |
14349 | else | |
14350 | *obufp++ = 'w'; | |
14351 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14352 | } | |
d9e3625e | 14353 | } |
d9e3625e | 14354 | } |
4b4c407a | 14355 | else |
252b5132 | 14356 | { |
4b4c407a L |
14357 | if (l != 1 || len != 2 || last[0] != 'L') |
14358 | { | |
14359 | SAVE_LAST (*p); | |
14360 | break; | |
14361 | } | |
14362 | ||
14363 | if ((prefixes & PREFIX_DATA) | |
14364 | || (rex & REX_W) | |
14365 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14366 | { |
4b4c407a L |
14367 | USED_REX (REX_W); |
14368 | if (rex & REX_W) | |
14369 | *obufp++ = 'q'; | |
14370 | else | |
14371 | { | |
14372 | if (sizeflag & DFLAG) | |
14373 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14374 | else | |
14375 | *obufp++ = 'w'; | |
14376 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14377 | } | |
52b15da3 | 14378 | } |
252b5132 RH |
14379 | } |
14380 | break; | |
6439fc28 | 14381 | case 'U': |
db6eb5be AM |
14382 | if (intel_syntax) |
14383 | break; | |
7bb15c6f | 14384 | if (address_mode == mode_64bit |
6c067bbb | 14385 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14386 | { |
7967e09e | 14387 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14388 | *obufp++ = 'q'; |
6439fc28 AM |
14389 | break; |
14390 | } | |
6608db57 | 14391 | /* Fall through. */ |
98b528ac | 14392 | goto case_Q; |
252b5132 | 14393 | case 'Q': |
98b528ac | 14394 | if (l == 0 && len == 1) |
252b5132 | 14395 | { |
98b528ac L |
14396 | case_Q: |
14397 | if (intel_syntax && !alt) | |
14398 | break; | |
14399 | USED_REX (REX_W); | |
14400 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14401 | { |
98b528ac L |
14402 | if (rex & REX_W) |
14403 | *obufp++ = 'q'; | |
52b15da3 | 14404 | else |
98b528ac L |
14405 | { |
14406 | if (sizeflag & DFLAG) | |
14407 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14408 | else | |
14409 | *obufp++ = 'w'; | |
f16cd0d5 | 14410 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14411 | } |
52b15da3 | 14412 | } |
98b528ac L |
14413 | } |
14414 | else | |
14415 | { | |
14416 | if (l != 1 || len != 2 || last[0] != 'L') | |
14417 | { | |
14418 | SAVE_LAST (*p); | |
14419 | break; | |
14420 | } | |
14421 | if (intel_syntax | |
14422 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14423 | break; | |
14424 | if ((rex & REX_W)) | |
14425 | { | |
14426 | USED_REX (REX_W); | |
14427 | *obufp++ = 'q'; | |
14428 | } | |
14429 | else | |
14430 | *obufp++ = 'l'; | |
252b5132 RH |
14431 | } |
14432 | break; | |
14433 | case 'R': | |
161a04f6 L |
14434 | USED_REX (REX_W); |
14435 | if (rex & REX_W) | |
a35ca55a JB |
14436 | *obufp++ = 'q'; |
14437 | else if (sizeflag & DFLAG) | |
c608c12e | 14438 | { |
a35ca55a | 14439 | if (intel_syntax) |
c608c12e | 14440 | *obufp++ = 'd'; |
c608c12e | 14441 | else |
a35ca55a | 14442 | *obufp++ = 'l'; |
c608c12e | 14443 | } |
252b5132 | 14444 | else |
a35ca55a JB |
14445 | *obufp++ = 'w'; |
14446 | if (intel_syntax && !p[1] | |
161a04f6 | 14447 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14448 | *obufp++ = 'e'; |
161a04f6 | 14449 | if (!(rex & REX_W)) |
52b15da3 | 14450 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14451 | break; |
1a114b12 | 14452 | case 'V': |
4b06377f | 14453 | if (l == 0 && len == 1) |
1a114b12 | 14454 | { |
4b06377f L |
14455 | if (intel_syntax) |
14456 | break; | |
7bb15c6f | 14457 | if (address_mode == mode_64bit |
6c067bbb | 14458 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14459 | { |
14460 | if (sizeflag & SUFFIX_ALWAYS) | |
14461 | *obufp++ = 'q'; | |
14462 | break; | |
14463 | } | |
14464 | } | |
14465 | else | |
14466 | { | |
14467 | if (l != 1 | |
14468 | || len != 2 | |
14469 | || last[0] != 'L') | |
14470 | { | |
14471 | SAVE_LAST (*p); | |
14472 | break; | |
14473 | } | |
14474 | ||
14475 | if (rex & REX_W) | |
14476 | { | |
14477 | *obufp++ = 'a'; | |
14478 | *obufp++ = 'b'; | |
14479 | *obufp++ = 's'; | |
14480 | } | |
1a114b12 JB |
14481 | } |
14482 | /* Fall through. */ | |
4b06377f | 14483 | goto case_S; |
252b5132 | 14484 | case 'S': |
4b06377f | 14485 | if (l == 0 && len == 1) |
252b5132 | 14486 | { |
4b06377f L |
14487 | case_S: |
14488 | if (intel_syntax) | |
14489 | break; | |
14490 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14491 | { |
4b06377f L |
14492 | if (rex & REX_W) |
14493 | *obufp++ = 'q'; | |
52b15da3 | 14494 | else |
4b06377f L |
14495 | { |
14496 | if (sizeflag & DFLAG) | |
14497 | *obufp++ = 'l'; | |
14498 | else | |
14499 | *obufp++ = 'w'; | |
14500 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14501 | } | |
14502 | } | |
14503 | } | |
14504 | else | |
14505 | { | |
14506 | if (l != 1 | |
14507 | || len != 2 | |
14508 | || last[0] != 'L') | |
14509 | { | |
14510 | SAVE_LAST (*p); | |
14511 | break; | |
52b15da3 | 14512 | } |
4b06377f L |
14513 | |
14514 | if (address_mode == mode_64bit | |
14515 | && !(prefixes & PREFIX_ADDR)) | |
14516 | { | |
14517 | *obufp++ = 'a'; | |
14518 | *obufp++ = 'b'; | |
14519 | *obufp++ = 's'; | |
14520 | } | |
14521 | ||
14522 | goto case_S; | |
252b5132 | 14523 | } |
252b5132 | 14524 | break; |
041bd2e0 | 14525 | case 'X': |
c0f3af97 L |
14526 | if (l != 0 || len != 1) |
14527 | { | |
14528 | SAVE_LAST (*p); | |
14529 | break; | |
14530 | } | |
14531 | if (need_vex && vex.prefix) | |
14532 | { | |
14533 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14534 | *obufp++ = 'd'; | |
14535 | else | |
14536 | *obufp++ = 's'; | |
14537 | } | |
041bd2e0 | 14538 | else |
f16cd0d5 L |
14539 | { |
14540 | if (prefixes & PREFIX_DATA) | |
14541 | *obufp++ = 'd'; | |
14542 | else | |
14543 | *obufp++ = 's'; | |
14544 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14545 | } | |
041bd2e0 | 14546 | break; |
76f227a5 | 14547 | case 'Y': |
c0f3af97 | 14548 | if (l == 0 && len == 1) |
76f227a5 | 14549 | { |
c0f3af97 L |
14550 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14551 | break; | |
14552 | if (rex & REX_W) | |
14553 | { | |
14554 | USED_REX (REX_W); | |
14555 | *obufp++ = 'q'; | |
14556 | } | |
14557 | break; | |
14558 | } | |
14559 | else | |
14560 | { | |
14561 | if (l != 1 || len != 2 || last[0] != 'X') | |
14562 | { | |
14563 | SAVE_LAST (*p); | |
14564 | break; | |
14565 | } | |
14566 | if (!need_vex) | |
14567 | abort (); | |
14568 | if (intel_syntax | |
04d824a4 | 14569 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14570 | break; |
14571 | switch (vex.length) | |
14572 | { | |
14573 | case 128: | |
14574 | *obufp++ = 'x'; | |
14575 | break; | |
14576 | case 256: | |
14577 | *obufp++ = 'y'; | |
14578 | break; | |
04d824a4 JB |
14579 | case 512: |
14580 | if (!vex.evex) | |
c0f3af97 | 14581 | default: |
04d824a4 | 14582 | abort (); |
c0f3af97 | 14583 | } |
76f227a5 JH |
14584 | } |
14585 | break; | |
252b5132 | 14586 | case 'W': |
0bfee649 | 14587 | if (l == 0 && len == 1) |
a35ca55a | 14588 | { |
0bfee649 L |
14589 | /* operand size flag for cwtl, cbtw */ |
14590 | USED_REX (REX_W); | |
14591 | if (rex & REX_W) | |
14592 | { | |
14593 | if (intel_syntax) | |
14594 | *obufp++ = 'd'; | |
14595 | else | |
14596 | *obufp++ = 'l'; | |
14597 | } | |
14598 | else if (sizeflag & DFLAG) | |
14599 | *obufp++ = 'w'; | |
a35ca55a | 14600 | else |
0bfee649 L |
14601 | *obufp++ = 'b'; |
14602 | if (!(rex & REX_W)) | |
14603 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14604 | } |
252b5132 | 14605 | else |
0bfee649 | 14606 | { |
6c30d220 L |
14607 | if (l != 1 |
14608 | || len != 2 | |
14609 | || (last[0] != 'X' | |
14610 | && last[0] != 'L')) | |
0bfee649 L |
14611 | { |
14612 | SAVE_LAST (*p); | |
14613 | break; | |
14614 | } | |
14615 | if (!need_vex) | |
14616 | abort (); | |
6c30d220 L |
14617 | if (last[0] == 'X') |
14618 | *obufp++ = vex.w ? 'd': 's'; | |
14619 | else | |
14620 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14621 | } |
252b5132 | 14622 | break; |
a72d2af2 L |
14623 | case '^': |
14624 | if (intel_syntax) | |
14625 | break; | |
14626 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14627 | { | |
14628 | if (sizeflag & DFLAG) | |
14629 | *obufp++ = 'l'; | |
14630 | else | |
14631 | *obufp++ = 'w'; | |
14632 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14633 | } | |
14634 | break; | |
5db04b09 L |
14635 | case '@': |
14636 | if (intel_syntax) | |
14637 | break; | |
14638 | if (address_mode == mode_64bit | |
14639 | && (isa64 == intel64 | |
14640 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14641 | *obufp++ = 'q'; | |
14642 | else if ((prefixes & PREFIX_DATA)) | |
14643 | { | |
14644 | if (!(sizeflag & DFLAG)) | |
14645 | *obufp++ = 'w'; | |
14646 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14647 | } | |
14648 | break; | |
252b5132 | 14649 | } |
9306ca4a | 14650 | alt = 0; |
252b5132 RH |
14651 | } |
14652 | *obufp = 0; | |
ea397f5b | 14653 | mnemonicendp = obufp; |
6439fc28 | 14654 | return 0; |
252b5132 RH |
14655 | } |
14656 | ||
14657 | static void | |
26ca5450 | 14658 | oappend (const char *s) |
252b5132 | 14659 | { |
ea397f5b | 14660 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14661 | } |
14662 | ||
14663 | static void | |
26ca5450 | 14664 | append_seg (void) |
252b5132 | 14665 | { |
285ca992 L |
14666 | /* Only print the active segment register. */ |
14667 | if (!active_seg_prefix) | |
14668 | return; | |
14669 | ||
14670 | used_prefixes |= active_seg_prefix; | |
14671 | switch (active_seg_prefix) | |
7d421014 | 14672 | { |
285ca992 | 14673 | case PREFIX_CS: |
9ce09ba2 | 14674 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14675 | break; |
14676 | case PREFIX_DS: | |
9ce09ba2 | 14677 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14678 | break; |
14679 | case PREFIX_SS: | |
9ce09ba2 | 14680 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14681 | break; |
14682 | case PREFIX_ES: | |
9ce09ba2 | 14683 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14684 | break; |
14685 | case PREFIX_FS: | |
9ce09ba2 | 14686 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14687 | break; |
14688 | case PREFIX_GS: | |
9ce09ba2 | 14689 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14690 | break; |
14691 | default: | |
14692 | break; | |
7d421014 | 14693 | } |
252b5132 RH |
14694 | } |
14695 | ||
14696 | static void | |
26ca5450 | 14697 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14698 | { |
14699 | if (!intel_syntax) | |
14700 | oappend ("*"); | |
14701 | OP_E (bytemode, sizeflag); | |
14702 | } | |
14703 | ||
52b15da3 | 14704 | static void |
26ca5450 | 14705 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14706 | { |
cb712a9e | 14707 | if (address_mode == mode_64bit) |
52b15da3 JH |
14708 | { |
14709 | if (hex) | |
14710 | { | |
14711 | char tmp[30]; | |
14712 | int i; | |
14713 | buf[0] = '0'; | |
14714 | buf[1] = 'x'; | |
14715 | sprintf_vma (tmp, disp); | |
6608db57 | 14716 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14717 | strcpy (buf + 2, tmp + i); |
14718 | } | |
14719 | else | |
14720 | { | |
14721 | bfd_signed_vma v = disp; | |
14722 | char tmp[30]; | |
14723 | int i; | |
14724 | if (v < 0) | |
14725 | { | |
14726 | *(buf++) = '-'; | |
14727 | v = -disp; | |
6608db57 | 14728 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14729 | if (v < 0) |
14730 | { | |
14731 | strcpy (buf, "9223372036854775808"); | |
14732 | return; | |
14733 | } | |
14734 | } | |
14735 | if (!v) | |
14736 | { | |
14737 | strcpy (buf, "0"); | |
14738 | return; | |
14739 | } | |
14740 | ||
14741 | i = 0; | |
14742 | tmp[29] = 0; | |
14743 | while (v) | |
14744 | { | |
6608db57 | 14745 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14746 | v /= 10; |
14747 | i++; | |
14748 | } | |
14749 | strcpy (buf, tmp + 29 - i); | |
14750 | } | |
14751 | } | |
14752 | else | |
14753 | { | |
14754 | if (hex) | |
14755 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14756 | else | |
14757 | sprintf (buf, "%d", (int) disp); | |
14758 | } | |
14759 | } | |
14760 | ||
5d669648 L |
14761 | /* Put DISP in BUF as signed hex number. */ |
14762 | ||
14763 | static void | |
14764 | print_displacement (char *buf, bfd_vma disp) | |
14765 | { | |
14766 | bfd_signed_vma val = disp; | |
14767 | char tmp[30]; | |
14768 | int i, j = 0; | |
14769 | ||
14770 | if (val < 0) | |
14771 | { | |
14772 | buf[j++] = '-'; | |
14773 | val = -disp; | |
14774 | ||
14775 | /* Check for possible overflow. */ | |
14776 | if (val < 0) | |
14777 | { | |
14778 | switch (address_mode) | |
14779 | { | |
14780 | case mode_64bit: | |
14781 | strcpy (buf + j, "0x8000000000000000"); | |
14782 | break; | |
14783 | case mode_32bit: | |
14784 | strcpy (buf + j, "0x80000000"); | |
14785 | break; | |
14786 | case mode_16bit: | |
14787 | strcpy (buf + j, "0x8000"); | |
14788 | break; | |
14789 | } | |
14790 | return; | |
14791 | } | |
14792 | } | |
14793 | ||
14794 | buf[j++] = '0'; | |
14795 | buf[j++] = 'x'; | |
14796 | ||
0af1713e | 14797 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14798 | for (i = 0; tmp[i] == '0'; i++) |
14799 | continue; | |
14800 | if (tmp[i] == '\0') | |
14801 | i--; | |
14802 | strcpy (buf + j, tmp + i); | |
14803 | } | |
14804 | ||
3f31e633 JB |
14805 | static void |
14806 | intel_operand_size (int bytemode, int sizeflag) | |
14807 | { | |
43234a1e L |
14808 | if (vex.evex |
14809 | && vex.b | |
14810 | && (bytemode == x_mode | |
14811 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14812 | { | |
14813 | if (vex.w) | |
14814 | oappend ("QWORD PTR "); | |
14815 | else | |
14816 | oappend ("DWORD PTR "); | |
14817 | return; | |
14818 | } | |
3f31e633 JB |
14819 | switch (bytemode) |
14820 | { | |
14821 | case b_mode: | |
b6169b20 | 14822 | case b_swap_mode: |
42903f7f | 14823 | case dqb_mode: |
1ba585e8 | 14824 | case db_mode: |
3f31e633 JB |
14825 | oappend ("BYTE PTR "); |
14826 | break; | |
14827 | case w_mode: | |
1ba585e8 | 14828 | case dw_mode: |
3f31e633 | 14829 | case dqw_mode: |
1ba585e8 | 14830 | case dqw_swap_mode: |
3f31e633 JB |
14831 | oappend ("WORD PTR "); |
14832 | break; | |
07f5af7d L |
14833 | case indir_v_mode: |
14834 | if (address_mode == mode_64bit && isa64 == intel64) | |
14835 | { | |
14836 | oappend ("QWORD PTR "); | |
14837 | break; | |
14838 | } | |
1a114b12 | 14839 | case stack_v_mode: |
7bb15c6f | 14840 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14841 | { |
14842 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14843 | break; |
14844 | } | |
14845 | /* FALLTHRU */ | |
14846 | case v_mode: | |
b6169b20 | 14847 | case v_swap_mode: |
3f31e633 | 14848 | case dq_mode: |
161a04f6 L |
14849 | USED_REX (REX_W); |
14850 | if (rex & REX_W) | |
3f31e633 | 14851 | oappend ("QWORD PTR "); |
3f31e633 | 14852 | else |
f16cd0d5 L |
14853 | { |
14854 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14855 | oappend ("DWORD PTR "); | |
14856 | else | |
14857 | oappend ("WORD PTR "); | |
14858 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14859 | } | |
3f31e633 | 14860 | break; |
52fd6d94 | 14861 | case z_mode: |
161a04f6 | 14862 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14863 | *obufp++ = 'D'; |
14864 | oappend ("WORD PTR "); | |
161a04f6 | 14865 | if (!(rex & REX_W)) |
52fd6d94 JB |
14866 | used_prefixes |= (prefixes & PREFIX_DATA); |
14867 | break; | |
34b772a6 JB |
14868 | case a_mode: |
14869 | if (sizeflag & DFLAG) | |
14870 | oappend ("QWORD PTR "); | |
14871 | else | |
14872 | oappend ("DWORD PTR "); | |
14873 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14874 | break; | |
3f31e633 | 14875 | case d_mode: |
539f890d L |
14876 | case d_scalar_mode: |
14877 | case d_scalar_swap_mode: | |
fa99fab2 | 14878 | case d_swap_mode: |
42903f7f | 14879 | case dqd_mode: |
3f31e633 JB |
14880 | oappend ("DWORD PTR "); |
14881 | break; | |
14882 | case q_mode: | |
539f890d L |
14883 | case q_scalar_mode: |
14884 | case q_scalar_swap_mode: | |
b6169b20 | 14885 | case q_swap_mode: |
3f31e633 JB |
14886 | oappend ("QWORD PTR "); |
14887 | break; | |
14888 | case m_mode: | |
cb712a9e | 14889 | if (address_mode == mode_64bit) |
3f31e633 JB |
14890 | oappend ("QWORD PTR "); |
14891 | else | |
14892 | oappend ("DWORD PTR "); | |
14893 | break; | |
14894 | case f_mode: | |
14895 | if (sizeflag & DFLAG) | |
14896 | oappend ("FWORD PTR "); | |
14897 | else | |
14898 | oappend ("DWORD PTR "); | |
14899 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14900 | break; | |
14901 | case t_mode: | |
14902 | oappend ("TBYTE PTR "); | |
14903 | break; | |
14904 | case x_mode: | |
b6169b20 | 14905 | case x_swap_mode: |
43234a1e L |
14906 | case evex_x_gscat_mode: |
14907 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14908 | if (need_vex) |
14909 | { | |
14910 | switch (vex.length) | |
14911 | { | |
14912 | case 128: | |
14913 | oappend ("XMMWORD PTR "); | |
14914 | break; | |
14915 | case 256: | |
14916 | oappend ("YMMWORD PTR "); | |
14917 | break; | |
43234a1e L |
14918 | case 512: |
14919 | oappend ("ZMMWORD PTR "); | |
14920 | break; | |
c0f3af97 L |
14921 | default: |
14922 | abort (); | |
14923 | } | |
14924 | } | |
14925 | else | |
14926 | oappend ("XMMWORD PTR "); | |
14927 | break; | |
14928 | case xmm_mode: | |
3f31e633 JB |
14929 | oappend ("XMMWORD PTR "); |
14930 | break; | |
43234a1e L |
14931 | case ymm_mode: |
14932 | oappend ("YMMWORD PTR "); | |
14933 | break; | |
c0f3af97 | 14934 | case xmmq_mode: |
43234a1e | 14935 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14936 | if (!need_vex) |
14937 | abort (); | |
14938 | ||
14939 | switch (vex.length) | |
14940 | { | |
14941 | case 128: | |
14942 | oappend ("QWORD PTR "); | |
14943 | break; | |
14944 | case 256: | |
14945 | oappend ("XMMWORD PTR "); | |
14946 | break; | |
43234a1e L |
14947 | case 512: |
14948 | oappend ("YMMWORD PTR "); | |
14949 | break; | |
c0f3af97 L |
14950 | default: |
14951 | abort (); | |
14952 | } | |
14953 | break; | |
6c30d220 L |
14954 | case xmm_mb_mode: |
14955 | if (!need_vex) | |
14956 | abort (); | |
14957 | ||
14958 | switch (vex.length) | |
14959 | { | |
14960 | case 128: | |
14961 | case 256: | |
43234a1e | 14962 | case 512: |
6c30d220 L |
14963 | oappend ("BYTE PTR "); |
14964 | break; | |
14965 | default: | |
14966 | abort (); | |
14967 | } | |
14968 | break; | |
14969 | case xmm_mw_mode: | |
14970 | if (!need_vex) | |
14971 | abort (); | |
14972 | ||
14973 | switch (vex.length) | |
14974 | { | |
14975 | case 128: | |
14976 | case 256: | |
43234a1e | 14977 | case 512: |
6c30d220 L |
14978 | oappend ("WORD PTR "); |
14979 | break; | |
14980 | default: | |
14981 | abort (); | |
14982 | } | |
14983 | break; | |
14984 | case xmm_md_mode: | |
14985 | if (!need_vex) | |
14986 | abort (); | |
14987 | ||
14988 | switch (vex.length) | |
14989 | { | |
14990 | case 128: | |
14991 | case 256: | |
43234a1e | 14992 | case 512: |
6c30d220 L |
14993 | oappend ("DWORD PTR "); |
14994 | break; | |
14995 | default: | |
14996 | abort (); | |
14997 | } | |
14998 | break; | |
14999 | case xmm_mq_mode: | |
15000 | if (!need_vex) | |
15001 | abort (); | |
15002 | ||
15003 | switch (vex.length) | |
15004 | { | |
15005 | case 128: | |
15006 | case 256: | |
43234a1e | 15007 | case 512: |
6c30d220 L |
15008 | oappend ("QWORD PTR "); |
15009 | break; | |
15010 | default: | |
15011 | abort (); | |
15012 | } | |
15013 | break; | |
15014 | case xmmdw_mode: | |
15015 | if (!need_vex) | |
15016 | abort (); | |
15017 | ||
15018 | switch (vex.length) | |
15019 | { | |
15020 | case 128: | |
15021 | oappend ("WORD PTR "); | |
15022 | break; | |
15023 | case 256: | |
15024 | oappend ("DWORD PTR "); | |
15025 | break; | |
43234a1e L |
15026 | case 512: |
15027 | oappend ("QWORD PTR "); | |
15028 | break; | |
6c30d220 L |
15029 | default: |
15030 | abort (); | |
15031 | } | |
15032 | break; | |
15033 | case xmmqd_mode: | |
15034 | if (!need_vex) | |
15035 | abort (); | |
15036 | ||
15037 | switch (vex.length) | |
15038 | { | |
15039 | case 128: | |
15040 | oappend ("DWORD PTR "); | |
15041 | break; | |
15042 | case 256: | |
15043 | oappend ("QWORD PTR "); | |
15044 | break; | |
43234a1e L |
15045 | case 512: |
15046 | oappend ("XMMWORD PTR "); | |
15047 | break; | |
6c30d220 L |
15048 | default: |
15049 | abort (); | |
15050 | } | |
15051 | break; | |
c0f3af97 L |
15052 | case ymmq_mode: |
15053 | if (!need_vex) | |
15054 | abort (); | |
15055 | ||
15056 | switch (vex.length) | |
15057 | { | |
15058 | case 128: | |
15059 | oappend ("QWORD PTR "); | |
15060 | break; | |
15061 | case 256: | |
15062 | oappend ("YMMWORD PTR "); | |
15063 | break; | |
43234a1e L |
15064 | case 512: |
15065 | oappend ("ZMMWORD PTR "); | |
15066 | break; | |
c0f3af97 L |
15067 | default: |
15068 | abort (); | |
15069 | } | |
15070 | break; | |
6c30d220 L |
15071 | case ymmxmm_mode: |
15072 | if (!need_vex) | |
15073 | abort (); | |
15074 | ||
15075 | switch (vex.length) | |
15076 | { | |
15077 | case 128: | |
15078 | case 256: | |
15079 | oappend ("XMMWORD PTR "); | |
15080 | break; | |
15081 | default: | |
15082 | abort (); | |
15083 | } | |
15084 | break; | |
fb9c77c7 L |
15085 | case o_mode: |
15086 | oappend ("OWORD PTR "); | |
15087 | break; | |
43234a1e | 15088 | case xmm_mdq_mode: |
0bfee649 | 15089 | case vex_w_dq_mode: |
1c480963 | 15090 | case vex_scalar_w_dq_mode: |
0bfee649 L |
15091 | if (!need_vex) |
15092 | abort (); | |
15093 | ||
15094 | if (vex.w) | |
15095 | oappend ("QWORD PTR "); | |
15096 | else | |
15097 | oappend ("DWORD PTR "); | |
15098 | break; | |
43234a1e L |
15099 | case vex_vsib_d_w_dq_mode: |
15100 | case vex_vsib_q_w_dq_mode: | |
15101 | if (!need_vex) | |
15102 | abort (); | |
15103 | ||
15104 | if (!vex.evex) | |
15105 | { | |
15106 | if (vex.w) | |
15107 | oappend ("QWORD PTR "); | |
15108 | else | |
15109 | oappend ("DWORD PTR "); | |
15110 | } | |
15111 | else | |
15112 | { | |
b28d1bda IT |
15113 | switch (vex.length) |
15114 | { | |
15115 | case 128: | |
15116 | oappend ("XMMWORD PTR "); | |
15117 | break; | |
15118 | case 256: | |
15119 | oappend ("YMMWORD PTR "); | |
15120 | break; | |
15121 | case 512: | |
15122 | oappend ("ZMMWORD PTR "); | |
15123 | break; | |
15124 | default: | |
15125 | abort (); | |
15126 | } | |
43234a1e L |
15127 | } |
15128 | break; | |
5fc35d96 IT |
15129 | case vex_vsib_q_w_d_mode: |
15130 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 15131 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
15132 | abort (); |
15133 | ||
b28d1bda IT |
15134 | switch (vex.length) |
15135 | { | |
15136 | case 128: | |
15137 | oappend ("QWORD PTR "); | |
15138 | break; | |
15139 | case 256: | |
15140 | oappend ("XMMWORD PTR "); | |
15141 | break; | |
15142 | case 512: | |
15143 | oappend ("YMMWORD PTR "); | |
15144 | break; | |
15145 | default: | |
15146 | abort (); | |
15147 | } | |
5fc35d96 IT |
15148 | |
15149 | break; | |
1ba585e8 IT |
15150 | case mask_bd_mode: |
15151 | if (!need_vex || vex.length != 128) | |
15152 | abort (); | |
15153 | if (vex.w) | |
15154 | oappend ("DWORD PTR "); | |
15155 | else | |
15156 | oappend ("BYTE PTR "); | |
15157 | break; | |
43234a1e L |
15158 | case mask_mode: |
15159 | if (!need_vex) | |
15160 | abort (); | |
1ba585e8 IT |
15161 | if (vex.w) |
15162 | oappend ("QWORD PTR "); | |
15163 | else | |
15164 | oappend ("WORD PTR "); | |
43234a1e | 15165 | break; |
6c75cc62 | 15166 | case v_bnd_mode: |
3f31e633 JB |
15167 | default: |
15168 | break; | |
15169 | } | |
15170 | } | |
15171 | ||
252b5132 | 15172 | static void |
c0f3af97 | 15173 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15174 | { |
c0f3af97 L |
15175 | int reg = modrm.rm; |
15176 | const char **names; | |
252b5132 | 15177 | |
c0f3af97 L |
15178 | USED_REX (REX_B); |
15179 | if ((rex & REX_B)) | |
15180 | reg += 8; | |
252b5132 | 15181 | |
b6169b20 | 15182 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 IT |
15183 | && (bytemode == b_swap_mode |
15184 | || bytemode == v_swap_mode | |
15185 | || bytemode == dqw_swap_mode)) | |
b6169b20 L |
15186 | swap_operand (); |
15187 | ||
c0f3af97 | 15188 | switch (bytemode) |
252b5132 | 15189 | { |
c0f3af97 | 15190 | case b_mode: |
b6169b20 | 15191 | case b_swap_mode: |
c0f3af97 L |
15192 | USED_REX (0); |
15193 | if (rex) | |
15194 | names = names8rex; | |
15195 | else | |
15196 | names = names8; | |
15197 | break; | |
15198 | case w_mode: | |
15199 | names = names16; | |
15200 | break; | |
15201 | case d_mode: | |
1ba585e8 IT |
15202 | case dw_mode: |
15203 | case db_mode: | |
c0f3af97 L |
15204 | names = names32; |
15205 | break; | |
15206 | case q_mode: | |
15207 | names = names64; | |
15208 | break; | |
15209 | case m_mode: | |
6c75cc62 | 15210 | case v_bnd_mode: |
c0f3af97 L |
15211 | names = address_mode == mode_64bit ? names64 : names32; |
15212 | break; | |
7e8b059b L |
15213 | case bnd_mode: |
15214 | names = names_bnd; | |
15215 | break; | |
07f5af7d L |
15216 | case indir_v_mode: |
15217 | if (address_mode == mode_64bit && isa64 == intel64) | |
15218 | { | |
15219 | names = names64; | |
15220 | break; | |
15221 | } | |
c0f3af97 | 15222 | case stack_v_mode: |
7bb15c6f | 15223 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15224 | { |
c0f3af97 | 15225 | names = names64; |
252b5132 | 15226 | break; |
252b5132 | 15227 | } |
c0f3af97 L |
15228 | bytemode = v_mode; |
15229 | /* FALLTHRU */ | |
15230 | case v_mode: | |
b6169b20 | 15231 | case v_swap_mode: |
c0f3af97 L |
15232 | case dq_mode: |
15233 | case dqb_mode: | |
15234 | case dqd_mode: | |
15235 | case dqw_mode: | |
1ba585e8 | 15236 | case dqw_swap_mode: |
c0f3af97 L |
15237 | USED_REX (REX_W); |
15238 | if (rex & REX_W) | |
15239 | names = names64; | |
c0f3af97 | 15240 | else |
f16cd0d5 | 15241 | { |
7bb15c6f | 15242 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15243 | || (bytemode != v_mode |
15244 | && bytemode != v_swap_mode)) | |
15245 | names = names32; | |
15246 | else | |
15247 | names = names16; | |
15248 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15249 | } | |
c0f3af97 | 15250 | break; |
1ba585e8 | 15251 | case mask_bd_mode: |
43234a1e L |
15252 | case mask_mode: |
15253 | names = names_mask; | |
15254 | break; | |
c0f3af97 L |
15255 | case 0: |
15256 | return; | |
15257 | default: | |
15258 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15259 | return; |
15260 | } | |
c0f3af97 L |
15261 | oappend (names[reg]); |
15262 | } | |
15263 | ||
15264 | static void | |
c1e679ec | 15265 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15266 | { |
15267 | bfd_vma disp = 0; | |
15268 | int add = (rex & REX_B) ? 8 : 0; | |
15269 | int riprel = 0; | |
43234a1e L |
15270 | int shift; |
15271 | ||
15272 | if (vex.evex) | |
15273 | { | |
15274 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15275 | if (vex.b | |
15276 | && bytemode != x_mode | |
90a915bf | 15277 | && bytemode != xmmq_mode |
43234a1e L |
15278 | && bytemode != evex_half_bcst_xmmq_mode) |
15279 | { | |
15280 | BadOp (); | |
15281 | return; | |
15282 | } | |
15283 | switch (bytemode) | |
15284 | { | |
1ba585e8 IT |
15285 | case dqw_mode: |
15286 | case dw_mode: | |
15287 | case dqw_swap_mode: | |
15288 | shift = 1; | |
15289 | break; | |
15290 | case dqb_mode: | |
15291 | case db_mode: | |
15292 | shift = 0; | |
15293 | break; | |
43234a1e | 15294 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15295 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15296 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15297 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15298 | case evex_x_gscat_mode: |
15299 | case xmm_mdq_mode: | |
15300 | shift = vex.w ? 3 : 2; | |
15301 | break; | |
43234a1e L |
15302 | case x_mode: |
15303 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15304 | case xmmq_mode: |
43234a1e L |
15305 | if (vex.b) |
15306 | { | |
15307 | shift = vex.w ? 3 : 2; | |
15308 | break; | |
15309 | } | |
15310 | /* Fall through if vex.b == 0. */ | |
15311 | case xmmqd_mode: | |
15312 | case xmmdw_mode: | |
43234a1e L |
15313 | case ymmq_mode: |
15314 | case evex_x_nobcst_mode: | |
15315 | case x_swap_mode: | |
15316 | switch (vex.length) | |
15317 | { | |
15318 | case 128: | |
15319 | shift = 4; | |
15320 | break; | |
15321 | case 256: | |
15322 | shift = 5; | |
15323 | break; | |
15324 | case 512: | |
15325 | shift = 6; | |
15326 | break; | |
15327 | default: | |
15328 | abort (); | |
15329 | } | |
15330 | break; | |
15331 | case ymm_mode: | |
15332 | shift = 5; | |
15333 | break; | |
15334 | case xmm_mode: | |
15335 | shift = 4; | |
15336 | break; | |
15337 | case xmm_mq_mode: | |
15338 | case q_mode: | |
15339 | case q_scalar_mode: | |
15340 | case q_swap_mode: | |
15341 | case q_scalar_swap_mode: | |
15342 | shift = 3; | |
15343 | break; | |
15344 | case dqd_mode: | |
15345 | case xmm_md_mode: | |
15346 | case d_mode: | |
15347 | case d_scalar_mode: | |
15348 | case d_swap_mode: | |
15349 | case d_scalar_swap_mode: | |
15350 | shift = 2; | |
15351 | break; | |
15352 | case xmm_mw_mode: | |
15353 | shift = 1; | |
15354 | break; | |
15355 | case xmm_mb_mode: | |
15356 | shift = 0; | |
15357 | break; | |
15358 | default: | |
15359 | abort (); | |
15360 | } | |
15361 | /* Make necessary corrections to shift for modes that need it. | |
15362 | For these modes we currently have shift 4, 5 or 6 depending on | |
15363 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15364 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15365 | xmmq_mode). In case of broadcast enabled the corrections | |
15366 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15367 | if (!vex.b |
15368 | && (bytemode == xmmq_mode | |
15369 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15370 | shift -= 1; |
15371 | else if (bytemode == xmmqd_mode) | |
15372 | shift -= 2; | |
15373 | else if (bytemode == xmmdw_mode) | |
15374 | shift -= 3; | |
b28d1bda IT |
15375 | else if (bytemode == ymmq_mode && vex.length == 128) |
15376 | shift -= 1; | |
43234a1e L |
15377 | } |
15378 | else | |
15379 | shift = 0; | |
252b5132 | 15380 | |
c0f3af97 | 15381 | USED_REX (REX_B); |
3f31e633 JB |
15382 | if (intel_syntax) |
15383 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15384 | append_seg (); |
15385 | ||
5d669648 | 15386 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15387 | { |
5d669648 L |
15388 | /* 32/64 bit address mode */ |
15389 | int havedisp; | |
252b5132 RH |
15390 | int havesib; |
15391 | int havebase; | |
0f7da397 | 15392 | int haveindex; |
20afcfb7 | 15393 | int needindex; |
82c18208 | 15394 | int base, rbase; |
91d6fa6a | 15395 | int vindex = 0; |
252b5132 | 15396 | int scale = 0; |
7e8b059b L |
15397 | int addr32flag = !((sizeflag & AFLAG) |
15398 | || bytemode == v_bnd_mode | |
15399 | || bytemode == bnd_mode); | |
6c30d220 L |
15400 | const char **indexes64 = names64; |
15401 | const char **indexes32 = names32; | |
252b5132 RH |
15402 | |
15403 | havesib = 0; | |
15404 | havebase = 1; | |
0f7da397 | 15405 | haveindex = 0; |
7967e09e | 15406 | base = modrm.rm; |
252b5132 RH |
15407 | |
15408 | if (base == 4) | |
15409 | { | |
15410 | havesib = 1; | |
dfc8cf43 | 15411 | vindex = sib.index; |
161a04f6 L |
15412 | USED_REX (REX_X); |
15413 | if (rex & REX_X) | |
91d6fa6a | 15414 | vindex += 8; |
6c30d220 L |
15415 | switch (bytemode) |
15416 | { | |
15417 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15418 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15419 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15420 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15421 | if (!need_vex) |
15422 | abort (); | |
43234a1e L |
15423 | if (vex.evex) |
15424 | { | |
15425 | if (!vex.v) | |
15426 | vindex += 16; | |
15427 | } | |
6c30d220 L |
15428 | |
15429 | haveindex = 1; | |
15430 | switch (vex.length) | |
15431 | { | |
15432 | case 128: | |
7bb15c6f | 15433 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15434 | break; |
15435 | case 256: | |
5fc35d96 IT |
15436 | if (!vex.w |
15437 | || bytemode == vex_vsib_q_w_dq_mode | |
15438 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15439 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15440 | else |
7bb15c6f | 15441 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15442 | break; |
43234a1e | 15443 | case 512: |
5fc35d96 IT |
15444 | if (!vex.w |
15445 | || bytemode == vex_vsib_q_w_dq_mode | |
15446 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15447 | indexes64 = indexes32 = names_zmm; |
15448 | else | |
15449 | indexes64 = indexes32 = names_ymm; | |
15450 | break; | |
6c30d220 L |
15451 | default: |
15452 | abort (); | |
15453 | } | |
15454 | break; | |
15455 | default: | |
15456 | haveindex = vindex != 4; | |
15457 | break; | |
15458 | } | |
15459 | scale = sib.scale; | |
15460 | base = sib.base; | |
252b5132 RH |
15461 | codep++; |
15462 | } | |
82c18208 | 15463 | rbase = base + add; |
252b5132 | 15464 | |
7967e09e | 15465 | switch (modrm.mod) |
252b5132 RH |
15466 | { |
15467 | case 0: | |
82c18208 | 15468 | if (base == 5) |
252b5132 RH |
15469 | { |
15470 | havebase = 0; | |
cb712a9e | 15471 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15472 | riprel = 1; |
15473 | disp = get32s (); | |
252b5132 RH |
15474 | } |
15475 | break; | |
15476 | case 1: | |
15477 | FETCH_DATA (the_info, codep + 1); | |
15478 | disp = *codep++; | |
15479 | if ((disp & 0x80) != 0) | |
15480 | disp -= 0x100; | |
43234a1e L |
15481 | if (vex.evex && shift > 0) |
15482 | disp <<= shift; | |
252b5132 RH |
15483 | break; |
15484 | case 2: | |
52b15da3 | 15485 | disp = get32s (); |
252b5132 RH |
15486 | break; |
15487 | } | |
15488 | ||
20afcfb7 L |
15489 | /* In 32bit mode, we need index register to tell [offset] from |
15490 | [eiz*1 + offset]. */ | |
15491 | needindex = (havesib | |
15492 | && !havebase | |
15493 | && !haveindex | |
15494 | && address_mode == mode_32bit); | |
15495 | havedisp = (havebase | |
15496 | || needindex | |
15497 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15498 | |
252b5132 | 15499 | if (!intel_syntax) |
82c18208 | 15500 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15501 | { |
5d669648 L |
15502 | if (havedisp || riprel) |
15503 | print_displacement (scratchbuf, disp); | |
15504 | else | |
15505 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15506 | oappend (scratchbuf); |
52b15da3 JH |
15507 | if (riprel) |
15508 | { | |
15509 | set_op (disp, 1); | |
87767711 | 15510 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 15511 | } |
db6eb5be | 15512 | } |
2da11e11 | 15513 | |
7e8b059b L |
15514 | if ((havebase || haveindex || riprel) |
15515 | && (bytemode != v_bnd_mode) | |
15516 | && (bytemode != bnd_mode)) | |
87767711 JB |
15517 | used_prefixes |= PREFIX_ADDR; |
15518 | ||
5d669648 | 15519 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15520 | { |
252b5132 | 15521 | *obufp++ = open_char; |
52b15da3 | 15522 | if (intel_syntax && riprel) |
185b1163 L |
15523 | { |
15524 | set_op (disp, 1); | |
87767711 | 15525 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 15526 | } |
db6eb5be | 15527 | *obufp = '\0'; |
252b5132 | 15528 | if (havebase) |
7e8b059b | 15529 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15530 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15531 | if (havesib) |
15532 | { | |
db51cc60 L |
15533 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15534 | print index to tell base + index from base. */ | |
15535 | if (scale != 0 | |
20afcfb7 | 15536 | || needindex |
db51cc60 L |
15537 | || haveindex |
15538 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15539 | { |
9306ca4a | 15540 | if (!intel_syntax || havebase) |
db6eb5be | 15541 | { |
9306ca4a JB |
15542 | *obufp++ = separator_char; |
15543 | *obufp = '\0'; | |
db6eb5be | 15544 | } |
db51cc60 | 15545 | if (haveindex) |
7e8b059b | 15546 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15547 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15548 | else |
7e8b059b | 15549 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15550 | ? index64 : index32); |
15551 | ||
db6eb5be AM |
15552 | *obufp++ = scale_char; |
15553 | *obufp = '\0'; | |
15554 | sprintf (scratchbuf, "%d", 1 << scale); | |
15555 | oappend (scratchbuf); | |
15556 | } | |
252b5132 | 15557 | } |
185b1163 | 15558 | if (intel_syntax |
82c18208 | 15559 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15560 | { |
db51cc60 | 15561 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15562 | { |
15563 | *obufp++ = '+'; | |
15564 | *obufp = '\0'; | |
15565 | } | |
05203043 | 15566 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15567 | { |
15568 | *obufp++ = '-'; | |
15569 | *obufp = '\0'; | |
15570 | disp = - (bfd_signed_vma) disp; | |
15571 | } | |
15572 | ||
db51cc60 L |
15573 | if (havedisp) |
15574 | print_displacement (scratchbuf, disp); | |
15575 | else | |
15576 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15577 | oappend (scratchbuf); |
15578 | } | |
252b5132 RH |
15579 | |
15580 | *obufp++ = close_char; | |
db6eb5be | 15581 | *obufp = '\0'; |
252b5132 RH |
15582 | } |
15583 | else if (intel_syntax) | |
db6eb5be | 15584 | { |
82c18208 | 15585 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15586 | { |
285ca992 | 15587 | if (!active_seg_prefix) |
252b5132 | 15588 | { |
d708bcba | 15589 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15590 | oappend (":"); |
15591 | } | |
52b15da3 | 15592 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15593 | oappend (scratchbuf); |
15594 | } | |
15595 | } | |
252b5132 RH |
15596 | } |
15597 | else | |
f16cd0d5 L |
15598 | { |
15599 | /* 16 bit address mode */ | |
15600 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15601 | switch (modrm.mod) |
252b5132 RH |
15602 | { |
15603 | case 0: | |
7967e09e | 15604 | if (modrm.rm == 6) |
252b5132 RH |
15605 | { |
15606 | disp = get16 (); | |
15607 | if ((disp & 0x8000) != 0) | |
15608 | disp -= 0x10000; | |
15609 | } | |
15610 | break; | |
15611 | case 1: | |
15612 | FETCH_DATA (the_info, codep + 1); | |
15613 | disp = *codep++; | |
15614 | if ((disp & 0x80) != 0) | |
15615 | disp -= 0x100; | |
15616 | break; | |
15617 | case 2: | |
15618 | disp = get16 (); | |
15619 | if ((disp & 0x8000) != 0) | |
15620 | disp -= 0x10000; | |
15621 | break; | |
15622 | } | |
15623 | ||
15624 | if (!intel_syntax) | |
7967e09e | 15625 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15626 | { |
5d669648 | 15627 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15628 | oappend (scratchbuf); |
15629 | } | |
252b5132 | 15630 | |
7967e09e | 15631 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15632 | { |
15633 | *obufp++ = open_char; | |
db6eb5be | 15634 | *obufp = '\0'; |
7967e09e | 15635 | oappend (index16[modrm.rm]); |
5d669648 L |
15636 | if (intel_syntax |
15637 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15638 | { |
5d669648 | 15639 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15640 | { |
15641 | *obufp++ = '+'; | |
15642 | *obufp = '\0'; | |
15643 | } | |
7967e09e | 15644 | else if (modrm.mod != 1) |
3d456fa1 JB |
15645 | { |
15646 | *obufp++ = '-'; | |
15647 | *obufp = '\0'; | |
15648 | disp = - (bfd_signed_vma) disp; | |
15649 | } | |
15650 | ||
5d669648 | 15651 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15652 | oappend (scratchbuf); |
15653 | } | |
15654 | ||
db6eb5be AM |
15655 | *obufp++ = close_char; |
15656 | *obufp = '\0'; | |
252b5132 | 15657 | } |
3d456fa1 JB |
15658 | else if (intel_syntax) |
15659 | { | |
285ca992 | 15660 | if (!active_seg_prefix) |
3d456fa1 JB |
15661 | { |
15662 | oappend (names_seg[ds_reg - es_reg]); | |
15663 | oappend (":"); | |
15664 | } | |
15665 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15666 | oappend (scratchbuf); | |
15667 | } | |
252b5132 | 15668 | } |
43234a1e L |
15669 | if (vex.evex && vex.b |
15670 | && (bytemode == x_mode | |
90a915bf | 15671 | || bytemode == xmmq_mode |
43234a1e L |
15672 | || bytemode == evex_half_bcst_xmmq_mode)) |
15673 | { | |
90a915bf IT |
15674 | if (vex.w |
15675 | || bytemode == xmmq_mode | |
15676 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15677 | { |
15678 | switch (vex.length) | |
15679 | { | |
15680 | case 128: | |
15681 | oappend ("{1to2}"); | |
15682 | break; | |
15683 | case 256: | |
15684 | oappend ("{1to4}"); | |
15685 | break; | |
15686 | case 512: | |
15687 | oappend ("{1to8}"); | |
15688 | break; | |
15689 | default: | |
15690 | abort (); | |
15691 | } | |
15692 | } | |
43234a1e | 15693 | else |
b28d1bda IT |
15694 | { |
15695 | switch (vex.length) | |
15696 | { | |
15697 | case 128: | |
15698 | oappend ("{1to4}"); | |
15699 | break; | |
15700 | case 256: | |
15701 | oappend ("{1to8}"); | |
15702 | break; | |
15703 | case 512: | |
15704 | oappend ("{1to16}"); | |
15705 | break; | |
15706 | default: | |
15707 | abort (); | |
15708 | } | |
15709 | } | |
43234a1e | 15710 | } |
252b5132 RH |
15711 | } |
15712 | ||
c0f3af97 | 15713 | static void |
8b3f93e7 | 15714 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15715 | { |
15716 | /* Skip mod/rm byte. */ | |
15717 | MODRM_CHECK; | |
15718 | codep++; | |
15719 | ||
15720 | if (modrm.mod == 3) | |
15721 | OP_E_register (bytemode, sizeflag); | |
15722 | else | |
c1e679ec | 15723 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15724 | } |
15725 | ||
252b5132 | 15726 | static void |
26ca5450 | 15727 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15728 | { |
52b15da3 | 15729 | int add = 0; |
161a04f6 L |
15730 | USED_REX (REX_R); |
15731 | if (rex & REX_R) | |
52b15da3 | 15732 | add += 8; |
252b5132 RH |
15733 | switch (bytemode) |
15734 | { | |
15735 | case b_mode: | |
52b15da3 JH |
15736 | USED_REX (0); |
15737 | if (rex) | |
7967e09e | 15738 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15739 | else |
7967e09e | 15740 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15741 | break; |
15742 | case w_mode: | |
7967e09e | 15743 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15744 | break; |
15745 | case d_mode: | |
1ba585e8 IT |
15746 | case db_mode: |
15747 | case dw_mode: | |
7967e09e | 15748 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15749 | break; |
15750 | case q_mode: | |
7967e09e | 15751 | oappend (names64[modrm.reg + add]); |
252b5132 | 15752 | break; |
7e8b059b L |
15753 | case bnd_mode: |
15754 | oappend (names_bnd[modrm.reg]); | |
15755 | break; | |
252b5132 | 15756 | case v_mode: |
9306ca4a | 15757 | case dq_mode: |
42903f7f L |
15758 | case dqb_mode: |
15759 | case dqd_mode: | |
9306ca4a | 15760 | case dqw_mode: |
1ba585e8 | 15761 | case dqw_swap_mode: |
161a04f6 L |
15762 | USED_REX (REX_W); |
15763 | if (rex & REX_W) | |
7967e09e | 15764 | oappend (names64[modrm.reg + add]); |
252b5132 | 15765 | else |
f16cd0d5 L |
15766 | { |
15767 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15768 | oappend (names32[modrm.reg + add]); | |
15769 | else | |
15770 | oappend (names16[modrm.reg + add]); | |
15771 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15772 | } | |
252b5132 | 15773 | break; |
90700ea2 | 15774 | case m_mode: |
cb712a9e | 15775 | if (address_mode == mode_64bit) |
7967e09e | 15776 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15777 | else |
7967e09e | 15778 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15779 | break; |
1ba585e8 | 15780 | case mask_bd_mode: |
43234a1e L |
15781 | case mask_mode: |
15782 | oappend (names_mask[modrm.reg + add]); | |
15783 | break; | |
252b5132 RH |
15784 | default: |
15785 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15786 | break; | |
15787 | } | |
15788 | } | |
15789 | ||
52b15da3 | 15790 | static bfd_vma |
26ca5450 | 15791 | get64 (void) |
52b15da3 | 15792 | { |
5dd0794d | 15793 | bfd_vma x; |
52b15da3 | 15794 | #ifdef BFD64 |
5dd0794d AM |
15795 | unsigned int a; |
15796 | unsigned int b; | |
15797 | ||
52b15da3 JH |
15798 | FETCH_DATA (the_info, codep + 8); |
15799 | a = *codep++ & 0xff; | |
15800 | a |= (*codep++ & 0xff) << 8; | |
15801 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15802 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15803 | b = *codep++ & 0xff; |
52b15da3 JH |
15804 | b |= (*codep++ & 0xff) << 8; |
15805 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15806 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15807 | x = a + ((bfd_vma) b << 32); |
15808 | #else | |
6608db57 | 15809 | abort (); |
5dd0794d | 15810 | x = 0; |
52b15da3 JH |
15811 | #endif |
15812 | return x; | |
15813 | } | |
15814 | ||
15815 | static bfd_signed_vma | |
26ca5450 | 15816 | get32 (void) |
252b5132 | 15817 | { |
52b15da3 | 15818 | bfd_signed_vma x = 0; |
252b5132 RH |
15819 | |
15820 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15821 | x = *codep++ & (bfd_signed_vma) 0xff; |
15822 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15823 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15824 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15825 | return x; | |
15826 | } | |
15827 | ||
15828 | static bfd_signed_vma | |
26ca5450 | 15829 | get32s (void) |
52b15da3 JH |
15830 | { |
15831 | bfd_signed_vma x = 0; | |
15832 | ||
15833 | FETCH_DATA (the_info, codep + 4); | |
15834 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15835 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15836 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15837 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15838 | ||
15839 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15840 | ||
252b5132 RH |
15841 | return x; |
15842 | } | |
15843 | ||
15844 | static int | |
26ca5450 | 15845 | get16 (void) |
252b5132 RH |
15846 | { |
15847 | int x = 0; | |
15848 | ||
15849 | FETCH_DATA (the_info, codep + 2); | |
15850 | x = *codep++ & 0xff; | |
15851 | x |= (*codep++ & 0xff) << 8; | |
15852 | return x; | |
15853 | } | |
15854 | ||
15855 | static void | |
26ca5450 | 15856 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15857 | { |
15858 | op_index[op_ad] = op_ad; | |
cb712a9e | 15859 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15860 | { |
15861 | op_address[op_ad] = op; | |
15862 | op_riprel[op_ad] = riprel; | |
15863 | } | |
15864 | else | |
15865 | { | |
15866 | /* Mask to get a 32-bit address. */ | |
15867 | op_address[op_ad] = op & 0xffffffff; | |
15868 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15869 | } | |
252b5132 RH |
15870 | } |
15871 | ||
15872 | static void | |
26ca5450 | 15873 | OP_REG (int code, int sizeflag) |
252b5132 | 15874 | { |
2da11e11 | 15875 | const char *s; |
9b60702d | 15876 | int add; |
de882298 RM |
15877 | |
15878 | switch (code) | |
15879 | { | |
15880 | case es_reg: case ss_reg: case cs_reg: | |
15881 | case ds_reg: case fs_reg: case gs_reg: | |
15882 | oappend (names_seg[code - es_reg]); | |
15883 | return; | |
15884 | } | |
15885 | ||
161a04f6 L |
15886 | USED_REX (REX_B); |
15887 | if (rex & REX_B) | |
52b15da3 | 15888 | add = 8; |
9b60702d L |
15889 | else |
15890 | add = 0; | |
52b15da3 JH |
15891 | |
15892 | switch (code) | |
15893 | { | |
52b15da3 JH |
15894 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15895 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15896 | s = names16[code - ax_reg + add]; | |
15897 | break; | |
52b15da3 JH |
15898 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15899 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15900 | USED_REX (0); | |
15901 | if (rex) | |
15902 | s = names8rex[code - al_reg + add]; | |
15903 | else | |
15904 | s = names8[code - al_reg]; | |
15905 | break; | |
6439fc28 AM |
15906 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15907 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15908 | if (address_mode == mode_64bit |
6c067bbb | 15909 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15910 | { |
15911 | s = names64[code - rAX_reg + add]; | |
15912 | break; | |
15913 | } | |
15914 | code += eAX_reg - rAX_reg; | |
6608db57 | 15915 | /* Fall through. */ |
52b15da3 JH |
15916 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15917 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15918 | USED_REX (REX_W); |
15919 | if (rex & REX_W) | |
52b15da3 | 15920 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15921 | else |
f16cd0d5 L |
15922 | { |
15923 | if (sizeflag & DFLAG) | |
15924 | s = names32[code - eAX_reg + add]; | |
15925 | else | |
15926 | s = names16[code - eAX_reg + add]; | |
15927 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15928 | } | |
52b15da3 | 15929 | break; |
52b15da3 JH |
15930 | default: |
15931 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15932 | break; | |
15933 | } | |
15934 | oappend (s); | |
15935 | } | |
15936 | ||
15937 | static void | |
26ca5450 | 15938 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15939 | { |
15940 | const char *s; | |
252b5132 RH |
15941 | |
15942 | switch (code) | |
15943 | { | |
15944 | case indir_dx_reg: | |
d708bcba | 15945 | if (intel_syntax) |
52fd6d94 | 15946 | s = "dx"; |
d708bcba | 15947 | else |
db6eb5be | 15948 | s = "(%dx)"; |
252b5132 RH |
15949 | break; |
15950 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15951 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15952 | s = names16[code - ax_reg]; | |
15953 | break; | |
15954 | case es_reg: case ss_reg: case cs_reg: | |
15955 | case ds_reg: case fs_reg: case gs_reg: | |
15956 | s = names_seg[code - es_reg]; | |
15957 | break; | |
15958 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15959 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15960 | USED_REX (0); |
15961 | if (rex) | |
15962 | s = names8rex[code - al_reg]; | |
15963 | else | |
15964 | s = names8[code - al_reg]; | |
252b5132 RH |
15965 | break; |
15966 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15967 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15968 | USED_REX (REX_W); |
15969 | if (rex & REX_W) | |
52b15da3 | 15970 | s = names64[code - eAX_reg]; |
252b5132 | 15971 | else |
f16cd0d5 L |
15972 | { |
15973 | if (sizeflag & DFLAG) | |
15974 | s = names32[code - eAX_reg]; | |
15975 | else | |
15976 | s = names16[code - eAX_reg]; | |
15977 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15978 | } | |
252b5132 | 15979 | break; |
52fd6d94 | 15980 | case z_mode_ax_reg: |
161a04f6 | 15981 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15982 | s = *names32; |
15983 | else | |
15984 | s = *names16; | |
161a04f6 | 15985 | if (!(rex & REX_W)) |
52fd6d94 JB |
15986 | used_prefixes |= (prefixes & PREFIX_DATA); |
15987 | break; | |
252b5132 RH |
15988 | default: |
15989 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15990 | break; | |
15991 | } | |
15992 | oappend (s); | |
15993 | } | |
15994 | ||
15995 | static void | |
26ca5450 | 15996 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15997 | { |
52b15da3 JH |
15998 | bfd_signed_vma op; |
15999 | bfd_signed_vma mask = -1; | |
252b5132 RH |
16000 | |
16001 | switch (bytemode) | |
16002 | { | |
16003 | case b_mode: | |
16004 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
16005 | op = *codep++; |
16006 | mask = 0xff; | |
16007 | break; | |
16008 | case q_mode: | |
cb712a9e | 16009 | if (address_mode == mode_64bit) |
6439fc28 AM |
16010 | { |
16011 | op = get32s (); | |
16012 | break; | |
16013 | } | |
6608db57 | 16014 | /* Fall through. */ |
252b5132 | 16015 | case v_mode: |
161a04f6 L |
16016 | USED_REX (REX_W); |
16017 | if (rex & REX_W) | |
52b15da3 | 16018 | op = get32s (); |
252b5132 | 16019 | else |
52b15da3 | 16020 | { |
f16cd0d5 L |
16021 | if (sizeflag & DFLAG) |
16022 | { | |
16023 | op = get32 (); | |
16024 | mask = 0xffffffff; | |
16025 | } | |
16026 | else | |
16027 | { | |
16028 | op = get16 (); | |
16029 | mask = 0xfffff; | |
16030 | } | |
16031 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16032 | } |
252b5132 RH |
16033 | break; |
16034 | case w_mode: | |
52b15da3 | 16035 | mask = 0xfffff; |
252b5132 RH |
16036 | op = get16 (); |
16037 | break; | |
9306ca4a JB |
16038 | case const_1_mode: |
16039 | if (intel_syntax) | |
6c067bbb | 16040 | oappend ("1"); |
9306ca4a | 16041 | return; |
252b5132 RH |
16042 | default: |
16043 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16044 | return; | |
16045 | } | |
16046 | ||
52b15da3 JH |
16047 | op &= mask; |
16048 | scratchbuf[0] = '$'; | |
d708bcba | 16049 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16050 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
16051 | scratchbuf[0] = '\0'; |
16052 | } | |
16053 | ||
16054 | static void | |
26ca5450 | 16055 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
16056 | { |
16057 | bfd_signed_vma op; | |
16058 | bfd_signed_vma mask = -1; | |
16059 | ||
cb712a9e | 16060 | if (address_mode != mode_64bit) |
6439fc28 AM |
16061 | { |
16062 | OP_I (bytemode, sizeflag); | |
16063 | return; | |
16064 | } | |
16065 | ||
52b15da3 JH |
16066 | switch (bytemode) |
16067 | { | |
16068 | case b_mode: | |
16069 | FETCH_DATA (the_info, codep + 1); | |
16070 | op = *codep++; | |
16071 | mask = 0xff; | |
16072 | break; | |
16073 | case v_mode: | |
161a04f6 L |
16074 | USED_REX (REX_W); |
16075 | if (rex & REX_W) | |
52b15da3 | 16076 | op = get64 (); |
52b15da3 JH |
16077 | else |
16078 | { | |
f16cd0d5 L |
16079 | if (sizeflag & DFLAG) |
16080 | { | |
16081 | op = get32 (); | |
16082 | mask = 0xffffffff; | |
16083 | } | |
16084 | else | |
16085 | { | |
16086 | op = get16 (); | |
16087 | mask = 0xfffff; | |
16088 | } | |
16089 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16090 | } |
52b15da3 JH |
16091 | break; |
16092 | case w_mode: | |
16093 | mask = 0xfffff; | |
16094 | op = get16 (); | |
16095 | break; | |
16096 | default: | |
16097 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16098 | return; | |
16099 | } | |
16100 | ||
16101 | op &= mask; | |
16102 | scratchbuf[0] = '$'; | |
d708bcba | 16103 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16104 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16105 | scratchbuf[0] = '\0'; |
16106 | } | |
16107 | ||
16108 | static void | |
26ca5450 | 16109 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16110 | { |
52b15da3 | 16111 | bfd_signed_vma op; |
252b5132 RH |
16112 | |
16113 | switch (bytemode) | |
16114 | { | |
16115 | case b_mode: | |
e3949f17 | 16116 | case b_T_mode: |
252b5132 RH |
16117 | FETCH_DATA (the_info, codep + 1); |
16118 | op = *codep++; | |
16119 | if ((op & 0x80) != 0) | |
16120 | op -= 0x100; | |
e3949f17 L |
16121 | if (bytemode == b_T_mode) |
16122 | { | |
16123 | if (address_mode != mode_64bit | |
7bb15c6f | 16124 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16125 | { |
6c067bbb RM |
16126 | /* The operand-size prefix is overridden by a REX prefix. */ |
16127 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16128 | op &= 0xffffffff; |
16129 | else | |
16130 | op &= 0xffff; | |
16131 | } | |
16132 | } | |
16133 | else | |
16134 | { | |
16135 | if (!(rex & REX_W)) | |
16136 | { | |
16137 | if (sizeflag & DFLAG) | |
16138 | op &= 0xffffffff; | |
16139 | else | |
16140 | op &= 0xffff; | |
16141 | } | |
16142 | } | |
252b5132 RH |
16143 | break; |
16144 | case v_mode: | |
7bb15c6f RM |
16145 | /* The operand-size prefix is overridden by a REX prefix. */ |
16146 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16147 | op = get32s (); |
252b5132 | 16148 | else |
d9e3625e | 16149 | op = get16 (); |
252b5132 RH |
16150 | break; |
16151 | default: | |
16152 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16153 | return; | |
16154 | } | |
52b15da3 JH |
16155 | |
16156 | scratchbuf[0] = '$'; | |
16157 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16158 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16159 | } |
16160 | ||
16161 | static void | |
26ca5450 | 16162 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16163 | { |
52b15da3 | 16164 | bfd_vma disp; |
7081ff04 | 16165 | bfd_vma mask = -1; |
65ca155d | 16166 | bfd_vma segment = 0; |
252b5132 RH |
16167 | |
16168 | switch (bytemode) | |
16169 | { | |
16170 | case b_mode: | |
16171 | FETCH_DATA (the_info, codep + 1); | |
16172 | disp = *codep++; | |
16173 | if ((disp & 0x80) != 0) | |
16174 | disp -= 0x100; | |
16175 | break; | |
16176 | case v_mode: | |
5db04b09 L |
16177 | if (isa64 == amd64) |
16178 | USED_REX (REX_W); | |
16179 | if ((sizeflag & DFLAG) | |
16180 | || (address_mode == mode_64bit | |
16181 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16182 | disp = get32s (); |
252b5132 RH |
16183 | else |
16184 | { | |
16185 | disp = get16 (); | |
206717e8 L |
16186 | if ((disp & 0x8000) != 0) |
16187 | disp -= 0x10000; | |
65ca155d L |
16188 | /* In 16bit mode, address is wrapped around at 64k within |
16189 | the same segment. Otherwise, a data16 prefix on a jump | |
16190 | instruction means that the pc is masked to 16 bits after | |
16191 | the displacement is added! */ | |
16192 | mask = 0xffff; | |
16193 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16194 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16195 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16196 | } |
5db04b09 L |
16197 | if (address_mode != mode_64bit |
16198 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16199 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16200 | break; |
16201 | default: | |
16202 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16203 | return; | |
16204 | } | |
42d5f9c6 | 16205 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16206 | set_op (disp, 0); |
16207 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16208 | oappend (scratchbuf); |
16209 | } | |
16210 | ||
252b5132 | 16211 | static void |
ed7841b3 | 16212 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16213 | { |
ed7841b3 | 16214 | if (bytemode == w_mode) |
7967e09e | 16215 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16216 | else |
7967e09e | 16217 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16218 | } |
16219 | ||
16220 | static void | |
26ca5450 | 16221 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16222 | { |
16223 | int seg, offset; | |
16224 | ||
c608c12e | 16225 | if (sizeflag & DFLAG) |
252b5132 | 16226 | { |
c608c12e AM |
16227 | offset = get32 (); |
16228 | seg = get16 (); | |
252b5132 | 16229 | } |
c608c12e AM |
16230 | else |
16231 | { | |
16232 | offset = get16 (); | |
16233 | seg = get16 (); | |
16234 | } | |
7d421014 | 16235 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16236 | if (intel_syntax) |
3f31e633 | 16237 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16238 | else |
16239 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16240 | oappend (scratchbuf); |
252b5132 RH |
16241 | } |
16242 | ||
252b5132 | 16243 | static void |
3f31e633 | 16244 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16245 | { |
52b15da3 | 16246 | bfd_vma off; |
252b5132 | 16247 | |
3f31e633 JB |
16248 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16249 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16250 | append_seg (); |
16251 | ||
cb712a9e | 16252 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16253 | off = get32 (); |
16254 | else | |
16255 | off = get16 (); | |
16256 | ||
16257 | if (intel_syntax) | |
16258 | { | |
285ca992 | 16259 | if (!active_seg_prefix) |
252b5132 | 16260 | { |
d708bcba | 16261 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16262 | oappend (":"); |
16263 | } | |
16264 | } | |
52b15da3 JH |
16265 | print_operand_value (scratchbuf, 1, off); |
16266 | oappend (scratchbuf); | |
16267 | } | |
6439fc28 | 16268 | |
52b15da3 | 16269 | static void |
3f31e633 | 16270 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16271 | { |
16272 | bfd_vma off; | |
16273 | ||
539e75ad L |
16274 | if (address_mode != mode_64bit |
16275 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16276 | { |
16277 | OP_OFF (bytemode, sizeflag); | |
16278 | return; | |
16279 | } | |
16280 | ||
3f31e633 JB |
16281 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16282 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16283 | append_seg (); |
16284 | ||
6608db57 | 16285 | off = get64 (); |
52b15da3 JH |
16286 | |
16287 | if (intel_syntax) | |
16288 | { | |
285ca992 | 16289 | if (!active_seg_prefix) |
52b15da3 | 16290 | { |
d708bcba | 16291 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16292 | oappend (":"); |
16293 | } | |
16294 | } | |
16295 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16296 | oappend (scratchbuf); |
16297 | } | |
16298 | ||
16299 | static void | |
26ca5450 | 16300 | ptr_reg (int code, int sizeflag) |
252b5132 | 16301 | { |
2da11e11 | 16302 | const char *s; |
d708bcba | 16303 | |
1d9f512f | 16304 | *obufp++ = open_char; |
20f0a1fc | 16305 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16306 | if (address_mode == mode_64bit) |
c1a64871 JH |
16307 | { |
16308 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16309 | s = names32[code - eAX_reg]; |
c1a64871 | 16310 | else |
db6eb5be | 16311 | s = names64[code - eAX_reg]; |
c1a64871 | 16312 | } |
52b15da3 | 16313 | else if (sizeflag & AFLAG) |
252b5132 RH |
16314 | s = names32[code - eAX_reg]; |
16315 | else | |
16316 | s = names16[code - eAX_reg]; | |
16317 | oappend (s); | |
1d9f512f AM |
16318 | *obufp++ = close_char; |
16319 | *obufp = 0; | |
252b5132 RH |
16320 | } |
16321 | ||
16322 | static void | |
26ca5450 | 16323 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16324 | { |
9306ca4a | 16325 | if (intel_syntax) |
52fd6d94 JB |
16326 | { |
16327 | switch (codep[-1]) | |
16328 | { | |
16329 | case 0x6d: /* insw/insl */ | |
16330 | intel_operand_size (z_mode, sizeflag); | |
16331 | break; | |
16332 | case 0xa5: /* movsw/movsl/movsq */ | |
16333 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16334 | case 0xab: /* stosw/stosl */ | |
16335 | case 0xaf: /* scasw/scasl */ | |
16336 | intel_operand_size (v_mode, sizeflag); | |
16337 | break; | |
16338 | default: | |
16339 | intel_operand_size (b_mode, sizeflag); | |
16340 | } | |
16341 | } | |
9ce09ba2 | 16342 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16343 | ptr_reg (code, sizeflag); |
16344 | } | |
16345 | ||
16346 | static void | |
26ca5450 | 16347 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16348 | { |
9306ca4a | 16349 | if (intel_syntax) |
52fd6d94 JB |
16350 | { |
16351 | switch (codep[-1]) | |
16352 | { | |
16353 | case 0x6f: /* outsw/outsl */ | |
16354 | intel_operand_size (z_mode, sizeflag); | |
16355 | break; | |
16356 | case 0xa5: /* movsw/movsl/movsq */ | |
16357 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16358 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16359 | intel_operand_size (v_mode, sizeflag); | |
16360 | break; | |
16361 | default: | |
16362 | intel_operand_size (b_mode, sizeflag); | |
16363 | } | |
16364 | } | |
285ca992 L |
16365 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16366 | default segment register DS is printed. */ | |
16367 | if (!active_seg_prefix) | |
16368 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16369 | append_seg (); |
252b5132 RH |
16370 | ptr_reg (code, sizeflag); |
16371 | } | |
16372 | ||
252b5132 | 16373 | static void |
26ca5450 | 16374 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16375 | { |
9b60702d | 16376 | int add; |
161a04f6 | 16377 | if (rex & REX_R) |
c4a530c5 | 16378 | { |
161a04f6 | 16379 | USED_REX (REX_R); |
c4a530c5 JB |
16380 | add = 8; |
16381 | } | |
cb712a9e | 16382 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16383 | { |
f16cd0d5 | 16384 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16385 | used_prefixes |= PREFIX_LOCK; |
16386 | add = 8; | |
16387 | } | |
9b60702d L |
16388 | else |
16389 | add = 0; | |
7967e09e | 16390 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16391 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16392 | } |
16393 | ||
252b5132 | 16394 | static void |
26ca5450 | 16395 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16396 | { |
9b60702d | 16397 | int add; |
161a04f6 L |
16398 | USED_REX (REX_R); |
16399 | if (rex & REX_R) | |
52b15da3 | 16400 | add = 8; |
9b60702d L |
16401 | else |
16402 | add = 0; | |
d708bcba | 16403 | if (intel_syntax) |
7967e09e | 16404 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16405 | else |
7967e09e | 16406 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16407 | oappend (scratchbuf); |
16408 | } | |
16409 | ||
252b5132 | 16410 | static void |
26ca5450 | 16411 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16412 | { |
7967e09e | 16413 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16414 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16415 | } |
16416 | ||
16417 | static void | |
6f74c397 | 16418 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16419 | { |
68f34464 L |
16420 | /* Skip mod/rm byte. */ |
16421 | MODRM_CHECK; | |
16422 | codep++; | |
16423 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16424 | } |
16425 | ||
16426 | static void | |
26ca5450 | 16427 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16428 | { |
b9733481 L |
16429 | int reg = modrm.reg; |
16430 | const char **names; | |
16431 | ||
041bd2e0 JH |
16432 | used_prefixes |= (prefixes & PREFIX_DATA); |
16433 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16434 | { |
b9733481 | 16435 | names = names_xmm; |
161a04f6 L |
16436 | USED_REX (REX_R); |
16437 | if (rex & REX_R) | |
b9733481 | 16438 | reg += 8; |
20f0a1fc | 16439 | } |
041bd2e0 | 16440 | else |
b9733481 L |
16441 | names = names_mm; |
16442 | oappend (names[reg]); | |
252b5132 RH |
16443 | } |
16444 | ||
c608c12e | 16445 | static void |
c0f3af97 | 16446 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16447 | { |
b9733481 L |
16448 | int reg = modrm.reg; |
16449 | const char **names; | |
16450 | ||
161a04f6 L |
16451 | USED_REX (REX_R); |
16452 | if (rex & REX_R) | |
b9733481 | 16453 | reg += 8; |
43234a1e L |
16454 | if (vex.evex) |
16455 | { | |
16456 | if (!vex.r) | |
16457 | reg += 16; | |
16458 | } | |
16459 | ||
539f890d L |
16460 | if (need_vex |
16461 | && bytemode != xmm_mode | |
43234a1e L |
16462 | && bytemode != xmmq_mode |
16463 | && bytemode != evex_half_bcst_xmmq_mode | |
16464 | && bytemode != ymm_mode | |
539f890d | 16465 | && bytemode != scalar_mode) |
c0f3af97 L |
16466 | { |
16467 | switch (vex.length) | |
16468 | { | |
16469 | case 128: | |
b9733481 | 16470 | names = names_xmm; |
c0f3af97 L |
16471 | break; |
16472 | case 256: | |
5fc35d96 IT |
16473 | if (vex.w |
16474 | || (bytemode != vex_vsib_q_w_dq_mode | |
16475 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16476 | names = names_ymm; |
16477 | else | |
16478 | names = names_xmm; | |
c0f3af97 | 16479 | break; |
43234a1e L |
16480 | case 512: |
16481 | names = names_zmm; | |
16482 | break; | |
c0f3af97 L |
16483 | default: |
16484 | abort (); | |
16485 | } | |
16486 | } | |
43234a1e L |
16487 | else if (bytemode == xmmq_mode |
16488 | || bytemode == evex_half_bcst_xmmq_mode) | |
16489 | { | |
16490 | switch (vex.length) | |
16491 | { | |
16492 | case 128: | |
16493 | case 256: | |
16494 | names = names_xmm; | |
16495 | break; | |
16496 | case 512: | |
16497 | names = names_ymm; | |
16498 | break; | |
16499 | default: | |
16500 | abort (); | |
16501 | } | |
16502 | } | |
16503 | else if (bytemode == ymm_mode) | |
16504 | names = names_ymm; | |
c0f3af97 | 16505 | else |
b9733481 L |
16506 | names = names_xmm; |
16507 | oappend (names[reg]); | |
c608c12e AM |
16508 | } |
16509 | ||
252b5132 | 16510 | static void |
26ca5450 | 16511 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16512 | { |
b9733481 L |
16513 | int reg; |
16514 | const char **names; | |
16515 | ||
7967e09e | 16516 | if (modrm.mod != 3) |
252b5132 | 16517 | { |
b6169b20 L |
16518 | if (intel_syntax |
16519 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16520 | { |
16521 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16522 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16523 | } |
252b5132 RH |
16524 | OP_E (bytemode, sizeflag); |
16525 | return; | |
16526 | } | |
16527 | ||
b6169b20 L |
16528 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16529 | swap_operand (); | |
16530 | ||
6608db57 | 16531 | /* Skip mod/rm byte. */ |
4bba6815 | 16532 | MODRM_CHECK; |
252b5132 | 16533 | codep++; |
041bd2e0 | 16534 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16535 | reg = modrm.rm; |
041bd2e0 | 16536 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16537 | { |
b9733481 | 16538 | names = names_xmm; |
161a04f6 L |
16539 | USED_REX (REX_B); |
16540 | if (rex & REX_B) | |
b9733481 | 16541 | reg += 8; |
20f0a1fc | 16542 | } |
041bd2e0 | 16543 | else |
b9733481 L |
16544 | names = names_mm; |
16545 | oappend (names[reg]); | |
252b5132 RH |
16546 | } |
16547 | ||
246c51aa L |
16548 | /* cvt* are the only instructions in sse2 which have |
16549 | both SSE and MMX operands and also have 0x66 prefix | |
16550 | in their opcode. 0x66 was originally used to differentiate | |
16551 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16552 | cvt* separately using OP_EMC and OP_MXC */ |
16553 | static void | |
16554 | OP_EMC (int bytemode, int sizeflag) | |
16555 | { | |
7967e09e | 16556 | if (modrm.mod != 3) |
4d9567e0 MM |
16557 | { |
16558 | if (intel_syntax && bytemode == v_mode) | |
16559 | { | |
16560 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16561 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16562 | } |
4d9567e0 MM |
16563 | OP_E (bytemode, sizeflag); |
16564 | return; | |
16565 | } | |
246c51aa | 16566 | |
4d9567e0 MM |
16567 | /* Skip mod/rm byte. */ |
16568 | MODRM_CHECK; | |
16569 | codep++; | |
16570 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16571 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16572 | } |
16573 | ||
16574 | static void | |
16575 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16576 | { | |
16577 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16578 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16579 | } |
16580 | ||
c608c12e | 16581 | static void |
26ca5450 | 16582 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16583 | { |
b9733481 L |
16584 | int reg; |
16585 | const char **names; | |
d6f574e0 L |
16586 | |
16587 | /* Skip mod/rm byte. */ | |
16588 | MODRM_CHECK; | |
16589 | codep++; | |
16590 | ||
7967e09e | 16591 | if (modrm.mod != 3) |
c608c12e | 16592 | { |
c1e679ec | 16593 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16594 | return; |
16595 | } | |
d6f574e0 | 16596 | |
b9733481 | 16597 | reg = modrm.rm; |
161a04f6 L |
16598 | USED_REX (REX_B); |
16599 | if (rex & REX_B) | |
b9733481 | 16600 | reg += 8; |
43234a1e L |
16601 | if (vex.evex) |
16602 | { | |
16603 | USED_REX (REX_X); | |
16604 | if ((rex & REX_X)) | |
16605 | reg += 16; | |
16606 | } | |
c608c12e | 16607 | |
b6169b20 | 16608 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16609 | && (bytemode == x_swap_mode |
16610 | || bytemode == d_swap_mode | |
1ba585e8 | 16611 | || bytemode == dqw_swap_mode |
7bb15c6f | 16612 | || bytemode == d_scalar_swap_mode |
539f890d L |
16613 | || bytemode == q_swap_mode |
16614 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16615 | swap_operand (); |
16616 | ||
c0f3af97 L |
16617 | if (need_vex |
16618 | && bytemode != xmm_mode | |
6c30d220 L |
16619 | && bytemode != xmmdw_mode |
16620 | && bytemode != xmmqd_mode | |
16621 | && bytemode != xmm_mb_mode | |
16622 | && bytemode != xmm_mw_mode | |
16623 | && bytemode != xmm_md_mode | |
16624 | && bytemode != xmm_mq_mode | |
43234a1e | 16625 | && bytemode != xmm_mdq_mode |
539f890d | 16626 | && bytemode != xmmq_mode |
43234a1e L |
16627 | && bytemode != evex_half_bcst_xmmq_mode |
16628 | && bytemode != ymm_mode | |
539f890d | 16629 | && bytemode != d_scalar_mode |
7bb15c6f | 16630 | && bytemode != d_scalar_swap_mode |
539f890d | 16631 | && bytemode != q_scalar_mode |
1c480963 L |
16632 | && bytemode != q_scalar_swap_mode |
16633 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16634 | { |
16635 | switch (vex.length) | |
16636 | { | |
16637 | case 128: | |
b9733481 | 16638 | names = names_xmm; |
c0f3af97 L |
16639 | break; |
16640 | case 256: | |
b9733481 | 16641 | names = names_ymm; |
c0f3af97 | 16642 | break; |
43234a1e L |
16643 | case 512: |
16644 | names = names_zmm; | |
16645 | break; | |
c0f3af97 L |
16646 | default: |
16647 | abort (); | |
16648 | } | |
16649 | } | |
43234a1e L |
16650 | else if (bytemode == xmmq_mode |
16651 | || bytemode == evex_half_bcst_xmmq_mode) | |
16652 | { | |
16653 | switch (vex.length) | |
16654 | { | |
16655 | case 128: | |
16656 | case 256: | |
16657 | names = names_xmm; | |
16658 | break; | |
16659 | case 512: | |
16660 | names = names_ymm; | |
16661 | break; | |
16662 | default: | |
16663 | abort (); | |
16664 | } | |
16665 | } | |
16666 | else if (bytemode == ymm_mode) | |
16667 | names = names_ymm; | |
c0f3af97 | 16668 | else |
b9733481 L |
16669 | names = names_xmm; |
16670 | oappend (names[reg]); | |
c608c12e AM |
16671 | } |
16672 | ||
252b5132 | 16673 | static void |
26ca5450 | 16674 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16675 | { |
7967e09e | 16676 | if (modrm.mod == 3) |
2da11e11 AM |
16677 | OP_EM (bytemode, sizeflag); |
16678 | else | |
6608db57 | 16679 | BadOp (); |
252b5132 RH |
16680 | } |
16681 | ||
992aaec9 | 16682 | static void |
26ca5450 | 16683 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16684 | { |
7967e09e | 16685 | if (modrm.mod == 3) |
992aaec9 AM |
16686 | OP_EX (bytemode, sizeflag); |
16687 | else | |
6608db57 | 16688 | BadOp (); |
992aaec9 AM |
16689 | } |
16690 | ||
cc0ec051 AM |
16691 | static void |
16692 | OP_M (int bytemode, int sizeflag) | |
16693 | { | |
7967e09e | 16694 | if (modrm.mod == 3) |
75413a22 L |
16695 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16696 | BadOp (); | |
cc0ec051 AM |
16697 | else |
16698 | OP_E (bytemode, sizeflag); | |
16699 | } | |
16700 | ||
16701 | static void | |
16702 | OP_0f07 (int bytemode, int sizeflag) | |
16703 | { | |
7967e09e | 16704 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16705 | BadOp (); |
16706 | else | |
16707 | OP_E (bytemode, sizeflag); | |
16708 | } | |
16709 | ||
46e883c5 | 16710 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16711 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16712 | |
cc0ec051 | 16713 | static void |
46e883c5 | 16714 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16715 | { |
8b38ad71 L |
16716 | if ((prefixes & PREFIX_DATA) != 0 |
16717 | || (rex != 0 | |
16718 | && rex != 0x48 | |
16719 | && address_mode == mode_64bit)) | |
46e883c5 L |
16720 | OP_REG (bytemode, sizeflag); |
16721 | else | |
16722 | strcpy (obuf, "nop"); | |
16723 | } | |
16724 | ||
16725 | static void | |
16726 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16727 | { | |
8b38ad71 L |
16728 | if ((prefixes & PREFIX_DATA) != 0 |
16729 | || (rex != 0 | |
16730 | && rex != 0x48 | |
16731 | && address_mode == mode_64bit)) | |
46e883c5 | 16732 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16733 | } |
16734 | ||
84037f8c | 16735 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16736 | /* 00 */ NULL, NULL, NULL, NULL, |
16737 | /* 04 */ NULL, NULL, NULL, NULL, | |
16738 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16739 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16740 | /* 10 */ NULL, NULL, NULL, NULL, |
16741 | /* 14 */ NULL, NULL, NULL, NULL, | |
16742 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16743 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16744 | /* 20 */ NULL, NULL, NULL, NULL, |
16745 | /* 24 */ NULL, NULL, NULL, NULL, | |
16746 | /* 28 */ NULL, NULL, NULL, NULL, | |
16747 | /* 2C */ NULL, NULL, NULL, NULL, | |
16748 | /* 30 */ NULL, NULL, NULL, NULL, | |
16749 | /* 34 */ NULL, NULL, NULL, NULL, | |
16750 | /* 38 */ NULL, NULL, NULL, NULL, | |
16751 | /* 3C */ NULL, NULL, NULL, NULL, | |
16752 | /* 40 */ NULL, NULL, NULL, NULL, | |
16753 | /* 44 */ NULL, NULL, NULL, NULL, | |
16754 | /* 48 */ NULL, NULL, NULL, NULL, | |
16755 | /* 4C */ NULL, NULL, NULL, NULL, | |
16756 | /* 50 */ NULL, NULL, NULL, NULL, | |
16757 | /* 54 */ NULL, NULL, NULL, NULL, | |
16758 | /* 58 */ NULL, NULL, NULL, NULL, | |
16759 | /* 5C */ NULL, NULL, NULL, NULL, | |
16760 | /* 60 */ NULL, NULL, NULL, NULL, | |
16761 | /* 64 */ NULL, NULL, NULL, NULL, | |
16762 | /* 68 */ NULL, NULL, NULL, NULL, | |
16763 | /* 6C */ NULL, NULL, NULL, NULL, | |
16764 | /* 70 */ NULL, NULL, NULL, NULL, | |
16765 | /* 74 */ NULL, NULL, NULL, NULL, | |
16766 | /* 78 */ NULL, NULL, NULL, NULL, | |
16767 | /* 7C */ NULL, NULL, NULL, NULL, | |
16768 | /* 80 */ NULL, NULL, NULL, NULL, | |
16769 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16770 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16771 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16772 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16773 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16774 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16775 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16776 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16777 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16778 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16779 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16780 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16781 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16782 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16783 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16784 | /* C0 */ NULL, NULL, NULL, NULL, | |
16785 | /* C4 */ NULL, NULL, NULL, NULL, | |
16786 | /* C8 */ NULL, NULL, NULL, NULL, | |
16787 | /* CC */ NULL, NULL, NULL, NULL, | |
16788 | /* D0 */ NULL, NULL, NULL, NULL, | |
16789 | /* D4 */ NULL, NULL, NULL, NULL, | |
16790 | /* D8 */ NULL, NULL, NULL, NULL, | |
16791 | /* DC */ NULL, NULL, NULL, NULL, | |
16792 | /* E0 */ NULL, NULL, NULL, NULL, | |
16793 | /* E4 */ NULL, NULL, NULL, NULL, | |
16794 | /* E8 */ NULL, NULL, NULL, NULL, | |
16795 | /* EC */ NULL, NULL, NULL, NULL, | |
16796 | /* F0 */ NULL, NULL, NULL, NULL, | |
16797 | /* F4 */ NULL, NULL, NULL, NULL, | |
16798 | /* F8 */ NULL, NULL, NULL, NULL, | |
16799 | /* FC */ NULL, NULL, NULL, NULL, | |
16800 | }; | |
16801 | ||
16802 | static void | |
26ca5450 | 16803 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16804 | { |
16805 | const char *mnemonic; | |
16806 | ||
16807 | FETCH_DATA (the_info, codep + 1); | |
16808 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16809 | place where an 8-bit immediate would normally go. ie. the last | |
16810 | byte of the instruction. */ | |
ea397f5b | 16811 | obufp = mnemonicendp; |
c608c12e | 16812 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16813 | if (mnemonic) |
2da11e11 | 16814 | oappend (mnemonic); |
252b5132 RH |
16815 | else |
16816 | { | |
16817 | /* Since a variable sized modrm/sib chunk is between the start | |
16818 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16819 | all the modrm processing first, and don't know until now that | |
16820 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16821 | op_out[0][0] = '\0'; |
16822 | op_out[1][0] = '\0'; | |
6608db57 | 16823 | BadOp (); |
252b5132 | 16824 | } |
ea397f5b | 16825 | mnemonicendp = obufp; |
252b5132 | 16826 | } |
c608c12e | 16827 | |
ea397f5b L |
16828 | static struct op simd_cmp_op[] = |
16829 | { | |
16830 | { STRING_COMMA_LEN ("eq") }, | |
16831 | { STRING_COMMA_LEN ("lt") }, | |
16832 | { STRING_COMMA_LEN ("le") }, | |
16833 | { STRING_COMMA_LEN ("unord") }, | |
16834 | { STRING_COMMA_LEN ("neq") }, | |
16835 | { STRING_COMMA_LEN ("nlt") }, | |
16836 | { STRING_COMMA_LEN ("nle") }, | |
16837 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16838 | }; |
16839 | ||
16840 | static void | |
ad19981d | 16841 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16842 | { |
16843 | unsigned int cmp_type; | |
16844 | ||
16845 | FETCH_DATA (the_info, codep + 1); | |
16846 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16847 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16848 | { |
ad19981d | 16849 | char suffix [3]; |
ea397f5b | 16850 | char *p = mnemonicendp - 2; |
ad19981d L |
16851 | suffix[0] = p[0]; |
16852 | suffix[1] = p[1]; | |
16853 | suffix[2] = '\0'; | |
ea397f5b L |
16854 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16855 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16856 | } |
16857 | else | |
16858 | { | |
ad19981d L |
16859 | /* We have a reserved extension byte. Output it directly. */ |
16860 | scratchbuf[0] = '$'; | |
16861 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16862 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16863 | scratchbuf[0] = '\0'; |
c608c12e AM |
16864 | } |
16865 | } | |
16866 | ||
9916071f AP |
16867 | static void |
16868 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16869 | int sizeflag ATTRIBUTE_UNUSED) | |
16870 | { | |
16871 | /* mwaitx %eax,%ecx,%ebx */ | |
16872 | if (!intel_syntax) | |
16873 | { | |
16874 | const char **names = (address_mode == mode_64bit | |
16875 | ? names64 : names32); | |
16876 | strcpy (op_out[0], names[0]); | |
16877 | strcpy (op_out[1], names[1]); | |
16878 | strcpy (op_out[2], names[3]); | |
16879 | two_source_ops = 1; | |
16880 | } | |
16881 | /* Skip mod/rm byte. */ | |
16882 | MODRM_CHECK; | |
16883 | codep++; | |
16884 | } | |
16885 | ||
ca164297 | 16886 | static void |
b844680a L |
16887 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16888 | int sizeflag ATTRIBUTE_UNUSED) | |
16889 | { | |
16890 | /* mwait %eax,%ecx */ | |
16891 | if (!intel_syntax) | |
16892 | { | |
16893 | const char **names = (address_mode == mode_64bit | |
16894 | ? names64 : names32); | |
16895 | strcpy (op_out[0], names[0]); | |
16896 | strcpy (op_out[1], names[1]); | |
16897 | two_source_ops = 1; | |
16898 | } | |
16899 | /* Skip mod/rm byte. */ | |
16900 | MODRM_CHECK; | |
16901 | codep++; | |
16902 | } | |
16903 | ||
16904 | static void | |
16905 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16906 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16907 | { |
b844680a L |
16908 | /* monitor %eax,%ecx,%edx" */ |
16909 | if (!intel_syntax) | |
ca164297 | 16910 | { |
b844680a | 16911 | const char **op1_names; |
cb712a9e L |
16912 | const char **names = (address_mode == mode_64bit |
16913 | ? names64 : names32); | |
1d9f512f | 16914 | |
b844680a L |
16915 | if (!(prefixes & PREFIX_ADDR)) |
16916 | op1_names = (address_mode == mode_16bit | |
16917 | ? names16 : names); | |
ca164297 L |
16918 | else |
16919 | { | |
b844680a | 16920 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16921 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16922 | op1_names = (address_mode != mode_32bit |
16923 | ? names32 : names16); | |
16924 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16925 | } |
b844680a L |
16926 | strcpy (op_out[0], op1_names[0]); |
16927 | strcpy (op_out[1], names[1]); | |
16928 | strcpy (op_out[2], names[2]); | |
16929 | two_source_ops = 1; | |
ca164297 | 16930 | } |
b844680a L |
16931 | /* Skip mod/rm byte. */ |
16932 | MODRM_CHECK; | |
16933 | codep++; | |
30123838 JB |
16934 | } |
16935 | ||
6608db57 KH |
16936 | static void |
16937 | BadOp (void) | |
2da11e11 | 16938 | { |
6608db57 KH |
16939 | /* Throw away prefixes and 1st. opcode byte. */ |
16940 | codep = insn_codep + 1; | |
2da11e11 AM |
16941 | oappend ("(bad)"); |
16942 | } | |
4cc91dba | 16943 | |
35c52694 L |
16944 | static void |
16945 | REP_Fixup (int bytemode, int sizeflag) | |
16946 | { | |
16947 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16948 | lods and stos. */ | |
35c52694 | 16949 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16950 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16951 | |
16952 | switch (bytemode) | |
16953 | { | |
16954 | case al_reg: | |
16955 | case eAX_reg: | |
16956 | case indir_dx_reg: | |
16957 | OP_IMREG (bytemode, sizeflag); | |
16958 | break; | |
16959 | case eDI_reg: | |
16960 | OP_ESreg (bytemode, sizeflag); | |
16961 | break; | |
16962 | case eSI_reg: | |
16963 | OP_DSreg (bytemode, sizeflag); | |
16964 | break; | |
16965 | default: | |
16966 | abort (); | |
16967 | break; | |
16968 | } | |
16969 | } | |
f5804c90 | 16970 | |
7e8b059b L |
16971 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16972 | "bnd". */ | |
16973 | ||
16974 | static void | |
16975 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16976 | { | |
16977 | if (prefixes & PREFIX_REPNZ) | |
16978 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16979 | } | |
16980 | ||
42164a71 L |
16981 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16982 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16983 | */ | |
16984 | ||
16985 | static void | |
16986 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16987 | { | |
16988 | if (modrm.mod != 3 | |
16989 | && (prefixes & PREFIX_LOCK) != 0) | |
16990 | { | |
16991 | if (prefixes & PREFIX_REPZ) | |
16992 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16993 | if (prefixes & PREFIX_REPNZ) | |
16994 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16995 | } | |
16996 | ||
16997 | OP_E (bytemode, sizeflag); | |
16998 | } | |
16999 | ||
17000 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
17001 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
17002 | */ | |
17003 | ||
17004 | static void | |
17005 | HLE_Fixup2 (int bytemode, int sizeflag) | |
17006 | { | |
17007 | if (modrm.mod != 3) | |
17008 | { | |
17009 | if (prefixes & PREFIX_REPZ) | |
17010 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17011 | if (prefixes & PREFIX_REPNZ) | |
17012 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17013 | } | |
17014 | ||
17015 | OP_E (bytemode, sizeflag); | |
17016 | } | |
17017 | ||
17018 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
17019 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
17020 | ||
17021 | static void | |
17022 | HLE_Fixup3 (int bytemode, int sizeflag) | |
17023 | { | |
17024 | if (modrm.mod != 3 | |
17025 | && last_repz_prefix > last_repnz_prefix | |
17026 | && (prefixes & PREFIX_REPZ) != 0) | |
17027 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17028 | ||
17029 | OP_E (bytemode, sizeflag); | |
17030 | } | |
17031 | ||
f5804c90 L |
17032 | static void |
17033 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
17034 | { | |
161a04f6 L |
17035 | USED_REX (REX_W); |
17036 | if (rex & REX_W) | |
f5804c90 L |
17037 | { |
17038 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
17039 | char *p = mnemonicendp - 2; |
17040 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 17041 | bytemode = o_mode; |
f5804c90 | 17042 | } |
42164a71 L |
17043 | else if ((prefixes & PREFIX_LOCK) != 0) |
17044 | { | |
17045 | if (prefixes & PREFIX_REPZ) | |
17046 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17047 | if (prefixes & PREFIX_REPNZ) | |
17048 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17049 | } | |
17050 | ||
f5804c90 L |
17051 | OP_M (bytemode, sizeflag); |
17052 | } | |
42903f7f L |
17053 | |
17054 | static void | |
17055 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
17056 | { | |
b9733481 L |
17057 | const char **names; |
17058 | ||
c0f3af97 L |
17059 | if (need_vex) |
17060 | { | |
17061 | switch (vex.length) | |
17062 | { | |
17063 | case 128: | |
b9733481 | 17064 | names = names_xmm; |
c0f3af97 L |
17065 | break; |
17066 | case 256: | |
b9733481 | 17067 | names = names_ymm; |
c0f3af97 L |
17068 | break; |
17069 | default: | |
17070 | abort (); | |
17071 | } | |
17072 | } | |
17073 | else | |
b9733481 L |
17074 | names = names_xmm; |
17075 | oappend (names[reg]); | |
42903f7f | 17076 | } |
381d071f L |
17077 | |
17078 | static void | |
17079 | CRC32_Fixup (int bytemode, int sizeflag) | |
17080 | { | |
17081 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 17082 | char *p = mnemonicendp; |
381d071f L |
17083 | |
17084 | switch (bytemode) | |
17085 | { | |
17086 | case b_mode: | |
20592a94 | 17087 | if (intel_syntax) |
ea397f5b | 17088 | goto skip; |
20592a94 | 17089 | |
381d071f L |
17090 | *p++ = 'b'; |
17091 | break; | |
17092 | case v_mode: | |
20592a94 | 17093 | if (intel_syntax) |
ea397f5b | 17094 | goto skip; |
20592a94 | 17095 | |
381d071f L |
17096 | USED_REX (REX_W); |
17097 | if (rex & REX_W) | |
17098 | *p++ = 'q'; | |
7bb15c6f | 17099 | else |
f16cd0d5 L |
17100 | { |
17101 | if (sizeflag & DFLAG) | |
17102 | *p++ = 'l'; | |
17103 | else | |
17104 | *p++ = 'w'; | |
17105 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17106 | } | |
381d071f L |
17107 | break; |
17108 | default: | |
17109 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17110 | break; | |
17111 | } | |
ea397f5b | 17112 | mnemonicendp = p; |
381d071f L |
17113 | *p = '\0'; |
17114 | ||
ea397f5b | 17115 | skip: |
381d071f L |
17116 | if (modrm.mod == 3) |
17117 | { | |
17118 | int add; | |
17119 | ||
17120 | /* Skip mod/rm byte. */ | |
17121 | MODRM_CHECK; | |
17122 | codep++; | |
17123 | ||
17124 | USED_REX (REX_B); | |
17125 | add = (rex & REX_B) ? 8 : 0; | |
17126 | if (bytemode == b_mode) | |
17127 | { | |
17128 | USED_REX (0); | |
17129 | if (rex) | |
17130 | oappend (names8rex[modrm.rm + add]); | |
17131 | else | |
17132 | oappend (names8[modrm.rm + add]); | |
17133 | } | |
17134 | else | |
17135 | { | |
17136 | USED_REX (REX_W); | |
17137 | if (rex & REX_W) | |
17138 | oappend (names64[modrm.rm + add]); | |
17139 | else if ((prefixes & PREFIX_DATA)) | |
17140 | oappend (names16[modrm.rm + add]); | |
17141 | else | |
17142 | oappend (names32[modrm.rm + add]); | |
17143 | } | |
17144 | } | |
17145 | else | |
9344ff29 | 17146 | OP_E (bytemode, sizeflag); |
381d071f | 17147 | } |
85f10a01 | 17148 | |
eacc9c89 L |
17149 | static void |
17150 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17151 | { | |
17152 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17153 | USED_REX (REX_W); | |
17154 | if (rex & REX_W) | |
17155 | { | |
17156 | char *p = mnemonicendp; | |
17157 | *p++ = '6'; | |
17158 | *p++ = '4'; | |
17159 | *p = '\0'; | |
17160 | mnemonicendp = p; | |
17161 | } | |
17162 | OP_M (bytemode, sizeflag); | |
17163 | } | |
17164 | ||
c0f3af97 L |
17165 | /* Display the destination register operand for instructions with |
17166 | VEX. */ | |
17167 | ||
17168 | static void | |
17169 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17170 | { | |
539f890d | 17171 | int reg; |
b9733481 L |
17172 | const char **names; |
17173 | ||
c0f3af97 L |
17174 | if (!need_vex) |
17175 | abort (); | |
17176 | ||
17177 | if (!need_vex_reg) | |
17178 | return; | |
17179 | ||
539f890d | 17180 | reg = vex.register_specifier; |
43234a1e L |
17181 | if (vex.evex) |
17182 | { | |
17183 | if (!vex.v) | |
17184 | reg += 16; | |
17185 | } | |
17186 | ||
539f890d L |
17187 | if (bytemode == vex_scalar_mode) |
17188 | { | |
17189 | oappend (names_xmm[reg]); | |
17190 | return; | |
17191 | } | |
17192 | ||
c0f3af97 L |
17193 | switch (vex.length) |
17194 | { | |
17195 | case 128: | |
17196 | switch (bytemode) | |
17197 | { | |
17198 | case vex_mode: | |
17199 | case vex128_mode: | |
6c30d220 | 17200 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17201 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17202 | names = names_xmm; |
17203 | break; | |
17204 | case dq_mode: | |
17205 | if (vex.w) | |
17206 | names = names64; | |
17207 | else | |
17208 | names = names32; | |
c0f3af97 | 17209 | break; |
1ba585e8 | 17210 | case mask_bd_mode: |
43234a1e L |
17211 | case mask_mode: |
17212 | names = names_mask; | |
17213 | break; | |
c0f3af97 L |
17214 | default: |
17215 | abort (); | |
17216 | return; | |
17217 | } | |
c0f3af97 L |
17218 | break; |
17219 | case 256: | |
17220 | switch (bytemode) | |
17221 | { | |
17222 | case vex_mode: | |
17223 | case vex256_mode: | |
6c30d220 L |
17224 | names = names_ymm; |
17225 | break; | |
17226 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17227 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17228 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17229 | break; |
1ba585e8 | 17230 | case mask_bd_mode: |
43234a1e L |
17231 | case mask_mode: |
17232 | names = names_mask; | |
17233 | break; | |
c0f3af97 L |
17234 | default: |
17235 | abort (); | |
17236 | return; | |
17237 | } | |
c0f3af97 | 17238 | break; |
43234a1e L |
17239 | case 512: |
17240 | names = names_zmm; | |
17241 | break; | |
c0f3af97 L |
17242 | default: |
17243 | abort (); | |
17244 | break; | |
17245 | } | |
539f890d | 17246 | oappend (names[reg]); |
c0f3af97 L |
17247 | } |
17248 | ||
922d8de8 DR |
17249 | /* Get the VEX immediate byte without moving codep. */ |
17250 | ||
17251 | static unsigned char | |
ccc5981b | 17252 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17253 | { |
17254 | int bytes_before_imm = 0; | |
17255 | ||
922d8de8 DR |
17256 | if (modrm.mod != 3) |
17257 | { | |
17258 | /* There are SIB/displacement bytes. */ | |
17259 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17260 | { |
922d8de8 | 17261 | /* 32/64 bit address mode */ |
6c067bbb | 17262 | int base = modrm.rm; |
922d8de8 DR |
17263 | |
17264 | /* Check SIB byte. */ | |
6c067bbb RM |
17265 | if (base == 4) |
17266 | { | |
17267 | FETCH_DATA (the_info, codep + 1); | |
17268 | base = *codep & 7; | |
17269 | /* When decoding the third source, don't increase | |
17270 | bytes_before_imm as this has already been incremented | |
17271 | by one in OP_E_memory while decoding the second | |
17272 | source operand. */ | |
17273 | if (opnum == 0) | |
17274 | bytes_before_imm++; | |
17275 | } | |
17276 | ||
17277 | /* Don't increase bytes_before_imm when decoding the third source, | |
17278 | it has already been incremented by OP_E_memory while decoding | |
17279 | the second source operand. */ | |
17280 | if (opnum == 0) | |
17281 | { | |
17282 | switch (modrm.mod) | |
17283 | { | |
17284 | case 0: | |
17285 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17286 | SIB == 5, there is a 4 byte displacement. */ | |
17287 | if (base != 5) | |
17288 | /* No displacement. */ | |
17289 | break; | |
17290 | case 2: | |
17291 | /* 4 byte displacement. */ | |
17292 | bytes_before_imm += 4; | |
17293 | break; | |
17294 | case 1: | |
17295 | /* 1 byte displacement. */ | |
17296 | bytes_before_imm++; | |
17297 | break; | |
17298 | } | |
17299 | } | |
17300 | } | |
922d8de8 | 17301 | else |
02e647f9 SP |
17302 | { |
17303 | /* 16 bit address mode */ | |
6c067bbb RM |
17304 | /* Don't increase bytes_before_imm when decoding the third source, |
17305 | it has already been incremented by OP_E_memory while decoding | |
17306 | the second source operand. */ | |
17307 | if (opnum == 0) | |
17308 | { | |
02e647f9 SP |
17309 | switch (modrm.mod) |
17310 | { | |
17311 | case 0: | |
17312 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17313 | if (modrm.rm != 6) | |
17314 | /* No displacement. */ | |
17315 | break; | |
17316 | case 2: | |
17317 | /* 2 byte displacement. */ | |
17318 | bytes_before_imm += 2; | |
17319 | break; | |
17320 | case 1: | |
17321 | /* 1 byte displacement: when decoding the third source, | |
17322 | don't increase bytes_before_imm as this has already | |
17323 | been incremented by one in OP_E_memory while decoding | |
17324 | the second source operand. */ | |
17325 | if (opnum == 0) | |
17326 | bytes_before_imm++; | |
ccc5981b | 17327 | |
02e647f9 SP |
17328 | break; |
17329 | } | |
922d8de8 DR |
17330 | } |
17331 | } | |
17332 | } | |
17333 | ||
17334 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17335 | return codep [bytes_before_imm]; | |
17336 | } | |
17337 | ||
17338 | static void | |
17339 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17340 | { | |
b9733481 L |
17341 | const char **names; |
17342 | ||
922d8de8 DR |
17343 | if (reg == -1 && modrm.mod != 3) |
17344 | { | |
17345 | OP_E_memory (bytemode, sizeflag); | |
17346 | return; | |
17347 | } | |
17348 | else | |
17349 | { | |
17350 | if (reg == -1) | |
17351 | { | |
17352 | reg = modrm.rm; | |
17353 | USED_REX (REX_B); | |
17354 | if (rex & REX_B) | |
17355 | reg += 8; | |
17356 | } | |
17357 | else if (reg > 7 && address_mode != mode_64bit) | |
17358 | BadOp (); | |
17359 | } | |
17360 | ||
17361 | switch (vex.length) | |
17362 | { | |
17363 | case 128: | |
b9733481 | 17364 | names = names_xmm; |
922d8de8 DR |
17365 | break; |
17366 | case 256: | |
b9733481 | 17367 | names = names_ymm; |
922d8de8 DR |
17368 | break; |
17369 | default: | |
17370 | abort (); | |
17371 | } | |
b9733481 | 17372 | oappend (names[reg]); |
922d8de8 DR |
17373 | } |
17374 | ||
a683cc34 SP |
17375 | static void |
17376 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17377 | { | |
17378 | int reg = -1; | |
17379 | static unsigned char vex_imm8; | |
17380 | ||
17381 | if (vex_w_done == 0) | |
17382 | { | |
17383 | vex_w_done = 1; | |
17384 | ||
17385 | /* Skip mod/rm byte. */ | |
17386 | MODRM_CHECK; | |
17387 | codep++; | |
17388 | ||
17389 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17390 | ||
17391 | if (vex.w) | |
17392 | reg = vex_imm8 >> 4; | |
17393 | ||
17394 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17395 | } | |
17396 | else if (vex_w_done == 1) | |
17397 | { | |
17398 | vex_w_done = 2; | |
17399 | ||
17400 | if (!vex.w) | |
17401 | reg = vex_imm8 >> 4; | |
17402 | ||
17403 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17404 | } | |
17405 | else | |
17406 | { | |
17407 | /* Output the imm8 directly. */ | |
17408 | scratchbuf[0] = '$'; | |
17409 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17410 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17411 | scratchbuf[0] = '\0'; |
17412 | codep++; | |
17413 | } | |
17414 | } | |
17415 | ||
5dd85c99 SP |
17416 | static void |
17417 | OP_Vex_2src (int bytemode, int sizeflag) | |
17418 | { | |
17419 | if (modrm.mod == 3) | |
17420 | { | |
b9733481 | 17421 | int reg = modrm.rm; |
5dd85c99 | 17422 | USED_REX (REX_B); |
b9733481 L |
17423 | if (rex & REX_B) |
17424 | reg += 8; | |
17425 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17426 | } |
17427 | else | |
17428 | { | |
17429 | if (intel_syntax | |
17430 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17431 | { | |
17432 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17433 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17434 | } | |
17435 | OP_E (bytemode, sizeflag); | |
17436 | } | |
17437 | } | |
17438 | ||
17439 | static void | |
17440 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17441 | { | |
17442 | if (modrm.mod == 3) | |
17443 | { | |
17444 | /* Skip mod/rm byte. */ | |
17445 | MODRM_CHECK; | |
17446 | codep++; | |
17447 | } | |
17448 | ||
17449 | if (vex.w) | |
b9733481 | 17450 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17451 | else |
17452 | OP_Vex_2src (bytemode, sizeflag); | |
17453 | } | |
17454 | ||
17455 | static void | |
17456 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17457 | { | |
17458 | if (vex.w) | |
17459 | OP_Vex_2src (bytemode, sizeflag); | |
17460 | else | |
b9733481 | 17461 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17462 | } |
17463 | ||
922d8de8 DR |
17464 | static void |
17465 | OP_EX_VexW (int bytemode, int sizeflag) | |
17466 | { | |
17467 | int reg = -1; | |
17468 | ||
17469 | if (!vex_w_done) | |
17470 | { | |
17471 | vex_w_done = 1; | |
41effecb SP |
17472 | |
17473 | /* Skip mod/rm byte. */ | |
17474 | MODRM_CHECK; | |
17475 | codep++; | |
17476 | ||
922d8de8 | 17477 | if (vex.w) |
ccc5981b | 17478 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17479 | } |
17480 | else | |
17481 | { | |
17482 | if (!vex.w) | |
ccc5981b | 17483 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17484 | } |
17485 | ||
17486 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17487 | } | |
17488 | ||
922d8de8 DR |
17489 | static void |
17490 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17491 | int sizeflag ATTRIBUTE_UNUSED) | |
17492 | { | |
17493 | /* Skip the immediate byte and check for invalid bits. */ | |
17494 | FETCH_DATA (the_info, codep + 1); | |
17495 | if (*codep++ & 0xf) | |
17496 | BadOp (); | |
17497 | } | |
17498 | ||
c0f3af97 L |
17499 | static void |
17500 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17501 | { | |
17502 | int reg; | |
b9733481 L |
17503 | const char **names; |
17504 | ||
c0f3af97 L |
17505 | FETCH_DATA (the_info, codep + 1); |
17506 | reg = *codep++; | |
17507 | ||
17508 | if (bytemode != x_mode) | |
17509 | abort (); | |
17510 | ||
17511 | if (reg & 0xf) | |
17512 | BadOp (); | |
17513 | ||
17514 | reg >>= 4; | |
dae39acc L |
17515 | if (reg > 7 && address_mode != mode_64bit) |
17516 | BadOp (); | |
17517 | ||
c0f3af97 L |
17518 | switch (vex.length) |
17519 | { | |
17520 | case 128: | |
b9733481 | 17521 | names = names_xmm; |
c0f3af97 L |
17522 | break; |
17523 | case 256: | |
b9733481 | 17524 | names = names_ymm; |
c0f3af97 L |
17525 | break; |
17526 | default: | |
17527 | abort (); | |
17528 | } | |
b9733481 | 17529 | oappend (names[reg]); |
c0f3af97 L |
17530 | } |
17531 | ||
922d8de8 DR |
17532 | static void |
17533 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17534 | { | |
17535 | /* Turn off the REX.W bit since it is used for swapping operands | |
17536 | now. */ | |
17537 | rex &= ~REX_W; | |
17538 | OP_XMM (bytemode, sizeflag); | |
17539 | } | |
17540 | ||
c0f3af97 L |
17541 | static void |
17542 | OP_EX_Vex (int bytemode, int sizeflag) | |
17543 | { | |
17544 | if (modrm.mod != 3) | |
17545 | { | |
17546 | if (vex.register_specifier != 0) | |
17547 | BadOp (); | |
17548 | need_vex_reg = 0; | |
17549 | } | |
17550 | OP_EX (bytemode, sizeflag); | |
17551 | } | |
17552 | ||
17553 | static void | |
17554 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17555 | { | |
17556 | if (modrm.mod != 3) | |
17557 | { | |
17558 | if (vex.register_specifier != 0) | |
17559 | BadOp (); | |
17560 | need_vex_reg = 0; | |
17561 | } | |
17562 | OP_XMM (bytemode, sizeflag); | |
17563 | } | |
17564 | ||
17565 | static void | |
17566 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17567 | { | |
17568 | switch (vex.length) | |
17569 | { | |
17570 | case 128: | |
ea397f5b | 17571 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17572 | break; |
17573 | case 256: | |
ea397f5b | 17574 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17575 | break; |
17576 | default: | |
17577 | abort (); | |
17578 | } | |
17579 | } | |
17580 | ||
ea397f5b L |
17581 | static struct op vex_cmp_op[] = |
17582 | { | |
17583 | { STRING_COMMA_LEN ("eq") }, | |
17584 | { STRING_COMMA_LEN ("lt") }, | |
17585 | { STRING_COMMA_LEN ("le") }, | |
17586 | { STRING_COMMA_LEN ("unord") }, | |
17587 | { STRING_COMMA_LEN ("neq") }, | |
17588 | { STRING_COMMA_LEN ("nlt") }, | |
17589 | { STRING_COMMA_LEN ("nle") }, | |
17590 | { STRING_COMMA_LEN ("ord") }, | |
17591 | { STRING_COMMA_LEN ("eq_uq") }, | |
17592 | { STRING_COMMA_LEN ("nge") }, | |
17593 | { STRING_COMMA_LEN ("ngt") }, | |
17594 | { STRING_COMMA_LEN ("false") }, | |
17595 | { STRING_COMMA_LEN ("neq_oq") }, | |
17596 | { STRING_COMMA_LEN ("ge") }, | |
17597 | { STRING_COMMA_LEN ("gt") }, | |
17598 | { STRING_COMMA_LEN ("true") }, | |
17599 | { STRING_COMMA_LEN ("eq_os") }, | |
17600 | { STRING_COMMA_LEN ("lt_oq") }, | |
17601 | { STRING_COMMA_LEN ("le_oq") }, | |
17602 | { STRING_COMMA_LEN ("unord_s") }, | |
17603 | { STRING_COMMA_LEN ("neq_us") }, | |
17604 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17605 | { STRING_COMMA_LEN ("nle_uq") }, | |
17606 | { STRING_COMMA_LEN ("ord_s") }, | |
17607 | { STRING_COMMA_LEN ("eq_us") }, | |
17608 | { STRING_COMMA_LEN ("nge_uq") }, | |
17609 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17610 | { STRING_COMMA_LEN ("false_os") }, | |
17611 | { STRING_COMMA_LEN ("neq_os") }, | |
17612 | { STRING_COMMA_LEN ("ge_oq") }, | |
17613 | { STRING_COMMA_LEN ("gt_oq") }, | |
17614 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17615 | }; |
17616 | ||
17617 | static void | |
17618 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17619 | { | |
17620 | unsigned int cmp_type; | |
17621 | ||
17622 | FETCH_DATA (the_info, codep + 1); | |
17623 | cmp_type = *codep++ & 0xff; | |
17624 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17625 | { | |
17626 | char suffix [3]; | |
ea397f5b | 17627 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17628 | suffix[0] = p[0]; |
17629 | suffix[1] = p[1]; | |
17630 | suffix[2] = '\0'; | |
ea397f5b L |
17631 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17632 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17633 | } |
17634 | else | |
17635 | { | |
17636 | /* We have a reserved extension byte. Output it directly. */ | |
17637 | scratchbuf[0] = '$'; | |
17638 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17639 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17640 | scratchbuf[0] = '\0'; |
17641 | } | |
17642 | } | |
17643 | ||
43234a1e L |
17644 | static void |
17645 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17646 | int sizeflag ATTRIBUTE_UNUSED) | |
17647 | { | |
17648 | unsigned int cmp_type; | |
17649 | ||
17650 | if (!vex.evex) | |
17651 | abort (); | |
17652 | ||
17653 | FETCH_DATA (the_info, codep + 1); | |
17654 | cmp_type = *codep++ & 0xff; | |
17655 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17656 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17657 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17658 | && cmp_type != 3 | |
17659 | && cmp_type != 7) | |
17660 | { | |
17661 | char suffix [3]; | |
17662 | char *p = mnemonicendp - 2; | |
17663 | ||
17664 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17665 | if (p[0] == 'p') | |
17666 | { | |
17667 | p++; | |
17668 | suffix[0] = p[0]; | |
17669 | suffix[1] = '\0'; | |
17670 | } | |
17671 | else | |
17672 | { | |
17673 | suffix[0] = p[0]; | |
17674 | suffix[1] = p[1]; | |
17675 | suffix[2] = '\0'; | |
17676 | } | |
17677 | ||
17678 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17679 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17680 | } | |
17681 | else | |
17682 | { | |
17683 | /* We have a reserved extension byte. Output it directly. */ | |
17684 | scratchbuf[0] = '$'; | |
17685 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17686 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17687 | scratchbuf[0] = '\0'; |
17688 | } | |
17689 | } | |
17690 | ||
ea397f5b L |
17691 | static const struct op pclmul_op[] = |
17692 | { | |
17693 | { STRING_COMMA_LEN ("lql") }, | |
17694 | { STRING_COMMA_LEN ("hql") }, | |
17695 | { STRING_COMMA_LEN ("lqh") }, | |
17696 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17697 | }; |
17698 | ||
17699 | static void | |
17700 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17701 | int sizeflag ATTRIBUTE_UNUSED) | |
17702 | { | |
17703 | unsigned int pclmul_type; | |
17704 | ||
17705 | FETCH_DATA (the_info, codep + 1); | |
17706 | pclmul_type = *codep++ & 0xff; | |
17707 | switch (pclmul_type) | |
17708 | { | |
17709 | case 0x10: | |
17710 | pclmul_type = 2; | |
17711 | break; | |
17712 | case 0x11: | |
17713 | pclmul_type = 3; | |
17714 | break; | |
17715 | default: | |
17716 | break; | |
7bb15c6f | 17717 | } |
c0f3af97 L |
17718 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17719 | { | |
17720 | char suffix [4]; | |
ea397f5b | 17721 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17722 | suffix[0] = p[0]; |
17723 | suffix[1] = p[1]; | |
17724 | suffix[2] = p[2]; | |
17725 | suffix[3] = '\0'; | |
ea397f5b L |
17726 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17727 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17728 | } |
17729 | else | |
17730 | { | |
17731 | /* We have a reserved extension byte. Output it directly. */ | |
17732 | scratchbuf[0] = '$'; | |
17733 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17734 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17735 | scratchbuf[0] = '\0'; |
17736 | } | |
17737 | } | |
17738 | ||
f1f8f695 L |
17739 | static void |
17740 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17741 | { | |
17742 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17743 | char *p = mnemonicendp; |
f1f8f695 L |
17744 | |
17745 | switch (bytemode) | |
17746 | { | |
17747 | case v_mode: | |
17748 | if (intel_syntax) | |
ea397f5b | 17749 | goto skip; |
f1f8f695 L |
17750 | |
17751 | USED_REX (REX_W); | |
17752 | if (sizeflag & SUFFIX_ALWAYS) | |
17753 | { | |
17754 | if (rex & REX_W) | |
17755 | *p++ = 'q'; | |
f1f8f695 | 17756 | else |
f16cd0d5 L |
17757 | { |
17758 | if (sizeflag & DFLAG) | |
17759 | *p++ = 'l'; | |
17760 | else | |
17761 | *p++ = 'w'; | |
17762 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17763 | } | |
f1f8f695 | 17764 | } |
f1f8f695 L |
17765 | break; |
17766 | default: | |
17767 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17768 | break; | |
17769 | } | |
ea397f5b | 17770 | mnemonicendp = p; |
f1f8f695 L |
17771 | *p = '\0'; |
17772 | ||
ea397f5b | 17773 | skip: |
f1f8f695 L |
17774 | OP_M (bytemode, sizeflag); |
17775 | } | |
f88c9eb0 SP |
17776 | |
17777 | static void | |
17778 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17779 | { | |
17780 | int reg; | |
17781 | const char **names; | |
17782 | ||
17783 | /* Skip mod/rm byte. */ | |
17784 | MODRM_CHECK; | |
17785 | codep++; | |
17786 | ||
17787 | if (vex.w) | |
17788 | names = names64; | |
f88c9eb0 | 17789 | else |
ce7d077e | 17790 | names = names32; |
f88c9eb0 SP |
17791 | |
17792 | reg = modrm.rm; | |
17793 | USED_REX (REX_B); | |
17794 | if (rex & REX_B) | |
17795 | reg += 8; | |
17796 | ||
17797 | oappend (names[reg]); | |
17798 | } | |
17799 | ||
17800 | static void | |
17801 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17802 | { | |
17803 | const char **names; | |
17804 | ||
17805 | if (vex.w) | |
17806 | names = names64; | |
f88c9eb0 | 17807 | else |
ce7d077e | 17808 | names = names32; |
f88c9eb0 SP |
17809 | |
17810 | oappend (names[vex.register_specifier]); | |
17811 | } | |
43234a1e L |
17812 | |
17813 | static void | |
17814 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17815 | { | |
17816 | if (!vex.evex | |
1ba585e8 | 17817 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17818 | abort (); |
17819 | ||
17820 | USED_REX (REX_R); | |
17821 | if ((rex & REX_R) != 0 || !vex.r) | |
17822 | { | |
17823 | BadOp (); | |
17824 | return; | |
17825 | } | |
17826 | ||
17827 | oappend (names_mask [modrm.reg]); | |
17828 | } | |
17829 | ||
17830 | static void | |
17831 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17832 | { | |
17833 | if (!vex.evex | |
17834 | || (bytemode != evex_rounding_mode | |
17835 | && bytemode != evex_sae_mode)) | |
17836 | abort (); | |
17837 | if (modrm.mod == 3 && vex.b) | |
17838 | switch (bytemode) | |
17839 | { | |
17840 | case evex_rounding_mode: | |
17841 | oappend (names_rounding[vex.ll]); | |
17842 | break; | |
17843 | case evex_sae_mode: | |
17844 | oappend ("{sae}"); | |
17845 | break; | |
17846 | default: | |
17847 | break; | |
17848 | } | |
17849 | } |