Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 | 90 | static void OP_VEX (int, int); |
41f5efc6 | 91 | static void OP_VexR (int, int); |
e6123d0c | 92 | static void OP_VexW (int, int); |
43234a1e | 93 | static void OP_Rounding (int, int); |
c0f3af97 | 94 | static void OP_REG_VexI4 (int, int); |
93abb146 | 95 | static void OP_VexI4 (int, int); |
c0f3af97 | 96 | static void PCLMUL_Fixup (int, int); |
43234a1e | 97 | static void VPCMP_Fixup (int, int); |
be92cb14 | 98 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 99 | static void OP_0f07 (int, int); |
b844680a L |
100 | static void OP_Monitor (int, int); |
101 | static void OP_Mwait (int, int); | |
46e883c5 L |
102 | static void NOP_Fixup1 (int, int); |
103 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 104 | static void OP_3DNowSuffix (int, int); |
ad19981d | 105 | static void CMP_Fixup (int, int); |
26ca5450 | 106 | static void BadOp (void); |
35c52694 | 107 | static void REP_Fixup (int, int); |
d835a58b | 108 | static void SEP_Fixup (int, int); |
7e8b059b | 109 | static void BND_Fixup (int, int); |
04ef582a | 110 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
111 | static void HLE_Fixup1 (int, int); |
112 | static void HLE_Fixup2 (int, int); | |
113 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 114 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 115 | static void XMM_Fixup (int, int); |
eacc9c89 | 116 | static void FXSAVE_Fixup (int, int); |
c1e679ec | 117 | |
bc31405e | 118 | static void MOVSXD_Fixup (int, int); |
252b5132 | 119 | |
43234a1e L |
120 | static void OP_Mask (int, int); |
121 | ||
6608db57 | 122 | struct dis_private { |
252b5132 RH |
123 | /* Points to first byte not fetched. */ |
124 | bfd_byte *max_fetched; | |
0b1cf022 | 125 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 126 | bfd_vma insn_start; |
e396998b | 127 | int orig_sizeflag; |
8df14d78 | 128 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
129 | }; |
130 | ||
cb712a9e L |
131 | enum address_mode |
132 | { | |
133 | mode_16bit, | |
134 | mode_32bit, | |
135 | mode_64bit | |
136 | }; | |
137 | ||
138 | enum address_mode address_mode; | |
52b15da3 | 139 | |
5076851f ILT |
140 | /* Flags for the prefixes for the current instruction. See below. */ |
141 | static int prefixes; | |
142 | ||
52b15da3 JH |
143 | /* REX prefix the current instruction. See below. */ |
144 | static int rex; | |
145 | /* Bits of REX we've already used. */ | |
146 | static int rex_used; | |
52b15da3 JH |
147 | /* Mark parts used in the REX prefix. When we are testing for |
148 | empty prefix (for 8bit register REX extension), just mask it | |
149 | out. Otherwise test for REX bit is excuse for existence of REX | |
150 | only in case value is nonzero. */ | |
151 | #define USED_REX(value) \ | |
152 | { \ | |
153 | if (value) \ | |
161a04f6 L |
154 | { \ |
155 | if ((rex & value)) \ | |
156 | rex_used |= (value) | REX_OPCODE; \ | |
157 | } \ | |
52b15da3 | 158 | else \ |
161a04f6 | 159 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
160 | } |
161 | ||
7d421014 ILT |
162 | /* Flags for prefixes which we somehow handled when printing the |
163 | current instruction. */ | |
164 | static int used_prefixes; | |
165 | ||
5076851f ILT |
166 | /* Flags stored in PREFIXES. */ |
167 | #define PREFIX_REPZ 1 | |
168 | #define PREFIX_REPNZ 2 | |
169 | #define PREFIX_LOCK 4 | |
170 | #define PREFIX_CS 8 | |
171 | #define PREFIX_SS 0x10 | |
172 | #define PREFIX_DS 0x20 | |
173 | #define PREFIX_ES 0x40 | |
174 | #define PREFIX_FS 0x80 | |
175 | #define PREFIX_GS 0x100 | |
176 | #define PREFIX_DATA 0x200 | |
177 | #define PREFIX_ADDR 0x400 | |
178 | #define PREFIX_FWAIT 0x800 | |
179 | ||
252b5132 RH |
180 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
181 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
182 | on error. */ | |
183 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 184 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
185 | ? 1 : fetch_data ((info), (addr))) |
186 | ||
187 | static int | |
26ca5450 | 188 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
189 | { |
190 | int status; | |
6608db57 | 191 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
192 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
193 | ||
0b1cf022 | 194 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
195 | status = (*info->read_memory_func) (start, |
196 | priv->max_fetched, | |
197 | addr - priv->max_fetched, | |
198 | info); | |
199 | else | |
200 | status = -1; | |
252b5132 RH |
201 | if (status != 0) |
202 | { | |
7d421014 | 203 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
204 | print_insn_i386 will do something sensible. Otherwise, print |
205 | an error. We do that here because this is where we know | |
206 | STATUS. */ | |
7d421014 | 207 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 208 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 209 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
210 | } |
211 | else | |
212 | priv->max_fetched = addr; | |
213 | return 1; | |
214 | } | |
215 | ||
bf890a93 | 216 | /* Possible values for prefix requirement. */ |
507bd325 L |
217 | #define PREFIX_IGNORED_SHIFT 16 |
218 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
219 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
220 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
221 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
222 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
223 | ||
224 | /* Opcode prefixes. */ | |
225 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
226 | | PREFIX_REPNZ \ | |
227 | | PREFIX_DATA) | |
228 | ||
229 | /* Prefixes ignored. */ | |
230 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
231 | | PREFIX_IGNORED_REPNZ \ | |
232 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 233 | |
ce518a5f | 234 | #define XX { NULL, 0 } |
507bd325 | 235 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
236 | |
237 | #define Eb { OP_E, b_mode } | |
7e8b059b | 238 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 239 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 240 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 241 | #define Ev { OP_E, v_mode } |
de89d0a3 | 242 | #define Eva { OP_E, va_mode } |
7e8b059b | 243 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 244 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
245 | #define Ed { OP_E, d_mode } |
246 | #define Edq { OP_E, dq_mode } | |
247 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 248 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
249 | #define Edb { OP_E, db_mode } |
250 | #define Edw { OP_E, dw_mode } | |
42903f7f | 251 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 252 | #define Eq { OP_E, q_mode } |
07f5af7d | 253 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
254 | #define indirEp { OP_indirE, f_mode } |
255 | #define stackEv { OP_E, stack_v_mode } | |
256 | #define Em { OP_E, m_mode } | |
257 | #define Ew { OP_E, w_mode } | |
258 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 259 | #define Ma { OP_M, a_mode } |
b844680a | 260 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 261 | #define Md { OP_M, d_mode } |
f1f8f695 | 262 | #define Mo { OP_M, o_mode } |
ce518a5f L |
263 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
264 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 265 | #define Mv { OP_M, v_mode } |
d276ec69 | 266 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 267 | #define Mx { OP_M, x_mode } |
c0f3af97 | 268 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 269 | #define Gb { OP_G, b_mode } |
7e8b059b | 270 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
271 | #define Gv { OP_G, v_mode } |
272 | #define Gd { OP_G, d_mode } | |
273 | #define Gdq { OP_G, dq_mode } | |
274 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 275 | #define Gva { OP_G, va_mode } |
ce518a5f | 276 | #define Gw { OP_G, w_mode } |
6f74c397 | 277 | #define Rd { OP_R, d_mode } |
43234a1e | 278 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 279 | #define Rm { OP_R, m_mode } |
ce518a5f L |
280 | #define Ib { OP_I, b_mode } |
281 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 282 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 283 | #define Iv { OP_I, v_mode } |
7bb15c6f | 284 | #define sIv { OP_sI, v_mode } |
ce518a5f | 285 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 286 | #define Id { OP_I, d_mode } |
ce518a5f L |
287 | #define Iw { OP_I, w_mode } |
288 | #define I1 { OP_I, const_1_mode } | |
289 | #define Jb { OP_J, b_mode } | |
290 | #define Jv { OP_J, v_mode } | |
376cd056 | 291 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
292 | #define Cm { OP_C, m_mode } |
293 | #define Dm { OP_D, m_mode } | |
294 | #define Td { OP_T, d_mode } | |
b844680a | 295 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
296 | |
297 | #define RMeAX { OP_REG, eAX_reg } | |
298 | #define RMeBX { OP_REG, eBX_reg } | |
299 | #define RMeCX { OP_REG, eCX_reg } | |
300 | #define RMeDX { OP_REG, eDX_reg } | |
301 | #define RMeSP { OP_REG, eSP_reg } | |
302 | #define RMeBP { OP_REG, eBP_reg } | |
303 | #define RMeSI { OP_REG, eSI_reg } | |
304 | #define RMeDI { OP_REG, eDI_reg } | |
305 | #define RMrAX { OP_REG, rAX_reg } | |
306 | #define RMrBX { OP_REG, rBX_reg } | |
307 | #define RMrCX { OP_REG, rCX_reg } | |
308 | #define RMrDX { OP_REG, rDX_reg } | |
309 | #define RMrSP { OP_REG, rSP_reg } | |
310 | #define RMrBP { OP_REG, rBP_reg } | |
311 | #define RMrSI { OP_REG, rSI_reg } | |
312 | #define RMrDI { OP_REG, rDI_reg } | |
313 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
314 | #define RMCL { OP_REG, cl_reg } |
315 | #define RMDL { OP_REG, dl_reg } | |
316 | #define RMBL { OP_REG, bl_reg } | |
317 | #define RMAH { OP_REG, ah_reg } | |
318 | #define RMCH { OP_REG, ch_reg } | |
319 | #define RMDH { OP_REG, dh_reg } | |
320 | #define RMBH { OP_REG, bh_reg } | |
321 | #define RMAX { OP_REG, ax_reg } | |
322 | #define RMDX { OP_REG, dx_reg } | |
323 | ||
324 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
325 | #define AL { OP_IMREG, al_reg } |
326 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
327 | #define zAX { OP_IMREG, z_mode_ax_reg } |
328 | #define indirDX { OP_IMREG, indir_dx_reg } | |
329 | ||
330 | #define Sw { OP_SEG, w_mode } | |
331 | #define Sv { OP_SEG, v_mode } | |
332 | #define Ap { OP_DIR, 0 } | |
333 | #define Ob { OP_OFF64, b_mode } | |
334 | #define Ov { OP_OFF64, v_mode } | |
335 | #define Xb { OP_DSreg, eSI_reg } | |
336 | #define Xv { OP_DSreg, eSI_reg } | |
337 | #define Xz { OP_DSreg, eSI_reg } | |
338 | #define Yb { OP_ESreg, eDI_reg } | |
339 | #define Yv { OP_ESreg, eDI_reg } | |
340 | #define DSBX { OP_DSreg, eBX_reg } | |
341 | ||
342 | #define es { OP_REG, es_reg } | |
343 | #define ss { OP_REG, ss_reg } | |
344 | #define cs { OP_REG, cs_reg } | |
345 | #define ds { OP_REG, ds_reg } | |
346 | #define fs { OP_REG, fs_reg } | |
347 | #define gs { OP_REG, gs_reg } | |
348 | ||
349 | #define MX { OP_MMX, 0 } | |
350 | #define XM { OP_XMM, 0 } | |
539f890d | 351 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 352 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 353 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 354 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 355 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 356 | #define EM { OP_EM, v_mode } |
b6169b20 | 357 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 358 | #define EMd { OP_EM, d_mode } |
14051056 | 359 | #define EMx { OP_EM, x_mode } |
4726e9a4 | 360 | #define EXbwUnit { OP_EX, bw_unit_mode } |
8976381e | 361 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 362 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 363 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 364 | #define EXq { OP_EX, q_mode } |
b6169b20 | 365 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 366 | #define EXx { OP_EX, x_mode } |
b6169b20 | 367 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 368 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 369 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 370 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 371 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 372 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
373 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
374 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
375 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
376 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
377 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
378 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 379 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 380 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
381 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
382 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
383 | #define MS { OP_MS, v_mode } |
384 | #define XS { OP_XS, v_mode } | |
09335d05 | 385 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 386 | #define MXC { OP_MXC, 0 } |
ce518a5f | 387 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 388 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 389 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 390 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 391 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 392 | |
c0f3af97 | 393 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 394 | #define VexW { OP_VexW, vex_mode } |
539f890d | 395 | #define VexScalar { OP_VEX, vex_scalar_mode } |
41f5efc6 | 396 | #define VexScalarR { OP_VexR, vex_scalar_mode } |
6c30d220 | 397 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
cb21baef | 398 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 399 | #define VexTmm { OP_VEX, tmm_mode } |
c0f3af97 | 400 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 401 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 402 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 403 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 404 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 405 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
406 | |
407 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 408 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
409 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
410 | ||
411 | #define XMask { OP_Mask, mask_mode } | |
412 | #define MaskG { OP_G, mask_mode } | |
413 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 414 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
415 | #define MaskR { OP_R, mask_mode } |
416 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 417 | |
6c30d220 | 418 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 419 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 420 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 421 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 422 | |
260cd341 LC |
423 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
424 | ||
35c52694 | 425 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
426 | #define Xbr { REP_Fixup, eSI_reg } |
427 | #define Xvr { REP_Fixup, eSI_reg } | |
428 | #define Ybr { REP_Fixup, eDI_reg } | |
429 | #define Yvr { REP_Fixup, eDI_reg } | |
430 | #define Yzr { REP_Fixup, eDI_reg } | |
431 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
432 | #define ALr { REP_Fixup, al_reg } | |
433 | #define eAXr { REP_Fixup, eAX_reg } | |
434 | ||
42164a71 L |
435 | /* Used handle HLE prefix for lockable instructions. */ |
436 | #define Ebh1 { HLE_Fixup1, b_mode } | |
437 | #define Evh1 { HLE_Fixup1, v_mode } | |
438 | #define Ebh2 { HLE_Fixup2, b_mode } | |
439 | #define Evh2 { HLE_Fixup2, v_mode } | |
440 | #define Ebh3 { HLE_Fixup3, b_mode } | |
441 | #define Evh3 { HLE_Fixup3, v_mode } | |
442 | ||
7e8b059b | 443 | #define BND { BND_Fixup, 0 } |
04ef582a | 444 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 445 | |
ce518a5f L |
446 | #define cond_jump_flag { NULL, cond_jump_mode } |
447 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 448 | |
252b5132 | 449 | /* bits in sizeflag */ |
252b5132 | 450 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
451 | #define AFLAG 2 |
452 | #define DFLAG 1 | |
453 | ||
51e7da1b L |
454 | enum |
455 | { | |
456 | /* byte operand */ | |
457 | b_mode = 1, | |
458 | /* byte operand with operand swapped */ | |
3873ba12 | 459 | b_swap_mode, |
e3949f17 L |
460 | /* byte operand, sign extend like 'T' suffix */ |
461 | b_T_mode, | |
51e7da1b | 462 | /* operand size depends on prefixes */ |
3873ba12 | 463 | v_mode, |
51e7da1b | 464 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 465 | v_swap_mode, |
de89d0a3 IT |
466 | /* operand size depends on address prefix */ |
467 | va_mode, | |
51e7da1b | 468 | /* word operand */ |
3873ba12 | 469 | w_mode, |
51e7da1b | 470 | /* double word operand */ |
3873ba12 | 471 | d_mode, |
51e7da1b | 472 | /* double word operand with operand swapped */ |
3873ba12 | 473 | d_swap_mode, |
51e7da1b | 474 | /* quad word operand */ |
3873ba12 | 475 | q_mode, |
51e7da1b | 476 | /* quad word operand with operand swapped */ |
3873ba12 | 477 | q_swap_mode, |
51e7da1b | 478 | /* ten-byte operand */ |
3873ba12 | 479 | t_mode, |
43234a1e L |
480 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
481 | broadcast enabled. */ | |
3873ba12 | 482 | x_mode, |
43234a1e L |
483 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
484 | evex_x_gscat_mode, | |
4726e9a4 JB |
485 | /* Similar to x_mode, but with yet different EVEX mem shifts. */ |
486 | bw_unit_mode, | |
43234a1e L |
487 | /* Similar to x_mode, but with disabled broadcast. */ |
488 | evex_x_nobcst_mode, | |
489 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
490 | in EVEX. */ | |
3873ba12 | 491 | x_swap_mode, |
51e7da1b | 492 | /* 16-byte XMM operand */ |
3873ba12 | 493 | xmm_mode, |
43234a1e L |
494 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
495 | memory operand (depending on vector length). Broadcast isn't | |
496 | allowed. */ | |
3873ba12 | 497 | xmmq_mode, |
43234a1e L |
498 | /* Same as xmmq_mode, but broadcast is allowed. */ |
499 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
500 | /* XMM register or byte memory operand */ |
501 | xmm_mb_mode, | |
502 | /* XMM register or word memory operand */ | |
503 | xmm_mw_mode, | |
504 | /* XMM register or double word memory operand */ | |
505 | xmm_md_mode, | |
506 | /* XMM register or quad word memory operand */ | |
507 | xmm_mq_mode, | |
43234a1e | 508 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 509 | xmmdw_mode, |
43234a1e | 510 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 511 | xmmqd_mode, |
43234a1e L |
512 | /* 32-byte YMM operand */ |
513 | ymm_mode, | |
514 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 515 | ymmq_mode, |
6c30d220 L |
516 | /* 32-byte YMM or 16-byte word operand */ |
517 | ymmxmm_mode, | |
260cd341 LC |
518 | /* TMM operand */ |
519 | tmm_mode, | |
51e7da1b | 520 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 521 | m_mode, |
51e7da1b | 522 | /* pair of v_mode operands */ |
3873ba12 L |
523 | a_mode, |
524 | cond_jump_mode, | |
525 | loop_jcxz_mode, | |
bc31405e | 526 | movsxd_mode, |
7e8b059b | 527 | v_bnd_mode, |
d276ec69 JB |
528 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
529 | v_bndmk_mode, | |
51e7da1b | 530 | /* operand size depends on REX prefixes. */ |
3873ba12 | 531 | dq_mode, |
376cd056 JB |
532 | /* registers like dq_mode, memory like w_mode, displacements like |
533 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 534 | dqw_mode, |
9f79e886 | 535 | /* bounds operand */ |
7e8b059b | 536 | bnd_mode, |
9f79e886 JB |
537 | /* bounds operand with operand swapped */ |
538 | bnd_swap_mode, | |
51e7da1b | 539 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
540 | f_mode, |
541 | const_1_mode, | |
07f5af7d L |
542 | /* v_mode for indirect branch opcodes. */ |
543 | indir_v_mode, | |
51e7da1b | 544 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 545 | stack_v_mode, |
51e7da1b | 546 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 547 | z_mode, |
51e7da1b | 548 | /* 16-byte operand */ |
3873ba12 | 549 | o_mode, |
51e7da1b | 550 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 551 | dqb_mode, |
1ba585e8 IT |
552 | /* registers like d_mode, memory like b_mode. */ |
553 | db_mode, | |
554 | /* registers like d_mode, memory like w_mode. */ | |
555 | dw_mode, | |
51e7da1b | 556 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 557 | dqd_mode, |
51e7da1b | 558 | /* normal vex mode */ |
3873ba12 | 559 | vex_mode, |
d55ee72f | 560 | |
825bd36c | 561 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 562 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
563 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
564 | vex_vsib_d_w_d_mode, | |
825bd36c | 565 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 566 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
567 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
568 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
569 | /* mandatory non-vector SIB. */ |
570 | vex_sibmem_mode, | |
6c30d220 | 571 | |
539f890d L |
572 | /* scalar, ignore vector length. */ |
573 | scalar_mode, | |
539f890d L |
574 | /* like vex_mode, ignore vector length. */ |
575 | vex_scalar_mode, | |
825bd36c | 576 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 577 | vex_scalar_w_dq_mode, |
539f890d | 578 | |
43234a1e L |
579 | /* Static rounding. */ |
580 | evex_rounding_mode, | |
70df6fc9 L |
581 | /* Static rounding, 64-bit mode only. */ |
582 | evex_rounding_64_mode, | |
43234a1e L |
583 | /* Supress all exceptions. */ |
584 | evex_sae_mode, | |
585 | ||
586 | /* Mask register operand. */ | |
587 | mask_mode, | |
1ba585e8 IT |
588 | /* Mask register operand. */ |
589 | mask_bd_mode, | |
43234a1e | 590 | |
3873ba12 L |
591 | es_reg, |
592 | cs_reg, | |
593 | ss_reg, | |
594 | ds_reg, | |
595 | fs_reg, | |
596 | gs_reg, | |
d55ee72f | 597 | |
3873ba12 L |
598 | eAX_reg, |
599 | eCX_reg, | |
600 | eDX_reg, | |
601 | eBX_reg, | |
602 | eSP_reg, | |
603 | eBP_reg, | |
604 | eSI_reg, | |
605 | eDI_reg, | |
d55ee72f | 606 | |
3873ba12 L |
607 | al_reg, |
608 | cl_reg, | |
609 | dl_reg, | |
610 | bl_reg, | |
611 | ah_reg, | |
612 | ch_reg, | |
613 | dh_reg, | |
614 | bh_reg, | |
d55ee72f | 615 | |
3873ba12 L |
616 | ax_reg, |
617 | cx_reg, | |
618 | dx_reg, | |
619 | bx_reg, | |
620 | sp_reg, | |
621 | bp_reg, | |
622 | si_reg, | |
623 | di_reg, | |
d55ee72f | 624 | |
3873ba12 L |
625 | rAX_reg, |
626 | rCX_reg, | |
627 | rDX_reg, | |
628 | rBX_reg, | |
629 | rSP_reg, | |
630 | rBP_reg, | |
631 | rSI_reg, | |
632 | rDI_reg, | |
d55ee72f | 633 | |
3873ba12 L |
634 | z_mode_ax_reg, |
635 | indir_dx_reg | |
51e7da1b | 636 | }; |
252b5132 | 637 | |
51e7da1b L |
638 | enum |
639 | { | |
640 | FLOATCODE = 1, | |
3873ba12 L |
641 | USE_REG_TABLE, |
642 | USE_MOD_TABLE, | |
643 | USE_RM_TABLE, | |
644 | USE_PREFIX_TABLE, | |
645 | USE_X86_64_TABLE, | |
646 | USE_3BYTE_TABLE, | |
f88c9eb0 | 647 | USE_XOP_8F_TABLE, |
3873ba12 L |
648 | USE_VEX_C4_TABLE, |
649 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 650 | USE_VEX_LEN_TABLE, |
43234a1e | 651 | USE_VEX_W_TABLE, |
04e2a182 L |
652 | USE_EVEX_TABLE, |
653 | USE_EVEX_LEN_TABLE | |
51e7da1b | 654 | }; |
6439fc28 | 655 | |
bf890a93 | 656 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 657 | |
bf890a93 IT |
658 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
659 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
660 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
661 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
662 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
663 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
664 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
665 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 666 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 667 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
668 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
669 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
670 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 671 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 672 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 673 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 674 | |
51e7da1b L |
675 | enum |
676 | { | |
677 | REG_80 = 0, | |
3873ba12 | 678 | REG_81, |
7148c369 | 679 | REG_83, |
3873ba12 L |
680 | REG_8F, |
681 | REG_C0, | |
682 | REG_C1, | |
683 | REG_C6, | |
684 | REG_C7, | |
685 | REG_D0, | |
686 | REG_D1, | |
687 | REG_D2, | |
688 | REG_D3, | |
689 | REG_F6, | |
690 | REG_F7, | |
691 | REG_FE, | |
692 | REG_FF, | |
693 | REG_0F00, | |
694 | REG_0F01, | |
695 | REG_0F0D, | |
696 | REG_0F18, | |
f8687e93 JB |
697 | REG_0F1C_P_0_MOD_0, |
698 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
699 | REG_0F71, |
700 | REG_0F72, | |
701 | REG_0F73, | |
702 | REG_0FA6, | |
703 | REG_0FA7, | |
704 | REG_0FAE, | |
705 | REG_0FBA, | |
706 | REG_0FC7, | |
592a252b L |
707 | REG_VEX_0F71, |
708 | REG_VEX_0F72, | |
709 | REG_VEX_0F73, | |
710 | REG_VEX_0FAE, | |
260cd341 | 711 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 712 | REG_VEX_0F38F3, |
467bbef0 JB |
713 | |
714 | REG_0FXOP_09_01_L_0, | |
715 | REG_0FXOP_09_02_L_0, | |
716 | REG_0FXOP_09_12_M_1_L_0, | |
717 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 718 | |
1ba585e8 | 719 | REG_EVEX_0F71, |
43234a1e L |
720 | REG_EVEX_0F72, |
721 | REG_EVEX_0F73, | |
722 | REG_EVEX_0F38C6, | |
723 | REG_EVEX_0F38C7 | |
51e7da1b | 724 | }; |
1ceb70f8 | 725 | |
51e7da1b L |
726 | enum |
727 | { | |
728 | MOD_8D = 0, | |
42164a71 L |
729 | MOD_C6_REG_7, |
730 | MOD_C7_REG_7, | |
4a357820 MZ |
731 | MOD_FF_REG_3, |
732 | MOD_FF_REG_5, | |
3873ba12 L |
733 | MOD_0F01_REG_0, |
734 | MOD_0F01_REG_1, | |
735 | MOD_0F01_REG_2, | |
736 | MOD_0F01_REG_3, | |
8eab4136 | 737 | MOD_0F01_REG_5, |
3873ba12 L |
738 | MOD_0F01_REG_7, |
739 | MOD_0F12_PREFIX_0, | |
18897deb | 740 | MOD_0F12_PREFIX_2, |
3873ba12 L |
741 | MOD_0F13, |
742 | MOD_0F16_PREFIX_0, | |
18897deb | 743 | MOD_0F16_PREFIX_2, |
3873ba12 L |
744 | MOD_0F17, |
745 | MOD_0F18_REG_0, | |
746 | MOD_0F18_REG_1, | |
747 | MOD_0F18_REG_2, | |
748 | MOD_0F18_REG_3, | |
d7189fa5 RM |
749 | MOD_0F18_REG_4, |
750 | MOD_0F18_REG_5, | |
751 | MOD_0F18_REG_6, | |
752 | MOD_0F18_REG_7, | |
7e8b059b L |
753 | MOD_0F1A_PREFIX_0, |
754 | MOD_0F1B_PREFIX_0, | |
755 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 756 | MOD_0F1C_PREFIX_0, |
603555e5 | 757 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
758 | MOD_0F24, |
759 | MOD_0F26, | |
760 | MOD_0F2B_PREFIX_0, | |
761 | MOD_0F2B_PREFIX_1, | |
762 | MOD_0F2B_PREFIX_2, | |
763 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 764 | MOD_0F50, |
3873ba12 L |
765 | MOD_0F71_REG_2, |
766 | MOD_0F71_REG_4, | |
767 | MOD_0F71_REG_6, | |
768 | MOD_0F72_REG_2, | |
769 | MOD_0F72_REG_4, | |
770 | MOD_0F72_REG_6, | |
771 | MOD_0F73_REG_2, | |
772 | MOD_0F73_REG_3, | |
773 | MOD_0F73_REG_6, | |
774 | MOD_0F73_REG_7, | |
775 | MOD_0FAE_REG_0, | |
776 | MOD_0FAE_REG_1, | |
777 | MOD_0FAE_REG_2, | |
778 | MOD_0FAE_REG_3, | |
779 | MOD_0FAE_REG_4, | |
780 | MOD_0FAE_REG_5, | |
781 | MOD_0FAE_REG_6, | |
782 | MOD_0FAE_REG_7, | |
783 | MOD_0FB2, | |
784 | MOD_0FB4, | |
785 | MOD_0FB5, | |
a8484f96 | 786 | MOD_0FC3, |
963f3586 IT |
787 | MOD_0FC7_REG_3, |
788 | MOD_0FC7_REG_4, | |
789 | MOD_0FC7_REG_5, | |
3873ba12 L |
790 | MOD_0FC7_REG_6, |
791 | MOD_0FC7_REG_7, | |
792 | MOD_0FD7, | |
793 | MOD_0FE7_PREFIX_2, | |
794 | MOD_0FF0_PREFIX_3, | |
795 | MOD_0F382A_PREFIX_2, | |
260cd341 LC |
796 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
797 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
798 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
799 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
800 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
801 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
802 | MOD_VEX_0F385C_X86_64_P_1_W_0, | |
803 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
804 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
805 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
806 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
603555e5 L |
807 | MOD_0F38F5_PREFIX_2, |
808 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 809 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 810 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 811 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 812 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
813 | MOD_62_32BIT, |
814 | MOD_C4_32BIT, | |
815 | MOD_C5_32BIT, | |
592a252b | 816 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 817 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
818 | MOD_VEX_0F13, |
819 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 820 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
821 | MOD_VEX_0F17, |
822 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
823 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
824 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
825 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
826 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
827 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
828 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
829 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
830 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
831 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
832 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
833 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
834 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
835 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
836 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
837 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
838 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
839 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
840 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
841 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
842 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
843 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
844 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
845 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
846 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
847 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
848 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
849 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
850 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
851 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
852 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
853 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
854 | MOD_VEX_0F50, |
855 | MOD_VEX_0F71_REG_2, | |
856 | MOD_VEX_0F71_REG_4, | |
857 | MOD_VEX_0F71_REG_6, | |
858 | MOD_VEX_0F72_REG_2, | |
859 | MOD_VEX_0F72_REG_4, | |
860 | MOD_VEX_0F72_REG_6, | |
861 | MOD_VEX_0F73_REG_2, | |
862 | MOD_VEX_0F73_REG_3, | |
863 | MOD_VEX_0F73_REG_6, | |
864 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
865 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
866 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
867 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
868 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
869 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
870 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 871 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
872 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
873 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 874 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
875 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
876 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
877 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
878 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
879 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
880 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
881 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
882 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
883 | MOD_VEX_0FAE_REG_2, |
884 | MOD_VEX_0FAE_REG_3, | |
885 | MOD_VEX_0FD7_PREFIX_2, | |
886 | MOD_VEX_0FE7_PREFIX_2, | |
887 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
888 | MOD_VEX_0F381A_PREFIX_2, |
889 | MOD_VEX_0F382A_PREFIX_2, | |
890 | MOD_VEX_0F382C_PREFIX_2, | |
891 | MOD_VEX_0F382D_PREFIX_2, | |
892 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
893 | MOD_VEX_0F382F_PREFIX_2, |
894 | MOD_VEX_0F385A_PREFIX_2, | |
895 | MOD_VEX_0F388C_PREFIX_2, | |
896 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
897 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
898 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
899 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
900 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
901 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
902 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
903 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
904 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 905 | |
467bbef0 JB |
906 | MOD_VEX_0FXOP_09_12, |
907 | ||
43234a1e | 908 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
909 | MOD_EVEX_0F12_PREFIX_2, |
910 | MOD_EVEX_0F13, | |
43234a1e | 911 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
912 | MOD_EVEX_0F16_PREFIX_2, |
913 | MOD_EVEX_0F17, | |
914 | MOD_EVEX_0F2B, | |
bc152a17 JB |
915 | MOD_EVEX_0F381A_P_2_W_0, |
916 | MOD_EVEX_0F381A_P_2_W_1, | |
917 | MOD_EVEX_0F381B_P_2_W_0, | |
918 | MOD_EVEX_0F381B_P_2_W_1, | |
919 | MOD_EVEX_0F385A_P_2_W_0, | |
920 | MOD_EVEX_0F385A_P_2_W_1, | |
921 | MOD_EVEX_0F385B_P_2_W_0, | |
922 | MOD_EVEX_0F385B_P_2_W_1, | |
43234a1e L |
923 | MOD_EVEX_0F38C6_REG_1, |
924 | MOD_EVEX_0F38C6_REG_2, | |
925 | MOD_EVEX_0F38C6_REG_5, | |
926 | MOD_EVEX_0F38C6_REG_6, | |
927 | MOD_EVEX_0F38C7_REG_1, | |
928 | MOD_EVEX_0F38C7_REG_2, | |
929 | MOD_EVEX_0F38C7_REG_5, | |
930 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 931 | }; |
1ceb70f8 | 932 | |
51e7da1b L |
933 | enum |
934 | { | |
42164a71 L |
935 | RM_C6_REG_7 = 0, |
936 | RM_C7_REG_7, | |
937 | RM_0F01_REG_0, | |
3873ba12 L |
938 | RM_0F01_REG_1, |
939 | RM_0F01_REG_2, | |
940 | RM_0F01_REG_3, | |
f8687e93 JB |
941 | RM_0F01_REG_5_MOD_3, |
942 | RM_0F01_REG_7_MOD_3, | |
943 | RM_0F1E_P_1_MOD_3_REG_7, | |
944 | RM_0FAE_REG_6_MOD_3_P_0, | |
945 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 946 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 947 | }; |
1ceb70f8 | 948 | |
51e7da1b L |
949 | enum |
950 | { | |
951 | PREFIX_90 = 0, | |
a847e322 | 952 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
953 | PREFIX_0F01_REG_5_MOD_0, |
954 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 955 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 956 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
957 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
958 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 959 | PREFIX_0F09, |
3873ba12 L |
960 | PREFIX_0F10, |
961 | PREFIX_0F11, | |
962 | PREFIX_0F12, | |
963 | PREFIX_0F16, | |
7e8b059b L |
964 | PREFIX_0F1A, |
965 | PREFIX_0F1B, | |
c48935d7 | 966 | PREFIX_0F1C, |
603555e5 | 967 | PREFIX_0F1E, |
3873ba12 L |
968 | PREFIX_0F2A, |
969 | PREFIX_0F2B, | |
970 | PREFIX_0F2C, | |
971 | PREFIX_0F2D, | |
972 | PREFIX_0F2E, | |
973 | PREFIX_0F2F, | |
974 | PREFIX_0F51, | |
975 | PREFIX_0F52, | |
976 | PREFIX_0F53, | |
977 | PREFIX_0F58, | |
978 | PREFIX_0F59, | |
979 | PREFIX_0F5A, | |
980 | PREFIX_0F5B, | |
981 | PREFIX_0F5C, | |
982 | PREFIX_0F5D, | |
983 | PREFIX_0F5E, | |
984 | PREFIX_0F5F, | |
985 | PREFIX_0F60, | |
986 | PREFIX_0F61, | |
987 | PREFIX_0F62, | |
988 | PREFIX_0F6C, | |
989 | PREFIX_0F6D, | |
990 | PREFIX_0F6F, | |
991 | PREFIX_0F70, | |
992 | PREFIX_0F73_REG_3, | |
993 | PREFIX_0F73_REG_7, | |
994 | PREFIX_0F78, | |
995 | PREFIX_0F79, | |
996 | PREFIX_0F7C, | |
997 | PREFIX_0F7D, | |
998 | PREFIX_0F7E, | |
999 | PREFIX_0F7F, | |
f8687e93 JB |
1000 | PREFIX_0FAE_REG_0_MOD_3, |
1001 | PREFIX_0FAE_REG_1_MOD_3, | |
1002 | PREFIX_0FAE_REG_2_MOD_3, | |
1003 | PREFIX_0FAE_REG_3_MOD_3, | |
1004 | PREFIX_0FAE_REG_4_MOD_0, | |
1005 | PREFIX_0FAE_REG_4_MOD_3, | |
1006 | PREFIX_0FAE_REG_5_MOD_0, | |
1007 | PREFIX_0FAE_REG_5_MOD_3, | |
1008 | PREFIX_0FAE_REG_6_MOD_0, | |
1009 | PREFIX_0FAE_REG_6_MOD_3, | |
1010 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1011 | PREFIX_0FB8, |
f12dc422 | 1012 | PREFIX_0FBC, |
3873ba12 L |
1013 | PREFIX_0FBD, |
1014 | PREFIX_0FC2, | |
f8687e93 JB |
1015 | PREFIX_0FC3_MOD_0, |
1016 | PREFIX_0FC7_REG_6_MOD_0, | |
1017 | PREFIX_0FC7_REG_6_MOD_3, | |
1018 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1019 | PREFIX_0FD0, |
1020 | PREFIX_0FD6, | |
1021 | PREFIX_0FE6, | |
1022 | PREFIX_0FE7, | |
1023 | PREFIX_0FF0, | |
1024 | PREFIX_0FF7, | |
1025 | PREFIX_0F3810, | |
1026 | PREFIX_0F3814, | |
1027 | PREFIX_0F3815, | |
1028 | PREFIX_0F3817, | |
1029 | PREFIX_0F3820, | |
1030 | PREFIX_0F3821, | |
1031 | PREFIX_0F3822, | |
1032 | PREFIX_0F3823, | |
1033 | PREFIX_0F3824, | |
1034 | PREFIX_0F3825, | |
1035 | PREFIX_0F3828, | |
1036 | PREFIX_0F3829, | |
1037 | PREFIX_0F382A, | |
1038 | PREFIX_0F382B, | |
1039 | PREFIX_0F3830, | |
1040 | PREFIX_0F3831, | |
1041 | PREFIX_0F3832, | |
1042 | PREFIX_0F3833, | |
1043 | PREFIX_0F3834, | |
1044 | PREFIX_0F3835, | |
1045 | PREFIX_0F3837, | |
1046 | PREFIX_0F3838, | |
1047 | PREFIX_0F3839, | |
1048 | PREFIX_0F383A, | |
1049 | PREFIX_0F383B, | |
1050 | PREFIX_0F383C, | |
1051 | PREFIX_0F383D, | |
1052 | PREFIX_0F383E, | |
1053 | PREFIX_0F383F, | |
1054 | PREFIX_0F3840, | |
1055 | PREFIX_0F3841, | |
1056 | PREFIX_0F3880, | |
1057 | PREFIX_0F3881, | |
6c30d220 | 1058 | PREFIX_0F3882, |
a0046408 L |
1059 | PREFIX_0F38C8, |
1060 | PREFIX_0F38C9, | |
1061 | PREFIX_0F38CA, | |
1062 | PREFIX_0F38CB, | |
1063 | PREFIX_0F38CC, | |
1064 | PREFIX_0F38CD, | |
48521003 | 1065 | PREFIX_0F38CF, |
3873ba12 L |
1066 | PREFIX_0F38DB, |
1067 | PREFIX_0F38DC, | |
1068 | PREFIX_0F38DD, | |
1069 | PREFIX_0F38DE, | |
1070 | PREFIX_0F38DF, | |
1071 | PREFIX_0F38F0, | |
1072 | PREFIX_0F38F1, | |
603555e5 | 1073 | PREFIX_0F38F5, |
e2e1fcde | 1074 | PREFIX_0F38F6, |
c0a30a9f L |
1075 | PREFIX_0F38F8, |
1076 | PREFIX_0F38F9, | |
3873ba12 L |
1077 | PREFIX_0F3A08, |
1078 | PREFIX_0F3A09, | |
1079 | PREFIX_0F3A0A, | |
1080 | PREFIX_0F3A0B, | |
1081 | PREFIX_0F3A0C, | |
1082 | PREFIX_0F3A0D, | |
1083 | PREFIX_0F3A0E, | |
1084 | PREFIX_0F3A14, | |
1085 | PREFIX_0F3A15, | |
1086 | PREFIX_0F3A16, | |
1087 | PREFIX_0F3A17, | |
1088 | PREFIX_0F3A20, | |
1089 | PREFIX_0F3A21, | |
1090 | PREFIX_0F3A22, | |
1091 | PREFIX_0F3A40, | |
1092 | PREFIX_0F3A41, | |
1093 | PREFIX_0F3A42, | |
1094 | PREFIX_0F3A44, | |
1095 | PREFIX_0F3A60, | |
1096 | PREFIX_0F3A61, | |
1097 | PREFIX_0F3A62, | |
1098 | PREFIX_0F3A63, | |
a0046408 | 1099 | PREFIX_0F3ACC, |
48521003 IT |
1100 | PREFIX_0F3ACE, |
1101 | PREFIX_0F3ACF, | |
3873ba12 | 1102 | PREFIX_0F3ADF, |
592a252b L |
1103 | PREFIX_VEX_0F10, |
1104 | PREFIX_VEX_0F11, | |
1105 | PREFIX_VEX_0F12, | |
1106 | PREFIX_VEX_0F16, | |
1107 | PREFIX_VEX_0F2A, | |
1108 | PREFIX_VEX_0F2C, | |
1109 | PREFIX_VEX_0F2D, | |
1110 | PREFIX_VEX_0F2E, | |
1111 | PREFIX_VEX_0F2F, | |
43234a1e L |
1112 | PREFIX_VEX_0F41, |
1113 | PREFIX_VEX_0F42, | |
1114 | PREFIX_VEX_0F44, | |
1115 | PREFIX_VEX_0F45, | |
1116 | PREFIX_VEX_0F46, | |
1117 | PREFIX_VEX_0F47, | |
1ba585e8 | 1118 | PREFIX_VEX_0F4A, |
43234a1e | 1119 | PREFIX_VEX_0F4B, |
592a252b L |
1120 | PREFIX_VEX_0F51, |
1121 | PREFIX_VEX_0F52, | |
1122 | PREFIX_VEX_0F53, | |
1123 | PREFIX_VEX_0F58, | |
1124 | PREFIX_VEX_0F59, | |
1125 | PREFIX_VEX_0F5A, | |
1126 | PREFIX_VEX_0F5B, | |
1127 | PREFIX_VEX_0F5C, | |
1128 | PREFIX_VEX_0F5D, | |
1129 | PREFIX_VEX_0F5E, | |
1130 | PREFIX_VEX_0F5F, | |
1131 | PREFIX_VEX_0F60, | |
1132 | PREFIX_VEX_0F61, | |
1133 | PREFIX_VEX_0F62, | |
1134 | PREFIX_VEX_0F63, | |
1135 | PREFIX_VEX_0F64, | |
1136 | PREFIX_VEX_0F65, | |
1137 | PREFIX_VEX_0F66, | |
1138 | PREFIX_VEX_0F67, | |
1139 | PREFIX_VEX_0F68, | |
1140 | PREFIX_VEX_0F69, | |
1141 | PREFIX_VEX_0F6A, | |
1142 | PREFIX_VEX_0F6B, | |
1143 | PREFIX_VEX_0F6C, | |
1144 | PREFIX_VEX_0F6D, | |
1145 | PREFIX_VEX_0F6E, | |
1146 | PREFIX_VEX_0F6F, | |
1147 | PREFIX_VEX_0F70, | |
1148 | PREFIX_VEX_0F71_REG_2, | |
1149 | PREFIX_VEX_0F71_REG_4, | |
1150 | PREFIX_VEX_0F71_REG_6, | |
1151 | PREFIX_VEX_0F72_REG_2, | |
1152 | PREFIX_VEX_0F72_REG_4, | |
1153 | PREFIX_VEX_0F72_REG_6, | |
1154 | PREFIX_VEX_0F73_REG_2, | |
1155 | PREFIX_VEX_0F73_REG_3, | |
1156 | PREFIX_VEX_0F73_REG_6, | |
1157 | PREFIX_VEX_0F73_REG_7, | |
1158 | PREFIX_VEX_0F74, | |
1159 | PREFIX_VEX_0F75, | |
1160 | PREFIX_VEX_0F76, | |
1161 | PREFIX_VEX_0F77, | |
1162 | PREFIX_VEX_0F7C, | |
1163 | PREFIX_VEX_0F7D, | |
1164 | PREFIX_VEX_0F7E, | |
1165 | PREFIX_VEX_0F7F, | |
43234a1e L |
1166 | PREFIX_VEX_0F90, |
1167 | PREFIX_VEX_0F91, | |
1168 | PREFIX_VEX_0F92, | |
1169 | PREFIX_VEX_0F93, | |
1170 | PREFIX_VEX_0F98, | |
1ba585e8 | 1171 | PREFIX_VEX_0F99, |
592a252b L |
1172 | PREFIX_VEX_0FC2, |
1173 | PREFIX_VEX_0FC4, | |
1174 | PREFIX_VEX_0FC5, | |
1175 | PREFIX_VEX_0FD0, | |
1176 | PREFIX_VEX_0FD1, | |
1177 | PREFIX_VEX_0FD2, | |
1178 | PREFIX_VEX_0FD3, | |
1179 | PREFIX_VEX_0FD4, | |
1180 | PREFIX_VEX_0FD5, | |
1181 | PREFIX_VEX_0FD6, | |
1182 | PREFIX_VEX_0FD7, | |
1183 | PREFIX_VEX_0FD8, | |
1184 | PREFIX_VEX_0FD9, | |
1185 | PREFIX_VEX_0FDA, | |
1186 | PREFIX_VEX_0FDB, | |
1187 | PREFIX_VEX_0FDC, | |
1188 | PREFIX_VEX_0FDD, | |
1189 | PREFIX_VEX_0FDE, | |
1190 | PREFIX_VEX_0FDF, | |
1191 | PREFIX_VEX_0FE0, | |
1192 | PREFIX_VEX_0FE1, | |
1193 | PREFIX_VEX_0FE2, | |
1194 | PREFIX_VEX_0FE3, | |
1195 | PREFIX_VEX_0FE4, | |
1196 | PREFIX_VEX_0FE5, | |
1197 | PREFIX_VEX_0FE6, | |
1198 | PREFIX_VEX_0FE7, | |
1199 | PREFIX_VEX_0FE8, | |
1200 | PREFIX_VEX_0FE9, | |
1201 | PREFIX_VEX_0FEA, | |
1202 | PREFIX_VEX_0FEB, | |
1203 | PREFIX_VEX_0FEC, | |
1204 | PREFIX_VEX_0FED, | |
1205 | PREFIX_VEX_0FEE, | |
1206 | PREFIX_VEX_0FEF, | |
1207 | PREFIX_VEX_0FF0, | |
1208 | PREFIX_VEX_0FF1, | |
1209 | PREFIX_VEX_0FF2, | |
1210 | PREFIX_VEX_0FF3, | |
1211 | PREFIX_VEX_0FF4, | |
1212 | PREFIX_VEX_0FF5, | |
1213 | PREFIX_VEX_0FF6, | |
1214 | PREFIX_VEX_0FF7, | |
1215 | PREFIX_VEX_0FF8, | |
1216 | PREFIX_VEX_0FF9, | |
1217 | PREFIX_VEX_0FFA, | |
1218 | PREFIX_VEX_0FFB, | |
1219 | PREFIX_VEX_0FFC, | |
1220 | PREFIX_VEX_0FFD, | |
1221 | PREFIX_VEX_0FFE, | |
1222 | PREFIX_VEX_0F3800, | |
1223 | PREFIX_VEX_0F3801, | |
1224 | PREFIX_VEX_0F3802, | |
1225 | PREFIX_VEX_0F3803, | |
1226 | PREFIX_VEX_0F3804, | |
1227 | PREFIX_VEX_0F3805, | |
1228 | PREFIX_VEX_0F3806, | |
1229 | PREFIX_VEX_0F3807, | |
1230 | PREFIX_VEX_0F3808, | |
1231 | PREFIX_VEX_0F3809, | |
1232 | PREFIX_VEX_0F380A, | |
1233 | PREFIX_VEX_0F380B, | |
1234 | PREFIX_VEX_0F380C, | |
1235 | PREFIX_VEX_0F380D, | |
1236 | PREFIX_VEX_0F380E, | |
1237 | PREFIX_VEX_0F380F, | |
1238 | PREFIX_VEX_0F3813, | |
6c30d220 | 1239 | PREFIX_VEX_0F3816, |
592a252b L |
1240 | PREFIX_VEX_0F3817, |
1241 | PREFIX_VEX_0F3818, | |
1242 | PREFIX_VEX_0F3819, | |
1243 | PREFIX_VEX_0F381A, | |
1244 | PREFIX_VEX_0F381C, | |
1245 | PREFIX_VEX_0F381D, | |
1246 | PREFIX_VEX_0F381E, | |
1247 | PREFIX_VEX_0F3820, | |
1248 | PREFIX_VEX_0F3821, | |
1249 | PREFIX_VEX_0F3822, | |
1250 | PREFIX_VEX_0F3823, | |
1251 | PREFIX_VEX_0F3824, | |
1252 | PREFIX_VEX_0F3825, | |
1253 | PREFIX_VEX_0F3828, | |
1254 | PREFIX_VEX_0F3829, | |
1255 | PREFIX_VEX_0F382A, | |
1256 | PREFIX_VEX_0F382B, | |
1257 | PREFIX_VEX_0F382C, | |
1258 | PREFIX_VEX_0F382D, | |
1259 | PREFIX_VEX_0F382E, | |
1260 | PREFIX_VEX_0F382F, | |
1261 | PREFIX_VEX_0F3830, | |
1262 | PREFIX_VEX_0F3831, | |
1263 | PREFIX_VEX_0F3832, | |
1264 | PREFIX_VEX_0F3833, | |
1265 | PREFIX_VEX_0F3834, | |
1266 | PREFIX_VEX_0F3835, | |
6c30d220 | 1267 | PREFIX_VEX_0F3836, |
592a252b L |
1268 | PREFIX_VEX_0F3837, |
1269 | PREFIX_VEX_0F3838, | |
1270 | PREFIX_VEX_0F3839, | |
1271 | PREFIX_VEX_0F383A, | |
1272 | PREFIX_VEX_0F383B, | |
1273 | PREFIX_VEX_0F383C, | |
1274 | PREFIX_VEX_0F383D, | |
1275 | PREFIX_VEX_0F383E, | |
1276 | PREFIX_VEX_0F383F, | |
1277 | PREFIX_VEX_0F3840, | |
1278 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1279 | PREFIX_VEX_0F3845, |
1280 | PREFIX_VEX_0F3846, | |
1281 | PREFIX_VEX_0F3847, | |
260cd341 LC |
1282 | PREFIX_VEX_0F3849_X86_64, |
1283 | PREFIX_VEX_0F384B_X86_64, | |
6c30d220 L |
1284 | PREFIX_VEX_0F3858, |
1285 | PREFIX_VEX_0F3859, | |
1286 | PREFIX_VEX_0F385A, | |
260cd341 LC |
1287 | PREFIX_VEX_0F385C_X86_64, |
1288 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1289 | PREFIX_VEX_0F3878, |
1290 | PREFIX_VEX_0F3879, | |
1291 | PREFIX_VEX_0F388C, | |
1292 | PREFIX_VEX_0F388E, | |
1293 | PREFIX_VEX_0F3890, | |
1294 | PREFIX_VEX_0F3891, | |
1295 | PREFIX_VEX_0F3892, | |
1296 | PREFIX_VEX_0F3893, | |
592a252b L |
1297 | PREFIX_VEX_0F3896, |
1298 | PREFIX_VEX_0F3897, | |
1299 | PREFIX_VEX_0F3898, | |
1300 | PREFIX_VEX_0F3899, | |
1301 | PREFIX_VEX_0F389A, | |
1302 | PREFIX_VEX_0F389B, | |
1303 | PREFIX_VEX_0F389C, | |
1304 | PREFIX_VEX_0F389D, | |
1305 | PREFIX_VEX_0F389E, | |
1306 | PREFIX_VEX_0F389F, | |
1307 | PREFIX_VEX_0F38A6, | |
1308 | PREFIX_VEX_0F38A7, | |
1309 | PREFIX_VEX_0F38A8, | |
1310 | PREFIX_VEX_0F38A9, | |
1311 | PREFIX_VEX_0F38AA, | |
1312 | PREFIX_VEX_0F38AB, | |
1313 | PREFIX_VEX_0F38AC, | |
1314 | PREFIX_VEX_0F38AD, | |
1315 | PREFIX_VEX_0F38AE, | |
1316 | PREFIX_VEX_0F38AF, | |
1317 | PREFIX_VEX_0F38B6, | |
1318 | PREFIX_VEX_0F38B7, | |
1319 | PREFIX_VEX_0F38B8, | |
1320 | PREFIX_VEX_0F38B9, | |
1321 | PREFIX_VEX_0F38BA, | |
1322 | PREFIX_VEX_0F38BB, | |
1323 | PREFIX_VEX_0F38BC, | |
1324 | PREFIX_VEX_0F38BD, | |
1325 | PREFIX_VEX_0F38BE, | |
1326 | PREFIX_VEX_0F38BF, | |
48521003 | 1327 | PREFIX_VEX_0F38CF, |
592a252b L |
1328 | PREFIX_VEX_0F38DB, |
1329 | PREFIX_VEX_0F38DC, | |
1330 | PREFIX_VEX_0F38DD, | |
1331 | PREFIX_VEX_0F38DE, | |
1332 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1333 | PREFIX_VEX_0F38F2, |
1334 | PREFIX_VEX_0F38F3_REG_1, | |
1335 | PREFIX_VEX_0F38F3_REG_2, | |
1336 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1337 | PREFIX_VEX_0F38F5, |
1338 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1339 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1340 | PREFIX_VEX_0F3A00, |
1341 | PREFIX_VEX_0F3A01, | |
1342 | PREFIX_VEX_0F3A02, | |
592a252b L |
1343 | PREFIX_VEX_0F3A04, |
1344 | PREFIX_VEX_0F3A05, | |
1345 | PREFIX_VEX_0F3A06, | |
1346 | PREFIX_VEX_0F3A08, | |
1347 | PREFIX_VEX_0F3A09, | |
1348 | PREFIX_VEX_0F3A0A, | |
1349 | PREFIX_VEX_0F3A0B, | |
1350 | PREFIX_VEX_0F3A0C, | |
1351 | PREFIX_VEX_0F3A0D, | |
1352 | PREFIX_VEX_0F3A0E, | |
1353 | PREFIX_VEX_0F3A0F, | |
1354 | PREFIX_VEX_0F3A14, | |
1355 | PREFIX_VEX_0F3A15, | |
1356 | PREFIX_VEX_0F3A16, | |
1357 | PREFIX_VEX_0F3A17, | |
1358 | PREFIX_VEX_0F3A18, | |
1359 | PREFIX_VEX_0F3A19, | |
1360 | PREFIX_VEX_0F3A1D, | |
1361 | PREFIX_VEX_0F3A20, | |
1362 | PREFIX_VEX_0F3A21, | |
1363 | PREFIX_VEX_0F3A22, | |
43234a1e | 1364 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1365 | PREFIX_VEX_0F3A31, |
43234a1e | 1366 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1367 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1368 | PREFIX_VEX_0F3A38, |
1369 | PREFIX_VEX_0F3A39, | |
592a252b L |
1370 | PREFIX_VEX_0F3A40, |
1371 | PREFIX_VEX_0F3A41, | |
1372 | PREFIX_VEX_0F3A42, | |
1373 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1374 | PREFIX_VEX_0F3A46, |
592a252b L |
1375 | PREFIX_VEX_0F3A48, |
1376 | PREFIX_VEX_0F3A49, | |
1377 | PREFIX_VEX_0F3A4A, | |
1378 | PREFIX_VEX_0F3A4B, | |
1379 | PREFIX_VEX_0F3A4C, | |
1380 | PREFIX_VEX_0F3A5C, | |
1381 | PREFIX_VEX_0F3A5D, | |
1382 | PREFIX_VEX_0F3A5E, | |
1383 | PREFIX_VEX_0F3A5F, | |
1384 | PREFIX_VEX_0F3A60, | |
1385 | PREFIX_VEX_0F3A61, | |
1386 | PREFIX_VEX_0F3A62, | |
1387 | PREFIX_VEX_0F3A63, | |
1388 | PREFIX_VEX_0F3A68, | |
1389 | PREFIX_VEX_0F3A69, | |
1390 | PREFIX_VEX_0F3A6A, | |
1391 | PREFIX_VEX_0F3A6B, | |
1392 | PREFIX_VEX_0F3A6C, | |
1393 | PREFIX_VEX_0F3A6D, | |
1394 | PREFIX_VEX_0F3A6E, | |
1395 | PREFIX_VEX_0F3A6F, | |
1396 | PREFIX_VEX_0F3A78, | |
1397 | PREFIX_VEX_0F3A79, | |
1398 | PREFIX_VEX_0F3A7A, | |
1399 | PREFIX_VEX_0F3A7B, | |
1400 | PREFIX_VEX_0F3A7C, | |
1401 | PREFIX_VEX_0F3A7D, | |
1402 | PREFIX_VEX_0F3A7E, | |
1403 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1404 | PREFIX_VEX_0F3ACE, |
1405 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1406 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1407 | PREFIX_VEX_0F3AF0, |
1408 | ||
1409 | PREFIX_EVEX_0F10, | |
1410 | PREFIX_EVEX_0F11, | |
1411 | PREFIX_EVEX_0F12, | |
43234a1e | 1412 | PREFIX_EVEX_0F16, |
43234a1e | 1413 | PREFIX_EVEX_0F2A, |
43234a1e L |
1414 | PREFIX_EVEX_0F51, |
1415 | PREFIX_EVEX_0F58, | |
1416 | PREFIX_EVEX_0F59, | |
1417 | PREFIX_EVEX_0F5A, | |
1418 | PREFIX_EVEX_0F5B, | |
1419 | PREFIX_EVEX_0F5C, | |
1420 | PREFIX_EVEX_0F5D, | |
1421 | PREFIX_EVEX_0F5E, | |
1422 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1423 | PREFIX_EVEX_0F64, |
1424 | PREFIX_EVEX_0F65, | |
43234a1e | 1425 | PREFIX_EVEX_0F66, |
43234a1e L |
1426 | PREFIX_EVEX_0F6E, |
1427 | PREFIX_EVEX_0F6F, | |
1428 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1429 | PREFIX_EVEX_0F71_REG_2, |
1430 | PREFIX_EVEX_0F71_REG_4, | |
1431 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1432 | PREFIX_EVEX_0F72_REG_0, |
1433 | PREFIX_EVEX_0F72_REG_1, | |
1434 | PREFIX_EVEX_0F72_REG_2, | |
1435 | PREFIX_EVEX_0F72_REG_4, | |
1436 | PREFIX_EVEX_0F72_REG_6, | |
1437 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1438 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1439 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1440 | PREFIX_EVEX_0F73_REG_7, |
1441 | PREFIX_EVEX_0F74, | |
1442 | PREFIX_EVEX_0F75, | |
43234a1e L |
1443 | PREFIX_EVEX_0F76, |
1444 | PREFIX_EVEX_0F78, | |
1445 | PREFIX_EVEX_0F79, | |
1446 | PREFIX_EVEX_0F7A, | |
1447 | PREFIX_EVEX_0F7B, | |
1448 | PREFIX_EVEX_0F7E, | |
1449 | PREFIX_EVEX_0F7F, | |
1450 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1451 | PREFIX_EVEX_0FC4, |
1452 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1453 | PREFIX_EVEX_0FD6, |
1454 | PREFIX_EVEX_0FDB, | |
1455 | PREFIX_EVEX_0FDF, | |
1456 | PREFIX_EVEX_0FE2, | |
1457 | PREFIX_EVEX_0FE6, | |
1458 | PREFIX_EVEX_0FE7, | |
1459 | PREFIX_EVEX_0FEB, | |
1460 | PREFIX_EVEX_0FEF, | |
43234a1e | 1461 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1462 | PREFIX_EVEX_0F3810, |
43234a1e L |
1463 | PREFIX_EVEX_0F3811, |
1464 | PREFIX_EVEX_0F3812, | |
1465 | PREFIX_EVEX_0F3813, | |
1466 | PREFIX_EVEX_0F3814, | |
1467 | PREFIX_EVEX_0F3815, | |
1468 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1469 | PREFIX_EVEX_0F3819, |
1470 | PREFIX_EVEX_0F381A, | |
1471 | PREFIX_EVEX_0F381B, | |
1472 | PREFIX_EVEX_0F381E, | |
1473 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1474 | PREFIX_EVEX_0F3820, |
43234a1e L |
1475 | PREFIX_EVEX_0F3821, |
1476 | PREFIX_EVEX_0F3822, | |
1477 | PREFIX_EVEX_0F3823, | |
1478 | PREFIX_EVEX_0F3824, | |
1479 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1480 | PREFIX_EVEX_0F3826, |
43234a1e L |
1481 | PREFIX_EVEX_0F3827, |
1482 | PREFIX_EVEX_0F3828, | |
1483 | PREFIX_EVEX_0F3829, | |
1484 | PREFIX_EVEX_0F382A, | |
1485 | PREFIX_EVEX_0F382C, | |
1486 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1487 | PREFIX_EVEX_0F3830, |
43234a1e L |
1488 | PREFIX_EVEX_0F3831, |
1489 | PREFIX_EVEX_0F3832, | |
1490 | PREFIX_EVEX_0F3833, | |
1491 | PREFIX_EVEX_0F3834, | |
1492 | PREFIX_EVEX_0F3835, | |
1493 | PREFIX_EVEX_0F3836, | |
1494 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1495 | PREFIX_EVEX_0F3838, |
43234a1e L |
1496 | PREFIX_EVEX_0F3839, |
1497 | PREFIX_EVEX_0F383A, | |
1498 | PREFIX_EVEX_0F383B, | |
1499 | PREFIX_EVEX_0F383D, | |
1500 | PREFIX_EVEX_0F383F, | |
1501 | PREFIX_EVEX_0F3840, | |
1502 | PREFIX_EVEX_0F3842, | |
1503 | PREFIX_EVEX_0F3843, | |
1504 | PREFIX_EVEX_0F3844, | |
1505 | PREFIX_EVEX_0F3845, | |
1506 | PREFIX_EVEX_0F3846, | |
1507 | PREFIX_EVEX_0F3847, | |
1508 | PREFIX_EVEX_0F384C, | |
1509 | PREFIX_EVEX_0F384D, | |
1510 | PREFIX_EVEX_0F384E, | |
1511 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1512 | PREFIX_EVEX_0F3850, |
1513 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1514 | PREFIX_EVEX_0F3852, |
1515 | PREFIX_EVEX_0F3853, | |
ee6872be | 1516 | PREFIX_EVEX_0F3854, |
620214f7 | 1517 | PREFIX_EVEX_0F3855, |
43234a1e L |
1518 | PREFIX_EVEX_0F3859, |
1519 | PREFIX_EVEX_0F385A, | |
1520 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1521 | PREFIX_EVEX_0F3862, |
1522 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1523 | PREFIX_EVEX_0F3864, |
1524 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1525 | PREFIX_EVEX_0F3866, |
9186c494 | 1526 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1527 | PREFIX_EVEX_0F3870, |
1528 | PREFIX_EVEX_0F3871, | |
1529 | PREFIX_EVEX_0F3872, | |
1530 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1531 | PREFIX_EVEX_0F3875, |
43234a1e L |
1532 | PREFIX_EVEX_0F3876, |
1533 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1534 | PREFIX_EVEX_0F387A, |
1535 | PREFIX_EVEX_0F387B, | |
43234a1e | 1536 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1537 | PREFIX_EVEX_0F387D, |
43234a1e L |
1538 | PREFIX_EVEX_0F387E, |
1539 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1540 | PREFIX_EVEX_0F3883, |
43234a1e L |
1541 | PREFIX_EVEX_0F3888, |
1542 | PREFIX_EVEX_0F3889, | |
1543 | PREFIX_EVEX_0F388A, | |
1544 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F388D, |
ee6872be | 1546 | PREFIX_EVEX_0F388F, |
43234a1e L |
1547 | PREFIX_EVEX_0F3890, |
1548 | PREFIX_EVEX_0F3891, | |
1549 | PREFIX_EVEX_0F3892, | |
1550 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1551 | PREFIX_EVEX_0F389A, |
1552 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1553 | PREFIX_EVEX_0F38A0, |
1554 | PREFIX_EVEX_0F38A1, | |
1555 | PREFIX_EVEX_0F38A2, | |
1556 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1557 | PREFIX_EVEX_0F38AA, |
1558 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1559 | PREFIX_EVEX_0F38B4, |
1560 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1561 | PREFIX_EVEX_0F38C4, |
1562 | PREFIX_EVEX_0F38C6_REG_1, | |
1563 | PREFIX_EVEX_0F38C6_REG_2, | |
1564 | PREFIX_EVEX_0F38C6_REG_5, | |
1565 | PREFIX_EVEX_0F38C6_REG_6, | |
1566 | PREFIX_EVEX_0F38C7_REG_1, | |
1567 | PREFIX_EVEX_0F38C7_REG_2, | |
1568 | PREFIX_EVEX_0F38C7_REG_5, | |
1569 | PREFIX_EVEX_0F38C7_REG_6, | |
1570 | PREFIX_EVEX_0F38C8, | |
1571 | PREFIX_EVEX_0F38CA, | |
1572 | PREFIX_EVEX_0F38CB, | |
1573 | PREFIX_EVEX_0F38CC, | |
1574 | PREFIX_EVEX_0F38CD, | |
1575 | ||
1576 | PREFIX_EVEX_0F3A00, | |
1577 | PREFIX_EVEX_0F3A01, | |
1578 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1579 | PREFIX_EVEX_0F3A05, |
1580 | PREFIX_EVEX_0F3A08, | |
1581 | PREFIX_EVEX_0F3A09, | |
1582 | PREFIX_EVEX_0F3A0A, | |
1583 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1584 | PREFIX_EVEX_0F3A14, |
1585 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1586 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1587 | PREFIX_EVEX_0F3A17, |
1588 | PREFIX_EVEX_0F3A18, | |
1589 | PREFIX_EVEX_0F3A19, | |
1590 | PREFIX_EVEX_0F3A1A, | |
1591 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1592 | PREFIX_EVEX_0F3A1E, |
1593 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1594 | PREFIX_EVEX_0F3A20, |
43234a1e | 1595 | PREFIX_EVEX_0F3A21, |
90a915bf | 1596 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1597 | PREFIX_EVEX_0F3A23, |
1598 | PREFIX_EVEX_0F3A25, | |
1599 | PREFIX_EVEX_0F3A26, | |
1600 | PREFIX_EVEX_0F3A27, | |
1601 | PREFIX_EVEX_0F3A38, | |
1602 | PREFIX_EVEX_0F3A39, | |
1603 | PREFIX_EVEX_0F3A3A, | |
1604 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1605 | PREFIX_EVEX_0F3A3E, |
1606 | PREFIX_EVEX_0F3A3F, | |
1607 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1608 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1609 | PREFIX_EVEX_0F3A50, |
1610 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1611 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1612 | PREFIX_EVEX_0F3A55, |
1613 | PREFIX_EVEX_0F3A56, | |
1614 | PREFIX_EVEX_0F3A57, | |
1615 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1616 | PREFIX_EVEX_0F3A67, |
1617 | PREFIX_EVEX_0F3A70, | |
1618 | PREFIX_EVEX_0F3A71, | |
1619 | PREFIX_EVEX_0F3A72, | |
48521003 | 1620 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1621 | }; |
4e7d34a6 | 1622 | |
51e7da1b L |
1623 | enum |
1624 | { | |
1625 | X86_64_06 = 0, | |
3873ba12 | 1626 | X86_64_07, |
1673df32 | 1627 | X86_64_0E, |
3873ba12 L |
1628 | X86_64_16, |
1629 | X86_64_17, | |
1630 | X86_64_1E, | |
1631 | X86_64_1F, | |
1632 | X86_64_27, | |
1633 | X86_64_2F, | |
1634 | X86_64_37, | |
1635 | X86_64_3F, | |
1636 | X86_64_60, | |
1637 | X86_64_61, | |
1638 | X86_64_62, | |
1639 | X86_64_63, | |
1640 | X86_64_6D, | |
1641 | X86_64_6F, | |
d039fef3 | 1642 | X86_64_82, |
3873ba12 | 1643 | X86_64_9A, |
aeab2b26 JB |
1644 | X86_64_C2, |
1645 | X86_64_C3, | |
3873ba12 L |
1646 | X86_64_C4, |
1647 | X86_64_C5, | |
1648 | X86_64_CE, | |
1649 | X86_64_D4, | |
1650 | X86_64_D5, | |
a72d2af2 L |
1651 | X86_64_E8, |
1652 | X86_64_E9, | |
3873ba12 L |
1653 | X86_64_EA, |
1654 | X86_64_0F01_REG_0, | |
1655 | X86_64_0F01_REG_1, | |
1656 | X86_64_0F01_REG_2, | |
260cd341 LC |
1657 | X86_64_0F01_REG_3, |
1658 | X86_64_VEX_0F3849, | |
1659 | X86_64_VEX_0F384B, | |
1660 | X86_64_VEX_0F385C, | |
1661 | X86_64_VEX_0F385E | |
51e7da1b | 1662 | }; |
4e7d34a6 | 1663 | |
51e7da1b L |
1664 | enum |
1665 | { | |
1666 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1667 | THREE_BYTE_0F3A |
51e7da1b | 1668 | }; |
4e7d34a6 | 1669 | |
f88c9eb0 SP |
1670 | enum |
1671 | { | |
5dd85c99 SP |
1672 | XOP_08 = 0, |
1673 | XOP_09, | |
f88c9eb0 SP |
1674 | XOP_0A |
1675 | }; | |
1676 | ||
51e7da1b L |
1677 | enum |
1678 | { | |
1679 | VEX_0F = 0, | |
3873ba12 L |
1680 | VEX_0F38, |
1681 | VEX_0F3A | |
51e7da1b | 1682 | }; |
c0f3af97 | 1683 | |
43234a1e L |
1684 | enum |
1685 | { | |
1686 | EVEX_0F = 0, | |
1687 | EVEX_0F38, | |
1688 | EVEX_0F3A | |
1689 | }; | |
1690 | ||
51e7da1b L |
1691 | enum |
1692 | { | |
ec6f095a | 1693 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1694 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1695 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1696 | VEX_LEN_0F13_M_0, |
1697 | VEX_LEN_0F16_P_0_M_0, | |
1698 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1699 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1700 | VEX_LEN_0F17_M_0, |
43234a1e | 1701 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1702 | VEX_LEN_0F41_P_2, |
43234a1e | 1703 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1704 | VEX_LEN_0F42_P_2, |
43234a1e | 1705 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1706 | VEX_LEN_0F44_P_2, |
43234a1e | 1707 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1708 | VEX_LEN_0F45_P_2, |
43234a1e | 1709 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1710 | VEX_LEN_0F46_P_2, |
43234a1e | 1711 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1712 | VEX_LEN_0F47_P_2, |
1713 | VEX_LEN_0F4A_P_0, | |
1714 | VEX_LEN_0F4A_P_2, | |
1715 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1716 | VEX_LEN_0F4B_P_2, |
592a252b | 1717 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1718 | VEX_LEN_0F77_P_0, |
592a252b L |
1719 | VEX_LEN_0F7E_P_1, |
1720 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1721 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1722 | VEX_LEN_0F90_P_2, |
43234a1e | 1723 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1724 | VEX_LEN_0F91_P_2, |
43234a1e | 1725 | VEX_LEN_0F92_P_0, |
90a915bf | 1726 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1727 | VEX_LEN_0F92_P_3, |
43234a1e | 1728 | VEX_LEN_0F93_P_0, |
90a915bf | 1729 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1730 | VEX_LEN_0F93_P_3, |
43234a1e | 1731 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1732 | VEX_LEN_0F98_P_2, |
1733 | VEX_LEN_0F99_P_0, | |
1734 | VEX_LEN_0F99_P_2, | |
592a252b L |
1735 | VEX_LEN_0FAE_R_2_M_0, |
1736 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1737 | VEX_LEN_0FC4_P_2, |
1738 | VEX_LEN_0FC5_P_2, | |
592a252b | 1739 | VEX_LEN_0FD6_P_2, |
592a252b | 1740 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1741 | VEX_LEN_0F3816_P_2, |
1742 | VEX_LEN_0F3819_P_2, | |
592a252b | 1743 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1744 | VEX_LEN_0F3836_P_2, |
592a252b | 1745 | VEX_LEN_0F3841_P_2, |
260cd341 LC |
1746 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1747 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1748 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1749 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1750 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1751 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1752 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
6c30d220 | 1753 | VEX_LEN_0F385A_P_2_M_0, |
260cd341 LC |
1754 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1755 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1756 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1757 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1758 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
592a252b | 1759 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1760 | VEX_LEN_0F38F2_P_0, |
1761 | VEX_LEN_0F38F3_R_1_P_0, | |
1762 | VEX_LEN_0F38F3_R_2_P_0, | |
1763 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1764 | VEX_LEN_0F38F5_P_0, |
1765 | VEX_LEN_0F38F5_P_1, | |
1766 | VEX_LEN_0F38F5_P_3, | |
1767 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1768 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1769 | VEX_LEN_0F38F7_P_1, |
1770 | VEX_LEN_0F38F7_P_2, | |
1771 | VEX_LEN_0F38F7_P_3, | |
1772 | VEX_LEN_0F3A00_P_2, | |
1773 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1774 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1775 | VEX_LEN_0F3A14_P_2, |
1776 | VEX_LEN_0F3A15_P_2, | |
1777 | VEX_LEN_0F3A16_P_2, | |
1778 | VEX_LEN_0F3A17_P_2, | |
1779 | VEX_LEN_0F3A18_P_2, | |
1780 | VEX_LEN_0F3A19_P_2, | |
1781 | VEX_LEN_0F3A20_P_2, | |
1782 | VEX_LEN_0F3A21_P_2, | |
1783 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1784 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1785 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1786 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1787 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1788 | VEX_LEN_0F3A38_P_2, |
1789 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1790 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1791 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1792 | VEX_LEN_0F3A60_P_2, |
1793 | VEX_LEN_0F3A61_P_2, | |
1794 | VEX_LEN_0F3A62_P_2, | |
1795 | VEX_LEN_0F3A63_P_2, | |
592a252b | 1796 | VEX_LEN_0F3ADF_P_2, |
6c30d220 | 1797 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1798 | VEX_LEN_0FXOP_08_85, |
1799 | VEX_LEN_0FXOP_08_86, | |
1800 | VEX_LEN_0FXOP_08_87, | |
1801 | VEX_LEN_0FXOP_08_8E, | |
1802 | VEX_LEN_0FXOP_08_8F, | |
1803 | VEX_LEN_0FXOP_08_95, | |
1804 | VEX_LEN_0FXOP_08_96, | |
1805 | VEX_LEN_0FXOP_08_97, | |
1806 | VEX_LEN_0FXOP_08_9E, | |
1807 | VEX_LEN_0FXOP_08_9F, | |
1808 | VEX_LEN_0FXOP_08_A3, | |
1809 | VEX_LEN_0FXOP_08_A6, | |
1810 | VEX_LEN_0FXOP_08_B6, | |
1811 | VEX_LEN_0FXOP_08_C0, | |
1812 | VEX_LEN_0FXOP_08_C1, | |
1813 | VEX_LEN_0FXOP_08_C2, | |
1814 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1815 | VEX_LEN_0FXOP_08_CC, |
1816 | VEX_LEN_0FXOP_08_CD, | |
1817 | VEX_LEN_0FXOP_08_CE, | |
1818 | VEX_LEN_0FXOP_08_CF, | |
1819 | VEX_LEN_0FXOP_08_EC, | |
1820 | VEX_LEN_0FXOP_08_ED, | |
1821 | VEX_LEN_0FXOP_08_EE, | |
1822 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1823 | VEX_LEN_0FXOP_09_01, |
1824 | VEX_LEN_0FXOP_09_02, | |
1825 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1826 | VEX_LEN_0FXOP_09_82_W_0, |
1827 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1828 | VEX_LEN_0FXOP_09_90, |
1829 | VEX_LEN_0FXOP_09_91, | |
1830 | VEX_LEN_0FXOP_09_92, | |
1831 | VEX_LEN_0FXOP_09_93, | |
1832 | VEX_LEN_0FXOP_09_94, | |
1833 | VEX_LEN_0FXOP_09_95, | |
1834 | VEX_LEN_0FXOP_09_96, | |
1835 | VEX_LEN_0FXOP_09_97, | |
1836 | VEX_LEN_0FXOP_09_98, | |
1837 | VEX_LEN_0FXOP_09_99, | |
1838 | VEX_LEN_0FXOP_09_9A, | |
1839 | VEX_LEN_0FXOP_09_9B, | |
1840 | VEX_LEN_0FXOP_09_C1, | |
1841 | VEX_LEN_0FXOP_09_C2, | |
1842 | VEX_LEN_0FXOP_09_C3, | |
1843 | VEX_LEN_0FXOP_09_C6, | |
1844 | VEX_LEN_0FXOP_09_C7, | |
1845 | VEX_LEN_0FXOP_09_CB, | |
1846 | VEX_LEN_0FXOP_09_D1, | |
1847 | VEX_LEN_0FXOP_09_D2, | |
1848 | VEX_LEN_0FXOP_09_D3, | |
1849 | VEX_LEN_0FXOP_09_D6, | |
1850 | VEX_LEN_0FXOP_09_D7, | |
1851 | VEX_LEN_0FXOP_09_DB, | |
1852 | VEX_LEN_0FXOP_09_E1, | |
1853 | VEX_LEN_0FXOP_09_E2, | |
1854 | VEX_LEN_0FXOP_09_E3, | |
1855 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1856 | }; |
c0f3af97 | 1857 | |
04e2a182 L |
1858 | enum |
1859 | { | |
1860 | EVEX_LEN_0F6E_P_2 = 0, | |
1861 | EVEX_LEN_0F7E_P_1, | |
1862 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1863 | EVEX_LEN_0FC4_P_2, |
1864 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1865 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1866 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1867 | EVEX_LEN_0F3819_P_2_W_0, |
1868 | EVEX_LEN_0F3819_P_2_W_1, | |
bc152a17 JB |
1869 | EVEX_LEN_0F381A_P_2_W_0_M_0, |
1870 | EVEX_LEN_0F381A_P_2_W_1_M_0, | |
1871 | EVEX_LEN_0F381B_P_2_W_0_M_0, | |
1872 | EVEX_LEN_0F381B_P_2_W_1_M_0, | |
3a57774c | 1873 | EVEX_LEN_0F3836_P_2, |
bc152a17 JB |
1874 | EVEX_LEN_0F385A_P_2_W_0_M_0, |
1875 | EVEX_LEN_0F385A_P_2_W_1_M_0, | |
1876 | EVEX_LEN_0F385B_P_2_W_0_M_0, | |
1877 | EVEX_LEN_0F385B_P_2_W_1_M_0, | |
e395f487 L |
1878 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1879 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1880 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1881 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1882 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1883 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1884 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1885 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1886 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1887 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1888 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1889 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1890 | EVEX_LEN_0F3A00_P_2_W_1, |
1891 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1892 | EVEX_LEN_0F3A14_P_2, |
1893 | EVEX_LEN_0F3A15_P_2, | |
1894 | EVEX_LEN_0F3A16_P_2, | |
1895 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1896 | EVEX_LEN_0F3A18_P_2_W_0, |
1897 | EVEX_LEN_0F3A18_P_2_W_1, | |
1898 | EVEX_LEN_0F3A19_P_2_W_0, | |
1899 | EVEX_LEN_0F3A19_P_2_W_1, | |
1900 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1901 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1902 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1903 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1904 | EVEX_LEN_0F3A20_P_2, |
1905 | EVEX_LEN_0F3A21_P_2_W_0, | |
1906 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1907 | EVEX_LEN_0F3A23_P_2_W_0, |
1908 | EVEX_LEN_0F3A23_P_2_W_1, | |
1909 | EVEX_LEN_0F3A38_P_2_W_0, | |
1910 | EVEX_LEN_0F3A38_P_2_W_1, | |
1911 | EVEX_LEN_0F3A39_P_2_W_0, | |
1912 | EVEX_LEN_0F3A39_P_2_W_1, | |
1913 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1914 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1915 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1916 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1917 | EVEX_LEN_0F3A43_P_2_W_0, | |
1918 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1919 | }; |
1920 | ||
9e30b8e0 L |
1921 | enum |
1922 | { | |
ec6f095a | 1923 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1924 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1925 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1926 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1927 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1928 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1929 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1930 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1931 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1932 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1933 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1934 | VEX_W_0F47_P_2_LEN_1, |
1935 | VEX_W_0F4A_P_0_LEN_1, | |
1936 | VEX_W_0F4A_P_2_LEN_1, | |
1937 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1938 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1939 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1940 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1941 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1942 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1943 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1944 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1945 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1946 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1947 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1948 | VEX_W_0F98_P_2_LEN_0, |
1949 | VEX_W_0F99_P_0_LEN_0, | |
1950 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1951 | VEX_W_0F380C_P_2, |
1952 | VEX_W_0F380D_P_2, | |
1953 | VEX_W_0F380E_P_2, | |
1954 | VEX_W_0F380F_P_2, | |
6431c801 | 1955 | VEX_W_0F3813_P_2, |
6c30d220 | 1956 | VEX_W_0F3816_P_2, |
6c30d220 L |
1957 | VEX_W_0F3818_P_2, |
1958 | VEX_W_0F3819_P_2, | |
89e65d17 | 1959 | VEX_W_0F381A_P_2_M_0_L_0, |
592a252b L |
1960 | VEX_W_0F382C_P_2_M_0, |
1961 | VEX_W_0F382D_P_2_M_0, | |
1962 | VEX_W_0F382E_P_2_M_0, | |
1963 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1964 | VEX_W_0F3836_P_2, |
6c30d220 | 1965 | VEX_W_0F3846_P_2, |
260cd341 LC |
1966 | VEX_W_0F3849_X86_64_P_0, |
1967 | VEX_W_0F3849_X86_64_P_2, | |
1968 | VEX_W_0F3849_X86_64_P_3, | |
1969 | VEX_W_0F384B_X86_64_P_1, | |
1970 | VEX_W_0F384B_X86_64_P_2, | |
1971 | VEX_W_0F384B_X86_64_P_3, | |
6c30d220 L |
1972 | VEX_W_0F3858_P_2, |
1973 | VEX_W_0F3859_P_2, | |
89e65d17 | 1974 | VEX_W_0F385A_P_2_M_0_L_0, |
260cd341 LC |
1975 | VEX_W_0F385C_X86_64_P_1, |
1976 | VEX_W_0F385E_X86_64_P_0, | |
1977 | VEX_W_0F385E_X86_64_P_1, | |
1978 | VEX_W_0F385E_X86_64_P_2, | |
1979 | VEX_W_0F385E_X86_64_P_3, | |
6c30d220 L |
1980 | VEX_W_0F3878_P_2, |
1981 | VEX_W_0F3879_P_2, | |
48521003 | 1982 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1983 | VEX_W_0F3A00_P_2, |
1984 | VEX_W_0F3A01_P_2, | |
1985 | VEX_W_0F3A02_P_2, | |
592a252b L |
1986 | VEX_W_0F3A04_P_2, |
1987 | VEX_W_0F3A05_P_2, | |
89e65d17 JB |
1988 | VEX_W_0F3A06_P_2_L_0, |
1989 | VEX_W_0F3A18_P_2_L_0, | |
1990 | VEX_W_0F3A19_P_2_L_0, | |
6431c801 | 1991 | VEX_W_0F3A1D_P_2, |
43234a1e | 1992 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 1993 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 1994 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 1995 | VEX_W_0F3A33_P_2_LEN_0, |
89e65d17 JB |
1996 | VEX_W_0F3A38_P_2_L_0, |
1997 | VEX_W_0F3A39_P_2_L_0, | |
1998 | VEX_W_0F3A46_P_2_L_0, | |
592a252b L |
1999 | VEX_W_0F3A4A_P_2, |
2000 | VEX_W_0F3A4B_P_2, | |
2001 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2002 | VEX_W_0F3ACE_P_2, |
2003 | VEX_W_0F3ACF_P_2, | |
43234a1e | 2004 | |
467bbef0 JB |
2005 | VEX_W_0FXOP_08_85_L_0, |
2006 | VEX_W_0FXOP_08_86_L_0, | |
2007 | VEX_W_0FXOP_08_87_L_0, | |
2008 | VEX_W_0FXOP_08_8E_L_0, | |
2009 | VEX_W_0FXOP_08_8F_L_0, | |
2010 | VEX_W_0FXOP_08_95_L_0, | |
2011 | VEX_W_0FXOP_08_96_L_0, | |
2012 | VEX_W_0FXOP_08_97_L_0, | |
2013 | VEX_W_0FXOP_08_9E_L_0, | |
2014 | VEX_W_0FXOP_08_9F_L_0, | |
2015 | VEX_W_0FXOP_08_A6_L_0, | |
2016 | VEX_W_0FXOP_08_B6_L_0, | |
2017 | VEX_W_0FXOP_08_C0_L_0, | |
2018 | VEX_W_0FXOP_08_C1_L_0, | |
2019 | VEX_W_0FXOP_08_C2_L_0, | |
2020 | VEX_W_0FXOP_08_C3_L_0, | |
2021 | VEX_W_0FXOP_08_CC_L_0, | |
2022 | VEX_W_0FXOP_08_CD_L_0, | |
2023 | VEX_W_0FXOP_08_CE_L_0, | |
2024 | VEX_W_0FXOP_08_CF_L_0, | |
2025 | VEX_W_0FXOP_08_EC_L_0, | |
2026 | VEX_W_0FXOP_08_ED_L_0, | |
2027 | VEX_W_0FXOP_08_EE_L_0, | |
2028 | VEX_W_0FXOP_08_EF_L_0, | |
2029 | ||
b5b098c2 JB |
2030 | VEX_W_0FXOP_09_80, |
2031 | VEX_W_0FXOP_09_81, | |
2032 | VEX_W_0FXOP_09_82, | |
2033 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
2034 | VEX_W_0FXOP_09_C1_L_0, |
2035 | VEX_W_0FXOP_09_C2_L_0, | |
2036 | VEX_W_0FXOP_09_C3_L_0, | |
2037 | VEX_W_0FXOP_09_C6_L_0, | |
2038 | VEX_W_0FXOP_09_C7_L_0, | |
2039 | VEX_W_0FXOP_09_CB_L_0, | |
2040 | VEX_W_0FXOP_09_D1_L_0, | |
2041 | VEX_W_0FXOP_09_D2_L_0, | |
2042 | VEX_W_0FXOP_09_D3_L_0, | |
2043 | VEX_W_0FXOP_09_D6_L_0, | |
2044 | VEX_W_0FXOP_09_D7_L_0, | |
2045 | VEX_W_0FXOP_09_DB_L_0, | |
2046 | VEX_W_0FXOP_09_E1_L_0, | |
2047 | VEX_W_0FXOP_09_E2_L_0, | |
2048 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 2049 | |
36cc073e | 2050 | EVEX_W_0F10_P_1, |
36cc073e | 2051 | EVEX_W_0F10_P_3, |
36cc073e | 2052 | EVEX_W_0F11_P_1, |
36cc073e | 2053 | EVEX_W_0F11_P_3, |
43234a1e L |
2054 | EVEX_W_0F12_P_0_M_1, |
2055 | EVEX_W_0F12_P_1, | |
43234a1e | 2056 | EVEX_W_0F12_P_3, |
43234a1e L |
2057 | EVEX_W_0F16_P_0_M_1, |
2058 | EVEX_W_0F16_P_1, | |
43234a1e | 2059 | EVEX_W_0F2A_P_3, |
43234a1e | 2060 | EVEX_W_0F51_P_1, |
43234a1e | 2061 | EVEX_W_0F51_P_3, |
43234a1e | 2062 | EVEX_W_0F58_P_1, |
43234a1e | 2063 | EVEX_W_0F58_P_3, |
43234a1e | 2064 | EVEX_W_0F59_P_1, |
43234a1e L |
2065 | EVEX_W_0F59_P_3, |
2066 | EVEX_W_0F5A_P_0, | |
2067 | EVEX_W_0F5A_P_1, | |
2068 | EVEX_W_0F5A_P_2, | |
2069 | EVEX_W_0F5A_P_3, | |
2070 | EVEX_W_0F5B_P_0, | |
2071 | EVEX_W_0F5B_P_1, | |
2072 | EVEX_W_0F5B_P_2, | |
43234a1e | 2073 | EVEX_W_0F5C_P_1, |
43234a1e | 2074 | EVEX_W_0F5C_P_3, |
43234a1e | 2075 | EVEX_W_0F5D_P_1, |
43234a1e | 2076 | EVEX_W_0F5D_P_3, |
43234a1e | 2077 | EVEX_W_0F5E_P_1, |
43234a1e | 2078 | EVEX_W_0F5E_P_3, |
43234a1e | 2079 | EVEX_W_0F5F_P_1, |
43234a1e | 2080 | EVEX_W_0F5F_P_3, |
fedfb81e | 2081 | EVEX_W_0F62, |
43234a1e | 2082 | EVEX_W_0F66_P_2, |
fedfb81e JB |
2083 | EVEX_W_0F6A, |
2084 | EVEX_W_0F6B, | |
2085 | EVEX_W_0F6C, | |
2086 | EVEX_W_0F6D, | |
43234a1e L |
2087 | EVEX_W_0F6F_P_1, |
2088 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2089 | EVEX_W_0F6F_P_3, |
43234a1e L |
2090 | EVEX_W_0F70_P_2, |
2091 | EVEX_W_0F72_R_2_P_2, | |
2092 | EVEX_W_0F72_R_6_P_2, | |
2093 | EVEX_W_0F73_R_2_P_2, | |
2094 | EVEX_W_0F73_R_6_P_2, | |
2095 | EVEX_W_0F76_P_2, | |
2096 | EVEX_W_0F78_P_0, | |
90a915bf | 2097 | EVEX_W_0F78_P_2, |
43234a1e | 2098 | EVEX_W_0F79_P_0, |
90a915bf | 2099 | EVEX_W_0F79_P_2, |
43234a1e | 2100 | EVEX_W_0F7A_P_1, |
90a915bf | 2101 | EVEX_W_0F7A_P_2, |
43234a1e | 2102 | EVEX_W_0F7A_P_3, |
90a915bf | 2103 | EVEX_W_0F7B_P_2, |
43234a1e L |
2104 | EVEX_W_0F7B_P_3, |
2105 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2106 | EVEX_W_0F7F_P_1, |
2107 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2108 | EVEX_W_0F7F_P_3, |
43234a1e | 2109 | EVEX_W_0FC2_P_1, |
43234a1e | 2110 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2111 | EVEX_W_0FD2, |
2112 | EVEX_W_0FD3, | |
2113 | EVEX_W_0FD4, | |
43234a1e L |
2114 | EVEX_W_0FD6_P_2, |
2115 | EVEX_W_0FE6_P_1, | |
2116 | EVEX_W_0FE6_P_2, | |
2117 | EVEX_W_0FE6_P_3, | |
2118 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2119 | EVEX_W_0FF2, |
2120 | EVEX_W_0FF3, | |
2121 | EVEX_W_0FF4, | |
2122 | EVEX_W_0FFA, | |
2123 | EVEX_W_0FFB, | |
2124 | EVEX_W_0FFE, | |
43234a1e | 2125 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2126 | EVEX_W_0F3810_P_1, |
2127 | EVEX_W_0F3810_P_2, | |
43234a1e | 2128 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2129 | EVEX_W_0F3811_P_2, |
43234a1e | 2130 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2131 | EVEX_W_0F3812_P_2, |
43234a1e L |
2132 | EVEX_W_0F3813_P_1, |
2133 | EVEX_W_0F3813_P_2, | |
2134 | EVEX_W_0F3814_P_1, | |
2135 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2136 | EVEX_W_0F3819_P_2, |
2137 | EVEX_W_0F381A_P_2, | |
2138 | EVEX_W_0F381B_P_2, | |
2139 | EVEX_W_0F381E_P_2, | |
2140 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2141 | EVEX_W_0F3820_P_1, |
43234a1e L |
2142 | EVEX_W_0F3821_P_1, |
2143 | EVEX_W_0F3822_P_1, | |
2144 | EVEX_W_0F3823_P_1, | |
2145 | EVEX_W_0F3824_P_1, | |
2146 | EVEX_W_0F3825_P_1, | |
2147 | EVEX_W_0F3825_P_2, | |
2148 | EVEX_W_0F3828_P_2, | |
2149 | EVEX_W_0F3829_P_2, | |
2150 | EVEX_W_0F382A_P_1, | |
2151 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2152 | EVEX_W_0F382B, |
1ba585e8 | 2153 | EVEX_W_0F3830_P_1, |
43234a1e L |
2154 | EVEX_W_0F3831_P_1, |
2155 | EVEX_W_0F3832_P_1, | |
2156 | EVEX_W_0F3833_P_1, | |
2157 | EVEX_W_0F3834_P_1, | |
2158 | EVEX_W_0F3835_P_1, | |
2159 | EVEX_W_0F3835_P_2, | |
2160 | EVEX_W_0F3837_P_2, | |
2161 | EVEX_W_0F383A_P_1, | |
d6aab7a1 | 2162 | EVEX_W_0F3852_P_1, |
43234a1e L |
2163 | EVEX_W_0F3859_P_2, |
2164 | EVEX_W_0F385A_P_2, | |
2165 | EVEX_W_0F385B_P_2, | |
53467f57 | 2166 | EVEX_W_0F3870_P_2, |
d6aab7a1 | 2167 | EVEX_W_0F3872_P_1, |
53467f57 | 2168 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2169 | EVEX_W_0F3872_P_3, |
1ba585e8 IT |
2170 | EVEX_W_0F387A_P_2, |
2171 | EVEX_W_0F387B_P_2, | |
14f195c9 | 2172 | EVEX_W_0F3883_P_2, |
43234a1e L |
2173 | EVEX_W_0F3891_P_2, |
2174 | EVEX_W_0F3893_P_2, | |
2175 | EVEX_W_0F38A1_P_2, | |
2176 | EVEX_W_0F38A3_P_2, | |
2177 | EVEX_W_0F38C7_R_1_P_2, | |
2178 | EVEX_W_0F38C7_R_2_P_2, | |
2179 | EVEX_W_0F38C7_R_5_P_2, | |
2180 | EVEX_W_0F38C7_R_6_P_2, | |
2181 | ||
2182 | EVEX_W_0F3A00_P_2, | |
2183 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2184 | EVEX_W_0F3A05_P_2, |
2185 | EVEX_W_0F3A08_P_2, | |
2186 | EVEX_W_0F3A09_P_2, | |
2187 | EVEX_W_0F3A0A_P_2, | |
2188 | EVEX_W_0F3A0B_P_2, | |
2189 | EVEX_W_0F3A18_P_2, | |
2190 | EVEX_W_0F3A19_P_2, | |
2191 | EVEX_W_0F3A1A_P_2, | |
2192 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2193 | EVEX_W_0F3A21_P_2, |
2194 | EVEX_W_0F3A23_P_2, | |
2195 | EVEX_W_0F3A38_P_2, | |
2196 | EVEX_W_0F3A39_P_2, | |
2197 | EVEX_W_0F3A3A_P_2, | |
2198 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 | 2199 | EVEX_W_0F3A42_P_2, |
90a915bf | 2200 | EVEX_W_0F3A43_P_2, |
53467f57 | 2201 | EVEX_W_0F3A70_P_2, |
53467f57 | 2202 | EVEX_W_0F3A72_P_2, |
9e30b8e0 L |
2203 | }; |
2204 | ||
26ca5450 | 2205 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2206 | |
2207 | struct dis386 { | |
2da11e11 | 2208 | const char *name; |
ce518a5f L |
2209 | struct |
2210 | { | |
2211 | op_rtn rtn; | |
2212 | int bytemode; | |
2213 | } op[MAX_OPERANDS]; | |
bf890a93 | 2214 | unsigned int prefix_requirement; |
252b5132 RH |
2215 | }; |
2216 | ||
2217 | /* Upper case letters in the instruction names here are macros. | |
2218 | 'A' => print 'b' if no register operands or suffix_always is true | |
2219 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2220 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2221 | size prefix |
ed7841b3 | 2222 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2223 | suffix_always is true |
252b5132 | 2224 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2225 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2226 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2227 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2228 | 'I' unused. |
8f570d62 | 2229 | 'J' unused. |
42903f7f | 2230 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2231 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2232 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2233 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2234 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2235 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2236 | or suffix_always is true. print 'q' if rex prefix is present. |
2237 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2238 | is true | |
a35ca55a | 2239 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2240 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2241 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2242 | prefix and behave as 'P' otherwise | |
2243 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2244 | prefix and behave as 'Q' otherwise | |
2245 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2246 | prefix and behave as 'S' otherwise | |
a35ca55a | 2247 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2248 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2249 | 'Y' unused. |
6dd5059a | 2250 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2251 | '!' => change condition from true to false or from false to true. |
98b528ac | 2252 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2253 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2254 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2255 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2256 | on operand size prefix. | |
07f5af7d L |
2257 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2258 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2259 | otherwise | |
98b528ac L |
2260 | |
2261 | 2 upper case letter macros: | |
04d824a4 JB |
2262 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2263 | operands and no broadcast. | |
2264 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2265 | register operands and no broadcast. | |
4b06377f | 2266 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
b24d668c JB |
2267 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
2268 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 2269 | is true. |
4b06377f L |
2270 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2271 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2272 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
492a76aa | 2273 | "DQ" => print 'd' or 'q' depending on the VEX.W bit |
931452b6 | 2274 | "BW" => print 'b' or 'w' depending on the EVEX.W bit |
4b4c407a L |
2275 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2276 | an operand size prefix, or suffix_always is true. print | |
2277 | 'q' if rex prefix is present. | |
52b15da3 | 2278 | |
6439fc28 AM |
2279 | Many of the above letters print nothing in Intel mode. See "putop" |
2280 | for the details. | |
52b15da3 | 2281 | |
6439fc28 | 2282 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2283 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2284 | |
6439fc28 | 2285 | static const struct dis386 dis386[] = { |
252b5132 | 2286 | /* 00 */ |
bf890a93 IT |
2287 | { "addB", { Ebh1, Gb }, 0 }, |
2288 | { "addS", { Evh1, Gv }, 0 }, | |
2289 | { "addB", { Gb, EbS }, 0 }, | |
2290 | { "addS", { Gv, EvS }, 0 }, | |
2291 | { "addB", { AL, Ib }, 0 }, | |
2292 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2293 | { X86_64_TABLE (X86_64_06) }, |
2294 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2295 | /* 08 */ |
bf890a93 IT |
2296 | { "orB", { Ebh1, Gb }, 0 }, |
2297 | { "orS", { Evh1, Gv }, 0 }, | |
2298 | { "orB", { Gb, EbS }, 0 }, | |
2299 | { "orS", { Gv, EvS }, 0 }, | |
2300 | { "orB", { AL, Ib }, 0 }, | |
2301 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2302 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2303 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2304 | /* 10 */ |
bf890a93 IT |
2305 | { "adcB", { Ebh1, Gb }, 0 }, |
2306 | { "adcS", { Evh1, Gv }, 0 }, | |
2307 | { "adcB", { Gb, EbS }, 0 }, | |
2308 | { "adcS", { Gv, EvS }, 0 }, | |
2309 | { "adcB", { AL, Ib }, 0 }, | |
2310 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2311 | { X86_64_TABLE (X86_64_16) }, |
2312 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2313 | /* 18 */ |
bf890a93 IT |
2314 | { "sbbB", { Ebh1, Gb }, 0 }, |
2315 | { "sbbS", { Evh1, Gv }, 0 }, | |
2316 | { "sbbB", { Gb, EbS }, 0 }, | |
2317 | { "sbbS", { Gv, EvS }, 0 }, | |
2318 | { "sbbB", { AL, Ib }, 0 }, | |
2319 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2320 | { X86_64_TABLE (X86_64_1E) }, |
2321 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2322 | /* 20 */ |
bf890a93 IT |
2323 | { "andB", { Ebh1, Gb }, 0 }, |
2324 | { "andS", { Evh1, Gv }, 0 }, | |
2325 | { "andB", { Gb, EbS }, 0 }, | |
2326 | { "andS", { Gv, EvS }, 0 }, | |
2327 | { "andB", { AL, Ib }, 0 }, | |
2328 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2329 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2330 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2331 | /* 28 */ |
bf890a93 IT |
2332 | { "subB", { Ebh1, Gb }, 0 }, |
2333 | { "subS", { Evh1, Gv }, 0 }, | |
2334 | { "subB", { Gb, EbS }, 0 }, | |
2335 | { "subS", { Gv, EvS }, 0 }, | |
2336 | { "subB", { AL, Ib }, 0 }, | |
2337 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2338 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2339 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2340 | /* 30 */ |
bf890a93 IT |
2341 | { "xorB", { Ebh1, Gb }, 0 }, |
2342 | { "xorS", { Evh1, Gv }, 0 }, | |
2343 | { "xorB", { Gb, EbS }, 0 }, | |
2344 | { "xorS", { Gv, EvS }, 0 }, | |
2345 | { "xorB", { AL, Ib }, 0 }, | |
2346 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2347 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2348 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2349 | /* 38 */ |
bf890a93 IT |
2350 | { "cmpB", { Eb, Gb }, 0 }, |
2351 | { "cmpS", { Ev, Gv }, 0 }, | |
2352 | { "cmpB", { Gb, EbS }, 0 }, | |
2353 | { "cmpS", { Gv, EvS }, 0 }, | |
2354 | { "cmpB", { AL, Ib }, 0 }, | |
2355 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2356 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2357 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2358 | /* 40 */ |
bf890a93 IT |
2359 | { "inc{S|}", { RMeAX }, 0 }, |
2360 | { "inc{S|}", { RMeCX }, 0 }, | |
2361 | { "inc{S|}", { RMeDX }, 0 }, | |
2362 | { "inc{S|}", { RMeBX }, 0 }, | |
2363 | { "inc{S|}", { RMeSP }, 0 }, | |
2364 | { "inc{S|}", { RMeBP }, 0 }, | |
2365 | { "inc{S|}", { RMeSI }, 0 }, | |
2366 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2367 | /* 48 */ |
bf890a93 IT |
2368 | { "dec{S|}", { RMeAX }, 0 }, |
2369 | { "dec{S|}", { RMeCX }, 0 }, | |
2370 | { "dec{S|}", { RMeDX }, 0 }, | |
2371 | { "dec{S|}", { RMeBX }, 0 }, | |
2372 | { "dec{S|}", { RMeSP }, 0 }, | |
2373 | { "dec{S|}", { RMeBP }, 0 }, | |
2374 | { "dec{S|}", { RMeSI }, 0 }, | |
2375 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2376 | /* 50 */ |
bf890a93 IT |
2377 | { "pushV", { RMrAX }, 0 }, |
2378 | { "pushV", { RMrCX }, 0 }, | |
2379 | { "pushV", { RMrDX }, 0 }, | |
2380 | { "pushV", { RMrBX }, 0 }, | |
2381 | { "pushV", { RMrSP }, 0 }, | |
2382 | { "pushV", { RMrBP }, 0 }, | |
2383 | { "pushV", { RMrSI }, 0 }, | |
2384 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2385 | /* 58 */ |
bf890a93 IT |
2386 | { "popV", { RMrAX }, 0 }, |
2387 | { "popV", { RMrCX }, 0 }, | |
2388 | { "popV", { RMrDX }, 0 }, | |
2389 | { "popV", { RMrBX }, 0 }, | |
2390 | { "popV", { RMrSP }, 0 }, | |
2391 | { "popV", { RMrBP }, 0 }, | |
2392 | { "popV", { RMrSI }, 0 }, | |
2393 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2394 | /* 60 */ |
4e7d34a6 L |
2395 | { X86_64_TABLE (X86_64_60) }, |
2396 | { X86_64_TABLE (X86_64_61) }, | |
2397 | { X86_64_TABLE (X86_64_62) }, | |
2398 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2399 | { Bad_Opcode }, /* seg fs */ |
2400 | { Bad_Opcode }, /* seg gs */ | |
2401 | { Bad_Opcode }, /* op size prefix */ | |
2402 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2403 | /* 68 */ |
bf890a93 IT |
2404 | { "pushT", { sIv }, 0 }, |
2405 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2406 | { "pushT", { sIbT }, 0 }, | |
2407 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2408 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2409 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2410 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2411 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2412 | /* 70 */ |
bf890a93 IT |
2413 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2414 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2415 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2416 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2417 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2418 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2419 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2420 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2421 | /* 78 */ |
bf890a93 IT |
2422 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2423 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2424 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2425 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2426 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2427 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2428 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2429 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2430 | /* 80 */ |
1ceb70f8 L |
2431 | { REG_TABLE (REG_80) }, |
2432 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2433 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2434 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2435 | { "testB", { Eb, Gb }, 0 }, |
2436 | { "testS", { Ev, Gv }, 0 }, | |
2437 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2438 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2439 | /* 88 */ |
bf890a93 IT |
2440 | { "movB", { Ebh3, Gb }, 0 }, |
2441 | { "movS", { Evh3, Gv }, 0 }, | |
2442 | { "movB", { Gb, EbS }, 0 }, | |
2443 | { "movS", { Gv, EvS }, 0 }, | |
2444 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2445 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2446 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2447 | { REG_TABLE (REG_8F) }, |
252b5132 | 2448 | /* 90 */ |
1ceb70f8 | 2449 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2450 | { "xchgS", { RMeCX, eAX }, 0 }, |
2451 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2452 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2453 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2454 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2455 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2456 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2457 | /* 98 */ |
bf890a93 IT |
2458 | { "cW{t|}R", { XX }, 0 }, |
2459 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2460 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2461 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2462 | { "pushfT", { XX }, 0 }, |
2463 | { "popfT", { XX }, 0 }, | |
2464 | { "sahf", { XX }, 0 }, | |
2465 | { "lahf", { XX }, 0 }, | |
252b5132 | 2466 | /* a0 */ |
bf890a93 IT |
2467 | { "mov%LB", { AL, Ob }, 0 }, |
2468 | { "mov%LS", { eAX, Ov }, 0 }, | |
2469 | { "mov%LB", { Ob, AL }, 0 }, | |
2470 | { "mov%LS", { Ov, eAX }, 0 }, | |
2471 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2472 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2473 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2474 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2475 | /* a8 */ |
bf890a93 IT |
2476 | { "testB", { AL, Ib }, 0 }, |
2477 | { "testS", { eAX, Iv }, 0 }, | |
2478 | { "stosB", { Ybr, AL }, 0 }, | |
2479 | { "stosS", { Yvr, eAX }, 0 }, | |
2480 | { "lodsB", { ALr, Xb }, 0 }, | |
2481 | { "lodsS", { eAXr, Xv }, 0 }, | |
2482 | { "scasB", { AL, Yb }, 0 }, | |
2483 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2484 | /* b0 */ |
bf890a93 IT |
2485 | { "movB", { RMAL, Ib }, 0 }, |
2486 | { "movB", { RMCL, Ib }, 0 }, | |
2487 | { "movB", { RMDL, Ib }, 0 }, | |
2488 | { "movB", { RMBL, Ib }, 0 }, | |
2489 | { "movB", { RMAH, Ib }, 0 }, | |
2490 | { "movB", { RMCH, Ib }, 0 }, | |
2491 | { "movB", { RMDH, Ib }, 0 }, | |
2492 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2493 | /* b8 */ |
bf890a93 IT |
2494 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2495 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2496 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2497 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2498 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2499 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2500 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2501 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2502 | /* c0 */ |
1ceb70f8 L |
2503 | { REG_TABLE (REG_C0) }, |
2504 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2505 | { X86_64_TABLE (X86_64_C2) }, |
2506 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2507 | { X86_64_TABLE (X86_64_C4) }, |
2508 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2509 | { REG_TABLE (REG_C6) }, |
2510 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2511 | /* c8 */ |
bf890a93 IT |
2512 | { "enterT", { Iw, Ib }, 0 }, |
2513 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2514 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2515 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2516 | { "int3", { XX }, 0 }, |
2517 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2518 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2519 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2520 | /* d0 */ |
1ceb70f8 L |
2521 | { REG_TABLE (REG_D0) }, |
2522 | { REG_TABLE (REG_D1) }, | |
2523 | { REG_TABLE (REG_D2) }, | |
2524 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2525 | { X86_64_TABLE (X86_64_D4) }, |
2526 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2527 | { Bad_Opcode }, |
bf890a93 | 2528 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2529 | /* d8 */ |
2530 | { FLOAT }, | |
2531 | { FLOAT }, | |
2532 | { FLOAT }, | |
2533 | { FLOAT }, | |
2534 | { FLOAT }, | |
2535 | { FLOAT }, | |
2536 | { FLOAT }, | |
2537 | { FLOAT }, | |
2538 | /* e0 */ | |
bf890a93 IT |
2539 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2540 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2541 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2542 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2543 | { "inB", { AL, Ib }, 0 }, | |
2544 | { "inG", { zAX, Ib }, 0 }, | |
2545 | { "outB", { Ib, AL }, 0 }, | |
2546 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2547 | /* e8 */ |
a72d2af2 L |
2548 | { X86_64_TABLE (X86_64_E8) }, |
2549 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2550 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2551 | { "jmp", { Jb, BND }, 0 }, |
2552 | { "inB", { AL, indirDX }, 0 }, | |
2553 | { "inG", { zAX, indirDX }, 0 }, | |
2554 | { "outB", { indirDX, AL }, 0 }, | |
2555 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2556 | /* f0 */ |
592d1631 | 2557 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2558 | { "icebp", { XX }, 0 }, |
592d1631 L |
2559 | { Bad_Opcode }, /* repne */ |
2560 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2561 | { "hlt", { XX }, 0 }, |
2562 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2563 | { REG_TABLE (REG_F6) }, |
2564 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2565 | /* f8 */ |
bf890a93 IT |
2566 | { "clc", { XX }, 0 }, |
2567 | { "stc", { XX }, 0 }, | |
2568 | { "cli", { XX }, 0 }, | |
2569 | { "sti", { XX }, 0 }, | |
2570 | { "cld", { XX }, 0 }, | |
2571 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2572 | { REG_TABLE (REG_FE) }, |
2573 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2574 | }; |
2575 | ||
6439fc28 | 2576 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2577 | /* 00 */ |
1ceb70f8 L |
2578 | { REG_TABLE (REG_0F00 ) }, |
2579 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2580 | { "larS", { Gv, Ew }, 0 }, |
2581 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2582 | { Bad_Opcode }, |
bf890a93 IT |
2583 | { "syscall", { XX }, 0 }, |
2584 | { "clts", { XX }, 0 }, | |
589958d6 | 2585 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2586 | /* 08 */ |
bf890a93 | 2587 | { "invd", { XX }, 0 }, |
3233d7d0 | 2588 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2589 | { Bad_Opcode }, |
bf890a93 | 2590 | { "ud2", { XX }, 0 }, |
592d1631 | 2591 | { Bad_Opcode }, |
b5b1fc4f | 2592 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2593 | { "femms", { XX }, 0 }, |
2594 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2595 | /* 10 */ |
1ceb70f8 L |
2596 | { PREFIX_TABLE (PREFIX_0F10) }, |
2597 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2598 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2599 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2600 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2601 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2602 | { PREFIX_TABLE (PREFIX_0F16) }, |
2603 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2604 | /* 18 */ |
1ceb70f8 | 2605 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2606 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2607 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2608 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2609 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2610 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2611 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2612 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2613 | /* 20 */ |
bf890a93 IT |
2614 | { "movZ", { Rm, Cm }, 0 }, |
2615 | { "movZ", { Rm, Dm }, 0 }, | |
2616 | { "movZ", { Cm, Rm }, 0 }, | |
2617 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2618 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2619 | { Bad_Opcode }, |
1ceb70f8 | 2620 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2621 | { Bad_Opcode }, |
252b5132 | 2622 | /* 28 */ |
507bd325 L |
2623 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2624 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2625 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2626 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2627 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2628 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2629 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2630 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2631 | /* 30 */ |
bf890a93 IT |
2632 | { "wrmsr", { XX }, 0 }, |
2633 | { "rdtsc", { XX }, 0 }, | |
2634 | { "rdmsr", { XX }, 0 }, | |
2635 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2636 | { "sysenter", { SEP }, 0 }, |
2637 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2638 | { Bad_Opcode }, |
bf890a93 | 2639 | { "getsec", { XX }, 0 }, |
252b5132 | 2640 | /* 38 */ |
507bd325 | 2641 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2642 | { Bad_Opcode }, |
507bd325 | 2643 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2644 | { Bad_Opcode }, |
2645 | { Bad_Opcode }, | |
2646 | { Bad_Opcode }, | |
2647 | { Bad_Opcode }, | |
2648 | { Bad_Opcode }, | |
252b5132 | 2649 | /* 40 */ |
bf890a93 IT |
2650 | { "cmovoS", { Gv, Ev }, 0 }, |
2651 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2652 | { "cmovbS", { Gv, Ev }, 0 }, | |
2653 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2654 | { "cmoveS", { Gv, Ev }, 0 }, | |
2655 | { "cmovneS", { Gv, Ev }, 0 }, | |
2656 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2657 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2658 | /* 48 */ |
bf890a93 IT |
2659 | { "cmovsS", { Gv, Ev }, 0 }, |
2660 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2661 | { "cmovpS", { Gv, Ev }, 0 }, | |
2662 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2663 | { "cmovlS", { Gv, Ev }, 0 }, | |
2664 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2665 | { "cmovleS", { Gv, Ev }, 0 }, | |
2666 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2667 | /* 50 */ |
a5aaedb9 | 2668 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2669 | { PREFIX_TABLE (PREFIX_0F51) }, |
2670 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2671 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2672 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2673 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2674 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2675 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2676 | /* 58 */ |
1ceb70f8 L |
2677 | { PREFIX_TABLE (PREFIX_0F58) }, |
2678 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2679 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2680 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2681 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2682 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2683 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2684 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2685 | /* 60 */ |
1ceb70f8 L |
2686 | { PREFIX_TABLE (PREFIX_0F60) }, |
2687 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2688 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2689 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2690 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2691 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2692 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2693 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2694 | /* 68 */ |
507bd325 L |
2695 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2696 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2697 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2698 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2699 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2700 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2701 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2702 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2703 | /* 70 */ |
1ceb70f8 L |
2704 | { PREFIX_TABLE (PREFIX_0F70) }, |
2705 | { REG_TABLE (REG_0F71) }, | |
2706 | { REG_TABLE (REG_0F72) }, | |
2707 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2708 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2709 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2710 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2711 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2712 | /* 78 */ |
1ceb70f8 L |
2713 | { PREFIX_TABLE (PREFIX_0F78) }, |
2714 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2715 | { Bad_Opcode }, |
592d1631 | 2716 | { Bad_Opcode }, |
1ceb70f8 L |
2717 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2718 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2719 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2720 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2721 | /* 80 */ |
bf890a93 IT |
2722 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2723 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2724 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2725 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2726 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2727 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2728 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2729 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2730 | /* 88 */ |
bf890a93 IT |
2731 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2732 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2733 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2734 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2735 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2736 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2737 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2738 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2739 | /* 90 */ |
bf890a93 IT |
2740 | { "seto", { Eb }, 0 }, |
2741 | { "setno", { Eb }, 0 }, | |
2742 | { "setb", { Eb }, 0 }, | |
2743 | { "setae", { Eb }, 0 }, | |
2744 | { "sete", { Eb }, 0 }, | |
2745 | { "setne", { Eb }, 0 }, | |
2746 | { "setbe", { Eb }, 0 }, | |
2747 | { "seta", { Eb }, 0 }, | |
252b5132 | 2748 | /* 98 */ |
bf890a93 IT |
2749 | { "sets", { Eb }, 0 }, |
2750 | { "setns", { Eb }, 0 }, | |
2751 | { "setp", { Eb }, 0 }, | |
2752 | { "setnp", { Eb }, 0 }, | |
2753 | { "setl", { Eb }, 0 }, | |
2754 | { "setge", { Eb }, 0 }, | |
2755 | { "setle", { Eb }, 0 }, | |
2756 | { "setg", { Eb }, 0 }, | |
252b5132 | 2757 | /* a0 */ |
bf890a93 IT |
2758 | { "pushT", { fs }, 0 }, |
2759 | { "popT", { fs }, 0 }, | |
2760 | { "cpuid", { XX }, 0 }, | |
2761 | { "btS", { Ev, Gv }, 0 }, | |
2762 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2763 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2764 | { REG_TABLE (REG_0FA6) }, |
2765 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2766 | /* a8 */ |
bf890a93 IT |
2767 | { "pushT", { gs }, 0 }, |
2768 | { "popT", { gs }, 0 }, | |
2769 | { "rsm", { XX }, 0 }, | |
2770 | { "btsS", { Evh1, Gv }, 0 }, | |
2771 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2772 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2773 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2774 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2775 | /* b0 */ |
bf890a93 IT |
2776 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2777 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2778 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2779 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2780 | { MOD_TABLE (MOD_0FB4) }, |
2781 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2782 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2783 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2784 | /* b8 */ |
1ceb70f8 | 2785 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2786 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2787 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2788 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2789 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2790 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2791 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2792 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2793 | /* c0 */ |
bf890a93 IT |
2794 | { "xaddB", { Ebh1, Gb }, 0 }, |
2795 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2796 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2797 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2798 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2799 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2800 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2801 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2802 | /* c8 */ |
bf890a93 IT |
2803 | { "bswap", { RMeAX }, 0 }, |
2804 | { "bswap", { RMeCX }, 0 }, | |
2805 | { "bswap", { RMeDX }, 0 }, | |
2806 | { "bswap", { RMeBX }, 0 }, | |
2807 | { "bswap", { RMeSP }, 0 }, | |
2808 | { "bswap", { RMeBP }, 0 }, | |
2809 | { "bswap", { RMeSI }, 0 }, | |
2810 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2811 | /* d0 */ |
1ceb70f8 | 2812 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2813 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2814 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2815 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2816 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2817 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2818 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2819 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2820 | /* d8 */ |
507bd325 L |
2821 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2822 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2823 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2824 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2825 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2826 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2827 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2828 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2829 | /* e0 */ |
507bd325 L |
2830 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2831 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2832 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2833 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2834 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2835 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2836 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2837 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2838 | /* e8 */ |
507bd325 L |
2839 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2840 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2841 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2842 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2843 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2844 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2845 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2846 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2847 | /* f0 */ |
1ceb70f8 | 2848 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2849 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2850 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2851 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2852 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2853 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2854 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2855 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2856 | /* f8 */ |
507bd325 L |
2857 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2858 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2859 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2860 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2861 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2862 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2863 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2864 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2865 | }; |
2866 | ||
2867 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2868 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2869 | /* ------------------------------- */ | |
2870 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2871 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2872 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2873 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2874 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2875 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2876 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2877 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2878 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2879 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2880 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2881 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2882 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2883 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2884 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2885 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2886 | /* ------------------------------- */ | |
2887 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2888 | }; |
2889 | ||
2890 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2891 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2892 | /* ------------------------------- */ | |
252b5132 | 2893 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2894 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2895 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2896 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2897 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2898 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2899 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2900 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2901 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2902 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2903 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2904 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2905 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2906 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2907 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2908 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2909 | /* ------------------------------- */ |
2910 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2911 | }; | |
2912 | ||
252b5132 RH |
2913 | static char obuf[100]; |
2914 | static char *obufp; | |
ea397f5b | 2915 | static char *mnemonicendp; |
252b5132 RH |
2916 | static char scratchbuf[100]; |
2917 | static unsigned char *start_codep; | |
2918 | static unsigned char *insn_codep; | |
2919 | static unsigned char *codep; | |
285ca992 | 2920 | static unsigned char *end_codep; |
f16cd0d5 L |
2921 | static int last_lock_prefix; |
2922 | static int last_repz_prefix; | |
2923 | static int last_repnz_prefix; | |
2924 | static int last_data_prefix; | |
2925 | static int last_addr_prefix; | |
2926 | static int last_rex_prefix; | |
2927 | static int last_seg_prefix; | |
d9949a36 | 2928 | static int fwait_prefix; |
285ca992 L |
2929 | /* The active segment register prefix. */ |
2930 | static int active_seg_prefix; | |
f16cd0d5 L |
2931 | #define MAX_CODE_LENGTH 15 |
2932 | /* We can up to 14 prefixes since the maximum instruction length is | |
2933 | 15bytes. */ | |
2934 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2935 | static disassemble_info *the_info; |
7967e09e L |
2936 | static struct |
2937 | { | |
2938 | int mod; | |
7967e09e | 2939 | int reg; |
484c222e | 2940 | int rm; |
7967e09e L |
2941 | } |
2942 | modrm; | |
4bba6815 | 2943 | static unsigned char need_modrm; |
dfc8cf43 L |
2944 | static struct |
2945 | { | |
2946 | int scale; | |
2947 | int index; | |
2948 | int base; | |
2949 | } | |
2950 | sib; | |
c0f3af97 L |
2951 | static struct |
2952 | { | |
2953 | int register_specifier; | |
2954 | int length; | |
2955 | int prefix; | |
2956 | int w; | |
43234a1e L |
2957 | int evex; |
2958 | int r; | |
2959 | int v; | |
2960 | int mask_register_specifier; | |
2961 | int zeroing; | |
2962 | int ll; | |
2963 | int b; | |
c0f3af97 L |
2964 | } |
2965 | vex; | |
2966 | static unsigned char need_vex; | |
252b5132 | 2967 | |
ea397f5b L |
2968 | struct op |
2969 | { | |
2970 | const char *name; | |
2971 | unsigned int len; | |
2972 | }; | |
2973 | ||
4bba6815 AM |
2974 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2975 | values are stale. Hitting this abort likely indicates that you | |
2976 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2977 | #define MODRM_CHECK if (!need_modrm) abort () | |
2978 | ||
d708bcba AM |
2979 | static const char **names64; |
2980 | static const char **names32; | |
2981 | static const char **names16; | |
2982 | static const char **names8; | |
2983 | static const char **names8rex; | |
2984 | static const char **names_seg; | |
db51cc60 L |
2985 | static const char *index64; |
2986 | static const char *index32; | |
d708bcba | 2987 | static const char **index16; |
7e8b059b | 2988 | static const char **names_bnd; |
d708bcba AM |
2989 | |
2990 | static const char *intel_names64[] = { | |
2991 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2992 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2993 | }; | |
2994 | static const char *intel_names32[] = { | |
2995 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2996 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2997 | }; | |
2998 | static const char *intel_names16[] = { | |
2999 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3000 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3001 | }; | |
3002 | static const char *intel_names8[] = { | |
3003 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3004 | }; | |
3005 | static const char *intel_names8rex[] = { | |
3006 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3007 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3008 | }; | |
3009 | static const char *intel_names_seg[] = { | |
3010 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3011 | }; | |
db51cc60 L |
3012 | static const char *intel_index64 = "riz"; |
3013 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3014 | static const char *intel_index16[] = { |
3015 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3016 | }; | |
3017 | ||
3018 | static const char *att_names64[] = { | |
3019 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3020 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3021 | }; | |
d708bcba AM |
3022 | static const char *att_names32[] = { |
3023 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3024 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3025 | }; |
d708bcba AM |
3026 | static const char *att_names16[] = { |
3027 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3028 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3029 | }; |
d708bcba AM |
3030 | static const char *att_names8[] = { |
3031 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3032 | }; |
d708bcba AM |
3033 | static const char *att_names8rex[] = { |
3034 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3035 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3036 | }; | |
d708bcba AM |
3037 | static const char *att_names_seg[] = { |
3038 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3039 | }; |
db51cc60 L |
3040 | static const char *att_index64 = "%riz"; |
3041 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3042 | static const char *att_index16[] = { |
3043 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3044 | }; |
3045 | ||
b9733481 L |
3046 | static const char **names_mm; |
3047 | static const char *intel_names_mm[] = { | |
3048 | "mm0", "mm1", "mm2", "mm3", | |
3049 | "mm4", "mm5", "mm6", "mm7" | |
3050 | }; | |
3051 | static const char *att_names_mm[] = { | |
3052 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3053 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3054 | }; | |
3055 | ||
7e8b059b L |
3056 | static const char *intel_names_bnd[] = { |
3057 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3058 | }; | |
3059 | ||
3060 | static const char *att_names_bnd[] = { | |
3061 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3062 | }; | |
3063 | ||
b9733481 L |
3064 | static const char **names_xmm; |
3065 | static const char *intel_names_xmm[] = { | |
3066 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3067 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3068 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3069 | "xmm12", "xmm13", "xmm14", "xmm15", |
3070 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3071 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3072 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3073 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3074 | }; |
3075 | static const char *att_names_xmm[] = { | |
3076 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3077 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3078 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3079 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3080 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3081 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3082 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3083 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3084 | }; |
3085 | ||
3086 | static const char **names_ymm; | |
3087 | static const char *intel_names_ymm[] = { | |
3088 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3089 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3090 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3091 | "ymm12", "ymm13", "ymm14", "ymm15", |
3092 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3093 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3094 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3095 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3096 | }; |
3097 | static const char *att_names_ymm[] = { | |
3098 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3099 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3100 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3101 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3102 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3103 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3104 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3105 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3106 | }; | |
3107 | ||
3108 | static const char **names_zmm; | |
3109 | static const char *intel_names_zmm[] = { | |
3110 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3111 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3112 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3113 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3114 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3115 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3116 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3117 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3118 | }; | |
3119 | static const char *att_names_zmm[] = { | |
3120 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3121 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3122 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3123 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3124 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3125 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3126 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3127 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3128 | }; | |
3129 | ||
260cd341 LC |
3130 | static const char **names_tmm; |
3131 | static const char *intel_names_tmm[] = { | |
3132 | "tmm0", "tmm1", "tmm2", "tmm3", | |
3133 | "tmm4", "tmm5", "tmm6", "tmm7" | |
3134 | }; | |
3135 | static const char *att_names_tmm[] = { | |
3136 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
3137 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
3138 | }; | |
3139 | ||
43234a1e L |
3140 | static const char **names_mask; |
3141 | static const char *intel_names_mask[] = { | |
3142 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3143 | }; | |
3144 | static const char *att_names_mask[] = { | |
3145 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3146 | }; | |
3147 | ||
3148 | static const char *names_rounding[] = | |
3149 | { | |
3150 | "{rn-sae}", | |
3151 | "{rd-sae}", | |
3152 | "{ru-sae}", | |
3153 | "{rz-sae}" | |
b9733481 L |
3154 | }; |
3155 | ||
1ceb70f8 L |
3156 | static const struct dis386 reg_table[][8] = { |
3157 | /* REG_80 */ | |
252b5132 | 3158 | { |
bf890a93 IT |
3159 | { "addA", { Ebh1, Ib }, 0 }, |
3160 | { "orA", { Ebh1, Ib }, 0 }, | |
3161 | { "adcA", { Ebh1, Ib }, 0 }, | |
3162 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3163 | { "andA", { Ebh1, Ib }, 0 }, | |
3164 | { "subA", { Ebh1, Ib }, 0 }, | |
3165 | { "xorA", { Ebh1, Ib }, 0 }, | |
3166 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3167 | }, |
1ceb70f8 | 3168 | /* REG_81 */ |
252b5132 | 3169 | { |
bf890a93 IT |
3170 | { "addQ", { Evh1, Iv }, 0 }, |
3171 | { "orQ", { Evh1, Iv }, 0 }, | |
3172 | { "adcQ", { Evh1, Iv }, 0 }, | |
3173 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3174 | { "andQ", { Evh1, Iv }, 0 }, | |
3175 | { "subQ", { Evh1, Iv }, 0 }, | |
3176 | { "xorQ", { Evh1, Iv }, 0 }, | |
3177 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3178 | }, |
7148c369 | 3179 | /* REG_83 */ |
252b5132 | 3180 | { |
bf890a93 IT |
3181 | { "addQ", { Evh1, sIb }, 0 }, |
3182 | { "orQ", { Evh1, sIb }, 0 }, | |
3183 | { "adcQ", { Evh1, sIb }, 0 }, | |
3184 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3185 | { "andQ", { Evh1, sIb }, 0 }, | |
3186 | { "subQ", { Evh1, sIb }, 0 }, | |
3187 | { "xorQ", { Evh1, sIb }, 0 }, | |
3188 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3189 | }, |
1ceb70f8 | 3190 | /* REG_8F */ |
4e7d34a6 | 3191 | { |
bf890a93 | 3192 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3193 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3194 | { Bad_Opcode }, |
3195 | { Bad_Opcode }, | |
3196 | { Bad_Opcode }, | |
f88c9eb0 | 3197 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3198 | }, |
1ceb70f8 | 3199 | /* REG_C0 */ |
252b5132 | 3200 | { |
bf890a93 IT |
3201 | { "rolA", { Eb, Ib }, 0 }, |
3202 | { "rorA", { Eb, Ib }, 0 }, | |
3203 | { "rclA", { Eb, Ib }, 0 }, | |
3204 | { "rcrA", { Eb, Ib }, 0 }, | |
3205 | { "shlA", { Eb, Ib }, 0 }, | |
3206 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3207 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3208 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3209 | }, |
1ceb70f8 | 3210 | /* REG_C1 */ |
252b5132 | 3211 | { |
bf890a93 IT |
3212 | { "rolQ", { Ev, Ib }, 0 }, |
3213 | { "rorQ", { Ev, Ib }, 0 }, | |
3214 | { "rclQ", { Ev, Ib }, 0 }, | |
3215 | { "rcrQ", { Ev, Ib }, 0 }, | |
3216 | { "shlQ", { Ev, Ib }, 0 }, | |
3217 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3218 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3219 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3220 | }, |
1ceb70f8 | 3221 | /* REG_C6 */ |
4e7d34a6 | 3222 | { |
bf890a93 | 3223 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3224 | { Bad_Opcode }, |
3225 | { Bad_Opcode }, | |
3226 | { Bad_Opcode }, | |
3227 | { Bad_Opcode }, | |
3228 | { Bad_Opcode }, | |
3229 | { Bad_Opcode }, | |
3230 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3231 | }, |
1ceb70f8 | 3232 | /* REG_C7 */ |
4e7d34a6 | 3233 | { |
bf890a93 | 3234 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3235 | { Bad_Opcode }, |
3236 | { Bad_Opcode }, | |
3237 | { Bad_Opcode }, | |
3238 | { Bad_Opcode }, | |
3239 | { Bad_Opcode }, | |
3240 | { Bad_Opcode }, | |
3241 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3242 | }, |
1ceb70f8 | 3243 | /* REG_D0 */ |
252b5132 | 3244 | { |
bf890a93 IT |
3245 | { "rolA", { Eb, I1 }, 0 }, |
3246 | { "rorA", { Eb, I1 }, 0 }, | |
3247 | { "rclA", { Eb, I1 }, 0 }, | |
3248 | { "rcrA", { Eb, I1 }, 0 }, | |
3249 | { "shlA", { Eb, I1 }, 0 }, | |
3250 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3251 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3252 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3253 | }, |
1ceb70f8 | 3254 | /* REG_D1 */ |
252b5132 | 3255 | { |
bf890a93 IT |
3256 | { "rolQ", { Ev, I1 }, 0 }, |
3257 | { "rorQ", { Ev, I1 }, 0 }, | |
3258 | { "rclQ", { Ev, I1 }, 0 }, | |
3259 | { "rcrQ", { Ev, I1 }, 0 }, | |
3260 | { "shlQ", { Ev, I1 }, 0 }, | |
3261 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3262 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3263 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3264 | }, |
1ceb70f8 | 3265 | /* REG_D2 */ |
252b5132 | 3266 | { |
bf890a93 IT |
3267 | { "rolA", { Eb, CL }, 0 }, |
3268 | { "rorA", { Eb, CL }, 0 }, | |
3269 | { "rclA", { Eb, CL }, 0 }, | |
3270 | { "rcrA", { Eb, CL }, 0 }, | |
3271 | { "shlA", { Eb, CL }, 0 }, | |
3272 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3273 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3274 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3275 | }, |
1ceb70f8 | 3276 | /* REG_D3 */ |
252b5132 | 3277 | { |
bf890a93 IT |
3278 | { "rolQ", { Ev, CL }, 0 }, |
3279 | { "rorQ", { Ev, CL }, 0 }, | |
3280 | { "rclQ", { Ev, CL }, 0 }, | |
3281 | { "rcrQ", { Ev, CL }, 0 }, | |
3282 | { "shlQ", { Ev, CL }, 0 }, | |
3283 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3284 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3285 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3286 | }, |
1ceb70f8 | 3287 | /* REG_F6 */ |
252b5132 | 3288 | { |
bf890a93 | 3289 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3290 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3291 | { "notA", { Ebh1 }, 0 }, |
3292 | { "negA", { Ebh1 }, 0 }, | |
3293 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3294 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3295 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3296 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3297 | }, |
1ceb70f8 | 3298 | /* REG_F7 */ |
252b5132 | 3299 | { |
bf890a93 | 3300 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3301 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3302 | { "notQ", { Evh1 }, 0 }, |
3303 | { "negQ", { Evh1 }, 0 }, | |
3304 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3305 | { "imulQ", { Ev }, 0 }, | |
3306 | { "divQ", { Ev }, 0 }, | |
3307 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3308 | }, |
1ceb70f8 | 3309 | /* REG_FE */ |
252b5132 | 3310 | { |
bf890a93 IT |
3311 | { "incA", { Ebh1 }, 0 }, |
3312 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3313 | }, |
1ceb70f8 | 3314 | /* REG_FF */ |
252b5132 | 3315 | { |
bf890a93 IT |
3316 | { "incQ", { Evh1 }, 0 }, |
3317 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3318 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3319 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3320 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3321 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3322 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3323 | { Bad_Opcode }, |
252b5132 | 3324 | }, |
1ceb70f8 | 3325 | /* REG_0F00 */ |
252b5132 | 3326 | { |
bf890a93 IT |
3327 | { "sldtD", { Sv }, 0 }, |
3328 | { "strD", { Sv }, 0 }, | |
3329 | { "lldt", { Ew }, 0 }, | |
3330 | { "ltr", { Ew }, 0 }, | |
3331 | { "verr", { Ew }, 0 }, | |
3332 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3333 | { Bad_Opcode }, |
3334 | { Bad_Opcode }, | |
252b5132 | 3335 | }, |
1ceb70f8 | 3336 | /* REG_0F01 */ |
252b5132 | 3337 | { |
1ceb70f8 L |
3338 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3339 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3340 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3341 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3342 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3343 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3344 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3345 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3346 | }, |
b5b1fc4f | 3347 | /* REG_0F0D */ |
252b5132 | 3348 | { |
bf890a93 IT |
3349 | { "prefetch", { Mb }, 0 }, |
3350 | { "prefetchw", { Mb }, 0 }, | |
3351 | { "prefetchwt1", { Mb }, 0 }, | |
3352 | { "prefetch", { Mb }, 0 }, | |
3353 | { "prefetch", { Mb }, 0 }, | |
3354 | { "prefetch", { Mb }, 0 }, | |
3355 | { "prefetch", { Mb }, 0 }, | |
3356 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3357 | }, |
1ceb70f8 | 3358 | /* REG_0F18 */ |
252b5132 | 3359 | { |
1ceb70f8 L |
3360 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3361 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3362 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3363 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3364 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3365 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3366 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3367 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3368 | }, |
f8687e93 | 3369 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3370 | { |
3371 | { "cldemote", { Mb }, 0 }, | |
3372 | { "nopQ", { Ev }, 0 }, | |
3373 | { "nopQ", { Ev }, 0 }, | |
3374 | { "nopQ", { Ev }, 0 }, | |
3375 | { "nopQ", { Ev }, 0 }, | |
3376 | { "nopQ", { Ev }, 0 }, | |
3377 | { "nopQ", { Ev }, 0 }, | |
3378 | { "nopQ", { Ev }, 0 }, | |
3379 | }, | |
f8687e93 | 3380 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3381 | { |
3382 | { "nopQ", { Ev }, 0 }, | |
3383 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3384 | { "nopQ", { Ev }, 0 }, | |
3385 | { "nopQ", { Ev }, 0 }, | |
3386 | { "nopQ", { Ev }, 0 }, | |
3387 | { "nopQ", { Ev }, 0 }, | |
3388 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3389 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3390 | }, |
1ceb70f8 | 3391 | /* REG_0F71 */ |
a6bd098c | 3392 | { |
592d1631 L |
3393 | { Bad_Opcode }, |
3394 | { Bad_Opcode }, | |
1ceb70f8 | 3395 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3396 | { Bad_Opcode }, |
1ceb70f8 | 3397 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3398 | { Bad_Opcode }, |
1ceb70f8 | 3399 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3400 | }, |
1ceb70f8 | 3401 | /* REG_0F72 */ |
a6bd098c | 3402 | { |
592d1631 L |
3403 | { Bad_Opcode }, |
3404 | { Bad_Opcode }, | |
1ceb70f8 | 3405 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3406 | { Bad_Opcode }, |
1ceb70f8 | 3407 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3408 | { Bad_Opcode }, |
1ceb70f8 | 3409 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3410 | }, |
1ceb70f8 | 3411 | /* REG_0F73 */ |
252b5132 | 3412 | { |
592d1631 L |
3413 | { Bad_Opcode }, |
3414 | { Bad_Opcode }, | |
1ceb70f8 L |
3415 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3416 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3417 | { Bad_Opcode }, |
3418 | { Bad_Opcode }, | |
1ceb70f8 L |
3419 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3420 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3421 | }, |
1ceb70f8 | 3422 | /* REG_0FA6 */ |
252b5132 | 3423 | { |
bf890a93 IT |
3424 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3425 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3426 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3427 | }, |
1ceb70f8 | 3428 | /* REG_0FA7 */ |
4e7d34a6 | 3429 | { |
bf890a93 IT |
3430 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3431 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3432 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3433 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3434 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3435 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3436 | }, |
1ceb70f8 | 3437 | /* REG_0FAE */ |
4e7d34a6 | 3438 | { |
1ceb70f8 L |
3439 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3440 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3441 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3442 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3443 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3444 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3445 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3446 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3447 | }, |
1ceb70f8 | 3448 | /* REG_0FBA */ |
252b5132 | 3449 | { |
592d1631 L |
3450 | { Bad_Opcode }, |
3451 | { Bad_Opcode }, | |
3452 | { Bad_Opcode }, | |
3453 | { Bad_Opcode }, | |
bf890a93 IT |
3454 | { "btQ", { Ev, Ib }, 0 }, |
3455 | { "btsQ", { Evh1, Ib }, 0 }, | |
3456 | { "btrQ", { Evh1, Ib }, 0 }, | |
3457 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3458 | }, |
1ceb70f8 | 3459 | /* REG_0FC7 */ |
c608c12e | 3460 | { |
592d1631 | 3461 | { Bad_Opcode }, |
bf890a93 | 3462 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3463 | { Bad_Opcode }, |
963f3586 IT |
3464 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3465 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3466 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3467 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3468 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3469 | }, |
592a252b | 3470 | /* REG_VEX_0F71 */ |
c0f3af97 | 3471 | { |
592d1631 L |
3472 | { Bad_Opcode }, |
3473 | { Bad_Opcode }, | |
592a252b | 3474 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3475 | { Bad_Opcode }, |
592a252b | 3476 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3477 | { Bad_Opcode }, |
592a252b | 3478 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3479 | }, |
592a252b | 3480 | /* REG_VEX_0F72 */ |
c0f3af97 | 3481 | { |
592d1631 L |
3482 | { Bad_Opcode }, |
3483 | { Bad_Opcode }, | |
592a252b | 3484 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3485 | { Bad_Opcode }, |
592a252b | 3486 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3487 | { Bad_Opcode }, |
592a252b | 3488 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3489 | }, |
592a252b | 3490 | /* REG_VEX_0F73 */ |
c0f3af97 | 3491 | { |
592d1631 L |
3492 | { Bad_Opcode }, |
3493 | { Bad_Opcode }, | |
592a252b L |
3494 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3495 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3496 | { Bad_Opcode }, |
3497 | { Bad_Opcode }, | |
592a252b L |
3498 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3499 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3500 | }, |
592a252b | 3501 | /* REG_VEX_0FAE */ |
c0f3af97 | 3502 | { |
592d1631 L |
3503 | { Bad_Opcode }, |
3504 | { Bad_Opcode }, | |
592a252b L |
3505 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3506 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3507 | }, |
260cd341 LC |
3508 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3509 | { | |
3510 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3511 | }, | |
f12dc422 L |
3512 | /* REG_VEX_0F38F3 */ |
3513 | { | |
3514 | { Bad_Opcode }, | |
3515 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3516 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3517 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3518 | }, | |
467bbef0 | 3519 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3520 | { |
3521 | { Bad_Opcode }, | |
467bbef0 JB |
3522 | { "blcfill", { VexGdq, Edq }, 0 }, |
3523 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3524 | { "blcs", { VexGdq, Edq }, 0 }, | |
3525 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3526 | { "blcic", { VexGdq, Edq }, 0 }, | |
3527 | { "blsic", { VexGdq, Edq }, 0 }, | |
3528 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3529 | }, |
467bbef0 | 3530 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3531 | { |
3532 | { Bad_Opcode }, | |
467bbef0 | 3533 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3534 | { Bad_Opcode }, |
3535 | { Bad_Opcode }, | |
3536 | { Bad_Opcode }, | |
3537 | { Bad_Opcode }, | |
467bbef0 JB |
3538 | { "blci", { VexGdq, Edq }, 0 }, |
3539 | }, | |
3540 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3541 | { | |
3542 | { "llwpcb", { Edq }, 0 }, | |
3543 | { "slwpcb", { Edq }, 0 }, | |
3544 | }, | |
3545 | /* REG_0FXOP_0A_12_L_0 */ | |
3546 | { | |
3547 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3548 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3549 | }, |
ad692897 L |
3550 | |
3551 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3552 | }; |
3553 | ||
1ceb70f8 L |
3554 | static const struct dis386 prefix_table[][4] = { |
3555 | /* PREFIX_90 */ | |
252b5132 | 3556 | { |
bf890a93 IT |
3557 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3558 | { "pause", { XX }, 0 }, | |
3559 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3560 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3561 | }, |
4e7d34a6 | 3562 | |
f9630fa6 | 3563 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3564 | { |
3565 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3566 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3567 | { Bad_Opcode }, |
3568 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3569 | }, |
3570 | ||
f8687e93 | 3571 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3572 | { |
3573 | { Bad_Opcode }, | |
3574 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3575 | }, | |
3576 | ||
f8687e93 | 3577 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3578 | { |
4b27d27c | 3579 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3580 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3581 | { Bad_Opcode }, |
efe30057 | 3582 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3583 | }, |
3584 | ||
3585 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3586 | { | |
3587 | { Bad_Opcode }, | |
3588 | { Bad_Opcode }, | |
3589 | { Bad_Opcode }, | |
3590 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3591 | }, |
3592 | ||
f8687e93 | 3593 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3594 | { |
3595 | { Bad_Opcode }, | |
c2f76402 | 3596 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3597 | }, |
3598 | ||
267b8516 JB |
3599 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3600 | { | |
3601 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3602 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3603 | }, |
3604 | ||
3605 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3606 | { | |
7abb8d81 | 3607 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3608 | }, |
3609 | ||
3233d7d0 IT |
3610 | /* PREFIX_0F09 */ |
3611 | { | |
3612 | { "wbinvd", { XX }, 0 }, | |
3613 | { "wbnoinvd", { XX }, 0 }, | |
3614 | }, | |
3615 | ||
1ceb70f8 | 3616 | /* PREFIX_0F10 */ |
cc0ec051 | 3617 | { |
507bd325 L |
3618 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3619 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3620 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3621 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3622 | }, |
4e7d34a6 | 3623 | |
1ceb70f8 | 3624 | /* PREFIX_0F11 */ |
30d1c836 | 3625 | { |
507bd325 L |
3626 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3627 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3628 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3629 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3630 | }, |
252b5132 | 3631 | |
1ceb70f8 | 3632 | /* PREFIX_0F12 */ |
c608c12e | 3633 | { |
1ceb70f8 | 3634 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3635 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3636 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3637 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3638 | }, |
4e7d34a6 | 3639 | |
1ceb70f8 | 3640 | /* PREFIX_0F16 */ |
c608c12e | 3641 | { |
1ceb70f8 | 3642 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3643 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3644 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3645 | }, |
4e7d34a6 | 3646 | |
7e8b059b L |
3647 | /* PREFIX_0F1A */ |
3648 | { | |
3649 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3650 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3651 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3652 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3653 | }, |
3654 | ||
3655 | /* PREFIX_0F1B */ | |
3656 | { | |
3657 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3658 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3659 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3660 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3661 | }, |
3662 | ||
c48935d7 IT |
3663 | /* PREFIX_0F1C */ |
3664 | { | |
3665 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3666 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3667 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3668 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3669 | }, | |
3670 | ||
603555e5 L |
3671 | /* PREFIX_0F1E */ |
3672 | { | |
3673 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3674 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3675 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3676 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3677 | }, | |
3678 | ||
1ceb70f8 | 3679 | /* PREFIX_0F2A */ |
c608c12e | 3680 | { |
507bd325 | 3681 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3682 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3683 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3684 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3685 | }, |
4e7d34a6 | 3686 | |
1ceb70f8 | 3687 | /* PREFIX_0F2B */ |
c608c12e | 3688 | { |
75c135a8 L |
3689 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3690 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3691 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3692 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3693 | }, |
4e7d34a6 | 3694 | |
1ceb70f8 | 3695 | /* PREFIX_0F2C */ |
c608c12e | 3696 | { |
507bd325 | 3697 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3698 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3699 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3700 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3701 | }, |
4e7d34a6 | 3702 | |
1ceb70f8 | 3703 | /* PREFIX_0F2D */ |
c608c12e | 3704 | { |
507bd325 | 3705 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3706 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3707 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3708 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3709 | }, |
4e7d34a6 | 3710 | |
1ceb70f8 | 3711 | /* PREFIX_0F2E */ |
c608c12e | 3712 | { |
bf890a93 | 3713 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3714 | { Bad_Opcode }, |
bf890a93 | 3715 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3716 | }, |
4e7d34a6 | 3717 | |
1ceb70f8 | 3718 | /* PREFIX_0F2F */ |
c608c12e | 3719 | { |
bf890a93 | 3720 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3721 | { Bad_Opcode }, |
bf890a93 | 3722 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3723 | }, |
4e7d34a6 | 3724 | |
1ceb70f8 | 3725 | /* PREFIX_0F51 */ |
c608c12e | 3726 | { |
507bd325 L |
3727 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3728 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3729 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3730 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3731 | }, |
4e7d34a6 | 3732 | |
1ceb70f8 | 3733 | /* PREFIX_0F52 */ |
c608c12e | 3734 | { |
507bd325 L |
3735 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3736 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3737 | }, |
4e7d34a6 | 3738 | |
1ceb70f8 | 3739 | /* PREFIX_0F53 */ |
c608c12e | 3740 | { |
507bd325 L |
3741 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3742 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3743 | }, |
4e7d34a6 | 3744 | |
1ceb70f8 | 3745 | /* PREFIX_0F58 */ |
c608c12e | 3746 | { |
507bd325 L |
3747 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3748 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3749 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3750 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3751 | }, |
4e7d34a6 | 3752 | |
1ceb70f8 | 3753 | /* PREFIX_0F59 */ |
c608c12e | 3754 | { |
507bd325 L |
3755 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3756 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3757 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3758 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3759 | }, |
4e7d34a6 | 3760 | |
1ceb70f8 | 3761 | /* PREFIX_0F5A */ |
041bd2e0 | 3762 | { |
507bd325 L |
3763 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3764 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3765 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3766 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3767 | }, |
4e7d34a6 | 3768 | |
1ceb70f8 | 3769 | /* PREFIX_0F5B */ |
041bd2e0 | 3770 | { |
507bd325 L |
3771 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3772 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3773 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3774 | }, |
4e7d34a6 | 3775 | |
1ceb70f8 | 3776 | /* PREFIX_0F5C */ |
041bd2e0 | 3777 | { |
507bd325 L |
3778 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3779 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3780 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3781 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3782 | }, |
4e7d34a6 | 3783 | |
1ceb70f8 | 3784 | /* PREFIX_0F5D */ |
041bd2e0 | 3785 | { |
507bd325 L |
3786 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3787 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3788 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3789 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3790 | }, |
4e7d34a6 | 3791 | |
1ceb70f8 | 3792 | /* PREFIX_0F5E */ |
041bd2e0 | 3793 | { |
507bd325 L |
3794 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3795 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3796 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3797 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3798 | }, |
4e7d34a6 | 3799 | |
1ceb70f8 | 3800 | /* PREFIX_0F5F */ |
041bd2e0 | 3801 | { |
507bd325 L |
3802 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3803 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3804 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3805 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3806 | }, |
4e7d34a6 | 3807 | |
1ceb70f8 | 3808 | /* PREFIX_0F60 */ |
041bd2e0 | 3809 | { |
507bd325 | 3810 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3811 | { Bad_Opcode }, |
507bd325 | 3812 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3813 | }, |
4e7d34a6 | 3814 | |
1ceb70f8 | 3815 | /* PREFIX_0F61 */ |
041bd2e0 | 3816 | { |
507bd325 | 3817 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3818 | { Bad_Opcode }, |
507bd325 | 3819 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3820 | }, |
4e7d34a6 | 3821 | |
1ceb70f8 | 3822 | /* PREFIX_0F62 */ |
041bd2e0 | 3823 | { |
507bd325 | 3824 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3825 | { Bad_Opcode }, |
507bd325 | 3826 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3827 | }, |
4e7d34a6 | 3828 | |
1ceb70f8 | 3829 | /* PREFIX_0F6C */ |
041bd2e0 | 3830 | { |
592d1631 L |
3831 | { Bad_Opcode }, |
3832 | { Bad_Opcode }, | |
507bd325 | 3833 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3834 | }, |
4e7d34a6 | 3835 | |
1ceb70f8 | 3836 | /* PREFIX_0F6D */ |
0f17484f | 3837 | { |
592d1631 L |
3838 | { Bad_Opcode }, |
3839 | { Bad_Opcode }, | |
507bd325 | 3840 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3841 | }, |
4e7d34a6 | 3842 | |
1ceb70f8 | 3843 | /* PREFIX_0F6F */ |
ca164297 | 3844 | { |
507bd325 L |
3845 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3846 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3847 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3848 | }, |
4e7d34a6 | 3849 | |
1ceb70f8 | 3850 | /* PREFIX_0F70 */ |
4e7d34a6 | 3851 | { |
507bd325 L |
3852 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3853 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3854 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3855 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3856 | }, |
3857 | ||
92fddf8e L |
3858 | /* PREFIX_0F73_REG_3 */ |
3859 | { | |
592d1631 L |
3860 | { Bad_Opcode }, |
3861 | { Bad_Opcode }, | |
bf890a93 | 3862 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3863 | }, |
3864 | ||
3865 | /* PREFIX_0F73_REG_7 */ | |
3866 | { | |
592d1631 L |
3867 | { Bad_Opcode }, |
3868 | { Bad_Opcode }, | |
bf890a93 | 3869 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3870 | }, |
3871 | ||
1ceb70f8 | 3872 | /* PREFIX_0F78 */ |
4e7d34a6 | 3873 | { |
bf890a93 | 3874 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3875 | { Bad_Opcode }, |
bf890a93 IT |
3876 | {"extrq", { XS, Ib, Ib }, 0 }, |
3877 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3878 | }, |
3879 | ||
1ceb70f8 | 3880 | /* PREFIX_0F79 */ |
4e7d34a6 | 3881 | { |
bf890a93 | 3882 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3883 | { Bad_Opcode }, |
bf890a93 IT |
3884 | {"extrq", { XM, XS }, 0 }, |
3885 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3886 | }, |
3887 | ||
1ceb70f8 | 3888 | /* PREFIX_0F7C */ |
ca164297 | 3889 | { |
592d1631 L |
3890 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, | |
507bd325 L |
3892 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3893 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3894 | }, |
4e7d34a6 | 3895 | |
1ceb70f8 | 3896 | /* PREFIX_0F7D */ |
ca164297 | 3897 | { |
592d1631 L |
3898 | { Bad_Opcode }, |
3899 | { Bad_Opcode }, | |
507bd325 L |
3900 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3901 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3902 | }, |
4e7d34a6 | 3903 | |
1ceb70f8 | 3904 | /* PREFIX_0F7E */ |
ca164297 | 3905 | { |
507bd325 L |
3906 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3907 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3908 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3909 | }, |
4e7d34a6 | 3910 | |
1ceb70f8 | 3911 | /* PREFIX_0F7F */ |
ca164297 | 3912 | { |
507bd325 L |
3913 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3914 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3915 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3916 | }, |
4e7d34a6 | 3917 | |
f8687e93 | 3918 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3919 | { |
3920 | { Bad_Opcode }, | |
bf890a93 | 3921 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3922 | }, |
3923 | ||
f8687e93 | 3924 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3925 | { |
3926 | { Bad_Opcode }, | |
bf890a93 | 3927 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3928 | }, |
3929 | ||
f8687e93 | 3930 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3931 | { |
3932 | { Bad_Opcode }, | |
bf890a93 | 3933 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3934 | }, |
3935 | ||
f8687e93 | 3936 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3937 | { |
3938 | { Bad_Opcode }, | |
bf890a93 | 3939 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3940 | }, |
3941 | ||
f8687e93 | 3942 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3943 | { |
3944 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3945 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3946 | }, |
3947 | ||
f8687e93 | 3948 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3949 | { |
3950 | { Bad_Opcode }, | |
b24d668c | 3951 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3952 | }, |
3953 | ||
f8687e93 | 3954 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3955 | { |
3956 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3957 | }, |
3958 | ||
f8687e93 | 3959 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3960 | { |
3961 | { "lfence", { Skip_MODRM }, 0 }, | |
3962 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3963 | }, |
3964 | ||
f8687e93 | 3965 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3966 | { |
603555e5 L |
3967 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3968 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3969 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3970 | }, |
3971 | ||
f8687e93 | 3972 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3973 | { |
f8687e93 | 3974 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3975 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3976 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3977 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3978 | }, |
3979 | ||
f8687e93 | 3980 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3981 | { |
bf890a93 | 3982 | { "clflush", { Mb }, 0 }, |
963f3586 | 3983 | { Bad_Opcode }, |
bf890a93 | 3984 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3985 | }, |
3986 | ||
1ceb70f8 | 3987 | /* PREFIX_0FB8 */ |
ca164297 | 3988 | { |
592d1631 | 3989 | { Bad_Opcode }, |
bf890a93 | 3990 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3991 | }, |
4e7d34a6 | 3992 | |
f12dc422 L |
3993 | /* PREFIX_0FBC */ |
3994 | { | |
bf890a93 IT |
3995 | { "bsfS", { Gv, Ev }, 0 }, |
3996 | { "tzcntS", { Gv, Ev }, 0 }, | |
3997 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3998 | }, |
3999 | ||
1ceb70f8 | 4000 | /* PREFIX_0FBD */ |
050dfa73 | 4001 | { |
bf890a93 IT |
4002 | { "bsrS", { Gv, Ev }, 0 }, |
4003 | { "lzcntS", { Gv, Ev }, 0 }, | |
4004 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4005 | }, |
4006 | ||
1ceb70f8 | 4007 | /* PREFIX_0FC2 */ |
050dfa73 | 4008 | { |
507bd325 L |
4009 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4010 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4011 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4012 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4013 | }, |
246c51aa | 4014 | |
f8687e93 | 4015 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4016 | { |
e1a1babd | 4017 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4018 | }, |
4019 | ||
f8687e93 | 4020 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4021 | { |
bf890a93 IT |
4022 | { "vmptrld",{ Mq }, 0 }, |
4023 | { "vmxon", { Mq }, 0 }, | |
4024 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4025 | }, |
4026 | ||
f8687e93 | 4027 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4028 | { |
4029 | { "rdrand", { Ev }, 0 }, | |
4030 | { Bad_Opcode }, | |
4031 | { "rdrand", { Ev }, 0 } | |
4032 | }, | |
4033 | ||
f8687e93 | 4034 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4035 | { |
4036 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4037 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4038 | { "rdseed", { Ev }, 0 }, |
4039 | }, | |
4040 | ||
1ceb70f8 | 4041 | /* PREFIX_0FD0 */ |
050dfa73 | 4042 | { |
592d1631 L |
4043 | { Bad_Opcode }, |
4044 | { Bad_Opcode }, | |
bf890a93 IT |
4045 | { "addsubpd", { XM, EXx }, 0 }, |
4046 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4047 | }, |
050dfa73 | 4048 | |
1ceb70f8 | 4049 | /* PREFIX_0FD6 */ |
050dfa73 | 4050 | { |
592d1631 | 4051 | { Bad_Opcode }, |
bf890a93 IT |
4052 | { "movq2dq",{ XM, MS }, 0 }, |
4053 | { "movq", { EXqS, XM }, 0 }, | |
4054 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4055 | }, |
4056 | ||
1ceb70f8 | 4057 | /* PREFIX_0FE6 */ |
7918206c | 4058 | { |
592d1631 | 4059 | { Bad_Opcode }, |
507bd325 L |
4060 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4061 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4062 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4063 | }, |
8b38ad71 | 4064 | |
1ceb70f8 | 4065 | /* PREFIX_0FE7 */ |
8b38ad71 | 4066 | { |
507bd325 | 4067 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4068 | { Bad_Opcode }, |
75c135a8 | 4069 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4070 | }, |
4071 | ||
1ceb70f8 | 4072 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4073 | { |
592d1631 L |
4074 | { Bad_Opcode }, |
4075 | { Bad_Opcode }, | |
4076 | { Bad_Opcode }, | |
1ceb70f8 | 4077 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4078 | }, |
4079 | ||
1ceb70f8 | 4080 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4081 | { |
507bd325 | 4082 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4083 | { Bad_Opcode }, |
507bd325 | 4084 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4085 | }, |
42903f7f | 4086 | |
1ceb70f8 | 4087 | /* PREFIX_0F3810 */ |
42903f7f | 4088 | { |
592d1631 L |
4089 | { Bad_Opcode }, |
4090 | { Bad_Opcode }, | |
507bd325 | 4091 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4092 | }, |
4093 | ||
1ceb70f8 | 4094 | /* PREFIX_0F3814 */ |
42903f7f | 4095 | { |
592d1631 L |
4096 | { Bad_Opcode }, |
4097 | { Bad_Opcode }, | |
507bd325 | 4098 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4099 | }, |
4100 | ||
1ceb70f8 | 4101 | /* PREFIX_0F3815 */ |
42903f7f | 4102 | { |
592d1631 L |
4103 | { Bad_Opcode }, |
4104 | { Bad_Opcode }, | |
507bd325 | 4105 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4106 | }, |
4107 | ||
1ceb70f8 | 4108 | /* PREFIX_0F3817 */ |
42903f7f | 4109 | { |
592d1631 L |
4110 | { Bad_Opcode }, |
4111 | { Bad_Opcode }, | |
507bd325 | 4112 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4113 | }, |
4114 | ||
1ceb70f8 | 4115 | /* PREFIX_0F3820 */ |
42903f7f | 4116 | { |
592d1631 L |
4117 | { Bad_Opcode }, |
4118 | { Bad_Opcode }, | |
507bd325 | 4119 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4120 | }, |
4121 | ||
1ceb70f8 | 4122 | /* PREFIX_0F3821 */ |
42903f7f | 4123 | { |
592d1631 L |
4124 | { Bad_Opcode }, |
4125 | { Bad_Opcode }, | |
507bd325 | 4126 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4127 | }, |
4128 | ||
1ceb70f8 | 4129 | /* PREFIX_0F3822 */ |
42903f7f | 4130 | { |
592d1631 L |
4131 | { Bad_Opcode }, |
4132 | { Bad_Opcode }, | |
507bd325 | 4133 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4134 | }, |
4135 | ||
1ceb70f8 | 4136 | /* PREFIX_0F3823 */ |
42903f7f | 4137 | { |
592d1631 L |
4138 | { Bad_Opcode }, |
4139 | { Bad_Opcode }, | |
507bd325 | 4140 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4141 | }, |
4142 | ||
1ceb70f8 | 4143 | /* PREFIX_0F3824 */ |
42903f7f | 4144 | { |
592d1631 L |
4145 | { Bad_Opcode }, |
4146 | { Bad_Opcode }, | |
507bd325 | 4147 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4148 | }, |
4149 | ||
1ceb70f8 | 4150 | /* PREFIX_0F3825 */ |
42903f7f | 4151 | { |
592d1631 L |
4152 | { Bad_Opcode }, |
4153 | { Bad_Opcode }, | |
507bd325 | 4154 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4155 | }, |
4156 | ||
1ceb70f8 | 4157 | /* PREFIX_0F3828 */ |
42903f7f | 4158 | { |
592d1631 L |
4159 | { Bad_Opcode }, |
4160 | { Bad_Opcode }, | |
507bd325 | 4161 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4162 | }, |
4163 | ||
1ceb70f8 | 4164 | /* PREFIX_0F3829 */ |
42903f7f | 4165 | { |
592d1631 L |
4166 | { Bad_Opcode }, |
4167 | { Bad_Opcode }, | |
507bd325 | 4168 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4169 | }, |
4170 | ||
1ceb70f8 | 4171 | /* PREFIX_0F382A */ |
42903f7f | 4172 | { |
592d1631 L |
4173 | { Bad_Opcode }, |
4174 | { Bad_Opcode }, | |
75c135a8 | 4175 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4176 | }, |
4177 | ||
1ceb70f8 | 4178 | /* PREFIX_0F382B */ |
42903f7f | 4179 | { |
592d1631 L |
4180 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, | |
507bd325 | 4182 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4183 | }, |
4184 | ||
1ceb70f8 | 4185 | /* PREFIX_0F3830 */ |
42903f7f | 4186 | { |
592d1631 L |
4187 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, | |
507bd325 | 4189 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4190 | }, |
4191 | ||
1ceb70f8 | 4192 | /* PREFIX_0F3831 */ |
42903f7f | 4193 | { |
592d1631 L |
4194 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, | |
507bd325 | 4196 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4197 | }, |
4198 | ||
1ceb70f8 | 4199 | /* PREFIX_0F3832 */ |
42903f7f | 4200 | { |
592d1631 L |
4201 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, | |
507bd325 | 4203 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4204 | }, |
4205 | ||
1ceb70f8 | 4206 | /* PREFIX_0F3833 */ |
42903f7f | 4207 | { |
592d1631 L |
4208 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, | |
507bd325 | 4210 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4211 | }, |
4212 | ||
1ceb70f8 | 4213 | /* PREFIX_0F3834 */ |
42903f7f | 4214 | { |
592d1631 L |
4215 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, | |
507bd325 | 4217 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4218 | }, |
4219 | ||
1ceb70f8 | 4220 | /* PREFIX_0F3835 */ |
42903f7f | 4221 | { |
592d1631 L |
4222 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, | |
507bd325 | 4224 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4225 | }, |
4226 | ||
1ceb70f8 | 4227 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4228 | { |
592d1631 L |
4229 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, | |
507bd325 | 4231 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4232 | }, |
4233 | ||
1ceb70f8 | 4234 | /* PREFIX_0F3838 */ |
42903f7f | 4235 | { |
592d1631 L |
4236 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, | |
507bd325 | 4238 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4239 | }, |
4240 | ||
1ceb70f8 | 4241 | /* PREFIX_0F3839 */ |
42903f7f | 4242 | { |
592d1631 L |
4243 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, | |
507bd325 | 4245 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4246 | }, |
4247 | ||
1ceb70f8 | 4248 | /* PREFIX_0F383A */ |
42903f7f | 4249 | { |
592d1631 L |
4250 | { Bad_Opcode }, |
4251 | { Bad_Opcode }, | |
507bd325 | 4252 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4253 | }, |
4254 | ||
1ceb70f8 | 4255 | /* PREFIX_0F383B */ |
42903f7f | 4256 | { |
592d1631 L |
4257 | { Bad_Opcode }, |
4258 | { Bad_Opcode }, | |
507bd325 | 4259 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4260 | }, |
4261 | ||
1ceb70f8 | 4262 | /* PREFIX_0F383C */ |
42903f7f | 4263 | { |
592d1631 L |
4264 | { Bad_Opcode }, |
4265 | { Bad_Opcode }, | |
507bd325 | 4266 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4267 | }, |
4268 | ||
1ceb70f8 | 4269 | /* PREFIX_0F383D */ |
42903f7f | 4270 | { |
592d1631 L |
4271 | { Bad_Opcode }, |
4272 | { Bad_Opcode }, | |
507bd325 | 4273 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4274 | }, |
4275 | ||
1ceb70f8 | 4276 | /* PREFIX_0F383E */ |
42903f7f | 4277 | { |
592d1631 L |
4278 | { Bad_Opcode }, |
4279 | { Bad_Opcode }, | |
507bd325 | 4280 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4281 | }, |
4282 | ||
1ceb70f8 | 4283 | /* PREFIX_0F383F */ |
42903f7f | 4284 | { |
592d1631 L |
4285 | { Bad_Opcode }, |
4286 | { Bad_Opcode }, | |
507bd325 | 4287 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4288 | }, |
4289 | ||
1ceb70f8 | 4290 | /* PREFIX_0F3840 */ |
42903f7f | 4291 | { |
592d1631 L |
4292 | { Bad_Opcode }, |
4293 | { Bad_Opcode }, | |
507bd325 | 4294 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4295 | }, |
4296 | ||
1ceb70f8 | 4297 | /* PREFIX_0F3841 */ |
42903f7f | 4298 | { |
592d1631 L |
4299 | { Bad_Opcode }, |
4300 | { Bad_Opcode }, | |
507bd325 | 4301 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4302 | }, |
4303 | ||
f1f8f695 L |
4304 | /* PREFIX_0F3880 */ |
4305 | { | |
592d1631 L |
4306 | { Bad_Opcode }, |
4307 | { Bad_Opcode }, | |
507bd325 | 4308 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4309 | }, |
4310 | ||
4311 | /* PREFIX_0F3881 */ | |
4312 | { | |
592d1631 L |
4313 | { Bad_Opcode }, |
4314 | { Bad_Opcode }, | |
507bd325 | 4315 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4316 | }, |
4317 | ||
6c30d220 L |
4318 | /* PREFIX_0F3882 */ |
4319 | { | |
4320 | { Bad_Opcode }, | |
4321 | { Bad_Opcode }, | |
507bd325 | 4322 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4323 | }, |
4324 | ||
a0046408 L |
4325 | /* PREFIX_0F38C8 */ |
4326 | { | |
507bd325 | 4327 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4328 | }, |
4329 | ||
4330 | /* PREFIX_0F38C9 */ | |
4331 | { | |
507bd325 | 4332 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4333 | }, |
4334 | ||
4335 | /* PREFIX_0F38CA */ | |
4336 | { | |
507bd325 | 4337 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4338 | }, |
4339 | ||
4340 | /* PREFIX_0F38CB */ | |
4341 | { | |
507bd325 | 4342 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4343 | }, |
4344 | ||
4345 | /* PREFIX_0F38CC */ | |
4346 | { | |
507bd325 | 4347 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4348 | }, |
4349 | ||
4350 | /* PREFIX_0F38CD */ | |
4351 | { | |
507bd325 | 4352 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4353 | }, |
4354 | ||
48521003 IT |
4355 | /* PREFIX_0F38CF */ |
4356 | { | |
4357 | { Bad_Opcode }, | |
4358 | { Bad_Opcode }, | |
4359 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4360 | }, | |
4361 | ||
c0f3af97 L |
4362 | /* PREFIX_0F38DB */ |
4363 | { | |
592d1631 L |
4364 | { Bad_Opcode }, |
4365 | { Bad_Opcode }, | |
507bd325 | 4366 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4367 | }, |
4368 | ||
4369 | /* PREFIX_0F38DC */ | |
4370 | { | |
592d1631 L |
4371 | { Bad_Opcode }, |
4372 | { Bad_Opcode }, | |
507bd325 | 4373 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4374 | }, |
4375 | ||
4376 | /* PREFIX_0F38DD */ | |
4377 | { | |
592d1631 L |
4378 | { Bad_Opcode }, |
4379 | { Bad_Opcode }, | |
507bd325 | 4380 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4381 | }, |
4382 | ||
4383 | /* PREFIX_0F38DE */ | |
4384 | { | |
592d1631 L |
4385 | { Bad_Opcode }, |
4386 | { Bad_Opcode }, | |
507bd325 | 4387 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4388 | }, |
4389 | ||
4390 | /* PREFIX_0F38DF */ | |
4391 | { | |
592d1631 L |
4392 | { Bad_Opcode }, |
4393 | { Bad_Opcode }, | |
507bd325 | 4394 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4395 | }, |
4396 | ||
1ceb70f8 | 4397 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4398 | { |
9ab00b61 | 4399 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 4400 | { Bad_Opcode }, |
9ab00b61 | 4401 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 4402 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
4403 | }, |
4404 | ||
1ceb70f8 | 4405 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4406 | { |
9ab00b61 | 4407 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 4408 | { Bad_Opcode }, |
9ab00b61 | 4409 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 4410 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
4411 | }, |
4412 | ||
603555e5 | 4413 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4414 | { |
4415 | { Bad_Opcode }, | |
603555e5 L |
4416 | { Bad_Opcode }, |
4417 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4418 | }, | |
4419 | ||
4420 | /* PREFIX_0F38F6 */ | |
4421 | { | |
4422 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4423 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4424 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4425 | { Bad_Opcode }, |
4426 | }, | |
4427 | ||
c0a30a9f L |
4428 | /* PREFIX_0F38F8 */ |
4429 | { | |
4430 | { Bad_Opcode }, | |
5d79adc4 | 4431 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4432 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4433 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4434 | }, |
4435 | ||
4436 | /* PREFIX_0F38F9 */ | |
4437 | { | |
4438 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4439 | }, | |
4440 | ||
1ceb70f8 | 4441 | /* PREFIX_0F3A08 */ |
42903f7f | 4442 | { |
592d1631 L |
4443 | { Bad_Opcode }, |
4444 | { Bad_Opcode }, | |
507bd325 | 4445 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4446 | }, |
4447 | ||
1ceb70f8 | 4448 | /* PREFIX_0F3A09 */ |
42903f7f | 4449 | { |
592d1631 L |
4450 | { Bad_Opcode }, |
4451 | { Bad_Opcode }, | |
507bd325 | 4452 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4453 | }, |
4454 | ||
1ceb70f8 | 4455 | /* PREFIX_0F3A0A */ |
42903f7f | 4456 | { |
592d1631 L |
4457 | { Bad_Opcode }, |
4458 | { Bad_Opcode }, | |
507bd325 | 4459 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4460 | }, |
4461 | ||
1ceb70f8 | 4462 | /* PREFIX_0F3A0B */ |
42903f7f | 4463 | { |
592d1631 L |
4464 | { Bad_Opcode }, |
4465 | { Bad_Opcode }, | |
507bd325 | 4466 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4467 | }, |
4468 | ||
1ceb70f8 | 4469 | /* PREFIX_0F3A0C */ |
42903f7f | 4470 | { |
592d1631 L |
4471 | { Bad_Opcode }, |
4472 | { Bad_Opcode }, | |
507bd325 | 4473 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4474 | }, |
4475 | ||
1ceb70f8 | 4476 | /* PREFIX_0F3A0D */ |
42903f7f | 4477 | { |
592d1631 L |
4478 | { Bad_Opcode }, |
4479 | { Bad_Opcode }, | |
507bd325 | 4480 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4481 | }, |
4482 | ||
1ceb70f8 | 4483 | /* PREFIX_0F3A0E */ |
42903f7f | 4484 | { |
592d1631 L |
4485 | { Bad_Opcode }, |
4486 | { Bad_Opcode }, | |
507bd325 | 4487 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4488 | }, |
4489 | ||
1ceb70f8 | 4490 | /* PREFIX_0F3A14 */ |
42903f7f | 4491 | { |
592d1631 L |
4492 | { Bad_Opcode }, |
4493 | { Bad_Opcode }, | |
507bd325 | 4494 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4495 | }, |
4496 | ||
1ceb70f8 | 4497 | /* PREFIX_0F3A15 */ |
42903f7f | 4498 | { |
592d1631 L |
4499 | { Bad_Opcode }, |
4500 | { Bad_Opcode }, | |
507bd325 | 4501 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4502 | }, |
4503 | ||
1ceb70f8 | 4504 | /* PREFIX_0F3A16 */ |
42903f7f | 4505 | { |
592d1631 L |
4506 | { Bad_Opcode }, |
4507 | { Bad_Opcode }, | |
507bd325 | 4508 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4509 | }, |
4510 | ||
1ceb70f8 | 4511 | /* PREFIX_0F3A17 */ |
42903f7f | 4512 | { |
592d1631 L |
4513 | { Bad_Opcode }, |
4514 | { Bad_Opcode }, | |
507bd325 | 4515 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4516 | }, |
4517 | ||
1ceb70f8 | 4518 | /* PREFIX_0F3A20 */ |
42903f7f | 4519 | { |
592d1631 L |
4520 | { Bad_Opcode }, |
4521 | { Bad_Opcode }, | |
507bd325 | 4522 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4523 | }, |
4524 | ||
1ceb70f8 | 4525 | /* PREFIX_0F3A21 */ |
42903f7f | 4526 | { |
592d1631 L |
4527 | { Bad_Opcode }, |
4528 | { Bad_Opcode }, | |
507bd325 | 4529 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4530 | }, |
4531 | ||
1ceb70f8 | 4532 | /* PREFIX_0F3A22 */ |
42903f7f | 4533 | { |
592d1631 L |
4534 | { Bad_Opcode }, |
4535 | { Bad_Opcode }, | |
507bd325 | 4536 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4537 | }, |
4538 | ||
1ceb70f8 | 4539 | /* PREFIX_0F3A40 */ |
42903f7f | 4540 | { |
592d1631 L |
4541 | { Bad_Opcode }, |
4542 | { Bad_Opcode }, | |
507bd325 | 4543 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4544 | }, |
4545 | ||
1ceb70f8 | 4546 | /* PREFIX_0F3A41 */ |
42903f7f | 4547 | { |
592d1631 L |
4548 | { Bad_Opcode }, |
4549 | { Bad_Opcode }, | |
507bd325 | 4550 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4551 | }, |
4552 | ||
1ceb70f8 | 4553 | /* PREFIX_0F3A42 */ |
42903f7f | 4554 | { |
592d1631 L |
4555 | { Bad_Opcode }, |
4556 | { Bad_Opcode }, | |
507bd325 | 4557 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4558 | }, |
381d071f | 4559 | |
c0f3af97 L |
4560 | /* PREFIX_0F3A44 */ |
4561 | { | |
592d1631 L |
4562 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, | |
507bd325 | 4564 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4565 | }, |
4566 | ||
1ceb70f8 | 4567 | /* PREFIX_0F3A60 */ |
381d071f | 4568 | { |
592d1631 L |
4569 | { Bad_Opcode }, |
4570 | { Bad_Opcode }, | |
b24d668c | 4571 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4572 | }, |
4573 | ||
1ceb70f8 | 4574 | /* PREFIX_0F3A61 */ |
381d071f | 4575 | { |
592d1631 L |
4576 | { Bad_Opcode }, |
4577 | { Bad_Opcode }, | |
b24d668c | 4578 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4579 | }, |
4580 | ||
1ceb70f8 | 4581 | /* PREFIX_0F3A62 */ |
381d071f | 4582 | { |
592d1631 L |
4583 | { Bad_Opcode }, |
4584 | { Bad_Opcode }, | |
507bd325 | 4585 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4586 | }, |
4587 | ||
1ceb70f8 | 4588 | /* PREFIX_0F3A63 */ |
381d071f | 4589 | { |
592d1631 L |
4590 | { Bad_Opcode }, |
4591 | { Bad_Opcode }, | |
507bd325 | 4592 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4593 | }, |
09a2c6cf | 4594 | |
a0046408 L |
4595 | /* PREFIX_0F3ACC */ |
4596 | { | |
507bd325 | 4597 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4598 | }, |
4599 | ||
48521003 IT |
4600 | /* PREFIX_0F3ACE */ |
4601 | { | |
4602 | { Bad_Opcode }, | |
4603 | { Bad_Opcode }, | |
4604 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4605 | }, | |
4606 | ||
4607 | /* PREFIX_0F3ACF */ | |
4608 | { | |
4609 | { Bad_Opcode }, | |
4610 | { Bad_Opcode }, | |
4611 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4612 | }, | |
4613 | ||
c0f3af97 | 4614 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4615 | { |
592d1631 L |
4616 | { Bad_Opcode }, |
4617 | { Bad_Opcode }, | |
507bd325 | 4618 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4619 | }, |
4620 | ||
592a252b | 4621 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4622 | { |
ec6f095a | 4623 | { "vmovups", { XM, EXx }, 0 }, |
41f5efc6 | 4624 | { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 }, |
ec6f095a | 4625 | { "vmovupd", { XM, EXx }, 0 }, |
41f5efc6 | 4626 | { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 }, |
09a2c6cf L |
4627 | }, |
4628 | ||
592a252b | 4629 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4630 | { |
ec6f095a | 4631 | { "vmovups", { EXxS, XM }, 0 }, |
41f5efc6 | 4632 | { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 }, |
ec6f095a | 4633 | { "vmovupd", { EXxS, XM }, 0 }, |
41f5efc6 | 4634 | { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 }, |
09a2c6cf L |
4635 | }, |
4636 | ||
592a252b | 4637 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4638 | { |
592a252b | 4639 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4640 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4641 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4642 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4643 | }, |
4644 | ||
592a252b | 4645 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4646 | { |
592a252b | 4647 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4648 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4649 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4650 | }, |
7c52e0e8 | 4651 | |
592a252b | 4652 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4653 | { |
592d1631 | 4654 | { Bad_Opcode }, |
b24d668c | 4655 | { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4656 | { Bad_Opcode }, |
b24d668c | 4657 | { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4658 | }, |
7c52e0e8 | 4659 | |
592a252b | 4660 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4661 | { |
592d1631 | 4662 | { Bad_Opcode }, |
17d3c7ec | 4663 | { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
592d1631 | 4664 | { Bad_Opcode }, |
17d3c7ec | 4665 | { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
5f754f58 | 4666 | }, |
7c52e0e8 | 4667 | |
592a252b | 4668 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4669 | { |
592d1631 | 4670 | { Bad_Opcode }, |
17d3c7ec | 4671 | { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
592d1631 | 4672 | { Bad_Opcode }, |
17d3c7ec | 4673 | { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
7c52e0e8 L |
4674 | }, |
4675 | ||
592a252b | 4676 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4677 | { |
17d3c7ec | 4678 | { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 4679 | { Bad_Opcode }, |
17d3c7ec | 4680 | { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
4681 | }, |
4682 | ||
592a252b | 4683 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4684 | { |
17d3c7ec | 4685 | { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 4686 | { Bad_Opcode }, |
17d3c7ec | 4687 | { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
4688 | }, |
4689 | ||
43234a1e L |
4690 | /* PREFIX_VEX_0F41 */ |
4691 | { | |
4692 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4693 | { Bad_Opcode }, |
4694 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4695 | }, |
4696 | ||
4697 | /* PREFIX_VEX_0F42 */ | |
4698 | { | |
4699 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4700 | { Bad_Opcode }, |
4701 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4702 | }, |
4703 | ||
4704 | /* PREFIX_VEX_0F44 */ | |
4705 | { | |
4706 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4707 | { Bad_Opcode }, |
4708 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4709 | }, |
4710 | ||
4711 | /* PREFIX_VEX_0F45 */ | |
4712 | { | |
4713 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4714 | { Bad_Opcode }, |
4715 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4716 | }, |
4717 | ||
4718 | /* PREFIX_VEX_0F46 */ | |
4719 | { | |
4720 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4721 | { Bad_Opcode }, |
4722 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4723 | }, |
4724 | ||
4725 | /* PREFIX_VEX_0F47 */ | |
4726 | { | |
4727 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4728 | { Bad_Opcode }, |
4729 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4730 | }, |
4731 | ||
1ba585e8 | 4732 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4733 | { |
1ba585e8 | 4734 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4735 | { Bad_Opcode }, |
1ba585e8 IT |
4736 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4737 | }, | |
4738 | ||
4739 | /* PREFIX_VEX_0F4B */ | |
4740 | { | |
4741 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4742 | { Bad_Opcode }, |
4743 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4744 | }, | |
4745 | ||
592a252b | 4746 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4747 | { |
ec6f095a | 4748 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4749 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4750 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4751 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4752 | }, |
4753 | ||
592a252b | 4754 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4755 | { |
ec6f095a | 4756 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4757 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4758 | }, |
4759 | ||
592a252b | 4760 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4761 | { |
ec6f095a | 4762 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4763 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4764 | }, |
4765 | ||
592a252b | 4766 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4767 | { |
ec6f095a | 4768 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4769 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4770 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4771 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4772 | }, |
4773 | ||
592a252b | 4774 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4775 | { |
ec6f095a | 4776 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4777 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4778 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4779 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4780 | }, |
4781 | ||
592a252b | 4782 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4783 | { |
ec6f095a | 4784 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4785 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4786 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4787 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4788 | }, |
4789 | ||
592a252b | 4790 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4791 | { |
ec6f095a L |
4792 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4793 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4794 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4795 | }, |
4796 | ||
592a252b | 4797 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4798 | { |
ec6f095a | 4799 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4800 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4801 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4802 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4803 | }, |
4804 | ||
592a252b | 4805 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4806 | { |
ec6f095a | 4807 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4808 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4809 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4810 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4811 | }, |
4812 | ||
592a252b | 4813 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4814 | { |
ec6f095a | 4815 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4816 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4817 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4818 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4819 | }, |
4820 | ||
592a252b | 4821 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4822 | { |
ec6f095a | 4823 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4824 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4825 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4826 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4827 | }, |
4828 | ||
592a252b | 4829 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4830 | { |
592d1631 L |
4831 | { Bad_Opcode }, |
4832 | { Bad_Opcode }, | |
ec6f095a | 4833 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4837 | { |
592d1631 L |
4838 | { Bad_Opcode }, |
4839 | { Bad_Opcode }, | |
ec6f095a | 4840 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4841 | }, |
4842 | ||
592a252b | 4843 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4844 | { |
592d1631 L |
4845 | { Bad_Opcode }, |
4846 | { Bad_Opcode }, | |
ec6f095a | 4847 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4848 | }, |
4849 | ||
592a252b | 4850 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4851 | { |
592d1631 L |
4852 | { Bad_Opcode }, |
4853 | { Bad_Opcode }, | |
ec6f095a | 4854 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4855 | }, |
4856 | ||
592a252b | 4857 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4858 | { |
592d1631 L |
4859 | { Bad_Opcode }, |
4860 | { Bad_Opcode }, | |
ec6f095a | 4861 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4862 | }, |
4863 | ||
592a252b | 4864 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4865 | { |
592d1631 L |
4866 | { Bad_Opcode }, |
4867 | { Bad_Opcode }, | |
ec6f095a | 4868 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4869 | }, |
4870 | ||
592a252b | 4871 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4872 | { |
592d1631 L |
4873 | { Bad_Opcode }, |
4874 | { Bad_Opcode }, | |
ec6f095a | 4875 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4876 | }, |
6439fc28 | 4877 | |
592a252b | 4878 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4879 | { |
592d1631 L |
4880 | { Bad_Opcode }, |
4881 | { Bad_Opcode }, | |
ec6f095a | 4882 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4883 | }, |
4884 | ||
592a252b | 4885 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4886 | { |
592d1631 L |
4887 | { Bad_Opcode }, |
4888 | { Bad_Opcode }, | |
ec6f095a | 4889 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4890 | }, |
4891 | ||
592a252b | 4892 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4893 | { |
592d1631 L |
4894 | { Bad_Opcode }, |
4895 | { Bad_Opcode }, | |
ec6f095a | 4896 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4897 | }, |
4898 | ||
592a252b | 4899 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4900 | { |
592d1631 L |
4901 | { Bad_Opcode }, |
4902 | { Bad_Opcode }, | |
ec6f095a | 4903 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4904 | }, |
4905 | ||
592a252b | 4906 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4907 | { |
592d1631 L |
4908 | { Bad_Opcode }, |
4909 | { Bad_Opcode }, | |
ec6f095a | 4910 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4911 | }, |
4912 | ||
592a252b | 4913 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4914 | { |
592d1631 L |
4915 | { Bad_Opcode }, |
4916 | { Bad_Opcode }, | |
ec6f095a | 4917 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4918 | }, |
4919 | ||
592a252b | 4920 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4921 | { |
592d1631 L |
4922 | { Bad_Opcode }, |
4923 | { Bad_Opcode }, | |
ec6f095a | 4924 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4925 | }, |
4926 | ||
592a252b | 4927 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4928 | { |
592d1631 L |
4929 | { Bad_Opcode }, |
4930 | { Bad_Opcode }, | |
592a252b | 4931 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4932 | }, |
4933 | ||
592a252b | 4934 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4935 | { |
592d1631 | 4936 | { Bad_Opcode }, |
ec6f095a L |
4937 | { "vmovdqu", { XM, EXx }, 0 }, |
4938 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4939 | }, |
4940 | ||
592a252b | 4941 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4942 | { |
592d1631 | 4943 | { Bad_Opcode }, |
ec6f095a L |
4944 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4945 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4946 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4947 | }, |
4948 | ||
592a252b | 4949 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4950 | { |
592d1631 L |
4951 | { Bad_Opcode }, |
4952 | { Bad_Opcode }, | |
ec6f095a | 4953 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4954 | }, |
4955 | ||
592a252b | 4956 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4957 | { |
592d1631 L |
4958 | { Bad_Opcode }, |
4959 | { Bad_Opcode }, | |
ec6f095a | 4960 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4961 | }, |
4962 | ||
592a252b | 4963 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4964 | { |
592d1631 L |
4965 | { Bad_Opcode }, |
4966 | { Bad_Opcode }, | |
ec6f095a | 4967 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4968 | }, |
4969 | ||
592a252b | 4970 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4971 | { |
592d1631 L |
4972 | { Bad_Opcode }, |
4973 | { Bad_Opcode }, | |
ec6f095a | 4974 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4975 | }, |
4976 | ||
592a252b | 4977 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4978 | { |
592d1631 L |
4979 | { Bad_Opcode }, |
4980 | { Bad_Opcode }, | |
ec6f095a | 4981 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4982 | }, |
4983 | ||
592a252b | 4984 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4985 | { |
592d1631 L |
4986 | { Bad_Opcode }, |
4987 | { Bad_Opcode }, | |
ec6f095a | 4988 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4989 | }, |
4990 | ||
592a252b | 4991 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4992 | { |
592d1631 L |
4993 | { Bad_Opcode }, |
4994 | { Bad_Opcode }, | |
ec6f095a | 4995 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4996 | }, |
4997 | ||
592a252b | 4998 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4999 | { |
592d1631 L |
5000 | { Bad_Opcode }, |
5001 | { Bad_Opcode }, | |
ec6f095a | 5002 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5003 | }, |
5004 | ||
592a252b | 5005 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5006 | { |
592d1631 L |
5007 | { Bad_Opcode }, |
5008 | { Bad_Opcode }, | |
ec6f095a | 5009 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5010 | }, |
5011 | ||
592a252b | 5012 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5013 | { |
592d1631 L |
5014 | { Bad_Opcode }, |
5015 | { Bad_Opcode }, | |
ec6f095a | 5016 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5017 | }, |
5018 | ||
592a252b | 5019 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5020 | { |
592d1631 L |
5021 | { Bad_Opcode }, |
5022 | { Bad_Opcode }, | |
ec6f095a | 5023 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5024 | }, |
5025 | ||
592a252b | 5026 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5027 | { |
592d1631 L |
5028 | { Bad_Opcode }, |
5029 | { Bad_Opcode }, | |
ec6f095a | 5030 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5031 | }, |
5032 | ||
592a252b | 5033 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5034 | { |
592d1631 L |
5035 | { Bad_Opcode }, |
5036 | { Bad_Opcode }, | |
ec6f095a | 5037 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5038 | }, |
5039 | ||
592a252b | 5040 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5041 | { |
ec6f095a | 5042 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5043 | }, |
5044 | ||
592a252b | 5045 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
ec6f095a L |
5049 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5050 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5051 | }, |
5052 | ||
592a252b | 5053 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5054 | { |
592d1631 L |
5055 | { Bad_Opcode }, |
5056 | { Bad_Opcode }, | |
ec6f095a L |
5057 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5058 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5059 | }, |
5060 | ||
592a252b | 5061 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5062 | { |
592d1631 | 5063 | { Bad_Opcode }, |
592a252b L |
5064 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5065 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5066 | }, |
5067 | ||
592a252b | 5068 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5069 | { |
592d1631 | 5070 | { Bad_Opcode }, |
ec6f095a L |
5071 | { "vmovdqu", { EXxS, XM }, 0 }, |
5072 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5073 | }, |
5074 | ||
43234a1e L |
5075 | /* PREFIX_VEX_0F90 */ |
5076 | { | |
5077 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5078 | { Bad_Opcode }, |
5079 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5080 | }, |
5081 | ||
5082 | /* PREFIX_VEX_0F91 */ | |
5083 | { | |
5084 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5085 | { Bad_Opcode }, |
5086 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5087 | }, |
5088 | ||
5089 | /* PREFIX_VEX_0F92 */ | |
5090 | { | |
5091 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5092 | { Bad_Opcode }, |
90a915bf | 5093 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5094 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5095 | }, |
5096 | ||
5097 | /* PREFIX_VEX_0F93 */ | |
5098 | { | |
5099 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5100 | { Bad_Opcode }, |
90a915bf | 5101 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5102 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5103 | }, |
5104 | ||
5105 | /* PREFIX_VEX_0F98 */ | |
5106 | { | |
5107 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5108 | { Bad_Opcode }, |
5109 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5110 | }, | |
5111 | ||
5112 | /* PREFIX_VEX_0F99 */ | |
5113 | { | |
5114 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5115 | { Bad_Opcode }, | |
5116 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5117 | }, |
5118 | ||
592a252b | 5119 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5120 | { |
c4de7606 JB |
5121 | { "vcmpps", { XM, Vex, EXx, CMP }, 0 }, |
5122 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 }, | |
5123 | { "vcmppd", { XM, Vex, EXx, CMP }, 0 }, | |
5124 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 }, | |
c0f3af97 L |
5125 | }, |
5126 | ||
592a252b | 5127 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5128 | { |
592d1631 L |
5129 | { Bad_Opcode }, |
5130 | { Bad_Opcode }, | |
592a252b | 5131 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5132 | }, |
5133 | ||
592a252b | 5134 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5135 | { |
592d1631 L |
5136 | { Bad_Opcode }, |
5137 | { Bad_Opcode }, | |
592a252b | 5138 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5139 | }, |
5140 | ||
592a252b | 5141 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5142 | { |
592d1631 L |
5143 | { Bad_Opcode }, |
5144 | { Bad_Opcode }, | |
ec6f095a L |
5145 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5146 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5147 | }, |
5148 | ||
592a252b | 5149 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5150 | { |
592d1631 L |
5151 | { Bad_Opcode }, |
5152 | { Bad_Opcode }, | |
ec6f095a | 5153 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5154 | }, |
5155 | ||
592a252b | 5156 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5157 | { |
592d1631 L |
5158 | { Bad_Opcode }, |
5159 | { Bad_Opcode }, | |
ec6f095a | 5160 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5161 | }, |
5162 | ||
592a252b | 5163 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5164 | { |
592d1631 L |
5165 | { Bad_Opcode }, |
5166 | { Bad_Opcode }, | |
ec6f095a | 5167 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5168 | }, |
5169 | ||
592a252b | 5170 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5171 | { |
592d1631 L |
5172 | { Bad_Opcode }, |
5173 | { Bad_Opcode }, | |
ec6f095a | 5174 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5175 | }, |
5176 | ||
592a252b | 5177 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5178 | { |
592d1631 L |
5179 | { Bad_Opcode }, |
5180 | { Bad_Opcode }, | |
ec6f095a | 5181 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5182 | }, |
5183 | ||
592a252b | 5184 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5185 | { |
592d1631 L |
5186 | { Bad_Opcode }, |
5187 | { Bad_Opcode }, | |
592a252b | 5188 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5189 | }, |
5190 | ||
592a252b | 5191 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5192 | { |
592d1631 L |
5193 | { Bad_Opcode }, |
5194 | { Bad_Opcode }, | |
592a252b | 5195 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5196 | }, |
5197 | ||
592a252b | 5198 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5199 | { |
592d1631 L |
5200 | { Bad_Opcode }, |
5201 | { Bad_Opcode }, | |
ec6f095a | 5202 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5203 | }, |
5204 | ||
592a252b | 5205 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5206 | { |
592d1631 L |
5207 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, | |
ec6f095a | 5209 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5210 | }, |
5211 | ||
592a252b | 5212 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5213 | { |
592d1631 L |
5214 | { Bad_Opcode }, |
5215 | { Bad_Opcode }, | |
ec6f095a | 5216 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5217 | }, |
5218 | ||
592a252b | 5219 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5220 | { |
592d1631 L |
5221 | { Bad_Opcode }, |
5222 | { Bad_Opcode }, | |
ec6f095a | 5223 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5224 | }, |
5225 | ||
592a252b | 5226 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5227 | { |
592d1631 L |
5228 | { Bad_Opcode }, |
5229 | { Bad_Opcode }, | |
ec6f095a | 5230 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5231 | }, |
5232 | ||
592a252b | 5233 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5234 | { |
592d1631 L |
5235 | { Bad_Opcode }, |
5236 | { Bad_Opcode }, | |
ec6f095a | 5237 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5238 | }, |
5239 | ||
592a252b | 5240 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5241 | { |
592d1631 L |
5242 | { Bad_Opcode }, |
5243 | { Bad_Opcode }, | |
ec6f095a | 5244 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5245 | }, |
5246 | ||
592a252b | 5247 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5248 | { |
592d1631 L |
5249 | { Bad_Opcode }, |
5250 | { Bad_Opcode }, | |
ec6f095a | 5251 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5252 | }, |
5253 | ||
592a252b | 5254 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5255 | { |
592d1631 L |
5256 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, | |
ec6f095a | 5258 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5259 | }, |
5260 | ||
592a252b | 5261 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5262 | { |
592d1631 L |
5263 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, | |
ec6f095a | 5265 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5266 | }, |
5267 | ||
592a252b | 5268 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5269 | { |
592d1631 L |
5270 | { Bad_Opcode }, |
5271 | { Bad_Opcode }, | |
ec6f095a | 5272 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5273 | }, |
5274 | ||
592a252b | 5275 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5276 | { |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
ec6f095a | 5279 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5280 | }, |
5281 | ||
592a252b | 5282 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5283 | { |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
ec6f095a | 5286 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5287 | }, |
5288 | ||
592a252b | 5289 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5290 | { |
592d1631 L |
5291 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, | |
ec6f095a | 5293 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5294 | }, |
5295 | ||
592a252b | 5296 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5297 | { |
592d1631 | 5298 | { Bad_Opcode }, |
ec6f095a L |
5299 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5300 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5301 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5302 | }, |
5303 | ||
592a252b | 5304 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5305 | { |
592d1631 L |
5306 | { Bad_Opcode }, |
5307 | { Bad_Opcode }, | |
592a252b | 5308 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5309 | }, |
5310 | ||
592a252b | 5311 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5312 | { |
592d1631 L |
5313 | { Bad_Opcode }, |
5314 | { Bad_Opcode }, | |
ec6f095a | 5315 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5316 | }, |
5317 | ||
592a252b | 5318 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5319 | { |
592d1631 L |
5320 | { Bad_Opcode }, |
5321 | { Bad_Opcode }, | |
ec6f095a | 5322 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5323 | }, |
5324 | ||
592a252b | 5325 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5326 | { |
592d1631 L |
5327 | { Bad_Opcode }, |
5328 | { Bad_Opcode }, | |
ec6f095a | 5329 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5330 | }, |
5331 | ||
592a252b | 5332 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5333 | { |
592d1631 L |
5334 | { Bad_Opcode }, |
5335 | { Bad_Opcode }, | |
ec6f095a | 5336 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5337 | }, |
5338 | ||
592a252b | 5339 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5340 | { |
592d1631 L |
5341 | { Bad_Opcode }, |
5342 | { Bad_Opcode }, | |
ec6f095a | 5343 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5344 | }, |
5345 | ||
592a252b | 5346 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5347 | { |
592d1631 L |
5348 | { Bad_Opcode }, |
5349 | { Bad_Opcode }, | |
ec6f095a | 5350 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5351 | }, |
5352 | ||
592a252b | 5353 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5354 | { |
592d1631 L |
5355 | { Bad_Opcode }, |
5356 | { Bad_Opcode }, | |
ec6f095a | 5357 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5358 | }, |
5359 | ||
592a252b | 5360 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5361 | { |
592d1631 L |
5362 | { Bad_Opcode }, |
5363 | { Bad_Opcode }, | |
ec6f095a | 5364 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5365 | }, |
5366 | ||
592a252b | 5367 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5368 | { |
592d1631 L |
5369 | { Bad_Opcode }, |
5370 | { Bad_Opcode }, | |
5371 | { Bad_Opcode }, | |
592a252b | 5372 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5373 | }, |
5374 | ||
592a252b | 5375 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5376 | { |
592d1631 L |
5377 | { Bad_Opcode }, |
5378 | { Bad_Opcode }, | |
ec6f095a | 5379 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5380 | }, |
5381 | ||
592a252b | 5382 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5383 | { |
592d1631 L |
5384 | { Bad_Opcode }, |
5385 | { Bad_Opcode }, | |
ec6f095a | 5386 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5387 | }, |
5388 | ||
592a252b | 5389 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5390 | { |
592d1631 L |
5391 | { Bad_Opcode }, |
5392 | { Bad_Opcode }, | |
ec6f095a | 5393 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5394 | }, |
5395 | ||
592a252b | 5396 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5397 | { |
592d1631 L |
5398 | { Bad_Opcode }, |
5399 | { Bad_Opcode }, | |
ec6f095a | 5400 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5401 | }, |
5402 | ||
592a252b | 5403 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5404 | { |
592d1631 L |
5405 | { Bad_Opcode }, |
5406 | { Bad_Opcode }, | |
ec6f095a | 5407 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5408 | }, |
5409 | ||
592a252b | 5410 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5411 | { |
592d1631 L |
5412 | { Bad_Opcode }, |
5413 | { Bad_Opcode }, | |
ec6f095a | 5414 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5415 | }, |
5416 | ||
592a252b | 5417 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5418 | { |
592d1631 L |
5419 | { Bad_Opcode }, |
5420 | { Bad_Opcode }, | |
592a252b | 5421 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5422 | }, |
5423 | ||
592a252b | 5424 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5425 | { |
592d1631 L |
5426 | { Bad_Opcode }, |
5427 | { Bad_Opcode }, | |
ec6f095a | 5428 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5429 | }, |
5430 | ||
592a252b | 5431 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5432 | { |
592d1631 L |
5433 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, | |
ec6f095a | 5435 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5436 | }, |
5437 | ||
592a252b | 5438 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5439 | { |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
ec6f095a | 5442 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5443 | }, |
5444 | ||
592a252b | 5445 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5446 | { |
592d1631 L |
5447 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, | |
ec6f095a | 5449 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5450 | }, |
5451 | ||
592a252b | 5452 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5453 | { |
592d1631 L |
5454 | { Bad_Opcode }, |
5455 | { Bad_Opcode }, | |
ec6f095a | 5456 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5457 | }, |
5458 | ||
592a252b | 5459 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5460 | { |
592d1631 L |
5461 | { Bad_Opcode }, |
5462 | { Bad_Opcode }, | |
ec6f095a | 5463 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5464 | }, |
5465 | ||
592a252b | 5466 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5467 | { |
592d1631 L |
5468 | { Bad_Opcode }, |
5469 | { Bad_Opcode }, | |
ec6f095a | 5470 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5471 | }, |
5472 | ||
592a252b | 5473 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5474 | { |
592d1631 L |
5475 | { Bad_Opcode }, |
5476 | { Bad_Opcode }, | |
ec6f095a | 5477 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5478 | }, |
5479 | ||
592a252b | 5480 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5481 | { |
592d1631 L |
5482 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, | |
ec6f095a | 5484 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5485 | }, |
5486 | ||
592a252b | 5487 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5488 | { |
592d1631 L |
5489 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, | |
ec6f095a | 5491 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5492 | }, |
5493 | ||
592a252b | 5494 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5495 | { |
592d1631 L |
5496 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, | |
ec6f095a | 5498 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5499 | }, |
5500 | ||
592a252b | 5501 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5502 | { |
592d1631 L |
5503 | { Bad_Opcode }, |
5504 | { Bad_Opcode }, | |
ec6f095a | 5505 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5506 | }, |
5507 | ||
592a252b | 5508 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5509 | { |
592d1631 L |
5510 | { Bad_Opcode }, |
5511 | { Bad_Opcode }, | |
ec6f095a | 5512 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5513 | }, |
5514 | ||
592a252b | 5515 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5516 | { |
592d1631 L |
5517 | { Bad_Opcode }, |
5518 | { Bad_Opcode }, | |
ec6f095a | 5519 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5520 | }, |
5521 | ||
592a252b | 5522 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5523 | { |
592d1631 L |
5524 | { Bad_Opcode }, |
5525 | { Bad_Opcode }, | |
ec6f095a | 5526 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5527 | }, |
5528 | ||
592a252b | 5529 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5530 | { |
592d1631 L |
5531 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, | |
ec6f095a | 5533 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5534 | }, |
5535 | ||
592a252b | 5536 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5537 | { |
592d1631 L |
5538 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, | |
ec6f095a | 5540 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5541 | }, |
5542 | ||
592a252b | 5543 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5544 | { |
592d1631 L |
5545 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, | |
ec6f095a | 5547 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5548 | }, |
5549 | ||
592a252b | 5550 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5551 | { |
592d1631 L |
5552 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, | |
ec6f095a | 5554 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5555 | }, |
5556 | ||
592a252b | 5557 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5558 | { |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
592a252b | 5561 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5562 | }, |
5563 | ||
592a252b | 5564 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5565 | { |
592d1631 L |
5566 | { Bad_Opcode }, |
5567 | { Bad_Opcode }, | |
592a252b | 5568 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5569 | }, |
5570 | ||
592a252b | 5571 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5572 | { |
592d1631 L |
5573 | { Bad_Opcode }, |
5574 | { Bad_Opcode }, | |
592a252b | 5575 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5576 | }, |
5577 | ||
592a252b | 5578 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5579 | { |
592d1631 L |
5580 | { Bad_Opcode }, |
5581 | { Bad_Opcode }, | |
592a252b | 5582 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5583 | }, |
5584 | ||
592a252b | 5585 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5586 | { |
5587 | { Bad_Opcode }, | |
5588 | { Bad_Opcode }, | |
6431c801 | 5589 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5590 | }, |
5591 | ||
6c30d220 L |
5592 | /* PREFIX_VEX_0F3816 */ |
5593 | { | |
5594 | { Bad_Opcode }, | |
5595 | { Bad_Opcode }, | |
5596 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5597 | }, | |
5598 | ||
592a252b | 5599 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5600 | { |
592d1631 L |
5601 | { Bad_Opcode }, |
5602 | { Bad_Opcode }, | |
ec6f095a | 5603 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5604 | }, |
5605 | ||
592a252b | 5606 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5607 | { |
592d1631 L |
5608 | { Bad_Opcode }, |
5609 | { Bad_Opcode }, | |
6c30d220 | 5610 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5611 | }, |
5612 | ||
592a252b | 5613 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5614 | { |
592d1631 L |
5615 | { Bad_Opcode }, |
5616 | { Bad_Opcode }, | |
6c30d220 | 5617 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5618 | }, |
5619 | ||
592a252b | 5620 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5621 | { |
592d1631 L |
5622 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, | |
592a252b | 5624 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5625 | }, |
5626 | ||
592a252b | 5627 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5628 | { |
592d1631 L |
5629 | { Bad_Opcode }, |
5630 | { Bad_Opcode }, | |
ec6f095a | 5631 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5632 | }, |
5633 | ||
592a252b | 5634 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5635 | { |
592d1631 L |
5636 | { Bad_Opcode }, |
5637 | { Bad_Opcode }, | |
ec6f095a | 5638 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5639 | }, |
5640 | ||
592a252b | 5641 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5642 | { |
592d1631 L |
5643 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, | |
ec6f095a | 5645 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5646 | }, |
5647 | ||
592a252b | 5648 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5649 | { |
592d1631 L |
5650 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, | |
ec6f095a | 5652 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5653 | }, |
5654 | ||
592a252b | 5655 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5656 | { |
592d1631 L |
5657 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, | |
ec6f095a | 5659 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5660 | }, |
5661 | ||
592a252b | 5662 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5663 | { |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
ec6f095a | 5666 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5667 | }, |
5668 | ||
592a252b | 5669 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5670 | { |
592d1631 L |
5671 | { Bad_Opcode }, |
5672 | { Bad_Opcode }, | |
ec6f095a | 5673 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5674 | }, |
5675 | ||
592a252b | 5676 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5677 | { |
592d1631 L |
5678 | { Bad_Opcode }, |
5679 | { Bad_Opcode }, | |
ec6f095a | 5680 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5681 | }, |
5682 | ||
592a252b | 5683 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5684 | { |
592d1631 L |
5685 | { Bad_Opcode }, |
5686 | { Bad_Opcode }, | |
ec6f095a | 5687 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5688 | }, |
5689 | ||
592a252b | 5690 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5691 | { |
592d1631 L |
5692 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, | |
ec6f095a | 5694 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5695 | }, |
5696 | ||
592a252b | 5697 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5698 | { |
592d1631 L |
5699 | { Bad_Opcode }, |
5700 | { Bad_Opcode }, | |
ec6f095a | 5701 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5702 | }, |
5703 | ||
592a252b | 5704 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5705 | { |
592d1631 L |
5706 | { Bad_Opcode }, |
5707 | { Bad_Opcode }, | |
592a252b | 5708 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5709 | }, |
5710 | ||
592a252b | 5711 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5712 | { |
592d1631 L |
5713 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, | |
ec6f095a | 5715 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5716 | }, |
5717 | ||
592a252b | 5718 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5719 | { |
592d1631 L |
5720 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, | |
592a252b | 5722 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5723 | }, |
5724 | ||
592a252b | 5725 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5726 | { |
592d1631 L |
5727 | { Bad_Opcode }, |
5728 | { Bad_Opcode }, | |
592a252b | 5729 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5730 | }, |
5731 | ||
592a252b | 5732 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5733 | { |
592d1631 L |
5734 | { Bad_Opcode }, |
5735 | { Bad_Opcode }, | |
592a252b | 5736 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5737 | }, |
5738 | ||
592a252b | 5739 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5740 | { |
592d1631 L |
5741 | { Bad_Opcode }, |
5742 | { Bad_Opcode }, | |
592a252b | 5743 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5744 | }, |
5745 | ||
592a252b | 5746 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5747 | { |
592d1631 L |
5748 | { Bad_Opcode }, |
5749 | { Bad_Opcode }, | |
ec6f095a | 5750 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5751 | }, |
5752 | ||
592a252b | 5753 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5754 | { |
592d1631 L |
5755 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, | |
ec6f095a | 5757 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5758 | }, |
5759 | ||
592a252b | 5760 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5761 | { |
592d1631 L |
5762 | { Bad_Opcode }, |
5763 | { Bad_Opcode }, | |
ec6f095a | 5764 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5765 | }, |
5766 | ||
592a252b | 5767 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5768 | { |
592d1631 L |
5769 | { Bad_Opcode }, |
5770 | { Bad_Opcode }, | |
ec6f095a | 5771 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5772 | }, |
5773 | ||
592a252b | 5774 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5775 | { |
592d1631 L |
5776 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, | |
ec6f095a | 5778 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5779 | }, |
5780 | ||
592a252b | 5781 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5782 | { |
592d1631 L |
5783 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, | |
ec6f095a | 5785 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5786 | }, |
5787 | ||
5788 | /* PREFIX_VEX_0F3836 */ | |
5789 | { | |
5790 | { Bad_Opcode }, | |
5791 | { Bad_Opcode }, | |
5792 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5793 | }, |
5794 | ||
592a252b | 5795 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5796 | { |
592d1631 L |
5797 | { Bad_Opcode }, |
5798 | { Bad_Opcode }, | |
ec6f095a | 5799 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5800 | }, |
5801 | ||
592a252b | 5802 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5803 | { |
592d1631 L |
5804 | { Bad_Opcode }, |
5805 | { Bad_Opcode }, | |
ec6f095a | 5806 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5807 | }, |
5808 | ||
592a252b | 5809 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5810 | { |
592d1631 L |
5811 | { Bad_Opcode }, |
5812 | { Bad_Opcode }, | |
ec6f095a | 5813 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5814 | }, |
5815 | ||
592a252b | 5816 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5817 | { |
592d1631 L |
5818 | { Bad_Opcode }, |
5819 | { Bad_Opcode }, | |
ec6f095a | 5820 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5821 | }, |
5822 | ||
592a252b | 5823 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5824 | { |
592d1631 L |
5825 | { Bad_Opcode }, |
5826 | { Bad_Opcode }, | |
ec6f095a | 5827 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5828 | }, |
5829 | ||
592a252b | 5830 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5831 | { |
592d1631 L |
5832 | { Bad_Opcode }, |
5833 | { Bad_Opcode }, | |
ec6f095a | 5834 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5835 | }, |
5836 | ||
592a252b | 5837 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5838 | { |
592d1631 L |
5839 | { Bad_Opcode }, |
5840 | { Bad_Opcode }, | |
ec6f095a | 5841 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5842 | }, |
5843 | ||
592a252b | 5844 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5845 | { |
592d1631 L |
5846 | { Bad_Opcode }, |
5847 | { Bad_Opcode }, | |
ec6f095a | 5848 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5849 | }, |
5850 | ||
592a252b | 5851 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5852 | { |
592d1631 L |
5853 | { Bad_Opcode }, |
5854 | { Bad_Opcode }, | |
ec6f095a | 5855 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5856 | }, |
5857 | ||
592a252b | 5858 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5859 | { |
592d1631 L |
5860 | { Bad_Opcode }, |
5861 | { Bad_Opcode }, | |
ec6f095a | 5862 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5863 | }, |
5864 | ||
592a252b | 5865 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5866 | { |
592d1631 L |
5867 | { Bad_Opcode }, |
5868 | { Bad_Opcode }, | |
592a252b | 5869 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5870 | }, |
5871 | ||
6c30d220 L |
5872 | /* PREFIX_VEX_0F3845 */ |
5873 | { | |
5874 | { Bad_Opcode }, | |
5875 | { Bad_Opcode }, | |
492a76aa | 5876 | { "vpsrlv%DQ", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5877 | }, |
5878 | ||
5879 | /* PREFIX_VEX_0F3846 */ | |
5880 | { | |
5881 | { Bad_Opcode }, | |
5882 | { Bad_Opcode }, | |
5883 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5884 | }, | |
5885 | ||
5886 | /* PREFIX_VEX_0F3847 */ | |
5887 | { | |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
492a76aa | 5890 | { "vpsllv%DQ", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5891 | }, |
5892 | ||
260cd341 LC |
5893 | /* PREFIX_VEX_0F3849_X86_64 */ |
5894 | { | |
5895 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, | |
5896 | { Bad_Opcode }, | |
5897 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, | |
5898 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
5899 | }, | |
5900 | ||
5901 | /* PREFIX_VEX_0F384B_X86_64 */ | |
5902 | { | |
5903 | { Bad_Opcode }, | |
5904 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, | |
5905 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
5906 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
5907 | }, | |
5908 | ||
6c30d220 L |
5909 | /* PREFIX_VEX_0F3858 */ |
5910 | { | |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
5913 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5914 | }, | |
5915 | ||
5916 | /* PREFIX_VEX_0F3859 */ | |
5917 | { | |
5918 | { Bad_Opcode }, | |
5919 | { Bad_Opcode }, | |
5920 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5921 | }, | |
5922 | ||
5923 | /* PREFIX_VEX_0F385A */ | |
5924 | { | |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
5927 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5928 | }, | |
5929 | ||
260cd341 LC |
5930 | /* PREFIX_VEX_0F385C_X86_64 */ |
5931 | { | |
5932 | { Bad_Opcode }, | |
5933 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, | |
5934 | { Bad_Opcode }, | |
5935 | }, | |
5936 | ||
5937 | /* PREFIX_VEX_0F385E_X86_64 */ | |
5938 | { | |
5939 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, | |
5940 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
5941 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
5942 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
5943 | }, | |
5944 | ||
6c30d220 L |
5945 | /* PREFIX_VEX_0F3878 */ |
5946 | { | |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
5949 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5950 | }, | |
5951 | ||
5952 | /* PREFIX_VEX_0F3879 */ | |
5953 | { | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
5956 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5957 | }, | |
5958 | ||
5959 | /* PREFIX_VEX_0F388C */ | |
5960 | { | |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
f7002f42 | 5963 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5964 | }, |
5965 | ||
5966 | /* PREFIX_VEX_0F388E */ | |
5967 | { | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
f7002f42 | 5970 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5971 | }, |
5972 | ||
5973 | /* PREFIX_VEX_0F3890 */ | |
5974 | { | |
5975 | { Bad_Opcode }, | |
5976 | { Bad_Opcode }, | |
492a76aa | 5977 | { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5978 | }, |
5979 | ||
5980 | /* PREFIX_VEX_0F3891 */ | |
5981 | { | |
5982 | { Bad_Opcode }, | |
5983 | { Bad_Opcode }, | |
492a76aa | 5984 | { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5985 | }, |
5986 | ||
5987 | /* PREFIX_VEX_0F3892 */ | |
5988 | { | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
bf890a93 | 5991 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5992 | }, |
5993 | ||
5994 | /* PREFIX_VEX_0F3893 */ | |
5995 | { | |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
bf890a93 | 5998 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5999 | }, |
6000 | ||
592a252b | 6001 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6002 | { |
592d1631 L |
6003 | { Bad_Opcode }, |
6004 | { Bad_Opcode }, | |
6df22cf6 | 6005 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6006 | }, |
6007 | ||
592a252b | 6008 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6009 | { |
592d1631 L |
6010 | { Bad_Opcode }, |
6011 | { Bad_Opcode }, | |
6df22cf6 | 6012 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6013 | }, |
6014 | ||
592a252b | 6015 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6016 | { |
592d1631 L |
6017 | { Bad_Opcode }, |
6018 | { Bad_Opcode }, | |
6df22cf6 | 6019 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6020 | }, |
6021 | ||
592a252b | 6022 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6023 | { |
592d1631 L |
6024 | { Bad_Opcode }, |
6025 | { Bad_Opcode }, | |
6df22cf6 | 6026 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6027 | }, |
6028 | ||
592a252b | 6029 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6030 | { |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
bf890a93 | 6033 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6034 | }, |
6035 | ||
592a252b | 6036 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6037 | { |
592d1631 L |
6038 | { Bad_Opcode }, |
6039 | { Bad_Opcode }, | |
bf890a93 | 6040 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
6df22cf6 | 6047 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
6df22cf6 | 6054 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6055 | }, |
6056 | ||
592a252b | 6057 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6058 | { |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
6df22cf6 | 6061 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6062 | }, |
6063 | ||
592a252b | 6064 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6065 | { |
592d1631 L |
6066 | { Bad_Opcode }, |
6067 | { Bad_Opcode }, | |
6df22cf6 | 6068 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6069 | }, |
6070 | ||
592a252b | 6071 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6072 | { |
592d1631 L |
6073 | { Bad_Opcode }, |
6074 | { Bad_Opcode }, | |
6df22cf6 | 6075 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 6076 | { Bad_Opcode }, |
c0f3af97 L |
6077 | }, |
6078 | ||
592a252b | 6079 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6080 | { |
592d1631 L |
6081 | { Bad_Opcode }, |
6082 | { Bad_Opcode }, | |
6df22cf6 | 6083 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6084 | }, |
6085 | ||
592a252b | 6086 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6087 | { |
592d1631 L |
6088 | { Bad_Opcode }, |
6089 | { Bad_Opcode }, | |
6df22cf6 | 6090 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6091 | }, |
6092 | ||
592a252b | 6093 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6094 | { |
592d1631 L |
6095 | { Bad_Opcode }, |
6096 | { Bad_Opcode }, | |
6df22cf6 | 6097 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6098 | }, |
6099 | ||
592a252b | 6100 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6101 | { |
592d1631 L |
6102 | { Bad_Opcode }, |
6103 | { Bad_Opcode }, | |
bf890a93 | 6104 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6105 | }, |
6106 | ||
592a252b | 6107 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6108 | { |
592d1631 L |
6109 | { Bad_Opcode }, |
6110 | { Bad_Opcode }, | |
bf890a93 | 6111 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6112 | }, |
6113 | ||
592a252b | 6114 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6115 | { |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
6df22cf6 | 6118 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
6df22cf6 | 6125 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
6df22cf6 | 6132 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
6df22cf6 | 6139 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
6df22cf6 | 6146 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
6df22cf6 | 6153 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
6df22cf6 | 6160 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
6df22cf6 | 6167 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6168 | }, |
6169 | ||
592a252b | 6170 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6171 | { |
592d1631 L |
6172 | { Bad_Opcode }, |
6173 | { Bad_Opcode }, | |
6df22cf6 | 6174 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6175 | }, |
6176 | ||
592a252b | 6177 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6178 | { |
592d1631 L |
6179 | { Bad_Opcode }, |
6180 | { Bad_Opcode }, | |
6df22cf6 | 6181 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6182 | }, |
6183 | ||
592a252b | 6184 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6185 | { |
592d1631 L |
6186 | { Bad_Opcode }, |
6187 | { Bad_Opcode }, | |
6df22cf6 | 6188 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6189 | }, |
6190 | ||
592a252b | 6191 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6192 | { |
592d1631 L |
6193 | { Bad_Opcode }, |
6194 | { Bad_Opcode }, | |
6df22cf6 | 6195 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6196 | }, |
6197 | ||
592a252b | 6198 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6199 | { |
592d1631 L |
6200 | { Bad_Opcode }, |
6201 | { Bad_Opcode }, | |
6df22cf6 | 6202 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6203 | }, |
6204 | ||
592a252b | 6205 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6206 | { |
592d1631 L |
6207 | { Bad_Opcode }, |
6208 | { Bad_Opcode }, | |
6df22cf6 | 6209 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6210 | }, |
6211 | ||
48521003 IT |
6212 | /* PREFIX_VEX_0F38CF */ |
6213 | { | |
6214 | { Bad_Opcode }, | |
6215 | { Bad_Opcode }, | |
6216 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6217 | }, | |
6218 | ||
592a252b | 6219 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6220 | { |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
592a252b | 6223 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6224 | }, |
6225 | ||
592a252b | 6226 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6227 | { |
592d1631 L |
6228 | { Bad_Opcode }, |
6229 | { Bad_Opcode }, | |
8dcf1fad | 6230 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6231 | }, |
6232 | ||
592a252b | 6233 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6234 | { |
592d1631 L |
6235 | { Bad_Opcode }, |
6236 | { Bad_Opcode }, | |
8dcf1fad | 6237 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6238 | }, |
6239 | ||
592a252b | 6240 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6241 | { |
592d1631 L |
6242 | { Bad_Opcode }, |
6243 | { Bad_Opcode }, | |
8dcf1fad | 6244 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6245 | }, |
6246 | ||
592a252b | 6247 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6248 | { |
592d1631 L |
6249 | { Bad_Opcode }, |
6250 | { Bad_Opcode }, | |
8dcf1fad | 6251 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6252 | }, |
6253 | ||
f12dc422 L |
6254 | /* PREFIX_VEX_0F38F2 */ |
6255 | { | |
6256 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6257 | }, | |
6258 | ||
6259 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6260 | { | |
6261 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6262 | }, | |
6263 | ||
6264 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6265 | { | |
6266 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6267 | }, | |
6268 | ||
6269 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6270 | { | |
6271 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6272 | }, | |
6273 | ||
6c30d220 L |
6274 | /* PREFIX_VEX_0F38F5 */ |
6275 | { | |
6276 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6277 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6278 | { Bad_Opcode }, | |
6279 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6280 | }, | |
6281 | ||
6282 | /* PREFIX_VEX_0F38F6 */ | |
6283 | { | |
6284 | { Bad_Opcode }, | |
6285 | { Bad_Opcode }, | |
6286 | { Bad_Opcode }, | |
6287 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6288 | }, | |
6289 | ||
f12dc422 L |
6290 | /* PREFIX_VEX_0F38F7 */ |
6291 | { | |
6292 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6293 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6294 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6295 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6296 | }, | |
6297 | ||
6298 | /* PREFIX_VEX_0F3A00 */ | |
6299 | { | |
6300 | { Bad_Opcode }, | |
6301 | { Bad_Opcode }, | |
6302 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6303 | }, | |
6304 | ||
6305 | /* PREFIX_VEX_0F3A01 */ | |
6306 | { | |
6307 | { Bad_Opcode }, | |
6308 | { Bad_Opcode }, | |
6309 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6310 | }, | |
6311 | ||
6312 | /* PREFIX_VEX_0F3A02 */ | |
6313 | { | |
6314 | { Bad_Opcode }, | |
6315 | { Bad_Opcode }, | |
6316 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6317 | }, |
6318 | ||
592a252b | 6319 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6320 | { |
592d1631 L |
6321 | { Bad_Opcode }, |
6322 | { Bad_Opcode }, | |
592a252b | 6323 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6324 | }, |
6325 | ||
592a252b | 6326 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6327 | { |
592d1631 L |
6328 | { Bad_Opcode }, |
6329 | { Bad_Opcode }, | |
592a252b | 6330 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6331 | }, |
6332 | ||
592a252b | 6333 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6334 | { |
592d1631 L |
6335 | { Bad_Opcode }, |
6336 | { Bad_Opcode }, | |
592a252b | 6337 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6338 | }, |
6339 | ||
592a252b | 6340 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6341 | { |
592d1631 L |
6342 | { Bad_Opcode }, |
6343 | { Bad_Opcode }, | |
ec6f095a | 6344 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6345 | }, |
6346 | ||
592a252b | 6347 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6348 | { |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
ec6f095a | 6351 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6352 | }, |
6353 | ||
592a252b | 6354 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6355 | { |
592d1631 L |
6356 | { Bad_Opcode }, |
6357 | { Bad_Opcode }, | |
5b872f7d | 6358 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6359 | }, |
6360 | ||
592a252b | 6361 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6362 | { |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
5b872f7d | 6365 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6366 | }, |
6367 | ||
592a252b | 6368 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6369 | { |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
ec6f095a | 6372 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6373 | }, |
6374 | ||
592a252b | 6375 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6376 | { |
592d1631 L |
6377 | { Bad_Opcode }, |
6378 | { Bad_Opcode }, | |
ec6f095a | 6379 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6380 | }, |
6381 | ||
592a252b | 6382 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6383 | { |
592d1631 L |
6384 | { Bad_Opcode }, |
6385 | { Bad_Opcode }, | |
ec6f095a | 6386 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6387 | }, |
6388 | ||
592a252b | 6389 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6390 | { |
592d1631 L |
6391 | { Bad_Opcode }, |
6392 | { Bad_Opcode }, | |
ec6f095a | 6393 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6394 | }, |
6395 | ||
592a252b | 6396 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6397 | { |
592d1631 L |
6398 | { Bad_Opcode }, |
6399 | { Bad_Opcode }, | |
592a252b | 6400 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6401 | }, |
6402 | ||
592a252b | 6403 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6404 | { |
592d1631 L |
6405 | { Bad_Opcode }, |
6406 | { Bad_Opcode }, | |
592a252b | 6407 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6408 | }, |
6409 | ||
592a252b | 6410 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6411 | { |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
592a252b | 6414 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6415 | }, |
6416 | ||
592a252b | 6417 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6418 | { |
592d1631 L |
6419 | { Bad_Opcode }, |
6420 | { Bad_Opcode }, | |
592a252b | 6421 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6422 | }, |
6423 | ||
592a252b | 6424 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6425 | { |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
592a252b | 6428 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6429 | }, |
6430 | ||
592a252b | 6431 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6432 | { |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
592a252b | 6435 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6436 | }, |
6437 | ||
592a252b | 6438 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6439 | { |
6440 | { Bad_Opcode }, | |
6441 | { Bad_Opcode }, | |
6431c801 | 6442 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6443 | }, |
6444 | ||
592a252b | 6445 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6446 | { |
592d1631 L |
6447 | { Bad_Opcode }, |
6448 | { Bad_Opcode }, | |
592a252b | 6449 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6450 | }, |
6451 | ||
592a252b | 6452 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6453 | { |
592d1631 L |
6454 | { Bad_Opcode }, |
6455 | { Bad_Opcode }, | |
592a252b | 6456 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6457 | }, |
6458 | ||
592a252b | 6459 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6460 | { |
592d1631 L |
6461 | { Bad_Opcode }, |
6462 | { Bad_Opcode }, | |
592a252b | 6463 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6464 | }, |
6465 | ||
43234a1e L |
6466 | /* PREFIX_VEX_0F3A30 */ |
6467 | { | |
6468 | { Bad_Opcode }, | |
6469 | { Bad_Opcode }, | |
6470 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6471 | }, | |
6472 | ||
1ba585e8 IT |
6473 | /* PREFIX_VEX_0F3A31 */ |
6474 | { | |
6475 | { Bad_Opcode }, | |
6476 | { Bad_Opcode }, | |
6477 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6478 | }, | |
6479 | ||
43234a1e L |
6480 | /* PREFIX_VEX_0F3A32 */ |
6481 | { | |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6485 | }, | |
6486 | ||
1ba585e8 IT |
6487 | /* PREFIX_VEX_0F3A33 */ |
6488 | { | |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6492 | }, | |
6493 | ||
6c30d220 L |
6494 | /* PREFIX_VEX_0F3A38 */ |
6495 | { | |
6496 | { Bad_Opcode }, | |
6497 | { Bad_Opcode }, | |
6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6499 | }, | |
6500 | ||
6501 | /* PREFIX_VEX_0F3A39 */ | |
6502 | { | |
6503 | { Bad_Opcode }, | |
6504 | { Bad_Opcode }, | |
6505 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6506 | }, | |
6507 | ||
592a252b | 6508 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6509 | { |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
ec6f095a | 6512 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6513 | }, |
6514 | ||
592a252b | 6515 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6516 | { |
592d1631 L |
6517 | { Bad_Opcode }, |
6518 | { Bad_Opcode }, | |
592a252b | 6519 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6520 | }, |
6521 | ||
592a252b | 6522 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6523 | { |
592d1631 L |
6524 | { Bad_Opcode }, |
6525 | { Bad_Opcode }, | |
ec6f095a | 6526 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6527 | }, |
6528 | ||
592a252b | 6529 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6530 | { |
592d1631 L |
6531 | { Bad_Opcode }, |
6532 | { Bad_Opcode }, | |
ff1982d5 | 6533 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6534 | }, |
6535 | ||
6c30d220 L |
6536 | /* PREFIX_VEX_0F3A46 */ |
6537 | { | |
6538 | { Bad_Opcode }, | |
6539 | { Bad_Opcode }, | |
6540 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6541 | }, | |
6542 | ||
592a252b | 6543 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6544 | { |
6545 | { Bad_Opcode }, | |
6546 | { Bad_Opcode }, | |
93abb146 | 6547 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6548 | }, |
6549 | ||
592a252b | 6550 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6551 | { |
6552 | { Bad_Opcode }, | |
6553 | { Bad_Opcode }, | |
93abb146 | 6554 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6555 | }, |
6556 | ||
592a252b | 6557 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6558 | { |
592d1631 L |
6559 | { Bad_Opcode }, |
6560 | { Bad_Opcode }, | |
592a252b | 6561 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6562 | }, |
6563 | ||
592a252b | 6564 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6565 | { |
592d1631 L |
6566 | { Bad_Opcode }, |
6567 | { Bad_Opcode }, | |
592a252b | 6568 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6572 | { |
592d1631 L |
6573 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, | |
6c30d220 | 6575 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6576 | }, |
6577 | ||
592a252b | 6578 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6579 | { |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
b13b1bc0 | 6582 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6583 | }, |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6586 | { |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
b13b1bc0 | 6589 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6590 | }, |
6591 | ||
592a252b | 6592 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6593 | { |
592d1631 L |
6594 | { Bad_Opcode }, |
6595 | { Bad_Opcode }, | |
b13b1bc0 | 6596 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6597 | }, |
6598 | ||
592a252b | 6599 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6600 | { |
592d1631 L |
6601 | { Bad_Opcode }, |
6602 | { Bad_Opcode }, | |
b13b1bc0 | 6603 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6604 | }, |
6605 | ||
592a252b | 6606 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6607 | { |
592d1631 L |
6608 | { Bad_Opcode }, |
6609 | { Bad_Opcode }, | |
592a252b | 6610 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6611 | { Bad_Opcode }, |
c0f3af97 L |
6612 | }, |
6613 | ||
592a252b | 6614 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6615 | { |
592d1631 L |
6616 | { Bad_Opcode }, |
6617 | { Bad_Opcode }, | |
592a252b | 6618 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6619 | }, |
6620 | ||
592a252b | 6621 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6622 | { |
592d1631 L |
6623 | { Bad_Opcode }, |
6624 | { Bad_Opcode }, | |
592a252b | 6625 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6626 | }, |
6627 | ||
592a252b | 6628 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6629 | { |
592d1631 L |
6630 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, | |
592a252b | 6632 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6633 | }, |
a5ff0eb2 | 6634 | |
592a252b | 6635 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6636 | { |
592d1631 L |
6637 | { Bad_Opcode }, |
6638 | { Bad_Opcode }, | |
b13b1bc0 | 6639 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6640 | }, |
6641 | ||
592a252b | 6642 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6643 | { |
592d1631 L |
6644 | { Bad_Opcode }, |
6645 | { Bad_Opcode }, | |
b13b1bc0 | 6646 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6647 | }, |
6648 | ||
592a252b | 6649 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6650 | { |
592d1631 L |
6651 | { Bad_Opcode }, |
6652 | { Bad_Opcode }, | |
6384fd9e | 6653 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6654 | }, |
6655 | ||
592a252b | 6656 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6657 | { |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
6384fd9e | 6660 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6661 | }, |
6662 | ||
592a252b | 6663 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6664 | { |
592d1631 L |
6665 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, | |
b13b1bc0 | 6667 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6668 | }, |
6669 | ||
592a252b | 6670 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6671 | { |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
b13b1bc0 | 6674 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6675 | }, |
6676 | ||
592a252b | 6677 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6678 | { |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
6384fd9e | 6681 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
6384fd9e | 6688 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
b13b1bc0 | 6695 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
b13b1bc0 | 6702 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6703 | }, |
6704 | ||
592a252b | 6705 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6706 | { |
592d1631 L |
6707 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, | |
6384fd9e | 6709 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6710 | }, |
6711 | ||
592a252b | 6712 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6713 | { |
592d1631 L |
6714 | { Bad_Opcode }, |
6715 | { Bad_Opcode }, | |
6384fd9e | 6716 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6717 | }, |
6718 | ||
592a252b | 6719 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6720 | { |
592d1631 L |
6721 | { Bad_Opcode }, |
6722 | { Bad_Opcode }, | |
b13b1bc0 | 6723 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 6724 | { Bad_Opcode }, |
922d8de8 DR |
6725 | }, |
6726 | ||
592a252b | 6727 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6728 | { |
592d1631 L |
6729 | { Bad_Opcode }, |
6730 | { Bad_Opcode }, | |
b13b1bc0 | 6731 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6732 | }, |
6733 | ||
592a252b | 6734 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6735 | { |
592d1631 L |
6736 | { Bad_Opcode }, |
6737 | { Bad_Opcode }, | |
6384fd9e | 6738 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6739 | }, |
6740 | ||
592a252b | 6741 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6742 | { |
592d1631 L |
6743 | { Bad_Opcode }, |
6744 | { Bad_Opcode }, | |
6384fd9e | 6745 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6746 | }, |
6747 | ||
48521003 IT |
6748 | /* PREFIX_VEX_0F3ACE */ |
6749 | { | |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
6752 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6753 | }, | |
6754 | ||
6755 | /* PREFIX_VEX_0F3ACF */ | |
6756 | { | |
6757 | { Bad_Opcode }, | |
6758 | { Bad_Opcode }, | |
6759 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6760 | }, | |
6761 | ||
592a252b | 6762 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6763 | { |
592d1631 L |
6764 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, | |
592a252b | 6766 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6767 | }, |
6c30d220 L |
6768 | |
6769 | /* PREFIX_VEX_0F3AF0 */ | |
6770 | { | |
6771 | { Bad_Opcode }, | |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6775 | }, | |
43234a1e | 6776 | |
ad692897 | 6777 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6778 | }; |
6779 | ||
6780 | static const struct dis386 x86_64_table[][2] = { | |
6781 | /* X86_64_06 */ | |
6782 | { | |
bf890a93 | 6783 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6784 | }, |
6785 | ||
6786 | /* X86_64_07 */ | |
6787 | { | |
bf890a93 | 6788 | { "popP", { es }, 0 }, |
c0f3af97 L |
6789 | }, |
6790 | ||
1673df32 | 6791 | /* X86_64_0E */ |
c0f3af97 | 6792 | { |
bf890a93 | 6793 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6794 | }, |
6795 | ||
6796 | /* X86_64_16 */ | |
6797 | { | |
bf890a93 | 6798 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6799 | }, |
6800 | ||
6801 | /* X86_64_17 */ | |
6802 | { | |
bf890a93 | 6803 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6804 | }, |
6805 | ||
6806 | /* X86_64_1E */ | |
6807 | { | |
bf890a93 | 6808 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6809 | }, |
6810 | ||
6811 | /* X86_64_1F */ | |
6812 | { | |
bf890a93 | 6813 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6814 | }, |
6815 | ||
6816 | /* X86_64_27 */ | |
6817 | { | |
bf890a93 | 6818 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6819 | }, |
6820 | ||
6821 | /* X86_64_2F */ | |
6822 | { | |
bf890a93 | 6823 | { "das", { XX }, 0 }, |
c0f3af97 L |
6824 | }, |
6825 | ||
6826 | /* X86_64_37 */ | |
6827 | { | |
bf890a93 | 6828 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6829 | }, |
6830 | ||
6831 | /* X86_64_3F */ | |
6832 | { | |
bf890a93 | 6833 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6834 | }, |
6835 | ||
6836 | /* X86_64_60 */ | |
6837 | { | |
bf890a93 | 6838 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6839 | }, |
6840 | ||
6841 | /* X86_64_61 */ | |
6842 | { | |
bf890a93 | 6843 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6844 | }, |
6845 | ||
6846 | /* X86_64_62 */ | |
6847 | { | |
6848 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6849 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6850 | }, |
6851 | ||
6852 | /* X86_64_63 */ | |
6853 | { | |
bf890a93 | 6854 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6855 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6856 | }, |
6857 | ||
6858 | /* X86_64_6D */ | |
6859 | { | |
bf890a93 IT |
6860 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6861 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6862 | }, |
6863 | ||
6864 | /* X86_64_6F */ | |
6865 | { | |
bf890a93 IT |
6866 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6867 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6868 | }, |
6869 | ||
d039fef3 | 6870 | /* X86_64_82 */ |
8b89fe14 | 6871 | { |
de194d85 | 6872 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6873 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6874 | }, |
6875 | ||
c0f3af97 L |
6876 | /* X86_64_9A */ |
6877 | { | |
8f570d62 | 6878 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6879 | }, |
6880 | ||
aeab2b26 JB |
6881 | /* X86_64_C2 */ |
6882 | { | |
6883 | { "retP", { Iw, BND }, 0 }, | |
6884 | { "ret@", { Iw, BND }, 0 }, | |
6885 | }, | |
6886 | ||
6887 | /* X86_64_C3 */ | |
6888 | { | |
6889 | { "retP", { BND }, 0 }, | |
6890 | { "ret@", { BND }, 0 }, | |
6891 | }, | |
6892 | ||
c0f3af97 L |
6893 | /* X86_64_C4 */ |
6894 | { | |
6895 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6896 | { VEX_C4_TABLE (VEX_0F) }, | |
6897 | }, | |
6898 | ||
6899 | /* X86_64_C5 */ | |
6900 | { | |
6901 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6902 | { VEX_C5_TABLE (VEX_0F) }, | |
6903 | }, | |
6904 | ||
6905 | /* X86_64_CE */ | |
6906 | { | |
bf890a93 | 6907 | { "into", { XX }, 0 }, |
c0f3af97 L |
6908 | }, |
6909 | ||
6910 | /* X86_64_D4 */ | |
6911 | { | |
bf890a93 | 6912 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6913 | }, |
6914 | ||
6915 | /* X86_64_D5 */ | |
6916 | { | |
bf890a93 | 6917 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6918 | }, |
6919 | ||
a72d2af2 L |
6920 | /* X86_64_E8 */ |
6921 | { | |
6922 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6923 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6924 | }, |
6925 | ||
6926 | /* X86_64_E9 */ | |
6927 | { | |
6928 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6929 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6930 | }, |
6931 | ||
c0f3af97 L |
6932 | /* X86_64_EA */ |
6933 | { | |
8f570d62 | 6934 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6935 | }, |
6936 | ||
6937 | /* X86_64_0F01_REG_0 */ | |
6938 | { | |
d1c36125 | 6939 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6940 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6941 | }, |
6942 | ||
6943 | /* X86_64_0F01_REG_1 */ | |
6944 | { | |
d1c36125 | 6945 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6946 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6947 | }, |
6948 | ||
6949 | /* X86_64_0F01_REG_2 */ | |
6950 | { | |
bf890a93 IT |
6951 | { "lgdt{Q|Q}", { M }, 0 }, |
6952 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6953 | }, |
6954 | ||
6955 | /* X86_64_0F01_REG_3 */ | |
6956 | { | |
bf890a93 IT |
6957 | { "lidt{Q|Q}", { M }, 0 }, |
6958 | { "lidt", { M }, 0 }, | |
c0f3af97 | 6959 | }, |
260cd341 LC |
6960 | |
6961 | /* X86_64_VEX_0F3849 */ | |
6962 | { | |
6963 | { Bad_Opcode }, | |
6964 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
6965 | }, | |
6966 | ||
6967 | /* X86_64_VEX_0F384B */ | |
6968 | { | |
6969 | { Bad_Opcode }, | |
6970 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
6971 | }, | |
6972 | ||
6973 | /* X86_64_VEX_0F385C */ | |
6974 | { | |
6975 | { Bad_Opcode }, | |
6976 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
6977 | }, | |
6978 | ||
6979 | /* X86_64_VEX_0F385E */ | |
6980 | { | |
6981 | { Bad_Opcode }, | |
6982 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
6983 | }, | |
c0f3af97 L |
6984 | }; |
6985 | ||
6986 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6987 | |
6988 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6989 | { |
6990 | /* 00 */ | |
507bd325 L |
6991 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6992 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6993 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6994 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6995 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6996 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6997 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6998 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6999 | /* 08 */ |
507bd325 L |
7000 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7001 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7002 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7003 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7004 | { Bad_Opcode }, |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
f88c9eb0 SP |
7008 | /* 10 */ |
7009 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7010 | { Bad_Opcode }, |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
f88c9eb0 SP |
7013 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7014 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7015 | { Bad_Opcode }, |
f88c9eb0 SP |
7016 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7017 | /* 18 */ | |
592d1631 L |
7018 | { Bad_Opcode }, |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
507bd325 L |
7022 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7023 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7024 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7025 | { Bad_Opcode }, |
f88c9eb0 SP |
7026 | /* 20 */ |
7027 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7028 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7029 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7030 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7031 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7032 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7033 | { Bad_Opcode }, |
7034 | { Bad_Opcode }, | |
f88c9eb0 SP |
7035 | /* 28 */ |
7036 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7037 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7038 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7039 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7040 | { Bad_Opcode }, |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
f88c9eb0 SP |
7044 | /* 30 */ |
7045 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7046 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7047 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7048 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7049 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7050 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7051 | { Bad_Opcode }, |
f88c9eb0 SP |
7052 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7053 | /* 38 */ | |
7054 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7055 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7056 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7057 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7058 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7059 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7060 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7061 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7062 | /* 40 */ | |
7063 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7064 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7065 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
f88c9eb0 | 7071 | /* 48 */ |
592d1631 L |
7072 | { Bad_Opcode }, |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
f88c9eb0 | 7080 | /* 50 */ |
592d1631 L |
7081 | { Bad_Opcode }, |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
f88c9eb0 | 7089 | /* 58 */ |
592d1631 L |
7090 | { Bad_Opcode }, |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
f88c9eb0 | 7098 | /* 60 */ |
592d1631 L |
7099 | { Bad_Opcode }, |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
f88c9eb0 | 7107 | /* 68 */ |
592d1631 L |
7108 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
f88c9eb0 | 7116 | /* 70 */ |
592d1631 L |
7117 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
f88c9eb0 | 7125 | /* 78 */ |
592d1631 L |
7126 | { Bad_Opcode }, |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
f88c9eb0 SP |
7134 | /* 80 */ |
7135 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7136 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7137 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7138 | { Bad_Opcode }, |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
f88c9eb0 | 7143 | /* 88 */ |
592d1631 L |
7144 | { Bad_Opcode }, |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
f88c9eb0 | 7152 | /* 90 */ |
592d1631 L |
7153 | { Bad_Opcode }, |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
f88c9eb0 | 7161 | /* 98 */ |
592d1631 L |
7162 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
f88c9eb0 | 7170 | /* a0 */ |
592d1631 L |
7171 | { Bad_Opcode }, |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
f88c9eb0 | 7179 | /* a8 */ |
592d1631 L |
7180 | { Bad_Opcode }, |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
f88c9eb0 | 7188 | /* b0 */ |
592d1631 L |
7189 | { Bad_Opcode }, |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
f88c9eb0 | 7197 | /* b8 */ |
592d1631 L |
7198 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
f88c9eb0 | 7206 | /* c0 */ |
592d1631 L |
7207 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
f88c9eb0 | 7215 | /* c8 */ |
a0046408 L |
7216 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7217 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7218 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7219 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7220 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7221 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7222 | { Bad_Opcode }, |
48521003 | 7223 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7224 | /* d0 */ |
592d1631 L |
7225 | { Bad_Opcode }, |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
f88c9eb0 | 7233 | /* d8 */ |
592d1631 L |
7234 | { Bad_Opcode }, |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
f88c9eb0 SP |
7237 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7238 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7239 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7240 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7241 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7242 | /* e0 */ | |
592d1631 L |
7243 | { Bad_Opcode }, |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
f88c9eb0 | 7251 | /* e8 */ |
592d1631 L |
7252 | { Bad_Opcode }, |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
f88c9eb0 SP |
7260 | /* f0 */ |
7261 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7263 | { Bad_Opcode }, |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
603555e5 | 7266 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7267 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7268 | { Bad_Opcode }, |
f88c9eb0 | 7269 | /* f8 */ |
c0a30a9f L |
7270 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7271 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7272 | { Bad_Opcode }, |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
f88c9eb0 SP |
7278 | }, |
7279 | /* THREE_BYTE_0F3A */ | |
7280 | { | |
7281 | /* 00 */ | |
592d1631 L |
7282 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
f88c9eb0 SP |
7290 | /* 08 */ |
7291 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7292 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7293 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7294 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7295 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7296 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7297 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7298 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7299 | /* 10 */ |
592d1631 L |
7300 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
f88c9eb0 SP |
7304 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7305 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7306 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7307 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7308 | /* 18 */ | |
592d1631 L |
7309 | { Bad_Opcode }, |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
f88c9eb0 SP |
7317 | /* 20 */ |
7318 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7319 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7320 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7321 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
f88c9eb0 | 7326 | /* 28 */ |
592d1631 L |
7327 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
f88c9eb0 | 7335 | /* 30 */ |
592d1631 L |
7336 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
f88c9eb0 | 7344 | /* 38 */ |
592d1631 L |
7345 | { Bad_Opcode }, |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
f88c9eb0 SP |
7353 | /* 40 */ |
7354 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7355 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7356 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7357 | { Bad_Opcode }, |
f88c9eb0 | 7358 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7359 | { Bad_Opcode }, |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
f88c9eb0 | 7362 | /* 48 */ |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
f88c9eb0 | 7371 | /* 50 */ |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
f88c9eb0 | 7380 | /* 58 */ |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
f88c9eb0 SP |
7389 | /* 60 */ |
7390 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7391 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7392 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7393 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7394 | { Bad_Opcode }, |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
f88c9eb0 | 7398 | /* 68 */ |
592d1631 L |
7399 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
f88c9eb0 | 7407 | /* 70 */ |
592d1631 L |
7408 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
f88c9eb0 | 7416 | /* 78 */ |
592d1631 L |
7417 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
f88c9eb0 | 7425 | /* 80 */ |
592d1631 L |
7426 | { Bad_Opcode }, |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
f88c9eb0 | 7434 | /* 88 */ |
592d1631 L |
7435 | { Bad_Opcode }, |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
f88c9eb0 | 7443 | /* 90 */ |
592d1631 L |
7444 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
f88c9eb0 | 7452 | /* 98 */ |
592d1631 L |
7453 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
f88c9eb0 | 7461 | /* a0 */ |
592d1631 L |
7462 | { Bad_Opcode }, |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
f88c9eb0 | 7470 | /* a8 */ |
592d1631 L |
7471 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
f88c9eb0 | 7479 | /* b0 */ |
592d1631 L |
7480 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
f88c9eb0 | 7488 | /* b8 */ |
592d1631 L |
7489 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
f88c9eb0 | 7497 | /* c0 */ |
592d1631 L |
7498 | { Bad_Opcode }, |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
f88c9eb0 | 7506 | /* c8 */ |
592d1631 L |
7507 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
a0046408 | 7511 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7512 | { Bad_Opcode }, |
48521003 IT |
7513 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7514 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7515 | /* d0 */ |
592d1631 L |
7516 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
f88c9eb0 | 7524 | /* d8 */ |
592d1631 L |
7525 | { Bad_Opcode }, |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
f88c9eb0 SP |
7532 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7533 | /* e0 */ | |
592d1631 L |
7534 | { Bad_Opcode }, |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
85f10a01 | 7542 | /* e8 */ |
592d1631 L |
7543 | { Bad_Opcode }, |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
85f10a01 | 7551 | /* f0 */ |
592d1631 L |
7552 | { Bad_Opcode }, |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
85f10a01 | 7560 | /* f8 */ |
592d1631 L |
7561 | { Bad_Opcode }, |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
85f10a01 | 7569 | }, |
f88c9eb0 SP |
7570 | }; |
7571 | ||
7572 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7573 | /* XOP_08 */ |
85f10a01 MM |
7574 | { |
7575 | /* 00 */ | |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
85f10a01 | 7584 | /* 08 */ |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
85f10a01 | 7593 | /* 10 */ |
3929df09 | 7594 | { Bad_Opcode }, |
592d1631 L |
7595 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
85f10a01 | 7602 | /* 18 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | /* 20 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
85f10a01 | 7620 | /* 28 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
c0f3af97 | 7629 | /* 30 */ |
592d1631 L |
7630 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
c0f3af97 | 7638 | /* 38 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
c0f3af97 | 7647 | /* 40 */ |
592d1631 L |
7648 | { Bad_Opcode }, |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
85f10a01 | 7656 | /* 48 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
c0f3af97 | 7665 | /* 50 */ |
592d1631 L |
7666 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
85f10a01 | 7674 | /* 58 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
c1e679ec | 7683 | /* 60 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
c0f3af97 | 7692 | /* 68 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
85f10a01 | 7701 | /* 70 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
85f10a01 | 7710 | /* 78 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
85f10a01 | 7719 | /* 80 */ |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
467bbef0 JB |
7725 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
7726 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
7727 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 7728 | /* 88 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
467bbef0 JB |
7735 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
7736 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 7737 | /* 90 */ |
592d1631 L |
7738 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
467bbef0 JB |
7743 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
7744 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
7745 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 7746 | /* 98 */ |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
467bbef0 JB |
7753 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
7754 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 7755 | /* a0 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
b13b1bc0 | 7758 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 7759 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
7760 | { Bad_Opcode }, |
7761 | { Bad_Opcode }, | |
467bbef0 | 7762 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 7763 | { Bad_Opcode }, |
5dd85c99 | 7764 | /* a8 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
5dd85c99 | 7773 | /* b0 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
467bbef0 | 7780 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 7781 | { Bad_Opcode }, |
5dd85c99 | 7782 | /* b8 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
5dd85c99 | 7791 | /* c0 */ |
467bbef0 JB |
7792 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
7793 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
7794 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
7795 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
7796 | { Bad_Opcode }, |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
5dd85c99 | 7800 | /* c8 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
ff688e1f L |
7805 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7806 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7807 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7808 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7809 | /* d0 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
5dd85c99 | 7818 | /* d8 */ |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
5dd85c99 | 7827 | /* e0 */ |
592d1631 L |
7828 | { Bad_Opcode }, |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
5dd85c99 | 7836 | /* e8 */ |
592d1631 L |
7837 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
ff688e1f L |
7841 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7842 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7843 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7844 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7845 | /* f0 */ |
592d1631 L |
7846 | { Bad_Opcode }, |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
5dd85c99 | 7854 | /* f8 */ |
592d1631 L |
7855 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
5dd85c99 SP |
7863 | }, |
7864 | /* XOP_09 */ | |
7865 | { | |
7866 | /* 00 */ | |
592d1631 | 7867 | { Bad_Opcode }, |
467bbef0 JB |
7868 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
7869 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
7870 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
5dd85c99 | 7875 | /* 08 */ |
592d1631 L |
7876 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
5dd85c99 | 7884 | /* 10 */ |
592d1631 L |
7885 | { Bad_Opcode }, |
7886 | { Bad_Opcode }, | |
467bbef0 | 7887 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
5dd85c99 | 7893 | /* 18 */ |
592d1631 L |
7894 | { Bad_Opcode }, |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
5dd85c99 | 7902 | /* 20 */ |
592d1631 L |
7903 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
5dd85c99 | 7911 | /* 28 */ |
592d1631 L |
7912 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
5dd85c99 | 7920 | /* 30 */ |
592d1631 L |
7921 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
5dd85c99 | 7929 | /* 38 */ |
592d1631 L |
7930 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
5dd85c99 | 7938 | /* 40 */ |
592d1631 L |
7939 | { Bad_Opcode }, |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
5dd85c99 | 7947 | /* 48 */ |
592d1631 L |
7948 | { Bad_Opcode }, |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
5dd85c99 | 7956 | /* 50 */ |
592d1631 L |
7957 | { Bad_Opcode }, |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
5dd85c99 | 7965 | /* 58 */ |
592d1631 L |
7966 | { Bad_Opcode }, |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
5dd85c99 | 7974 | /* 60 */ |
592d1631 L |
7975 | { Bad_Opcode }, |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
5dd85c99 | 7983 | /* 68 */ |
592d1631 L |
7984 | { Bad_Opcode }, |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
5dd85c99 | 7992 | /* 70 */ |
592d1631 L |
7993 | { Bad_Opcode }, |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
5dd85c99 | 8001 | /* 78 */ |
592d1631 L |
8002 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
5dd85c99 | 8010 | /* 80 */ |
b5b098c2 JB |
8011 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
8012 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
8013 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
8014 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
8015 | { Bad_Opcode }, |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
5dd85c99 | 8019 | /* 88 */ |
592d1631 L |
8020 | { Bad_Opcode }, |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
5dd85c99 | 8028 | /* 90 */ |
467bbef0 JB |
8029 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
8030 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
8031 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
8032 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
8033 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
8034 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
8035 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
8036 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 8037 | /* 98 */ |
467bbef0 JB |
8038 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
8039 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
8040 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
8041 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
8042 | { Bad_Opcode }, |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
5dd85c99 | 8046 | /* a0 */ |
592d1631 L |
8047 | { Bad_Opcode }, |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
5dd85c99 | 8055 | /* a8 */ |
592d1631 L |
8056 | { Bad_Opcode }, |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
5dd85c99 | 8064 | /* b0 */ |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
5dd85c99 | 8073 | /* b8 */ |
592d1631 L |
8074 | { Bad_Opcode }, |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
5dd85c99 | 8082 | /* c0 */ |
592d1631 | 8083 | { Bad_Opcode }, |
467bbef0 JB |
8084 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
8085 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
8086 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
8087 | { Bad_Opcode }, |
8088 | { Bad_Opcode }, | |
467bbef0 JB |
8089 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
8090 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 8091 | /* c8 */ |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
467bbef0 | 8095 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
8096 | { Bad_Opcode }, |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
5dd85c99 | 8100 | /* d0 */ |
592d1631 | 8101 | { Bad_Opcode }, |
467bbef0 JB |
8102 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
8103 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
8104 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
8105 | { Bad_Opcode }, |
8106 | { Bad_Opcode }, | |
467bbef0 JB |
8107 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
8108 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 8109 | /* d8 */ |
592d1631 L |
8110 | { Bad_Opcode }, |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
467bbef0 | 8113 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
8114 | { Bad_Opcode }, |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
5dd85c99 | 8118 | /* e0 */ |
592d1631 | 8119 | { Bad_Opcode }, |
467bbef0 JB |
8120 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
8121 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
8122 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
8123 | { Bad_Opcode }, |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
4e7d34a6 | 8127 | /* e8 */ |
592d1631 L |
8128 | { Bad_Opcode }, |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
4e7d34a6 | 8136 | /* f0 */ |
592d1631 L |
8137 | { Bad_Opcode }, |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
4e7d34a6 | 8145 | /* f8 */ |
592d1631 L |
8146 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
4e7d34a6 | 8154 | }, |
f88c9eb0 | 8155 | /* XOP_0A */ |
4e7d34a6 L |
8156 | { |
8157 | /* 00 */ | |
592d1631 L |
8158 | { Bad_Opcode }, |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
4e7d34a6 | 8166 | /* 08 */ |
592d1631 L |
8167 | { Bad_Opcode }, |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
4e7d34a6 | 8175 | /* 10 */ |
c1dc7af5 | 8176 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8177 | { Bad_Opcode }, |
467bbef0 | 8178 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
4e7d34a6 | 8184 | /* 18 */ |
592d1631 L |
8185 | { Bad_Opcode }, |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
4e7d34a6 | 8193 | /* 20 */ |
592d1631 L |
8194 | { Bad_Opcode }, |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
4e7d34a6 | 8202 | /* 28 */ |
592d1631 L |
8203 | { Bad_Opcode }, |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
4e7d34a6 | 8211 | /* 30 */ |
592d1631 L |
8212 | { Bad_Opcode }, |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
c0f3af97 | 8220 | /* 38 */ |
592d1631 L |
8221 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
c0f3af97 | 8229 | /* 40 */ |
592d1631 L |
8230 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
c1e679ec | 8238 | /* 48 */ |
592d1631 L |
8239 | { Bad_Opcode }, |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
c1e679ec | 8247 | /* 50 */ |
592d1631 L |
8248 | { Bad_Opcode }, |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
4e7d34a6 | 8256 | /* 58 */ |
592d1631 L |
8257 | { Bad_Opcode }, |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
4e7d34a6 | 8265 | /* 60 */ |
592d1631 L |
8266 | { Bad_Opcode }, |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
4e7d34a6 | 8274 | /* 68 */ |
592d1631 L |
8275 | { Bad_Opcode }, |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
4e7d34a6 | 8283 | /* 70 */ |
592d1631 L |
8284 | { Bad_Opcode }, |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
4e7d34a6 | 8292 | /* 78 */ |
592d1631 L |
8293 | { Bad_Opcode }, |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
4e7d34a6 | 8301 | /* 80 */ |
592d1631 L |
8302 | { Bad_Opcode }, |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
4e7d34a6 | 8310 | /* 88 */ |
592d1631 L |
8311 | { Bad_Opcode }, |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
4e7d34a6 | 8319 | /* 90 */ |
592d1631 L |
8320 | { Bad_Opcode }, |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
4e7d34a6 | 8328 | /* 98 */ |
592d1631 L |
8329 | { Bad_Opcode }, |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
4e7d34a6 | 8337 | /* a0 */ |
592d1631 L |
8338 | { Bad_Opcode }, |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
4e7d34a6 | 8346 | /* a8 */ |
592d1631 L |
8347 | { Bad_Opcode }, |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
d5d7db8e | 8355 | /* b0 */ |
592d1631 L |
8356 | { Bad_Opcode }, |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
85f10a01 | 8364 | /* b8 */ |
592d1631 L |
8365 | { Bad_Opcode }, |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
85f10a01 | 8373 | /* c0 */ |
592d1631 L |
8374 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
85f10a01 | 8382 | /* c8 */ |
592d1631 L |
8383 | { Bad_Opcode }, |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
85f10a01 | 8391 | /* d0 */ |
592d1631 L |
8392 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
85f10a01 | 8400 | /* d8 */ |
592d1631 L |
8401 | { Bad_Opcode }, |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
85f10a01 | 8409 | /* e0 */ |
592d1631 L |
8410 | { Bad_Opcode }, |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
85f10a01 | 8418 | /* e8 */ |
592d1631 L |
8419 | { Bad_Opcode }, |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
85f10a01 | 8427 | /* f0 */ |
592d1631 L |
8428 | { Bad_Opcode }, |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
85f10a01 | 8436 | /* f8 */ |
592d1631 L |
8437 | { Bad_Opcode }, |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
85f10a01 | 8445 | }, |
c0f3af97 L |
8446 | }; |
8447 | ||
8448 | static const struct dis386 vex_table[][256] = { | |
8449 | /* VEX_0F */ | |
85f10a01 MM |
8450 | { |
8451 | /* 00 */ | |
592d1631 L |
8452 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
85f10a01 | 8460 | /* 08 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
c0f3af97 | 8469 | /* 10 */ |
592a252b L |
8470 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8471 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8472 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8473 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8474 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8475 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8476 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8477 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8478 | /* 18 */ |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
c0f3af97 | 8487 | /* 20 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
c0f3af97 | 8496 | /* 28 */ |
bf926894 JB |
8497 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8498 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8499 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8500 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8501 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8502 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8503 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8504 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8505 | /* 30 */ |
592d1631 L |
8506 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
4e7d34a6 | 8514 | /* 38 */ |
592d1631 L |
8515 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
d5d7db8e | 8523 | /* 40 */ |
592d1631 | 8524 | { Bad_Opcode }, |
43234a1e L |
8525 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8527 | { Bad_Opcode }, |
43234a1e L |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8532 | /* 48 */ |
592d1631 L |
8533 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, | |
1ba585e8 | 8535 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8536 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8537 | { Bad_Opcode }, |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
d5d7db8e | 8541 | /* 50 */ |
592a252b L |
8542 | { MOD_TABLE (MOD_VEX_0F50) }, |
8543 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8544 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8546 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8547 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8548 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8549 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8550 | /* 58 */ |
592a252b L |
8551 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8555 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8556 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8557 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8559 | /* 60 */ |
592a252b L |
8560 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8561 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8564 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8565 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8566 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8568 | /* 68 */ |
592a252b L |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8574 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8575 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8577 | /* 70 */ |
592a252b L |
8578 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8579 | { REG_TABLE (REG_VEX_0F71) }, | |
8580 | { REG_TABLE (REG_VEX_0F72) }, | |
8581 | { REG_TABLE (REG_VEX_0F73) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8583 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8584 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8585 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8586 | /* 78 */ |
592d1631 L |
8587 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
592a252b L |
8591 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8592 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8593 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8594 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8595 | /* 80 */ |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
c0f3af97 | 8604 | /* 88 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
c0f3af97 | 8613 | /* 90 */ |
43234a1e L |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8618 | { Bad_Opcode }, |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
c0f3af97 | 8622 | /* 98 */ |
43234a1e | 8623 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8624 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8625 | { Bad_Opcode }, |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
c0f3af97 | 8631 | /* a0 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
c0f3af97 | 8640 | /* a8 */ |
592d1631 L |
8641 | { Bad_Opcode }, |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
592a252b | 8647 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8648 | { Bad_Opcode }, |
c0f3af97 | 8649 | /* b0 */ |
592d1631 L |
8650 | { Bad_Opcode }, |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
8655 | { Bad_Opcode }, | |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
c0f3af97 | 8658 | /* b8 */ |
592d1631 L |
8659 | { Bad_Opcode }, |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
c0f3af97 | 8667 | /* c0 */ |
592d1631 L |
8668 | { Bad_Opcode }, |
8669 | { Bad_Opcode }, | |
592a252b | 8670 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8671 | { Bad_Opcode }, |
592a252b L |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8674 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8675 | { Bad_Opcode }, |
c0f3af97 | 8676 | /* c8 */ |
592d1631 L |
8677 | { Bad_Opcode }, |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
c0f3af97 | 8685 | /* d0 */ |
592a252b L |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8694 | /* d8 */ |
592a252b L |
8695 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8696 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8703 | /* e0 */ |
592a252b L |
8704 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8705 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8712 | /* e8 */ |
592a252b L |
8713 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8719 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8721 | /* f0 */ |
592a252b L |
8722 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8723 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8724 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8726 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8728 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8730 | /* f8 */ |
592a252b L |
8731 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8732 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8738 | { Bad_Opcode }, |
c0f3af97 L |
8739 | }, |
8740 | /* VEX_0F38 */ | |
8741 | { | |
8742 | /* 00 */ | |
592a252b L |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8751 | /* 08 */ |
592a252b L |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8760 | /* 10 */ |
592d1631 L |
8761 | { Bad_Opcode }, |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
592a252b | 8764 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8765 | { Bad_Opcode }, |
8766 | { Bad_Opcode }, | |
6c30d220 | 8767 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8768 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8769 | /* 18 */ |
592a252b L |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8773 | { Bad_Opcode }, |
592a252b L |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8777 | { Bad_Opcode }, |
c0f3af97 | 8778 | /* 20 */ |
592a252b L |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8785 | { Bad_Opcode }, |
8786 | { Bad_Opcode }, | |
c0f3af97 | 8787 | /* 28 */ |
592a252b L |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8796 | /* 30 */ |
592a252b L |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8803 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8804 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8805 | /* 38 */ |
592a252b L |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8814 | /* 40 */ |
592a252b L |
8815 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8817 | { Bad_Opcode }, |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
6c30d220 L |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8823 | /* 48 */ |
592d1631 | 8824 | { Bad_Opcode }, |
260cd341 | 8825 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 8826 | { Bad_Opcode }, |
260cd341 | 8827 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
8828 | { Bad_Opcode }, |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
c0f3af97 | 8832 | /* 50 */ |
592d1631 L |
8833 | { Bad_Opcode }, |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
c0f3af97 | 8841 | /* 58 */ |
6c30d220 L |
8842 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 | 8845 | { Bad_Opcode }, |
260cd341 | 8846 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 8847 | { Bad_Opcode }, |
260cd341 | 8848 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 8849 | { Bad_Opcode }, |
c0f3af97 | 8850 | /* 60 */ |
592d1631 L |
8851 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
c0f3af97 | 8859 | /* 68 */ |
592d1631 L |
8860 | { Bad_Opcode }, |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
c0f3af97 | 8868 | /* 70 */ |
592d1631 L |
8869 | { Bad_Opcode }, |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
c0f3af97 | 8877 | /* 78 */ |
6c30d220 L |
8878 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8879 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8880 | { Bad_Opcode }, |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
c0f3af97 | 8886 | /* 80 */ |
592d1631 L |
8887 | { Bad_Opcode }, |
8888 | { Bad_Opcode }, | |
8889 | { Bad_Opcode }, | |
8890 | { Bad_Opcode }, | |
8891 | { Bad_Opcode }, | |
8892 | { Bad_Opcode }, | |
8893 | { Bad_Opcode }, | |
8894 | { Bad_Opcode }, | |
c0f3af97 | 8895 | /* 88 */ |
592d1631 L |
8896 | { Bad_Opcode }, |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
6c30d220 | 8900 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8901 | { Bad_Opcode }, |
6c30d220 | 8902 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8903 | { Bad_Opcode }, |
c0f3af97 | 8904 | /* 90 */ |
6c30d220 L |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8909 | { Bad_Opcode }, |
8910 | { Bad_Opcode }, | |
592a252b L |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8913 | /* 98 */ |
592a252b L |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8922 | /* a0 */ |
592d1631 L |
8923 | { Bad_Opcode }, |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
592a252b L |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8931 | /* a8 */ |
592a252b L |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8940 | /* b0 */ |
592d1631 L |
8941 | { Bad_Opcode }, |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
592a252b L |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8949 | /* b8 */ |
592a252b L |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8958 | /* c0 */ |
592d1631 L |
8959 | { Bad_Opcode }, |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
c0f3af97 | 8967 | /* c8 */ |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
48521003 | 8975 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8976 | /* d0 */ |
592d1631 L |
8977 | { Bad_Opcode }, |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
c0f3af97 | 8985 | /* d8 */ |
592d1631 L |
8986 | { Bad_Opcode }, |
8987 | { Bad_Opcode }, | |
8988 | { Bad_Opcode }, | |
592a252b L |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8994 | /* e0 */ |
592d1631 L |
8995 | { Bad_Opcode }, |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
c0f3af97 | 9003 | /* e8 */ |
592d1631 L |
9004 | { Bad_Opcode }, |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
c0f3af97 | 9012 | /* f0 */ |
592d1631 L |
9013 | { Bad_Opcode }, |
9014 | { Bad_Opcode }, | |
f12dc422 L |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9016 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9017 | { Bad_Opcode }, |
6c30d220 L |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9020 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9021 | /* f8 */ |
592d1631 L |
9022 | { Bad_Opcode }, |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
c0f3af97 L |
9030 | }, |
9031 | /* VEX_0F3A */ | |
9032 | { | |
9033 | /* 00 */ | |
6c30d220 L |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9037 | { Bad_Opcode }, |
592a252b L |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9039 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9041 | { Bad_Opcode }, |
c0f3af97 | 9042 | /* 08 */ |
592a252b L |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9049 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9051 | /* 10 */ |
592d1631 L |
9052 | { Bad_Opcode }, |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
592a252b L |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9060 | /* 18 */ |
592a252b L |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9063 | { Bad_Opcode }, |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
592a252b | 9066 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9067 | { Bad_Opcode }, |
9068 | { Bad_Opcode }, | |
c0f3af97 | 9069 | /* 20 */ |
592a252b L |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9073 | { Bad_Opcode }, |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
c0f3af97 | 9078 | /* 28 */ |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
c0f3af97 | 9087 | /* 30 */ |
43234a1e | 9088 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9089 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9090 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9092 | { Bad_Opcode }, |
9093 | { Bad_Opcode }, | |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
c0f3af97 | 9096 | /* 38 */ |
6c30d220 L |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9099 | { Bad_Opcode }, |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
c0f3af97 | 9105 | /* 40 */ |
592a252b L |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9109 | { Bad_Opcode }, |
592a252b | 9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9111 | { Bad_Opcode }, |
6c30d220 | 9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9113 | { Bad_Opcode }, |
c0f3af97 | 9114 | /* 48 */ |
592a252b L |
9115 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9116 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9117 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9118 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9119 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9120 | { Bad_Opcode }, |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
c0f3af97 | 9123 | /* 50 */ |
592d1631 L |
9124 | { Bad_Opcode }, |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
c0f3af97 | 9132 | /* 58 */ |
592d1631 L |
9133 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
592a252b L |
9137 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9141 | /* 60 */ |
592a252b L |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9143 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9144 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9145 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9146 | { Bad_Opcode }, |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
c0f3af97 | 9150 | /* 68 */ |
592a252b L |
9151 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9152 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9153 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9154 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9155 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9156 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9159 | /* 70 */ |
592d1631 L |
9160 | { Bad_Opcode }, |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
c0f3af97 | 9168 | /* 78 */ |
592a252b L |
9169 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9170 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9171 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9172 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9173 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9174 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9175 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9176 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9177 | /* 80 */ |
592d1631 L |
9178 | { Bad_Opcode }, |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
c0f3af97 | 9186 | /* 88 */ |
592d1631 L |
9187 | { Bad_Opcode }, |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
c0f3af97 | 9195 | /* 90 */ |
592d1631 L |
9196 | { Bad_Opcode }, |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
c0f3af97 | 9204 | /* 98 */ |
592d1631 L |
9205 | { Bad_Opcode }, |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
c0f3af97 | 9213 | /* a0 */ |
592d1631 L |
9214 | { Bad_Opcode }, |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
c0f3af97 | 9222 | /* a8 */ |
592d1631 L |
9223 | { Bad_Opcode }, |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
c0f3af97 | 9231 | /* b0 */ |
592d1631 L |
9232 | { Bad_Opcode }, |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
c0f3af97 | 9240 | /* b8 */ |
592d1631 L |
9241 | { Bad_Opcode }, |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
c0f3af97 | 9249 | /* c0 */ |
592d1631 L |
9250 | { Bad_Opcode }, |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
c0f3af97 | 9258 | /* c8 */ |
592d1631 L |
9259 | { Bad_Opcode }, |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
48521003 IT |
9265 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9266 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9267 | /* d0 */ |
592d1631 L |
9268 | { Bad_Opcode }, |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
c0f3af97 | 9276 | /* d8 */ |
592d1631 L |
9277 | { Bad_Opcode }, |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
9282 | { Bad_Opcode }, | |
9283 | { Bad_Opcode }, | |
592a252b | 9284 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9285 | /* e0 */ |
592d1631 L |
9286 | { Bad_Opcode }, |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
9291 | { Bad_Opcode }, | |
9292 | { Bad_Opcode }, | |
9293 | { Bad_Opcode }, | |
c0f3af97 | 9294 | /* e8 */ |
592d1631 L |
9295 | { Bad_Opcode }, |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
9299 | { Bad_Opcode }, | |
9300 | { Bad_Opcode }, | |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
c0f3af97 | 9303 | /* f0 */ |
6c30d220 | 9304 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9305 | { Bad_Opcode }, |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
9308 | { Bad_Opcode }, | |
9309 | { Bad_Opcode }, | |
9310 | { Bad_Opcode }, | |
9311 | { Bad_Opcode }, | |
c0f3af97 | 9312 | /* f8 */ |
592d1631 L |
9313 | { Bad_Opcode }, |
9314 | { Bad_Opcode }, | |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
9318 | { Bad_Opcode }, | |
9319 | { Bad_Opcode }, | |
9320 | { Bad_Opcode }, | |
c0f3af97 L |
9321 | }, |
9322 | }; | |
9323 | ||
43234a1e | 9324 | #include "i386-dis-evex.h" |
ad692897 | 9325 | |
c0f3af97 | 9326 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9327 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9328 | { |
89e65d17 | 9329 | { "vmovlpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
9330 | }, |
9331 | ||
592a252b | 9332 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9333 | { |
89e65d17 | 9334 | { "vmovhlps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
9335 | }, |
9336 | ||
592a252b | 9337 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9338 | { |
bf926894 | 9339 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9340 | }, |
9341 | ||
18897deb | 9342 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9343 | { |
89e65d17 | 9344 | { "vmovhpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
9345 | }, |
9346 | ||
592a252b | 9347 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9348 | { |
89e65d17 | 9349 | { "vmovlhps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
9350 | }, |
9351 | ||
592a252b | 9352 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9353 | { |
bf926894 | 9354 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9355 | }, |
9356 | ||
43234a1e L |
9357 | /* VEX_LEN_0F41_P_0 */ |
9358 | { | |
9359 | { Bad_Opcode }, | |
9360 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9361 | }, | |
1ba585e8 IT |
9362 | /* VEX_LEN_0F41_P_2 */ |
9363 | { | |
9364 | { Bad_Opcode }, | |
9365 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9366 | }, | |
43234a1e L |
9367 | /* VEX_LEN_0F42_P_0 */ |
9368 | { | |
9369 | { Bad_Opcode }, | |
9370 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9371 | }, | |
1ba585e8 IT |
9372 | /* VEX_LEN_0F42_P_2 */ |
9373 | { | |
9374 | { Bad_Opcode }, | |
9375 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9376 | }, | |
43234a1e L |
9377 | /* VEX_LEN_0F44_P_0 */ |
9378 | { | |
9379 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9380 | }, | |
1ba585e8 IT |
9381 | /* VEX_LEN_0F44_P_2 */ |
9382 | { | |
9383 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9384 | }, | |
43234a1e L |
9385 | /* VEX_LEN_0F45_P_0 */ |
9386 | { | |
9387 | { Bad_Opcode }, | |
9388 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9389 | }, | |
1ba585e8 IT |
9390 | /* VEX_LEN_0F45_P_2 */ |
9391 | { | |
9392 | { Bad_Opcode }, | |
9393 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9394 | }, | |
43234a1e L |
9395 | /* VEX_LEN_0F46_P_0 */ |
9396 | { | |
9397 | { Bad_Opcode }, | |
9398 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9399 | }, | |
1ba585e8 IT |
9400 | /* VEX_LEN_0F46_P_2 */ |
9401 | { | |
9402 | { Bad_Opcode }, | |
9403 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9404 | }, | |
43234a1e L |
9405 | /* VEX_LEN_0F47_P_0 */ |
9406 | { | |
9407 | { Bad_Opcode }, | |
9408 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9409 | }, | |
1ba585e8 IT |
9410 | /* VEX_LEN_0F47_P_2 */ |
9411 | { | |
9412 | { Bad_Opcode }, | |
9413 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9414 | }, | |
9415 | /* VEX_LEN_0F4A_P_0 */ | |
9416 | { | |
9417 | { Bad_Opcode }, | |
9418 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9419 | }, | |
9420 | /* VEX_LEN_0F4A_P_2 */ | |
9421 | { | |
9422 | { Bad_Opcode }, | |
9423 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9424 | }, | |
9425 | /* VEX_LEN_0F4B_P_0 */ | |
9426 | { | |
9427 | { Bad_Opcode }, | |
9428 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9429 | }, | |
43234a1e L |
9430 | /* VEX_LEN_0F4B_P_2 */ |
9431 | { | |
9432 | { Bad_Opcode }, | |
9433 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9434 | }, | |
9435 | ||
ec6f095a | 9436 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9437 | { |
ec6f095a | 9438 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9439 | }, |
9440 | ||
ec6f095a | 9441 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9442 | { |
ec6f095a L |
9443 | { "vzeroupper", { XX }, 0 }, |
9444 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9445 | }, |
9446 | ||
ec6f095a | 9447 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9448 | { |
5b872f7d | 9449 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9450 | }, |
9451 | ||
ec6f095a | 9452 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9453 | { |
ec6f095a | 9454 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9455 | }, |
9456 | ||
ec6f095a | 9457 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9458 | { |
ec6f095a | 9459 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9460 | }, |
9461 | ||
ec6f095a | 9462 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9463 | { |
ec6f095a | 9464 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9465 | }, |
9466 | ||
ec6f095a | 9467 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9468 | { |
ec6f095a | 9469 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9470 | }, |
9471 | ||
ec6f095a | 9472 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9473 | { |
ec6f095a | 9474 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9475 | }, |
9476 | ||
ec6f095a | 9477 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9478 | { |
ec6f095a | 9479 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9480 | }, |
9481 | ||
ec6f095a | 9482 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9483 | { |
ec6f095a | 9484 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9485 | }, |
9486 | ||
ec6f095a | 9487 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9488 | { |
58a211d2 | 9489 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9490 | }, |
9491 | ||
ec6f095a | 9492 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9493 | { |
ec6f095a | 9494 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9495 | }, |
9496 | ||
ec6f095a | 9497 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9498 | { |
ec6f095a | 9499 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9500 | }, |
9501 | ||
ec6f095a | 9502 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9503 | { |
58a211d2 | 9504 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9505 | }, |
9506 | ||
ec6f095a | 9507 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9508 | { |
9509 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9510 | }, | |
9511 | ||
1ba585e8 IT |
9512 | /* VEX_LEN_0F98_P_2 */ |
9513 | { | |
9514 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9515 | }, | |
9516 | ||
9517 | /* VEX_LEN_0F99_P_0 */ | |
9518 | { | |
9519 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9520 | }, | |
9521 | ||
9522 | /* VEX_LEN_0F99_P_2 */ | |
9523 | { | |
9524 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9525 | }, | |
9526 | ||
6c30d220 | 9527 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9528 | { |
ec6f095a | 9529 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9530 | }, |
9531 | ||
6c30d220 | 9532 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9533 | { |
ec6f095a | 9534 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9535 | }, |
9536 | ||
6c30d220 | 9537 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9538 | { |
89e65d17 | 9539 | { "vpinsrw", { XM, Vex, Edqw, Ib }, 0 }, |
c0f3af97 L |
9540 | }, |
9541 | ||
6c30d220 | 9542 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9543 | { |
b50c9f31 | 9544 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9545 | }, |
9546 | ||
6c30d220 | 9547 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9548 | { |
41f5efc6 | 9549 | { "vmovq", { EXqS, XMScalar }, 0 }, |
c0f3af97 L |
9550 | }, |
9551 | ||
6c30d220 | 9552 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9553 | { |
ec6f095a | 9554 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9555 | }, |
9556 | ||
6c30d220 | 9557 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9558 | { |
6c30d220 L |
9559 | { Bad_Opcode }, |
9560 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9561 | }, |
9562 | ||
6c30d220 | 9563 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9564 | { |
6c30d220 L |
9565 | { Bad_Opcode }, |
9566 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9567 | }, |
9568 | ||
6c30d220 | 9569 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9570 | { |
6c30d220 | 9571 | { Bad_Opcode }, |
89e65d17 | 9572 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0) }, |
c0f3af97 L |
9573 | }, |
9574 | ||
6c30d220 | 9575 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9576 | { |
6c30d220 L |
9577 | { Bad_Opcode }, |
9578 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9579 | }, |
9580 | ||
592a252b | 9581 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9582 | { |
ec6f095a | 9583 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9584 | }, |
9585 | ||
260cd341 LC |
9586 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
9587 | { | |
9588 | { "ldtilecfg", { M }, 0 }, | |
9589 | }, | |
9590 | ||
9591 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
9592 | { | |
9593 | { "tilerelease", { Skip_MODRM }, 0 }, | |
9594 | }, | |
9595 | ||
9596 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
9597 | { | |
9598 | { "sttilecfg", { M }, 0 }, | |
9599 | }, | |
9600 | ||
9601 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
9602 | { | |
9603 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
9604 | }, | |
9605 | ||
9606 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
9607 | { | |
9608 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
9609 | }, | |
9610 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
9611 | { | |
9612 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
9613 | }, | |
9614 | ||
9615 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
9616 | { | |
9617 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
9618 | }, | |
9619 | ||
6c30d220 L |
9620 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9621 | { | |
9622 | { Bad_Opcode }, | |
89e65d17 | 9623 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0) }, |
6c30d220 L |
9624 | }, |
9625 | ||
260cd341 LC |
9626 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
9627 | { | |
9628 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
9629 | }, | |
9630 | ||
9631 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
9632 | { | |
9633 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
9634 | }, | |
9635 | ||
9636 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
9637 | { | |
9638 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
9639 | }, | |
9640 | ||
9641 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
9642 | { | |
9643 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
9644 | }, | |
9645 | ||
9646 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
9647 | { | |
9648 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
9649 | }, | |
9650 | ||
592a252b | 9651 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9652 | { |
ec6f095a | 9653 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9654 | }, |
9655 | ||
f12dc422 L |
9656 | /* VEX_LEN_0F38F2_P_0 */ |
9657 | { | |
bf890a93 | 9658 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9659 | }, |
9660 | ||
9661 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9662 | { | |
bf890a93 | 9663 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9664 | }, |
9665 | ||
9666 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9667 | { | |
bf890a93 | 9668 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9669 | }, |
9670 | ||
9671 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9672 | { | |
bf890a93 | 9673 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9674 | }, |
9675 | ||
6c30d220 L |
9676 | /* VEX_LEN_0F38F5_P_0 */ |
9677 | { | |
bf890a93 | 9678 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9679 | }, |
9680 | ||
9681 | /* VEX_LEN_0F38F5_P_1 */ | |
9682 | { | |
bf890a93 | 9683 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9684 | }, |
9685 | ||
9686 | /* VEX_LEN_0F38F5_P_3 */ | |
9687 | { | |
bf890a93 | 9688 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9689 | }, |
9690 | ||
9691 | /* VEX_LEN_0F38F6_P_3 */ | |
9692 | { | |
bf890a93 | 9693 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9694 | }, |
9695 | ||
f12dc422 L |
9696 | /* VEX_LEN_0F38F7_P_0 */ |
9697 | { | |
bf890a93 | 9698 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9699 | }, |
9700 | ||
6c30d220 L |
9701 | /* VEX_LEN_0F38F7_P_1 */ |
9702 | { | |
bf890a93 | 9703 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9704 | }, |
9705 | ||
9706 | /* VEX_LEN_0F38F7_P_2 */ | |
9707 | { | |
bf890a93 | 9708 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9709 | }, |
9710 | ||
9711 | /* VEX_LEN_0F38F7_P_3 */ | |
9712 | { | |
bf890a93 | 9713 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9714 | }, |
9715 | ||
9716 | /* VEX_LEN_0F3A00_P_2 */ | |
9717 | { | |
9718 | { Bad_Opcode }, | |
9719 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9720 | }, | |
9721 | ||
9722 | /* VEX_LEN_0F3A01_P_2 */ | |
9723 | { | |
9724 | { Bad_Opcode }, | |
9725 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9726 | }, | |
9727 | ||
592a252b | 9728 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9729 | { |
592d1631 | 9730 | { Bad_Opcode }, |
89e65d17 | 9731 | { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0) }, |
c0f3af97 L |
9732 | }, |
9733 | ||
592a252b | 9734 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9735 | { |
b50c9f31 | 9736 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9737 | }, |
9738 | ||
592a252b | 9739 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9740 | { |
b50c9f31 | 9741 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9742 | }, |
9743 | ||
592a252b | 9744 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9745 | { |
bf890a93 | 9746 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9747 | }, |
9748 | ||
592a252b | 9749 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9750 | { |
bf890a93 | 9751 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9752 | }, |
9753 | ||
592a252b | 9754 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9755 | { |
592d1631 | 9756 | { Bad_Opcode }, |
89e65d17 | 9757 | { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0) }, |
c0f3af97 L |
9758 | }, |
9759 | ||
592a252b | 9760 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9761 | { |
592d1631 | 9762 | { Bad_Opcode }, |
89e65d17 | 9763 | { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0) }, |
c0f3af97 L |
9764 | }, |
9765 | ||
592a252b | 9766 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9767 | { |
89e65d17 | 9768 | { "vpinsrb", { XM, Vex, Edqb, Ib }, 0 }, |
c0f3af97 L |
9769 | }, |
9770 | ||
592a252b | 9771 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9772 | { |
89e65d17 | 9773 | { "vinsertps", { XM, Vex, EXd, Ib }, 0 }, |
c0f3af97 L |
9774 | }, |
9775 | ||
592a252b | 9776 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9777 | { |
89e65d17 | 9778 | { "vpinsrK", { XM, Vex, Edq, Ib }, 0 }, |
c0f3af97 L |
9779 | }, |
9780 | ||
43234a1e L |
9781 | /* VEX_LEN_0F3A30_P_2 */ |
9782 | { | |
9783 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9784 | }, | |
9785 | ||
1ba585e8 IT |
9786 | /* VEX_LEN_0F3A31_P_2 */ |
9787 | { | |
9788 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9789 | }, | |
9790 | ||
43234a1e L |
9791 | /* VEX_LEN_0F3A32_P_2 */ |
9792 | { | |
9793 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9794 | }, | |
9795 | ||
1ba585e8 IT |
9796 | /* VEX_LEN_0F3A33_P_2 */ |
9797 | { | |
9798 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9799 | }, | |
9800 | ||
6c30d220 | 9801 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9802 | { |
6c30d220 | 9803 | { Bad_Opcode }, |
89e65d17 | 9804 | { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0) }, |
c0f3af97 L |
9805 | }, |
9806 | ||
6c30d220 | 9807 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9808 | { |
6c30d220 | 9809 | { Bad_Opcode }, |
89e65d17 | 9810 | { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0) }, |
6c30d220 L |
9811 | }, |
9812 | ||
9813 | /* VEX_LEN_0F3A41_P_2 */ | |
9814 | { | |
89e65d17 | 9815 | { "vdppd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
9816 | }, |
9817 | ||
6c30d220 | 9818 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9819 | { |
6c30d220 | 9820 | { Bad_Opcode }, |
89e65d17 | 9821 | { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0) }, |
c0f3af97 L |
9822 | }, |
9823 | ||
592a252b | 9824 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9825 | { |
b24d668c | 9826 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9827 | }, |
9828 | ||
592a252b | 9829 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9830 | { |
b24d668c | 9831 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9832 | }, |
9833 | ||
592a252b | 9834 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9835 | { |
ec6f095a | 9836 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9837 | }, |
9838 | ||
592a252b | 9839 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9840 | { |
ec6f095a | 9841 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9842 | }, |
9843 | ||
592a252b | 9844 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9845 | { |
ec6f095a | 9846 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9847 | }, |
4c807e72 | 9848 | |
6c30d220 L |
9849 | /* VEX_LEN_0F3AF0_P_3 */ |
9850 | { | |
bf890a93 | 9851 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9852 | }, |
9853 | ||
467bbef0 JB |
9854 | /* VEX_LEN_0FXOP_08_85 */ |
9855 | { | |
9856 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
9857 | }, | |
9858 | ||
9859 | /* VEX_LEN_0FXOP_08_86 */ | |
9860 | { | |
9861 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
9862 | }, | |
9863 | ||
9864 | /* VEX_LEN_0FXOP_08_87 */ | |
9865 | { | |
9866 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
9867 | }, | |
9868 | ||
9869 | /* VEX_LEN_0FXOP_08_8E */ | |
9870 | { | |
9871 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
9872 | }, | |
9873 | ||
9874 | /* VEX_LEN_0FXOP_08_8F */ | |
9875 | { | |
9876 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
9877 | }, | |
9878 | ||
9879 | /* VEX_LEN_0FXOP_08_95 */ | |
9880 | { | |
9881 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
9882 | }, | |
9883 | ||
9884 | /* VEX_LEN_0FXOP_08_96 */ | |
9885 | { | |
9886 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
9887 | }, | |
9888 | ||
9889 | /* VEX_LEN_0FXOP_08_97 */ | |
9890 | { | |
9891 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
9892 | }, | |
9893 | ||
9894 | /* VEX_LEN_0FXOP_08_9E */ | |
9895 | { | |
9896 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
9897 | }, | |
9898 | ||
9899 | /* VEX_LEN_0FXOP_08_9F */ | |
9900 | { | |
9901 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
9902 | }, | |
9903 | ||
9904 | /* VEX_LEN_0FXOP_08_A3 */ | |
9905 | { | |
9906 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
9907 | }, | |
9908 | ||
9909 | /* VEX_LEN_0FXOP_08_A6 */ | |
9910 | { | |
9911 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
9912 | }, | |
9913 | ||
9914 | /* VEX_LEN_0FXOP_08_B6 */ | |
9915 | { | |
9916 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
9917 | }, | |
9918 | ||
9919 | /* VEX_LEN_0FXOP_08_C0 */ | |
9920 | { | |
9921 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
9922 | }, | |
9923 | ||
9924 | /* VEX_LEN_0FXOP_08_C1 */ | |
9925 | { | |
9926 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
9927 | }, | |
9928 | ||
9929 | /* VEX_LEN_0FXOP_08_C2 */ | |
9930 | { | |
9931 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
9932 | }, | |
9933 | ||
9934 | /* VEX_LEN_0FXOP_08_C3 */ | |
9935 | { | |
9936 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
9937 | }, | |
9938 | ||
ff688e1f L |
9939 | /* VEX_LEN_0FXOP_08_CC */ |
9940 | { | |
467bbef0 | 9941 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
9942 | }, |
9943 | ||
9944 | /* VEX_LEN_0FXOP_08_CD */ | |
9945 | { | |
467bbef0 | 9946 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
9947 | }, |
9948 | ||
9949 | /* VEX_LEN_0FXOP_08_CE */ | |
9950 | { | |
467bbef0 | 9951 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
9952 | }, |
9953 | ||
9954 | /* VEX_LEN_0FXOP_08_CF */ | |
9955 | { | |
467bbef0 | 9956 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
9957 | }, |
9958 | ||
9959 | /* VEX_LEN_0FXOP_08_EC */ | |
9960 | { | |
467bbef0 | 9961 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
9962 | }, |
9963 | ||
9964 | /* VEX_LEN_0FXOP_08_ED */ | |
9965 | { | |
467bbef0 | 9966 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
9967 | }, |
9968 | ||
9969 | /* VEX_LEN_0FXOP_08_EE */ | |
9970 | { | |
467bbef0 | 9971 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
9972 | }, |
9973 | ||
9974 | /* VEX_LEN_0FXOP_08_EF */ | |
9975 | { | |
467bbef0 JB |
9976 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
9977 | }, | |
9978 | ||
9979 | /* VEX_LEN_0FXOP_09_01 */ | |
9980 | { | |
9981 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
9982 | }, | |
9983 | ||
9984 | /* VEX_LEN_0FXOP_09_02 */ | |
9985 | { | |
9986 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
9987 | }, | |
9988 | ||
9989 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
9990 | { | |
9991 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
9992 | }, |
9993 | ||
b5b098c2 | 9994 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 9995 | { |
b5b098c2 | 9996 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 9997 | }, |
4c807e72 | 9998 | |
b5b098c2 | 9999 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 10000 | { |
b5b098c2 | 10001 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 10002 | }, |
467bbef0 JB |
10003 | |
10004 | /* VEX_LEN_0FXOP_09_90 */ | |
10005 | { | |
10006 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
10007 | }, | |
10008 | ||
10009 | /* VEX_LEN_0FXOP_09_91 */ | |
10010 | { | |
10011 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
10012 | }, | |
10013 | ||
10014 | /* VEX_LEN_0FXOP_09_92 */ | |
10015 | { | |
10016 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
10017 | }, | |
10018 | ||
10019 | /* VEX_LEN_0FXOP_09_93 */ | |
10020 | { | |
10021 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
10022 | }, | |
10023 | ||
10024 | /* VEX_LEN_0FXOP_09_94 */ | |
10025 | { | |
10026 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
10027 | }, | |
10028 | ||
10029 | /* VEX_LEN_0FXOP_09_95 */ | |
10030 | { | |
10031 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
10032 | }, | |
10033 | ||
10034 | /* VEX_LEN_0FXOP_09_96 */ | |
10035 | { | |
10036 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
10037 | }, | |
10038 | ||
10039 | /* VEX_LEN_0FXOP_09_97 */ | |
10040 | { | |
10041 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
10042 | }, | |
10043 | ||
10044 | /* VEX_LEN_0FXOP_09_98 */ | |
10045 | { | |
10046 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
10047 | }, | |
10048 | ||
10049 | /* VEX_LEN_0FXOP_09_99 */ | |
10050 | { | |
10051 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
10052 | }, | |
10053 | ||
10054 | /* VEX_LEN_0FXOP_09_9A */ | |
10055 | { | |
10056 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
10057 | }, | |
10058 | ||
10059 | /* VEX_LEN_0FXOP_09_9B */ | |
10060 | { | |
10061 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
10062 | }, | |
10063 | ||
10064 | /* VEX_LEN_0FXOP_09_C1 */ | |
10065 | { | |
10066 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
10067 | }, | |
10068 | ||
10069 | /* VEX_LEN_0FXOP_09_C2 */ | |
10070 | { | |
10071 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
10072 | }, | |
10073 | ||
10074 | /* VEX_LEN_0FXOP_09_C3 */ | |
10075 | { | |
10076 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
10077 | }, | |
10078 | ||
10079 | /* VEX_LEN_0FXOP_09_C6 */ | |
10080 | { | |
10081 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
10082 | }, | |
10083 | ||
10084 | /* VEX_LEN_0FXOP_09_C7 */ | |
10085 | { | |
10086 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
10087 | }, | |
10088 | ||
10089 | /* VEX_LEN_0FXOP_09_CB */ | |
10090 | { | |
10091 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
10092 | }, | |
10093 | ||
10094 | /* VEX_LEN_0FXOP_09_D1 */ | |
10095 | { | |
10096 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
10097 | }, | |
10098 | ||
10099 | /* VEX_LEN_0FXOP_09_D2 */ | |
10100 | { | |
10101 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
10102 | }, | |
10103 | ||
10104 | /* VEX_LEN_0FXOP_09_D3 */ | |
10105 | { | |
10106 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
10107 | }, | |
10108 | ||
10109 | /* VEX_LEN_0FXOP_09_D6 */ | |
10110 | { | |
10111 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
10112 | }, | |
10113 | ||
10114 | /* VEX_LEN_0FXOP_09_D7 */ | |
10115 | { | |
10116 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
10117 | }, | |
10118 | ||
10119 | /* VEX_LEN_0FXOP_09_DB */ | |
10120 | { | |
10121 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
10122 | }, | |
10123 | ||
10124 | /* VEX_LEN_0FXOP_09_E1 */ | |
10125 | { | |
10126 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
10127 | }, | |
10128 | ||
10129 | /* VEX_LEN_0FXOP_09_E2 */ | |
10130 | { | |
10131 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
10132 | }, | |
10133 | ||
10134 | /* VEX_LEN_0FXOP_09_E3 */ | |
10135 | { | |
10136 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
10137 | }, | |
10138 | ||
10139 | /* VEX_LEN_0FXOP_0A_12 */ | |
10140 | { | |
10141 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
10142 | }, | |
331d2d0d L |
10143 | }; |
10144 | ||
ad692897 | 10145 | #include "i386-dis-evex-len.h" |
04e2a182 | 10146 | |
9e30b8e0 | 10147 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
10148 | { |
10149 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10150 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10151 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10152 | }, |
10153 | { | |
10154 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10155 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10156 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10157 | }, |
10158 | { | |
10159 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10160 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10161 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10162 | }, |
10163 | { | |
10164 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10165 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10166 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10167 | }, |
10168 | { | |
10169 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10170 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10171 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10172 | }, |
10173 | { | |
10174 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10175 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10176 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10177 | }, |
10178 | { | |
ec6f095a L |
10179 | /* VEX_W_0F45_P_0_LEN_1 */ |
10180 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
10181 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
10182 | }, |
10183 | { | |
ec6f095a L |
10184 | /* VEX_W_0F45_P_2_LEN_1 */ |
10185 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
10186 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
10187 | }, |
10188 | { | |
ec6f095a L |
10189 | /* VEX_W_0F46_P_0_LEN_1 */ |
10190 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
10191 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
10192 | }, |
10193 | { | |
ec6f095a L |
10194 | /* VEX_W_0F46_P_2_LEN_1 */ |
10195 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
10196 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
10197 | }, |
10198 | { | |
ec6f095a L |
10199 | /* VEX_W_0F47_P_0_LEN_1 */ |
10200 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
10201 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
10202 | }, |
10203 | { | |
ec6f095a L |
10204 | /* VEX_W_0F47_P_2_LEN_1 */ |
10205 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
10206 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
10207 | }, |
10208 | { | |
ec6f095a L |
10209 | /* VEX_W_0F4A_P_0_LEN_1 */ |
10210 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
10211 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
10212 | }, |
10213 | { | |
ec6f095a L |
10214 | /* VEX_W_0F4A_P_2_LEN_1 */ |
10215 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
10216 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
10217 | }, |
10218 | { | |
ec6f095a L |
10219 | /* VEX_W_0F4B_P_0_LEN_1 */ |
10220 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
10221 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
10222 | }, |
10223 | { | |
ec6f095a L |
10224 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10225 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
10226 | }, |
10227 | { | |
ec6f095a L |
10228 | /* VEX_W_0F90_P_0_LEN_0 */ |
10229 | { "kmovw", { MaskG, MaskE }, 0 }, | |
10230 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
10231 | }, |
10232 | { | |
ec6f095a L |
10233 | /* VEX_W_0F90_P_2_LEN_0 */ |
10234 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
10235 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
10236 | }, |
10237 | { | |
ec6f095a L |
10238 | /* VEX_W_0F91_P_0_LEN_0 */ |
10239 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
10240 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
10241 | }, |
10242 | { | |
ec6f095a L |
10243 | /* VEX_W_0F91_P_2_LEN_0 */ |
10244 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
10245 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
10246 | }, |
10247 | { | |
ec6f095a L |
10248 | /* VEX_W_0F92_P_0_LEN_0 */ |
10249 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
10250 | }, |
10251 | { | |
ec6f095a L |
10252 | /* VEX_W_0F92_P_2_LEN_0 */ |
10253 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 10254 | }, |
9e30b8e0 | 10255 | { |
ec6f095a L |
10256 | /* VEX_W_0F93_P_0_LEN_0 */ |
10257 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
10258 | }, |
10259 | { | |
ec6f095a L |
10260 | /* VEX_W_0F93_P_2_LEN_0 */ |
10261 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10262 | }, |
9e30b8e0 | 10263 | { |
ec6f095a L |
10264 | /* VEX_W_0F98_P_0_LEN_0 */ |
10265 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10266 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10267 | }, |
10268 | { | |
ec6f095a L |
10269 | /* VEX_W_0F98_P_2_LEN_0 */ |
10270 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10271 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10272 | }, |
10273 | { | |
ec6f095a L |
10274 | /* VEX_W_0F99_P_0_LEN_0 */ |
10275 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10276 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10277 | }, |
10278 | { | |
ec6f095a L |
10279 | /* VEX_W_0F99_P_2_LEN_0 */ |
10280 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10281 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10282 | }, |
9e30b8e0 | 10283 | { |
592a252b | 10284 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10285 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10286 | }, |
10287 | { | |
592a252b | 10288 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10289 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10290 | }, |
10291 | { | |
592a252b | 10292 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10293 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10294 | }, |
10295 | { | |
592a252b | 10296 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10297 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10298 | }, |
6431c801 JB |
10299 | { |
10300 | /* VEX_W_0F3813_P_2 */ | |
10301 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
10302 | }, | |
6c30d220 L |
10303 | { |
10304 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10305 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10306 | }, |
bcf2684f | 10307 | { |
6c30d220 | 10308 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10309 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10310 | }, |
9e30b8e0 | 10311 | { |
6c30d220 | 10312 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10313 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10314 | }, |
10315 | { | |
89e65d17 | 10316 | /* VEX_W_0F381A_P_2_M_0_L_0 */ |
bf890a93 | 10317 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10318 | }, |
53aa04a0 | 10319 | { |
592a252b | 10320 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10321 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10322 | }, |
10323 | { | |
592a252b | 10324 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10325 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10326 | }, |
10327 | { | |
592a252b | 10328 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10329 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10330 | }, |
10331 | { | |
592a252b | 10332 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10333 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10334 | }, |
6c30d220 L |
10335 | { |
10336 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10337 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10338 | }, |
6c30d220 L |
10339 | { |
10340 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10341 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10342 | }, |
260cd341 LC |
10343 | { |
10344 | /* VEX_W_0F3849_X86_64_P_0 */ | |
10345 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
10346 | }, | |
10347 | { | |
10348 | /* VEX_W_0F3849_X86_64_P_2 */ | |
10349 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
10350 | }, | |
10351 | { | |
10352 | /* VEX_W_0F3849_X86_64_P_3 */ | |
10353 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
10354 | }, | |
10355 | { | |
10356 | /* VEX_W_0F384B_X86_64_P_1 */ | |
10357 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
10358 | }, | |
10359 | { | |
10360 | /* VEX_W_0F384B_X86_64_P_2 */ | |
10361 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
10362 | }, | |
10363 | { | |
10364 | /* VEX_W_0F384B_X86_64_P_3 */ | |
10365 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
10366 | }, | |
6c30d220 L |
10367 | { |
10368 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10369 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10370 | }, |
10371 | { | |
10372 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10373 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10374 | }, |
10375 | { | |
89e65d17 | 10376 | /* VEX_W_0F385A_P_2_M_0_L_0 */ |
bf890a93 | 10377 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 | 10378 | }, |
260cd341 LC |
10379 | { |
10380 | /* VEX_W_0F385C_X86_64_P_1 */ | |
10381 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
10382 | }, | |
10383 | { | |
10384 | /* VEX_W_0F385E_X86_64_P_0 */ | |
10385 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
10386 | }, | |
10387 | { | |
10388 | /* VEX_W_0F385E_X86_64_P_1 */ | |
10389 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
10390 | }, | |
10391 | { | |
10392 | /* VEX_W_0F385E_X86_64_P_2 */ | |
10393 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
10394 | }, | |
10395 | { | |
10396 | /* VEX_W_0F385E_X86_64_P_3 */ | |
10397 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
10398 | }, | |
6c30d220 L |
10399 | { |
10400 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10401 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10402 | }, |
10403 | { | |
10404 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10405 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10406 | }, |
48521003 IT |
10407 | { |
10408 | /* VEX_W_0F38CF_P_2 */ | |
10409 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10410 | }, | |
6c30d220 L |
10411 | { |
10412 | /* VEX_W_0F3A00_P_2 */ | |
10413 | { Bad_Opcode }, | |
bf890a93 | 10414 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10415 | }, |
10416 | { | |
10417 | /* VEX_W_0F3A01_P_2 */ | |
10418 | { Bad_Opcode }, | |
bf890a93 | 10419 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10420 | }, |
10421 | { | |
10422 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10423 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10424 | }, |
9e30b8e0 | 10425 | { |
592a252b | 10426 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10427 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10428 | }, |
10429 | { | |
592a252b | 10430 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10431 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10432 | }, |
10433 | { | |
89e65d17 JB |
10434 | /* VEX_W_0F3A06_P_2_L_0 */ |
10435 | { "vperm2f128", { XM, Vex, EXx, Ib }, 0 }, | |
9e30b8e0 | 10436 | }, |
9e30b8e0 | 10437 | { |
89e65d17 JB |
10438 | /* VEX_W_0F3A18_P_2_L_0 */ |
10439 | { "vinsertf128", { XM, Vex, EXxmm, Ib }, 0 }, | |
9e30b8e0 L |
10440 | }, |
10441 | { | |
89e65d17 | 10442 | /* VEX_W_0F3A19_P_2_L_0 */ |
bf890a93 | 10443 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10444 | }, |
6431c801 JB |
10445 | { |
10446 | /* VEX_W_0F3A1D_P_2 */ | |
10447 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10448 | }, | |
43234a1e | 10449 | { |
1ba585e8 | 10450 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10451 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10452 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10453 | }, |
10454 | { | |
1ba585e8 | 10455 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10456 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10457 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10458 | }, |
10459 | { | |
10460 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10461 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10462 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10463 | }, |
1ba585e8 IT |
10464 | { |
10465 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10466 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10467 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10468 | }, |
6c30d220 | 10469 | { |
89e65d17 JB |
10470 | /* VEX_W_0F3A38_P_2_L_0 */ |
10471 | { "vinserti128", { XM, Vex, EXxmm, Ib }, 0 }, | |
6c30d220 L |
10472 | }, |
10473 | { | |
89e65d17 | 10474 | /* VEX_W_0F3A39_P_2_L_0 */ |
bf890a93 | 10475 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10476 | }, |
6c30d220 | 10477 | { |
89e65d17 JB |
10478 | /* VEX_W_0F3A46_P_2_L_0 */ |
10479 | { "vperm2i128", { XM, Vex, EXx, Ib }, 0 }, | |
6c30d220 | 10480 | }, |
9e30b8e0 | 10481 | { |
592a252b | 10482 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10483 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10484 | }, |
10485 | { | |
592a252b | 10486 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10487 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10488 | }, |
10489 | { | |
592a252b | 10490 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10491 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10492 | }, |
48521003 IT |
10493 | { |
10494 | /* VEX_W_0F3ACE_P_2 */ | |
10495 | { Bad_Opcode }, | |
10496 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10497 | }, | |
10498 | { | |
10499 | /* VEX_W_0F3ACF_P_2 */ | |
10500 | { Bad_Opcode }, | |
10501 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10502 | }, | |
467bbef0 JB |
10503 | /* VEX_W_0FXOP_08_85_L_0 */ |
10504 | { | |
10505 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10506 | }, | |
10507 | /* VEX_W_0FXOP_08_86_L_0 */ | |
10508 | { | |
10509 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10510 | }, | |
10511 | /* VEX_W_0FXOP_08_87_L_0 */ | |
10512 | { | |
10513 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10514 | }, | |
10515 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
10516 | { | |
10517 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10518 | }, | |
10519 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
10520 | { | |
10521 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10522 | }, | |
10523 | /* VEX_W_0FXOP_08_95_L_0 */ | |
10524 | { | |
10525 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10526 | }, | |
10527 | /* VEX_W_0FXOP_08_96_L_0 */ | |
10528 | { | |
10529 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10530 | }, | |
10531 | /* VEX_W_0FXOP_08_97_L_0 */ | |
10532 | { | |
10533 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10534 | }, | |
10535 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
10536 | { | |
10537 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10538 | }, | |
10539 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
10540 | { | |
10541 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10542 | }, | |
10543 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
10544 | { | |
10545 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10546 | }, | |
10547 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
10548 | { | |
10549 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10550 | }, | |
10551 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
10552 | { | |
10553 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
10554 | }, | |
10555 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
10556 | { | |
10557 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
10558 | }, | |
10559 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
10560 | { | |
10561 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
10562 | }, | |
10563 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
10564 | { | |
10565 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
10566 | }, | |
10567 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
10568 | { | |
89e65d17 | 10569 | { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10570 | }, |
10571 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
10572 | { | |
89e65d17 | 10573 | { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10574 | }, |
10575 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
10576 | { | |
89e65d17 | 10577 | { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10578 | }, |
10579 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
10580 | { | |
89e65d17 | 10581 | { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10582 | }, |
10583 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
10584 | { | |
89e65d17 | 10585 | { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10586 | }, |
10587 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
10588 | { | |
89e65d17 | 10589 | { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10590 | }, |
10591 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
10592 | { | |
89e65d17 | 10593 | { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
10594 | }, |
10595 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
10596 | { | |
89e65d17 | 10597 | { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 10598 | }, |
b5b098c2 JB |
10599 | /* VEX_W_0FXOP_09_80 */ |
10600 | { | |
10601 | { "vfrczps", { XM, EXx }, 0 }, | |
10602 | }, | |
10603 | /* VEX_W_0FXOP_09_81 */ | |
10604 | { | |
10605 | { "vfrczpd", { XM, EXx }, 0 }, | |
10606 | }, | |
10607 | /* VEX_W_0FXOP_09_82 */ | |
10608 | { | |
10609 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
10610 | }, | |
10611 | /* VEX_W_0FXOP_09_83 */ | |
10612 | { | |
10613 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
10614 | }, | |
467bbef0 JB |
10615 | /* VEX_W_0FXOP_09_C1_L_0 */ |
10616 | { | |
10617 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
10618 | }, | |
10619 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
10620 | { | |
10621 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
10622 | }, | |
10623 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
10624 | { | |
10625 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
10626 | }, | |
10627 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
10628 | { | |
10629 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
10630 | }, | |
10631 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
10632 | { | |
10633 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
10634 | }, | |
10635 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
10636 | { | |
10637 | { "vphadddq", { XM, EXxmm }, 0 }, | |
10638 | }, | |
10639 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
10640 | { | |
10641 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
10642 | }, | |
10643 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
10644 | { | |
10645 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
10646 | }, | |
10647 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
10648 | { | |
10649 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
10650 | }, | |
10651 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
10652 | { | |
10653 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
10654 | }, | |
10655 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
10656 | { | |
10657 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
10658 | }, | |
10659 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
10660 | { | |
10661 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
10662 | }, | |
10663 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
10664 | { | |
10665 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
10666 | }, | |
10667 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
10668 | { | |
10669 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
10670 | }, | |
10671 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
10672 | { | |
10673 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
10674 | }, | |
ad692897 L |
10675 | |
10676 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10677 | }; |
10678 | ||
10679 | static const struct dis386 mod_table[][2] = { | |
10680 | { | |
10681 | /* MOD_8D */ | |
bf890a93 | 10682 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10683 | }, |
42164a71 L |
10684 | { |
10685 | /* MOD_C6_REG_7 */ | |
10686 | { Bad_Opcode }, | |
10687 | { RM_TABLE (RM_C6_REG_7) }, | |
10688 | }, | |
10689 | { | |
10690 | /* MOD_C7_REG_7 */ | |
10691 | { Bad_Opcode }, | |
10692 | { RM_TABLE (RM_C7_REG_7) }, | |
10693 | }, | |
4a357820 MZ |
10694 | { |
10695 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10696 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10697 | }, |
10698 | { | |
10699 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10700 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10701 | }, |
9e30b8e0 L |
10702 | { |
10703 | /* MOD_0F01_REG_0 */ | |
10704 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10705 | { RM_TABLE (RM_0F01_REG_0) }, | |
10706 | }, | |
10707 | { | |
10708 | /* MOD_0F01_REG_1 */ | |
10709 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10710 | { RM_TABLE (RM_0F01_REG_1) }, | |
10711 | }, | |
10712 | { | |
10713 | /* MOD_0F01_REG_2 */ | |
10714 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10715 | { RM_TABLE (RM_0F01_REG_2) }, | |
10716 | }, | |
10717 | { | |
10718 | /* MOD_0F01_REG_3 */ | |
10719 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10720 | { RM_TABLE (RM_0F01_REG_3) }, | |
10721 | }, | |
8eab4136 L |
10722 | { |
10723 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10724 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10725 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10726 | }, |
9e30b8e0 L |
10727 | { |
10728 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10729 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10730 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10731 | }, |
10732 | { | |
10733 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10734 | { "movlpX", { XM, EXq }, 0 }, |
10735 | { "movhlps", { XM, EXq }, 0 }, | |
10736 | }, | |
10737 | { | |
10738 | /* MOD_0F12_PREFIX_2 */ | |
10739 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10740 | }, |
10741 | { | |
10742 | /* MOD_0F13 */ | |
507bd325 | 10743 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10744 | }, |
10745 | { | |
10746 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10747 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10748 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10749 | }, |
18897deb JB |
10750 | { |
10751 | /* MOD_0F16_PREFIX_2 */ | |
10752 | { "movhpX", { XM, EXq }, 0 }, | |
10753 | }, | |
9e30b8e0 L |
10754 | { |
10755 | /* MOD_0F17 */ | |
507bd325 | 10756 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10757 | }, |
10758 | { | |
10759 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10760 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10761 | }, |
10762 | { | |
10763 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10764 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10765 | }, |
10766 | { | |
10767 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10768 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10769 | }, |
10770 | { | |
10771 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10772 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10773 | }, |
d7189fa5 RM |
10774 | { |
10775 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10776 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10777 | }, |
10778 | { | |
10779 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10780 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10781 | }, |
10782 | { | |
10783 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10784 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10785 | }, |
10786 | { | |
10787 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10788 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10789 | }, |
7e8b059b L |
10790 | { |
10791 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10792 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10793 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10794 | }, |
10795 | { | |
10796 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10797 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10798 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10799 | }, |
10800 | { | |
10801 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10802 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10803 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10804 | }, |
c48935d7 IT |
10805 | { |
10806 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10807 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10808 | { "nopQ", { Ev }, 0 }, |
10809 | }, | |
603555e5 L |
10810 | { |
10811 | /* MOD_0F1E_PREFIX_1 */ | |
10812 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10813 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10814 | }, |
b844680a | 10815 | { |
92fddf8e | 10816 | /* MOD_0F24 */ |
7bb15c6f | 10817 | { Bad_Opcode }, |
bf890a93 | 10818 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10819 | }, |
10820 | { | |
92fddf8e | 10821 | /* MOD_0F26 */ |
592d1631 | 10822 | { Bad_Opcode }, |
bf890a93 | 10823 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10824 | }, |
75c135a8 L |
10825 | { |
10826 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10827 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10828 | }, |
10829 | { | |
10830 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10831 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10832 | }, |
10833 | { | |
10834 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10835 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10836 | }, |
10837 | { | |
10838 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10839 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10840 | }, |
10841 | { | |
a5aaedb9 | 10842 | /* MOD_0F50 */ |
592d1631 | 10843 | { Bad_Opcode }, |
507bd325 | 10844 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10845 | }, |
b844680a | 10846 | { |
1ceb70f8 | 10847 | /* MOD_0F71_REG_2 */ |
592d1631 | 10848 | { Bad_Opcode }, |
bf890a93 | 10849 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10850 | }, |
10851 | { | |
1ceb70f8 | 10852 | /* MOD_0F71_REG_4 */ |
592d1631 | 10853 | { Bad_Opcode }, |
bf890a93 | 10854 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10855 | }, |
10856 | { | |
1ceb70f8 | 10857 | /* MOD_0F71_REG_6 */ |
592d1631 | 10858 | { Bad_Opcode }, |
bf890a93 | 10859 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10860 | }, |
10861 | { | |
1ceb70f8 | 10862 | /* MOD_0F72_REG_2 */ |
592d1631 | 10863 | { Bad_Opcode }, |
bf890a93 | 10864 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10865 | }, |
10866 | { | |
1ceb70f8 | 10867 | /* MOD_0F72_REG_4 */ |
592d1631 | 10868 | { Bad_Opcode }, |
bf890a93 | 10869 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10870 | }, |
10871 | { | |
1ceb70f8 | 10872 | /* MOD_0F72_REG_6 */ |
592d1631 | 10873 | { Bad_Opcode }, |
bf890a93 | 10874 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10875 | }, |
10876 | { | |
1ceb70f8 | 10877 | /* MOD_0F73_REG_2 */ |
592d1631 | 10878 | { Bad_Opcode }, |
bf890a93 | 10879 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10880 | }, |
10881 | { | |
1ceb70f8 | 10882 | /* MOD_0F73_REG_3 */ |
592d1631 | 10883 | { Bad_Opcode }, |
c0f3af97 L |
10884 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10885 | }, | |
10886 | { | |
10887 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10888 | { Bad_Opcode }, |
bf890a93 | 10889 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10890 | }, |
10891 | { | |
10892 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10893 | { Bad_Opcode }, |
c0f3af97 L |
10894 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10895 | }, | |
10896 | { | |
10897 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10898 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10899 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10900 | }, |
10901 | { | |
10902 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10903 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10904 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10905 | }, |
10906 | { | |
10907 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10908 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10909 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10910 | }, |
10911 | { | |
10912 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10913 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10914 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10915 | }, |
10916 | { | |
10917 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10918 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10919 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10920 | }, |
10921 | { | |
10922 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10923 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10924 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10925 | }, |
10926 | { | |
10927 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10928 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10929 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10930 | }, |
10931 | { | |
10932 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10933 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10934 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10935 | }, |
10936 | { | |
10937 | /* MOD_0FB2 */ | |
bf890a93 | 10938 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10939 | }, |
10940 | { | |
10941 | /* MOD_0FB4 */ | |
bf890a93 | 10942 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10943 | }, |
10944 | { | |
10945 | /* MOD_0FB5 */ | |
bf890a93 | 10946 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10947 | }, |
a8484f96 L |
10948 | { |
10949 | /* MOD_0FC3 */ | |
f8687e93 | 10950 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10951 | }, |
963f3586 IT |
10952 | { |
10953 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10954 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10955 | }, |
10956 | { | |
10957 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10958 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10959 | }, |
10960 | { | |
10961 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10962 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10963 | }, |
c0f3af97 L |
10964 | { |
10965 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10966 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10967 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10968 | }, |
10969 | { | |
10970 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10971 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10972 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10973 | }, |
10974 | { | |
10975 | /* MOD_0FD7 */ | |
592d1631 | 10976 | { Bad_Opcode }, |
bf890a93 | 10977 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10978 | }, |
10979 | { | |
10980 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10981 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10982 | }, |
10983 | { | |
10984 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10985 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10986 | }, |
10987 | { | |
10988 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10989 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10990 | }, |
260cd341 LC |
10991 | { |
10992 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
10993 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
10994 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
10995 | }, | |
10996 | { | |
10997 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
10998 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
10999 | }, | |
11000 | { | |
11001 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
11002 | { Bad_Opcode }, | |
11003 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
11004 | }, | |
11005 | { | |
11006 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
11007 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
11008 | }, | |
11009 | { | |
11010 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
11011 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
11012 | }, | |
11013 | { | |
11014 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
11015 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
11016 | }, | |
11017 | { | |
11018 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
11019 | { Bad_Opcode }, | |
11020 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
11021 | }, | |
11022 | { | |
11023 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
11024 | { Bad_Opcode }, | |
11025 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
11026 | }, | |
11027 | { | |
11028 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
11029 | { Bad_Opcode }, | |
11030 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
11031 | }, | |
11032 | { | |
11033 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
11034 | { Bad_Opcode }, | |
11035 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
11036 | }, | |
11037 | { | |
11038 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
11039 | { Bad_Opcode }, | |
11040 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
11041 | }, | |
603555e5 L |
11042 | { |
11043 | /* MOD_0F38F5_PREFIX_2 */ | |
11044 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11045 | }, | |
11046 | { | |
11047 | /* MOD_0F38F6_PREFIX_0 */ | |
11048 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11049 | }, | |
5d79adc4 L |
11050 | { |
11051 | /* MOD_0F38F8_PREFIX_1 */ | |
11052 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
11053 | }, | |
c0a30a9f L |
11054 | { |
11055 | /* MOD_0F38F8_PREFIX_2 */ | |
11056 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
11057 | }, | |
5d79adc4 L |
11058 | { |
11059 | /* MOD_0F38F8_PREFIX_3 */ | |
11060 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
11061 | }, | |
c0a30a9f L |
11062 | { |
11063 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 11064 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 11065 | }, |
c0f3af97 L |
11066 | { |
11067 | /* MOD_62_32BIT */ | |
bf890a93 | 11068 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11069 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11070 | }, |
11071 | { | |
11072 | /* MOD_C4_32BIT */ | |
bf890a93 | 11073 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11074 | { VEX_C4_TABLE (VEX_0F) }, |
11075 | }, | |
11076 | { | |
11077 | /* MOD_C5_32BIT */ | |
bf890a93 | 11078 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11079 | { VEX_C5_TABLE (VEX_0F) }, |
11080 | }, | |
11081 | { | |
592a252b L |
11082 | /* MOD_VEX_0F12_PREFIX_0 */ |
11083 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11084 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 11085 | }, |
18897deb JB |
11086 | { |
11087 | /* MOD_VEX_0F12_PREFIX_2 */ | |
11088 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
11089 | }, | |
c0f3af97 | 11090 | { |
592a252b L |
11091 | /* MOD_VEX_0F13 */ |
11092 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11093 | }, |
11094 | { | |
592a252b L |
11095 | /* MOD_VEX_0F16_PREFIX_0 */ |
11096 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11097 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 11098 | }, |
18897deb JB |
11099 | { |
11100 | /* MOD_VEX_0F16_PREFIX_2 */ | |
11101 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
11102 | }, | |
c0f3af97 | 11103 | { |
592a252b L |
11104 | /* MOD_VEX_0F17 */ |
11105 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11106 | }, |
11107 | { | |
592a252b | 11108 | /* MOD_VEX_0F2B */ |
bf926894 | 11109 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 11110 | }, |
ab4e4ed5 AF |
11111 | { |
11112 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11113 | { Bad_Opcode }, | |
11114 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11115 | }, | |
11116 | { | |
11117 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11118 | { Bad_Opcode }, | |
11119 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11120 | }, | |
11121 | { | |
11122 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11123 | { Bad_Opcode }, | |
11124 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11125 | }, | |
11126 | { | |
11127 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11128 | { Bad_Opcode }, | |
11129 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11130 | }, | |
11131 | { | |
11132 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11133 | { Bad_Opcode }, | |
11134 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11135 | }, | |
11136 | { | |
11137 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11138 | { Bad_Opcode }, | |
11139 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11140 | }, | |
11141 | { | |
11142 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11143 | { Bad_Opcode }, | |
11144 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11145 | }, | |
11146 | { | |
11147 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11148 | { Bad_Opcode }, | |
11149 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11150 | }, | |
11151 | { | |
11152 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11153 | { Bad_Opcode }, | |
11154 | { "knotw", { MaskG, MaskR }, 0 }, | |
11155 | }, | |
11156 | { | |
11157 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11158 | { Bad_Opcode }, | |
11159 | { "knotq", { MaskG, MaskR }, 0 }, | |
11160 | }, | |
11161 | { | |
11162 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11163 | { Bad_Opcode }, | |
11164 | { "knotb", { MaskG, MaskR }, 0 }, | |
11165 | }, | |
11166 | { | |
11167 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11168 | { Bad_Opcode }, | |
11169 | { "knotd", { MaskG, MaskR }, 0 }, | |
11170 | }, | |
11171 | { | |
11172 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11173 | { Bad_Opcode }, | |
11174 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11175 | }, | |
11176 | { | |
11177 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11178 | { Bad_Opcode }, | |
11179 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11180 | }, | |
11181 | { | |
11182 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11183 | { Bad_Opcode }, | |
11184 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11185 | }, | |
11186 | { | |
11187 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11188 | { Bad_Opcode }, | |
11189 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11190 | }, | |
11191 | { | |
11192 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11193 | { Bad_Opcode }, | |
11194 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11195 | }, | |
11196 | { | |
11197 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11198 | { Bad_Opcode }, | |
11199 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11200 | }, | |
11201 | { | |
11202 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11203 | { Bad_Opcode }, | |
11204 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11205 | }, | |
11206 | { | |
11207 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11208 | { Bad_Opcode }, | |
11209 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11210 | }, | |
11211 | { | |
11212 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11213 | { Bad_Opcode }, | |
11214 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11215 | }, | |
11216 | { | |
11217 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11218 | { Bad_Opcode }, | |
11219 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11220 | }, | |
11221 | { | |
11222 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11223 | { Bad_Opcode }, | |
11224 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11225 | }, | |
11226 | { | |
11227 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11228 | { Bad_Opcode }, | |
11229 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11230 | }, | |
11231 | { | |
11232 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11233 | { Bad_Opcode }, | |
11234 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11235 | }, | |
11236 | { | |
11237 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11238 | { Bad_Opcode }, | |
11239 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11240 | }, | |
11241 | { | |
11242 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11243 | { Bad_Opcode }, | |
11244 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11245 | }, | |
11246 | { | |
11247 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11248 | { Bad_Opcode }, | |
11249 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11250 | }, | |
11251 | { | |
11252 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11253 | { Bad_Opcode }, | |
11254 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11255 | }, | |
11256 | { | |
11257 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11258 | { Bad_Opcode }, | |
11259 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11260 | }, | |
11261 | { | |
11262 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11263 | { Bad_Opcode }, | |
11264 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11265 | }, | |
c0f3af97 | 11266 | { |
592a252b | 11267 | /* MOD_VEX_0F50 */ |
592d1631 | 11268 | { Bad_Opcode }, |
bf926894 | 11269 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
11270 | }, |
11271 | { | |
592a252b | 11272 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11273 | { Bad_Opcode }, |
592a252b | 11274 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11275 | }, |
11276 | { | |
592a252b | 11277 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11278 | { Bad_Opcode }, |
592a252b | 11279 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11280 | }, |
11281 | { | |
592a252b | 11282 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11283 | { Bad_Opcode }, |
592a252b | 11284 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11285 | }, |
11286 | { | |
592a252b | 11287 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11288 | { Bad_Opcode }, |
592a252b | 11289 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11290 | }, |
d8faab4e | 11291 | { |
592a252b | 11292 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11293 | { Bad_Opcode }, |
592a252b | 11294 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11295 | }, |
11296 | { | |
592a252b | 11297 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11298 | { Bad_Opcode }, |
592a252b | 11299 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11300 | }, |
876d4bfa | 11301 | { |
592a252b | 11302 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11303 | { Bad_Opcode }, |
592a252b | 11304 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11305 | }, |
11306 | { | |
592a252b | 11307 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11308 | { Bad_Opcode }, |
592a252b | 11309 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11310 | }, |
11311 | { | |
592a252b | 11312 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11313 | { Bad_Opcode }, |
592a252b | 11314 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11315 | }, |
11316 | { | |
592a252b | 11317 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11318 | { Bad_Opcode }, |
592a252b | 11319 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 11320 | }, |
ab4e4ed5 AF |
11321 | { |
11322 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11323 | { "kmovw", { Ew, MaskG }, 0 }, | |
11324 | { Bad_Opcode }, | |
11325 | }, | |
11326 | { | |
11327 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11328 | { "kmovq", { Eq, MaskG }, 0 }, | |
11329 | { Bad_Opcode }, | |
11330 | }, | |
11331 | { | |
11332 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11333 | { "kmovb", { Eb, MaskG }, 0 }, | |
11334 | { Bad_Opcode }, | |
11335 | }, | |
11336 | { | |
11337 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11338 | { "kmovd", { Ed, MaskG }, 0 }, | |
11339 | { Bad_Opcode }, | |
11340 | }, | |
11341 | { | |
11342 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
11343 | { Bad_Opcode }, | |
11344 | { "kmovw", { MaskG, Rdq }, 0 }, | |
11345 | }, | |
11346 | { | |
11347 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
11348 | { Bad_Opcode }, | |
11349 | { "kmovb", { MaskG, Rdq }, 0 }, | |
11350 | }, | |
11351 | { | |
58a211d2 | 11352 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 11353 | { Bad_Opcode }, |
58a211d2 | 11354 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
11355 | }, |
11356 | { | |
11357 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
11358 | { Bad_Opcode }, | |
11359 | { "kmovw", { Gdq, MaskR }, 0 }, | |
11360 | }, | |
11361 | { | |
11362 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
11363 | { Bad_Opcode }, | |
11364 | { "kmovb", { Gdq, MaskR }, 0 }, | |
11365 | }, | |
11366 | { | |
58a211d2 | 11367 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 11368 | { Bad_Opcode }, |
58a211d2 | 11369 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
11370 | }, |
11371 | { | |
11372 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
11373 | { Bad_Opcode }, | |
11374 | { "kortestw", { MaskG, MaskR }, 0 }, | |
11375 | }, | |
11376 | { | |
11377 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
11378 | { Bad_Opcode }, | |
11379 | { "kortestq", { MaskG, MaskR }, 0 }, | |
11380 | }, | |
11381 | { | |
11382 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
11383 | { Bad_Opcode }, | |
11384 | { "kortestb", { MaskG, MaskR }, 0 }, | |
11385 | }, | |
11386 | { | |
11387 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
11388 | { Bad_Opcode }, | |
11389 | { "kortestd", { MaskG, MaskR }, 0 }, | |
11390 | }, | |
11391 | { | |
11392 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
11393 | { Bad_Opcode }, | |
11394 | { "ktestw", { MaskG, MaskR }, 0 }, | |
11395 | }, | |
11396 | { | |
11397 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
11398 | { Bad_Opcode }, | |
11399 | { "ktestq", { MaskG, MaskR }, 0 }, | |
11400 | }, | |
11401 | { | |
11402 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
11403 | { Bad_Opcode }, | |
11404 | { "ktestb", { MaskG, MaskR }, 0 }, | |
11405 | }, | |
11406 | { | |
11407 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
11408 | { Bad_Opcode }, | |
11409 | { "ktestd", { MaskG, MaskR }, 0 }, | |
11410 | }, | |
876d4bfa | 11411 | { |
592a252b L |
11412 | /* MOD_VEX_0FAE_REG_2 */ |
11413 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11414 | }, |
bbedc832 | 11415 | { |
592a252b L |
11416 | /* MOD_VEX_0FAE_REG_3 */ |
11417 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11418 | }, |
144c41d9 | 11419 | { |
592a252b | 11420 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11421 | { Bad_Opcode }, |
ec6f095a | 11422 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 11423 | }, |
1afd85e3 | 11424 | { |
592a252b | 11425 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 11426 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
11427 | }, |
11428 | { | |
592a252b | 11429 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 11430 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 11431 | }, |
75c135a8 | 11432 | { |
592a252b L |
11433 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11434 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11435 | }, |
1afd85e3 | 11436 | { |
592a252b | 11437 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 11438 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 11439 | }, |
75c135a8 | 11440 | { |
592a252b L |
11441 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11442 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11443 | }, |
1afd85e3 | 11444 | { |
592a252b L |
11445 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11446 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11447 | }, |
11448 | { | |
592a252b L |
11449 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11450 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11451 | }, |
11452 | { | |
592a252b L |
11453 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11454 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11455 | }, |
6c30d220 L |
11456 | { |
11457 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11458 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11459 | }, | |
11460 | { | |
11461 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
492a76aa | 11462 | { "vpmaskmov%DQ", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
11463 | }, |
11464 | { | |
11465 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
492a76aa | 11466 | { "vpmaskmov%DQ", { Mx, Vex, XM }, 0 }, |
6c30d220 | 11467 | }, |
ab4e4ed5 AF |
11468 | { |
11469 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
11470 | { Bad_Opcode }, | |
11471 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
11472 | }, | |
11473 | { | |
11474 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
11475 | { Bad_Opcode }, | |
11476 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
11477 | }, | |
11478 | { | |
11479 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
11480 | { Bad_Opcode }, | |
11481 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
11482 | }, | |
11483 | { | |
11484 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
11485 | { Bad_Opcode }, | |
11486 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
11487 | }, | |
11488 | { | |
11489 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
11490 | { Bad_Opcode }, | |
11491 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
11492 | }, | |
11493 | { | |
11494 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
11495 | { Bad_Opcode }, | |
11496 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
11497 | }, | |
11498 | { | |
11499 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
11500 | { Bad_Opcode }, | |
11501 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
11502 | }, | |
11503 | { | |
11504 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
11505 | { Bad_Opcode }, | |
11506 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
11507 | }, | |
467bbef0 JB |
11508 | { |
11509 | /* MOD_VEX_0FXOP_09_12 */ | |
11510 | { Bad_Opcode }, | |
11511 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
11512 | }, | |
ad692897 L |
11513 | |
11514 | #include "i386-dis-evex-mod.h" | |
b844680a L |
11515 | }; |
11516 | ||
1ceb70f8 | 11517 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11518 | { |
11519 | /* RM_C6_REG_7 */ | |
bf890a93 | 11520 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
11521 | }, |
11522 | { | |
11523 | /* RM_C7_REG_7 */ | |
376cd056 | 11524 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 11525 | }, |
b844680a | 11526 | { |
1ceb70f8 | 11527 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 11528 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
11529 | { "vmcall", { Skip_MODRM }, 0 }, |
11530 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
11531 | { "vmresume", { Skip_MODRM }, 0 }, | |
11532 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 11533 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
11534 | }, |
11535 | { | |
1ceb70f8 | 11536 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
11537 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11538 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
11539 | { "clac", { Skip_MODRM }, 0 }, | |
11540 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
11541 | { Bad_Opcode }, |
11542 | { Bad_Opcode }, | |
11543 | { Bad_Opcode }, | |
bf890a93 | 11544 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 11545 | }, |
475a2301 L |
11546 | { |
11547 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11548 | { "xgetbv", { Skip_MODRM }, 0 }, |
11549 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11550 | { Bad_Opcode }, |
11551 | { Bad_Opcode }, | |
bf890a93 IT |
11552 | { "vmfunc", { Skip_MODRM }, 0 }, |
11553 | { "xend", { Skip_MODRM }, 0 }, | |
11554 | { "xtest", { Skip_MODRM }, 0 }, | |
11555 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11556 | }, |
b844680a | 11557 | { |
1ceb70f8 | 11558 | /* RM_0F01_REG_3 */ |
bf890a93 | 11559 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 11560 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
11561 | { "vmload", { Skip_MODRM }, 0 }, |
11562 | { "vmsave", { Skip_MODRM }, 0 }, | |
11563 | { "stgi", { Skip_MODRM }, 0 }, | |
11564 | { "clgi", { Skip_MODRM }, 0 }, | |
11565 | { "skinit", { Skip_MODRM }, 0 }, | |
11566 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11567 | }, |
8eab4136 | 11568 | { |
f8687e93 JB |
11569 | /* RM_0F01_REG_5_MOD_3 */ |
11570 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 11571 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 11572 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11573 | { Bad_Opcode }, |
11574 | { Bad_Opcode }, | |
11575 | { Bad_Opcode }, | |
11576 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11577 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11578 | }, | |
4e7d34a6 | 11579 | { |
f8687e93 | 11580 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11581 | { "swapgs", { Skip_MODRM }, 0 }, |
11582 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11583 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11584 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11585 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11586 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11587 | }, |
603555e5 | 11588 | { |
f8687e93 | 11589 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11590 | { "nopQ", { Ev }, 0 }, |
11591 | { "nopQ", { Ev }, 0 }, | |
11592 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11593 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11594 | { "nopQ", { Ev }, 0 }, | |
11595 | { "nopQ", { Ev }, 0 }, | |
11596 | { "nopQ", { Ev }, 0 }, | |
11597 | { "nopQ", { Ev }, 0 }, | |
11598 | }, | |
b844680a | 11599 | { |
f8687e93 | 11600 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11601 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11602 | }, |
bbedc832 | 11603 | { |
f8687e93 | 11604 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11605 | { "sfence", { Skip_MODRM }, 0 }, |
11606 | ||
144c41d9 | 11607 | }, |
260cd341 LC |
11608 | { |
11609 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
11610 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
11611 | }, | |
b844680a L |
11612 | }; |
11613 | ||
c608c12e AM |
11614 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11615 | ||
f16cd0d5 L |
11616 | /* We use the high bit to indicate different name for the same |
11617 | prefix. */ | |
f16cd0d5 | 11618 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11619 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11620 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11621 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11622 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11623 | |
1d67fe3b TT |
11624 | /* Remember if the current op is a jump instruction. */ |
11625 | static bfd_boolean op_is_jump = FALSE; | |
11626 | ||
f16cd0d5 | 11627 | static int |
26ca5450 | 11628 | ckprefix (void) |
252b5132 | 11629 | { |
f16cd0d5 | 11630 | int newrex, i, length; |
52b15da3 | 11631 | rex = 0; |
252b5132 | 11632 | prefixes = 0; |
7d421014 | 11633 | used_prefixes = 0; |
52b15da3 | 11634 | rex_used = 0; |
f16cd0d5 L |
11635 | last_lock_prefix = -1; |
11636 | last_repz_prefix = -1; | |
11637 | last_repnz_prefix = -1; | |
11638 | last_data_prefix = -1; | |
11639 | last_addr_prefix = -1; | |
11640 | last_rex_prefix = -1; | |
11641 | last_seg_prefix = -1; | |
d9949a36 | 11642 | fwait_prefix = -1; |
285ca992 | 11643 | active_seg_prefix = 0; |
f310f33d L |
11644 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11645 | all_prefixes[i] = 0; | |
11646 | i = 0; | |
f16cd0d5 L |
11647 | length = 0; |
11648 | /* The maximum instruction length is 15bytes. */ | |
11649 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11650 | { |
11651 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11652 | newrex = 0; |
252b5132 RH |
11653 | switch (*codep) |
11654 | { | |
52b15da3 JH |
11655 | /* REX prefixes family. */ |
11656 | case 0x40: | |
11657 | case 0x41: | |
11658 | case 0x42: | |
11659 | case 0x43: | |
11660 | case 0x44: | |
11661 | case 0x45: | |
11662 | case 0x46: | |
11663 | case 0x47: | |
11664 | case 0x48: | |
11665 | case 0x49: | |
11666 | case 0x4a: | |
11667 | case 0x4b: | |
11668 | case 0x4c: | |
11669 | case 0x4d: | |
11670 | case 0x4e: | |
11671 | case 0x4f: | |
f16cd0d5 L |
11672 | if (address_mode == mode_64bit) |
11673 | newrex = *codep; | |
11674 | else | |
11675 | return 1; | |
11676 | last_rex_prefix = i; | |
52b15da3 | 11677 | break; |
252b5132 RH |
11678 | case 0xf3: |
11679 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11680 | last_repz_prefix = i; |
252b5132 RH |
11681 | break; |
11682 | case 0xf2: | |
11683 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11684 | last_repnz_prefix = i; |
252b5132 RH |
11685 | break; |
11686 | case 0xf0: | |
11687 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11688 | last_lock_prefix = i; |
252b5132 RH |
11689 | break; |
11690 | case 0x2e: | |
11691 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11692 | last_seg_prefix = i; |
285ca992 | 11693 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11694 | break; |
11695 | case 0x36: | |
11696 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11697 | last_seg_prefix = i; |
285ca992 | 11698 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11699 | break; |
11700 | case 0x3e: | |
11701 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11702 | last_seg_prefix = i; |
285ca992 | 11703 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11704 | break; |
11705 | case 0x26: | |
11706 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11707 | last_seg_prefix = i; |
285ca992 | 11708 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11709 | break; |
11710 | case 0x64: | |
11711 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11712 | last_seg_prefix = i; |
285ca992 | 11713 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11714 | break; |
11715 | case 0x65: | |
11716 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11717 | last_seg_prefix = i; |
285ca992 | 11718 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11719 | break; |
11720 | case 0x66: | |
11721 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11722 | last_data_prefix = i; |
252b5132 RH |
11723 | break; |
11724 | case 0x67: | |
11725 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11726 | last_addr_prefix = i; |
252b5132 | 11727 | break; |
5076851f | 11728 | case FWAIT_OPCODE: |
252b5132 RH |
11729 | /* fwait is really an instruction. If there are prefixes |
11730 | before the fwait, they belong to the fwait, *not* to the | |
11731 | following instruction. */ | |
d9949a36 | 11732 | fwait_prefix = i; |
3e7d61b2 | 11733 | if (prefixes || rex) |
252b5132 RH |
11734 | { |
11735 | prefixes |= PREFIX_FWAIT; | |
11736 | codep++; | |
6c067bbb RM |
11737 | /* This ensures that the previous REX prefixes are noticed |
11738 | as unused prefixes, as in the return case below. */ | |
11739 | rex_used = rex; | |
f16cd0d5 | 11740 | return 1; |
252b5132 RH |
11741 | } |
11742 | prefixes = PREFIX_FWAIT; | |
11743 | break; | |
11744 | default: | |
f16cd0d5 | 11745 | return 1; |
252b5132 | 11746 | } |
52b15da3 JH |
11747 | /* Rex is ignored when followed by another prefix. */ |
11748 | if (rex) | |
11749 | { | |
3e7d61b2 | 11750 | rex_used = rex; |
f16cd0d5 | 11751 | return 1; |
52b15da3 | 11752 | } |
f16cd0d5 | 11753 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11754 | all_prefixes[i++] = *codep; |
52b15da3 | 11755 | rex = newrex; |
252b5132 | 11756 | codep++; |
f16cd0d5 L |
11757 | length++; |
11758 | } | |
11759 | return 0; | |
11760 | } | |
11761 | ||
7d421014 ILT |
11762 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11763 | prefix byte. */ | |
11764 | ||
11765 | static const char * | |
26ca5450 | 11766 | prefix_name (int pref, int sizeflag) |
7d421014 | 11767 | { |
0003779b L |
11768 | static const char *rexes [16] = |
11769 | { | |
11770 | "rex", /* 0x40 */ | |
11771 | "rex.B", /* 0x41 */ | |
11772 | "rex.X", /* 0x42 */ | |
11773 | "rex.XB", /* 0x43 */ | |
11774 | "rex.R", /* 0x44 */ | |
11775 | "rex.RB", /* 0x45 */ | |
11776 | "rex.RX", /* 0x46 */ | |
11777 | "rex.RXB", /* 0x47 */ | |
11778 | "rex.W", /* 0x48 */ | |
11779 | "rex.WB", /* 0x49 */ | |
11780 | "rex.WX", /* 0x4a */ | |
11781 | "rex.WXB", /* 0x4b */ | |
11782 | "rex.WR", /* 0x4c */ | |
11783 | "rex.WRB", /* 0x4d */ | |
11784 | "rex.WRX", /* 0x4e */ | |
11785 | "rex.WRXB", /* 0x4f */ | |
11786 | }; | |
11787 | ||
7d421014 ILT |
11788 | switch (pref) |
11789 | { | |
52b15da3 JH |
11790 | /* REX prefixes family. */ |
11791 | case 0x40: | |
52b15da3 | 11792 | case 0x41: |
52b15da3 | 11793 | case 0x42: |
52b15da3 | 11794 | case 0x43: |
52b15da3 | 11795 | case 0x44: |
52b15da3 | 11796 | case 0x45: |
52b15da3 | 11797 | case 0x46: |
52b15da3 | 11798 | case 0x47: |
52b15da3 | 11799 | case 0x48: |
52b15da3 | 11800 | case 0x49: |
52b15da3 | 11801 | case 0x4a: |
52b15da3 | 11802 | case 0x4b: |
52b15da3 | 11803 | case 0x4c: |
52b15da3 | 11804 | case 0x4d: |
52b15da3 | 11805 | case 0x4e: |
52b15da3 | 11806 | case 0x4f: |
0003779b | 11807 | return rexes [pref - 0x40]; |
7d421014 ILT |
11808 | case 0xf3: |
11809 | return "repz"; | |
11810 | case 0xf2: | |
11811 | return "repnz"; | |
11812 | case 0xf0: | |
11813 | return "lock"; | |
11814 | case 0x2e: | |
11815 | return "cs"; | |
11816 | case 0x36: | |
11817 | return "ss"; | |
11818 | case 0x3e: | |
11819 | return "ds"; | |
11820 | case 0x26: | |
11821 | return "es"; | |
11822 | case 0x64: | |
11823 | return "fs"; | |
11824 | case 0x65: | |
11825 | return "gs"; | |
11826 | case 0x66: | |
11827 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11828 | case 0x67: | |
cb712a9e | 11829 | if (address_mode == mode_64bit) |
db6eb5be | 11830 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11831 | else |
2888cb7a | 11832 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11833 | case FWAIT_OPCODE: |
11834 | return "fwait"; | |
f16cd0d5 L |
11835 | case REP_PREFIX: |
11836 | return "rep"; | |
42164a71 L |
11837 | case XACQUIRE_PREFIX: |
11838 | return "xacquire"; | |
11839 | case XRELEASE_PREFIX: | |
11840 | return "xrelease"; | |
7e8b059b L |
11841 | case BND_PREFIX: |
11842 | return "bnd"; | |
04ef582a L |
11843 | case NOTRACK_PREFIX: |
11844 | return "notrack"; | |
7d421014 ILT |
11845 | default: |
11846 | return NULL; | |
11847 | } | |
11848 | } | |
11849 | ||
ce518a5f L |
11850 | static char op_out[MAX_OPERANDS][100]; |
11851 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11852 | static int two_source_ops; |
ce518a5f L |
11853 | static bfd_vma op_address[MAX_OPERANDS]; |
11854 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11855 | static bfd_vma start_pc; |
ce518a5f | 11856 | |
252b5132 RH |
11857 | /* |
11858 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11859 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11860 | * section of the "Virtual 8086 Mode" chapter.) | |
11861 | * 'pc' should be the address of this instruction, it will | |
11862 | * be used to print the target address if this is a relative jump or call | |
11863 | * The function returns the length of this instruction in bytes. | |
11864 | */ | |
11865 | ||
252b5132 | 11866 | static char intel_syntax; |
9d141669 | 11867 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11868 | static char open_char; |
11869 | static char close_char; | |
11870 | static char separator_char; | |
11871 | static char scale_char; | |
11872 | ||
5db04b09 L |
11873 | enum x86_64_isa |
11874 | { | |
d835a58b | 11875 | amd64 = 1, |
5db04b09 L |
11876 | intel64 |
11877 | }; | |
11878 | ||
11879 | static enum x86_64_isa isa64; | |
11880 | ||
e396998b AM |
11881 | /* Here for backwards compatibility. When gdb stops using |
11882 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11883 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11884 | int |
26ca5450 | 11885 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11886 | { |
11887 | intel_syntax = 0; | |
e396998b AM |
11888 | |
11889 | return print_insn (pc, info); | |
252b5132 RH |
11890 | } |
11891 | ||
11892 | int | |
26ca5450 | 11893 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11894 | { |
11895 | intel_syntax = 1; | |
e396998b AM |
11896 | |
11897 | return print_insn (pc, info); | |
252b5132 RH |
11898 | } |
11899 | ||
e396998b | 11900 | int |
26ca5450 | 11901 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11902 | { |
11903 | intel_syntax = -1; | |
11904 | ||
11905 | return print_insn (pc, info); | |
11906 | } | |
11907 | ||
f59a29b9 L |
11908 | void |
11909 | print_i386_disassembler_options (FILE *stream) | |
11910 | { | |
11911 | fprintf (stream, _("\n\ | |
11912 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11913 | with the -M switch (multiple options should be separated by commas):\n")); | |
11914 | ||
11915 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11916 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11917 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11918 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11919 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11920 | fprintf (stream, _(" att-mnemonic\n" |
11921 | " Display instruction in AT&T mnemonic\n")); | |
11922 | fprintf (stream, _(" intel-mnemonic\n" | |
11923 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11924 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11925 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11926 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11927 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11928 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11929 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11930 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11931 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11932 | } |
11933 | ||
592d1631 | 11934 | /* Bad opcode. */ |
bf890a93 | 11935 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11936 | |
b844680a L |
11937 | /* Get a pointer to struct dis386 with a valid name. */ |
11938 | ||
11939 | static const struct dis386 * | |
8bb15339 | 11940 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11941 | { |
91d6fa6a | 11942 | int vindex, vex_table_index; |
b844680a L |
11943 | |
11944 | if (dp->name != NULL) | |
11945 | return dp; | |
11946 | ||
11947 | switch (dp->op[0].bytemode) | |
11948 | { | |
1ceb70f8 L |
11949 | case USE_REG_TABLE: |
11950 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11951 | break; | |
11952 | ||
11953 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11954 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11955 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11956 | break; |
11957 | ||
11958 | case USE_RM_TABLE: | |
11959 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11960 | break; |
11961 | ||
4e7d34a6 | 11962 | case USE_PREFIX_TABLE: |
c0f3af97 | 11963 | if (need_vex) |
b844680a | 11964 | { |
c0f3af97 L |
11965 | /* The prefix in VEX is implicit. */ |
11966 | switch (vex.prefix) | |
11967 | { | |
11968 | case 0: | |
91d6fa6a | 11969 | vindex = 0; |
c0f3af97 L |
11970 | break; |
11971 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11972 | vindex = 1; |
c0f3af97 L |
11973 | break; |
11974 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11975 | vindex = 2; |
c0f3af97 L |
11976 | break; |
11977 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11978 | vindex = 3; |
c0f3af97 L |
11979 | break; |
11980 | default: | |
11981 | abort (); | |
11982 | break; | |
11983 | } | |
b844680a | 11984 | } |
7bb15c6f | 11985 | else |
b844680a | 11986 | { |
285ca992 L |
11987 | int last_prefix = -1; |
11988 | int prefix = 0; | |
91d6fa6a | 11989 | vindex = 0; |
285ca992 L |
11990 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11991 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11992 | last one wins. */ | |
11993 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11994 | { |
285ca992 | 11995 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11996 | { |
285ca992 L |
11997 | vindex = 1; |
11998 | prefix = PREFIX_REPZ; | |
11999 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12000 | } |
12001 | else | |
b844680a | 12002 | { |
285ca992 L |
12003 | vindex = 3; |
12004 | prefix = PREFIX_REPNZ; | |
12005 | last_prefix = last_repnz_prefix; | |
b844680a | 12006 | } |
285ca992 | 12007 | |
507bd325 L |
12008 | /* Check if prefix should be ignored. */ |
12009 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12010 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12011 | & prefix) != 0) | |
285ca992 L |
12012 | vindex = 0; |
12013 | } | |
12014 | ||
12015 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12016 | { | |
12017 | vindex = 2; | |
12018 | prefix = PREFIX_DATA; | |
12019 | last_prefix = last_data_prefix; | |
12020 | } | |
12021 | ||
12022 | if (vindex != 0) | |
12023 | { | |
12024 | used_prefixes |= prefix; | |
12025 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12026 | } |
12027 | } | |
91d6fa6a | 12028 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12029 | break; |
12030 | ||
4e7d34a6 | 12031 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12032 | vindex = address_mode == mode_64bit ? 1 : 0; |
12033 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12034 | break; |
12035 | ||
4e7d34a6 | 12036 | case USE_3BYTE_TABLE: |
8bb15339 | 12037 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12038 | vindex = *codep++; |
12039 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12040 | end_codep = codep; |
8bb15339 L |
12041 | modrm.mod = (*codep >> 6) & 3; |
12042 | modrm.reg = (*codep >> 3) & 7; | |
12043 | modrm.rm = *codep & 7; | |
12044 | break; | |
12045 | ||
c0f3af97 L |
12046 | case USE_VEX_LEN_TABLE: |
12047 | if (!need_vex) | |
12048 | abort (); | |
12049 | ||
12050 | switch (vex.length) | |
12051 | { | |
12052 | case 128: | |
91d6fa6a | 12053 | vindex = 0; |
c0f3af97 L |
12054 | break; |
12055 | case 256: | |
91d6fa6a | 12056 | vindex = 1; |
c0f3af97 L |
12057 | break; |
12058 | default: | |
12059 | abort (); | |
12060 | break; | |
12061 | } | |
12062 | ||
91d6fa6a | 12063 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12064 | break; |
12065 | ||
04e2a182 L |
12066 | case USE_EVEX_LEN_TABLE: |
12067 | if (!vex.evex) | |
12068 | abort (); | |
12069 | ||
12070 | switch (vex.length) | |
12071 | { | |
12072 | case 128: | |
12073 | vindex = 0; | |
12074 | break; | |
12075 | case 256: | |
12076 | vindex = 1; | |
12077 | break; | |
12078 | case 512: | |
12079 | vindex = 2; | |
12080 | break; | |
12081 | default: | |
12082 | abort (); | |
12083 | break; | |
12084 | } | |
12085 | ||
12086 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
12087 | break; | |
12088 | ||
f88c9eb0 SP |
12089 | case USE_XOP_8F_TABLE: |
12090 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
12091 | rex = ~(*codep >> 5) & 0x7; |
12092 | ||
12093 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12094 | switch ((*codep & 0x1f)) | |
12095 | { | |
12096 | default: | |
f07af43e L |
12097 | dp = &bad_opcode; |
12098 | return dp; | |
5dd85c99 SP |
12099 | case 0x8: |
12100 | vex_table_index = XOP_08; | |
12101 | break; | |
f88c9eb0 SP |
12102 | case 0x9: |
12103 | vex_table_index = XOP_09; | |
12104 | break; | |
12105 | case 0xa: | |
12106 | vex_table_index = XOP_0A; | |
12107 | break; | |
12108 | } | |
12109 | codep++; | |
12110 | vex.w = *codep & 0x80; | |
12111 | if (vex.w && address_mode == mode_64bit) | |
12112 | rex |= REX_W; | |
12113 | ||
12114 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12115 | if (address_mode != mode_64bit) |
f07af43e | 12116 | { |
abfcb414 AP |
12117 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12118 | rex &= ~REX_B; | |
f07af43e | 12119 | } |
f88c9eb0 SP |
12120 | |
12121 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12122 | switch ((*codep & 0x3)) | |
12123 | { | |
12124 | case 0: | |
f88c9eb0 SP |
12125 | break; |
12126 | case 1: | |
12127 | vex.prefix = DATA_PREFIX_OPCODE; | |
12128 | break; | |
12129 | case 2: | |
12130 | vex.prefix = REPE_PREFIX_OPCODE; | |
12131 | break; | |
12132 | case 3: | |
12133 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12134 | break; | |
12135 | } | |
12136 | need_vex = 1; | |
f88c9eb0 | 12137 | codep++; |
91d6fa6a NC |
12138 | vindex = *codep++; |
12139 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12140 | |
285ca992 | 12141 | end_codep = codep; |
c48244a5 SP |
12142 | FETCH_DATA (info, codep + 1); |
12143 | modrm.mod = (*codep >> 6) & 3; | |
12144 | modrm.reg = (*codep >> 3) & 7; | |
12145 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
12146 | |
12147 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
12148 | having to decode the bits for every otherwise valid encoding. */ | |
12149 | if (vex.prefix) | |
12150 | return &bad_opcode; | |
f88c9eb0 SP |
12151 | break; |
12152 | ||
c0f3af97 | 12153 | case USE_VEX_C4_TABLE: |
43234a1e | 12154 | /* VEX prefix. */ |
c0f3af97 | 12155 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
12156 | rex = ~(*codep >> 5) & 0x7; |
12157 | switch ((*codep & 0x1f)) | |
12158 | { | |
12159 | default: | |
f07af43e L |
12160 | dp = &bad_opcode; |
12161 | return dp; | |
c0f3af97 | 12162 | case 0x1: |
f88c9eb0 | 12163 | vex_table_index = VEX_0F; |
c0f3af97 L |
12164 | break; |
12165 | case 0x2: | |
f88c9eb0 | 12166 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12167 | break; |
12168 | case 0x3: | |
f88c9eb0 | 12169 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12170 | break; |
12171 | } | |
12172 | codep++; | |
12173 | vex.w = *codep & 0x80; | |
9889cbb1 | 12174 | if (address_mode == mode_64bit) |
f07af43e | 12175 | { |
9889cbb1 L |
12176 | if (vex.w) |
12177 | rex |= REX_W; | |
9889cbb1 L |
12178 | } |
12179 | else | |
12180 | { | |
12181 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12182 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12183 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12184 | rex = 0; |
f07af43e | 12185 | } |
5f847646 | 12186 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12187 | vex.length = (*codep & 0x4) ? 256 : 128; |
12188 | switch ((*codep & 0x3)) | |
12189 | { | |
12190 | case 0: | |
c0f3af97 L |
12191 | break; |
12192 | case 1: | |
12193 | vex.prefix = DATA_PREFIX_OPCODE; | |
12194 | break; | |
12195 | case 2: | |
12196 | vex.prefix = REPE_PREFIX_OPCODE; | |
12197 | break; | |
12198 | case 3: | |
12199 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12200 | break; | |
12201 | } | |
12202 | need_vex = 1; | |
c0f3af97 | 12203 | codep++; |
91d6fa6a NC |
12204 | vindex = *codep++; |
12205 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12206 | end_codep = codep; |
53c4d625 JB |
12207 | /* There is no MODRM byte for VEX0F 77. */ |
12208 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12209 | { |
12210 | FETCH_DATA (info, codep + 1); | |
12211 | modrm.mod = (*codep >> 6) & 3; | |
12212 | modrm.reg = (*codep >> 3) & 7; | |
12213 | modrm.rm = *codep & 7; | |
12214 | } | |
12215 | break; | |
12216 | ||
12217 | case USE_VEX_C5_TABLE: | |
43234a1e | 12218 | /* VEX prefix. */ |
c0f3af97 | 12219 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
12220 | rex = (*codep & 0x80) ? 0 : REX_R; |
12221 | ||
9889cbb1 L |
12222 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12223 | VEX.vvvv is 1. */ | |
c0f3af97 | 12224 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12225 | vex.length = (*codep & 0x4) ? 256 : 128; |
12226 | switch ((*codep & 0x3)) | |
12227 | { | |
12228 | case 0: | |
c0f3af97 L |
12229 | break; |
12230 | case 1: | |
12231 | vex.prefix = DATA_PREFIX_OPCODE; | |
12232 | break; | |
12233 | case 2: | |
12234 | vex.prefix = REPE_PREFIX_OPCODE; | |
12235 | break; | |
12236 | case 3: | |
12237 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12238 | break; | |
12239 | } | |
12240 | need_vex = 1; | |
c0f3af97 | 12241 | codep++; |
91d6fa6a NC |
12242 | vindex = *codep++; |
12243 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12244 | end_codep = codep; |
53c4d625 JB |
12245 | /* There is no MODRM byte for VEX 77. */ |
12246 | if (vindex != 0x77) | |
c0f3af97 L |
12247 | { |
12248 | FETCH_DATA (info, codep + 1); | |
12249 | modrm.mod = (*codep >> 6) & 3; | |
12250 | modrm.reg = (*codep >> 3) & 7; | |
12251 | modrm.rm = *codep & 7; | |
12252 | } | |
12253 | break; | |
12254 | ||
9e30b8e0 L |
12255 | case USE_VEX_W_TABLE: |
12256 | if (!need_vex) | |
12257 | abort (); | |
12258 | ||
12259 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12260 | break; | |
12261 | ||
43234a1e L |
12262 | case USE_EVEX_TABLE: |
12263 | two_source_ops = 0; | |
12264 | /* EVEX prefix. */ | |
12265 | vex.evex = 1; | |
12266 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
12267 | /* The first byte after 0x62. */ |
12268 | rex = ~(*codep >> 5) & 0x7; | |
12269 | vex.r = *codep & 0x10; | |
12270 | switch ((*codep & 0xf)) | |
12271 | { | |
12272 | default: | |
12273 | return &bad_opcode; | |
12274 | case 0x1: | |
12275 | vex_table_index = EVEX_0F; | |
12276 | break; | |
12277 | case 0x2: | |
12278 | vex_table_index = EVEX_0F38; | |
12279 | break; | |
12280 | case 0x3: | |
12281 | vex_table_index = EVEX_0F3A; | |
12282 | break; | |
12283 | } | |
12284 | ||
12285 | /* The second byte after 0x62. */ | |
12286 | codep++; | |
12287 | vex.w = *codep & 0x80; | |
12288 | if (vex.w && address_mode == mode_64bit) | |
12289 | rex |= REX_W; | |
12290 | ||
12291 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
12292 | |
12293 | /* The U bit. */ | |
12294 | if (!(*codep & 0x4)) | |
12295 | return &bad_opcode; | |
12296 | ||
12297 | switch ((*codep & 0x3)) | |
12298 | { | |
12299 | case 0: | |
43234a1e L |
12300 | break; |
12301 | case 1: | |
12302 | vex.prefix = DATA_PREFIX_OPCODE; | |
12303 | break; | |
12304 | case 2: | |
12305 | vex.prefix = REPE_PREFIX_OPCODE; | |
12306 | break; | |
12307 | case 3: | |
12308 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12309 | break; | |
12310 | } | |
12311 | ||
12312 | /* The third byte after 0x62. */ | |
12313 | codep++; | |
12314 | ||
12315 | /* Remember the static rounding bits. */ | |
12316 | vex.ll = (*codep >> 5) & 3; | |
12317 | vex.b = (*codep & 0x10) != 0; | |
12318 | ||
12319 | vex.v = *codep & 0x8; | |
12320 | vex.mask_register_specifier = *codep & 0x7; | |
12321 | vex.zeroing = *codep & 0x80; | |
12322 | ||
5f847646 JB |
12323 | if (address_mode != mode_64bit) |
12324 | { | |
12325 | /* In 16/32-bit mode silently ignore following bits. */ | |
12326 | rex &= ~REX_B; | |
12327 | vex.r = 1; | |
12328 | vex.v = 1; | |
12329 | } | |
12330 | ||
43234a1e | 12331 | need_vex = 1; |
43234a1e L |
12332 | codep++; |
12333 | vindex = *codep++; | |
12334 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12335 | end_codep = codep; |
43234a1e L |
12336 | FETCH_DATA (info, codep + 1); |
12337 | modrm.mod = (*codep >> 6) & 3; | |
12338 | modrm.reg = (*codep >> 3) & 7; | |
12339 | modrm.rm = *codep & 7; | |
12340 | ||
12341 | /* Set vector length. */ | |
12342 | if (modrm.mod == 3 && vex.b) | |
12343 | vex.length = 512; | |
12344 | else | |
12345 | { | |
12346 | switch (vex.ll) | |
12347 | { | |
12348 | case 0x0: | |
12349 | vex.length = 128; | |
12350 | break; | |
12351 | case 0x1: | |
12352 | vex.length = 256; | |
12353 | break; | |
12354 | case 0x2: | |
12355 | vex.length = 512; | |
12356 | break; | |
12357 | default: | |
12358 | return &bad_opcode; | |
12359 | } | |
12360 | } | |
12361 | break; | |
12362 | ||
592d1631 L |
12363 | case 0: |
12364 | dp = &bad_opcode; | |
12365 | break; | |
12366 | ||
b844680a | 12367 | default: |
d34b5006 | 12368 | abort (); |
b844680a L |
12369 | } |
12370 | ||
12371 | if (dp->name != NULL) | |
12372 | return dp; | |
12373 | else | |
8bb15339 | 12374 | return get_valid_dis386 (dp, info); |
b844680a L |
12375 | } |
12376 | ||
dfc8cf43 | 12377 | static void |
55cf16e1 | 12378 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12379 | { |
12380 | /* If modrm.mod == 3, operand must be register. */ | |
12381 | if (need_modrm | |
55cf16e1 | 12382 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12383 | && modrm.mod != 3 |
12384 | && modrm.rm == 4) | |
12385 | { | |
12386 | FETCH_DATA (info, codep + 2); | |
12387 | sib.index = (codep [1] >> 3) & 7; | |
12388 | sib.scale = (codep [1] >> 6) & 3; | |
12389 | sib.base = codep [1] & 7; | |
12390 | } | |
12391 | } | |
12392 | ||
e396998b | 12393 | static int |
26ca5450 | 12394 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12395 | { |
2da11e11 | 12396 | const struct dis386 *dp; |
252b5132 | 12397 | int i; |
ce518a5f | 12398 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12399 | int needcomma; |
df18fdba | 12400 | int sizeflag, orig_sizeflag; |
e396998b | 12401 | const char *p; |
252b5132 | 12402 | struct dis_private priv; |
f16cd0d5 | 12403 | int prefix_length; |
252b5132 | 12404 | |
d7921315 L |
12405 | priv.orig_sizeflag = AFLAG | DFLAG; |
12406 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12407 | address_mode = mode_32bit; |
2da11e11 | 12408 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12409 | { |
12410 | address_mode = mode_16bit; | |
12411 | priv.orig_sizeflag = 0; | |
12412 | } | |
2da11e11 | 12413 | else |
d7921315 L |
12414 | address_mode = mode_64bit; |
12415 | ||
12416 | if (intel_syntax == (char) -1) | |
12417 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12418 | |
12419 | for (p = info->disassembler_options; p != NULL; ) | |
12420 | { | |
5db04b09 L |
12421 | if (CONST_STRNEQ (p, "amd64")) |
12422 | isa64 = amd64; | |
12423 | else if (CONST_STRNEQ (p, "intel64")) | |
12424 | isa64 = intel64; | |
12425 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 12426 | { |
cb712a9e | 12427 | address_mode = mode_64bit; |
2a1bb84c | 12428 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12429 | } |
0112cd26 | 12430 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12431 | { |
cb712a9e | 12432 | address_mode = mode_32bit; |
2a1bb84c | 12433 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12434 | } |
0112cd26 | 12435 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12436 | { |
cb712a9e | 12437 | address_mode = mode_16bit; |
2a1bb84c | 12438 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 12439 | } |
0112cd26 | 12440 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12441 | { |
12442 | intel_syntax = 1; | |
9d141669 L |
12443 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12444 | intel_mnemonic = 1; | |
e396998b | 12445 | } |
0112cd26 | 12446 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12447 | { |
12448 | intel_syntax = 0; | |
9d141669 L |
12449 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12450 | intel_mnemonic = 0; | |
e396998b | 12451 | } |
0112cd26 | 12452 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12453 | { |
f59a29b9 L |
12454 | if (address_mode == mode_64bit) |
12455 | { | |
12456 | if (p[4] == '3' && p[5] == '2') | |
12457 | priv.orig_sizeflag &= ~AFLAG; | |
12458 | else if (p[4] == '6' && p[5] == '4') | |
12459 | priv.orig_sizeflag |= AFLAG; | |
12460 | } | |
12461 | else | |
12462 | { | |
12463 | if (p[4] == '1' && p[5] == '6') | |
12464 | priv.orig_sizeflag &= ~AFLAG; | |
12465 | else if (p[4] == '3' && p[5] == '2') | |
12466 | priv.orig_sizeflag |= AFLAG; | |
12467 | } | |
e396998b | 12468 | } |
0112cd26 | 12469 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12470 | { |
12471 | if (p[4] == '1' && p[5] == '6') | |
12472 | priv.orig_sizeflag &= ~DFLAG; | |
12473 | else if (p[4] == '3' && p[5] == '2') | |
12474 | priv.orig_sizeflag |= DFLAG; | |
12475 | } | |
0112cd26 | 12476 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12477 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12478 | ||
12479 | p = strchr (p, ','); | |
12480 | if (p != NULL) | |
12481 | p++; | |
12482 | } | |
12483 | ||
c0f92bf9 L |
12484 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
12485 | { | |
12486 | (*info->fprintf_func) (info->stream, | |
12487 | _("64-bit address is disabled")); | |
12488 | return -1; | |
12489 | } | |
12490 | ||
e396998b AM |
12491 | if (intel_syntax) |
12492 | { | |
12493 | names64 = intel_names64; | |
12494 | names32 = intel_names32; | |
12495 | names16 = intel_names16; | |
12496 | names8 = intel_names8; | |
12497 | names8rex = intel_names8rex; | |
12498 | names_seg = intel_names_seg; | |
b9733481 | 12499 | names_mm = intel_names_mm; |
7e8b059b | 12500 | names_bnd = intel_names_bnd; |
b9733481 L |
12501 | names_xmm = intel_names_xmm; |
12502 | names_ymm = intel_names_ymm; | |
43234a1e | 12503 | names_zmm = intel_names_zmm; |
260cd341 | 12504 | names_tmm = intel_names_tmm; |
db51cc60 L |
12505 | index64 = intel_index64; |
12506 | index32 = intel_index32; | |
43234a1e | 12507 | names_mask = intel_names_mask; |
e396998b AM |
12508 | index16 = intel_index16; |
12509 | open_char = '['; | |
12510 | close_char = ']'; | |
12511 | separator_char = '+'; | |
12512 | scale_char = '*'; | |
12513 | } | |
12514 | else | |
12515 | { | |
12516 | names64 = att_names64; | |
12517 | names32 = att_names32; | |
12518 | names16 = att_names16; | |
12519 | names8 = att_names8; | |
12520 | names8rex = att_names8rex; | |
12521 | names_seg = att_names_seg; | |
b9733481 | 12522 | names_mm = att_names_mm; |
7e8b059b | 12523 | names_bnd = att_names_bnd; |
b9733481 L |
12524 | names_xmm = att_names_xmm; |
12525 | names_ymm = att_names_ymm; | |
43234a1e | 12526 | names_zmm = att_names_zmm; |
260cd341 | 12527 | names_tmm = att_names_tmm; |
db51cc60 L |
12528 | index64 = att_index64; |
12529 | index32 = att_index32; | |
43234a1e | 12530 | names_mask = att_names_mask; |
e396998b AM |
12531 | index16 = att_index16; |
12532 | open_char = '('; | |
12533 | close_char = ')'; | |
12534 | separator_char = ','; | |
12535 | scale_char = ','; | |
12536 | } | |
2da11e11 | 12537 | |
4fe53c98 | 12538 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12539 | puts most long word instructions on a single line. Use 8 bytes |
12540 | for Intel L1OM. */ | |
d7921315 | 12541 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12542 | info->bytes_per_line = 8; |
12543 | else | |
12544 | info->bytes_per_line = 7; | |
252b5132 | 12545 | |
26ca5450 | 12546 | info->private_data = &priv; |
252b5132 RH |
12547 | priv.max_fetched = priv.the_buffer; |
12548 | priv.insn_start = pc; | |
252b5132 RH |
12549 | |
12550 | obuf[0] = 0; | |
ce518a5f L |
12551 | for (i = 0; i < MAX_OPERANDS; ++i) |
12552 | { | |
12553 | op_out[i][0] = 0; | |
12554 | op_index[i] = -1; | |
12555 | } | |
252b5132 RH |
12556 | |
12557 | the_info = info; | |
12558 | start_pc = pc; | |
e396998b AM |
12559 | start_codep = priv.the_buffer; |
12560 | codep = priv.the_buffer; | |
252b5132 | 12561 | |
8df14d78 | 12562 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12563 | { |
7d421014 ILT |
12564 | const char *name; |
12565 | ||
5076851f | 12566 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12567 | means we have an incomplete instruction of some sort. Just |
12568 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12569 | if (codep > priv.the_buffer) | |
5076851f | 12570 | { |
e396998b | 12571 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12572 | if (name != NULL) |
12573 | (*info->fprintf_func) (info->stream, "%s", name); | |
12574 | else | |
5076851f | 12575 | { |
7d421014 ILT |
12576 | /* Just print the first byte as a .byte instruction. */ |
12577 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12578 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12579 | } |
5076851f | 12580 | |
7d421014 | 12581 | return 1; |
5076851f ILT |
12582 | } |
12583 | ||
12584 | return -1; | |
12585 | } | |
12586 | ||
52b15da3 | 12587 | obufp = obuf; |
f16cd0d5 L |
12588 | sizeflag = priv.orig_sizeflag; |
12589 | ||
12590 | if (!ckprefix () || rex_used) | |
12591 | { | |
12592 | /* Too many prefixes or unused REX prefixes. */ | |
12593 | for (i = 0; | |
f6dd4781 | 12594 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12595 | i++) |
de882298 | 12596 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12597 | i == 0 ? "" : " ", |
f16cd0d5 | 12598 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12599 | return i; |
f16cd0d5 | 12600 | } |
252b5132 RH |
12601 | |
12602 | insn_codep = codep; | |
12603 | ||
12604 | FETCH_DATA (info, codep + 1); | |
12605 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12606 | ||
3e7d61b2 | 12607 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12608 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12609 | { |
86a80a50 | 12610 | /* Handle prefixes before fwait. */ |
d9949a36 | 12611 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12612 | i++) |
12613 | (*info->fprintf_func) (info->stream, "%s ", | |
12614 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12615 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12616 | return i + 1; |
252b5132 RH |
12617 | } |
12618 | ||
252b5132 RH |
12619 | if (*codep == 0x0f) |
12620 | { | |
eec0f4ca | 12621 | unsigned char threebyte; |
5f40e14d JS |
12622 | |
12623 | codep++; | |
12624 | FETCH_DATA (info, codep + 1); | |
12625 | threebyte = *codep; | |
eec0f4ca | 12626 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12627 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12628 | codep++; |
252b5132 RH |
12629 | } |
12630 | else | |
12631 | { | |
6439fc28 | 12632 | dp = &dis386[*codep]; |
252b5132 | 12633 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12634 | codep++; |
252b5132 | 12635 | } |
246c51aa | 12636 | |
df18fdba L |
12637 | /* Save sizeflag for printing the extra prefixes later before updating |
12638 | it for mnemonic and operand processing. The prefix names depend | |
12639 | only on the address mode. */ | |
12640 | orig_sizeflag = sizeflag; | |
c608c12e | 12641 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12642 | sizeflag ^= AFLAG; |
b844680a | 12643 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12644 | sizeflag ^= DFLAG; |
3ffd33cf | 12645 | |
285ca992 | 12646 | end_codep = codep; |
8bb15339 | 12647 | if (need_modrm) |
252b5132 RH |
12648 | { |
12649 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12650 | modrm.mod = (*codep >> 6) & 3; |
12651 | modrm.reg = (*codep >> 3) & 7; | |
12652 | modrm.rm = *codep & 7; | |
252b5132 RH |
12653 | } |
12654 | ||
42d5f9c6 | 12655 | need_vex = 0; |
caf0678c | 12656 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12657 | |
ce518a5f | 12658 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12659 | { |
55cf16e1 | 12660 | get_sib (info, sizeflag); |
252b5132 RH |
12661 | dofloat (sizeflag); |
12662 | } | |
12663 | else | |
12664 | { | |
8bb15339 | 12665 | dp = get_valid_dis386 (dp, info); |
b844680a | 12666 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12667 | { |
55cf16e1 | 12668 | get_sib (info, sizeflag); |
ce518a5f L |
12669 | for (i = 0; i < MAX_OPERANDS; ++i) |
12670 | { | |
246c51aa | 12671 | obufp = op_out[i]; |
ce518a5f L |
12672 | op_ad = MAX_OPERANDS - 1 - i; |
12673 | if (dp->op[i].rtn) | |
12674 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12675 | /* For EVEX instruction after the last operand masking |
12676 | should be printed. */ | |
12677 | if (i == 0 && vex.evex) | |
12678 | { | |
12679 | /* Don't print {%k0}. */ | |
12680 | if (vex.mask_register_specifier) | |
12681 | { | |
12682 | oappend ("{"); | |
12683 | oappend (names_mask[vex.mask_register_specifier]); | |
12684 | oappend ("}"); | |
12685 | } | |
12686 | if (vex.zeroing) | |
12687 | oappend ("{z}"); | |
12688 | } | |
ce518a5f | 12689 | } |
6439fc28 | 12690 | } |
252b5132 RH |
12691 | } |
12692 | ||
1d67fe3b TT |
12693 | /* Clear instruction information. */ |
12694 | if (the_info) | |
12695 | { | |
12696 | the_info->insn_info_valid = 0; | |
12697 | the_info->branch_delay_insns = 0; | |
12698 | the_info->data_size = 0; | |
12699 | the_info->insn_type = dis_noninsn; | |
12700 | the_info->target = 0; | |
12701 | the_info->target2 = 0; | |
12702 | } | |
12703 | ||
12704 | /* Reset jump operation indicator. */ | |
12705 | op_is_jump = FALSE; | |
12706 | ||
12707 | { | |
12708 | int jump_detection = 0; | |
12709 | ||
12710 | /* Extract flags. */ | |
12711 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12712 | { | |
12713 | if ((dp->op[i].rtn == OP_J) | |
12714 | || (dp->op[i].rtn == OP_indirE)) | |
12715 | jump_detection |= 1; | |
12716 | else if ((dp->op[i].rtn == BND_Fixup) | |
12717 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12718 | jump_detection |= 2; | |
12719 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12720 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12721 | jump_detection |= 4; | |
12722 | } | |
12723 | ||
12724 | /* Determine if this is a jump or branch. */ | |
12725 | if ((jump_detection & 0x3) == 0x3) | |
12726 | { | |
12727 | op_is_jump = TRUE; | |
12728 | if (jump_detection & 0x4) | |
12729 | the_info->insn_type = dis_condbranch; | |
12730 | else | |
12731 | the_info->insn_type = | |
12732 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12733 | ? dis_jsr : dis_branch; | |
12734 | } | |
12735 | } | |
12736 | ||
63c6fc6c L |
12737 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12738 | are all 0s in inverted form. */ | |
12739 | if (need_vex && vex.register_specifier != 0) | |
12740 | { | |
12741 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12742 | return end_codep - priv.the_buffer; | |
12743 | } | |
12744 | ||
d869730d | 12745 | /* Check if the REX prefix is used. */ |
73239888 | 12746 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12747 | all_prefixes[last_rex_prefix] = 0; |
12748 | ||
5e6718e4 | 12749 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12750 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12751 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12752 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12753 | all_prefixes[last_seg_prefix] = 0; |
12754 | ||
5e6718e4 | 12755 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12756 | if ((prefixes & PREFIX_ADDR) != 0 |
12757 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12758 | all_prefixes[last_addr_prefix] = 0; | |
12759 | ||
df18fdba L |
12760 | /* Check if the DATA prefix is used. */ |
12761 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12762 | && (used_prefixes & PREFIX_DATA) != 0 |
12763 | && !need_vex) | |
df18fdba | 12764 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12765 | |
df18fdba | 12766 | /* Print the extra prefixes. */ |
f16cd0d5 | 12767 | prefix_length = 0; |
f310f33d | 12768 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12769 | if (all_prefixes[i]) |
12770 | { | |
12771 | const char *name; | |
df18fdba | 12772 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12773 | if (name == NULL) |
12774 | abort (); | |
12775 | prefix_length += strlen (name) + 1; | |
12776 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12777 | } | |
b844680a | 12778 | |
285ca992 L |
12779 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12780 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12781 | used by putop and MMX/SSE operand and may be overriden by the | |
12782 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12783 | separately. */ | |
3888916d | 12784 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12785 | && (((need_vex |
12786 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12787 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12788 | : (prefixes | |
12789 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12790 | && (used_prefixes |
12791 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12792 | || (((need_vex |
12793 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12794 | : ((prefixes | |
12795 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12796 | == PREFIX_DATA)) | |
97e6786a JB |
12797 | && (used_prefixes & PREFIX_DATA) == 0)) |
12798 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12799 | { |
12800 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12801 | return end_codep - priv.the_buffer; | |
12802 | } | |
12803 | ||
f16cd0d5 L |
12804 | /* Check maximum code length. */ |
12805 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12806 | { | |
12807 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12808 | return MAX_CODE_LENGTH; | |
12809 | } | |
b844680a | 12810 | |
ea397f5b | 12811 | obufp = mnemonicendp; |
f16cd0d5 | 12812 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12813 | oappend (" "); |
12814 | oappend (" "); | |
12815 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12816 | ||
12817 | /* The enter and bound instructions are printed with operands in the same | |
12818 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12819 | if (intel_syntax || two_source_ops) |
252b5132 | 12820 | { |
185b1163 L |
12821 | bfd_vma riprel; |
12822 | ||
ce518a5f | 12823 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12824 | op_txt[i] = op_out[i]; |
246c51aa | 12825 | |
3a8547d2 JB |
12826 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12827 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12828 | { | |
12829 | op_txt[2] = op_out[3]; | |
12830 | op_txt[3] = op_out[2]; | |
12831 | } | |
12832 | ||
ce518a5f L |
12833 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12834 | { | |
6c067bbb RM |
12835 | op_ad = op_index[i]; |
12836 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12837 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12838 | riprel = op_riprel[i]; |
12839 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12840 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12841 | } |
252b5132 RH |
12842 | } |
12843 | else | |
12844 | { | |
ce518a5f | 12845 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12846 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12847 | } |
12848 | ||
ce518a5f L |
12849 | needcomma = 0; |
12850 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12851 | if (*op_txt[i]) | |
12852 | { | |
12853 | if (needcomma) | |
12854 | (*info->fprintf_func) (info->stream, ","); | |
12855 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12856 | { |
12857 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12858 | ||
12859 | if (the_info && op_is_jump) | |
12860 | { | |
12861 | the_info->insn_info_valid = 1; | |
12862 | the_info->branch_delay_insns = 0; | |
12863 | the_info->data_size = 0; | |
12864 | the_info->target = target; | |
12865 | the_info->target2 = 0; | |
12866 | } | |
12867 | (*info->print_address_func) (target, info); | |
12868 | } | |
ce518a5f L |
12869 | else |
12870 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12871 | needcomma = 1; | |
12872 | } | |
050dfa73 | 12873 | |
ce518a5f | 12874 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12875 | if (op_index[i] != -1 && op_riprel[i]) |
12876 | { | |
12877 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12878 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12879 | + op_address[op_index[i]]), info); |
185b1163 | 12880 | break; |
52b15da3 | 12881 | } |
e396998b | 12882 | return codep - priv.the_buffer; |
252b5132 RH |
12883 | } |
12884 | ||
6439fc28 | 12885 | static const char *float_mem[] = { |
252b5132 | 12886 | /* d8 */ |
7c52e0e8 L |
12887 | "fadd{s|}", |
12888 | "fmul{s|}", | |
12889 | "fcom{s|}", | |
12890 | "fcomp{s|}", | |
12891 | "fsub{s|}", | |
12892 | "fsubr{s|}", | |
12893 | "fdiv{s|}", | |
12894 | "fdivr{s|}", | |
db6eb5be | 12895 | /* d9 */ |
7c52e0e8 | 12896 | "fld{s|}", |
252b5132 | 12897 | "(bad)", |
7c52e0e8 L |
12898 | "fst{s|}", |
12899 | "fstp{s|}", | |
d1c36125 | 12900 | "fldenv{C|C}", |
252b5132 | 12901 | "fldcw", |
d1c36125 | 12902 | "fNstenv{C|C}", |
252b5132 RH |
12903 | "fNstcw", |
12904 | /* da */ | |
7c52e0e8 L |
12905 | "fiadd{l|}", |
12906 | "fimul{l|}", | |
12907 | "ficom{l|}", | |
12908 | "ficomp{l|}", | |
12909 | "fisub{l|}", | |
12910 | "fisubr{l|}", | |
12911 | "fidiv{l|}", | |
12912 | "fidivr{l|}", | |
252b5132 | 12913 | /* db */ |
7c52e0e8 L |
12914 | "fild{l|}", |
12915 | "fisttp{l|}", | |
12916 | "fist{l|}", | |
12917 | "fistp{l|}", | |
252b5132 | 12918 | "(bad)", |
464dc4af | 12919 | "fld{t|}", |
252b5132 | 12920 | "(bad)", |
464dc4af | 12921 | "fstp{t|}", |
252b5132 | 12922 | /* dc */ |
7c52e0e8 L |
12923 | "fadd{l|}", |
12924 | "fmul{l|}", | |
12925 | "fcom{l|}", | |
12926 | "fcomp{l|}", | |
12927 | "fsub{l|}", | |
12928 | "fsubr{l|}", | |
12929 | "fdiv{l|}", | |
12930 | "fdivr{l|}", | |
252b5132 | 12931 | /* dd */ |
7c52e0e8 L |
12932 | "fld{l|}", |
12933 | "fisttp{ll|}", | |
12934 | "fst{l||}", | |
12935 | "fstp{l|}", | |
d1c36125 | 12936 | "frstor{C|C}", |
252b5132 | 12937 | "(bad)", |
d1c36125 | 12938 | "fNsave{C|C}", |
252b5132 RH |
12939 | "fNstsw", |
12940 | /* de */ | |
ac465521 JB |
12941 | "fiadd{s|}", |
12942 | "fimul{s|}", | |
12943 | "ficom{s|}", | |
12944 | "ficomp{s|}", | |
12945 | "fisub{s|}", | |
12946 | "fisubr{s|}", | |
12947 | "fidiv{s|}", | |
12948 | "fidivr{s|}", | |
252b5132 | 12949 | /* df */ |
ac465521 JB |
12950 | "fild{s|}", |
12951 | "fisttp{s|}", | |
12952 | "fist{s|}", | |
12953 | "fistp{s|}", | |
252b5132 | 12954 | "fbld", |
7c52e0e8 | 12955 | "fild{ll|}", |
252b5132 | 12956 | "fbstp", |
7c52e0e8 | 12957 | "fistp{ll|}", |
1d9f512f AM |
12958 | }; |
12959 | ||
12960 | static const unsigned char float_mem_mode[] = { | |
12961 | /* d8 */ | |
12962 | d_mode, | |
12963 | d_mode, | |
12964 | d_mode, | |
12965 | d_mode, | |
12966 | d_mode, | |
12967 | d_mode, | |
12968 | d_mode, | |
12969 | d_mode, | |
12970 | /* d9 */ | |
12971 | d_mode, | |
12972 | 0, | |
12973 | d_mode, | |
12974 | d_mode, | |
12975 | 0, | |
12976 | w_mode, | |
12977 | 0, | |
12978 | w_mode, | |
12979 | /* da */ | |
12980 | d_mode, | |
12981 | d_mode, | |
12982 | d_mode, | |
12983 | d_mode, | |
12984 | d_mode, | |
12985 | d_mode, | |
12986 | d_mode, | |
12987 | d_mode, | |
12988 | /* db */ | |
12989 | d_mode, | |
12990 | d_mode, | |
12991 | d_mode, | |
12992 | d_mode, | |
12993 | 0, | |
9306ca4a | 12994 | t_mode, |
1d9f512f | 12995 | 0, |
9306ca4a | 12996 | t_mode, |
1d9f512f AM |
12997 | /* dc */ |
12998 | q_mode, | |
12999 | q_mode, | |
13000 | q_mode, | |
13001 | q_mode, | |
13002 | q_mode, | |
13003 | q_mode, | |
13004 | q_mode, | |
13005 | q_mode, | |
13006 | /* dd */ | |
13007 | q_mode, | |
13008 | q_mode, | |
13009 | q_mode, | |
13010 | q_mode, | |
13011 | 0, | |
13012 | 0, | |
13013 | 0, | |
13014 | w_mode, | |
13015 | /* de */ | |
13016 | w_mode, | |
13017 | w_mode, | |
13018 | w_mode, | |
13019 | w_mode, | |
13020 | w_mode, | |
13021 | w_mode, | |
13022 | w_mode, | |
13023 | w_mode, | |
13024 | /* df */ | |
13025 | w_mode, | |
13026 | w_mode, | |
13027 | w_mode, | |
13028 | w_mode, | |
9306ca4a | 13029 | t_mode, |
1d9f512f | 13030 | q_mode, |
9306ca4a | 13031 | t_mode, |
1d9f512f | 13032 | q_mode |
252b5132 RH |
13033 | }; |
13034 | ||
ce518a5f L |
13035 | #define ST { OP_ST, 0 } |
13036 | #define STi { OP_STi, 0 } | |
252b5132 | 13037 | |
48c97fa1 L |
13038 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13039 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13040 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13041 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13042 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13043 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13044 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13045 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13046 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13047 | |
2da11e11 | 13048 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13049 | /* d8 */ |
13050 | { | |
bf890a93 IT |
13051 | { "fadd", { ST, STi }, 0 }, |
13052 | { "fmul", { ST, STi }, 0 }, | |
13053 | { "fcom", { STi }, 0 }, | |
13054 | { "fcomp", { STi }, 0 }, | |
13055 | { "fsub", { ST, STi }, 0 }, | |
13056 | { "fsubr", { ST, STi }, 0 }, | |
13057 | { "fdiv", { ST, STi }, 0 }, | |
13058 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13059 | }, |
13060 | /* d9 */ | |
13061 | { | |
bf890a93 IT |
13062 | { "fld", { STi }, 0 }, |
13063 | { "fxch", { STi }, 0 }, | |
252b5132 | 13064 | { FGRPd9_2 }, |
592d1631 | 13065 | { Bad_Opcode }, |
252b5132 RH |
13066 | { FGRPd9_4 }, |
13067 | { FGRPd9_5 }, | |
13068 | { FGRPd9_6 }, | |
13069 | { FGRPd9_7 }, | |
13070 | }, | |
13071 | /* da */ | |
13072 | { | |
bf890a93 IT |
13073 | { "fcmovb", { ST, STi }, 0 }, |
13074 | { "fcmove", { ST, STi }, 0 }, | |
13075 | { "fcmovbe",{ ST, STi }, 0 }, | |
13076 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13077 | { Bad_Opcode }, |
252b5132 | 13078 | { FGRPda_5 }, |
592d1631 L |
13079 | { Bad_Opcode }, |
13080 | { Bad_Opcode }, | |
252b5132 RH |
13081 | }, |
13082 | /* db */ | |
13083 | { | |
bf890a93 IT |
13084 | { "fcmovnb",{ ST, STi }, 0 }, |
13085 | { "fcmovne",{ ST, STi }, 0 }, | |
13086 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13087 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13088 | { FGRPdb_4 }, |
bf890a93 IT |
13089 | { "fucomi", { ST, STi }, 0 }, |
13090 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13091 | { Bad_Opcode }, |
252b5132 RH |
13092 | }, |
13093 | /* dc */ | |
13094 | { | |
bf890a93 IT |
13095 | { "fadd", { STi, ST }, 0 }, |
13096 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13097 | { Bad_Opcode }, |
13098 | { Bad_Opcode }, | |
d53e6b98 JB |
13099 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13100 | { "fsub{M|}", { STi, ST }, 0 }, | |
13101 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13102 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13103 | }, |
13104 | /* dd */ | |
13105 | { | |
bf890a93 | 13106 | { "ffree", { STi }, 0 }, |
592d1631 | 13107 | { Bad_Opcode }, |
bf890a93 IT |
13108 | { "fst", { STi }, 0 }, |
13109 | { "fstp", { STi }, 0 }, | |
13110 | { "fucom", { STi }, 0 }, | |
13111 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13112 | { Bad_Opcode }, |
13113 | { Bad_Opcode }, | |
252b5132 RH |
13114 | }, |
13115 | /* de */ | |
13116 | { | |
bf890a93 IT |
13117 | { "faddp", { STi, ST }, 0 }, |
13118 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13119 | { Bad_Opcode }, |
252b5132 | 13120 | { FGRPde_3 }, |
d53e6b98 JB |
13121 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13122 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13123 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13124 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13125 | }, |
13126 | /* df */ | |
13127 | { | |
bf890a93 | 13128 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13129 | { Bad_Opcode }, |
13130 | { Bad_Opcode }, | |
13131 | { Bad_Opcode }, | |
252b5132 | 13132 | { FGRPdf_4 }, |
bf890a93 IT |
13133 | { "fucomip", { ST, STi }, 0 }, |
13134 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13135 | { Bad_Opcode }, |
252b5132 RH |
13136 | }, |
13137 | }; | |
13138 | ||
252b5132 | 13139 | static char *fgrps[][8] = { |
48c97fa1 L |
13140 | /* Bad opcode 0 */ |
13141 | { | |
13142 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13143 | }, | |
13144 | ||
13145 | /* d9_2 1 */ | |
252b5132 RH |
13146 | { |
13147 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13148 | }, | |
13149 | ||
48c97fa1 | 13150 | /* d9_4 2 */ |
252b5132 RH |
13151 | { |
13152 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13153 | }, | |
13154 | ||
48c97fa1 | 13155 | /* d9_5 3 */ |
252b5132 RH |
13156 | { |
13157 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13158 | }, | |
13159 | ||
48c97fa1 | 13160 | /* d9_6 4 */ |
252b5132 RH |
13161 | { |
13162 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13163 | }, | |
13164 | ||
48c97fa1 | 13165 | /* d9_7 5 */ |
252b5132 RH |
13166 | { |
13167 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13168 | }, | |
13169 | ||
48c97fa1 | 13170 | /* da_5 6 */ |
252b5132 RH |
13171 | { |
13172 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13173 | }, | |
13174 | ||
48c97fa1 | 13175 | /* db_4 7 */ |
252b5132 | 13176 | { |
309d3373 JB |
13177 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13178 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13179 | }, |
13180 | ||
48c97fa1 | 13181 | /* de_3 8 */ |
252b5132 RH |
13182 | { |
13183 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13184 | }, | |
13185 | ||
48c97fa1 | 13186 | /* df_4 9 */ |
252b5132 RH |
13187 | { |
13188 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13189 | }, | |
13190 | }; | |
13191 | ||
b6169b20 L |
13192 | static void |
13193 | swap_operand (void) | |
13194 | { | |
13195 | mnemonicendp[0] = '.'; | |
13196 | mnemonicendp[1] = 's'; | |
13197 | mnemonicendp += 2; | |
13198 | } | |
13199 | ||
b844680a L |
13200 | static void |
13201 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13202 | int sizeflag ATTRIBUTE_UNUSED) | |
13203 | { | |
13204 | /* Skip mod/rm byte. */ | |
13205 | MODRM_CHECK; | |
13206 | codep++; | |
13207 | } | |
13208 | ||
252b5132 | 13209 | static void |
26ca5450 | 13210 | dofloat (int sizeflag) |
252b5132 | 13211 | { |
2da11e11 | 13212 | const struct dis386 *dp; |
252b5132 RH |
13213 | unsigned char floatop; |
13214 | ||
13215 | floatop = codep[-1]; | |
13216 | ||
7967e09e | 13217 | if (modrm.mod != 3) |
252b5132 | 13218 | { |
7967e09e | 13219 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13220 | |
13221 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13222 | obufp = op_out[0]; |
6e50d963 | 13223 | op_ad = 2; |
1d9f512f | 13224 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13225 | return; |
13226 | } | |
6608db57 | 13227 | /* Skip mod/rm byte. */ |
4bba6815 | 13228 | MODRM_CHECK; |
252b5132 RH |
13229 | codep++; |
13230 | ||
7967e09e | 13231 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13232 | if (dp->name == NULL) |
13233 | { | |
7967e09e | 13234 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13235 | |
6608db57 | 13236 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13237 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13238 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13239 | } |
13240 | else | |
13241 | { | |
13242 | putop (dp->name, sizeflag); | |
13243 | ||
ce518a5f | 13244 | obufp = op_out[0]; |
6e50d963 | 13245 | op_ad = 2; |
ce518a5f L |
13246 | if (dp->op[0].rtn) |
13247 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13248 | |
ce518a5f | 13249 | obufp = op_out[1]; |
6e50d963 | 13250 | op_ad = 1; |
ce518a5f L |
13251 | if (dp->op[1].rtn) |
13252 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13253 | } |
13254 | } | |
13255 | ||
9ce09ba2 RM |
13256 | /* Like oappend (below), but S is a string starting with '%'. |
13257 | In Intel syntax, the '%' is elided. */ | |
13258 | static void | |
13259 | oappend_maybe_intel (const char *s) | |
13260 | { | |
13261 | oappend (s + intel_syntax); | |
13262 | } | |
13263 | ||
252b5132 | 13264 | static void |
26ca5450 | 13265 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13266 | { |
9ce09ba2 | 13267 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13268 | } |
13269 | ||
252b5132 | 13270 | static void |
26ca5450 | 13271 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13272 | { |
7967e09e | 13273 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13274 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13275 | } |
13276 | ||
6608db57 | 13277 | /* Capital letters in template are macros. */ |
6439fc28 | 13278 | static int |
d3ce72d0 | 13279 | putop (const char *in_template, int sizeflag) |
252b5132 | 13280 | { |
2da11e11 | 13281 | const char *p; |
9306ca4a | 13282 | int alt = 0; |
9d141669 | 13283 | int cond = 1; |
21a3faeb | 13284 | unsigned int l = 0, len = 0; |
98b528ac L |
13285 | char last[4]; |
13286 | ||
d3ce72d0 | 13287 | for (p = in_template; *p; p++) |
252b5132 | 13288 | { |
21a3faeb JB |
13289 | if (len > l) |
13290 | { | |
13291 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
13292 | abort (); | |
13293 | last[l++] = *p; | |
13294 | continue; | |
13295 | } | |
252b5132 RH |
13296 | switch (*p) |
13297 | { | |
13298 | default: | |
13299 | *obufp++ = *p; | |
13300 | break; | |
98b528ac L |
13301 | case '%': |
13302 | len++; | |
13303 | break; | |
9d141669 L |
13304 | case '!': |
13305 | cond = 0; | |
13306 | break; | |
6439fc28 | 13307 | case '{': |
6439fc28 | 13308 | if (intel_syntax) |
6439fc28 AM |
13309 | { |
13310 | while (*++p != '|') | |
7c52e0e8 L |
13311 | if (*p == '}' || *p == '\0') |
13312 | abort (); | |
d1c36125 | 13313 | alt = 1; |
6439fc28 | 13314 | } |
d1c36125 | 13315 | break; |
6439fc28 AM |
13316 | case '|': |
13317 | while (*++p != '}') | |
13318 | { | |
13319 | if (*p == '\0') | |
13320 | abort (); | |
13321 | } | |
13322 | break; | |
13323 | case '}': | |
d1c36125 | 13324 | alt = 0; |
6439fc28 | 13325 | break; |
252b5132 | 13326 | case 'A': |
db6eb5be AM |
13327 | if (intel_syntax) |
13328 | break; | |
7967e09e | 13329 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13330 | *obufp++ = 'b'; |
13331 | break; | |
13332 | case 'B': | |
21a3faeb | 13333 | if (l == 0) |
4b06377f | 13334 | { |
dc1e8a47 | 13335 | case_B: |
4b06377f L |
13336 | if (intel_syntax) |
13337 | break; | |
13338 | if (sizeflag & SUFFIX_ALWAYS) | |
13339 | *obufp++ = 'b'; | |
13340 | } | |
21a3faeb | 13341 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13342 | { |
4b06377f L |
13343 | if (address_mode == mode_64bit |
13344 | && !(prefixes & PREFIX_ADDR)) | |
13345 | { | |
13346 | *obufp++ = 'a'; | |
13347 | *obufp++ = 'b'; | |
13348 | *obufp++ = 's'; | |
13349 | } | |
13350 | ||
13351 | goto case_B; | |
13352 | } | |
21a3faeb JB |
13353 | else |
13354 | abort (); | |
252b5132 | 13355 | break; |
9306ca4a JB |
13356 | case 'C': |
13357 | if (intel_syntax && !alt) | |
13358 | break; | |
13359 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13360 | { | |
13361 | if (sizeflag & DFLAG) | |
13362 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13363 | else | |
13364 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13365 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13366 | } | |
13367 | break; | |
ed7841b3 JB |
13368 | case 'D': |
13369 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13370 | break; | |
161a04f6 | 13371 | USED_REX (REX_W); |
7967e09e | 13372 | if (modrm.mod == 3) |
ed7841b3 | 13373 | { |
161a04f6 | 13374 | if (rex & REX_W) |
ed7841b3 | 13375 | *obufp++ = 'q'; |
ed7841b3 | 13376 | else |
f16cd0d5 L |
13377 | { |
13378 | if (sizeflag & DFLAG) | |
13379 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13380 | else | |
13381 | *obufp++ = 'w'; | |
13382 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13383 | } | |
ed7841b3 JB |
13384 | } |
13385 | else | |
13386 | *obufp++ = 'w'; | |
13387 | break; | |
252b5132 | 13388 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13389 | if (address_mode == mode_64bit) |
c1a64871 JH |
13390 | { |
13391 | if (sizeflag & AFLAG) | |
13392 | *obufp++ = 'r'; | |
13393 | else | |
13394 | *obufp++ = 'e'; | |
13395 | } | |
13396 | else | |
13397 | if (sizeflag & AFLAG) | |
13398 | *obufp++ = 'e'; | |
3ffd33cf AM |
13399 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13400 | break; | |
13401 | case 'F': | |
db6eb5be AM |
13402 | if (intel_syntax) |
13403 | break; | |
e396998b | 13404 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13405 | { |
13406 | if (sizeflag & AFLAG) | |
cb712a9e | 13407 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13408 | else |
cb712a9e | 13409 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13410 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13411 | } | |
252b5132 | 13412 | break; |
52fd6d94 JB |
13413 | case 'G': |
13414 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13415 | break; | |
161a04f6 | 13416 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13417 | *obufp++ = 'l'; |
13418 | else | |
13419 | *obufp++ = 'w'; | |
161a04f6 | 13420 | if (!(rex & REX_W)) |
52fd6d94 JB |
13421 | used_prefixes |= (prefixes & PREFIX_DATA); |
13422 | break; | |
5dd0794d | 13423 | case 'H': |
db6eb5be AM |
13424 | if (intel_syntax) |
13425 | break; | |
5dd0794d AM |
13426 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13427 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13428 | { | |
13429 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13430 | *obufp++ = ','; | |
13431 | *obufp++ = 'p'; | |
13432 | if (prefixes & PREFIX_DS) | |
13433 | *obufp++ = 't'; | |
13434 | else | |
13435 | *obufp++ = 'n'; | |
13436 | } | |
13437 | break; | |
42903f7f L |
13438 | case 'K': |
13439 | USED_REX (REX_W); | |
13440 | if (rex & REX_W) | |
13441 | *obufp++ = 'q'; | |
13442 | else | |
13443 | *obufp++ = 'd'; | |
13444 | break; | |
6dd5059a | 13445 | case 'Z': |
21a3faeb | 13446 | if (l != 0) |
04d824a4 | 13447 | { |
21a3faeb JB |
13448 | if (l != 1 || last[0] != 'X') |
13449 | abort (); | |
04d824a4 JB |
13450 | if (!need_vex || !vex.evex) |
13451 | abort (); | |
13452 | if (intel_syntax | |
13453 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
13454 | break; | |
13455 | switch (vex.length) | |
13456 | { | |
13457 | case 128: | |
13458 | *obufp++ = 'x'; | |
13459 | break; | |
13460 | case 256: | |
13461 | *obufp++ = 'y'; | |
13462 | break; | |
13463 | case 512: | |
13464 | *obufp++ = 'z'; | |
13465 | break; | |
13466 | default: | |
13467 | abort (); | |
13468 | } | |
13469 | break; | |
13470 | } | |
6dd5059a L |
13471 | if (intel_syntax) |
13472 | break; | |
13473 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13474 | { | |
13475 | *obufp++ = 'q'; | |
13476 | break; | |
13477 | } | |
13478 | /* Fall through. */ | |
98b528ac | 13479 | goto case_L; |
252b5132 | 13480 | case 'L': |
21a3faeb JB |
13481 | if (l != 0) |
13482 | abort (); | |
dc1e8a47 | 13483 | case_L: |
db6eb5be AM |
13484 | if (intel_syntax) |
13485 | break; | |
252b5132 RH |
13486 | if (sizeflag & SUFFIX_ALWAYS) |
13487 | *obufp++ = 'l'; | |
252b5132 | 13488 | break; |
9d141669 L |
13489 | case 'M': |
13490 | if (intel_mnemonic != cond) | |
13491 | *obufp++ = 'r'; | |
13492 | break; | |
252b5132 RH |
13493 | case 'N': |
13494 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13495 | *obufp++ = 'n'; | |
7d421014 ILT |
13496 | else |
13497 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13498 | break; |
52b15da3 | 13499 | case 'O': |
161a04f6 L |
13500 | USED_REX (REX_W); |
13501 | if (rex & REX_W) | |
6439fc28 | 13502 | *obufp++ = 'o'; |
a35ca55a JB |
13503 | else if (intel_syntax && (sizeflag & DFLAG)) |
13504 | *obufp++ = 'q'; | |
52b15da3 JH |
13505 | else |
13506 | *obufp++ = 'd'; | |
161a04f6 | 13507 | if (!(rex & REX_W)) |
a35ca55a | 13508 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13509 | break; |
07f5af7d L |
13510 | case '&': |
13511 | if (!intel_syntax | |
13512 | && address_mode == mode_64bit | |
13513 | && isa64 == intel64) | |
13514 | { | |
13515 | *obufp++ = 'q'; | |
13516 | break; | |
13517 | } | |
13518 | /* Fall through. */ | |
6439fc28 | 13519 | case 'T': |
d9e3625e L |
13520 | if (!intel_syntax |
13521 | && address_mode == mode_64bit | |
7bb15c6f | 13522 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13523 | { |
13524 | *obufp++ = 'q'; | |
13525 | break; | |
13526 | } | |
6608db57 | 13527 | /* Fall through. */ |
4b4c407a | 13528 | goto case_P; |
252b5132 | 13529 | case 'P': |
21a3faeb | 13530 | if (l == 0) |
d9e3625e | 13531 | { |
dc1e8a47 | 13532 | case_P: |
4b4c407a | 13533 | if (intel_syntax) |
d9e3625e | 13534 | { |
4b4c407a L |
13535 | if ((rex & REX_W) == 0 |
13536 | && (prefixes & PREFIX_DATA)) | |
13537 | { | |
13538 | if ((sizeflag & DFLAG) == 0) | |
13539 | *obufp++ = 'w'; | |
13540 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13541 | } | |
13542 | break; | |
13543 | } | |
13544 | if ((prefixes & PREFIX_DATA) | |
13545 | || (rex & REX_W) | |
13546 | || (sizeflag & SUFFIX_ALWAYS)) | |
13547 | { | |
13548 | USED_REX (REX_W); | |
13549 | if (rex & REX_W) | |
13550 | *obufp++ = 'q'; | |
13551 | else | |
13552 | { | |
13553 | if (sizeflag & DFLAG) | |
13554 | *obufp++ = 'l'; | |
13555 | else | |
13556 | *obufp++ = 'w'; | |
13557 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13558 | } | |
d9e3625e | 13559 | } |
d9e3625e | 13560 | } |
21a3faeb | 13561 | else if (l == 1 && last[0] == 'L') |
252b5132 | 13562 | { |
4b4c407a L |
13563 | if ((prefixes & PREFIX_DATA) |
13564 | || (rex & REX_W) | |
13565 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13566 | { |
4b4c407a L |
13567 | USED_REX (REX_W); |
13568 | if (rex & REX_W) | |
13569 | *obufp++ = 'q'; | |
13570 | else | |
13571 | { | |
13572 | if (sizeflag & DFLAG) | |
13573 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13574 | else | |
13575 | *obufp++ = 'w'; | |
13576 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13577 | } | |
52b15da3 | 13578 | } |
252b5132 | 13579 | } |
21a3faeb JB |
13580 | else |
13581 | abort (); | |
252b5132 | 13582 | break; |
6439fc28 | 13583 | case 'U': |
db6eb5be AM |
13584 | if (intel_syntax) |
13585 | break; | |
7bb15c6f | 13586 | if (address_mode == mode_64bit |
6c067bbb | 13587 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13588 | { |
7967e09e | 13589 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13590 | *obufp++ = 'q'; |
6439fc28 AM |
13591 | break; |
13592 | } | |
6608db57 | 13593 | /* Fall through. */ |
98b528ac | 13594 | goto case_Q; |
252b5132 | 13595 | case 'Q': |
21a3faeb | 13596 | if (l == 0) |
252b5132 | 13597 | { |
dc1e8a47 | 13598 | case_Q: |
98b528ac L |
13599 | if (intel_syntax && !alt) |
13600 | break; | |
13601 | USED_REX (REX_W); | |
13602 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13603 | { |
98b528ac L |
13604 | if (rex & REX_W) |
13605 | *obufp++ = 'q'; | |
52b15da3 | 13606 | else |
98b528ac L |
13607 | { |
13608 | if (sizeflag & DFLAG) | |
13609 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13610 | else | |
13611 | *obufp++ = 'w'; | |
f16cd0d5 | 13612 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13613 | } |
52b15da3 | 13614 | } |
98b528ac | 13615 | } |
492a76aa JB |
13616 | else if (l == 1 && last[0] == 'D') |
13617 | *obufp++ = vex.w ? 'q' : 'd'; | |
21a3faeb | 13618 | else if (l == 1 && last[0] == 'L') |
98b528ac | 13619 | { |
b24d668c JB |
13620 | if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
13621 | : address_mode != mode_64bit) | |
98b528ac L |
13622 | break; |
13623 | if ((rex & REX_W)) | |
13624 | { | |
13625 | USED_REX (REX_W); | |
13626 | *obufp++ = 'q'; | |
13627 | } | |
b24d668c | 13628 | else if((address_mode == mode_64bit && need_modrm && cond) |
589958d6 JB |
13629 | || (sizeflag & SUFFIX_ALWAYS)) |
13630 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 13631 | } |
21a3faeb JB |
13632 | else |
13633 | abort (); | |
252b5132 RH |
13634 | break; |
13635 | case 'R': | |
161a04f6 L |
13636 | USED_REX (REX_W); |
13637 | if (rex & REX_W) | |
a35ca55a JB |
13638 | *obufp++ = 'q'; |
13639 | else if (sizeflag & DFLAG) | |
c608c12e | 13640 | { |
a35ca55a | 13641 | if (intel_syntax) |
c608c12e | 13642 | *obufp++ = 'd'; |
c608c12e | 13643 | else |
a35ca55a | 13644 | *obufp++ = 'l'; |
c608c12e | 13645 | } |
252b5132 | 13646 | else |
a35ca55a JB |
13647 | *obufp++ = 'w'; |
13648 | if (intel_syntax && !p[1] | |
161a04f6 | 13649 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13650 | *obufp++ = 'e'; |
161a04f6 | 13651 | if (!(rex & REX_W)) |
52b15da3 | 13652 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13653 | break; |
1a114b12 | 13654 | case 'V': |
21a3faeb | 13655 | if (l == 0) |
1a114b12 | 13656 | { |
4b06377f L |
13657 | if (intel_syntax) |
13658 | break; | |
7bb15c6f | 13659 | if (address_mode == mode_64bit |
6c067bbb | 13660 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13661 | { |
13662 | if (sizeflag & SUFFIX_ALWAYS) | |
13663 | *obufp++ = 'q'; | |
13664 | break; | |
13665 | } | |
13666 | } | |
21a3faeb | 13667 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13668 | { |
4b06377f L |
13669 | if (rex & REX_W) |
13670 | { | |
13671 | *obufp++ = 'a'; | |
13672 | *obufp++ = 'b'; | |
13673 | *obufp++ = 's'; | |
13674 | } | |
1a114b12 | 13675 | } |
21a3faeb JB |
13676 | else |
13677 | abort (); | |
1a114b12 | 13678 | /* Fall through. */ |
4b06377f | 13679 | goto case_S; |
252b5132 | 13680 | case 'S': |
21a3faeb | 13681 | if (l == 0) |
252b5132 | 13682 | { |
dc1e8a47 | 13683 | case_S: |
4b06377f L |
13684 | if (intel_syntax) |
13685 | break; | |
13686 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13687 | { |
4b06377f L |
13688 | if (rex & REX_W) |
13689 | *obufp++ = 'q'; | |
52b15da3 | 13690 | else |
4b06377f L |
13691 | { |
13692 | if (sizeflag & DFLAG) | |
13693 | *obufp++ = 'l'; | |
13694 | else | |
13695 | *obufp++ = 'w'; | |
13696 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13697 | } | |
13698 | } | |
13699 | } | |
21a3faeb | 13700 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13701 | { |
4b06377f L |
13702 | if (address_mode == mode_64bit |
13703 | && !(prefixes & PREFIX_ADDR)) | |
13704 | { | |
13705 | *obufp++ = 'a'; | |
13706 | *obufp++ = 'b'; | |
13707 | *obufp++ = 's'; | |
13708 | } | |
13709 | ||
13710 | goto case_S; | |
252b5132 | 13711 | } |
21a3faeb JB |
13712 | else |
13713 | abort (); | |
252b5132 | 13714 | break; |
041bd2e0 | 13715 | case 'X': |
21a3faeb JB |
13716 | if (l != 0) |
13717 | abort (); | |
bf926894 JB |
13718 | if (need_vex |
13719 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13720 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13721 | { |
bf926894 JB |
13722 | *obufp++ = 'd'; |
13723 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13724 | } |
041bd2e0 | 13725 | else |
bf926894 | 13726 | *obufp++ = 's'; |
041bd2e0 | 13727 | break; |
76f227a5 | 13728 | case 'Y': |
21a3faeb | 13729 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 13730 | { |
c0f3af97 L |
13731 | if (!need_vex) |
13732 | abort (); | |
13733 | if (intel_syntax | |
04d824a4 | 13734 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13735 | break; |
13736 | switch (vex.length) | |
13737 | { | |
13738 | case 128: | |
13739 | *obufp++ = 'x'; | |
13740 | break; | |
13741 | case 256: | |
13742 | *obufp++ = 'y'; | |
13743 | break; | |
04d824a4 JB |
13744 | case 512: |
13745 | if (!vex.evex) | |
c0f3af97 | 13746 | default: |
04d824a4 | 13747 | abort (); |
c0f3af97 | 13748 | } |
76f227a5 | 13749 | } |
21a3faeb JB |
13750 | else |
13751 | abort (); | |
76f227a5 | 13752 | break; |
252b5132 | 13753 | case 'W': |
21a3faeb | 13754 | if (l == 0) |
a35ca55a | 13755 | { |
0bfee649 L |
13756 | /* operand size flag for cwtl, cbtw */ |
13757 | USED_REX (REX_W); | |
13758 | if (rex & REX_W) | |
13759 | { | |
13760 | if (intel_syntax) | |
13761 | *obufp++ = 'd'; | |
13762 | else | |
13763 | *obufp++ = 'l'; | |
13764 | } | |
13765 | else if (sizeflag & DFLAG) | |
13766 | *obufp++ = 'w'; | |
a35ca55a | 13767 | else |
0bfee649 L |
13768 | *obufp++ = 'b'; |
13769 | if (!(rex & REX_W)) | |
13770 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13771 | } |
21a3faeb | 13772 | else if (l == 1) |
0bfee649 | 13773 | { |
0bfee649 L |
13774 | if (!need_vex) |
13775 | abort (); | |
6c30d220 L |
13776 | if (last[0] == 'X') |
13777 | *obufp++ = vex.w ? 'd': 's'; | |
931452b6 JB |
13778 | else if (last[0] == 'B') |
13779 | *obufp++ = vex.w ? 'w': 'b'; | |
21a3faeb JB |
13780 | else |
13781 | abort (); | |
0bfee649 | 13782 | } |
21a3faeb JB |
13783 | else |
13784 | abort (); | |
252b5132 | 13785 | break; |
a72d2af2 L |
13786 | case '^': |
13787 | if (intel_syntax) | |
13788 | break; | |
5990e377 JB |
13789 | if (isa64 == intel64 && (rex & REX_W)) |
13790 | { | |
13791 | USED_REX (REX_W); | |
13792 | *obufp++ = 'q'; | |
13793 | break; | |
13794 | } | |
a72d2af2 L |
13795 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13796 | { | |
13797 | if (sizeflag & DFLAG) | |
13798 | *obufp++ = 'l'; | |
13799 | else | |
13800 | *obufp++ = 'w'; | |
13801 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13802 | } | |
13803 | break; | |
5db04b09 L |
13804 | case '@': |
13805 | if (intel_syntax) | |
13806 | break; | |
13807 | if (address_mode == mode_64bit | |
13808 | && (isa64 == intel64 | |
13809 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13810 | *obufp++ = 'q'; | |
13811 | else if ((prefixes & PREFIX_DATA)) | |
13812 | { | |
13813 | if (!(sizeflag & DFLAG)) | |
13814 | *obufp++ = 'w'; | |
13815 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13816 | } | |
13817 | break; | |
252b5132 | 13818 | } |
21a3faeb JB |
13819 | |
13820 | if (len == l) | |
13821 | len = l = 0; | |
252b5132 RH |
13822 | } |
13823 | *obufp = 0; | |
ea397f5b | 13824 | mnemonicendp = obufp; |
6439fc28 | 13825 | return 0; |
252b5132 RH |
13826 | } |
13827 | ||
13828 | static void | |
26ca5450 | 13829 | oappend (const char *s) |
252b5132 | 13830 | { |
ea397f5b | 13831 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13832 | } |
13833 | ||
13834 | static void | |
26ca5450 | 13835 | append_seg (void) |
252b5132 | 13836 | { |
285ca992 L |
13837 | /* Only print the active segment register. */ |
13838 | if (!active_seg_prefix) | |
13839 | return; | |
13840 | ||
13841 | used_prefixes |= active_seg_prefix; | |
13842 | switch (active_seg_prefix) | |
7d421014 | 13843 | { |
285ca992 | 13844 | case PREFIX_CS: |
9ce09ba2 | 13845 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13846 | break; |
13847 | case PREFIX_DS: | |
9ce09ba2 | 13848 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13849 | break; |
13850 | case PREFIX_SS: | |
9ce09ba2 | 13851 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13852 | break; |
13853 | case PREFIX_ES: | |
9ce09ba2 | 13854 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13855 | break; |
13856 | case PREFIX_FS: | |
9ce09ba2 | 13857 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13858 | break; |
13859 | case PREFIX_GS: | |
9ce09ba2 | 13860 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13861 | break; |
13862 | default: | |
13863 | break; | |
7d421014 | 13864 | } |
252b5132 RH |
13865 | } |
13866 | ||
13867 | static void | |
26ca5450 | 13868 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13869 | { |
13870 | if (!intel_syntax) | |
13871 | oappend ("*"); | |
13872 | OP_E (bytemode, sizeflag); | |
13873 | } | |
13874 | ||
52b15da3 | 13875 | static void |
26ca5450 | 13876 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13877 | { |
cb712a9e | 13878 | if (address_mode == mode_64bit) |
52b15da3 JH |
13879 | { |
13880 | if (hex) | |
13881 | { | |
13882 | char tmp[30]; | |
13883 | int i; | |
13884 | buf[0] = '0'; | |
13885 | buf[1] = 'x'; | |
13886 | sprintf_vma (tmp, disp); | |
6608db57 | 13887 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13888 | strcpy (buf + 2, tmp + i); |
13889 | } | |
13890 | else | |
13891 | { | |
13892 | bfd_signed_vma v = disp; | |
13893 | char tmp[30]; | |
13894 | int i; | |
13895 | if (v < 0) | |
13896 | { | |
13897 | *(buf++) = '-'; | |
13898 | v = -disp; | |
6608db57 | 13899 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13900 | if (v < 0) |
13901 | { | |
13902 | strcpy (buf, "9223372036854775808"); | |
13903 | return; | |
13904 | } | |
13905 | } | |
13906 | if (!v) | |
13907 | { | |
13908 | strcpy (buf, "0"); | |
13909 | return; | |
13910 | } | |
13911 | ||
13912 | i = 0; | |
13913 | tmp[29] = 0; | |
13914 | while (v) | |
13915 | { | |
6608db57 | 13916 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13917 | v /= 10; |
13918 | i++; | |
13919 | } | |
13920 | strcpy (buf, tmp + 29 - i); | |
13921 | } | |
13922 | } | |
13923 | else | |
13924 | { | |
13925 | if (hex) | |
13926 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13927 | else | |
13928 | sprintf (buf, "%d", (int) disp); | |
13929 | } | |
13930 | } | |
13931 | ||
5d669648 L |
13932 | /* Put DISP in BUF as signed hex number. */ |
13933 | ||
13934 | static void | |
13935 | print_displacement (char *buf, bfd_vma disp) | |
13936 | { | |
13937 | bfd_signed_vma val = disp; | |
13938 | char tmp[30]; | |
13939 | int i, j = 0; | |
13940 | ||
13941 | if (val < 0) | |
13942 | { | |
13943 | buf[j++] = '-'; | |
13944 | val = -disp; | |
13945 | ||
13946 | /* Check for possible overflow. */ | |
13947 | if (val < 0) | |
13948 | { | |
13949 | switch (address_mode) | |
13950 | { | |
13951 | case mode_64bit: | |
13952 | strcpy (buf + j, "0x8000000000000000"); | |
13953 | break; | |
13954 | case mode_32bit: | |
13955 | strcpy (buf + j, "0x80000000"); | |
13956 | break; | |
13957 | case mode_16bit: | |
13958 | strcpy (buf + j, "0x8000"); | |
13959 | break; | |
13960 | } | |
13961 | return; | |
13962 | } | |
13963 | } | |
13964 | ||
13965 | buf[j++] = '0'; | |
13966 | buf[j++] = 'x'; | |
13967 | ||
0af1713e | 13968 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13969 | for (i = 0; tmp[i] == '0'; i++) |
13970 | continue; | |
13971 | if (tmp[i] == '\0') | |
13972 | i--; | |
13973 | strcpy (buf + j, tmp + i); | |
13974 | } | |
13975 | ||
3f31e633 JB |
13976 | static void |
13977 | intel_operand_size (int bytemode, int sizeflag) | |
13978 | { | |
43234a1e L |
13979 | if (vex.evex |
13980 | && vex.b | |
13981 | && (bytemode == x_mode | |
13982 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13983 | { | |
13984 | if (vex.w) | |
13985 | oappend ("QWORD PTR "); | |
13986 | else | |
13987 | oappend ("DWORD PTR "); | |
13988 | return; | |
13989 | } | |
3f31e633 JB |
13990 | switch (bytemode) |
13991 | { | |
13992 | case b_mode: | |
b6169b20 | 13993 | case b_swap_mode: |
42903f7f | 13994 | case dqb_mode: |
1ba585e8 | 13995 | case db_mode: |
3f31e633 JB |
13996 | oappend ("BYTE PTR "); |
13997 | break; | |
13998 | case w_mode: | |
1ba585e8 | 13999 | case dw_mode: |
3f31e633 JB |
14000 | case dqw_mode: |
14001 | oappend ("WORD PTR "); | |
14002 | break; | |
07f5af7d L |
14003 | case indir_v_mode: |
14004 | if (address_mode == mode_64bit && isa64 == intel64) | |
14005 | { | |
14006 | oappend ("QWORD PTR "); | |
14007 | break; | |
14008 | } | |
1a0670f3 | 14009 | /* Fall through. */ |
1a114b12 | 14010 | case stack_v_mode: |
7bb15c6f | 14011 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14012 | { |
14013 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14014 | break; |
14015 | } | |
1a0670f3 | 14016 | /* Fall through. */ |
3f31e633 | 14017 | case v_mode: |
b6169b20 | 14018 | case v_swap_mode: |
3f31e633 | 14019 | case dq_mode: |
161a04f6 L |
14020 | USED_REX (REX_W); |
14021 | if (rex & REX_W) | |
3f31e633 | 14022 | oappend ("QWORD PTR "); |
3f31e633 | 14023 | else |
f16cd0d5 L |
14024 | { |
14025 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14026 | oappend ("DWORD PTR "); | |
14027 | else | |
14028 | oappend ("WORD PTR "); | |
14029 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14030 | } | |
3f31e633 | 14031 | break; |
52fd6d94 | 14032 | case z_mode: |
161a04f6 | 14033 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14034 | *obufp++ = 'D'; |
14035 | oappend ("WORD PTR "); | |
161a04f6 | 14036 | if (!(rex & REX_W)) |
52fd6d94 JB |
14037 | used_prefixes |= (prefixes & PREFIX_DATA); |
14038 | break; | |
34b772a6 JB |
14039 | case a_mode: |
14040 | if (sizeflag & DFLAG) | |
14041 | oappend ("QWORD PTR "); | |
14042 | else | |
14043 | oappend ("DWORD PTR "); | |
14044 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14045 | break; | |
bc31405e L |
14046 | case movsxd_mode: |
14047 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14048 | oappend ("WORD PTR "); | |
14049 | else | |
14050 | oappend ("DWORD PTR "); | |
14051 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14052 | break; | |
3f31e633 | 14053 | case d_mode: |
fa99fab2 | 14054 | case d_swap_mode: |
42903f7f | 14055 | case dqd_mode: |
3f31e633 JB |
14056 | oappend ("DWORD PTR "); |
14057 | break; | |
14058 | case q_mode: | |
b6169b20 | 14059 | case q_swap_mode: |
3f31e633 JB |
14060 | oappend ("QWORD PTR "); |
14061 | break; | |
14062 | case m_mode: | |
cb712a9e | 14063 | if (address_mode == mode_64bit) |
3f31e633 JB |
14064 | oappend ("QWORD PTR "); |
14065 | else | |
14066 | oappend ("DWORD PTR "); | |
14067 | break; | |
14068 | case f_mode: | |
14069 | if (sizeflag & DFLAG) | |
14070 | oappend ("FWORD PTR "); | |
14071 | else | |
14072 | oappend ("DWORD PTR "); | |
14073 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14074 | break; | |
14075 | case t_mode: | |
14076 | oappend ("TBYTE PTR "); | |
14077 | break; | |
14078 | case x_mode: | |
b6169b20 | 14079 | case x_swap_mode: |
43234a1e L |
14080 | case evex_x_gscat_mode: |
14081 | case evex_x_nobcst_mode: | |
4726e9a4 | 14082 | case bw_unit_mode: |
c0f3af97 L |
14083 | if (need_vex) |
14084 | { | |
14085 | switch (vex.length) | |
14086 | { | |
14087 | case 128: | |
14088 | oappend ("XMMWORD PTR "); | |
14089 | break; | |
14090 | case 256: | |
14091 | oappend ("YMMWORD PTR "); | |
14092 | break; | |
43234a1e L |
14093 | case 512: |
14094 | oappend ("ZMMWORD PTR "); | |
14095 | break; | |
c0f3af97 L |
14096 | default: |
14097 | abort (); | |
14098 | } | |
14099 | } | |
14100 | else | |
14101 | oappend ("XMMWORD PTR "); | |
14102 | break; | |
14103 | case xmm_mode: | |
3f31e633 JB |
14104 | oappend ("XMMWORD PTR "); |
14105 | break; | |
43234a1e L |
14106 | case ymm_mode: |
14107 | oappend ("YMMWORD PTR "); | |
14108 | break; | |
c0f3af97 | 14109 | case xmmq_mode: |
43234a1e | 14110 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14111 | if (!need_vex) |
14112 | abort (); | |
14113 | ||
14114 | switch (vex.length) | |
14115 | { | |
14116 | case 128: | |
14117 | oappend ("QWORD PTR "); | |
14118 | break; | |
14119 | case 256: | |
14120 | oappend ("XMMWORD PTR "); | |
14121 | break; | |
43234a1e L |
14122 | case 512: |
14123 | oappend ("YMMWORD PTR "); | |
14124 | break; | |
c0f3af97 L |
14125 | default: |
14126 | abort (); | |
14127 | } | |
14128 | break; | |
6c30d220 L |
14129 | case xmm_mb_mode: |
14130 | if (!need_vex) | |
14131 | abort (); | |
14132 | ||
14133 | switch (vex.length) | |
14134 | { | |
14135 | case 128: | |
14136 | case 256: | |
43234a1e | 14137 | case 512: |
6c30d220 L |
14138 | oappend ("BYTE PTR "); |
14139 | break; | |
14140 | default: | |
14141 | abort (); | |
14142 | } | |
14143 | break; | |
14144 | case xmm_mw_mode: | |
14145 | if (!need_vex) | |
14146 | abort (); | |
14147 | ||
14148 | switch (vex.length) | |
14149 | { | |
14150 | case 128: | |
14151 | case 256: | |
43234a1e | 14152 | case 512: |
6c30d220 L |
14153 | oappend ("WORD PTR "); |
14154 | break; | |
14155 | default: | |
14156 | abort (); | |
14157 | } | |
14158 | break; | |
14159 | case xmm_md_mode: | |
14160 | if (!need_vex) | |
14161 | abort (); | |
14162 | ||
14163 | switch (vex.length) | |
14164 | { | |
14165 | case 128: | |
14166 | case 256: | |
43234a1e | 14167 | case 512: |
6c30d220 L |
14168 | oappend ("DWORD PTR "); |
14169 | break; | |
14170 | default: | |
14171 | abort (); | |
14172 | } | |
14173 | break; | |
14174 | case xmm_mq_mode: | |
14175 | if (!need_vex) | |
14176 | abort (); | |
14177 | ||
14178 | switch (vex.length) | |
14179 | { | |
14180 | case 128: | |
14181 | case 256: | |
43234a1e | 14182 | case 512: |
6c30d220 L |
14183 | oappend ("QWORD PTR "); |
14184 | break; | |
14185 | default: | |
14186 | abort (); | |
14187 | } | |
14188 | break; | |
14189 | case xmmdw_mode: | |
14190 | if (!need_vex) | |
14191 | abort (); | |
14192 | ||
14193 | switch (vex.length) | |
14194 | { | |
14195 | case 128: | |
14196 | oappend ("WORD PTR "); | |
14197 | break; | |
14198 | case 256: | |
14199 | oappend ("DWORD PTR "); | |
14200 | break; | |
43234a1e L |
14201 | case 512: |
14202 | oappend ("QWORD PTR "); | |
14203 | break; | |
6c30d220 L |
14204 | default: |
14205 | abort (); | |
14206 | } | |
14207 | break; | |
14208 | case xmmqd_mode: | |
14209 | if (!need_vex) | |
14210 | abort (); | |
14211 | ||
14212 | switch (vex.length) | |
14213 | { | |
14214 | case 128: | |
14215 | oappend ("DWORD PTR "); | |
14216 | break; | |
14217 | case 256: | |
14218 | oappend ("QWORD PTR "); | |
14219 | break; | |
43234a1e L |
14220 | case 512: |
14221 | oappend ("XMMWORD PTR "); | |
14222 | break; | |
6c30d220 L |
14223 | default: |
14224 | abort (); | |
14225 | } | |
14226 | break; | |
c0f3af97 L |
14227 | case ymmq_mode: |
14228 | if (!need_vex) | |
14229 | abort (); | |
14230 | ||
14231 | switch (vex.length) | |
14232 | { | |
14233 | case 128: | |
14234 | oappend ("QWORD PTR "); | |
14235 | break; | |
14236 | case 256: | |
14237 | oappend ("YMMWORD PTR "); | |
14238 | break; | |
43234a1e L |
14239 | case 512: |
14240 | oappend ("ZMMWORD PTR "); | |
14241 | break; | |
c0f3af97 L |
14242 | default: |
14243 | abort (); | |
14244 | } | |
14245 | break; | |
6c30d220 L |
14246 | case ymmxmm_mode: |
14247 | if (!need_vex) | |
14248 | abort (); | |
14249 | ||
14250 | switch (vex.length) | |
14251 | { | |
14252 | case 128: | |
14253 | case 256: | |
14254 | oappend ("XMMWORD PTR "); | |
14255 | break; | |
14256 | default: | |
14257 | abort (); | |
14258 | } | |
14259 | break; | |
fb9c77c7 L |
14260 | case o_mode: |
14261 | oappend ("OWORD PTR "); | |
14262 | break; | |
1c480963 | 14263 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14264 | if (!need_vex) |
14265 | abort (); | |
14266 | ||
14267 | if (vex.w) | |
14268 | oappend ("QWORD PTR "); | |
14269 | else | |
14270 | oappend ("DWORD PTR "); | |
14271 | break; | |
43234a1e L |
14272 | case vex_vsib_d_w_dq_mode: |
14273 | case vex_vsib_q_w_dq_mode: | |
14274 | if (!need_vex) | |
14275 | abort (); | |
14276 | ||
14277 | if (!vex.evex) | |
14278 | { | |
14279 | if (vex.w) | |
14280 | oappend ("QWORD PTR "); | |
14281 | else | |
14282 | oappend ("DWORD PTR "); | |
14283 | } | |
14284 | else | |
14285 | { | |
b28d1bda IT |
14286 | switch (vex.length) |
14287 | { | |
14288 | case 128: | |
14289 | oappend ("XMMWORD PTR "); | |
14290 | break; | |
14291 | case 256: | |
14292 | oappend ("YMMWORD PTR "); | |
14293 | break; | |
14294 | case 512: | |
14295 | oappend ("ZMMWORD PTR "); | |
14296 | break; | |
14297 | default: | |
14298 | abort (); | |
14299 | } | |
43234a1e L |
14300 | } |
14301 | break; | |
5fc35d96 IT |
14302 | case vex_vsib_q_w_d_mode: |
14303 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14304 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14305 | abort (); |
14306 | ||
b28d1bda IT |
14307 | switch (vex.length) |
14308 | { | |
14309 | case 128: | |
14310 | oappend ("QWORD PTR "); | |
14311 | break; | |
14312 | case 256: | |
14313 | oappend ("XMMWORD PTR "); | |
14314 | break; | |
14315 | case 512: | |
14316 | oappend ("YMMWORD PTR "); | |
14317 | break; | |
14318 | default: | |
14319 | abort (); | |
14320 | } | |
5fc35d96 IT |
14321 | |
14322 | break; | |
1ba585e8 IT |
14323 | case mask_bd_mode: |
14324 | if (!need_vex || vex.length != 128) | |
14325 | abort (); | |
14326 | if (vex.w) | |
14327 | oappend ("DWORD PTR "); | |
14328 | else | |
14329 | oappend ("BYTE PTR "); | |
14330 | break; | |
43234a1e L |
14331 | case mask_mode: |
14332 | if (!need_vex) | |
14333 | abort (); | |
1ba585e8 IT |
14334 | if (vex.w) |
14335 | oappend ("QWORD PTR "); | |
14336 | else | |
14337 | oappend ("WORD PTR "); | |
43234a1e | 14338 | break; |
6c75cc62 | 14339 | case v_bnd_mode: |
d276ec69 | 14340 | case v_bndmk_mode: |
3f31e633 JB |
14341 | default: |
14342 | break; | |
14343 | } | |
14344 | } | |
14345 | ||
252b5132 | 14346 | static void |
c0f3af97 | 14347 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14348 | { |
c0f3af97 L |
14349 | int reg = modrm.rm; |
14350 | const char **names; | |
252b5132 | 14351 | |
c0f3af97 L |
14352 | USED_REX (REX_B); |
14353 | if ((rex & REX_B)) | |
14354 | reg += 8; | |
252b5132 | 14355 | |
b6169b20 | 14356 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 14357 | && (bytemode == b_swap_mode |
9f79e886 | 14358 | || bytemode == bnd_swap_mode |
60227d64 | 14359 | || bytemode == v_swap_mode)) |
b6169b20 L |
14360 | swap_operand (); |
14361 | ||
c0f3af97 | 14362 | switch (bytemode) |
252b5132 | 14363 | { |
c0f3af97 | 14364 | case b_mode: |
b6169b20 | 14365 | case b_swap_mode: |
e184e611 JB |
14366 | if (reg & 4) |
14367 | USED_REX (0); | |
c0f3af97 L |
14368 | if (rex) |
14369 | names = names8rex; | |
14370 | else | |
14371 | names = names8; | |
14372 | break; | |
14373 | case w_mode: | |
14374 | names = names16; | |
14375 | break; | |
14376 | case d_mode: | |
1ba585e8 IT |
14377 | case dw_mode: |
14378 | case db_mode: | |
c0f3af97 L |
14379 | names = names32; |
14380 | break; | |
14381 | case q_mode: | |
14382 | names = names64; | |
14383 | break; | |
14384 | case m_mode: | |
6c75cc62 | 14385 | case v_bnd_mode: |
c0f3af97 L |
14386 | names = address_mode == mode_64bit ? names64 : names32; |
14387 | break; | |
7e8b059b | 14388 | case bnd_mode: |
9f79e886 | 14389 | case bnd_swap_mode: |
0d96e4df L |
14390 | if (reg > 0x3) |
14391 | { | |
14392 | oappend ("(bad)"); | |
14393 | return; | |
14394 | } | |
7e8b059b L |
14395 | names = names_bnd; |
14396 | break; | |
07f5af7d L |
14397 | case indir_v_mode: |
14398 | if (address_mode == mode_64bit && isa64 == intel64) | |
14399 | { | |
14400 | names = names64; | |
14401 | break; | |
14402 | } | |
1a0670f3 | 14403 | /* Fall through. */ |
c0f3af97 | 14404 | case stack_v_mode: |
7bb15c6f | 14405 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14406 | { |
c0f3af97 | 14407 | names = names64; |
252b5132 | 14408 | break; |
252b5132 | 14409 | } |
c0f3af97 | 14410 | bytemode = v_mode; |
1a0670f3 | 14411 | /* Fall through. */ |
c0f3af97 | 14412 | case v_mode: |
b6169b20 | 14413 | case v_swap_mode: |
c0f3af97 L |
14414 | case dq_mode: |
14415 | case dqb_mode: | |
14416 | case dqd_mode: | |
14417 | case dqw_mode: | |
14418 | USED_REX (REX_W); | |
14419 | if (rex & REX_W) | |
14420 | names = names64; | |
c0f3af97 | 14421 | else |
f16cd0d5 | 14422 | { |
7bb15c6f | 14423 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14424 | || (bytemode != v_mode |
14425 | && bytemode != v_swap_mode)) | |
14426 | names = names32; | |
14427 | else | |
14428 | names = names16; | |
14429 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14430 | } | |
c0f3af97 | 14431 | break; |
bc31405e L |
14432 | case movsxd_mode: |
14433 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14434 | names = names16; | |
14435 | else | |
14436 | names = names32; | |
14437 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14438 | break; | |
de89d0a3 IT |
14439 | case va_mode: |
14440 | names = (address_mode == mode_64bit | |
14441 | ? names64 : names32); | |
14442 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
14443 | names = (address_mode == mode_16bit |
14444 | ? names16 : names); | |
de89d0a3 IT |
14445 | else |
14446 | { | |
14447 | /* Remove "addr16/addr32". */ | |
14448 | all_prefixes[last_addr_prefix] = 0; | |
14449 | names = (address_mode != mode_32bit | |
14450 | ? names32 : names16); | |
14451 | used_prefixes |= PREFIX_ADDR; | |
14452 | } | |
14453 | break; | |
1ba585e8 | 14454 | case mask_bd_mode: |
43234a1e | 14455 | case mask_mode: |
9889cbb1 L |
14456 | if (reg > 0x7) |
14457 | { | |
14458 | oappend ("(bad)"); | |
14459 | return; | |
14460 | } | |
43234a1e L |
14461 | names = names_mask; |
14462 | break; | |
c0f3af97 L |
14463 | case 0: |
14464 | return; | |
14465 | default: | |
14466 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14467 | return; |
14468 | } | |
c0f3af97 L |
14469 | oappend (names[reg]); |
14470 | } | |
14471 | ||
14472 | static void | |
c1e679ec | 14473 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14474 | { |
14475 | bfd_vma disp = 0; | |
14476 | int add = (rex & REX_B) ? 8 : 0; | |
14477 | int riprel = 0; | |
43234a1e L |
14478 | int shift; |
14479 | ||
14480 | if (vex.evex) | |
14481 | { | |
14482 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14483 | if (vex.b | |
14484 | && bytemode != x_mode | |
90a915bf | 14485 | && bytemode != xmmq_mode |
43234a1e L |
14486 | && bytemode != evex_half_bcst_xmmq_mode) |
14487 | { | |
14488 | BadOp (); | |
14489 | return; | |
14490 | } | |
14491 | switch (bytemode) | |
14492 | { | |
1ba585e8 IT |
14493 | case dqw_mode: |
14494 | case dw_mode: | |
059edf8b | 14495 | case xmm_mw_mode: |
1ba585e8 IT |
14496 | shift = 1; |
14497 | break; | |
14498 | case dqb_mode: | |
14499 | case db_mode: | |
059edf8b | 14500 | case xmm_mb_mode: |
1ba585e8 IT |
14501 | shift = 0; |
14502 | break; | |
b50c9f31 JB |
14503 | case dq_mode: |
14504 | if (address_mode != mode_64bit) | |
14505 | { | |
059edf8b JB |
14506 | case dqd_mode: |
14507 | case xmm_md_mode: | |
14508 | case d_mode: | |
14509 | case d_swap_mode: | |
b50c9f31 JB |
14510 | shift = 2; |
14511 | break; | |
14512 | } | |
14513 | /* fall through */ | |
4102be5c | 14514 | case vex_scalar_w_dq_mode: |
43234a1e | 14515 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14516 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14517 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14518 | case vex_vsib_q_w_d_mode: |
43234a1e | 14519 | case evex_x_gscat_mode: |
43234a1e L |
14520 | shift = vex.w ? 3 : 2; |
14521 | break; | |
43234a1e L |
14522 | case x_mode: |
14523 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14524 | case xmmq_mode: |
43234a1e L |
14525 | if (vex.b) |
14526 | { | |
14527 | shift = vex.w ? 3 : 2; | |
14528 | break; | |
14529 | } | |
1a0670f3 | 14530 | /* Fall through. */ |
43234a1e L |
14531 | case xmmqd_mode: |
14532 | case xmmdw_mode: | |
43234a1e L |
14533 | case ymmq_mode: |
14534 | case evex_x_nobcst_mode: | |
14535 | case x_swap_mode: | |
14536 | switch (vex.length) | |
14537 | { | |
14538 | case 128: | |
14539 | shift = 4; | |
14540 | break; | |
14541 | case 256: | |
14542 | shift = 5; | |
14543 | break; | |
14544 | case 512: | |
14545 | shift = 6; | |
14546 | break; | |
14547 | default: | |
14548 | abort (); | |
14549 | } | |
059edf8b JB |
14550 | /* Make necessary corrections to shift for modes that need it. */ |
14551 | if (bytemode == xmmq_mode | |
14552 | || bytemode == evex_half_bcst_xmmq_mode | |
14553 | || (bytemode == ymmq_mode && vex.length == 128)) | |
14554 | shift -= 1; | |
14555 | else if (bytemode == xmmqd_mode) | |
14556 | shift -= 2; | |
14557 | else if (bytemode == xmmdw_mode) | |
14558 | shift -= 3; | |
43234a1e L |
14559 | break; |
14560 | case ymm_mode: | |
14561 | shift = 5; | |
14562 | break; | |
14563 | case xmm_mode: | |
14564 | shift = 4; | |
14565 | break; | |
14566 | case xmm_mq_mode: | |
14567 | case q_mode: | |
43234a1e | 14568 | case q_swap_mode: |
43234a1e L |
14569 | shift = 3; |
14570 | break; | |
4726e9a4 JB |
14571 | case bw_unit_mode: |
14572 | shift = vex.w ? 1 : 0; | |
14573 | break; | |
43234a1e L |
14574 | default: |
14575 | abort (); | |
14576 | } | |
43234a1e L |
14577 | } |
14578 | else | |
14579 | shift = 0; | |
252b5132 | 14580 | |
c0f3af97 | 14581 | USED_REX (REX_B); |
3f31e633 JB |
14582 | if (intel_syntax) |
14583 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14584 | append_seg (); |
14585 | ||
5d669648 | 14586 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14587 | { |
5d669648 L |
14588 | /* 32/64 bit address mode */ |
14589 | int havedisp; | |
252b5132 RH |
14590 | int havesib; |
14591 | int havebase; | |
0f7da397 | 14592 | int haveindex; |
20afcfb7 | 14593 | int needindex; |
1bc60e56 | 14594 | int needaddr32; |
82c18208 | 14595 | int base, rbase; |
91d6fa6a | 14596 | int vindex = 0; |
252b5132 | 14597 | int scale = 0; |
7e8b059b L |
14598 | int addr32flag = !((sizeflag & AFLAG) |
14599 | || bytemode == v_bnd_mode | |
d276ec69 | 14600 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14601 | || bytemode == bnd_mode |
14602 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14603 | const char **indexes64 = names64; |
14604 | const char **indexes32 = names32; | |
252b5132 RH |
14605 | |
14606 | havesib = 0; | |
14607 | havebase = 1; | |
0f7da397 | 14608 | haveindex = 0; |
7967e09e | 14609 | base = modrm.rm; |
252b5132 RH |
14610 | |
14611 | if (base == 4) | |
14612 | { | |
14613 | havesib = 1; | |
dfc8cf43 | 14614 | vindex = sib.index; |
161a04f6 L |
14615 | USED_REX (REX_X); |
14616 | if (rex & REX_X) | |
91d6fa6a | 14617 | vindex += 8; |
6c30d220 L |
14618 | switch (bytemode) |
14619 | { | |
14620 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14621 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14622 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14623 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14624 | if (!need_vex) |
14625 | abort (); | |
43234a1e L |
14626 | if (vex.evex) |
14627 | { | |
14628 | if (!vex.v) | |
14629 | vindex += 16; | |
14630 | } | |
6c30d220 L |
14631 | |
14632 | haveindex = 1; | |
14633 | switch (vex.length) | |
14634 | { | |
14635 | case 128: | |
7bb15c6f | 14636 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14637 | break; |
14638 | case 256: | |
5fc35d96 IT |
14639 | if (!vex.w |
14640 | || bytemode == vex_vsib_q_w_dq_mode | |
14641 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14642 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14643 | else |
7bb15c6f | 14644 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14645 | break; |
43234a1e | 14646 | case 512: |
5fc35d96 IT |
14647 | if (!vex.w |
14648 | || bytemode == vex_vsib_q_w_dq_mode | |
14649 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14650 | indexes64 = indexes32 = names_zmm; |
14651 | else | |
14652 | indexes64 = indexes32 = names_ymm; | |
14653 | break; | |
6c30d220 L |
14654 | default: |
14655 | abort (); | |
14656 | } | |
14657 | break; | |
14658 | default: | |
14659 | haveindex = vindex != 4; | |
14660 | break; | |
14661 | } | |
14662 | scale = sib.scale; | |
14663 | base = sib.base; | |
252b5132 RH |
14664 | codep++; |
14665 | } | |
260cd341 LC |
14666 | else |
14667 | { | |
14668 | /* mandatory non-vector SIB must have sib */ | |
14669 | if (bytemode == vex_sibmem_mode) | |
14670 | { | |
14671 | oappend ("(bad)"); | |
14672 | return; | |
14673 | } | |
14674 | } | |
82c18208 | 14675 | rbase = base + add; |
252b5132 | 14676 | |
7967e09e | 14677 | switch (modrm.mod) |
252b5132 RH |
14678 | { |
14679 | case 0: | |
82c18208 | 14680 | if (base == 5) |
252b5132 RH |
14681 | { |
14682 | havebase = 0; | |
cb712a9e | 14683 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14684 | riprel = 1; |
14685 | disp = get32s (); | |
d276ec69 JB |
14686 | if (riprel && bytemode == v_bndmk_mode) |
14687 | { | |
14688 | oappend ("(bad)"); | |
14689 | return; | |
14690 | } | |
252b5132 RH |
14691 | } |
14692 | break; | |
14693 | case 1: | |
14694 | FETCH_DATA (the_info, codep + 1); | |
14695 | disp = *codep++; | |
14696 | if ((disp & 0x80) != 0) | |
14697 | disp -= 0x100; | |
43234a1e L |
14698 | if (vex.evex && shift > 0) |
14699 | disp <<= shift; | |
252b5132 RH |
14700 | break; |
14701 | case 2: | |
52b15da3 | 14702 | disp = get32s (); |
252b5132 RH |
14703 | break; |
14704 | } | |
14705 | ||
1bc60e56 L |
14706 | needindex = 0; |
14707 | needaddr32 = 0; | |
14708 | if (havesib | |
14709 | && !havebase | |
14710 | && !haveindex | |
14711 | && address_mode != mode_16bit) | |
14712 | { | |
14713 | if (address_mode == mode_64bit) | |
14714 | { | |
14715 | /* Display eiz instead of addr32. */ | |
14716 | needindex = addr32flag; | |
14717 | needaddr32 = 1; | |
14718 | } | |
14719 | else | |
14720 | { | |
14721 | /* In 32-bit mode, we need index register to tell [offset] | |
14722 | from [eiz*1 + offset]. */ | |
14723 | needindex = 1; | |
14724 | } | |
14725 | } | |
14726 | ||
20afcfb7 L |
14727 | havedisp = (havebase |
14728 | || needindex | |
14729 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14730 | |
252b5132 | 14731 | if (!intel_syntax) |
82c18208 | 14732 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14733 | { |
5d669648 L |
14734 | if (havedisp || riprel) |
14735 | print_displacement (scratchbuf, disp); | |
14736 | else | |
14737 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14738 | oappend (scratchbuf); |
52b15da3 JH |
14739 | if (riprel) |
14740 | { | |
14741 | set_op (disp, 1); | |
28596323 | 14742 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14743 | } |
db6eb5be | 14744 | } |
2da11e11 | 14745 | |
c1dc7af5 | 14746 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14747 | && (address_mode != mode_64bit |
14748 | || ((bytemode != v_bnd_mode) | |
14749 | && (bytemode != v_bndmk_mode) | |
14750 | && (bytemode != bnd_mode) | |
14751 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14752 | used_prefixes |= PREFIX_ADDR; |
14753 | ||
5d669648 | 14754 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14755 | { |
252b5132 | 14756 | *obufp++ = open_char; |
52b15da3 | 14757 | if (intel_syntax && riprel) |
185b1163 L |
14758 | { |
14759 | set_op (disp, 1); | |
28596323 | 14760 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14761 | } |
db6eb5be | 14762 | *obufp = '\0'; |
252b5132 | 14763 | if (havebase) |
7e8b059b | 14764 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14765 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14766 | if (havesib) |
14767 | { | |
db51cc60 L |
14768 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14769 | print index to tell base + index from base. */ | |
14770 | if (scale != 0 | |
20afcfb7 | 14771 | || needindex |
db51cc60 L |
14772 | || haveindex |
14773 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14774 | { |
9306ca4a | 14775 | if (!intel_syntax || havebase) |
db6eb5be | 14776 | { |
9306ca4a JB |
14777 | *obufp++ = separator_char; |
14778 | *obufp = '\0'; | |
db6eb5be | 14779 | } |
db51cc60 | 14780 | if (haveindex) |
7e8b059b | 14781 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14782 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14783 | else |
7e8b059b | 14784 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14785 | ? index64 : index32); |
14786 | ||
db6eb5be AM |
14787 | *obufp++ = scale_char; |
14788 | *obufp = '\0'; | |
14789 | sprintf (scratchbuf, "%d", 1 << scale); | |
14790 | oappend (scratchbuf); | |
14791 | } | |
252b5132 | 14792 | } |
185b1163 | 14793 | if (intel_syntax |
82c18208 | 14794 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14795 | { |
db51cc60 | 14796 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14797 | { |
14798 | *obufp++ = '+'; | |
14799 | *obufp = '\0'; | |
14800 | } | |
05203043 | 14801 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14802 | { |
14803 | *obufp++ = '-'; | |
14804 | *obufp = '\0'; | |
14805 | disp = - (bfd_signed_vma) disp; | |
14806 | } | |
14807 | ||
db51cc60 L |
14808 | if (havedisp) |
14809 | print_displacement (scratchbuf, disp); | |
14810 | else | |
14811 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14812 | oappend (scratchbuf); |
14813 | } | |
252b5132 RH |
14814 | |
14815 | *obufp++ = close_char; | |
db6eb5be | 14816 | *obufp = '\0'; |
252b5132 RH |
14817 | } |
14818 | else if (intel_syntax) | |
db6eb5be | 14819 | { |
82c18208 | 14820 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14821 | { |
285ca992 | 14822 | if (!active_seg_prefix) |
252b5132 | 14823 | { |
d708bcba | 14824 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14825 | oappend (":"); |
14826 | } | |
52b15da3 | 14827 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14828 | oappend (scratchbuf); |
14829 | } | |
14830 | } | |
252b5132 | 14831 | } |
a23b33b3 JB |
14832 | else if (bytemode == v_bnd_mode |
14833 | || bytemode == v_bndmk_mode | |
14834 | || bytemode == bnd_mode | |
14835 | || bytemode == bnd_swap_mode) | |
14836 | { | |
14837 | oappend ("(bad)"); | |
14838 | return; | |
14839 | } | |
252b5132 | 14840 | else |
f16cd0d5 L |
14841 | { |
14842 | /* 16 bit address mode */ | |
14843 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14844 | switch (modrm.mod) |
252b5132 RH |
14845 | { |
14846 | case 0: | |
7967e09e | 14847 | if (modrm.rm == 6) |
252b5132 RH |
14848 | { |
14849 | disp = get16 (); | |
14850 | if ((disp & 0x8000) != 0) | |
14851 | disp -= 0x10000; | |
14852 | } | |
14853 | break; | |
14854 | case 1: | |
14855 | FETCH_DATA (the_info, codep + 1); | |
14856 | disp = *codep++; | |
14857 | if ((disp & 0x80) != 0) | |
14858 | disp -= 0x100; | |
65f3ed04 JB |
14859 | if (vex.evex && shift > 0) |
14860 | disp <<= shift; | |
252b5132 RH |
14861 | break; |
14862 | case 2: | |
14863 | disp = get16 (); | |
14864 | if ((disp & 0x8000) != 0) | |
14865 | disp -= 0x10000; | |
14866 | break; | |
14867 | } | |
14868 | ||
14869 | if (!intel_syntax) | |
7967e09e | 14870 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14871 | { |
5d669648 | 14872 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14873 | oappend (scratchbuf); |
14874 | } | |
252b5132 | 14875 | |
7967e09e | 14876 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14877 | { |
14878 | *obufp++ = open_char; | |
db6eb5be | 14879 | *obufp = '\0'; |
7967e09e | 14880 | oappend (index16[modrm.rm]); |
5d669648 L |
14881 | if (intel_syntax |
14882 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14883 | { |
5d669648 | 14884 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14885 | { |
14886 | *obufp++ = '+'; | |
14887 | *obufp = '\0'; | |
14888 | } | |
7967e09e | 14889 | else if (modrm.mod != 1) |
3d456fa1 JB |
14890 | { |
14891 | *obufp++ = '-'; | |
14892 | *obufp = '\0'; | |
14893 | disp = - (bfd_signed_vma) disp; | |
14894 | } | |
14895 | ||
5d669648 | 14896 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14897 | oappend (scratchbuf); |
14898 | } | |
14899 | ||
db6eb5be AM |
14900 | *obufp++ = close_char; |
14901 | *obufp = '\0'; | |
252b5132 | 14902 | } |
3d456fa1 JB |
14903 | else if (intel_syntax) |
14904 | { | |
285ca992 | 14905 | if (!active_seg_prefix) |
3d456fa1 JB |
14906 | { |
14907 | oappend (names_seg[ds_reg - es_reg]); | |
14908 | oappend (":"); | |
14909 | } | |
14910 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14911 | oappend (scratchbuf); | |
14912 | } | |
252b5132 | 14913 | } |
43234a1e L |
14914 | if (vex.evex && vex.b |
14915 | && (bytemode == x_mode | |
90a915bf | 14916 | || bytemode == xmmq_mode |
43234a1e L |
14917 | || bytemode == evex_half_bcst_xmmq_mode)) |
14918 | { | |
90a915bf IT |
14919 | if (vex.w |
14920 | || bytemode == xmmq_mode | |
14921 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14922 | { |
14923 | switch (vex.length) | |
14924 | { | |
14925 | case 128: | |
14926 | oappend ("{1to2}"); | |
14927 | break; | |
14928 | case 256: | |
14929 | oappend ("{1to4}"); | |
14930 | break; | |
14931 | case 512: | |
14932 | oappend ("{1to8}"); | |
14933 | break; | |
14934 | default: | |
14935 | abort (); | |
14936 | } | |
14937 | } | |
43234a1e | 14938 | else |
b28d1bda IT |
14939 | { |
14940 | switch (vex.length) | |
14941 | { | |
14942 | case 128: | |
14943 | oappend ("{1to4}"); | |
14944 | break; | |
14945 | case 256: | |
14946 | oappend ("{1to8}"); | |
14947 | break; | |
14948 | case 512: | |
14949 | oappend ("{1to16}"); | |
14950 | break; | |
14951 | default: | |
14952 | abort (); | |
14953 | } | |
14954 | } | |
43234a1e | 14955 | } |
252b5132 RH |
14956 | } |
14957 | ||
c0f3af97 | 14958 | static void |
8b3f93e7 | 14959 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14960 | { |
14961 | /* Skip mod/rm byte. */ | |
14962 | MODRM_CHECK; | |
14963 | codep++; | |
14964 | ||
14965 | if (modrm.mod == 3) | |
14966 | OP_E_register (bytemode, sizeflag); | |
14967 | else | |
c1e679ec | 14968 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14969 | } |
14970 | ||
252b5132 | 14971 | static void |
26ca5450 | 14972 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14973 | { |
52b15da3 | 14974 | int add = 0; |
c0a30a9f | 14975 | const char **names; |
161a04f6 L |
14976 | USED_REX (REX_R); |
14977 | if (rex & REX_R) | |
52b15da3 | 14978 | add += 8; |
252b5132 RH |
14979 | switch (bytemode) |
14980 | { | |
14981 | case b_mode: | |
e184e611 JB |
14982 | if (modrm.reg & 4) |
14983 | USED_REX (0); | |
52b15da3 | 14984 | if (rex) |
7967e09e | 14985 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14986 | else |
7967e09e | 14987 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14988 | break; |
14989 | case w_mode: | |
7967e09e | 14990 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14991 | break; |
14992 | case d_mode: | |
1ba585e8 IT |
14993 | case db_mode: |
14994 | case dw_mode: | |
7967e09e | 14995 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14996 | break; |
14997 | case q_mode: | |
7967e09e | 14998 | oappend (names64[modrm.reg + add]); |
252b5132 | 14999 | break; |
7e8b059b | 15000 | case bnd_mode: |
0d96e4df L |
15001 | if (modrm.reg > 0x3) |
15002 | { | |
15003 | oappend ("(bad)"); | |
15004 | return; | |
15005 | } | |
7e8b059b L |
15006 | oappend (names_bnd[modrm.reg]); |
15007 | break; | |
252b5132 | 15008 | case v_mode: |
9306ca4a | 15009 | case dq_mode: |
42903f7f L |
15010 | case dqb_mode: |
15011 | case dqd_mode: | |
9306ca4a | 15012 | case dqw_mode: |
bc31405e | 15013 | case movsxd_mode: |
161a04f6 L |
15014 | USED_REX (REX_W); |
15015 | if (rex & REX_W) | |
7967e09e | 15016 | oappend (names64[modrm.reg + add]); |
252b5132 | 15017 | else |
f16cd0d5 | 15018 | { |
bc31405e L |
15019 | if ((sizeflag & DFLAG) |
15020 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
15021 | oappend (names32[modrm.reg + add]); |
15022 | else | |
15023 | oappend (names16[modrm.reg + add]); | |
15024 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15025 | } | |
252b5132 | 15026 | break; |
c0a30a9f L |
15027 | case va_mode: |
15028 | names = (address_mode == mode_64bit | |
15029 | ? names64 : names32); | |
15030 | if (!(prefixes & PREFIX_ADDR)) | |
15031 | { | |
15032 | if (address_mode == mode_16bit) | |
15033 | names = names16; | |
15034 | } | |
15035 | else | |
15036 | { | |
15037 | /* Remove "addr16/addr32". */ | |
15038 | all_prefixes[last_addr_prefix] = 0; | |
15039 | names = (address_mode != mode_32bit | |
15040 | ? names32 : names16); | |
15041 | used_prefixes |= PREFIX_ADDR; | |
15042 | } | |
15043 | oappend (names[modrm.reg + add]); | |
15044 | break; | |
90700ea2 | 15045 | case m_mode: |
cb712a9e | 15046 | if (address_mode == mode_64bit) |
7967e09e | 15047 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15048 | else |
7967e09e | 15049 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15050 | break; |
1ba585e8 | 15051 | case mask_bd_mode: |
43234a1e | 15052 | case mask_mode: |
9889cbb1 L |
15053 | if ((modrm.reg + add) > 0x7) |
15054 | { | |
15055 | oappend ("(bad)"); | |
15056 | return; | |
15057 | } | |
43234a1e L |
15058 | oappend (names_mask[modrm.reg + add]); |
15059 | break; | |
252b5132 RH |
15060 | default: |
15061 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15062 | break; | |
15063 | } | |
15064 | } | |
15065 | ||
52b15da3 | 15066 | static bfd_vma |
26ca5450 | 15067 | get64 (void) |
52b15da3 | 15068 | { |
5dd0794d | 15069 | bfd_vma x; |
52b15da3 | 15070 | #ifdef BFD64 |
5dd0794d AM |
15071 | unsigned int a; |
15072 | unsigned int b; | |
15073 | ||
52b15da3 JH |
15074 | FETCH_DATA (the_info, codep + 8); |
15075 | a = *codep++ & 0xff; | |
15076 | a |= (*codep++ & 0xff) << 8; | |
15077 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15078 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15079 | b = *codep++ & 0xff; |
52b15da3 JH |
15080 | b |= (*codep++ & 0xff) << 8; |
15081 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15082 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15083 | x = a + ((bfd_vma) b << 32); |
15084 | #else | |
6608db57 | 15085 | abort (); |
5dd0794d | 15086 | x = 0; |
52b15da3 JH |
15087 | #endif |
15088 | return x; | |
15089 | } | |
15090 | ||
15091 | static bfd_signed_vma | |
26ca5450 | 15092 | get32 (void) |
252b5132 | 15093 | { |
52b15da3 | 15094 | bfd_signed_vma x = 0; |
252b5132 RH |
15095 | |
15096 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15097 | x = *codep++ & (bfd_signed_vma) 0xff; |
15098 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15099 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15100 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15101 | return x; | |
15102 | } | |
15103 | ||
15104 | static bfd_signed_vma | |
26ca5450 | 15105 | get32s (void) |
52b15da3 JH |
15106 | { |
15107 | bfd_signed_vma x = 0; | |
15108 | ||
15109 | FETCH_DATA (the_info, codep + 4); | |
15110 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15111 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15112 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15113 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15114 | ||
15115 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15116 | ||
252b5132 RH |
15117 | return x; |
15118 | } | |
15119 | ||
15120 | static int | |
26ca5450 | 15121 | get16 (void) |
252b5132 RH |
15122 | { |
15123 | int x = 0; | |
15124 | ||
15125 | FETCH_DATA (the_info, codep + 2); | |
15126 | x = *codep++ & 0xff; | |
15127 | x |= (*codep++ & 0xff) << 8; | |
15128 | return x; | |
15129 | } | |
15130 | ||
15131 | static void | |
26ca5450 | 15132 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15133 | { |
15134 | op_index[op_ad] = op_ad; | |
cb712a9e | 15135 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15136 | { |
15137 | op_address[op_ad] = op; | |
15138 | op_riprel[op_ad] = riprel; | |
15139 | } | |
15140 | else | |
15141 | { | |
15142 | /* Mask to get a 32-bit address. */ | |
15143 | op_address[op_ad] = op & 0xffffffff; | |
15144 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15145 | } | |
252b5132 RH |
15146 | } |
15147 | ||
15148 | static void | |
26ca5450 | 15149 | OP_REG (int code, int sizeflag) |
252b5132 | 15150 | { |
2da11e11 | 15151 | const char *s; |
9b60702d | 15152 | int add; |
de882298 RM |
15153 | |
15154 | switch (code) | |
15155 | { | |
15156 | case es_reg: case ss_reg: case cs_reg: | |
15157 | case ds_reg: case fs_reg: case gs_reg: | |
15158 | oappend (names_seg[code - es_reg]); | |
15159 | return; | |
15160 | } | |
15161 | ||
161a04f6 L |
15162 | USED_REX (REX_B); |
15163 | if (rex & REX_B) | |
52b15da3 | 15164 | add = 8; |
9b60702d L |
15165 | else |
15166 | add = 0; | |
52b15da3 JH |
15167 | |
15168 | switch (code) | |
15169 | { | |
52b15da3 JH |
15170 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15171 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15172 | s = names16[code - ax_reg + add]; | |
15173 | break; | |
e184e611 | 15174 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 15175 | USED_REX (0); |
e184e611 JB |
15176 | /* Fall through. */ |
15177 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
52b15da3 JH |
15178 | if (rex) |
15179 | s = names8rex[code - al_reg + add]; | |
15180 | else | |
15181 | s = names8[code - al_reg]; | |
15182 | break; | |
6439fc28 AM |
15183 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15184 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15185 | if (address_mode == mode_64bit |
6c067bbb | 15186 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15187 | { |
15188 | s = names64[code - rAX_reg + add]; | |
15189 | break; | |
15190 | } | |
15191 | code += eAX_reg - rAX_reg; | |
6608db57 | 15192 | /* Fall through. */ |
52b15da3 JH |
15193 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15194 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15195 | USED_REX (REX_W); |
15196 | if (rex & REX_W) | |
52b15da3 | 15197 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15198 | else |
f16cd0d5 L |
15199 | { |
15200 | if (sizeflag & DFLAG) | |
15201 | s = names32[code - eAX_reg + add]; | |
15202 | else | |
15203 | s = names16[code - eAX_reg + add]; | |
15204 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15205 | } | |
52b15da3 | 15206 | break; |
52b15da3 JH |
15207 | default: |
15208 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15209 | break; | |
15210 | } | |
15211 | oappend (s); | |
15212 | } | |
15213 | ||
15214 | static void | |
26ca5450 | 15215 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15216 | { |
15217 | const char *s; | |
252b5132 RH |
15218 | |
15219 | switch (code) | |
15220 | { | |
15221 | case indir_dx_reg: | |
d708bcba | 15222 | if (intel_syntax) |
52fd6d94 | 15223 | s = "dx"; |
d708bcba | 15224 | else |
db6eb5be | 15225 | s = "(%dx)"; |
252b5132 | 15226 | break; |
e8b5d5f9 JB |
15227 | case al_reg: case cl_reg: |
15228 | s = names8[code - al_reg]; | |
252b5132 | 15229 | break; |
e8b5d5f9 | 15230 | case eAX_reg: |
161a04f6 L |
15231 | USED_REX (REX_W); |
15232 | if (rex & REX_W) | |
f16cd0d5 | 15233 | { |
e8b5d5f9 JB |
15234 | s = *names64; |
15235 | break; | |
f16cd0d5 | 15236 | } |
e8b5d5f9 | 15237 | /* Fall through. */ |
52fd6d94 | 15238 | case z_mode_ax_reg: |
161a04f6 | 15239 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15240 | s = *names32; |
15241 | else | |
15242 | s = *names16; | |
161a04f6 | 15243 | if (!(rex & REX_W)) |
52fd6d94 JB |
15244 | used_prefixes |= (prefixes & PREFIX_DATA); |
15245 | break; | |
252b5132 RH |
15246 | default: |
15247 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15248 | break; | |
15249 | } | |
15250 | oappend (s); | |
15251 | } | |
15252 | ||
15253 | static void | |
26ca5450 | 15254 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15255 | { |
52b15da3 JH |
15256 | bfd_signed_vma op; |
15257 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15258 | |
15259 | switch (bytemode) | |
15260 | { | |
15261 | case b_mode: | |
15262 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15263 | op = *codep++; |
15264 | mask = 0xff; | |
15265 | break; | |
252b5132 | 15266 | case v_mode: |
161a04f6 L |
15267 | USED_REX (REX_W); |
15268 | if (rex & REX_W) | |
52b15da3 | 15269 | op = get32s (); |
252b5132 | 15270 | else |
52b15da3 | 15271 | { |
f16cd0d5 L |
15272 | if (sizeflag & DFLAG) |
15273 | { | |
15274 | op = get32 (); | |
15275 | mask = 0xffffffff; | |
15276 | } | |
15277 | else | |
15278 | { | |
15279 | op = get16 (); | |
15280 | mask = 0xfffff; | |
15281 | } | |
15282 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15283 | } |
252b5132 | 15284 | break; |
c1dc7af5 JB |
15285 | case d_mode: |
15286 | mask = 0xffffffff; | |
15287 | op = get32 (); | |
15288 | break; | |
252b5132 | 15289 | case w_mode: |
52b15da3 | 15290 | mask = 0xfffff; |
252b5132 RH |
15291 | op = get16 (); |
15292 | break; | |
9306ca4a JB |
15293 | case const_1_mode: |
15294 | if (intel_syntax) | |
6c067bbb | 15295 | oappend ("1"); |
9306ca4a | 15296 | return; |
252b5132 RH |
15297 | default: |
15298 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15299 | return; | |
15300 | } | |
15301 | ||
52b15da3 JH |
15302 | op &= mask; |
15303 | scratchbuf[0] = '$'; | |
d708bcba | 15304 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15305 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15306 | scratchbuf[0] = '\0'; |
15307 | } | |
15308 | ||
15309 | static void | |
26ca5450 | 15310 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 15311 | { |
a280ab8e | 15312 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
15313 | { |
15314 | OP_I (bytemode, sizeflag); | |
15315 | return; | |
15316 | } | |
15317 | ||
a280ab8e | 15318 | USED_REX (REX_W); |
52b15da3 | 15319 | |
52b15da3 | 15320 | scratchbuf[0] = '$'; |
a280ab8e | 15321 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 15322 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15323 | scratchbuf[0] = '\0'; |
15324 | } | |
15325 | ||
15326 | static void | |
26ca5450 | 15327 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15328 | { |
52b15da3 | 15329 | bfd_signed_vma op; |
252b5132 RH |
15330 | |
15331 | switch (bytemode) | |
15332 | { | |
15333 | case b_mode: | |
e3949f17 | 15334 | case b_T_mode: |
252b5132 RH |
15335 | FETCH_DATA (the_info, codep + 1); |
15336 | op = *codep++; | |
15337 | if ((op & 0x80) != 0) | |
15338 | op -= 0x100; | |
e3949f17 L |
15339 | if (bytemode == b_T_mode) |
15340 | { | |
15341 | if (address_mode != mode_64bit | |
7bb15c6f | 15342 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15343 | { |
6c067bbb RM |
15344 | /* The operand-size prefix is overridden by a REX prefix. */ |
15345 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15346 | op &= 0xffffffff; |
15347 | else | |
15348 | op &= 0xffff; | |
15349 | } | |
15350 | } | |
15351 | else | |
15352 | { | |
15353 | if (!(rex & REX_W)) | |
15354 | { | |
15355 | if (sizeflag & DFLAG) | |
15356 | op &= 0xffffffff; | |
15357 | else | |
15358 | op &= 0xffff; | |
15359 | } | |
15360 | } | |
252b5132 RH |
15361 | break; |
15362 | case v_mode: | |
7bb15c6f RM |
15363 | /* The operand-size prefix is overridden by a REX prefix. */ |
15364 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15365 | op = get32s (); |
252b5132 | 15366 | else |
d9e3625e | 15367 | op = get16 (); |
252b5132 RH |
15368 | break; |
15369 | default: | |
15370 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15371 | return; | |
15372 | } | |
52b15da3 JH |
15373 | |
15374 | scratchbuf[0] = '$'; | |
15375 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15376 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15377 | } |
15378 | ||
15379 | static void | |
26ca5450 | 15380 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15381 | { |
52b15da3 | 15382 | bfd_vma disp; |
7081ff04 | 15383 | bfd_vma mask = -1; |
65ca155d | 15384 | bfd_vma segment = 0; |
252b5132 RH |
15385 | |
15386 | switch (bytemode) | |
15387 | { | |
15388 | case b_mode: | |
15389 | FETCH_DATA (the_info, codep + 1); | |
15390 | disp = *codep++; | |
15391 | if ((disp & 0x80) != 0) | |
15392 | disp -= 0x100; | |
15393 | break; | |
15394 | case v_mode: | |
d835a58b | 15395 | if (isa64 != intel64) |
376cd056 | 15396 | case dqw_mode: |
5db04b09 L |
15397 | USED_REX (REX_W); |
15398 | if ((sizeflag & DFLAG) | |
15399 | || (address_mode == mode_64bit | |
d835a58b | 15400 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 15401 | || (rex & REX_W)))) |
52b15da3 | 15402 | disp = get32s (); |
252b5132 RH |
15403 | else |
15404 | { | |
15405 | disp = get16 (); | |
206717e8 L |
15406 | if ((disp & 0x8000) != 0) |
15407 | disp -= 0x10000; | |
65ca155d L |
15408 | /* In 16bit mode, address is wrapped around at 64k within |
15409 | the same segment. Otherwise, a data16 prefix on a jump | |
15410 | instruction means that the pc is masked to 16 bits after | |
15411 | the displacement is added! */ | |
15412 | mask = 0xffff; | |
15413 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 15414 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 15415 | & ~((bfd_vma) 0xffff)); |
252b5132 | 15416 | } |
5db04b09 | 15417 | if (address_mode != mode_64bit |
d835a58b | 15418 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 15419 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
15420 | break; |
15421 | default: | |
15422 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15423 | return; | |
15424 | } | |
42d5f9c6 | 15425 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15426 | set_op (disp, 0); |
15427 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15428 | oappend (scratchbuf); |
15429 | } | |
15430 | ||
252b5132 | 15431 | static void |
ed7841b3 | 15432 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15433 | { |
ed7841b3 | 15434 | if (bytemode == w_mode) |
7967e09e | 15435 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15436 | else |
7967e09e | 15437 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15438 | } |
15439 | ||
15440 | static void | |
26ca5450 | 15441 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15442 | { |
15443 | int seg, offset; | |
15444 | ||
c608c12e | 15445 | if (sizeflag & DFLAG) |
252b5132 | 15446 | { |
c608c12e AM |
15447 | offset = get32 (); |
15448 | seg = get16 (); | |
252b5132 | 15449 | } |
c608c12e AM |
15450 | else |
15451 | { | |
15452 | offset = get16 (); | |
15453 | seg = get16 (); | |
15454 | } | |
7d421014 | 15455 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15456 | if (intel_syntax) |
3f31e633 | 15457 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15458 | else |
15459 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15460 | oappend (scratchbuf); |
252b5132 RH |
15461 | } |
15462 | ||
252b5132 | 15463 | static void |
3f31e633 | 15464 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15465 | { |
52b15da3 | 15466 | bfd_vma off; |
252b5132 | 15467 | |
3f31e633 JB |
15468 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15469 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15470 | append_seg (); |
15471 | ||
cb712a9e | 15472 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15473 | off = get32 (); |
15474 | else | |
15475 | off = get16 (); | |
15476 | ||
15477 | if (intel_syntax) | |
15478 | { | |
285ca992 | 15479 | if (!active_seg_prefix) |
252b5132 | 15480 | { |
d708bcba | 15481 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15482 | oappend (":"); |
15483 | } | |
15484 | } | |
52b15da3 JH |
15485 | print_operand_value (scratchbuf, 1, off); |
15486 | oappend (scratchbuf); | |
15487 | } | |
6439fc28 | 15488 | |
52b15da3 | 15489 | static void |
3f31e633 | 15490 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15491 | { |
15492 | bfd_vma off; | |
15493 | ||
539e75ad L |
15494 | if (address_mode != mode_64bit |
15495 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15496 | { |
15497 | OP_OFF (bytemode, sizeflag); | |
15498 | return; | |
15499 | } | |
15500 | ||
3f31e633 JB |
15501 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15502 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15503 | append_seg (); |
15504 | ||
6608db57 | 15505 | off = get64 (); |
52b15da3 JH |
15506 | |
15507 | if (intel_syntax) | |
15508 | { | |
285ca992 | 15509 | if (!active_seg_prefix) |
52b15da3 | 15510 | { |
d708bcba | 15511 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15512 | oappend (":"); |
15513 | } | |
15514 | } | |
15515 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15516 | oappend (scratchbuf); |
15517 | } | |
15518 | ||
15519 | static void | |
26ca5450 | 15520 | ptr_reg (int code, int sizeflag) |
252b5132 | 15521 | { |
2da11e11 | 15522 | const char *s; |
d708bcba | 15523 | |
1d9f512f | 15524 | *obufp++ = open_char; |
20f0a1fc | 15525 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15526 | if (address_mode == mode_64bit) |
c1a64871 JH |
15527 | { |
15528 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15529 | s = names32[code - eAX_reg]; |
c1a64871 | 15530 | else |
db6eb5be | 15531 | s = names64[code - eAX_reg]; |
c1a64871 | 15532 | } |
52b15da3 | 15533 | else if (sizeflag & AFLAG) |
252b5132 RH |
15534 | s = names32[code - eAX_reg]; |
15535 | else | |
15536 | s = names16[code - eAX_reg]; | |
15537 | oappend (s); | |
1d9f512f AM |
15538 | *obufp++ = close_char; |
15539 | *obufp = 0; | |
252b5132 RH |
15540 | } |
15541 | ||
15542 | static void | |
26ca5450 | 15543 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15544 | { |
9306ca4a | 15545 | if (intel_syntax) |
52fd6d94 JB |
15546 | { |
15547 | switch (codep[-1]) | |
15548 | { | |
15549 | case 0x6d: /* insw/insl */ | |
15550 | intel_operand_size (z_mode, sizeflag); | |
15551 | break; | |
15552 | case 0xa5: /* movsw/movsl/movsq */ | |
15553 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15554 | case 0xab: /* stosw/stosl */ | |
15555 | case 0xaf: /* scasw/scasl */ | |
15556 | intel_operand_size (v_mode, sizeflag); | |
15557 | break; | |
15558 | default: | |
15559 | intel_operand_size (b_mode, sizeflag); | |
15560 | } | |
15561 | } | |
9ce09ba2 | 15562 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15563 | ptr_reg (code, sizeflag); |
15564 | } | |
15565 | ||
15566 | static void | |
26ca5450 | 15567 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15568 | { |
9306ca4a | 15569 | if (intel_syntax) |
52fd6d94 JB |
15570 | { |
15571 | switch (codep[-1]) | |
15572 | { | |
15573 | case 0x6f: /* outsw/outsl */ | |
15574 | intel_operand_size (z_mode, sizeflag); | |
15575 | break; | |
15576 | case 0xa5: /* movsw/movsl/movsq */ | |
15577 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15578 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15579 | intel_operand_size (v_mode, sizeflag); | |
15580 | break; | |
15581 | default: | |
15582 | intel_operand_size (b_mode, sizeflag); | |
15583 | } | |
15584 | } | |
285ca992 L |
15585 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15586 | default segment register DS is printed. */ | |
15587 | if (!active_seg_prefix) | |
15588 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15589 | append_seg (); |
252b5132 RH |
15590 | ptr_reg (code, sizeflag); |
15591 | } | |
15592 | ||
252b5132 | 15593 | static void |
26ca5450 | 15594 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15595 | { |
9b60702d | 15596 | int add; |
161a04f6 | 15597 | if (rex & REX_R) |
c4a530c5 | 15598 | { |
161a04f6 | 15599 | USED_REX (REX_R); |
c4a530c5 JB |
15600 | add = 8; |
15601 | } | |
cb712a9e | 15602 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15603 | { |
f16cd0d5 | 15604 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15605 | used_prefixes |= PREFIX_LOCK; |
15606 | add = 8; | |
15607 | } | |
9b60702d L |
15608 | else |
15609 | add = 0; | |
7967e09e | 15610 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15611 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15612 | } |
15613 | ||
252b5132 | 15614 | static void |
26ca5450 | 15615 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15616 | { |
9b60702d | 15617 | int add; |
161a04f6 L |
15618 | USED_REX (REX_R); |
15619 | if (rex & REX_R) | |
52b15da3 | 15620 | add = 8; |
9b60702d L |
15621 | else |
15622 | add = 0; | |
d708bcba | 15623 | if (intel_syntax) |
7967e09e | 15624 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15625 | else |
7967e09e | 15626 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15627 | oappend (scratchbuf); |
15628 | } | |
15629 | ||
252b5132 | 15630 | static void |
26ca5450 | 15631 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15632 | { |
7967e09e | 15633 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15634 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15635 | } |
15636 | ||
15637 | static void | |
6f74c397 | 15638 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15639 | { |
68f34464 L |
15640 | /* Skip mod/rm byte. */ |
15641 | MODRM_CHECK; | |
15642 | codep++; | |
15643 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15644 | } |
15645 | ||
15646 | static void | |
26ca5450 | 15647 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15648 | { |
b9733481 L |
15649 | int reg = modrm.reg; |
15650 | const char **names; | |
15651 | ||
041bd2e0 JH |
15652 | used_prefixes |= (prefixes & PREFIX_DATA); |
15653 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15654 | { |
b9733481 | 15655 | names = names_xmm; |
161a04f6 L |
15656 | USED_REX (REX_R); |
15657 | if (rex & REX_R) | |
b9733481 | 15658 | reg += 8; |
20f0a1fc | 15659 | } |
041bd2e0 | 15660 | else |
b9733481 L |
15661 | names = names_mm; |
15662 | oappend (names[reg]); | |
252b5132 RH |
15663 | } |
15664 | ||
c608c12e | 15665 | static void |
c0f3af97 | 15666 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15667 | { |
b9733481 L |
15668 | int reg = modrm.reg; |
15669 | const char **names; | |
15670 | ||
161a04f6 L |
15671 | USED_REX (REX_R); |
15672 | if (rex & REX_R) | |
b9733481 | 15673 | reg += 8; |
43234a1e L |
15674 | if (vex.evex) |
15675 | { | |
15676 | if (!vex.r) | |
15677 | reg += 16; | |
15678 | } | |
15679 | ||
539f890d L |
15680 | if (need_vex |
15681 | && bytemode != xmm_mode | |
43234a1e L |
15682 | && bytemode != xmmq_mode |
15683 | && bytemode != evex_half_bcst_xmmq_mode | |
15684 | && bytemode != ymm_mode | |
260cd341 | 15685 | && bytemode != tmm_mode |
539f890d | 15686 | && bytemode != scalar_mode) |
c0f3af97 L |
15687 | { |
15688 | switch (vex.length) | |
15689 | { | |
15690 | case 128: | |
b9733481 | 15691 | names = names_xmm; |
c0f3af97 L |
15692 | break; |
15693 | case 256: | |
5fc35d96 IT |
15694 | if (vex.w |
15695 | || (bytemode != vex_vsib_q_w_dq_mode | |
15696 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15697 | names = names_ymm; |
15698 | else | |
15699 | names = names_xmm; | |
c0f3af97 | 15700 | break; |
43234a1e L |
15701 | case 512: |
15702 | names = names_zmm; | |
15703 | break; | |
c0f3af97 L |
15704 | default: |
15705 | abort (); | |
15706 | } | |
15707 | } | |
43234a1e L |
15708 | else if (bytemode == xmmq_mode |
15709 | || bytemode == evex_half_bcst_xmmq_mode) | |
15710 | { | |
15711 | switch (vex.length) | |
15712 | { | |
15713 | case 128: | |
15714 | case 256: | |
15715 | names = names_xmm; | |
15716 | break; | |
15717 | case 512: | |
15718 | names = names_ymm; | |
15719 | break; | |
15720 | default: | |
15721 | abort (); | |
15722 | } | |
15723 | } | |
260cd341 LC |
15724 | else if (bytemode == tmm_mode) |
15725 | { | |
15726 | modrm.reg = reg; | |
15727 | if (reg >= 8) | |
15728 | { | |
15729 | oappend ("(bad)"); | |
15730 | return; | |
15731 | } | |
15732 | names = names_tmm; | |
15733 | } | |
43234a1e L |
15734 | else if (bytemode == ymm_mode) |
15735 | names = names_ymm; | |
c0f3af97 | 15736 | else |
b9733481 L |
15737 | names = names_xmm; |
15738 | oappend (names[reg]); | |
c608c12e AM |
15739 | } |
15740 | ||
252b5132 | 15741 | static void |
26ca5450 | 15742 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15743 | { |
b9733481 L |
15744 | int reg; |
15745 | const char **names; | |
15746 | ||
7967e09e | 15747 | if (modrm.mod != 3) |
252b5132 | 15748 | { |
b6169b20 L |
15749 | if (intel_syntax |
15750 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15751 | { |
15752 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15753 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15754 | } |
252b5132 RH |
15755 | OP_E (bytemode, sizeflag); |
15756 | return; | |
15757 | } | |
15758 | ||
b6169b20 L |
15759 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15760 | swap_operand (); | |
15761 | ||
6608db57 | 15762 | /* Skip mod/rm byte. */ |
4bba6815 | 15763 | MODRM_CHECK; |
252b5132 | 15764 | codep++; |
041bd2e0 | 15765 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15766 | reg = modrm.rm; |
041bd2e0 | 15767 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15768 | { |
b9733481 | 15769 | names = names_xmm; |
161a04f6 L |
15770 | USED_REX (REX_B); |
15771 | if (rex & REX_B) | |
b9733481 | 15772 | reg += 8; |
20f0a1fc | 15773 | } |
041bd2e0 | 15774 | else |
b9733481 L |
15775 | names = names_mm; |
15776 | oappend (names[reg]); | |
252b5132 RH |
15777 | } |
15778 | ||
246c51aa L |
15779 | /* cvt* are the only instructions in sse2 which have |
15780 | both SSE and MMX operands and also have 0x66 prefix | |
15781 | in their opcode. 0x66 was originally used to differentiate | |
15782 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15783 | cvt* separately using OP_EMC and OP_MXC */ |
15784 | static void | |
15785 | OP_EMC (int bytemode, int sizeflag) | |
15786 | { | |
7967e09e | 15787 | if (modrm.mod != 3) |
4d9567e0 MM |
15788 | { |
15789 | if (intel_syntax && bytemode == v_mode) | |
15790 | { | |
15791 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15792 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15793 | } |
4d9567e0 MM |
15794 | OP_E (bytemode, sizeflag); |
15795 | return; | |
15796 | } | |
246c51aa | 15797 | |
4d9567e0 MM |
15798 | /* Skip mod/rm byte. */ |
15799 | MODRM_CHECK; | |
15800 | codep++; | |
15801 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15802 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15803 | } |
15804 | ||
15805 | static void | |
15806 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15807 | { | |
15808 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15809 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15810 | } |
15811 | ||
c608c12e | 15812 | static void |
26ca5450 | 15813 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15814 | { |
b9733481 L |
15815 | int reg; |
15816 | const char **names; | |
d6f574e0 L |
15817 | |
15818 | /* Skip mod/rm byte. */ | |
15819 | MODRM_CHECK; | |
15820 | codep++; | |
15821 | ||
7967e09e | 15822 | if (modrm.mod != 3) |
c608c12e | 15823 | { |
c1e679ec | 15824 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15825 | return; |
15826 | } | |
d6f574e0 | 15827 | |
b9733481 | 15828 | reg = modrm.rm; |
161a04f6 L |
15829 | USED_REX (REX_B); |
15830 | if (rex & REX_B) | |
b9733481 | 15831 | reg += 8; |
43234a1e L |
15832 | if (vex.evex) |
15833 | { | |
15834 | USED_REX (REX_X); | |
15835 | if ((rex & REX_X)) | |
15836 | reg += 16; | |
15837 | } | |
c608c12e | 15838 | |
b6169b20 | 15839 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15840 | && (bytemode == x_swap_mode |
15841 | || bytemode == d_swap_mode | |
41f5efc6 | 15842 | || bytemode == q_swap_mode)) |
b6169b20 L |
15843 | swap_operand (); |
15844 | ||
c0f3af97 L |
15845 | if (need_vex |
15846 | && bytemode != xmm_mode | |
6c30d220 L |
15847 | && bytemode != xmmdw_mode |
15848 | && bytemode != xmmqd_mode | |
15849 | && bytemode != xmm_mb_mode | |
15850 | && bytemode != xmm_mw_mode | |
15851 | && bytemode != xmm_md_mode | |
15852 | && bytemode != xmm_mq_mode | |
539f890d | 15853 | && bytemode != xmmq_mode |
43234a1e L |
15854 | && bytemode != evex_half_bcst_xmmq_mode |
15855 | && bytemode != ymm_mode | |
260cd341 | 15856 | && bytemode != tmm_mode |
1c480963 | 15857 | && bytemode != vex_scalar_w_dq_mode) |
c0f3af97 L |
15858 | { |
15859 | switch (vex.length) | |
15860 | { | |
15861 | case 128: | |
b9733481 | 15862 | names = names_xmm; |
c0f3af97 L |
15863 | break; |
15864 | case 256: | |
b9733481 | 15865 | names = names_ymm; |
c0f3af97 | 15866 | break; |
43234a1e L |
15867 | case 512: |
15868 | names = names_zmm; | |
15869 | break; | |
c0f3af97 L |
15870 | default: |
15871 | abort (); | |
15872 | } | |
15873 | } | |
43234a1e L |
15874 | else if (bytemode == xmmq_mode |
15875 | || bytemode == evex_half_bcst_xmmq_mode) | |
15876 | { | |
15877 | switch (vex.length) | |
15878 | { | |
15879 | case 128: | |
15880 | case 256: | |
15881 | names = names_xmm; | |
15882 | break; | |
15883 | case 512: | |
15884 | names = names_ymm; | |
15885 | break; | |
15886 | default: | |
15887 | abort (); | |
15888 | } | |
15889 | } | |
260cd341 LC |
15890 | else if (bytemode == tmm_mode) |
15891 | { | |
15892 | modrm.rm = reg; | |
15893 | if (reg >= 8) | |
15894 | { | |
15895 | oappend ("(bad)"); | |
15896 | return; | |
15897 | } | |
15898 | names = names_tmm; | |
15899 | } | |
43234a1e L |
15900 | else if (bytemode == ymm_mode) |
15901 | names = names_ymm; | |
c0f3af97 | 15902 | else |
b9733481 L |
15903 | names = names_xmm; |
15904 | oappend (names[reg]); | |
c608c12e AM |
15905 | } |
15906 | ||
252b5132 | 15907 | static void |
26ca5450 | 15908 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15909 | { |
7967e09e | 15910 | if (modrm.mod == 3) |
2da11e11 AM |
15911 | OP_EM (bytemode, sizeflag); |
15912 | else | |
6608db57 | 15913 | BadOp (); |
252b5132 RH |
15914 | } |
15915 | ||
992aaec9 | 15916 | static void |
26ca5450 | 15917 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15918 | { |
7967e09e | 15919 | if (modrm.mod == 3) |
992aaec9 AM |
15920 | OP_EX (bytemode, sizeflag); |
15921 | else | |
6608db57 | 15922 | BadOp (); |
992aaec9 AM |
15923 | } |
15924 | ||
cc0ec051 AM |
15925 | static void |
15926 | OP_M (int bytemode, int sizeflag) | |
15927 | { | |
7967e09e | 15928 | if (modrm.mod == 3) |
75413a22 L |
15929 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15930 | BadOp (); | |
cc0ec051 AM |
15931 | else |
15932 | OP_E (bytemode, sizeflag); | |
15933 | } | |
15934 | ||
15935 | static void | |
15936 | OP_0f07 (int bytemode, int sizeflag) | |
15937 | { | |
7967e09e | 15938 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15939 | BadOp (); |
15940 | else | |
15941 | OP_E (bytemode, sizeflag); | |
15942 | } | |
15943 | ||
46e883c5 | 15944 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15945 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15946 | |
cc0ec051 | 15947 | static void |
46e883c5 | 15948 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15949 | { |
8b38ad71 L |
15950 | if ((prefixes & PREFIX_DATA) != 0 |
15951 | || (rex != 0 | |
15952 | && rex != 0x48 | |
15953 | && address_mode == mode_64bit)) | |
46e883c5 L |
15954 | OP_REG (bytemode, sizeflag); |
15955 | else | |
15956 | strcpy (obuf, "nop"); | |
15957 | } | |
15958 | ||
15959 | static void | |
15960 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15961 | { | |
8b38ad71 L |
15962 | if ((prefixes & PREFIX_DATA) != 0 |
15963 | || (rex != 0 | |
15964 | && rex != 0x48 | |
15965 | && address_mode == mode_64bit)) | |
46e883c5 | 15966 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15967 | } |
15968 | ||
84037f8c | 15969 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15970 | /* 00 */ NULL, NULL, NULL, NULL, |
15971 | /* 04 */ NULL, NULL, NULL, NULL, | |
15972 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15973 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15974 | /* 10 */ NULL, NULL, NULL, NULL, |
15975 | /* 14 */ NULL, NULL, NULL, NULL, | |
15976 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15977 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15978 | /* 20 */ NULL, NULL, NULL, NULL, |
15979 | /* 24 */ NULL, NULL, NULL, NULL, | |
15980 | /* 28 */ NULL, NULL, NULL, NULL, | |
15981 | /* 2C */ NULL, NULL, NULL, NULL, | |
15982 | /* 30 */ NULL, NULL, NULL, NULL, | |
15983 | /* 34 */ NULL, NULL, NULL, NULL, | |
15984 | /* 38 */ NULL, NULL, NULL, NULL, | |
15985 | /* 3C */ NULL, NULL, NULL, NULL, | |
15986 | /* 40 */ NULL, NULL, NULL, NULL, | |
15987 | /* 44 */ NULL, NULL, NULL, NULL, | |
15988 | /* 48 */ NULL, NULL, NULL, NULL, | |
15989 | /* 4C */ NULL, NULL, NULL, NULL, | |
15990 | /* 50 */ NULL, NULL, NULL, NULL, | |
15991 | /* 54 */ NULL, NULL, NULL, NULL, | |
15992 | /* 58 */ NULL, NULL, NULL, NULL, | |
15993 | /* 5C */ NULL, NULL, NULL, NULL, | |
15994 | /* 60 */ NULL, NULL, NULL, NULL, | |
15995 | /* 64 */ NULL, NULL, NULL, NULL, | |
15996 | /* 68 */ NULL, NULL, NULL, NULL, | |
15997 | /* 6C */ NULL, NULL, NULL, NULL, | |
15998 | /* 70 */ NULL, NULL, NULL, NULL, | |
15999 | /* 74 */ NULL, NULL, NULL, NULL, | |
16000 | /* 78 */ NULL, NULL, NULL, NULL, | |
16001 | /* 7C */ NULL, NULL, NULL, NULL, | |
16002 | /* 80 */ NULL, NULL, NULL, NULL, | |
16003 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16004 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16005 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16006 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16007 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16008 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16009 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16010 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16011 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16012 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16013 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16014 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16015 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16016 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16017 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16018 | /* C0 */ NULL, NULL, NULL, NULL, | |
16019 | /* C4 */ NULL, NULL, NULL, NULL, | |
16020 | /* C8 */ NULL, NULL, NULL, NULL, | |
16021 | /* CC */ NULL, NULL, NULL, NULL, | |
16022 | /* D0 */ NULL, NULL, NULL, NULL, | |
16023 | /* D4 */ NULL, NULL, NULL, NULL, | |
16024 | /* D8 */ NULL, NULL, NULL, NULL, | |
16025 | /* DC */ NULL, NULL, NULL, NULL, | |
16026 | /* E0 */ NULL, NULL, NULL, NULL, | |
16027 | /* E4 */ NULL, NULL, NULL, NULL, | |
16028 | /* E8 */ NULL, NULL, NULL, NULL, | |
16029 | /* EC */ NULL, NULL, NULL, NULL, | |
16030 | /* F0 */ NULL, NULL, NULL, NULL, | |
16031 | /* F4 */ NULL, NULL, NULL, NULL, | |
16032 | /* F8 */ NULL, NULL, NULL, NULL, | |
16033 | /* FC */ NULL, NULL, NULL, NULL, | |
16034 | }; | |
16035 | ||
16036 | static void | |
26ca5450 | 16037 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16038 | { |
16039 | const char *mnemonic; | |
16040 | ||
16041 | FETCH_DATA (the_info, codep + 1); | |
16042 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16043 | place where an 8-bit immediate would normally go. ie. the last | |
16044 | byte of the instruction. */ | |
ea397f5b | 16045 | obufp = mnemonicendp; |
c608c12e | 16046 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16047 | if (mnemonic) |
2da11e11 | 16048 | oappend (mnemonic); |
252b5132 RH |
16049 | else |
16050 | { | |
16051 | /* Since a variable sized modrm/sib chunk is between the start | |
16052 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16053 | all the modrm processing first, and don't know until now that | |
16054 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16055 | op_out[0][0] = '\0'; |
16056 | op_out[1][0] = '\0'; | |
6608db57 | 16057 | BadOp (); |
252b5132 | 16058 | } |
ea397f5b | 16059 | mnemonicendp = obufp; |
252b5132 | 16060 | } |
c608c12e | 16061 | |
c4de7606 | 16062 | static const struct op simd_cmp_op[] = |
ea397f5b L |
16063 | { |
16064 | { STRING_COMMA_LEN ("eq") }, | |
16065 | { STRING_COMMA_LEN ("lt") }, | |
16066 | { STRING_COMMA_LEN ("le") }, | |
16067 | { STRING_COMMA_LEN ("unord") }, | |
16068 | { STRING_COMMA_LEN ("neq") }, | |
16069 | { STRING_COMMA_LEN ("nlt") }, | |
16070 | { STRING_COMMA_LEN ("nle") }, | |
16071 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16072 | }; |
16073 | ||
c4de7606 JB |
16074 | static const struct op vex_cmp_op[] = |
16075 | { | |
16076 | { STRING_COMMA_LEN ("eq_uq") }, | |
16077 | { STRING_COMMA_LEN ("nge") }, | |
16078 | { STRING_COMMA_LEN ("ngt") }, | |
16079 | { STRING_COMMA_LEN ("false") }, | |
16080 | { STRING_COMMA_LEN ("neq_oq") }, | |
16081 | { STRING_COMMA_LEN ("ge") }, | |
16082 | { STRING_COMMA_LEN ("gt") }, | |
16083 | { STRING_COMMA_LEN ("true") }, | |
16084 | { STRING_COMMA_LEN ("eq_os") }, | |
16085 | { STRING_COMMA_LEN ("lt_oq") }, | |
16086 | { STRING_COMMA_LEN ("le_oq") }, | |
16087 | { STRING_COMMA_LEN ("unord_s") }, | |
16088 | { STRING_COMMA_LEN ("neq_us") }, | |
16089 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16090 | { STRING_COMMA_LEN ("nle_uq") }, | |
16091 | { STRING_COMMA_LEN ("ord_s") }, | |
16092 | { STRING_COMMA_LEN ("eq_us") }, | |
16093 | { STRING_COMMA_LEN ("nge_uq") }, | |
16094 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16095 | { STRING_COMMA_LEN ("false_os") }, | |
16096 | { STRING_COMMA_LEN ("neq_os") }, | |
16097 | { STRING_COMMA_LEN ("ge_oq") }, | |
16098 | { STRING_COMMA_LEN ("gt_oq") }, | |
16099 | { STRING_COMMA_LEN ("true_us") }, | |
16100 | }; | |
16101 | ||
c608c12e | 16102 | static void |
ad19981d | 16103 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16104 | { |
16105 | unsigned int cmp_type; | |
16106 | ||
16107 | FETCH_DATA (the_info, codep + 1); | |
16108 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16109 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16110 | { |
ad19981d | 16111 | char suffix [3]; |
ea397f5b | 16112 | char *p = mnemonicendp - 2; |
ad19981d L |
16113 | suffix[0] = p[0]; |
16114 | suffix[1] = p[1]; | |
16115 | suffix[2] = '\0'; | |
ea397f5b L |
16116 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16117 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e | 16118 | } |
c4de7606 JB |
16119 | else if (need_vex |
16120 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) | |
16121 | { | |
16122 | char suffix [3]; | |
16123 | char *p = mnemonicendp - 2; | |
16124 | suffix[0] = p[0]; | |
16125 | suffix[1] = p[1]; | |
16126 | suffix[2] = '\0'; | |
16127 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
16128 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
16129 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
16130 | } | |
c608c12e AM |
16131 | else |
16132 | { | |
ad19981d L |
16133 | /* We have a reserved extension byte. Output it directly. */ |
16134 | scratchbuf[0] = '$'; | |
16135 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16136 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16137 | scratchbuf[0] = '\0'; |
c608c12e AM |
16138 | } |
16139 | } | |
16140 | ||
9916071f | 16141 | static void |
7abb8d81 | 16142 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 16143 | { |
7abb8d81 | 16144 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
16145 | if (!intel_syntax) |
16146 | { | |
081e283f JB |
16147 | strcpy (op_out[0], names32[0]); |
16148 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 16149 | if (bytemode == eBX_reg) |
081e283f | 16150 | strcpy (op_out[2], names32[3]); |
b844680a L |
16151 | two_source_ops = 1; |
16152 | } | |
16153 | /* Skip mod/rm byte. */ | |
16154 | MODRM_CHECK; | |
16155 | codep++; | |
16156 | } | |
16157 | ||
16158 | static void | |
16159 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16160 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16161 | { |
081e283f | 16162 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 16163 | if (!intel_syntax) |
ca164297 | 16164 | { |
cb712a9e L |
16165 | const char **names = (address_mode == mode_64bit |
16166 | ? names64 : names32); | |
1d9f512f | 16167 | |
081e283f | 16168 | if (prefixes & PREFIX_ADDR) |
ca164297 | 16169 | { |
b844680a | 16170 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16171 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
16172 | names = (address_mode != mode_32bit |
16173 | ? names32 : names16); | |
b844680a | 16174 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 16175 | } |
081e283f JB |
16176 | else if (address_mode == mode_16bit) |
16177 | names = names16; | |
16178 | strcpy (op_out[0], names[0]); | |
16179 | strcpy (op_out[1], names32[1]); | |
16180 | strcpy (op_out[2], names32[2]); | |
b844680a | 16181 | two_source_ops = 1; |
ca164297 | 16182 | } |
b844680a L |
16183 | /* Skip mod/rm byte. */ |
16184 | MODRM_CHECK; | |
16185 | codep++; | |
30123838 JB |
16186 | } |
16187 | ||
6608db57 KH |
16188 | static void |
16189 | BadOp (void) | |
2da11e11 | 16190 | { |
6608db57 KH |
16191 | /* Throw away prefixes and 1st. opcode byte. */ |
16192 | codep = insn_codep + 1; | |
2da11e11 AM |
16193 | oappend ("(bad)"); |
16194 | } | |
4cc91dba | 16195 | |
35c52694 L |
16196 | static void |
16197 | REP_Fixup (int bytemode, int sizeflag) | |
16198 | { | |
16199 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16200 | lods and stos. */ | |
35c52694 | 16201 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16202 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16203 | |
16204 | switch (bytemode) | |
16205 | { | |
16206 | case al_reg: | |
16207 | case eAX_reg: | |
16208 | case indir_dx_reg: | |
16209 | OP_IMREG (bytemode, sizeflag); | |
16210 | break; | |
16211 | case eDI_reg: | |
16212 | OP_ESreg (bytemode, sizeflag); | |
16213 | break; | |
16214 | case eSI_reg: | |
16215 | OP_DSreg (bytemode, sizeflag); | |
16216 | break; | |
16217 | default: | |
16218 | abort (); | |
16219 | break; | |
16220 | } | |
16221 | } | |
f5804c90 | 16222 | |
d835a58b JB |
16223 | static void |
16224 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16225 | { | |
16226 | if ( isa64 != amd64 ) | |
16227 | return; | |
16228 | ||
16229 | obufp = obuf; | |
16230 | BadOp (); | |
16231 | mnemonicendp = obufp; | |
16232 | ++codep; | |
16233 | } | |
16234 | ||
7e8b059b L |
16235 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16236 | "bnd". */ | |
16237 | ||
16238 | static void | |
16239 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16240 | { | |
16241 | if (prefixes & PREFIX_REPNZ) | |
16242 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16243 | } | |
16244 | ||
04ef582a L |
16245 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16246 | "notrack". */ | |
16247 | ||
16248 | static void | |
16249 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16250 | int sizeflag ATTRIBUTE_UNUSED) | |
16251 | { | |
9fef80d6 | 16252 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16253 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16254 | { | |
4e9ac44a | 16255 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16256 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16257 | active_seg_prefix = 0; |
16258 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16259 | } | |
16260 | } | |
16261 | ||
42164a71 L |
16262 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16263 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16264 | */ | |
16265 | ||
16266 | static void | |
16267 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16268 | { | |
16269 | if (modrm.mod != 3 | |
16270 | && (prefixes & PREFIX_LOCK) != 0) | |
16271 | { | |
16272 | if (prefixes & PREFIX_REPZ) | |
16273 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16274 | if (prefixes & PREFIX_REPNZ) | |
16275 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16276 | } | |
16277 | ||
16278 | OP_E (bytemode, sizeflag); | |
16279 | } | |
16280 | ||
16281 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16282 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16283 | */ | |
16284 | ||
16285 | static void | |
16286 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16287 | { | |
16288 | if (modrm.mod != 3) | |
16289 | { | |
16290 | if (prefixes & PREFIX_REPZ) | |
16291 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16292 | if (prefixes & PREFIX_REPNZ) | |
16293 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16294 | } | |
16295 | ||
16296 | OP_E (bytemode, sizeflag); | |
16297 | } | |
16298 | ||
16299 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16300 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16301 | ||
16302 | static void | |
16303 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16304 | { | |
16305 | if (modrm.mod != 3 | |
16306 | && last_repz_prefix > last_repnz_prefix | |
16307 | && (prefixes & PREFIX_REPZ) != 0) | |
16308 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16309 | ||
16310 | OP_E (bytemode, sizeflag); | |
16311 | } | |
16312 | ||
f5804c90 L |
16313 | static void |
16314 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16315 | { | |
161a04f6 L |
16316 | USED_REX (REX_W); |
16317 | if (rex & REX_W) | |
f5804c90 L |
16318 | { |
16319 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16320 | char *p = mnemonicendp - 2; |
16321 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16322 | bytemode = o_mode; |
f5804c90 | 16323 | } |
42164a71 L |
16324 | else if ((prefixes & PREFIX_LOCK) != 0) |
16325 | { | |
16326 | if (prefixes & PREFIX_REPZ) | |
16327 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16328 | if (prefixes & PREFIX_REPNZ) | |
16329 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16330 | } | |
16331 | ||
f5804c90 L |
16332 | OP_M (bytemode, sizeflag); |
16333 | } | |
42903f7f L |
16334 | |
16335 | static void | |
16336 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16337 | { | |
b9733481 L |
16338 | const char **names; |
16339 | ||
c0f3af97 L |
16340 | if (need_vex) |
16341 | { | |
16342 | switch (vex.length) | |
16343 | { | |
16344 | case 128: | |
b9733481 | 16345 | names = names_xmm; |
c0f3af97 L |
16346 | break; |
16347 | case 256: | |
b9733481 | 16348 | names = names_ymm; |
c0f3af97 L |
16349 | break; |
16350 | default: | |
16351 | abort (); | |
16352 | } | |
16353 | } | |
16354 | else | |
b9733481 L |
16355 | names = names_xmm; |
16356 | oappend (names[reg]); | |
42903f7f | 16357 | } |
381d071f L |
16358 | |
16359 | static void | |
eacc9c89 L |
16360 | FXSAVE_Fixup (int bytemode, int sizeflag) |
16361 | { | |
16362 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16363 | USED_REX (REX_W); | |
16364 | if (rex & REX_W) | |
16365 | { | |
16366 | char *p = mnemonicendp; | |
16367 | *p++ = '6'; | |
16368 | *p++ = '4'; | |
16369 | *p = '\0'; | |
16370 | mnemonicendp = p; | |
16371 | } | |
16372 | OP_M (bytemode, sizeflag); | |
15c7c1d8 JB |
16373 | } |
16374 | ||
c0f3af97 L |
16375 | /* Display the destination register operand for instructions with |
16376 | VEX. */ | |
16377 | ||
16378 | static void | |
16379 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16380 | { | |
539f890d | 16381 | int reg; |
b9733481 L |
16382 | const char **names; |
16383 | ||
c0f3af97 L |
16384 | if (!need_vex) |
16385 | abort (); | |
16386 | ||
539f890d | 16387 | reg = vex.register_specifier; |
63c6fc6c | 16388 | vex.register_specifier = 0; |
5f847646 JB |
16389 | if (address_mode != mode_64bit) |
16390 | reg &= 7; | |
16391 | else if (vex.evex && !vex.v) | |
16392 | reg += 16; | |
43234a1e | 16393 | |
539f890d L |
16394 | if (bytemode == vex_scalar_mode) |
16395 | { | |
16396 | oappend (names_xmm[reg]); | |
16397 | return; | |
16398 | } | |
16399 | ||
260cd341 LC |
16400 | if (bytemode == tmm_mode) |
16401 | { | |
16402 | /* All 3 TMM registers must be distinct. */ | |
16403 | if (reg >= 8) | |
16404 | oappend ("(bad)"); | |
16405 | else | |
16406 | { | |
16407 | /* This must be the 3rd operand. */ | |
16408 | if (obufp != op_out[2]) | |
16409 | abort (); | |
16410 | oappend (names_tmm[reg]); | |
16411 | if (reg == modrm.reg || reg == modrm.rm) | |
16412 | strcpy (obufp, "/(bad)"); | |
16413 | } | |
16414 | ||
16415 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
16416 | { | |
16417 | if (modrm.reg <= 8 | |
16418 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
16419 | strcat (op_out[0], "/(bad)"); | |
16420 | if (modrm.rm <= 8 | |
16421 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
16422 | strcat (op_out[1], "/(bad)"); | |
16423 | } | |
16424 | ||
16425 | return; | |
16426 | } | |
16427 | ||
c0f3af97 L |
16428 | switch (vex.length) |
16429 | { | |
16430 | case 128: | |
16431 | switch (bytemode) | |
16432 | { | |
16433 | case vex_mode: | |
6c30d220 | 16434 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16435 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16436 | names = names_xmm; |
16437 | break; | |
16438 | case dq_mode: | |
390a6789 | 16439 | if (rex & REX_W) |
cb21baef L |
16440 | names = names64; |
16441 | else | |
16442 | names = names32; | |
c0f3af97 | 16443 | break; |
1ba585e8 | 16444 | case mask_bd_mode: |
43234a1e | 16445 | case mask_mode: |
9889cbb1 L |
16446 | if (reg > 0x7) |
16447 | { | |
16448 | oappend ("(bad)"); | |
16449 | return; | |
16450 | } | |
43234a1e L |
16451 | names = names_mask; |
16452 | break; | |
c0f3af97 L |
16453 | default: |
16454 | abort (); | |
16455 | return; | |
16456 | } | |
c0f3af97 L |
16457 | break; |
16458 | case 256: | |
16459 | switch (bytemode) | |
16460 | { | |
16461 | case vex_mode: | |
6c30d220 L |
16462 | names = names_ymm; |
16463 | break; | |
16464 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16465 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16466 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16467 | break; |
1ba585e8 | 16468 | case mask_bd_mode: |
43234a1e | 16469 | case mask_mode: |
9889cbb1 L |
16470 | if (reg > 0x7) |
16471 | { | |
16472 | oappend ("(bad)"); | |
16473 | return; | |
16474 | } | |
43234a1e L |
16475 | names = names_mask; |
16476 | break; | |
c0f3af97 | 16477 | default: |
a37a2806 NC |
16478 | /* See PR binutils/20893 for a reproducer. */ |
16479 | oappend ("(bad)"); | |
c0f3af97 L |
16480 | return; |
16481 | } | |
c0f3af97 | 16482 | break; |
43234a1e L |
16483 | case 512: |
16484 | names = names_zmm; | |
16485 | break; | |
c0f3af97 L |
16486 | default: |
16487 | abort (); | |
16488 | break; | |
16489 | } | |
539f890d | 16490 | oappend (names[reg]); |
c0f3af97 L |
16491 | } |
16492 | ||
41f5efc6 JB |
16493 | static void |
16494 | OP_VexR (int bytemode, int sizeflag) | |
16495 | { | |
16496 | if (modrm.mod == 3) | |
16497 | OP_VEX (bytemode, sizeflag); | |
16498 | } | |
16499 | ||
5dd85c99 | 16500 | static void |
e6123d0c | 16501 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 16502 | { |
e6123d0c | 16503 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 16504 | |
5dd85c99 | 16505 | if (vex.w) |
5f847646 | 16506 | { |
e6123d0c JB |
16507 | /* Swap 2nd and 3rd operands. */ |
16508 | strcpy (scratchbuf, op_out[2]); | |
16509 | strcpy (op_out[2], op_out[1]); | |
16510 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 16511 | } |
5dd85c99 SP |
16512 | } |
16513 | ||
c0f3af97 L |
16514 | static void |
16515 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16516 | { | |
16517 | int reg; | |
6384fd9e | 16518 | const char **names = names_xmm; |
b9733481 | 16519 | |
c0f3af97 L |
16520 | FETCH_DATA (the_info, codep + 1); |
16521 | reg = *codep++; | |
16522 | ||
6384fd9e | 16523 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
16524 | abort (); |
16525 | ||
c0f3af97 | 16526 | reg >>= 4; |
5f847646 JB |
16527 | if (address_mode != mode_64bit) |
16528 | reg &= 7; | |
dae39acc | 16529 | |
6384fd9e JB |
16530 | if (bytemode == x_mode && vex.length == 256) |
16531 | names = names_ymm; | |
16532 | ||
b9733481 | 16533 | oappend (names[reg]); |
b13b1bc0 JB |
16534 | |
16535 | if (vex.w) | |
16536 | { | |
16537 | /* Swap 3rd and 4th operands. */ | |
16538 | strcpy (scratchbuf, op_out[3]); | |
16539 | strcpy (op_out[3], op_out[2]); | |
16540 | strcpy (op_out[2], scratchbuf); | |
16541 | } | |
c0f3af97 L |
16542 | } |
16543 | ||
922d8de8 | 16544 | static void |
93abb146 JB |
16545 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
16546 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 16547 | { |
93abb146 JB |
16548 | scratchbuf[0] = '$'; |
16549 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
16550 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
16551 | } |
16552 | ||
43234a1e L |
16553 | static void |
16554 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16555 | int sizeflag ATTRIBUTE_UNUSED) | |
16556 | { | |
16557 | unsigned int cmp_type; | |
16558 | ||
16559 | if (!vex.evex) | |
16560 | abort (); | |
16561 | ||
16562 | FETCH_DATA (the_info, codep + 1); | |
16563 | cmp_type = *codep++ & 0xff; | |
16564 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16565 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16566 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16567 | && cmp_type != 3 | |
16568 | && cmp_type != 7) | |
16569 | { | |
16570 | char suffix [3]; | |
16571 | char *p = mnemonicendp - 2; | |
16572 | ||
16573 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16574 | if (p[0] == 'p') | |
16575 | { | |
16576 | p++; | |
16577 | suffix[0] = p[0]; | |
16578 | suffix[1] = '\0'; | |
16579 | } | |
16580 | else | |
16581 | { | |
16582 | suffix[0] = p[0]; | |
16583 | suffix[1] = p[1]; | |
16584 | suffix[2] = '\0'; | |
16585 | } | |
16586 | ||
16587 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16588 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16589 | } | |
be92cb14 JB |
16590 | else |
16591 | { | |
16592 | /* We have a reserved extension byte. Output it directly. */ | |
16593 | scratchbuf[0] = '$'; | |
16594 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16595 | oappend_maybe_intel (scratchbuf); | |
16596 | scratchbuf[0] = '\0'; | |
16597 | } | |
16598 | } | |
16599 | ||
16600 | static const struct op xop_cmp_op[] = | |
16601 | { | |
16602 | { STRING_COMMA_LEN ("lt") }, | |
16603 | { STRING_COMMA_LEN ("le") }, | |
16604 | { STRING_COMMA_LEN ("gt") }, | |
16605 | { STRING_COMMA_LEN ("ge") }, | |
16606 | { STRING_COMMA_LEN ("eq") }, | |
16607 | { STRING_COMMA_LEN ("neq") }, | |
16608 | { STRING_COMMA_LEN ("false") }, | |
16609 | { STRING_COMMA_LEN ("true") } | |
16610 | }; | |
16611 | ||
16612 | static void | |
16613 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16614 | int sizeflag ATTRIBUTE_UNUSED) | |
16615 | { | |
16616 | unsigned int cmp_type; | |
16617 | ||
16618 | FETCH_DATA (the_info, codep + 1); | |
16619 | cmp_type = *codep++ & 0xff; | |
16620 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16621 | { | |
16622 | char suffix[3]; | |
16623 | char *p = mnemonicendp - 2; | |
16624 | ||
16625 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16626 | if (p[0] == 'm') | |
16627 | { | |
16628 | p++; | |
16629 | suffix[0] = p[0]; | |
16630 | suffix[1] = '\0'; | |
16631 | } | |
16632 | else | |
16633 | { | |
16634 | suffix[0] = p[0]; | |
16635 | suffix[1] = p[1]; | |
16636 | suffix[2] = '\0'; | |
16637 | } | |
16638 | ||
16639 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16640 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16641 | } | |
43234a1e L |
16642 | else |
16643 | { | |
16644 | /* We have a reserved extension byte. Output it directly. */ | |
16645 | scratchbuf[0] = '$'; | |
16646 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16647 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16648 | scratchbuf[0] = '\0'; |
16649 | } | |
16650 | } | |
16651 | ||
ea397f5b L |
16652 | static const struct op pclmul_op[] = |
16653 | { | |
16654 | { STRING_COMMA_LEN ("lql") }, | |
16655 | { STRING_COMMA_LEN ("hql") }, | |
16656 | { STRING_COMMA_LEN ("lqh") }, | |
16657 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16658 | }; |
16659 | ||
16660 | static void | |
16661 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16662 | int sizeflag ATTRIBUTE_UNUSED) | |
16663 | { | |
16664 | unsigned int pclmul_type; | |
16665 | ||
16666 | FETCH_DATA (the_info, codep + 1); | |
16667 | pclmul_type = *codep++ & 0xff; | |
16668 | switch (pclmul_type) | |
16669 | { | |
16670 | case 0x10: | |
16671 | pclmul_type = 2; | |
16672 | break; | |
16673 | case 0x11: | |
16674 | pclmul_type = 3; | |
16675 | break; | |
16676 | default: | |
16677 | break; | |
7bb15c6f | 16678 | } |
c0f3af97 L |
16679 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16680 | { | |
16681 | char suffix [4]; | |
ea397f5b | 16682 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16683 | suffix[0] = p[0]; |
16684 | suffix[1] = p[1]; | |
16685 | suffix[2] = p[2]; | |
16686 | suffix[3] = '\0'; | |
ea397f5b L |
16687 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16688 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16689 | } |
16690 | else | |
16691 | { | |
16692 | /* We have a reserved extension byte. Output it directly. */ | |
16693 | scratchbuf[0] = '$'; | |
16694 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16695 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16696 | scratchbuf[0] = '\0'; |
16697 | } | |
16698 | } | |
16699 | ||
bc31405e L |
16700 | static void |
16701 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16702 | { | |
16703 | /* Add proper suffix to "movsxd". */ | |
16704 | char *p = mnemonicendp; | |
16705 | ||
16706 | switch (bytemode) | |
16707 | { | |
16708 | case movsxd_mode: | |
16709 | if (intel_syntax) | |
16710 | { | |
16711 | *p++ = 'x'; | |
16712 | *p++ = 'd'; | |
16713 | goto skip; | |
16714 | } | |
16715 | ||
16716 | USED_REX (REX_W); | |
16717 | if (rex & REX_W) | |
16718 | { | |
16719 | *p++ = 'l'; | |
16720 | *p++ = 'q'; | |
16721 | } | |
16722 | else | |
16723 | { | |
16724 | *p++ = 'x'; | |
16725 | *p++ = 'd'; | |
16726 | } | |
16727 | break; | |
16728 | default: | |
16729 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16730 | break; | |
16731 | } | |
16732 | ||
dc1e8a47 | 16733 | skip: |
bc31405e L |
16734 | mnemonicendp = p; |
16735 | *p = '\0'; | |
16736 | OP_E (bytemode, sizeflag); | |
16737 | } | |
16738 | ||
43234a1e L |
16739 | static void |
16740 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16741 | { | |
16742 | if (!vex.evex | |
1ba585e8 | 16743 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16744 | abort (); |
16745 | ||
16746 | USED_REX (REX_R); | |
16747 | if ((rex & REX_R) != 0 || !vex.r) | |
16748 | { | |
16749 | BadOp (); | |
16750 | return; | |
16751 | } | |
16752 | ||
16753 | oappend (names_mask [modrm.reg]); | |
16754 | } | |
16755 | ||
16756 | static void | |
16757 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16758 | { | |
43234a1e L |
16759 | if (modrm.mod == 3 && vex.b) |
16760 | switch (bytemode) | |
16761 | { | |
70df6fc9 L |
16762 | case evex_rounding_64_mode: |
16763 | if (address_mode != mode_64bit) | |
16764 | { | |
16765 | oappend ("(bad)"); | |
16766 | break; | |
16767 | } | |
16768 | /* Fall through. */ | |
43234a1e L |
16769 | case evex_rounding_mode: |
16770 | oappend (names_rounding[vex.ll]); | |
16771 | break; | |
16772 | case evex_sae_mode: | |
16773 | oappend ("{sae}"); | |
16774 | break; | |
16775 | default: | |
6df22cf6 | 16776 | abort (); |
43234a1e L |
16777 | break; |
16778 | } | |
16779 | } |