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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
0af1713e 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5 6 This file is part of the GNU opcodes library.
20f0a1fc 7
9b201bb5 8 This library is free software; you can redistribute it and/or modify
20f0a1fc 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
20f0a1fc 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
20f0a1fc
NC		 17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
20f0a1fc
NC		 23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
252b5132 36
252b5132 37#include "sysdep.h"
dabbade6 38#include "dis-asm.h"
252b5132 39#include "opintl.h"
0b1cf022 40#include "opcode/i386.h"
85f10a01 41#include "libiberty.h"
252b5132
RH		 42
43#include <setjmp.h>
44
26ca5450
AJ		 45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
c0f3af97 54static void OP_E_register (int, int);
c1e679ec 55static void OP_E_memory (int, int);
5d669648 56static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 57static void OP_E (int, int);
58static void OP_G (int, int);
59static bfd_vma get64 (void);
60static bfd_signed_vma get32 (void);
61static bfd_signed_vma get32s (void);
62static int get16 (void);
63static void set_op (bfd_vma, int);
b844680a 64static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 65static void OP_REG (int, int);
66static void OP_IMREG (int, int);
67static void OP_I (int, int);
68static void OP_I64 (int, int);
69static void OP_sI (int, int);
70static void OP_J (int, int);
71static void OP_SEG (int, int);
72static void OP_DIR (int, int);
73static void OP_OFF (int, int);
74static void OP_OFF64 (int, int);
75static void ptr_reg (int, int);
76static void OP_ESreg (int, int);
77static void OP_DSreg (int, int);
78static void OP_C (int, int);
79static void OP_D (int, int);
80static void OP_T (int, int);
6f74c397 81static void OP_R (int, int);
26ca5450
AJ		 82static void OP_MMX (int, int);
83static void OP_XMM (int, int);
84static void OP_EM (int, int);
85static void OP_EX (int, int);
4d9567e0
MM		 86static void OP_EMC (int,int);
87static void OP_MXC (int,int);
26ca5450
AJ		 88static void OP_MS (int, int);
89static void OP_XS (int, int);
cc0ec051 90static void OP_M (int, int);
c0f3af97
L		 91static void OP_VEX (int, int);
92static void OP_EX_Vex (int, int);
922d8de8 93static void OP_EX_VexW (int, int);
c0f3af97 94static void OP_XMM_Vex (int, int);
922d8de8 95static void OP_XMM_VexW (int, int);
c0f3af97
L		 96static void OP_REG_VexI4 (int, int);
97static void PCLMUL_Fixup (int, int);
922d8de8 98static void VEXI4_Fixup (int, int);
c0f3af97
L		 99static void VZERO_Fixup (int, int);
100static void VCMP_Fixup (int, int);
cc0ec051 101static void OP_0f07 (int, int);
b844680a
L		 102static void OP_Monitor (int, int);
103static void OP_Mwait (int, int);
46e883c5
L		 104static void NOP_Fixup1 (int, int);
105static void NOP_Fixup2 (int, int);
26ca5450 106static void OP_3DNowSuffix (int, int);
ad19981d 107static void CMP_Fixup (int, int);
26ca5450 108static void BadOp (void);
35c52694 109static void REP_Fixup (int, int);
f5804c90 110static void CMPXCHG8B_Fixup (int, int);
42903f7f 111static void XMM_Fixup (int, int);
381d071f 112static void CRC32_Fixup (int, int);
eacc9c89 113static void FXSAVE_Fixup (int, int);
f88c9eb0
SP		 114static void OP_LWPCB_E (int, int);
115static void OP_LWP_E (int, int);
116static void OP_LWP_I (int, int);
5dd85c99
SP		 117static void OP_Vex_2src_1 (int, int);
118static void OP_Vex_2src_2 (int, int);
c1e679ec 119
f1f8f695 120static void MOVBE_Fixup (int, int);
252b5132 121
6608db57 122struct dis_private {
252b5132
RH		 123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
0b1cf022 125 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 126 bfd_vma insn_start;
e396998b 127 int orig_sizeflag;
252b5132
RH		 128 jmp_buf bailout;
129};
130
cb712a9e
L		 131enum address_mode
132{
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136};
137
138enum address_mode address_mode;
52b15da3 139
5076851f
ILT		 140/* Flags for the prefixes for the current instruction. See below. */
141static int prefixes;
142
52b15da3
JH		 143/* REX prefix the current instruction. See below. */
144static int rex;
145/* Bits of REX we've already used. */
146static int rex_used;
c0f3af97
L		 147/* Original REX prefix. */
148static int rex_original;
149/* REX bits in original REX prefix ignored. It may not be the same
150 as rex_original since some bits may not be ignored. */
151static int rex_ignored;
52b15da3
JH		 152/* Mark parts used in the REX prefix. When we are testing for
153 empty prefix (for 8bit register REX extension), just mask it
154 out. Otherwise test for REX bit is excuse for existence of REX
155 only in case value is nonzero. */
156#define USED_REX(value) \
157 { \
158 if (value) \
161a04f6
L		 159 { \
160 if ((rex & value)) \
161 rex_used |= (value) | REX_OPCODE; \
162 } \
52b15da3 163 else \
161a04f6 164 rex_used |= REX_OPCODE; \
52b15da3
JH		 165 }
166
7d421014
ILT		 167/* Flags for prefixes which we somehow handled when printing the
168 current instruction. */
169static int used_prefixes;
170
5076851f
ILT		 171/* Flags stored in PREFIXES. */
172#define PREFIX_REPZ 1
173#define PREFIX_REPNZ 2
174#define PREFIX_LOCK 4
175#define PREFIX_CS 8
176#define PREFIX_SS 0x10
177#define PREFIX_DS 0x20
178#define PREFIX_ES 0x40
179#define PREFIX_FS 0x80
180#define PREFIX_GS 0x100
181#define PREFIX_DATA 0x200
182#define PREFIX_ADDR 0x400
183#define PREFIX_FWAIT 0x800
184
252b5132
RH		 185/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
186 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
187 on error. */
188#define FETCH_DATA(info, addr) \
6608db57 189 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 190 ? 1 : fetch_data ((info), (addr)))
191
192static int
26ca5450 193fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 194{
195 int status;
6608db57 196 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 197 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
198
0b1cf022 199 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 200 status = (*info->read_memory_func) (start,
201 priv->max_fetched,
202 addr - priv->max_fetched,
203 info);
204 else
205 status = -1;
252b5132
RH		 206 if (status != 0)
207 {
7d421014 208 /* If we did manage to read at least one byte, then
db6eb5be
AM		 209 print_insn_i386 will do something sensible. Otherwise, print
210 an error. We do that here because this is where we know
211 STATUS. */
7d421014 212 if (priv->max_fetched == priv->the_buffer)
5076851f 213 (*info->memory_error_func) (status, start, info);
252b5132
RH		 214 longjmp (priv->bailout, 1);
215 }
216 else
217 priv->max_fetched = addr;
218 return 1;
219}
220
ce518a5f
L		 221#define XX { NULL, 0 }
222
223#define Eb { OP_E, b_mode }
b6169b20 224#define EbS { OP_E, b_swap_mode }
ce518a5f 225#define Ev { OP_E, v_mode }
b6169b20 226#define EvS { OP_E, v_swap_mode }
ce518a5f
L		 227#define Ed { OP_E, d_mode }
228#define Edq { OP_E, dq_mode }
229#define Edqw { OP_E, dqw_mode }
42903f7f
L		 230#define Edqb { OP_E, dqb_mode }
231#define Edqd { OP_E, dqd_mode }
09335d05 232#define Eq { OP_E, q_mode }
ce518a5f
L		 233#define indirEv { OP_indirE, stack_v_mode }
234#define indirEp { OP_indirE, f_mode }
235#define stackEv { OP_E, stack_v_mode }
236#define Em { OP_E, m_mode }
237#define Ew { OP_E, w_mode }
238#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 239#define Ma { OP_M, a_mode }
b844680a 240#define Mb { OP_M, b_mode }
d9a5e5e5 241#define Md { OP_M, d_mode }
f1f8f695 242#define Mo { OP_M, o_mode }
ce518a5f
L		 243#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
244#define Mq { OP_M, q_mode }
4ee52178 245#define Mx { OP_M, x_mode }
c0f3af97 246#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 247#define Gb { OP_G, b_mode }
248#define Gv { OP_G, v_mode }
249#define Gd { OP_G, d_mode }
250#define Gdq { OP_G, dq_mode }
251#define Gm { OP_G, m_mode }
252#define Gw { OP_G, w_mode }
6f74c397
L		 253#define Rd { OP_R, d_mode }
254#define Rm { OP_R, m_mode }
ce518a5f
L		 255#define Ib { OP_I, b_mode }
256#define sIb { OP_sI, b_mode } /* sign extened byte */
257#define Iv { OP_I, v_mode }
258#define Iq { OP_I, q_mode }
259#define Iv64 { OP_I64, v_mode }
260#define Iw { OP_I, w_mode }
261#define I1 { OP_I, const_1_mode }
262#define Jb { OP_J, b_mode }
263#define Jv { OP_J, v_mode }
264#define Cm { OP_C, m_mode }
265#define Dm { OP_D, m_mode }
266#define Td { OP_T, d_mode }
b844680a 267#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 268
269#define RMeAX { OP_REG, eAX_reg }
270#define RMeBX { OP_REG, eBX_reg }
271#define RMeCX { OP_REG, eCX_reg }
272#define RMeDX { OP_REG, eDX_reg }
273#define RMeSP { OP_REG, eSP_reg }
274#define RMeBP { OP_REG, eBP_reg }
275#define RMeSI { OP_REG, eSI_reg }
276#define RMeDI { OP_REG, eDI_reg }
277#define RMrAX { OP_REG, rAX_reg }
278#define RMrBX { OP_REG, rBX_reg }
279#define RMrCX { OP_REG, rCX_reg }
280#define RMrDX { OP_REG, rDX_reg }
281#define RMrSP { OP_REG, rSP_reg }
282#define RMrBP { OP_REG, rBP_reg }
283#define RMrSI { OP_REG, rSI_reg }
284#define RMrDI { OP_REG, rDI_reg }
285#define RMAL { OP_REG, al_reg }
286#define RMAL { OP_REG, al_reg }
287#define RMCL { OP_REG, cl_reg }
288#define RMDL { OP_REG, dl_reg }
289#define RMBL { OP_REG, bl_reg }
290#define RMAH { OP_REG, ah_reg }
291#define RMCH { OP_REG, ch_reg }
292#define RMDH { OP_REG, dh_reg }
293#define RMBH { OP_REG, bh_reg }
294#define RMAX { OP_REG, ax_reg }
295#define RMDX { OP_REG, dx_reg }
296
297#define eAX { OP_IMREG, eAX_reg }
298#define eBX { OP_IMREG, eBX_reg }
299#define eCX { OP_IMREG, eCX_reg }
300#define eDX { OP_IMREG, eDX_reg }
301#define eSP { OP_IMREG, eSP_reg }
302#define eBP { OP_IMREG, eBP_reg }
303#define eSI { OP_IMREG, eSI_reg }
304#define eDI { OP_IMREG, eDI_reg }
305#define AL { OP_IMREG, al_reg }
306#define CL { OP_IMREG, cl_reg }
307#define DL { OP_IMREG, dl_reg }
308#define BL { OP_IMREG, bl_reg }
309#define AH { OP_IMREG, ah_reg }
310#define CH { OP_IMREG, ch_reg }
311#define DH { OP_IMREG, dh_reg }
312#define BH { OP_IMREG, bh_reg }
313#define AX { OP_IMREG, ax_reg }
314#define DX { OP_IMREG, dx_reg }
315#define zAX { OP_IMREG, z_mode_ax_reg }
316#define indirDX { OP_IMREG, indir_dx_reg }
317
318#define Sw { OP_SEG, w_mode }
319#define Sv { OP_SEG, v_mode }
320#define Ap { OP_DIR, 0 }
321#define Ob { OP_OFF64, b_mode }
322#define Ov { OP_OFF64, v_mode }
323#define Xb { OP_DSreg, eSI_reg }
324#define Xv { OP_DSreg, eSI_reg }
325#define Xz { OP_DSreg, eSI_reg }
326#define Yb { OP_ESreg, eDI_reg }
327#define Yv { OP_ESreg, eDI_reg }
328#define DSBX { OP_DSreg, eBX_reg }
329
330#define es { OP_REG, es_reg }
331#define ss { OP_REG, ss_reg }
332#define cs { OP_REG, cs_reg }
333#define ds { OP_REG, ds_reg }
334#define fs { OP_REG, fs_reg }
335#define gs { OP_REG, gs_reg }
336
337#define MX { OP_MMX, 0 }
338#define XM { OP_XMM, 0 }
c0f3af97 339#define XMM { OP_XMM, xmm_mode }
ce518a5f 340#define EM { OP_EM, v_mode }
b6169b20 341#define EMS { OP_EM, v_swap_mode }
09a2c6cf 342#define EMd { OP_EM, d_mode }
14051056 343#define EMx { OP_EM, x_mode }
8976381e 344#define EXw { OP_EX, w_mode }
09a2c6cf 345#define EXd { OP_EX, d_mode }
fa99fab2 346#define EXdS { OP_EX, d_swap_mode }
09a2c6cf 347#define EXq { OP_EX, q_mode }
b6169b20 348#define EXqS { OP_EX, q_swap_mode }
09a2c6cf 349#define EXx { OP_EX, x_mode }
b6169b20 350#define EXxS { OP_EX, x_swap_mode }
c0f3af97
L		 351#define EXxmm { OP_EX, xmm_mode }
352#define EXxmmq { OP_EX, xmmq_mode }
353#define EXymmq { OP_EX, ymmq_mode }
0bfee649 354#define EXVexWdq { OP_EX, vex_w_dq_mode }
ce518a5f
L		 355#define MS { OP_MS, v_mode }
356#define XS { OP_XS, v_mode }
09335d05 357#define EMCq { OP_EMC, q_mode }
ce518a5f 358#define MXC { OP_MXC, 0 }
ce518a5f 359#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 360#define CMP { CMP_Fixup, 0 }
42903f7f 361#define XMM0 { XMM_Fixup, 0 }
eacc9c89 362#define FXSAVE { FXSAVE_Fixup, 0 }
5dd85c99
SP		 363#define Vex_2src_1 { OP_Vex_2src_1, 0 }
364#define Vex_2src_2 { OP_Vex_2src_2, 0 }
252b5132 365
c0f3af97
L		 366#define Vex { OP_VEX, vex_mode }
367#define Vex128 { OP_VEX, vex128_mode }
368#define Vex256 { OP_VEX, vex256_mode }
922d8de8 369#define VexI4 { VEXI4_Fixup, 0}
c0f3af97 370#define EXdVex { OP_EX_Vex, d_mode }
fa99fab2 371#define EXdVexS { OP_EX_Vex, d_swap_mode }
c0f3af97 372#define EXqVex { OP_EX_Vex, q_mode }
fa99fab2 373#define EXqVexS { OP_EX_Vex, q_swap_mode }
922d8de8
DR		 374#define EXVexW { OP_EX_VexW, x_mode }
375#define EXdVexW { OP_EX_VexW, d_mode }
376#define EXqVexW { OP_EX_VexW, q_mode }
c0f3af97 377#define XMVex { OP_XMM_Vex, 0 }
922d8de8 378#define XMVexW { OP_XMM_VexW, 0 }
c0f3af97
L		 379#define XMVexI4 { OP_REG_VexI4, x_mode }
380#define PCLMUL { PCLMUL_Fixup, 0 }
381#define VZERO { VZERO_Fixup, 0 }
382#define VCMP { VCMP_Fixup, 0 }
c0f3af97 383
35c52694 384/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 385#define Xbr { REP_Fixup, eSI_reg }
386#define Xvr { REP_Fixup, eSI_reg }
387#define Ybr { REP_Fixup, eDI_reg }
388#define Yvr { REP_Fixup, eDI_reg }
389#define Yzr { REP_Fixup, eDI_reg }
390#define indirDXr { REP_Fixup, indir_dx_reg }
391#define ALr { REP_Fixup, al_reg }
392#define eAXr { REP_Fixup, eAX_reg }
393
394#define cond_jump_flag { NULL, cond_jump_mode }
395#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 396
252b5132 397/* bits in sizeflag */
252b5132 398#define SUFFIX_ALWAYS 4
252b5132
RH		 399#define AFLAG 2
400#define DFLAG 1
401
51e7da1b
L		 402enum
403{
404 /* byte operand */
405 b_mode = 1,
406 /* byte operand with operand swapped */
3873ba12 407 b_swap_mode,
51e7da1b 408 /* operand size depends on prefixes */
3873ba12 409 v_mode,
51e7da1b 410 /* operand size depends on prefixes with operand swapped */
3873ba12 411 v_swap_mode,
51e7da1b 412 /* word operand */
3873ba12 413 w_mode,
51e7da1b 414 /* double word operand */
3873ba12 415 d_mode,
51e7da1b 416 /* double word operand with operand swapped */
3873ba12 417 d_swap_mode,
51e7da1b 418 /* quad word operand */
3873ba12 419 q_mode,
51e7da1b 420 /* quad word operand with operand swapped */
3873ba12 421 q_swap_mode,
51e7da1b 422 /* ten-byte operand */
3873ba12 423 t_mode,
51e7da1b 424 /* 16-byte XMM or 32-byte YMM operand */
3873ba12 425 x_mode,
51e7da1b 426 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
3873ba12 427 x_swap_mode,
51e7da1b 428 /* 16-byte XMM operand */
3873ba12 429 xmm_mode,
51e7da1b 430 /* 16-byte XMM or quad word operand */
3873ba12 431 xmmq_mode,
51e7da1b 432 /* 32-byte YMM or quad word operand */
3873ba12 433 ymmq_mode,
51e7da1b 434 /* d_mode in 32bit, q_mode in 64bit mode. */
3873ba12 435 m_mode,
51e7da1b 436 /* pair of v_mode operands */
3873ba12
L		 437 a_mode,
438 cond_jump_mode,
439 loop_jcxz_mode,
51e7da1b 440 /* operand size depends on REX prefixes. */
3873ba12 441 dq_mode,
51e7da1b 442 /* registers like dq_mode, memory like w_mode. */
3873ba12 443 dqw_mode,
51e7da1b 444 /* 4- or 6-byte pointer operand */
3873ba12
L		 445 f_mode,
446 const_1_mode,
51e7da1b 447 /* v_mode for stack-related opcodes. */
3873ba12 448 stack_v_mode,
51e7da1b 449 /* non-quad operand size depends on prefixes */
3873ba12 450 z_mode,
51e7da1b 451 /* 16-byte operand */
3873ba12 452 o_mode,
51e7da1b 453 /* registers like dq_mode, memory like b_mode. */
3873ba12 454 dqb_mode,
51e7da1b 455 /* registers like dq_mode, memory like d_mode. */
3873ba12 456 dqd_mode,
51e7da1b 457 /* normal vex mode */
3873ba12 458 vex_mode,
51e7da1b 459 /* 128bit vex mode */
3873ba12 460 vex128_mode,
51e7da1b 461 /* 256bit vex mode */
3873ba12 462 vex256_mode,
51e7da1b 463 /* operand size depends on the VEX.W bit. */
3873ba12 464 vex_w_dq_mode,
d55ee72f 465
3873ba12
L		 466 es_reg,
467 cs_reg,
468 ss_reg,
469 ds_reg,
470 fs_reg,
471 gs_reg,
d55ee72f 472
3873ba12
L		 473 eAX_reg,
474 eCX_reg,
475 eDX_reg,
476 eBX_reg,
477 eSP_reg,
478 eBP_reg,
479 eSI_reg,
480 eDI_reg,
d55ee72f 481
3873ba12
L		 482 al_reg,
483 cl_reg,
484 dl_reg,
485 bl_reg,
486 ah_reg,
487 ch_reg,
488 dh_reg,
489 bh_reg,
d55ee72f 490
3873ba12
L		 491 ax_reg,
492 cx_reg,
493 dx_reg,
494 bx_reg,
495 sp_reg,
496 bp_reg,
497 si_reg,
498 di_reg,
d55ee72f 499
3873ba12
L		 500 rAX_reg,
501 rCX_reg,
502 rDX_reg,
503 rBX_reg,
504 rSP_reg,
505 rBP_reg,
506 rSI_reg,
507 rDI_reg,
d55ee72f 508
3873ba12
L		 509 z_mode_ax_reg,
510 indir_dx_reg
51e7da1b 511};
252b5132 512
51e7da1b
L		 513enum
514{
515 FLOATCODE = 1,
3873ba12
L		 516 USE_REG_TABLE,
517 USE_MOD_TABLE,
518 USE_RM_TABLE,
519 USE_PREFIX_TABLE,
520 USE_X86_64_TABLE,
521 USE_3BYTE_TABLE,
f88c9eb0 522 USE_XOP_8F_TABLE,
3873ba12
L		 523 USE_VEX_C4_TABLE,
524 USE_VEX_C5_TABLE,
9e30b8e0
L		 525 USE_VEX_LEN_TABLE,
526 USE_VEX_W_TABLE
51e7da1b 527};
6439fc28 528
1ceb70f8 529#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 530
4e7d34a6 531#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 532#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
533#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
534#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
535#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 536#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
537#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
f88c9eb0 538#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
c0f3af97
L		 539#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
540#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
541#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
9e30b8e0 542#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
1ceb70f8 543
51e7da1b
L		 544enum
545{
546 REG_80 = 0,
3873ba12
L		 547 REG_81,
548 REG_82,
549 REG_8F,
550 REG_C0,
551 REG_C1,
552 REG_C6,
553 REG_C7,
554 REG_D0,
555 REG_D1,
556 REG_D2,
557 REG_D3,
558 REG_F6,
559 REG_F7,
560 REG_FE,
561 REG_FF,
562 REG_0F00,
563 REG_0F01,
564 REG_0F0D,
565 REG_0F18,
566 REG_0F71,
567 REG_0F72,
568 REG_0F73,
569 REG_0FA6,
570 REG_0FA7,
571 REG_0FAE,
572 REG_0FBA,
573 REG_0FC7,
574 REG_VEX_71,
575 REG_VEX_72,
576 REG_VEX_73,
f88c9eb0
SP		 577 REG_VEX_AE,
578 REG_XOP_LWPCB,
579 REG_XOP_LWP
51e7da1b 580};
1ceb70f8 581
51e7da1b
L		 582enum
583{
584 MOD_8D = 0,
3873ba12
L		 585 MOD_0F01_REG_0,
586 MOD_0F01_REG_1,
587 MOD_0F01_REG_2,
588 MOD_0F01_REG_3,
589 MOD_0F01_REG_7,
590 MOD_0F12_PREFIX_0,
591 MOD_0F13,
592 MOD_0F16_PREFIX_0,
593 MOD_0F17,
594 MOD_0F18_REG_0,
595 MOD_0F18_REG_1,
596 MOD_0F18_REG_2,
597 MOD_0F18_REG_3,
598 MOD_0F20,
599 MOD_0F21,
600 MOD_0F22,
601 MOD_0F23,
602 MOD_0F24,
603 MOD_0F26,
604 MOD_0F2B_PREFIX_0,
605 MOD_0F2B_PREFIX_1,
606 MOD_0F2B_PREFIX_2,
607 MOD_0F2B_PREFIX_3,
608 MOD_0F51,
609 MOD_0F71_REG_2,
610 MOD_0F71_REG_4,
611 MOD_0F71_REG_6,
612 MOD_0F72_REG_2,
613 MOD_0F72_REG_4,
614 MOD_0F72_REG_6,
615 MOD_0F73_REG_2,
616 MOD_0F73_REG_3,
617 MOD_0F73_REG_6,
618 MOD_0F73_REG_7,
619 MOD_0FAE_REG_0,
620 MOD_0FAE_REG_1,
621 MOD_0FAE_REG_2,
622 MOD_0FAE_REG_3,
623 MOD_0FAE_REG_4,
624 MOD_0FAE_REG_5,
625 MOD_0FAE_REG_6,
626 MOD_0FAE_REG_7,
627 MOD_0FB2,
628 MOD_0FB4,
629 MOD_0FB5,
630 MOD_0FC7_REG_6,
631 MOD_0FC7_REG_7,
632 MOD_0FD7,
633 MOD_0FE7_PREFIX_2,
634 MOD_0FF0_PREFIX_3,
635 MOD_0F382A_PREFIX_2,
636 MOD_62_32BIT,
637 MOD_C4_32BIT,
638 MOD_C5_32BIT,
639 MOD_VEX_12_PREFIX_0,
640 MOD_VEX_13,
641 MOD_VEX_16_PREFIX_0,
642 MOD_VEX_17,
643 MOD_VEX_2B,
976f1fde 644 MOD_VEX_50,
3873ba12
L		 645 MOD_VEX_71_REG_2,
646 MOD_VEX_71_REG_4,
647 MOD_VEX_71_REG_6,
648 MOD_VEX_72_REG_2,
649 MOD_VEX_72_REG_4,
650 MOD_VEX_72_REG_6,
651 MOD_VEX_73_REG_2,
652 MOD_VEX_73_REG_3,
653 MOD_VEX_73_REG_6,
654 MOD_VEX_73_REG_7,
655 MOD_VEX_AE_REG_2,
656 MOD_VEX_AE_REG_3,
657 MOD_VEX_D7_PREFIX_2,
658 MOD_VEX_E7_PREFIX_2,
659 MOD_VEX_F0_PREFIX_3,
660 MOD_VEX_3818_PREFIX_2,
661 MOD_VEX_3819_PREFIX_2,
662 MOD_VEX_381A_PREFIX_2,
663 MOD_VEX_382A_PREFIX_2,
664 MOD_VEX_382C_PREFIX_2,
665 MOD_VEX_382D_PREFIX_2,
666 MOD_VEX_382E_PREFIX_2,
667 MOD_VEX_382F_PREFIX_2
51e7da1b 668};
1ceb70f8 669
51e7da1b
L		 670enum
671{
672 RM_0F01_REG_0 = 0,
3873ba12
L		 673 RM_0F01_REG_1,
674 RM_0F01_REG_2,
675 RM_0F01_REG_3,
676 RM_0F01_REG_7,
677 RM_0FAE_REG_5,
678 RM_0FAE_REG_6,
679 RM_0FAE_REG_7
51e7da1b 680};
1ceb70f8 681
51e7da1b
L		 682enum
683{
684 PREFIX_90 = 0,
3873ba12
L		 685 PREFIX_0F10,
686 PREFIX_0F11,
687 PREFIX_0F12,
688 PREFIX_0F16,
689 PREFIX_0F2A,
690 PREFIX_0F2B,
691 PREFIX_0F2C,
692 PREFIX_0F2D,
693 PREFIX_0F2E,
694 PREFIX_0F2F,
695 PREFIX_0F51,
696 PREFIX_0F52,
697 PREFIX_0F53,
698 PREFIX_0F58,
699 PREFIX_0F59,
700 PREFIX_0F5A,
701 PREFIX_0F5B,
702 PREFIX_0F5C,
703 PREFIX_0F5D,
704 PREFIX_0F5E,
705 PREFIX_0F5F,
706 PREFIX_0F60,
707 PREFIX_0F61,
708 PREFIX_0F62,
709 PREFIX_0F6C,
710 PREFIX_0F6D,
711 PREFIX_0F6F,
712 PREFIX_0F70,
713 PREFIX_0F73_REG_3,
714 PREFIX_0F73_REG_7,
715 PREFIX_0F78,
716 PREFIX_0F79,
717 PREFIX_0F7C,
718 PREFIX_0F7D,
719 PREFIX_0F7E,
720 PREFIX_0F7F,
721 PREFIX_0FB8,
722 PREFIX_0FBD,
723 PREFIX_0FC2,
724 PREFIX_0FC3,
725 PREFIX_0FC7_REG_6,
726 PREFIX_0FD0,
727 PREFIX_0FD6,
728 PREFIX_0FE6,
729 PREFIX_0FE7,
730 PREFIX_0FF0,
731 PREFIX_0FF7,
732 PREFIX_0F3810,
733 PREFIX_0F3814,
734 PREFIX_0F3815,
735 PREFIX_0F3817,
736 PREFIX_0F3820,
737 PREFIX_0F3821,
738 PREFIX_0F3822,
739 PREFIX_0F3823,
740 PREFIX_0F3824,
741 PREFIX_0F3825,
742 PREFIX_0F3828,
743 PREFIX_0F3829,
744 PREFIX_0F382A,
745 PREFIX_0F382B,
746 PREFIX_0F3830,
747 PREFIX_0F3831,
748 PREFIX_0F3832,
749 PREFIX_0F3833,
750 PREFIX_0F3834,
751 PREFIX_0F3835,
752 PREFIX_0F3837,
753 PREFIX_0F3838,
754 PREFIX_0F3839,
755 PREFIX_0F383A,
756 PREFIX_0F383B,
757 PREFIX_0F383C,
758 PREFIX_0F383D,
759 PREFIX_0F383E,
760 PREFIX_0F383F,
761 PREFIX_0F3840,
762 PREFIX_0F3841,
763 PREFIX_0F3880,
764 PREFIX_0F3881,
765 PREFIX_0F38DB,
766 PREFIX_0F38DC,
767 PREFIX_0F38DD,
768 PREFIX_0F38DE,
769 PREFIX_0F38DF,
770 PREFIX_0F38F0,
771 PREFIX_0F38F1,
772 PREFIX_0F3A08,
773 PREFIX_0F3A09,
774 PREFIX_0F3A0A,
775 PREFIX_0F3A0B,
776 PREFIX_0F3A0C,
777 PREFIX_0F3A0D,
778 PREFIX_0F3A0E,
779 PREFIX_0F3A14,
780 PREFIX_0F3A15,
781 PREFIX_0F3A16,
782 PREFIX_0F3A17,
783 PREFIX_0F3A20,
784 PREFIX_0F3A21,
785 PREFIX_0F3A22,
786 PREFIX_0F3A40,
787 PREFIX_0F3A41,
788 PREFIX_0F3A42,
789 PREFIX_0F3A44,
790 PREFIX_0F3A60,
791 PREFIX_0F3A61,
792 PREFIX_0F3A62,
793 PREFIX_0F3A63,
794 PREFIX_0F3ADF,
795 PREFIX_VEX_10,
796 PREFIX_VEX_11,
797 PREFIX_VEX_12,
798 PREFIX_VEX_16,
799 PREFIX_VEX_2A,
800 PREFIX_VEX_2C,
801 PREFIX_VEX_2D,
802 PREFIX_VEX_2E,
803 PREFIX_VEX_2F,
804 PREFIX_VEX_51,
805 PREFIX_VEX_52,
806 PREFIX_VEX_53,
807 PREFIX_VEX_58,
808 PREFIX_VEX_59,
809 PREFIX_VEX_5A,
810 PREFIX_VEX_5B,
811 PREFIX_VEX_5C,
812 PREFIX_VEX_5D,
813 PREFIX_VEX_5E,
814 PREFIX_VEX_5F,
815 PREFIX_VEX_60,
816 PREFIX_VEX_61,
817 PREFIX_VEX_62,
818 PREFIX_VEX_63,
819 PREFIX_VEX_64,
820 PREFIX_VEX_65,
821 PREFIX_VEX_66,
822 PREFIX_VEX_67,
823 PREFIX_VEX_68,
824 PREFIX_VEX_69,
825 PREFIX_VEX_6A,
826 PREFIX_VEX_6B,
827 PREFIX_VEX_6C,
828 PREFIX_VEX_6D,
829 PREFIX_VEX_6E,
830 PREFIX_VEX_6F,
831 PREFIX_VEX_70,
832 PREFIX_VEX_71_REG_2,
833 PREFIX_VEX_71_REG_4,
834 PREFIX_VEX_71_REG_6,
835 PREFIX_VEX_72_REG_2,
836 PREFIX_VEX_72_REG_4,
837 PREFIX_VEX_72_REG_6,
838 PREFIX_VEX_73_REG_2,
839 PREFIX_VEX_73_REG_3,
840 PREFIX_VEX_73_REG_6,
841 PREFIX_VEX_73_REG_7,
842 PREFIX_VEX_74,
843 PREFIX_VEX_75,
844 PREFIX_VEX_76,
845 PREFIX_VEX_77,
846 PREFIX_VEX_7C,
847 PREFIX_VEX_7D,
848 PREFIX_VEX_7E,
849 PREFIX_VEX_7F,
850 PREFIX_VEX_C2,
851 PREFIX_VEX_C4,
852 PREFIX_VEX_C5,
853 PREFIX_VEX_D0,
854 PREFIX_VEX_D1,
855 PREFIX_VEX_D2,
856 PREFIX_VEX_D3,
857 PREFIX_VEX_D4,
858 PREFIX_VEX_D5,
859 PREFIX_VEX_D6,
860 PREFIX_VEX_D7,
861 PREFIX_VEX_D8,
862 PREFIX_VEX_D9,
863 PREFIX_VEX_DA,
864 PREFIX_VEX_DB,
865 PREFIX_VEX_DC,
866 PREFIX_VEX_DD,
867 PREFIX_VEX_DE,
868 PREFIX_VEX_DF,
869 PREFIX_VEX_E0,
870 PREFIX_VEX_E1,
871 PREFIX_VEX_E2,
872 PREFIX_VEX_E3,
873 PREFIX_VEX_E4,
874 PREFIX_VEX_E5,
875 PREFIX_VEX_E6,
876 PREFIX_VEX_E7,
877 PREFIX_VEX_E8,
878 PREFIX_VEX_E9,
879 PREFIX_VEX_EA,
880 PREFIX_VEX_EB,
881 PREFIX_VEX_EC,
882 PREFIX_VEX_ED,
883 PREFIX_VEX_EE,
884 PREFIX_VEX_EF,
885 PREFIX_VEX_F0,
886 PREFIX_VEX_F1,
887 PREFIX_VEX_F2,
888 PREFIX_VEX_F3,
889 PREFIX_VEX_F4,
890 PREFIX_VEX_F5,
891 PREFIX_VEX_F6,
892 PREFIX_VEX_F7,
893 PREFIX_VEX_F8,
894 PREFIX_VEX_F9,
895 PREFIX_VEX_FA,
896 PREFIX_VEX_FB,
897 PREFIX_VEX_FC,
898 PREFIX_VEX_FD,
899 PREFIX_VEX_FE,
900 PREFIX_VEX_3800,
901 PREFIX_VEX_3801,
902 PREFIX_VEX_3802,
903 PREFIX_VEX_3803,
904 PREFIX_VEX_3804,
905 PREFIX_VEX_3805,
906 PREFIX_VEX_3806,
907 PREFIX_VEX_3807,
908 PREFIX_VEX_3808,
909 PREFIX_VEX_3809,
910 PREFIX_VEX_380A,
911 PREFIX_VEX_380B,
912 PREFIX_VEX_380C,
913 PREFIX_VEX_380D,
914 PREFIX_VEX_380E,
915 PREFIX_VEX_380F,
916 PREFIX_VEX_3817,
917 PREFIX_VEX_3818,
918 PREFIX_VEX_3819,
919 PREFIX_VEX_381A,
920 PREFIX_VEX_381C,
921 PREFIX_VEX_381D,
922 PREFIX_VEX_381E,
923 PREFIX_VEX_3820,
924 PREFIX_VEX_3821,
925 PREFIX_VEX_3822,
926 PREFIX_VEX_3823,
927 PREFIX_VEX_3824,
928 PREFIX_VEX_3825,
929 PREFIX_VEX_3828,
930 PREFIX_VEX_3829,
931 PREFIX_VEX_382A,
932 PREFIX_VEX_382B,
933 PREFIX_VEX_382C,
934 PREFIX_VEX_382D,
935 PREFIX_VEX_382E,
936 PREFIX_VEX_382F,
937 PREFIX_VEX_3830,
938 PREFIX_VEX_3831,
939 PREFIX_VEX_3832,
940 PREFIX_VEX_3833,
941 PREFIX_VEX_3834,
942 PREFIX_VEX_3835,
943 PREFIX_VEX_3837,
944 PREFIX_VEX_3838,
945 PREFIX_VEX_3839,
946 PREFIX_VEX_383A,
947 PREFIX_VEX_383B,
948 PREFIX_VEX_383C,
949 PREFIX_VEX_383D,
950 PREFIX_VEX_383E,
951 PREFIX_VEX_383F,
952 PREFIX_VEX_3840,
953 PREFIX_VEX_3841,
954 PREFIX_VEX_3896,
955 PREFIX_VEX_3897,
956 PREFIX_VEX_3898,
957 PREFIX_VEX_3899,
958 PREFIX_VEX_389A,
959 PREFIX_VEX_389B,
960 PREFIX_VEX_389C,
961 PREFIX_VEX_389D,
962 PREFIX_VEX_389E,
963 PREFIX_VEX_389F,
964 PREFIX_VEX_38A6,
965 PREFIX_VEX_38A7,
966 PREFIX_VEX_38A8,
967 PREFIX_VEX_38A9,
968 PREFIX_VEX_38AA,
969 PREFIX_VEX_38AB,
970 PREFIX_VEX_38AC,
971 PREFIX_VEX_38AD,
972 PREFIX_VEX_38AE,
973 PREFIX_VEX_38AF,
974 PREFIX_VEX_38B6,
975 PREFIX_VEX_38B7,
976 PREFIX_VEX_38B8,
977 PREFIX_VEX_38B9,
978 PREFIX_VEX_38BA,
979 PREFIX_VEX_38BB,
980 PREFIX_VEX_38BC,
981 PREFIX_VEX_38BD,
982 PREFIX_VEX_38BE,
983 PREFIX_VEX_38BF,
984 PREFIX_VEX_38DB,
985 PREFIX_VEX_38DC,
986 PREFIX_VEX_38DD,
987 PREFIX_VEX_38DE,
988 PREFIX_VEX_38DF,
989 PREFIX_VEX_3A04,
990 PREFIX_VEX_3A05,
991 PREFIX_VEX_3A06,
992 PREFIX_VEX_3A08,
993 PREFIX_VEX_3A09,
994 PREFIX_VEX_3A0A,
995 PREFIX_VEX_3A0B,
996 PREFIX_VEX_3A0C,
997 PREFIX_VEX_3A0D,
998 PREFIX_VEX_3A0E,
999 PREFIX_VEX_3A0F,
1000 PREFIX_VEX_3A14,
1001 PREFIX_VEX_3A15,
1002 PREFIX_VEX_3A16,
1003 PREFIX_VEX_3A17,
1004 PREFIX_VEX_3A18,
1005 PREFIX_VEX_3A19,
1006 PREFIX_VEX_3A20,
1007 PREFIX_VEX_3A21,
1008 PREFIX_VEX_3A22,
1009 PREFIX_VEX_3A40,
1010 PREFIX_VEX_3A41,
1011 PREFIX_VEX_3A42,
1012 PREFIX_VEX_3A44,
1013 PREFIX_VEX_3A4A,
1014 PREFIX_VEX_3A4B,
1015 PREFIX_VEX_3A4C,
1016 PREFIX_VEX_3A5C,
1017 PREFIX_VEX_3A5D,
1018 PREFIX_VEX_3A5E,
1019 PREFIX_VEX_3A5F,
1020 PREFIX_VEX_3A60,
1021 PREFIX_VEX_3A61,
1022 PREFIX_VEX_3A62,
1023 PREFIX_VEX_3A63,
1024 PREFIX_VEX_3A68,
1025 PREFIX_VEX_3A69,
1026 PREFIX_VEX_3A6A,
1027 PREFIX_VEX_3A6B,
1028 PREFIX_VEX_3A6C,
1029 PREFIX_VEX_3A6D,
1030 PREFIX_VEX_3A6E,
1031 PREFIX_VEX_3A6F,
1032 PREFIX_VEX_3A78,
1033 PREFIX_VEX_3A79,
1034 PREFIX_VEX_3A7A,
1035 PREFIX_VEX_3A7B,
1036 PREFIX_VEX_3A7C,
1037 PREFIX_VEX_3A7D,
1038 PREFIX_VEX_3A7E,
1039 PREFIX_VEX_3A7F,
1040 PREFIX_VEX_3ADF
51e7da1b 1041};
4e7d34a6 1042
51e7da1b
L		 1043enum
1044{
1045 X86_64_06 = 0,
3873ba12
L		 1046 X86_64_07,
1047 X86_64_0D,
1048 X86_64_16,
1049 X86_64_17,
1050 X86_64_1E,
1051 X86_64_1F,
1052 X86_64_27,
1053 X86_64_2F,
1054 X86_64_37,
1055 X86_64_3F,
1056 X86_64_60,
1057 X86_64_61,
1058 X86_64_62,
1059 X86_64_63,
1060 X86_64_6D,
1061 X86_64_6F,
1062 X86_64_9A,
1063 X86_64_C4,
1064 X86_64_C5,
1065 X86_64_CE,
1066 X86_64_D4,
1067 X86_64_D5,
1068 X86_64_EA,
1069 X86_64_0F01_REG_0,
1070 X86_64_0F01_REG_1,
1071 X86_64_0F01_REG_2,
1072 X86_64_0F01_REG_3
51e7da1b 1073};
4e7d34a6 1074
51e7da1b
L		 1075enum
1076{
1077 THREE_BYTE_0F38 = 0,
3873ba12
L		 1078 THREE_BYTE_0F3A,
1079 THREE_BYTE_0F7A
51e7da1b 1080};
4e7d34a6 1081
f88c9eb0
SP		 1082enum
1083{
5dd85c99
SP		 1084 XOP_08 = 0,
1085 XOP_09,
f88c9eb0
SP		 1086 XOP_0A
1087};
1088
51e7da1b
L		 1089enum
1090{
1091 VEX_0F = 0,
3873ba12
L		 1092 VEX_0F38,
1093 VEX_0F3A
51e7da1b 1094};
c0f3af97 1095
51e7da1b
L		 1096enum
1097{
1098 VEX_LEN_10_P_1 = 0,
3873ba12
L		 1099 VEX_LEN_10_P_3,
1100 VEX_LEN_11_P_1,
1101 VEX_LEN_11_P_3,
1102 VEX_LEN_12_P_0_M_0,
1103 VEX_LEN_12_P_0_M_1,
1104 VEX_LEN_12_P_2,
1105 VEX_LEN_13_M_0,
1106 VEX_LEN_16_P_0_M_0,
1107 VEX_LEN_16_P_0_M_1,
1108 VEX_LEN_16_P_2,
1109 VEX_LEN_17_M_0,
1110 VEX_LEN_2A_P_1,
1111 VEX_LEN_2A_P_3,
1112 VEX_LEN_2C_P_1,
1113 VEX_LEN_2C_P_3,
1114 VEX_LEN_2D_P_1,
1115 VEX_LEN_2D_P_3,
1116 VEX_LEN_2E_P_0,
1117 VEX_LEN_2E_P_2,
1118 VEX_LEN_2F_P_0,
1119 VEX_LEN_2F_P_2,
1120 VEX_LEN_51_P_1,
1121 VEX_LEN_51_P_3,
1122 VEX_LEN_52_P_1,
1123 VEX_LEN_53_P_1,
1124 VEX_LEN_58_P_1,
1125 VEX_LEN_58_P_3,
1126 VEX_LEN_59_P_1,
1127 VEX_LEN_59_P_3,
1128 VEX_LEN_5A_P_1,
1129 VEX_LEN_5A_P_3,
1130 VEX_LEN_5C_P_1,
1131 VEX_LEN_5C_P_3,
1132 VEX_LEN_5D_P_1,
1133 VEX_LEN_5D_P_3,
1134 VEX_LEN_5E_P_1,
1135 VEX_LEN_5E_P_3,
1136 VEX_LEN_5F_P_1,
1137 VEX_LEN_5F_P_3,
1138 VEX_LEN_60_P_2,
1139 VEX_LEN_61_P_2,
1140 VEX_LEN_62_P_2,
1141 VEX_LEN_63_P_2,
1142 VEX_LEN_64_P_2,
1143 VEX_LEN_65_P_2,
1144 VEX_LEN_66_P_2,
1145 VEX_LEN_67_P_2,
1146 VEX_LEN_68_P_2,
1147 VEX_LEN_69_P_2,
1148 VEX_LEN_6A_P_2,
1149 VEX_LEN_6B_P_2,
1150 VEX_LEN_6C_P_2,
1151 VEX_LEN_6D_P_2,
1152 VEX_LEN_6E_P_2,
1153 VEX_LEN_70_P_1,
1154 VEX_LEN_70_P_2,
1155 VEX_LEN_70_P_3,
1156 VEX_LEN_71_R_2_P_2,
1157 VEX_LEN_71_R_4_P_2,
1158 VEX_LEN_71_R_6_P_2,
1159 VEX_LEN_72_R_2_P_2,
1160 VEX_LEN_72_R_4_P_2,
1161 VEX_LEN_72_R_6_P_2,
1162 VEX_LEN_73_R_2_P_2,
1163 VEX_LEN_73_R_3_P_2,
1164 VEX_LEN_73_R_6_P_2,
1165 VEX_LEN_73_R_7_P_2,
1166 VEX_LEN_74_P_2,
1167 VEX_LEN_75_P_2,
1168 VEX_LEN_76_P_2,
1169 VEX_LEN_7E_P_1,
1170 VEX_LEN_7E_P_2,
1171 VEX_LEN_AE_R_2_M_0,
1172 VEX_LEN_AE_R_3_M_0,
1173 VEX_LEN_C2_P_1,
1174 VEX_LEN_C2_P_3,
1175 VEX_LEN_C4_P_2,
1176 VEX_LEN_C5_P_2,
1177 VEX_LEN_D1_P_2,
1178 VEX_LEN_D2_P_2,
1179 VEX_LEN_D3_P_2,
1180 VEX_LEN_D4_P_2,
1181 VEX_LEN_D5_P_2,
1182 VEX_LEN_D6_P_2,
1183 VEX_LEN_D7_P_2_M_1,
1184 VEX_LEN_D8_P_2,
1185 VEX_LEN_D9_P_2,
1186 VEX_LEN_DA_P_2,
1187 VEX_LEN_DB_P_2,
1188 VEX_LEN_DC_P_2,
1189 VEX_LEN_DD_P_2,
1190 VEX_LEN_DE_P_2,
1191 VEX_LEN_DF_P_2,
1192 VEX_LEN_E0_P_2,
1193 VEX_LEN_E1_P_2,
1194 VEX_LEN_E2_P_2,
1195 VEX_LEN_E3_P_2,
1196 VEX_LEN_E4_P_2,
1197 VEX_LEN_E5_P_2,
1198 VEX_LEN_E8_P_2,
1199 VEX_LEN_E9_P_2,
1200 VEX_LEN_EA_P_2,
1201 VEX_LEN_EB_P_2,
1202 VEX_LEN_EC_P_2,
1203 VEX_LEN_ED_P_2,
1204 VEX_LEN_EE_P_2,
1205 VEX_LEN_EF_P_2,
1206 VEX_LEN_F1_P_2,
1207 VEX_LEN_F2_P_2,
1208 VEX_LEN_F3_P_2,
1209 VEX_LEN_F4_P_2,
1210 VEX_LEN_F5_P_2,
1211 VEX_LEN_F6_P_2,
1212 VEX_LEN_F7_P_2,
1213 VEX_LEN_F8_P_2,
1214 VEX_LEN_F9_P_2,
1215 VEX_LEN_FA_P_2,
1216 VEX_LEN_FB_P_2,
1217 VEX_LEN_FC_P_2,
1218 VEX_LEN_FD_P_2,
1219 VEX_LEN_FE_P_2,
1220 VEX_LEN_3800_P_2,
1221 VEX_LEN_3801_P_2,
1222 VEX_LEN_3802_P_2,
1223 VEX_LEN_3803_P_2,
1224 VEX_LEN_3804_P_2,
1225 VEX_LEN_3805_P_2,
1226 VEX_LEN_3806_P_2,
1227 VEX_LEN_3807_P_2,
1228 VEX_LEN_3808_P_2,
1229 VEX_LEN_3809_P_2,
1230 VEX_LEN_380A_P_2,
1231 VEX_LEN_380B_P_2,
1232 VEX_LEN_3819_P_2_M_0,
1233 VEX_LEN_381A_P_2_M_0,
1234 VEX_LEN_381C_P_2,
1235 VEX_LEN_381D_P_2,
1236 VEX_LEN_381E_P_2,
1237 VEX_LEN_3820_P_2,
1238 VEX_LEN_3821_P_2,
1239 VEX_LEN_3822_P_2,
1240 VEX_LEN_3823_P_2,
1241 VEX_LEN_3824_P_2,
1242 VEX_LEN_3825_P_2,
1243 VEX_LEN_3828_P_2,
1244 VEX_LEN_3829_P_2,
1245 VEX_LEN_382A_P_2_M_0,
1246 VEX_LEN_382B_P_2,
1247 VEX_LEN_3830_P_2,
1248 VEX_LEN_3831_P_2,
1249 VEX_LEN_3832_P_2,
1250 VEX_LEN_3833_P_2,
1251 VEX_LEN_3834_P_2,
1252 VEX_LEN_3835_P_2,
1253 VEX_LEN_3837_P_2,
1254 VEX_LEN_3838_P_2,
1255 VEX_LEN_3839_P_2,
1256 VEX_LEN_383A_P_2,
1257 VEX_LEN_383B_P_2,
1258 VEX_LEN_383C_P_2,
1259 VEX_LEN_383D_P_2,
1260 VEX_LEN_383E_P_2,
1261 VEX_LEN_383F_P_2,
1262 VEX_LEN_3840_P_2,
1263 VEX_LEN_3841_P_2,
1264 VEX_LEN_38DB_P_2,
1265 VEX_LEN_38DC_P_2,
1266 VEX_LEN_38DD_P_2,
1267 VEX_LEN_38DE_P_2,
1268 VEX_LEN_38DF_P_2,
1269 VEX_LEN_3A06_P_2,
1270 VEX_LEN_3A0A_P_2,
1271 VEX_LEN_3A0B_P_2,
1272 VEX_LEN_3A0E_P_2,
1273 VEX_LEN_3A0F_P_2,
1274 VEX_LEN_3A14_P_2,
1275 VEX_LEN_3A15_P_2,
1276 VEX_LEN_3A16_P_2,
1277 VEX_LEN_3A17_P_2,
1278 VEX_LEN_3A18_P_2,
1279 VEX_LEN_3A19_P_2,
1280 VEX_LEN_3A20_P_2,
1281 VEX_LEN_3A21_P_2,
1282 VEX_LEN_3A22_P_2,
1283 VEX_LEN_3A41_P_2,
1284 VEX_LEN_3A42_P_2,
1285 VEX_LEN_3A44_P_2,
1286 VEX_LEN_3A4C_P_2,
1287 VEX_LEN_3A60_P_2,
1288 VEX_LEN_3A61_P_2,
1289 VEX_LEN_3A62_P_2,
1290 VEX_LEN_3A63_P_2,
1291 VEX_LEN_3A6A_P_2,
1292 VEX_LEN_3A6B_P_2,
1293 VEX_LEN_3A6E_P_2,
1294 VEX_LEN_3A6F_P_2,
1295 VEX_LEN_3A7A_P_2,
1296 VEX_LEN_3A7B_P_2,
1297 VEX_LEN_3A7E_P_2,
1298 VEX_LEN_3A7F_P_2,
5dd85c99 1299 VEX_LEN_3ADF_P_2,
5dd85c99
SP		 1300 VEX_LEN_XOP_09_80,
1301 VEX_LEN_XOP_09_81
51e7da1b 1302};
c0f3af97 1303
9e30b8e0
L		 1304enum
1305{
1306 VEX_W_10_P_0 = 0,
1307 VEX_W_10_P_1,
1308 VEX_W_10_P_2,
1309 VEX_W_10_P_3,
1310 VEX_W_11_P_0,
1311 VEX_W_11_P_1,
1312 VEX_W_11_P_2,
1313 VEX_W_11_P_3,
1314 VEX_W_12_P_0_M_0,
1315 VEX_W_12_P_0_M_1,
1316 VEX_W_12_P_1,
1317 VEX_W_12_P_2,
1318 VEX_W_12_P_3,
1319 VEX_W_13_M_0,
1320 VEX_W_14,
1321 VEX_W_15,
1322 VEX_W_16_P_0_M_0,
1323 VEX_W_16_P_0_M_1,
1324 VEX_W_16_P_1,
1325 VEX_W_16_P_2,
1326 VEX_W_17_M_0,
1327 VEX_W_28,
1328 VEX_W_29,
1329 VEX_W_2B_M_0,
1330 VEX_W_2E_P_0,
1331 VEX_W_2E_P_2,
1332 VEX_W_2F_P_0,
1333 VEX_W_2F_P_2,
1334 VEX_W_50_M_0,
1335 VEX_W_51_P_0,
1336 VEX_W_51_P_1,
1337 VEX_W_51_P_2,
1338 VEX_W_51_P_3,
1339 VEX_W_52_P_0,
1340 VEX_W_52_P_1,
1341 VEX_W_53_P_0,
1342 VEX_W_53_P_1,
1343 VEX_W_58_P_0,
1344 VEX_W_58_P_1,
1345 VEX_W_58_P_2,
1346 VEX_W_58_P_3,
1347 VEX_W_59_P_0,
1348 VEX_W_59_P_1,
1349 VEX_W_59_P_2,
1350 VEX_W_59_P_3,
1351 VEX_W_5A_P_0,
1352 VEX_W_5A_P_1,
1353 VEX_W_5A_P_3,
1354 VEX_W_5B_P_0,
1355 VEX_W_5B_P_1,
1356 VEX_W_5B_P_2,
1357 VEX_W_5C_P_0,
1358 VEX_W_5C_P_1,
1359 VEX_W_5C_P_2,
1360 VEX_W_5C_P_3,
1361 VEX_W_5D_P_0,
1362 VEX_W_5D_P_1,
1363 VEX_W_5D_P_2,
1364 VEX_W_5D_P_3,
1365 VEX_W_5E_P_0,
1366 VEX_W_5E_P_1,
1367 VEX_W_5E_P_2,
1368 VEX_W_5E_P_3,
1369 VEX_W_5F_P_0,
1370 VEX_W_5F_P_1,
1371 VEX_W_5F_P_2,
1372 VEX_W_5F_P_3,
1373 VEX_W_60_P_2,
1374 VEX_W_61_P_2,
1375 VEX_W_62_P_2,
1376 VEX_W_63_P_2,
1377 VEX_W_64_P_2,
1378 VEX_W_65_P_2,
1379 VEX_W_66_P_2,
1380 VEX_W_67_P_2,
1381 VEX_W_68_P_2,
1382 VEX_W_69_P_2,
1383 VEX_W_6A_P_2,
1384 VEX_W_6B_P_2,
1385 VEX_W_6C_P_2,
1386 VEX_W_6D_P_2,
1387 VEX_W_6F_P_1,
1388 VEX_W_6F_P_2,
1389 VEX_W_70_P_1,
1390 VEX_W_70_P_2,
1391 VEX_W_70_P_3,
1392 VEX_W_71_R_2_P_2,
1393 VEX_W_71_R_4_P_2,
1394 VEX_W_71_R_6_P_2,
1395 VEX_W_72_R_2_P_2,
1396 VEX_W_72_R_4_P_2,
1397 VEX_W_72_R_6_P_2,
1398 VEX_W_73_R_2_P_2,
1399 VEX_W_73_R_3_P_2,
1400 VEX_W_73_R_6_P_2,
1401 VEX_W_73_R_7_P_2,
1402 VEX_W_74_P_2,
1403 VEX_W_75_P_2,
1404 VEX_W_76_P_2,
1405 VEX_W_77_P_0,
1406 VEX_W_7C_P_2,
1407 VEX_W_7C_P_3,
1408 VEX_W_7D_P_2,
1409 VEX_W_7D_P_3,
1410 VEX_W_7E_P_1,
1411 VEX_W_7F_P_1,
1412 VEX_W_7F_P_2,
1413 VEX_W_AE_R_2_M_0,
1414 VEX_W_AE_R_3_M_0,
1415 VEX_W_C2_P_0,
1416 VEX_W_C2_P_1,
1417 VEX_W_C2_P_2,
1418 VEX_W_C2_P_3,
1419 VEX_W_C4_P_2,
1420 VEX_W_C5_P_2,
1421 VEX_W_D0_P_2,
1422 VEX_W_D0_P_3,
1423 VEX_W_D1_P_2,
1424 VEX_W_D2_P_2,
1425 VEX_W_D3_P_2,
1426 VEX_W_D4_P_2,
1427 VEX_W_D5_P_2,
1428 VEX_W_D6_P_2,
1429 VEX_W_D7_P_2_M_1,
1430 VEX_W_D8_P_2,
1431 VEX_W_D9_P_2,
1432 VEX_W_DA_P_2,
1433 VEX_W_DB_P_2,
1434 VEX_W_DC_P_2,
1435 VEX_W_DD_P_2,
1436 VEX_W_DE_P_2,
1437 VEX_W_DF_P_2,
1438 VEX_W_E0_P_2,
1439 VEX_W_E1_P_2,
1440 VEX_W_E2_P_2,
1441 VEX_W_E3_P_2,
1442 VEX_W_E4_P_2,
1443 VEX_W_E5_P_2,
1444 VEX_W_E6_P_1,
1445 VEX_W_E6_P_2,
1446 VEX_W_E6_P_3,
1447 VEX_W_E7_P_2_M_0,
1448 VEX_W_E8_P_2,
1449 VEX_W_E9_P_2,
1450 VEX_W_EA_P_2,
1451 VEX_W_EB_P_2,
1452 VEX_W_EC_P_2,
1453 VEX_W_ED_P_2,
1454 VEX_W_EE_P_2,
1455 VEX_W_EF_P_2,
1456 VEX_W_F0_P_3_M_0,
1457 VEX_W_F1_P_2,
1458 VEX_W_F2_P_2,
1459 VEX_W_F3_P_2,
1460 VEX_W_F4_P_2,
1461 VEX_W_F5_P_2,
1462 VEX_W_F6_P_2,
1463 VEX_W_F7_P_2,
1464 VEX_W_F8_P_2,
1465 VEX_W_F9_P_2,
1466 VEX_W_FA_P_2,
1467 VEX_W_FB_P_2,
1468 VEX_W_FC_P_2,
1469 VEX_W_FD_P_2,
1470 VEX_W_FE_P_2,
1471 VEX_W_3800_P_2,
1472 VEX_W_3801_P_2,
1473 VEX_W_3802_P_2,
1474 VEX_W_3803_P_2,
1475 VEX_W_3804_P_2,
1476 VEX_W_3805_P_2,
1477 VEX_W_3806_P_2,
1478 VEX_W_3807_P_2,
1479 VEX_W_3808_P_2,
1480 VEX_W_3809_P_2,
1481 VEX_W_380A_P_2,
1482 VEX_W_380B_P_2,
1483 VEX_W_380C_P_2,
1484 VEX_W_380D_P_2,
1485 VEX_W_380E_P_2,
1486 VEX_W_380F_P_2,
1487 VEX_W_3817_P_2,
1488 VEX_W_3819_P_2_M_0,
1489 VEX_W_381A_P_2_M_0,
1490 VEX_W_381C_P_2,
1491 VEX_W_381D_P_2,
1492 VEX_W_381E_P_2,
1493 VEX_W_3820_P_2,
1494 VEX_W_3821_P_2,
1495 VEX_W_3822_P_2,
1496 VEX_W_3823_P_2,
1497 VEX_W_3824_P_2,
1498 VEX_W_3825_P_2,
1499 VEX_W_3828_P_2,
1500 VEX_W_3829_P_2,
1501 VEX_W_382A_P_2_M_0,
1502 VEX_W_382B_P_2,
53aa04a0
L		 1503 VEX_W_382C_P_2_M_0,
1504 VEX_W_382D_P_2_M_0,
1505 VEX_W_382E_P_2_M_0,
1506 VEX_W_382F_P_2_M_0,
9e30b8e0
L		 1507 VEX_W_3830_P_2,
1508 VEX_W_3831_P_2,
1509 VEX_W_3832_P_2,
1510 VEX_W_3833_P_2,
1511 VEX_W_3834_P_2,
1512 VEX_W_3835_P_2,
1513 VEX_W_3837_P_2,
1514 VEX_W_3838_P_2,
1515 VEX_W_3839_P_2,
1516 VEX_W_383A_P_2,
1517 VEX_W_383B_P_2,
1518 VEX_W_383C_P_2,
1519 VEX_W_383D_P_2,
1520 VEX_W_383E_P_2,
1521 VEX_W_383F_P_2,
1522 VEX_W_3840_P_2,
1523 VEX_W_3841_P_2,
1524 VEX_W_38DB_P_2,
1525 VEX_W_38DC_P_2,
1526 VEX_W_38DD_P_2,
1527 VEX_W_38DE_P_2,
1528 VEX_W_38DF_P_2,
1529 VEX_W_3A04_P_2,
1530 VEX_W_3A05_P_2,
1531 VEX_W_3A06_P_2,
1532 VEX_W_3A08_P_2,
1533 VEX_W_3A09_P_2,
1534 VEX_W_3A0A_P_2,
1535 VEX_W_3A0B_P_2,
1536 VEX_W_3A0C_P_2,
1537 VEX_W_3A0D_P_2,
1538 VEX_W_3A0E_P_2,
1539 VEX_W_3A0F_P_2,
1540 VEX_W_3A14_P_2,
1541 VEX_W_3A15_P_2,
1542 VEX_W_3A18_P_2,
1543 VEX_W_3A19_P_2,
1544 VEX_W_3A20_P_2,
1545 VEX_W_3A21_P_2,
1546 VEX_W_3A40_P_2,
1547 VEX_W_3A41_P_2,
1548 VEX_W_3A42_P_2,
1549 VEX_W_3A44_P_2,
1550 VEX_W_3A4A_P_2,
1551 VEX_W_3A4B_P_2,
1552 VEX_W_3A4C_P_2,
1553 VEX_W_3A60_P_2,
1554 VEX_W_3A61_P_2,
1555 VEX_W_3A62_P_2,
1556 VEX_W_3A63_P_2,
1557 VEX_W_3ADF_P_2
1558};
1559
26ca5450 1560typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1561
1562struct dis386 {
2da11e11 1563 const char *name;
ce518a5f
L		 1564 struct
1565 {
1566 op_rtn rtn;
1567 int bytemode;
1568 } op[MAX_OPERANDS];
252b5132
RH		 1569};
1570
1571/* Upper case letters in the instruction names here are macros.
1572 'A' => print 'b' if no register operands or suffix_always is true
1573 'B' => print 'b' if suffix_always is true
9306ca4a 1574 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1575 size prefix
ed7841b3 1576 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1577 suffix_always is true
252b5132 1578 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1579 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1580 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1581 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1582 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1583 for some of the macro letters)
9306ca4a 1584 'J' => print 'l'
42903f7f 1585 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1586 'L' => print 'l' if suffix_always is true
9d141669 1587 'M' => print 'r' if intel_mnemonic is false.
252b5132 1588 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1589 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1590 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1591 or suffix_always is true. print 'q' if rex prefix is present.
1592 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1593 is true
a35ca55a 1594 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1595 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1596 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1597 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1598 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1599 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1600 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1601 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1602 suffix_always is true.
6dd5059a 1603 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1604 '!' => change condition from true to false or from false to true.
98b528ac
L		 1605 '%' => add 1 upper case letter to the macro.
1606
1607 2 upper case letter macros:
c0f3af97
L		 1608 "XY" => print 'x' or 'y' if no register operands or suffix_always
1609 is true.
4b06377f
L		 1610 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1611 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
98b528ac 1612 or suffix_always is true
4b06377f
L		 1613 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1614 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1615 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
52b15da3 1616
6439fc28
AM		 1617 Many of the above letters print nothing in Intel mode. See "putop"
1618 for the details.
52b15da3 1619
6439fc28 1620 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1621 mnemonic strings for AT&T and Intel. */
252b5132 1622
6439fc28 1623static const struct dis386 dis386[] = {
252b5132 1624 /* 00 */
ce518a5f
L		 1625 { "addB", { Eb, Gb } },
1626 { "addS", { Ev, Gv } },
c7532693
L		 1627 { "addB", { Gb, EbS } },
1628 { "addS", { Gv, EvS } },
ce518a5f
L		 1629 { "addB", { AL, Ib } },
1630 { "addS", { eAX, Iv } },
4e7d34a6
L		 1631 { X86_64_TABLE (X86_64_06) },
1632 { X86_64_TABLE (X86_64_07) },
252b5132 1633 /* 08 */
ce518a5f
L		 1634 { "orB", { Eb, Gb } },
1635 { "orS", { Ev, Gv } },
c7532693
L		 1636 { "orB", { Gb, EbS } },
1637 { "orS", { Gv, EvS } },
ce518a5f
L		 1638 { "orB", { AL, Ib } },
1639 { "orS", { eAX, Iv } },
4e7d34a6 1640 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1641 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1642 /* 10 */
ce518a5f
L		 1643 { "adcB", { Eb, Gb } },
1644 { "adcS", { Ev, Gv } },
c7532693
L		 1645 { "adcB", { Gb, EbS } },
1646 { "adcS", { Gv, EvS } },
ce518a5f
L		 1647 { "adcB", { AL, Ib } },
1648 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1649 { X86_64_TABLE (X86_64_16) },
1650 { X86_64_TABLE (X86_64_17) },
252b5132 1651 /* 18 */
ce518a5f
L		 1652 { "sbbB", { Eb, Gb } },
1653 { "sbbS", { Ev, Gv } },
c7532693
L		 1654 { "sbbB", { Gb, EbS } },
1655 { "sbbS", { Gv, EvS } },
ce518a5f
L		 1656 { "sbbB", { AL, Ib } },
1657 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1658 { X86_64_TABLE (X86_64_1E) },
1659 { X86_64_TABLE (X86_64_1F) },
252b5132 1660 /* 20 */
ce518a5f
L		 1661 { "andB", { Eb, Gb } },
1662 { "andS", { Ev, Gv } },
c7532693
L		 1663 { "andB", { Gb, EbS } },
1664 { "andS", { Gv, EvS } },
ce518a5f
L		 1665 { "andB", { AL, Ib } },
1666 { "andS", { eAX, Iv } },
1667 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1668 { X86_64_TABLE (X86_64_27) },
252b5132 1669 /* 28 */
ce518a5f
L		 1670 { "subB", { Eb, Gb } },
1671 { "subS", { Ev, Gv } },
c7532693
L		 1672 { "subB", { Gb, EbS } },
1673 { "subS", { Gv, EvS } },
ce518a5f
L		 1674 { "subB", { AL, Ib } },
1675 { "subS", { eAX, Iv } },
1676 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1677 { X86_64_TABLE (X86_64_2F) },
252b5132 1678 /* 30 */
ce518a5f
L		 1679 { "xorB", { Eb, Gb } },
1680 { "xorS", { Ev, Gv } },
c7532693
L		 1681 { "xorB", { Gb, EbS } },
1682 { "xorS", { Gv, EvS } },
ce518a5f
L		 1683 { "xorB", { AL, Ib } },
1684 { "xorS", { eAX, Iv } },
1685 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1686 { X86_64_TABLE (X86_64_37) },
252b5132 1687 /* 38 */
ce518a5f
L		 1688 { "cmpB", { Eb, Gb } },
1689 { "cmpS", { Ev, Gv } },
c7532693
L		 1690 { "cmpB", { Gb, EbS } },
1691 { "cmpS", { Gv, EvS } },
ce518a5f
L		 1692 { "cmpB", { AL, Ib } },
1693 { "cmpS", { eAX, Iv } },
1694 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1695 { X86_64_TABLE (X86_64_3F) },
252b5132 1696 /* 40 */
ce518a5f
L		 1697 { "inc{S|}", { RMeAX } },
1698 { "inc{S|}", { RMeCX } },
1699 { "inc{S|}", { RMeDX } },
1700 { "inc{S|}", { RMeBX } },
1701 { "inc{S|}", { RMeSP } },
1702 { "inc{S|}", { RMeBP } },
1703 { "inc{S|}", { RMeSI } },
1704 { "inc{S|}", { RMeDI } },
252b5132 1705 /* 48 */
ce518a5f
L		 1706 { "dec{S|}", { RMeAX } },
1707 { "dec{S|}", { RMeCX } },
1708 { "dec{S|}", { RMeDX } },
1709 { "dec{S|}", { RMeBX } },
1710 { "dec{S|}", { RMeSP } },
1711 { "dec{S|}", { RMeBP } },
1712 { "dec{S|}", { RMeSI } },
1713 { "dec{S|}", { RMeDI } },
252b5132 1714 /* 50 */
ce518a5f
L		 1715 { "pushV", { RMrAX } },
1716 { "pushV", { RMrCX } },
1717 { "pushV", { RMrDX } },
1718 { "pushV", { RMrBX } },
1719 { "pushV", { RMrSP } },
1720 { "pushV", { RMrBP } },
1721 { "pushV", { RMrSI } },
1722 { "pushV", { RMrDI } },
252b5132 1723 /* 58 */
ce518a5f
L		 1724 { "popV", { RMrAX } },
1725 { "popV", { RMrCX } },
1726 { "popV", { RMrDX } },
1727 { "popV", { RMrBX } },
1728 { "popV", { RMrSP } },
1729 { "popV", { RMrBP } },
1730 { "popV", { RMrSI } },
1731 { "popV", { RMrDI } },
252b5132 1732 /* 60 */
4e7d34a6
L		 1733 { X86_64_TABLE (X86_64_60) },
1734 { X86_64_TABLE (X86_64_61) },
1735 { X86_64_TABLE (X86_64_62) },
1736 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1737 { "(bad)", { XX } }, /* seg fs */
1738 { "(bad)", { XX } }, /* seg gs */
1739 { "(bad)", { XX } }, /* op size prefix */
1740 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1741 /* 68 */
ce518a5f
L		 1742 { "pushT", { Iq } },
1743 { "imulS", { Gv, Ev, Iv } },
1744 { "pushT", { sIb } },
1745 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1746 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1747 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1748 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1749 { X86_64_TABLE (X86_64_6F) },
252b5132 1750 /* 70 */
ce518a5f
L		 1751 { "joH", { Jb, XX, cond_jump_flag } },
1752 { "jnoH", { Jb, XX, cond_jump_flag } },
1753 { "jbH", { Jb, XX, cond_jump_flag } },
1754 { "jaeH", { Jb, XX, cond_jump_flag } },
1755 { "jeH", { Jb, XX, cond_jump_flag } },
1756 { "jneH", { Jb, XX, cond_jump_flag } },
1757 { "jbeH", { Jb, XX, cond_jump_flag } },
1758 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1759 /* 78 */
ce518a5f
L		 1760 { "jsH", { Jb, XX, cond_jump_flag } },
1761 { "jnsH", { Jb, XX, cond_jump_flag } },
1762 { "jpH", { Jb, XX, cond_jump_flag } },
1763 { "jnpH", { Jb, XX, cond_jump_flag } },
1764 { "jlH", { Jb, XX, cond_jump_flag } },
1765 { "jgeH", { Jb, XX, cond_jump_flag } },
1766 { "jleH", { Jb, XX, cond_jump_flag } },
1767 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1768 /* 80 */
1ceb70f8
L		 1769 { REG_TABLE (REG_80) },
1770 { REG_TABLE (REG_81) },
ce518a5f 1771 { "(bad)", { XX } },
1ceb70f8 1772 { REG_TABLE (REG_82) },
ce518a5f
L		 1773 { "testB", { Eb, Gb } },
1774 { "testS", { Ev, Gv } },
1775 { "xchgB", { Eb, Gb } },
1776 { "xchgS", { Ev, Gv } },
252b5132 1777 /* 88 */
ce518a5f
L		 1778 { "movB", { Eb, Gb } },
1779 { "movS", { Ev, Gv } },
b6169b20
L		 1780 { "movB", { Gb, EbS } },
1781 { "movS", { Gv, EvS } },
ce518a5f 1782 { "movD", { Sv, Sw } },
1ceb70f8 1783 { MOD_TABLE (MOD_8D) },
ce518a5f 1784 { "movD", { Sw, Sv } },
1ceb70f8 1785 { REG_TABLE (REG_8F) },
252b5132 1786 /* 90 */
1ceb70f8 1787 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1788 { "xchgS", { RMeCX, eAX } },
1789 { "xchgS", { RMeDX, eAX } },
1790 { "xchgS", { RMeBX, eAX } },
1791 { "xchgS", { RMeSP, eAX } },
1792 { "xchgS", { RMeBP, eAX } },
1793 { "xchgS", { RMeSI, eAX } },
1794 { "xchgS", { RMeDI, eAX } },
252b5132 1795 /* 98 */
7c52e0e8
L		 1796 { "cW{t|}R", { XX } },
1797 { "cR{t|}O", { XX } },
4e7d34a6 1798 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1799 { "(bad)", { XX } }, /* fwait */
1800 { "pushfT", { XX } },
1801 { "popfT", { XX } },
7c52e0e8
L		 1802 { "sahf", { XX } },
1803 { "lahf", { XX } },
252b5132 1804 /* a0 */
4b06377f
L		 1805 { "mov%LB", { AL, Ob } },
1806 { "mov%LS", { eAX, Ov } },
1807 { "mov%LB", { Ob, AL } },
1808 { "mov%LS", { Ov, eAX } },
7c52e0e8
L		 1809 { "movs{b|}", { Ybr, Xb } },
1810 { "movs{R|}", { Yvr, Xv } },
1811 { "cmps{b|}", { Xb, Yb } },
1812 { "cmps{R|}", { Xv, Yv } },
252b5132 1813 /* a8 */
ce518a5f
L		 1814 { "testB", { AL, Ib } },
1815 { "testS", { eAX, Iv } },
1816 { "stosB", { Ybr, AL } },
1817 { "stosS", { Yvr, eAX } },
1818 { "lodsB", { ALr, Xb } },
1819 { "lodsS", { eAXr, Xv } },
1820 { "scasB", { AL, Yb } },
1821 { "scasS", { eAX, Yv } },
252b5132 1822 /* b0 */
ce518a5f
L		 1823 { "movB", { RMAL, Ib } },
1824 { "movB", { RMCL, Ib } },
1825 { "movB", { RMDL, Ib } },
1826 { "movB", { RMBL, Ib } },
1827 { "movB", { RMAH, Ib } },
1828 { "movB", { RMCH, Ib } },
1829 { "movB", { RMDH, Ib } },
1830 { "movB", { RMBH, Ib } },
252b5132 1831 /* b8 */
4b06377f
L		 1832 { "mov%LV", { RMeAX, Iv64 } },
1833 { "mov%LV", { RMeCX, Iv64 } },
1834 { "mov%LV", { RMeDX, Iv64 } },
1835 { "mov%LV", { RMeBX, Iv64 } },
1836 { "mov%LV", { RMeSP, Iv64 } },
1837 { "mov%LV", { RMeBP, Iv64 } },
1838 { "mov%LV", { RMeSI, Iv64 } },
1839 { "mov%LV", { RMeDI, Iv64 } },
252b5132 1840 /* c0 */
1ceb70f8
L		 1841 { REG_TABLE (REG_C0) },
1842 { REG_TABLE (REG_C1) },
ce518a5f
L		 1843 { "retT", { Iw } },
1844 { "retT", { XX } },
4e7d34a6
L		 1845 { X86_64_TABLE (X86_64_C4) },
1846 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1847 { REG_TABLE (REG_C6) },
1848 { REG_TABLE (REG_C7) },
252b5132 1849 /* c8 */
ce518a5f
L		 1850 { "enterT", { Iw, Ib } },
1851 { "leaveT", { XX } },
ddab3d59
JB		 1852 { "Jret{|f}P", { Iw } },
1853 { "Jret{|f}P", { XX } },
ce518a5f
L		 1854 { "int3", { XX } },
1855 { "int", { Ib } },
4e7d34a6 1856 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1857 { "iretP", { XX } },
252b5132 1858 /* d0 */
1ceb70f8
L		 1859 { REG_TABLE (REG_D0) },
1860 { REG_TABLE (REG_D1) },
1861 { REG_TABLE (REG_D2) },
1862 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1863 { X86_64_TABLE (X86_64_D4) },
1864 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1865 { "(bad)", { XX } },
1866 { "xlat", { DSBX } },
252b5132
RH		 1867 /* d8 */
1868 { FLOAT },
1869 { FLOAT },
1870 { FLOAT },
1871 { FLOAT },
1872 { FLOAT },
1873 { FLOAT },
1874 { FLOAT },
1875 { FLOAT },
1876 /* e0 */
ce518a5f
L		 1877 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1878 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1879 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1880 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1881 { "inB", { AL, Ib } },
1882 { "inG", { zAX, Ib } },
1883 { "outB", { Ib, AL } },
1884 { "outG", { Ib, zAX } },
252b5132 1885 /* e8 */
ce518a5f
L		 1886 { "callT", { Jv } },
1887 { "jmpT", { Jv } },
4e7d34a6 1888 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1889 { "jmp", { Jb } },
1890 { "inB", { AL, indirDX } },
1891 { "inG", { zAX, indirDX } },
1892 { "outB", { indirDX, AL } },
1893 { "outG", { indirDX, zAX } },
252b5132 1894 /* f0 */
ce518a5f
L		 1895 { "(bad)", { XX } }, /* lock prefix */
1896 { "icebp", { XX } },
1897 { "(bad)", { XX } }, /* repne */
1898 { "(bad)", { XX } }, /* repz */
1899 { "hlt", { XX } },
1900 { "cmc", { XX } },
1ceb70f8
L		 1901 { REG_TABLE (REG_F6) },
1902 { REG_TABLE (REG_F7) },
252b5132 1903 /* f8 */
ce518a5f
L		 1904 { "clc", { XX } },
1905 { "stc", { XX } },
1906 { "cli", { XX } },
1907 { "sti", { XX } },
1908 { "cld", { XX } },
1909 { "std", { XX } },
1ceb70f8
L		 1910 { REG_TABLE (REG_FE) },
1911 { REG_TABLE (REG_FF) },
252b5132
RH		 1912};
1913
6439fc28 1914static const struct dis386 dis386_twobyte[] = {
252b5132 1915 /* 00 */
1ceb70f8
L		 1916 { REG_TABLE (REG_0F00 ) },
1917 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1918 { "larS", { Gv, Ew } },
1919 { "lslS", { Gv, Ew } },
1920 { "(bad)", { XX } },
1921 { "syscall", { XX } },
1922 { "clts", { XX } },
1923 { "sysretP", { XX } },
252b5132 1924 /* 08 */
ce518a5f
L		 1925 { "invd", { XX } },
1926 { "wbinvd", { XX } },
1927 { "(bad)", { XX } },
1928 { "ud2a", { XX } },
1929 { "(bad)", { XX } },
b5b1fc4f 1930 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1931 { "femms", { XX } },
1932 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1933 /* 10 */
1ceb70f8
L		 1934 { PREFIX_TABLE (PREFIX_0F10) },
1935 { PREFIX_TABLE (PREFIX_0F11) },
1936 { PREFIX_TABLE (PREFIX_0F12) },
1937 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1938 { "unpcklpX", { XM, EXx } },
1939 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1940 { PREFIX_TABLE (PREFIX_0F16) },
1941 { MOD_TABLE (MOD_0F17) },
252b5132 1942 /* 18 */
1ceb70f8 1943 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1944 { "nopQ", { Ev } },
1945 { "nopQ", { Ev } },
1946 { "nopQ", { Ev } },
1947 { "nopQ", { Ev } },
1948 { "nopQ", { Ev } },
1949 { "nopQ", { Ev } },
ce518a5f 1950 { "nopQ", { Ev } },
252b5132 1951 /* 20 */
1ceb70f8
L		 1952 { MOD_TABLE (MOD_0F20) },
1953 { MOD_TABLE (MOD_0F21) },
1954 { MOD_TABLE (MOD_0F22) },
1955 { MOD_TABLE (MOD_0F23) },
1956 { MOD_TABLE (MOD_0F24) },
c1e679ec 1957 { "(bad)", { XX } },
1ceb70f8 1958 { MOD_TABLE (MOD_0F26) },
ce518a5f 1959 { "(bad)", { XX } },
252b5132 1960 /* 28 */
09a2c6cf 1961 { "movapX", { XM, EXx } },
b6169b20 1962 { "movapX", { EXxS, XM } },
1ceb70f8
L		 1963 { PREFIX_TABLE (PREFIX_0F2A) },
1964 { PREFIX_TABLE (PREFIX_0F2B) },
1965 { PREFIX_TABLE (PREFIX_0F2C) },
1966 { PREFIX_TABLE (PREFIX_0F2D) },
1967 { PREFIX_TABLE (PREFIX_0F2E) },
1968 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1969 /* 30 */
ce518a5f
L		 1970 { "wrmsr", { XX } },
1971 { "rdtsc", { XX } },
1972 { "rdmsr", { XX } },
1973 { "rdpmc", { XX } },
1974 { "sysenter", { XX } },
1975 { "sysexit", { XX } },
1976 { "(bad)", { XX } },
47dd174c 1977 { "getsec", { XX } },
252b5132 1978 /* 38 */
4e7d34a6 1979 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1980 { "(bad)", { XX } },
4e7d34a6 1981 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1982 { "(bad)", { XX } },
1983 { "(bad)", { XX } },
1984 { "(bad)", { XX } },
1985 { "(bad)", { XX } },
1986 { "(bad)", { XX } },
252b5132 1987 /* 40 */
b19d5385
JB		 1988 { "cmovoS", { Gv, Ev } },
1989 { "cmovnoS", { Gv, Ev } },
1990 { "cmovbS", { Gv, Ev } },
1991 { "cmovaeS", { Gv, Ev } },
1992 { "cmoveS", { Gv, Ev } },
1993 { "cmovneS", { Gv, Ev } },
1994 { "cmovbeS", { Gv, Ev } },
1995 { "cmovaS", { Gv, Ev } },
252b5132 1996 /* 48 */
b19d5385
JB		 1997 { "cmovsS", { Gv, Ev } },
1998 { "cmovnsS", { Gv, Ev } },
1999 { "cmovpS", { Gv, Ev } },
2000 { "cmovnpS", { Gv, Ev } },
2001 { "cmovlS", { Gv, Ev } },
2002 { "cmovgeS", { Gv, Ev } },
2003 { "cmovleS", { Gv, Ev } },
2004 { "cmovgS", { Gv, Ev } },
252b5132 2005 /* 50 */
75c135a8 2006 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 2007 { PREFIX_TABLE (PREFIX_0F51) },
2008 { PREFIX_TABLE (PREFIX_0F52) },
2009 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 2010 { "andpX", { XM, EXx } },
2011 { "andnpX", { XM, EXx } },
2012 { "orpX", { XM, EXx } },
2013 { "xorpX", { XM, EXx } },
252b5132 2014 /* 58 */
1ceb70f8
L		 2015 { PREFIX_TABLE (PREFIX_0F58) },
2016 { PREFIX_TABLE (PREFIX_0F59) },
2017 { PREFIX_TABLE (PREFIX_0F5A) },
2018 { PREFIX_TABLE (PREFIX_0F5B) },
2019 { PREFIX_TABLE (PREFIX_0F5C) },
2020 { PREFIX_TABLE (PREFIX_0F5D) },
2021 { PREFIX_TABLE (PREFIX_0F5E) },
2022 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 2023 /* 60 */
1ceb70f8
L		 2024 { PREFIX_TABLE (PREFIX_0F60) },
2025 { PREFIX_TABLE (PREFIX_0F61) },
2026 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 2027 { "packsswb", { MX, EM } },
2028 { "pcmpgtb", { MX, EM } },
2029 { "pcmpgtw", { MX, EM } },
2030 { "pcmpgtd", { MX, EM } },
2031 { "packuswb", { MX, EM } },
252b5132 2032 /* 68 */
ce518a5f
L		 2033 { "punpckhbw", { MX, EM } },
2034 { "punpckhwd", { MX, EM } },
2035 { "punpckhdq", { MX, EM } },
2036 { "packssdw", { MX, EM } },
1ceb70f8
L		 2037 { PREFIX_TABLE (PREFIX_0F6C) },
2038 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 2039 { "movK", { MX, Edq } },
1ceb70f8 2040 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 2041 /* 70 */
1ceb70f8
L		 2042 { PREFIX_TABLE (PREFIX_0F70) },
2043 { REG_TABLE (REG_0F71) },
2044 { REG_TABLE (REG_0F72) },
2045 { REG_TABLE (REG_0F73) },
ce518a5f
L		 2046 { "pcmpeqb", { MX, EM } },
2047 { "pcmpeqw", { MX, EM } },
2048 { "pcmpeqd", { MX, EM } },
2049 { "emms", { XX } },
252b5132 2050 /* 78 */
1ceb70f8
L		 2051 { PREFIX_TABLE (PREFIX_0F78) },
2052 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 2053 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
c1e679ec 2054 { "(bad)", { XX } },
1ceb70f8
L		 2055 { PREFIX_TABLE (PREFIX_0F7C) },
2056 { PREFIX_TABLE (PREFIX_0F7D) },
2057 { PREFIX_TABLE (PREFIX_0F7E) },
2058 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 2059 /* 80 */
ce518a5f
L		 2060 { "joH", { Jv, XX, cond_jump_flag } },
2061 { "jnoH", { Jv, XX, cond_jump_flag } },
2062 { "jbH", { Jv, XX, cond_jump_flag } },
2063 { "jaeH", { Jv, XX, cond_jump_flag } },
2064 { "jeH", { Jv, XX, cond_jump_flag } },
2065 { "jneH", { Jv, XX, cond_jump_flag } },
2066 { "jbeH", { Jv, XX, cond_jump_flag } },
2067 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 2068 /* 88 */
ce518a5f
L		 2069 { "jsH", { Jv, XX, cond_jump_flag } },
2070 { "jnsH", { Jv, XX, cond_jump_flag } },
2071 { "jpH", { Jv, XX, cond_jump_flag } },
2072 { "jnpH", { Jv, XX, cond_jump_flag } },
2073 { "jlH", { Jv, XX, cond_jump_flag } },
2074 { "jgeH", { Jv, XX, cond_jump_flag } },
2075 { "jleH", { Jv, XX, cond_jump_flag } },
2076 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 2077 /* 90 */
ce518a5f
L		 2078 { "seto", { Eb } },
2079 { "setno", { Eb } },
2080 { "setb", { Eb } },
2081 { "setae", { Eb } },
2082 { "sete", { Eb } },
2083 { "setne", { Eb } },
2084 { "setbe", { Eb } },
2085 { "seta", { Eb } },
252b5132 2086 /* 98 */
ce518a5f
L		 2087 { "sets", { Eb } },
2088 { "setns", { Eb } },
2089 { "setp", { Eb } },
2090 { "setnp", { Eb } },
2091 { "setl", { Eb } },
2092 { "setge", { Eb } },
2093 { "setle", { Eb } },
2094 { "setg", { Eb } },
252b5132 2095 /* a0 */
ce518a5f
L		 2096 { "pushT", { fs } },
2097 { "popT", { fs } },
2098 { "cpuid", { XX } },
2099 { "btS", { Ev, Gv } },
2100 { "shldS", { Ev, Gv, Ib } },
2101 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 2102 { REG_TABLE (REG_0FA6) },
2103 { REG_TABLE (REG_0FA7) },
252b5132 2104 /* a8 */
ce518a5f
L		 2105 { "pushT", { gs } },
2106 { "popT", { gs } },
2107 { "rsm", { XX } },
2108 { "btsS", { Ev, Gv } },
2109 { "shrdS", { Ev, Gv, Ib } },
2110 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 2111 { REG_TABLE (REG_0FAE) },
ce518a5f 2112 { "imulS", { Gv, Ev } },
252b5132 2113 /* b0 */
ce518a5f
L		 2114 { "cmpxchgB", { Eb, Gb } },
2115 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 2116 { MOD_TABLE (MOD_0FB2) },
ce518a5f 2117 { "btrS", { Ev, Gv } },
1ceb70f8
L		 2118 { MOD_TABLE (MOD_0FB4) },
2119 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 2120 { "movz{bR|x}", { Gv, Eb } },
2121 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 2122 /* b8 */
1ceb70f8 2123 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 2124 { "ud2b", { XX } },
1ceb70f8 2125 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 2126 { "btcS", { Ev, Gv } },
2127 { "bsfS", { Gv, Ev } },
1ceb70f8 2128 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 2129 { "movs{bR|x}", { Gv, Eb } },
2130 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 2131 /* c0 */
ce518a5f
L		 2132 { "xaddB", { Eb, Gb } },
2133 { "xaddS", { Ev, Gv } },
1ceb70f8 2134 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 2135 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 2136 { "pinsrw", { MX, Edqw, Ib } },
2137 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 2138 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 2139 { REG_TABLE (REG_0FC7) },
252b5132 2140 /* c8 */
ce518a5f
L		 2141 { "bswap", { RMeAX } },
2142 { "bswap", { RMeCX } },
2143 { "bswap", { RMeDX } },
2144 { "bswap", { RMeBX } },
2145 { "bswap", { RMeSP } },
2146 { "bswap", { RMeBP } },
2147 { "bswap", { RMeSI } },
2148 { "bswap", { RMeDI } },
252b5132 2149 /* d0 */
1ceb70f8 2150 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 2151 { "psrlw", { MX, EM } },
2152 { "psrld", { MX, EM } },
2153 { "psrlq", { MX, EM } },
2154 { "paddq", { MX, EM } },
2155 { "pmullw", { MX, EM } },
1ceb70f8 2156 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 2157 { MOD_TABLE (MOD_0FD7) },
252b5132 2158 /* d8 */
ce518a5f
L		 2159 { "psubusb", { MX, EM } },
2160 { "psubusw", { MX, EM } },
2161 { "pminub", { MX, EM } },
2162 { "pand", { MX, EM } },
2163 { "paddusb", { MX, EM } },
2164 { "paddusw", { MX, EM } },
2165 { "pmaxub", { MX, EM } },
2166 { "pandn", { MX, EM } },
252b5132 2167 /* e0 */
ce518a5f
L		 2168 { "pavgb", { MX, EM } },
2169 { "psraw", { MX, EM } },
2170 { "psrad", { MX, EM } },
2171 { "pavgw", { MX, EM } },
2172 { "pmulhuw", { MX, EM } },
2173 { "pmulhw", { MX, EM } },
1ceb70f8
L		 2174 { PREFIX_TABLE (PREFIX_0FE6) },
2175 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 2176 /* e8 */
ce518a5f
L		 2177 { "psubsb", { MX, EM } },
2178 { "psubsw", { MX, EM } },
2179 { "pminsw", { MX, EM } },
2180 { "por", { MX, EM } },
2181 { "paddsb", { MX, EM } },
2182 { "paddsw", { MX, EM } },
2183 { "pmaxsw", { MX, EM } },
2184 { "pxor", { MX, EM } },
252b5132 2185 /* f0 */
1ceb70f8 2186 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 2187 { "psllw", { MX, EM } },
2188 { "pslld", { MX, EM } },
2189 { "psllq", { MX, EM } },
2190 { "pmuludq", { MX, EM } },
2191 { "pmaddwd", { MX, EM } },
2192 { "psadbw", { MX, EM } },
1ceb70f8 2193 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 2194 /* f8 */
ce518a5f
L		 2195 { "psubb", { MX, EM } },
2196 { "psubw", { MX, EM } },
2197 { "psubd", { MX, EM } },
2198 { "psubq", { MX, EM } },
2199 { "paddb", { MX, EM } },
2200 { "paddw", { MX, EM } },
2201 { "paddd", { MX, EM } },
2202 { "(bad)", { XX } },
252b5132
RH		 2203};
2204
2205static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 2206 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2207 /* ------------------------------- */
2208 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2209 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2210 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2211 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2212 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2213 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2214 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2215 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2216 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2217 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2218 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2219 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2220 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2221 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2222 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2223 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2224 /* ------------------------------- */
2225 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 2226};
2227
2228static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 2229 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2230 /* ------------------------------- */
252b5132 2231 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 2232 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 2233 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 2234 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 2235 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 2236 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2237 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 2238 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 2239 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2240 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 2241 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 2242 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 2243 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 2244 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 2245 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 2246 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 2247 /* ------------------------------- */
2248 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2249};
2250
252b5132
RH		 2251static char obuf[100];
2252static char *obufp;
ea397f5b 2253static char *mnemonicendp;
252b5132
RH		 2254static char scratchbuf[100];
2255static unsigned char *start_codep;
2256static unsigned char *insn_codep;
2257static unsigned char *codep;
f16cd0d5
L		 2258static int last_lock_prefix;
2259static int last_repz_prefix;
2260static int last_repnz_prefix;
2261static int last_data_prefix;
2262static int last_addr_prefix;
2263static int last_rex_prefix;
2264static int last_seg_prefix;
2265#define MAX_CODE_LENGTH 15
2266/* We can up to 14 prefixes since the maximum instruction length is
2267 15bytes. */
2268static int all_prefixes[MAX_CODE_LENGTH - 1];
252b5132 2269static disassemble_info *the_info;
7967e09e
L		 2270static struct
2271 {
2272 int mod;
7967e09e 2273 int reg;
484c222e 2274 int rm;
7967e09e
L		 2275 }
2276modrm;
4bba6815 2277static unsigned char need_modrm;
c0f3af97
L		 2278static struct
2279 {
2280 int register_specifier;
2281 int length;
2282 int prefix;
2283 int w;
2284 }
2285vex;
2286static unsigned char need_vex;
2287static unsigned char need_vex_reg;
dae39acc 2288static unsigned char vex_w_done;
252b5132 2289
ea397f5b
L		 2290struct op
2291 {
2292 const char *name;
2293 unsigned int len;
2294 };
2295
4bba6815
AM		 2296/* If we are accessing mod/rm/reg without need_modrm set, then the
2297 values are stale. Hitting this abort likely indicates that you
2298 need to update onebyte_has_modrm or twobyte_has_modrm. */
2299#define MODRM_CHECK if (!need_modrm) abort ()
2300
d708bcba
AM		 2301static const char **names64;
2302static const char **names32;
2303static const char **names16;
2304static const char **names8;
2305static const char **names8rex;
2306static const char **names_seg;
db51cc60
L		 2307static const char *index64;
2308static const char *index32;
d708bcba
AM		 2309static const char **index16;
2310
2311static const char *intel_names64[] = {
2312 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2313 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2314};
2315static const char *intel_names32[] = {
2316 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2317 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2318};
2319static const char *intel_names16[] = {
2320 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2321 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2322};
2323static const char *intel_names8[] = {
2324 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2325};
2326static const char *intel_names8rex[] = {
2327 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2328 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2329};
2330static const char *intel_names_seg[] = {
2331 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2332};
db51cc60
L		 2333static const char *intel_index64 = "riz";
2334static const char *intel_index32 = "eiz";
d708bcba
AM		 2335static const char *intel_index16[] = {
2336 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2337};
2338
2339static const char *att_names64[] = {
2340 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 2341 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2342};
d708bcba
AM		 2343static const char *att_names32[] = {
2344 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2345 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2346};
d708bcba
AM		 2347static const char *att_names16[] = {
2348 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2349 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2350};
d708bcba
AM		 2351static const char *att_names8[] = {
2352 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2353};
d708bcba
AM		 2354static const char *att_names8rex[] = {
2355 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2356 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2357};
d708bcba
AM		 2358static const char *att_names_seg[] = {
2359 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2360};
db51cc60
L		 2361static const char *att_index64 = "%riz";
2362static const char *att_index32 = "%eiz";
d708bcba
AM		 2363static const char *att_index16[] = {
2364 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2365};
2366
1ceb70f8
L		 2367static const struct dis386 reg_table[][8] = {
2368 /* REG_80 */
252b5132 2369 {
ce518a5f
L		 2370 { "addA", { Eb, Ib } },
2371 { "orA", { Eb, Ib } },
2372 { "adcA", { Eb, Ib } },
2373 { "sbbA", { Eb, Ib } },
2374 { "andA", { Eb, Ib } },
2375 { "subA", { Eb, Ib } },
2376 { "xorA", { Eb, Ib } },
2377 { "cmpA", { Eb, Ib } },
252b5132 2378 },
1ceb70f8 2379 /* REG_81 */
252b5132 2380 {
ce518a5f
L		 2381 { "addQ", { Ev, Iv } },
2382 { "orQ", { Ev, Iv } },
2383 { "adcQ", { Ev, Iv } },
2384 { "sbbQ", { Ev, Iv } },
2385 { "andQ", { Ev, Iv } },
2386 { "subQ", { Ev, Iv } },
2387 { "xorQ", { Ev, Iv } },
2388 { "cmpQ", { Ev, Iv } },
252b5132 2389 },
1ceb70f8 2390 /* REG_82 */
252b5132 2391 {
ce518a5f
L		 2392 { "addQ", { Ev, sIb } },
2393 { "orQ", { Ev, sIb } },
2394 { "adcQ", { Ev, sIb } },
2395 { "sbbQ", { Ev, sIb } },
2396 { "andQ", { Ev, sIb } },
2397 { "subQ", { Ev, sIb } },
2398 { "xorQ", { Ev, sIb } },
2399 { "cmpQ", { Ev, sIb } },
252b5132 2400 },
1ceb70f8 2401 /* REG_8F */
4e7d34a6
L		 2402 {
2403 { "popU", { stackEv } },
c48244a5 2404 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2405 { "(bad)", { XX } },
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
f88c9eb0 2408 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2409 { "(bad)", { XX } },
2410 { "(bad)", { XX } },
2411 },
1ceb70f8 2412 /* REG_C0 */
252b5132 2413 {
ce518a5f
L		 2414 { "rolA", { Eb, Ib } },
2415 { "rorA", { Eb, Ib } },
2416 { "rclA", { Eb, Ib } },
2417 { "rcrA", { Eb, Ib } },
2418 { "shlA", { Eb, Ib } },
2419 { "shrA", { Eb, Ib } },
2420 { "(bad)", { XX } },
2421 { "sarA", { Eb, Ib } },
252b5132 2422 },
1ceb70f8 2423 /* REG_C1 */
252b5132 2424 {
ce518a5f
L		 2425 { "rolQ", { Ev, Ib } },
2426 { "rorQ", { Ev, Ib } },
2427 { "rclQ", { Ev, Ib } },
2428 { "rcrQ", { Ev, Ib } },
2429 { "shlQ", { Ev, Ib } },
2430 { "shrQ", { Ev, Ib } },
2431 { "(bad)", { XX } },
2432 { "sarQ", { Ev, Ib } },
252b5132 2433 },
1ceb70f8 2434 /* REG_C6 */
4e7d34a6
L		 2435 {
2436 { "movA", { Eb, Ib } },
2437 { "(bad)", { XX } },
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { "(bad)", { XX } },
2441 { "(bad)", { XX } },
2442 { "(bad)", { XX } },
2443 { "(bad)", { XX } },
2444 },
1ceb70f8 2445 /* REG_C7 */
4e7d34a6
L		 2446 {
2447 { "movQ", { Ev, Iv } },
2448 { "(bad)", { XX } },
2449 { "(bad)", { XX } },
2450 { "(bad)", { XX } },
2451 { "(bad)", { XX } },
2452 { "(bad)", { XX } },
2453 { "(bad)", { XX } },
2454 { "(bad)", { XX } },
2455 },
1ceb70f8 2456 /* REG_D0 */
252b5132 2457 {
ce518a5f
L		 2458 { "rolA", { Eb, I1 } },
2459 { "rorA", { Eb, I1 } },
2460 { "rclA", { Eb, I1 } },
2461 { "rcrA", { Eb, I1 } },
2462 { "shlA", { Eb, I1 } },
2463 { "shrA", { Eb, I1 } },
2464 { "(bad)", { XX } },
2465 { "sarA", { Eb, I1 } },
252b5132 2466 },
1ceb70f8 2467 /* REG_D1 */
252b5132 2468 {
ce518a5f
L		 2469 { "rolQ", { Ev, I1 } },
2470 { "rorQ", { Ev, I1 } },
2471 { "rclQ", { Ev, I1 } },
2472 { "rcrQ", { Ev, I1 } },
2473 { "shlQ", { Ev, I1 } },
2474 { "shrQ", { Ev, I1 } },
2475 { "(bad)", { XX } },
2476 { "sarQ", { Ev, I1 } },
252b5132 2477 },
1ceb70f8 2478 /* REG_D2 */
252b5132 2479 {
ce518a5f
L		 2480 { "rolA", { Eb, CL } },
2481 { "rorA", { Eb, CL } },
2482 { "rclA", { Eb, CL } },
2483 { "rcrA", { Eb, CL } },
2484 { "shlA", { Eb, CL } },
2485 { "shrA", { Eb, CL } },
2486 { "(bad)", { XX } },
2487 { "sarA", { Eb, CL } },
252b5132 2488 },
1ceb70f8 2489 /* REG_D3 */
252b5132 2490 {
ce518a5f
L		 2491 { "rolQ", { Ev, CL } },
2492 { "rorQ", { Ev, CL } },
2493 { "rclQ", { Ev, CL } },
2494 { "rcrQ", { Ev, CL } },
2495 { "shlQ", { Ev, CL } },
2496 { "shrQ", { Ev, CL } },
2497 { "(bad)", { XX } },
2498 { "sarQ", { Ev, CL } },
252b5132 2499 },
1ceb70f8 2500 /* REG_F6 */
252b5132 2501 {
ce518a5f 2502 { "testA", { Eb, Ib } },
058f233b 2503 { "(bad)", { XX } },
ce518a5f
L		 2504 { "notA", { Eb } },
2505 { "negA", { Eb } },
2506 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2507 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2508 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2509 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2510 },
1ceb70f8 2511 /* REG_F7 */
252b5132 2512 {
ce518a5f
L		 2513 { "testQ", { Ev, Iv } },
2514 { "(bad)", { XX } },
2515 { "notQ", { Ev } },
2516 { "negQ", { Ev } },
2517 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2518 { "imulQ", { Ev } },
2519 { "divQ", { Ev } },
2520 { "idivQ", { Ev } },
252b5132 2521 },
1ceb70f8 2522 /* REG_FE */
252b5132 2523 {
ce518a5f
L		 2524 { "incA", { Eb } },
2525 { "decA", { Eb } },
2526 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
2528 { "(bad)", { XX } },
2529 { "(bad)", { XX } },
2530 { "(bad)", { XX } },
2531 { "(bad)", { XX } },
252b5132 2532 },
1ceb70f8 2533 /* REG_FF */
252b5132 2534 {
ce518a5f
L		 2535 { "incQ", { Ev } },
2536 { "decQ", { Ev } },
2537 { "callT", { indirEv } },
2538 { "JcallT", { indirEp } },
2539 { "jmpT", { indirEv } },
2540 { "JjmpT", { indirEp } },
2541 { "pushU", { stackEv } },
2542 { "(bad)", { XX } },
252b5132 2543 },
1ceb70f8 2544 /* REG_0F00 */
252b5132 2545 {
ce518a5f
L		 2546 { "sldtD", { Sv } },
2547 { "strD", { Sv } },
2548 { "lldt", { Ew } },
2549 { "ltr", { Ew } },
2550 { "verr", { Ew } },
2551 { "verw", { Ew } },
2552 { "(bad)", { XX } },
2553 { "(bad)", { XX } },
252b5132 2554 },
1ceb70f8 2555 /* REG_0F01 */
252b5132 2556 {
1ceb70f8
L		 2557 { MOD_TABLE (MOD_0F01_REG_0) },
2558 { MOD_TABLE (MOD_0F01_REG_1) },
2559 { MOD_TABLE (MOD_0F01_REG_2) },
2560 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2561 { "smswD", { Sv } },
2562 { "(bad)", { XX } },
2563 { "lmsw", { Ew } },
1ceb70f8 2564 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2565 },
b5b1fc4f 2566 /* REG_0F0D */
252b5132 2567 {
4e7d34a6
L		 2568 { "prefetch", { Eb } },
2569 { "prefetchw", { Eb } },
2570 { "(bad)", { XX } },
2571 { "(bad)", { XX } },
2572 { "(bad)", { XX } },
2573 { "(bad)", { XX } },
2574 { "(bad)", { XX } },
2575 { "(bad)", { XX } },
252b5132 2576 },
1ceb70f8 2577 /* REG_0F18 */
252b5132 2578 {
1ceb70f8
L		 2579 { MOD_TABLE (MOD_0F18_REG_0) },
2580 { MOD_TABLE (MOD_0F18_REG_1) },
2581 { MOD_TABLE (MOD_0F18_REG_2) },
2582 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2583 { "(bad)", { XX } },
2584 { "(bad)", { XX } },
2585 { "(bad)", { XX } },
2586 { "(bad)", { XX } },
252b5132 2587 },
1ceb70f8 2588 /* REG_0F71 */
a6bd098c 2589 {
ce518a5f
L		 2590 { "(bad)", { XX } },
2591 { "(bad)", { XX } },
1ceb70f8 2592 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2593 { "(bad)", { XX } },
1ceb70f8 2594 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2595 { "(bad)", { XX } },
1ceb70f8 2596 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2597 { "(bad)", { XX } },
a6bd098c 2598 },
1ceb70f8 2599 /* REG_0F72 */
a6bd098c 2600 {
ce518a5f
L		 2601 { "(bad)", { XX } },
2602 { "(bad)", { XX } },
1ceb70f8 2603 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2604 { "(bad)", { XX } },
1ceb70f8 2605 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2606 { "(bad)", { XX } },
1ceb70f8 2607 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2608 { "(bad)", { XX } },
a6bd098c 2609 },
1ceb70f8 2610 /* REG_0F73 */
252b5132 2611 {
ce518a5f
L		 2612 { "(bad)", { XX } },
2613 { "(bad)", { XX } },
1ceb70f8
L		 2614 { MOD_TABLE (MOD_0F73_REG_2) },
2615 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2616 { "(bad)", { XX } },
ce518a5f 2617 { "(bad)", { XX } },
1ceb70f8
L		 2618 { MOD_TABLE (MOD_0F73_REG_6) },
2619 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2620 },
1ceb70f8 2621 /* REG_0FA6 */
252b5132 2622 {
4e7d34a6
L		 2623 { "montmul", { { OP_0f07, 0 } } },
2624 { "xsha1", { { OP_0f07, 0 } } },
2625 { "xsha256", { { OP_0f07, 0 } } },
2626 { "(bad)", { { OP_0f07, 0 } } },
2627 { "(bad)", { { OP_0f07, 0 } } },
2628 { "(bad)", { { OP_0f07, 0 } } },
2629 { "(bad)", { { OP_0f07, 0 } } },
2630 { "(bad)", { { OP_0f07, 0 } } },
2631 },
1ceb70f8 2632 /* REG_0FA7 */
4e7d34a6
L		 2633 {
2634 { "xstore-rng", { { OP_0f07, 0 } } },
2635 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2636 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2637 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2638 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2639 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2640 { "(bad)", { { OP_0f07, 0 } } },
2641 { "(bad)", { { OP_0f07, 0 } } },
2642 },
1ceb70f8 2643 /* REG_0FAE */
4e7d34a6 2644 {
1ceb70f8
L		 2645 { MOD_TABLE (MOD_0FAE_REG_0) },
2646 { MOD_TABLE (MOD_0FAE_REG_1) },
2647 { MOD_TABLE (MOD_0FAE_REG_2) },
2648 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2649 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2650 { MOD_TABLE (MOD_0FAE_REG_5) },
2651 { MOD_TABLE (MOD_0FAE_REG_6) },
2652 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2653 },
1ceb70f8 2654 /* REG_0FBA */
252b5132 2655 {
ce518a5f
L		 2656 { "(bad)", { XX } },
2657 { "(bad)", { XX } },
d8faab4e
L		 2658 { "(bad)", { XX } },
2659 { "(bad)", { XX } },
4e7d34a6
L		 2660 { "btQ", { Ev, Ib } },
2661 { "btsQ", { Ev, Ib } },
2662 { "btrQ", { Ev, Ib } },
2663 { "btcQ", { Ev, Ib } },
c608c12e 2664 },
1ceb70f8 2665 /* REG_0FC7 */
c608c12e 2666 {
b844680a 2667 { "(bad)", { XX } },
4e7d34a6 2668 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2669 { "(bad)", { XX } },
b844680a
L		 2670 { "(bad)", { XX } },
2671 { "(bad)", { XX } },
2672 { "(bad)", { XX } },
1ceb70f8
L		 2673 { MOD_TABLE (MOD_0FC7_REG_6) },
2674 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2675 },
c0f3af97
L		 2676 /* REG_VEX_71 */
2677 {
2678 { "(bad)", { XX } },
2679 { "(bad)", { XX } },
2680 { MOD_TABLE (MOD_VEX_71_REG_2) },
2681 { "(bad)", { XX } },
2682 { MOD_TABLE (MOD_VEX_71_REG_4) },
2683 { "(bad)", { XX } },
2684 { MOD_TABLE (MOD_VEX_71_REG_6) },
2685 { "(bad)", { XX } },
2686 },
2687 /* REG_VEX_72 */
2688 {
2689 { "(bad)", { XX } },
2690 { "(bad)", { XX } },
2691 { MOD_TABLE (MOD_VEX_72_REG_2) },
2692 { "(bad)", { XX } },
2693 { MOD_TABLE (MOD_VEX_72_REG_4) },
2694 { "(bad)", { XX } },
2695 { MOD_TABLE (MOD_VEX_72_REG_6) },
2696 { "(bad)", { XX } },
2697 },
2698 /* REG_VEX_73 */
2699 {
2700 { "(bad)", { XX } },
2701 { "(bad)", { XX } },
2702 { MOD_TABLE (MOD_VEX_73_REG_2) },
2703 { MOD_TABLE (MOD_VEX_73_REG_3) },
2704 { "(bad)", { XX } },
2705 { "(bad)", { XX } },
2706 { MOD_TABLE (MOD_VEX_73_REG_6) },
2707 { MOD_TABLE (MOD_VEX_73_REG_7) },
2708 },
2709 /* REG_VEX_AE */
2710 {
2711 { "(bad)", { XX } },
2712 { "(bad)", { XX } },
2713 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2714 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2715 { "(bad)", { XX } },
2716 { "(bad)", { XX } },
2717 { "(bad)", { XX } },
2718 { "(bad)", { XX } },
2719 },
f88c9eb0
SP		 2720 /* REG_XOP_LWPCB */
2721 {
2722 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2723 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2724 { "(bad)", { XX } },
2725 { "(bad)", { XX } },
2726 { "(bad)", { XX } },
2727 { "(bad)", { XX } },
2728 { "(bad)", { XX } },
2729 { "(bad)", { XX } },
2730 },
2731 /* REG_XOP_LWP */
2732 {
2733 { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2734 { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2735 { "(bad)", { XX } },
2736 { "(bad)", { XX } },
2737 { "(bad)", { XX } },
2738 { "(bad)", { XX } },
2739 { "(bad)", { XX } },
2740 { "(bad)", { XX } },
2741 },
4e7d34a6
L		 2742};
2743
1ceb70f8
L		 2744static const struct dis386 prefix_table[][4] = {
2745 /* PREFIX_90 */
252b5132 2746 {
4e7d34a6
L		 2747 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2748 { "pause", { XX } },
2749 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2750 { "(bad)", { XX } },
0f10071e 2751 },
4e7d34a6 2752
1ceb70f8 2753 /* PREFIX_0F10 */
cc0ec051 2754 {
4e7d34a6
L		 2755 { "movups", { XM, EXx } },
2756 { "movss", { XM, EXd } },
2757 { "movupd", { XM, EXx } },
2758 { "movsd", { XM, EXq } },
30d1c836 2759 },
4e7d34a6 2760
1ceb70f8 2761 /* PREFIX_0F11 */
30d1c836 2762 {
b6169b20 2763 { "movups", { EXxS, XM } },
fa99fab2 2764 { "movss", { EXdS, XM } },
b6169b20 2765 { "movupd", { EXxS, XM } },
fa99fab2 2766 { "movsd", { EXqS, XM } },
4e7d34a6 2767 },
252b5132 2768
1ceb70f8 2769 /* PREFIX_0F12 */
c608c12e 2770 {
1ceb70f8 2771 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2772 { "movsldup", { XM, EXx } },
2773 { "movlpd", { XM, EXq } },
2774 { "movddup", { XM, EXq } },
c608c12e 2775 },
4e7d34a6 2776
1ceb70f8 2777 /* PREFIX_0F16 */
c608c12e 2778 {
1ceb70f8 2779 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2780 { "movshdup", { XM, EXx } },
2781 { "movhpd", { XM, EXq } },
058f233b 2782 { "(bad)", { XX } },
c608c12e 2783 },
4e7d34a6 2784
1ceb70f8 2785 /* PREFIX_0F2A */
c608c12e 2786 {
09335d05 2787 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2788 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2789 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2790 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2791 },
4e7d34a6 2792
1ceb70f8 2793 /* PREFIX_0F2B */
c608c12e 2794 {
75c135a8
L		 2795 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2796 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2797 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2798 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2799 },
4e7d34a6 2800
1ceb70f8 2801 /* PREFIX_0F2C */
c608c12e 2802 {
09335d05
L		 2803 { "cvttps2pi", { MXC, EXq } },
2804 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2805 { "cvttpd2pi", { MXC, EXx } },
09335d05 2806 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2807 },
4e7d34a6 2808
1ceb70f8 2809 /* PREFIX_0F2D */
c608c12e 2810 {
4e7d34a6
L		 2811 { "cvtps2pi", { MXC, EXq } },
2812 { "cvtss2siY", { Gv, EXd } },
2813 { "cvtpd2pi", { MXC, EXx } },
2814 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2815 },
4e7d34a6 2816
1ceb70f8 2817 /* PREFIX_0F2E */
c608c12e 2818 {
4e7d34a6
L		 2819 { "ucomiss",{ XM, EXd } },
2820 { "(bad)", { XX } },
2821 { "ucomisd",{ XM, EXq } },
2822 { "(bad)", { XX } },
c608c12e 2823 },
4e7d34a6 2824
1ceb70f8 2825 /* PREFIX_0F2F */
c608c12e 2826 {
4e7d34a6
L		 2827 { "comiss", { XM, EXd } },
2828 { "(bad)", { XX } },
2829 { "comisd", { XM, EXq } },
2830 { "(bad)", { XX } },
c608c12e 2831 },
4e7d34a6 2832
1ceb70f8 2833 /* PREFIX_0F51 */
c608c12e 2834 {
4e7d34a6
L		 2835 { "sqrtps", { XM, EXx } },
2836 { "sqrtss", { XM, EXd } },
2837 { "sqrtpd", { XM, EXx } },
2838 { "sqrtsd", { XM, EXq } },
c608c12e 2839 },
4e7d34a6 2840
1ceb70f8 2841 /* PREFIX_0F52 */
c608c12e 2842 {
4e7d34a6
L		 2843 { "rsqrtps",{ XM, EXx } },
2844 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
c608c12e 2847 },
4e7d34a6 2848
1ceb70f8 2849 /* PREFIX_0F53 */
c608c12e 2850 {
4e7d34a6
L		 2851 { "rcpps", { XM, EXx } },
2852 { "rcpss", { XM, EXd } },
058f233b
L		 2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
c608c12e 2855 },
4e7d34a6 2856
1ceb70f8 2857 /* PREFIX_0F58 */
c608c12e 2858 {
4e7d34a6
L		 2859 { "addps", { XM, EXx } },
2860 { "addss", { XM, EXd } },
2861 { "addpd", { XM, EXx } },
2862 { "addsd", { XM, EXq } },
c608c12e 2863 },
4e7d34a6 2864
1ceb70f8 2865 /* PREFIX_0F59 */
c608c12e 2866 {
4e7d34a6
L		 2867 { "mulps", { XM, EXx } },
2868 { "mulss", { XM, EXd } },
2869 { "mulpd", { XM, EXx } },
2870 { "mulsd", { XM, EXq } },
041bd2e0 2871 },
4e7d34a6 2872
1ceb70f8 2873 /* PREFIX_0F5A */
041bd2e0 2874 {
4e7d34a6
L		 2875 { "cvtps2pd", { XM, EXq } },
2876 { "cvtss2sd", { XM, EXd } },
2877 { "cvtpd2ps", { XM, EXx } },
2878 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2879 },
4e7d34a6 2880
1ceb70f8 2881 /* PREFIX_0F5B */
041bd2e0 2882 {
09a2c6cf
L		 2883 { "cvtdq2ps", { XM, EXx } },
2884 { "cvttps2dq", { XM, EXx } },
2885 { "cvtps2dq", { XM, EXx } },
058f233b 2886 { "(bad)", { XX } },
041bd2e0 2887 },
4e7d34a6 2888
1ceb70f8 2889 /* PREFIX_0F5C */
041bd2e0 2890 {
4e7d34a6
L		 2891 { "subps", { XM, EXx } },
2892 { "subss", { XM, EXd } },
2893 { "subpd", { XM, EXx } },
2894 { "subsd", { XM, EXq } },
041bd2e0 2895 },
4e7d34a6 2896
1ceb70f8 2897 /* PREFIX_0F5D */
041bd2e0 2898 {
4e7d34a6
L		 2899 { "minps", { XM, EXx } },
2900 { "minss", { XM, EXd } },
2901 { "minpd", { XM, EXx } },
2902 { "minsd", { XM, EXq } },
041bd2e0 2903 },
4e7d34a6 2904
1ceb70f8 2905 /* PREFIX_0F5E */
041bd2e0 2906 {
4e7d34a6
L		 2907 { "divps", { XM, EXx } },
2908 { "divss", { XM, EXd } },
2909 { "divpd", { XM, EXx } },
2910 { "divsd", { XM, EXq } },
041bd2e0 2911 },
4e7d34a6 2912
1ceb70f8 2913 /* PREFIX_0F5F */
041bd2e0 2914 {
4e7d34a6
L		 2915 { "maxps", { XM, EXx } },
2916 { "maxss", { XM, EXd } },
2917 { "maxpd", { XM, EXx } },
2918 { "maxsd", { XM, EXq } },
041bd2e0 2919 },
4e7d34a6 2920
1ceb70f8 2921 /* PREFIX_0F60 */
041bd2e0 2922 {
4e7d34a6
L		 2923 { "punpcklbw",{ MX, EMd } },
2924 { "(bad)", { XX } },
2925 { "punpcklbw",{ MX, EMx } },
2926 { "(bad)", { XX } },
041bd2e0 2927 },
4e7d34a6 2928
1ceb70f8 2929 /* PREFIX_0F61 */
041bd2e0 2930 {
4e7d34a6
L		 2931 { "punpcklwd",{ MX, EMd } },
2932 { "(bad)", { XX } },
2933 { "punpcklwd",{ MX, EMx } },
2934 { "(bad)", { XX } },
041bd2e0 2935 },
4e7d34a6 2936
1ceb70f8 2937 /* PREFIX_0F62 */
041bd2e0 2938 {
4e7d34a6
L		 2939 { "punpckldq",{ MX, EMd } },
2940 { "(bad)", { XX } },
2941 { "punpckldq",{ MX, EMx } },
2942 { "(bad)", { XX } },
041bd2e0 2943 },
4e7d34a6 2944
1ceb70f8 2945 /* PREFIX_0F6C */
041bd2e0 2946 {
058f233b
L		 2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
4e7d34a6 2949 { "punpcklqdq", { XM, EXx } },
058f233b 2950 { "(bad)", { XX } },
0f17484f 2951 },
4e7d34a6 2952
1ceb70f8 2953 /* PREFIX_0F6D */
0f17484f 2954 {
058f233b
L		 2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
4e7d34a6 2957 { "punpckhqdq", { XM, EXx } },
058f233b 2958 { "(bad)", { XX } },
041bd2e0 2959 },
4e7d34a6 2960
1ceb70f8 2961 /* PREFIX_0F6F */
ca164297 2962 {
4e7d34a6
L		 2963 { "movq", { MX, EM } },
2964 { "movdqu", { XM, EXx } },
2965 { "movdqa", { XM, EXx } },
058f233b 2966 { "(bad)", { XX } },
ca164297 2967 },
4e7d34a6 2968
1ceb70f8 2969 /* PREFIX_0F70 */
4e7d34a6
L		 2970 {
2971 { "pshufw", { MX, EM, Ib } },
2972 { "pshufhw",{ XM, EXx, Ib } },
2973 { "pshufd", { XM, EXx, Ib } },
2974 { "pshuflw",{ XM, EXx, Ib } },
2975 },
2976
92fddf8e
L		 2977 /* PREFIX_0F73_REG_3 */
2978 {
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "psrldq", { XS, Ib } },
2982 { "(bad)", { XX } },
2983 },
2984
2985 /* PREFIX_0F73_REG_7 */
2986 {
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "pslldq", { XS, Ib } },
2990 { "(bad)", { XX } },
2991 },
2992
1ceb70f8 2993 /* PREFIX_0F78 */
4e7d34a6
L		 2994 {
2995 {"vmread", { Em, Gm } },
2996 {"(bad)", { XX } },
2997 {"extrq", { XS, Ib, Ib } },
2998 {"insertq", { XM, XS, Ib, Ib } },
2999 },
3000
1ceb70f8 3001 /* PREFIX_0F79 */
4e7d34a6
L		 3002 {
3003 {"vmwrite", { Gm, Em } },
3004 {"(bad)", { XX } },
3005 {"extrq", { XM, XS } },
3006 {"insertq", { XM, XS } },
3007 },
3008
1ceb70f8 3009 /* PREFIX_0F7C */
ca164297 3010 {
058f233b
L		 3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
09a2c6cf
L		 3013 { "haddpd", { XM, EXx } },
3014 { "haddps", { XM, EXx } },
ca164297 3015 },
4e7d34a6 3016
1ceb70f8 3017 /* PREFIX_0F7D */
ca164297 3018 {
058f233b
L		 3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
09a2c6cf
L		 3021 { "hsubpd", { XM, EXx } },
3022 { "hsubps", { XM, EXx } },
ca164297 3023 },
4e7d34a6 3024
1ceb70f8 3025 /* PREFIX_0F7E */
ca164297 3026 {
4e7d34a6
L		 3027 { "movK", { Edq, MX } },
3028 { "movq", { XM, EXq } },
3029 { "movK", { Edq, XM } },
058f233b 3030 { "(bad)", { XX } },
ca164297 3031 },
4e7d34a6 3032
1ceb70f8 3033 /* PREFIX_0F7F */
ca164297 3034 {
b6169b20
L		 3035 { "movq", { EMS, MX } },
3036 { "movdqu", { EXxS, XM } },
3037 { "movdqa", { EXxS, XM } },
058f233b 3038 { "(bad)", { XX } },
ca164297 3039 },
4e7d34a6 3040
1ceb70f8 3041 /* PREFIX_0FB8 */
ca164297 3042 {
4e7d34a6
L		 3043 { "(bad)", { XX } },
3044 { "popcntS", { Gv, Ev } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
ca164297 3047 },
4e7d34a6 3048
1ceb70f8 3049 /* PREFIX_0FBD */
050dfa73 3050 {
4e7d34a6
L		 3051 { "bsrS", { Gv, Ev } },
3052 { "lzcntS", { Gv, Ev } },
3053 { "bsrS", { Gv, Ev } },
3054 { "(bad)", { XX } },
050dfa73
MM		 3055 },
3056
1ceb70f8 3057 /* PREFIX_0FC2 */
050dfa73 3058 {
ad19981d
L		 3059 { "cmpps", { XM, EXx, CMP } },
3060 { "cmpss", { XM, EXd, CMP } },
3061 { "cmppd", { XM, EXx, CMP } },
3062 { "cmpsd", { XM, EXq, CMP } },
050dfa73 3063 },
246c51aa 3064
4ee52178
L		 3065 /* PREFIX_0FC3 */
3066 {
3067 { "movntiS", { Ma, Gv } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 },
3072
92fddf8e
L		 3073 /* PREFIX_0FC7_REG_6 */
3074 {
3075 { "vmptrld",{ Mq } },
3076 { "vmxon", { Mq } },
3077 { "vmclear",{ Mq } },
3078 { "(bad)", { XX } },
3079 },
3080
1ceb70f8 3081 /* PREFIX_0FD0 */
050dfa73 3082 {
058f233b
L		 3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
4e7d34a6
L		 3085 { "addsubpd", { XM, EXx } },
3086 { "addsubps", { XM, EXx } },
246c51aa 3087 },
050dfa73 3088
1ceb70f8 3089 /* PREFIX_0FD6 */
050dfa73 3090 {
058f233b 3091 { "(bad)", { XX } },
4e7d34a6 3092 { "movq2dq",{ XM, MS } },
b6169b20 3093 { "movq", { EXqS, XM } },
4e7d34a6 3094 { "movdq2q",{ MX, XS } },
050dfa73
MM		 3095 },
3096
1ceb70f8 3097 /* PREFIX_0FE6 */
7918206c 3098 {
058f233b 3099 { "(bad)", { XX } },
4e7d34a6
L		 3100 { "cvtdq2pd", { XM, EXq } },
3101 { "cvttpd2dq", { XM, EXx } },
3102 { "cvtpd2dq", { XM, EXx } },
7918206c 3103 },
8b38ad71 3104
1ceb70f8 3105 /* PREFIX_0FE7 */
8b38ad71 3106 {
4ee52178 3107 { "movntq", { Mq, MX } },
058f233b 3108 { "(bad)", { XX } },
75c135a8 3109 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 3110 { "(bad)", { XX } },
4e7d34a6
L		 3111 },
3112
1ceb70f8 3113 /* PREFIX_0FF0 */
4e7d34a6 3114 {
058f233b
L		 3115 { "(bad)", { XX } },
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
1ceb70f8 3118 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 3119 },
3120
1ceb70f8 3121 /* PREFIX_0FF7 */
4e7d34a6
L		 3122 {
3123 { "maskmovq", { MX, MS } },
058f233b 3124 { "(bad)", { XX } },
4e7d34a6 3125 { "maskmovdqu", { XM, XS } },
058f233b 3126 { "(bad)", { XX } },
8b38ad71 3127 },
42903f7f 3128
1ceb70f8 3129 /* PREFIX_0F3810 */
42903f7f
L		 3130 {
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
88a94849 3133 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 3134 { "(bad)", { XX } },
3135 },
3136
1ceb70f8 3137 /* PREFIX_0F3814 */
42903f7f
L		 3138 {
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
88a94849 3141 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 3142 { "(bad)", { XX } },
3143 },
3144
1ceb70f8 3145 /* PREFIX_0F3815 */
42903f7f
L		 3146 {
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
09a2c6cf 3149 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 3150 { "(bad)", { XX } },
3151 },
3152
1ceb70f8 3153 /* PREFIX_0F3817 */
42903f7f
L		 3154 {
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
09a2c6cf 3157 { "ptest", { XM, EXx } },
42903f7f
L		 3158 { "(bad)", { XX } },
3159 },
3160
1ceb70f8 3161 /* PREFIX_0F3820 */
42903f7f
L		 3162 {
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
8976381e 3165 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 3166 { "(bad)", { XX } },
3167 },
3168
1ceb70f8 3169 /* PREFIX_0F3821 */
42903f7f
L		 3170 {
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
8976381e 3173 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 3174 { "(bad)", { XX } },
3175 },
3176
1ceb70f8 3177 /* PREFIX_0F3822 */
42903f7f
L		 3178 {
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
8976381e 3181 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 3182 { "(bad)", { XX } },
3183 },
3184
1ceb70f8 3185 /* PREFIX_0F3823 */
42903f7f
L		 3186 {
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
8976381e 3189 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 3190 { "(bad)", { XX } },
3191 },
3192
1ceb70f8 3193 /* PREFIX_0F3824 */
42903f7f
L		 3194 {
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
8976381e 3197 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 3198 { "(bad)", { XX } },
3199 },
3200
1ceb70f8 3201 /* PREFIX_0F3825 */
42903f7f
L		 3202 {
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
8976381e 3205 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 3206 { "(bad)", { XX } },
3207 },
3208
1ceb70f8 3209 /* PREFIX_0F3828 */
42903f7f
L		 3210 {
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
09a2c6cf 3213 { "pmuldq", { XM, EXx } },
42903f7f
L		 3214 { "(bad)", { XX } },
3215 },
3216
1ceb70f8 3217 /* PREFIX_0F3829 */
42903f7f
L		 3218 {
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
09a2c6cf 3221 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 3222 { "(bad)", { XX } },
3223 },
3224
1ceb70f8 3225 /* PREFIX_0F382A */
42903f7f
L		 3226 {
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
75c135a8 3229 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 3230 { "(bad)", { XX } },
3231 },
3232
1ceb70f8 3233 /* PREFIX_0F382B */
42903f7f
L		 3234 {
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
09a2c6cf 3237 { "packusdw", { XM, EXx } },
42903f7f
L		 3238 { "(bad)", { XX } },
3239 },
3240
1ceb70f8 3241 /* PREFIX_0F3830 */
42903f7f
L		 3242 {
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
8976381e 3245 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 3246 { "(bad)", { XX } },
3247 },
3248
1ceb70f8 3249 /* PREFIX_0F3831 */
42903f7f
L		 3250 {
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
8976381e 3253 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 3254 { "(bad)", { XX } },
3255 },
3256
1ceb70f8 3257 /* PREFIX_0F3832 */
42903f7f
L		 3258 {
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
8976381e 3261 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 3262 { "(bad)", { XX } },
3263 },
3264
1ceb70f8 3265 /* PREFIX_0F3833 */
42903f7f
L		 3266 {
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
8976381e 3269 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 3270 { "(bad)", { XX } },
3271 },
3272
1ceb70f8 3273 /* PREFIX_0F3834 */
42903f7f
L		 3274 {
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
8976381e 3277 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 3278 { "(bad)", { XX } },
3279 },
3280
1ceb70f8 3281 /* PREFIX_0F3835 */
42903f7f
L		 3282 {
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
8976381e 3285 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 3286 { "(bad)", { XX } },
3287 },
3288
1ceb70f8 3289 /* PREFIX_0F3837 */
4e7d34a6
L		 3290 {
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "pcmpgtq", { XM, EXx } },
3294 { "(bad)", { XX } },
3295 },
3296
1ceb70f8 3297 /* PREFIX_0F3838 */
42903f7f
L		 3298 {
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
09a2c6cf 3301 { "pminsb", { XM, EXx } },
42903f7f
L		 3302 { "(bad)", { XX } },
3303 },
3304
1ceb70f8 3305 /* PREFIX_0F3839 */
42903f7f
L		 3306 {
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
09a2c6cf 3309 { "pminsd", { XM, EXx } },
42903f7f
L		 3310 { "(bad)", { XX } },
3311 },
3312
1ceb70f8 3313 /* PREFIX_0F383A */
42903f7f
L		 3314 {
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
09a2c6cf 3317 { "pminuw", { XM, EXx } },
42903f7f
L		 3318 { "(bad)", { XX } },
3319 },
3320
1ceb70f8 3321 /* PREFIX_0F383B */
42903f7f
L		 3322 {
3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
09a2c6cf 3325 { "pminud", { XM, EXx } },
42903f7f
L		 3326 { "(bad)", { XX } },
3327 },
3328
1ceb70f8 3329 /* PREFIX_0F383C */
42903f7f
L		 3330 {
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
09a2c6cf 3333 { "pmaxsb", { XM, EXx } },
42903f7f
L		 3334 { "(bad)", { XX } },
3335 },
3336
1ceb70f8 3337 /* PREFIX_0F383D */
42903f7f
L		 3338 {
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
09a2c6cf 3341 { "pmaxsd", { XM, EXx } },
42903f7f
L		 3342 { "(bad)", { XX } },
3343 },
3344
1ceb70f8 3345 /* PREFIX_0F383E */
42903f7f
L		 3346 {
3347 { "(bad)", { XX } },
3348 { "(bad)", { XX } },
09a2c6cf 3349 { "pmaxuw", { XM, EXx } },
42903f7f
L		 3350 { "(bad)", { XX } },
3351 },
3352
1ceb70f8 3353 /* PREFIX_0F383F */
42903f7f
L		 3354 {
3355 { "(bad)", { XX } },
3356 { "(bad)", { XX } },
09a2c6cf 3357 { "pmaxud", { XM, EXx } },
42903f7f
L		 3358 { "(bad)", { XX } },
3359 },
3360
1ceb70f8 3361 /* PREFIX_0F3840 */
42903f7f
L		 3362 {
3363 { "(bad)", { XX } },
3364 { "(bad)", { XX } },
09a2c6cf 3365 { "pmulld", { XM, EXx } },
42903f7f
L		 3366 { "(bad)", { XX } },
3367 },
3368
1ceb70f8 3369 /* PREFIX_0F3841 */
42903f7f
L		 3370 {
3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
09a2c6cf 3373 { "phminposuw", { XM, EXx } },
42903f7f
L		 3374 { "(bad)", { XX } },
3375 },
3376
f1f8f695
L		 3377 /* PREFIX_0F3880 */
3378 {
3379 { "(bad)", { XX } },
3380 { "(bad)", { XX } },
3381 { "invept", { Gm, Mo } },
3382 { "(bad)", { XX } },
3383 },
3384
3385 /* PREFIX_0F3881 */
3386 {
3387 { "(bad)", { XX } },
3388 { "(bad)", { XX } },
3389 { "invvpid", { Gm, Mo } },
3390 { "(bad)", { XX } },
3391 },
3392
c0f3af97
L		 3393 /* PREFIX_0F38DB */
3394 {
3395 { "(bad)", { XX } },
3396 { "(bad)", { XX } },
3397 { "aesimc", { XM, EXx } },
3398 { "(bad)", { XX } },
3399 },
3400
3401 /* PREFIX_0F38DC */
3402 {
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "aesenc", { XM, EXx } },
3406 { "(bad)", { XX } },
3407 },
3408
3409 /* PREFIX_0F38DD */
3410 {
3411 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
3413 { "aesenclast", { XM, EXx } },
3414 { "(bad)", { XX } },
3415 },
3416
3417 /* PREFIX_0F38DE */
3418 {
3419 { "(bad)", { XX } },
3420 { "(bad)", { XX } },
3421 { "aesdec", { XM, EXx } },
3422 { "(bad)", { XX } },
3423 },
3424
3425 /* PREFIX_0F38DF */
3426 {
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3429 { "aesdeclast", { XM, EXx } },
3430 { "(bad)", { XX } },
3431 },
3432
1ceb70f8 3433 /* PREFIX_0F38F0 */
4e7d34a6 3434 {
f1f8f695 3435 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3436 { "(bad)", { XX } },
f1f8f695 3437 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3438 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3439 },
3440
1ceb70f8 3441 /* PREFIX_0F38F1 */
4e7d34a6 3442 {
f1f8f695 3443 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3444 { "(bad)", { XX } },
f1f8f695 3445 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3446 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3447 },
3448
1ceb70f8 3449 /* PREFIX_0F3A08 */
42903f7f
L		 3450 {
3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
09a2c6cf 3453 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3454 { "(bad)", { XX } },
3455 },
3456
1ceb70f8 3457 /* PREFIX_0F3A09 */
42903f7f
L		 3458 {
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
09a2c6cf 3461 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3462 { "(bad)", { XX } },
3463 },
3464
1ceb70f8 3465 /* PREFIX_0F3A0A */
42903f7f
L		 3466 {
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
09335d05 3469 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3470 { "(bad)", { XX } },
3471 },
3472
1ceb70f8 3473 /* PREFIX_0F3A0B */
42903f7f
L		 3474 {
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
09335d05 3477 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3478 { "(bad)", { XX } },
3479 },
3480
1ceb70f8 3481 /* PREFIX_0F3A0C */
42903f7f
L		 3482 {
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
09a2c6cf 3485 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3486 { "(bad)", { XX } },
3487 },
3488
1ceb70f8 3489 /* PREFIX_0F3A0D */
42903f7f
L		 3490 {
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
09a2c6cf 3493 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3494 { "(bad)", { XX } },
3495 },
3496
1ceb70f8 3497 /* PREFIX_0F3A0E */
42903f7f
L		 3498 {
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
09a2c6cf 3501 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3502 { "(bad)", { XX } },
3503 },
3504
1ceb70f8 3505 /* PREFIX_0F3A14 */
42903f7f
L		 3506 {
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "pextrb", { Edqb, XM, Ib } },
3510 { "(bad)", { XX } },
3511 },
3512
1ceb70f8 3513 /* PREFIX_0F3A15 */
42903f7f
L		 3514 {
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "pextrw", { Edqw, XM, Ib } },
3518 { "(bad)", { XX } },
3519 },
3520
1ceb70f8 3521 /* PREFIX_0F3A16 */
42903f7f
L		 3522 {
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "pextrK", { Edq, XM, Ib } },
3526 { "(bad)", { XX } },
3527 },
3528
1ceb70f8 3529 /* PREFIX_0F3A17 */
42903f7f
L		 3530 {
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "extractps", { Edqd, XM, Ib } },
3534 { "(bad)", { XX } },
3535 },
3536
1ceb70f8 3537 /* PREFIX_0F3A20 */
42903f7f
L		 3538 {
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "pinsrb", { XM, Edqb, Ib } },
3542 { "(bad)", { XX } },
3543 },
3544
1ceb70f8 3545 /* PREFIX_0F3A21 */
42903f7f
L		 3546 {
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
8976381e 3549 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3550 { "(bad)", { XX } },
3551 },
3552
1ceb70f8 3553 /* PREFIX_0F3A22 */
42903f7f
L		 3554 {
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "pinsrK", { XM, Edq, Ib } },
3558 { "(bad)", { XX } },
3559 },
3560
1ceb70f8 3561 /* PREFIX_0F3A40 */
42903f7f
L		 3562 {
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
09a2c6cf 3565 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3566 { "(bad)", { XX } },
3567 },
3568
1ceb70f8 3569 /* PREFIX_0F3A41 */
42903f7f
L		 3570 {
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
09a2c6cf 3573 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3574 { "(bad)", { XX } },
3575 },
3576
1ceb70f8 3577 /* PREFIX_0F3A42 */
42903f7f
L		 3578 {
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
09a2c6cf 3581 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3582 { "(bad)", { XX } },
3583 },
381d071f 3584
c0f3af97
L		 3585 /* PREFIX_0F3A44 */
3586 {
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "pclmulqdq", { XM, EXx, PCLMUL } },
3590 { "(bad)", { XX } },
3591 },
3592
1ceb70f8 3593 /* PREFIX_0F3A60 */
381d071f
L		 3594 {
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
4e7d34a6 3597 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3598 { "(bad)", { XX } },
3599 },
3600
1ceb70f8 3601 /* PREFIX_0F3A61 */
381d071f
L		 3602 {
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
4e7d34a6 3605 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3606 { "(bad)", { XX } },
381d071f
L		 3607 },
3608
1ceb70f8 3609 /* PREFIX_0F3A62 */
381d071f
L		 3610 {
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
4e7d34a6 3613 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3614 { "(bad)", { XX } },
381d071f
L		 3615 },
3616
1ceb70f8 3617 /* PREFIX_0F3A63 */
381d071f
L		 3618 {
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
4e7d34a6 3621 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3622 { "(bad)", { XX } },
3623 },
09a2c6cf 3624
c0f3af97 3625 /* PREFIX_0F3ADF */
09a2c6cf 3626 {
c0f3af97
L		 3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "aeskeygenassist", { XM, EXx, Ib } },
3630 { "(bad)", { XX } },
09a2c6cf
L		 3631 },
3632
c0f3af97 3633 /* PREFIX_VEX_10 */
09a2c6cf 3634 {
9e30b8e0 3635 { VEX_W_TABLE (VEX_W_10_P_0) },
c0f3af97 3636 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
9e30b8e0 3637 { VEX_W_TABLE (VEX_W_10_P_2) },
c0f3af97 3638 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3639 },
3640
c0f3af97 3641 /* PREFIX_VEX_11 */
09a2c6cf 3642 {
9e30b8e0 3643 { VEX_W_TABLE (VEX_W_11_P_0) },
c0f3af97 3644 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
9e30b8e0 3645 { VEX_W_TABLE (VEX_W_11_P_2) },
c0f3af97 3646 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3647 },
3648
c0f3af97 3649 /* PREFIX_VEX_12 */
09a2c6cf 3650 {
c0f3af97 3651 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
9e30b8e0 3652 { VEX_W_TABLE (VEX_W_12_P_1) },
c0f3af97 3653 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
9e30b8e0 3654 { VEX_W_TABLE (VEX_W_12_P_3) },
09a2c6cf
L		 3655 },
3656
c0f3af97 3657 /* PREFIX_VEX_16 */
09a2c6cf 3658 {
c0f3af97 3659 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
9e30b8e0 3660 { VEX_W_TABLE (VEX_W_16_P_1) },
c0f3af97
L		 3661 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3662 { "(bad)", { XX } },
5f754f58 3663 },
7c52e0e8 3664
c0f3af97 3665 /* PREFIX_VEX_2A */
5f754f58 3666 {
c0f3af97
L		 3667 { "(bad)", { XX } },
3668 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3669 { "(bad)", { XX } },
3670 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3671 },
7c52e0e8 3672
c0f3af97 3673 /* PREFIX_VEX_2C */
5f754f58 3674 {
c0f3af97
L		 3675 { "(bad)", { XX } },
3676 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3677 { "(bad)", { XX } },
3678 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3679 },
7c52e0e8 3680
c0f3af97 3681 /* PREFIX_VEX_2D */
7c52e0e8 3682 {
c0f3af97
L		 3683 { "(bad)", { XX } },
3684 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3685 { "(bad)", { XX } },
3686 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3687 },
3688
c0f3af97 3689 /* PREFIX_VEX_2E */
7c52e0e8 3690 {
c0f3af97
L		 3691 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3692 { "(bad)", { XX } },
3693 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3694 { "(bad)", { XX } },
7c52e0e8
L		 3695 },
3696
c0f3af97 3697 /* PREFIX_VEX_2F */
7c52e0e8 3698 {
c0f3af97
L		 3699 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3700 { "(bad)", { XX } },
3701 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3702 { "(bad)", { XX } },
7c52e0e8
L		 3703 },
3704
c0f3af97 3705 /* PREFIX_VEX_51 */
7c52e0e8 3706 {
9e30b8e0 3707 { VEX_W_TABLE (VEX_W_51_P_0) },
c0f3af97 3708 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
9e30b8e0 3709 { VEX_W_TABLE (VEX_W_51_P_2) },
c0f3af97 3710 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3711 },
3712
c0f3af97 3713 /* PREFIX_VEX_52 */
7c52e0e8 3714 {
9e30b8e0 3715 { VEX_W_TABLE (VEX_W_52_P_0) },
c0f3af97
L		 3716 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
7c52e0e8
L		 3719 },
3720
c0f3af97 3721 /* PREFIX_VEX_53 */
7c52e0e8 3722 {
9e30b8e0 3723 { VEX_W_TABLE (VEX_W_53_P_0) },
c0f3af97
L		 3724 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
7c52e0e8
L		 3727 },
3728
c0f3af97 3729 /* PREFIX_VEX_58 */
7c52e0e8 3730 {
9e30b8e0 3731 { VEX_W_TABLE (VEX_W_58_P_0) },
c0f3af97 3732 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
9e30b8e0 3733 { VEX_W_TABLE (VEX_W_58_P_2) },
c0f3af97 3734 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3735 },
3736
c0f3af97 3737 /* PREFIX_VEX_59 */
7c52e0e8 3738 {
9e30b8e0 3739 { VEX_W_TABLE (VEX_W_59_P_0) },
c0f3af97 3740 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
9e30b8e0 3741 { VEX_W_TABLE (VEX_W_59_P_2) },
c0f3af97 3742 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3743 },
3744
c0f3af97 3745 /* PREFIX_VEX_5A */
7c52e0e8 3746 {
9e30b8e0 3747 { VEX_W_TABLE (VEX_W_5A_P_0) },
c0f3af97
L		 3748 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3749 { "vcvtpd2ps%XY", { XMM, EXx } },
3750 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3751 },
3752
c0f3af97 3753 /* PREFIX_VEX_5B */
7c52e0e8 3754 {
9e30b8e0
L		 3755 { VEX_W_TABLE (VEX_W_5B_P_0) },
3756 { VEX_W_TABLE (VEX_W_5B_P_1) },
3757 { VEX_W_TABLE (VEX_W_5B_P_2) },
c0f3af97 3758 { "(bad)", { XX } },
7c52e0e8
L		 3759 },
3760
c0f3af97 3761 /* PREFIX_VEX_5C */
7c52e0e8 3762 {
9e30b8e0 3763 { VEX_W_TABLE (VEX_W_5C_P_0) },
c0f3af97 3764 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
9e30b8e0 3765 { VEX_W_TABLE (VEX_W_5C_P_2) },
c0f3af97 3766 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3767 },
3768
c0f3af97 3769 /* PREFIX_VEX_5D */
7c52e0e8 3770 {
9e30b8e0 3771 { VEX_W_TABLE (VEX_W_5D_P_0) },
c0f3af97 3772 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
9e30b8e0 3773 { VEX_W_TABLE (VEX_W_5D_P_2) },
c0f3af97 3774 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3775 },
3776
c0f3af97 3777 /* PREFIX_VEX_5E */
7c52e0e8 3778 {
9e30b8e0 3779 { VEX_W_TABLE (VEX_W_5E_P_0) },
c0f3af97 3780 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
9e30b8e0 3781 { VEX_W_TABLE (VEX_W_5E_P_2) },
c0f3af97 3782 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3783 },
3784
c0f3af97 3785 /* PREFIX_VEX_5F */
7c52e0e8 3786 {
9e30b8e0 3787 { VEX_W_TABLE (VEX_W_5F_P_0) },
c0f3af97 3788 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
9e30b8e0 3789 { VEX_W_TABLE (VEX_W_5F_P_2) },
c0f3af97 3790 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3791 },
3792
c0f3af97 3793 /* PREFIX_VEX_60 */
7c52e0e8 3794 {
c0f3af97
L		 3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3798 { "(bad)", { XX } },
7c52e0e8
L		 3799 },
3800
c0f3af97 3801 /* PREFIX_VEX_61 */
7c52e0e8 3802 {
c0f3af97
L		 3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3806 { "(bad)", { XX } },
7c52e0e8
L		 3807 },
3808
c0f3af97 3809 /* PREFIX_VEX_62 */
7c52e0e8 3810 {
c0f3af97
L		 3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3814 { "(bad)", { XX } },
7c52e0e8
L		 3815 },
3816
c0f3af97 3817 /* PREFIX_VEX_63 */
7c52e0e8 3818 {
c0f3af97
L		 3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3822 { "(bad)", { XX } },
7c52e0e8
L		 3823 },
3824
c0f3af97 3825 /* PREFIX_VEX_64 */
7c52e0e8 3826 {
c0f3af97
L		 3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3830 { "(bad)", { XX } },
7c52e0e8
L		 3831 },
3832
c0f3af97 3833 /* PREFIX_VEX_65 */
7c52e0e8 3834 {
c0f3af97
L		 3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3838 { "(bad)", { XX } },
7c52e0e8
L		 3839 },
3840
c0f3af97 3841 /* PREFIX_VEX_66 */
7c52e0e8 3842 {
c0f3af97
L		 3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3846 { "(bad)", { XX } },
7c52e0e8 3847 },
6439fc28 3848
c0f3af97 3849 /* PREFIX_VEX_67 */
331d2d0d 3850 {
c0f3af97
L		 3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3854 { "(bad)", { XX } },
3855 },
3856
3857 /* PREFIX_VEX_68 */
3858 {
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3862 { "(bad)", { XX } },
3863 },
3864
3865 /* PREFIX_VEX_69 */
3866 {
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3870 { "(bad)", { XX } },
3871 },
3872
3873 /* PREFIX_VEX_6A */
3874 {
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3878 { "(bad)", { XX } },
3879 },
3880
3881 /* PREFIX_VEX_6B */
3882 {
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3886 { "(bad)", { XX } },
3887 },
3888
3889 /* PREFIX_VEX_6C */
3890 {
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3894 { "(bad)", { XX } },
3895 },
3896
3897 /* PREFIX_VEX_6D */
3898 {
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3902 { "(bad)", { XX } },
3903 },
3904
3905 /* PREFIX_VEX_6E */
3906 {
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3910 { "(bad)", { XX } },
3911 },
3912
3913 /* PREFIX_VEX_6F */
3914 {
3915 { "(bad)", { XX } },
9e30b8e0
L		 3916 { VEX_W_TABLE (VEX_W_6F_P_1) },
3917 { VEX_W_TABLE (VEX_W_6F_P_2) },
c0f3af97
L		 3918 { "(bad)", { XX } },
3919 },
3920
3921 /* PREFIX_VEX_70 */
3922 {
3923 { "(bad)", { XX } },
3924 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3925 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3926 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3927 },
3928
3929 /* PREFIX_VEX_71_REG_2 */
3930 {
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3934 { "(bad)", { XX } },
3935 },
3936
3937 /* PREFIX_VEX_71_REG_4 */
3938 {
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3942 { "(bad)", { XX } },
3943 },
3944
3945 /* PREFIX_VEX_71_REG_6 */
3946 {
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3950 { "(bad)", { XX } },
3951 },
3952
3953 /* PREFIX_VEX_72_REG_2 */
3954 {
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3958 { "(bad)", { XX } },
3959 },
3960
3961 /* PREFIX_VEX_72_REG_4 */
3962 {
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3966 { "(bad)", { XX } },
3967 },
3968
3969 /* PREFIX_VEX_72_REG_6 */
3970 {
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
3973 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3974 { "(bad)", { XX } },
3975 },
3976
3977 /* PREFIX_VEX_73_REG_2 */
3978 {
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3982 { "(bad)", { XX } },
3983 },
3984
3985 /* PREFIX_VEX_73_REG_3 */
3986 {
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3990 { "(bad)", { XX } },
3991 },
3992
3993 /* PREFIX_VEX_73_REG_6 */
3994 {
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3998 { "(bad)", { XX } },
3999 },
4000
4001 /* PREFIX_VEX_73_REG_7 */
4002 {
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
4006 { "(bad)", { XX } },
4007 },
4008
4009 /* PREFIX_VEX_74 */
4010 {
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
4014 { "(bad)", { XX } },
4015 },
4016
4017 /* PREFIX_VEX_75 */
4018 {
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
4022 { "(bad)", { XX } },
4023 },
4024
4025 /* PREFIX_VEX_76 */
4026 {
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
4030 { "(bad)", { XX } },
4031 },
4032
4033 /* PREFIX_VEX_77 */
4034 {
9e30b8e0 4035 { VEX_W_TABLE (VEX_W_77_P_0) },
c0f3af97
L		 4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
4039 },
4040
4041 /* PREFIX_VEX_7C */
4042 {
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
9e30b8e0
L		 4045 { VEX_W_TABLE (VEX_W_7C_P_2) },
4046 { VEX_W_TABLE (VEX_W_7C_P_3) },
c0f3af97
L		 4047 },
4048
4049 /* PREFIX_VEX_7D */
4050 {
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
9e30b8e0
L		 4053 { VEX_W_TABLE (VEX_W_7D_P_2) },
4054 { VEX_W_TABLE (VEX_W_7D_P_3) },
c0f3af97
L		 4055 },
4056
4057 /* PREFIX_VEX_7E */
4058 {
4059 { "(bad)", { XX } },
4060 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
4061 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
4062 { "(bad)", { XX } },
4063 },
4064
4065 /* PREFIX_VEX_7F */
4066 {
4067 { "(bad)", { XX } },
9e30b8e0
L		 4068 { VEX_W_TABLE (VEX_W_7F_P_1) },
4069 { VEX_W_TABLE (VEX_W_7F_P_2) },
c0f3af97
L		 4070 { "(bad)", { XX } },
4071 },
4072
4073 /* PREFIX_VEX_C2 */
4074 {
9e30b8e0 4075 { VEX_W_TABLE (VEX_W_C2_P_0) },
c0f3af97 4076 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
9e30b8e0 4077 { VEX_W_TABLE (VEX_W_C2_P_2) },
c0f3af97
L		 4078 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
4079 },
4080
4081 /* PREFIX_VEX_C4 */
4082 {
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
4086 { "(bad)", { XX } },
4087 },
4088
4089 /* PREFIX_VEX_C5 */
4090 {
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
4094 { "(bad)", { XX } },
4095 },
4096
4097 /* PREFIX_VEX_D0 */
4098 {
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
9e30b8e0
L		 4101 { VEX_W_TABLE (VEX_W_D0_P_2) },
4102 { VEX_W_TABLE (VEX_W_D0_P_3) },
c0f3af97
L		 4103 },
4104
4105 /* PREFIX_VEX_D1 */
4106 {
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
4110 { "(bad)", { XX } },
4111 },
4112
4113 /* PREFIX_VEX_D2 */
4114 {
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
4118 { "(bad)", { XX } },
4119 },
4120
4121 /* PREFIX_VEX_D3 */
4122 {
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4126 { "(bad)", { XX } },
4127 },
4128
4129 /* PREFIX_VEX_D4 */
4130 {
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4134 { "(bad)", { XX } },
4135 },
4136
4137 /* PREFIX_VEX_D5 */
4138 {
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4142 { "(bad)", { XX } },
4143 },
4144
4145 /* PREFIX_VEX_D6 */
4146 {
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4150 { "(bad)", { XX } },
4151 },
4152
4153 /* PREFIX_VEX_D7 */
4154 {
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4158 { "(bad)", { XX } },
4159 },
4160
4161 /* PREFIX_VEX_D8 */
4162 {
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4166 { "(bad)", { XX } },
4167 },
4168
4169 /* PREFIX_VEX_D9 */
4170 {
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4174 { "(bad)", { XX } },
4175 },
4176
4177 /* PREFIX_VEX_DA */
4178 {
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4182 { "(bad)", { XX } },
4183 },
4184
4185 /* PREFIX_VEX_DB */
4186 {
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4190 { "(bad)", { XX } },
4191 },
4192
4193 /* PREFIX_VEX_DC */
4194 {
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4198 { "(bad)", { XX } },
4199 },
4200
4201 /* PREFIX_VEX_DD */
4202 {
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4206 { "(bad)", { XX } },
4207 },
4208
4209 /* PREFIX_VEX_DE */
4210 {
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4214 { "(bad)", { XX } },
4215 },
4216
4217 /* PREFIX_VEX_DF */
4218 {
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4222 { "(bad)", { XX } },
4223 },
4224
4225 /* PREFIX_VEX_E0 */
4226 {
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4230 { "(bad)", { XX } },
4231 },
4232
4233 /* PREFIX_VEX_E1 */
4234 {
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4238 { "(bad)", { XX } },
4239 },
4240
4241 /* PREFIX_VEX_E2 */
4242 {
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4246 { "(bad)", { XX } },
4247 },
4248
4249 /* PREFIX_VEX_E3 */
4250 {
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4254 { "(bad)", { XX } },
4255 },
4256
4257 /* PREFIX_VEX_E4 */
4258 {
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4262 { "(bad)", { XX } },
4263 },
4264
4265 /* PREFIX_VEX_E5 */
4266 {
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4270 { "(bad)", { XX } },
4271 },
4272
4273 /* PREFIX_VEX_E6 */
4274 {
4275 { "(bad)", { XX } },
9e30b8e0
L		 4276 { VEX_W_TABLE (VEX_W_E6_P_1) },
4277 { VEX_W_TABLE (VEX_W_E6_P_2) },
4278 { VEX_W_TABLE (VEX_W_E6_P_3) },
c0f3af97
L		 4279 },
4280
4281 /* PREFIX_VEX_E7 */
4282 {
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4286 { "(bad)", { XX } },
4287 },
4288
4289 /* PREFIX_VEX_E8 */
4290 {
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4294 { "(bad)", { XX } },
4295 },
4296
4297 /* PREFIX_VEX_E9 */
4298 {
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4302 { "(bad)", { XX } },
4303 },
4304
4305 /* PREFIX_VEX_EA */
4306 {
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4310 { "(bad)", { XX } },
4311 },
4312
4313 /* PREFIX_VEX_EB */
4314 {
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4318 { "(bad)", { XX } },
4319 },
4320
4321 /* PREFIX_VEX_EC */
4322 {
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4326 { "(bad)", { XX } },
4327 },
4328
4329 /* PREFIX_VEX_ED */
4330 {
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4334 { "(bad)", { XX } },
4335 },
4336
4337 /* PREFIX_VEX_EE */
4338 {
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4342 { "(bad)", { XX } },
4343 },
4344
4345 /* PREFIX_VEX_EF */
4346 {
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4350 { "(bad)", { XX } },
4351 },
4352
4353 /* PREFIX_VEX_F0 */
4354 {
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4359 },
4360
4361 /* PREFIX_VEX_F1 */
4362 {
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4366 { "(bad)", { XX } },
4367 },
4368
4369 /* PREFIX_VEX_F2 */
4370 {
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4374 { "(bad)", { XX } },
4375 },
4376
4377 /* PREFIX_VEX_F3 */
4378 {
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4382 { "(bad)", { XX } },
4383 },
4384
4385 /* PREFIX_VEX_F4 */
4386 {
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4390 { "(bad)", { XX } },
4391 },
4392
4393 /* PREFIX_VEX_F5 */
4394 {
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4398 { "(bad)", { XX } },
4399 },
4400
4401 /* PREFIX_VEX_F6 */
4402 {
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4406 { "(bad)", { XX } },
4407 },
4408
4409 /* PREFIX_VEX_F7 */
4410 {
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4414 { "(bad)", { XX } },
4415 },
4416
4417 /* PREFIX_VEX_F8 */
4418 {
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4422 { "(bad)", { XX } },
4423 },
4424
4425 /* PREFIX_VEX_F9 */
4426 {
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4430 { "(bad)", { XX } },
4431 },
4432
4433 /* PREFIX_VEX_FA */
4434 {
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4438 { "(bad)", { XX } },
4439 },
4440
4441 /* PREFIX_VEX_FB */
4442 {
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4446 { "(bad)", { XX } },
4447 },
4448
4449 /* PREFIX_VEX_FC */
4450 {
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4454 { "(bad)", { XX } },
4455 },
4456
4457 /* PREFIX_VEX_FD */
4458 {
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4462 { "(bad)", { XX } },
4463 },
4464
4465 /* PREFIX_VEX_FE */
4466 {
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4470 { "(bad)", { XX } },
4471 },
4472
4473 /* PREFIX_VEX_3800 */
4474 {
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4478 { "(bad)", { XX } },
4479 },
4480
4481 /* PREFIX_VEX_3801 */
4482 {
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4486 { "(bad)", { XX } },
4487 },
4488
4489 /* PREFIX_VEX_3802 */
4490 {
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4494 { "(bad)", { XX } },
4495 },
4496
4497 /* PREFIX_VEX_3803 */
4498 {
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4502 { "(bad)", { XX } },
4503 },
4504
4505 /* PREFIX_VEX_3804 */
4506 {
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4510 { "(bad)", { XX } },
4511 },
4512
4513 /* PREFIX_VEX_3805 */
4514 {
4515 { "(bad)", { XX } },
4516 { "(bad)", { XX } },
4517 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4518 { "(bad)", { XX } },
4519 },
4520
4521 /* PREFIX_VEX_3806 */
4522 {
4523 { "(bad)", { XX } },
4524 { "(bad)", { XX } },
4525 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4526 { "(bad)", { XX } },
4527 },
4528
4529 /* PREFIX_VEX_3807 */
4530 {
4531 { "(bad)", { XX } },
4532 { "(bad)", { XX } },
4533 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4534 { "(bad)", { XX } },
4535 },
4536
4537 /* PREFIX_VEX_3808 */
4538 {
4539 { "(bad)", { XX } },
4540 { "(bad)", { XX } },
4541 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4542 { "(bad)", { XX } },
4543 },
4544
4545 /* PREFIX_VEX_3809 */
4546 {
4547 { "(bad)", { XX } },
4548 { "(bad)", { XX } },
4549 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4550 { "(bad)", { XX } },
4551 },
4552
4553 /* PREFIX_VEX_380A */
4554 {
4555 { "(bad)", { XX } },
4556 { "(bad)", { XX } },
4557 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4558 { "(bad)", { XX } },
4559 },
4560
4561 /* PREFIX_VEX_380B */
4562 {
4563 { "(bad)", { XX } },
4564 { "(bad)", { XX } },
4565 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4566 { "(bad)", { XX } },
4567 },
4568
4569 /* PREFIX_VEX_380C */
4570 {
4571 { "(bad)", { XX } },
4572 { "(bad)", { XX } },
9e30b8e0 4573 { VEX_W_TABLE (VEX_W_380C_P_2) },
c0f3af97
L		 4574 { "(bad)", { XX } },
4575 },
4576
4577 /* PREFIX_VEX_380D */
4578 {
4579 { "(bad)", { XX } },
4580 { "(bad)", { XX } },
9e30b8e0 4581 { VEX_W_TABLE (VEX_W_380D_P_2) },
c0f3af97
L		 4582 { "(bad)", { XX } },
4583 },
4584
4585 /* PREFIX_VEX_380E */
4586 {
4587 { "(bad)", { XX } },
4588 { "(bad)", { XX } },
9e30b8e0 4589 { VEX_W_TABLE (VEX_W_380E_P_2) },
c0f3af97
L		 4590 { "(bad)", { XX } },
4591 },
4592
4593 /* PREFIX_VEX_380F */
4594 {
4595 { "(bad)", { XX } },
4596 { "(bad)", { XX } },
9e30b8e0 4597 { VEX_W_TABLE (VEX_W_380F_P_2) },
c0f3af97
L		 4598 { "(bad)", { XX } },
4599 },
4600
4601 /* PREFIX_VEX_3817 */
4602 {
4603 { "(bad)", { XX } },
4604 { "(bad)", { XX } },
9e30b8e0 4605 { VEX_W_TABLE (VEX_W_3817_P_2) },
c0f3af97
L		 4606 { "(bad)", { XX } },
4607 },
4608
4609 /* PREFIX_VEX_3818 */
4610 {
4611 { "(bad)", { XX } },
4612 { "(bad)", { XX } },
4613 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4614 { "(bad)", { XX } },
4615 },
4616
4617 /* PREFIX_VEX_3819 */
4618 {
4619 { "(bad)", { XX } },
4620 { "(bad)", { XX } },
4621 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4622 { "(bad)", { XX } },
4623 },
4624
4625 /* PREFIX_VEX_381A */
4626 {
4627 { "(bad)", { XX } },
4628 { "(bad)", { XX } },
4629 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4630 { "(bad)", { XX } },
4631 },
4632
4633 /* PREFIX_VEX_381C */
4634 {
4635 { "(bad)", { XX } },
4636 { "(bad)", { XX } },
4637 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4638 { "(bad)", { XX } },
4639 },
4640
4641 /* PREFIX_VEX_381D */
4642 {
4643 { "(bad)", { XX } },
4644 { "(bad)", { XX } },
4645 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4646 { "(bad)", { XX } },
4647 },
4648
4649 /* PREFIX_VEX_381E */
4650 {
4651 { "(bad)", { XX } },
4652 { "(bad)", { XX } },
4653 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4654 { "(bad)", { XX } },
4655 },
4656
4657 /* PREFIX_VEX_3820 */
4658 {
4659 { "(bad)", { XX } },
4660 { "(bad)", { XX } },
4661 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4662 { "(bad)", { XX } },
4663 },
4664
4665 /* PREFIX_VEX_3821 */
4666 {
4667 { "(bad)", { XX } },
4668 { "(bad)", { XX } },
4669 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4670 { "(bad)", { XX } },
4671 },
4672
4673 /* PREFIX_VEX_3822 */
4674 {
4675 { "(bad)", { XX } },
4676 { "(bad)", { XX } },
4677 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4678 { "(bad)", { XX } },
4679 },
4680
4681 /* PREFIX_VEX_3823 */
4682 {
4683 { "(bad)", { XX } },
4684 { "(bad)", { XX } },
4685 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4686 { "(bad)", { XX } },
4687 },
4688
4689 /* PREFIX_VEX_3824 */
4690 {
4691 { "(bad)", { XX } },
4692 { "(bad)", { XX } },
4693 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4694 { "(bad)", { XX } },
4695 },
4696
4697 /* PREFIX_VEX_3825 */
4698 {
4699 { "(bad)", { XX } },
4700 { "(bad)", { XX } },
4701 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4702 { "(bad)", { XX } },
4703 },
4704
4705 /* PREFIX_VEX_3828 */
4706 {
4707 { "(bad)", { XX } },
4708 { "(bad)", { XX } },
4709 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4710 { "(bad)", { XX } },
4711 },
4712
4713 /* PREFIX_VEX_3829 */
4714 {
4715 { "(bad)", { XX } },
4716 { "(bad)", { XX } },
4717 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4718 { "(bad)", { XX } },
4719 },
4720
4721 /* PREFIX_VEX_382A */
4722 {
4723 { "(bad)", { XX } },
4724 { "(bad)", { XX } },
4725 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4726 { "(bad)", { XX } },
4727 },
4728
4729 /* PREFIX_VEX_382B */
4730 {
4731 { "(bad)", { XX } },
4732 { "(bad)", { XX } },
4733 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4734 { "(bad)", { XX } },
4735 },
4736
4737 /* PREFIX_VEX_382C */
4738 {
4739 { "(bad)", { XX } },
4740 { "(bad)", { XX } },
4741 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4742 { "(bad)", { XX } },
4743 },
4744
4745 /* PREFIX_VEX_382D */
4746 {
4747 { "(bad)", { XX } },
4748 { "(bad)", { XX } },
4749 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4750 { "(bad)", { XX } },
4751 },
4752
4753 /* PREFIX_VEX_382E */
4754 {
4755 { "(bad)", { XX } },
4756 { "(bad)", { XX } },
4757 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4758 { "(bad)", { XX } },
4759 },
4760
4761 /* PREFIX_VEX_382F */
4762 {
4763 { "(bad)", { XX } },
4764 { "(bad)", { XX } },
4765 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4766 { "(bad)", { XX } },
4767 },
4768
4769 /* PREFIX_VEX_3830 */
4770 {
4771 { "(bad)", { XX } },
4772 { "(bad)", { XX } },
4773 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4774 { "(bad)", { XX } },
4775 },
4776
4777 /* PREFIX_VEX_3831 */
4778 {
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4782 { "(bad)", { XX } },
4783 },
4784
4785 /* PREFIX_VEX_3832 */
4786 {
4787 { "(bad)", { XX } },
4788 { "(bad)", { XX } },
4789 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4790 { "(bad)", { XX } },
4791 },
4792
4793 /* PREFIX_VEX_3833 */
4794 {
4795 { "(bad)", { XX } },
4796 { "(bad)", { XX } },
4797 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4798 { "(bad)", { XX } },
4799 },
4800
4801 /* PREFIX_VEX_3834 */
4802 {
4803 { "(bad)", { XX } },
4804 { "(bad)", { XX } },
4805 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4806 { "(bad)", { XX } },
4807 },
4808
4809 /* PREFIX_VEX_3835 */
4810 {
4811 { "(bad)", { XX } },
4812 { "(bad)", { XX } },
4813 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4814 { "(bad)", { XX } },
4815 },
4816
4817 /* PREFIX_VEX_3837 */
4818 {
4819 { "(bad)", { XX } },
4820 { "(bad)", { XX } },
4821 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4822 { "(bad)", { XX } },
4823 },
4824
4825 /* PREFIX_VEX_3838 */
4826 {
4827 { "(bad)", { XX } },
4828 { "(bad)", { XX } },
4829 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4830 { "(bad)", { XX } },
4831 },
4832
4833 /* PREFIX_VEX_3839 */
4834 {
4835 { "(bad)", { XX } },
4836 { "(bad)", { XX } },
4837 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4838 { "(bad)", { XX } },
4839 },
4840
4841 /* PREFIX_VEX_383A */
4842 {
4843 { "(bad)", { XX } },
4844 { "(bad)", { XX } },
4845 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4846 { "(bad)", { XX } },
4847 },
4848
4849 /* PREFIX_VEX_383B */
4850 {
4851 { "(bad)", { XX } },
4852 { "(bad)", { XX } },
4853 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4854 { "(bad)", { XX } },
4855 },
4856
4857 /* PREFIX_VEX_383C */
4858 {
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
4861 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4862 { "(bad)", { XX } },
4863 },
4864
4865 /* PREFIX_VEX_383D */
4866 {
4867 { "(bad)", { XX } },
4868 { "(bad)", { XX } },
4869 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4870 { "(bad)", { XX } },
4871 },
4872
4873 /* PREFIX_VEX_383E */
4874 {
4875 { "(bad)", { XX } },
4876 { "(bad)", { XX } },
4877 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4878 { "(bad)", { XX } },
4879 },
4880
4881 /* PREFIX_VEX_383F */
4882 {
4883 { "(bad)", { XX } },
4884 { "(bad)", { XX } },
4885 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4886 { "(bad)", { XX } },
4887 },
4888
4889 /* PREFIX_VEX_3840 */
4890 {
4891 { "(bad)", { XX } },
4892 { "(bad)", { XX } },
4893 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4894 { "(bad)", { XX } },
4895 },
4896
4897 /* PREFIX_VEX_3841 */
4898 {
4899 { "(bad)", { XX } },
4900 { "(bad)", { XX } },
4901 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4902 { "(bad)", { XX } },
4903 },
4904
0bfee649 4905 /* PREFIX_VEX_3896 */
a5ff0eb2
L		 4906 {
4907 { "(bad)", { XX } },
4908 { "(bad)", { XX } },
0bfee649 4909 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4910 { "(bad)", { XX } },
4911 },
4912
0bfee649 4913 /* PREFIX_VEX_3897 */
a5ff0eb2
L		 4914 {
4915 { "(bad)", { XX } },
4916 { "(bad)", { XX } },
0bfee649 4917 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4918 { "(bad)", { XX } },
4919 },
4920
0bfee649 4921 /* PREFIX_VEX_3898 */
a5ff0eb2
L		 4922 {
4923 { "(bad)", { XX } },
4924 { "(bad)", { XX } },
0bfee649 4925 { "vfmadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4926 { "(bad)", { XX } },
4927 },
4928
0bfee649 4929 /* PREFIX_VEX_3899 */
a5ff0eb2
L		 4930 {
4931 { "(bad)", { XX } },
4932 { "(bad)", { XX } },
0bfee649 4933 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
a5ff0eb2
L		 4934 { "(bad)", { XX } },
4935 },
4936
0bfee649 4937 /* PREFIX_VEX_389A */
a5ff0eb2
L		 4938 {
4939 { "(bad)", { XX } },
4940 { "(bad)", { XX } },
0bfee649 4941 { "vfmsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4942 { "(bad)", { XX } },
4943 },
4944
0bfee649 4945 /* PREFIX_VEX_389B */
c0f3af97
L		 4946 {
4947 { "(bad)", { XX } },
4948 { "(bad)", { XX } },
0bfee649 4949 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4950 { "(bad)", { XX } },
4951 },
4952
0bfee649 4953 /* PREFIX_VEX_389C */
c0f3af97
L		 4954 {
4955 { "(bad)", { XX } },
4956 { "(bad)", { XX } },
0bfee649 4957 { "vfnmadd132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4958 { "(bad)", { XX } },
4959 },
4960
0bfee649 4961 /* PREFIX_VEX_389D */
c0f3af97
L		 4962 {
4963 { "(bad)", { XX } },
4964 { "(bad)", { XX } },
0bfee649 4965 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4966 { "(bad)", { XX } },
4967 },
4968
0bfee649 4969 /* PREFIX_VEX_389E */
c0f3af97
L		 4970 {
4971 { "(bad)", { XX } },
4972 { "(bad)", { XX } },
0bfee649 4973 { "vfnmsub132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4974 { "(bad)", { XX } },
4975 },
4976
0bfee649 4977 /* PREFIX_VEX_389F */
c0f3af97
L		 4978 {
4979 { "(bad)", { XX } },
4980 { "(bad)", { XX } },
0bfee649 4981 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4982 { "(bad)", { XX } },
4983 },
4984
0bfee649 4985 /* PREFIX_VEX_38A6 */
c0f3af97
L		 4986 {
4987 { "(bad)", { XX } },
4988 { "(bad)", { XX } },
0bfee649 4989 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4990 { "(bad)", { XX } },
4991 },
4992
0bfee649 4993 /* PREFIX_VEX_38A7 */
c0f3af97
L		 4994 {
4995 { "(bad)", { XX } },
4996 { "(bad)", { XX } },
0bfee649 4997 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4998 { "(bad)", { XX } },
4999 },
5000
0bfee649 5001 /* PREFIX_VEX_38A8 */
c0f3af97
L		 5002 {
5003 { "(bad)", { XX } },
5004 { "(bad)", { XX } },
0bfee649 5005 { "vfmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5006 { "(bad)", { XX } },
5007 },
5008
0bfee649 5009 /* PREFIX_VEX_38A9 */
c0f3af97
L		 5010 {
5011 { "(bad)", { XX } },
5012 { "(bad)", { XX } },
0bfee649 5013 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5014 { "(bad)", { XX } },
5015 },
5016
0bfee649 5017 /* PREFIX_VEX_38AA */
c0f3af97
L		 5018 {
5019 { "(bad)", { XX } },
5020 { "(bad)", { XX } },
0bfee649 5021 { "vfmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5022 { "(bad)", { XX } },
5023 },
5024
0bfee649 5025 /* PREFIX_VEX_38AB */
c0f3af97
L		 5026 {
5027 { "(bad)", { XX } },
5028 { "(bad)", { XX } },
0bfee649 5029 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5030 { "(bad)", { XX } },
5031 },
5032
0bfee649 5033 /* PREFIX_VEX_38AC */
c0f3af97
L		 5034 {
5035 { "(bad)", { XX } },
5036 { "(bad)", { XX } },
0bfee649 5037 { "vfnmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5038 { "(bad)", { XX } },
5039 },
5040
0bfee649 5041 /* PREFIX_VEX_38AD */
c0f3af97
L		 5042 {
5043 { "(bad)", { XX } },
5044 { "(bad)", { XX } },
0bfee649 5045 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5046 { "(bad)", { XX } },
5047 },
5048
0bfee649 5049 /* PREFIX_VEX_38AE */
c0f3af97
L		 5050 {
5051 { "(bad)", { XX } },
5052 { "(bad)", { XX } },
0bfee649 5053 { "vfnmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5054 { "(bad)", { XX } },
5055 },
5056
0bfee649 5057 /* PREFIX_VEX_38AF */
c0f3af97
L		 5058 {
5059 { "(bad)", { XX } },
5060 { "(bad)", { XX } },
0bfee649 5061 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5062 { "(bad)", { XX } },
5063 },
5064
0bfee649 5065 /* PREFIX_VEX_38B6 */
c0f3af97
L		 5066 {
5067 { "(bad)", { XX } },
5068 { "(bad)", { XX } },
0bfee649 5069 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5070 { "(bad)", { XX } },
5071 },
5072
0bfee649 5073 /* PREFIX_VEX_38B7 */
c0f3af97
L		 5074 {
5075 { "(bad)", { XX } },
5076 { "(bad)", { XX } },
0bfee649 5077 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5078 { "(bad)", { XX } },
5079 },
5080
0bfee649 5081 /* PREFIX_VEX_38B8 */
c0f3af97
L		 5082 {
5083 { "(bad)", { XX } },
5084 { "(bad)", { XX } },
0bfee649 5085 { "vfmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5086 { "(bad)", { XX } },
5087 },
5088
0bfee649 5089 /* PREFIX_VEX_38B9 */
c0f3af97
L		 5090 {
5091 { "(bad)", { XX } },
5092 { "(bad)", { XX } },
0bfee649 5093 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5094 { "(bad)", { XX } },
5095 },
5096
0bfee649 5097 /* PREFIX_VEX_38BA */
c0f3af97
L		 5098 {
5099 { "(bad)", { XX } },
5100 { "(bad)", { XX } },
0bfee649 5101 { "vfmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5102 { "(bad)", { XX } },
5103 },
5104
0bfee649 5105 /* PREFIX_VEX_38BB */
c0f3af97
L		 5106 {
5107 { "(bad)", { XX } },
5108 { "(bad)", { XX } },
0bfee649 5109 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5110 { "(bad)", { XX } },
5111 },
5112
0bfee649 5113 /* PREFIX_VEX_38BC */
c0f3af97
L		 5114 {
5115 { "(bad)", { XX } },
5116 { "(bad)", { XX } },
0bfee649 5117 { "vfnmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5118 { "(bad)", { XX } },
5119 },
5120
0bfee649 5121 /* PREFIX_VEX_38BD */
c0f3af97
L		 5122 {
5123 { "(bad)", { XX } },
5124 { "(bad)", { XX } },
0bfee649 5125 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5126 { "(bad)", { XX } },
5127 },
5128
0bfee649 5129 /* PREFIX_VEX_38BE */
c0f3af97
L		 5130 {
5131 { "(bad)", { XX } },
5132 { "(bad)", { XX } },
0bfee649 5133 { "vfnmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 5134 { "(bad)", { XX } },
5135 },
5136
0bfee649 5137 /* PREFIX_VEX_38BF */
c0f3af97
L		 5138 {
5139 { "(bad)", { XX } },
5140 { "(bad)", { XX } },
0bfee649 5141 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 5142 { "(bad)", { XX } },
5143 },
5144
0bfee649 5145 /* PREFIX_VEX_38DB */
c0f3af97
L		 5146 {
5147 { "(bad)", { XX } },
5148 { "(bad)", { XX } },
0bfee649 5149 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
c0f3af97
L		 5150 { "(bad)", { XX } },
5151 },
5152
0bfee649 5153 /* PREFIX_VEX_38DC */
c0f3af97
L		 5154 {
5155 { "(bad)", { XX } },
5156 { "(bad)", { XX } },
0bfee649 5157 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
c0f3af97
L		 5158 { "(bad)", { XX } },
5159 },
5160
0bfee649 5161 /* PREFIX_VEX_38DD */
c0f3af97
L		 5162 {
5163 { "(bad)", { XX } },
5164 { "(bad)", { XX } },
0bfee649 5165 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
c0f3af97
L		 5166 { "(bad)", { XX } },
5167 },
5168
0bfee649 5169 /* PREFIX_VEX_38DE */
c0f3af97
L		 5170 {
5171 { "(bad)", { XX } },
5172 { "(bad)", { XX } },
0bfee649 5173 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
c0f3af97
L		 5174 { "(bad)", { XX } },
5175 },
5176
0bfee649 5177 /* PREFIX_VEX_38DF */
c0f3af97
L		 5178 {
5179 { "(bad)", { XX } },
5180 { "(bad)", { XX } },
0bfee649 5181 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
c0f3af97
L		 5182 { "(bad)", { XX } },
5183 },
5184
0bfee649 5185 /* PREFIX_VEX_3A04 */
c0f3af97
L		 5186 {
5187 { "(bad)", { XX } },
5188 { "(bad)", { XX } },
9e30b8e0 5189 { VEX_W_TABLE (VEX_W_3A04_P_2) },
c0f3af97
L		 5190 { "(bad)", { XX } },
5191 },
5192
0bfee649 5193 /* PREFIX_VEX_3A05 */
c0f3af97
L		 5194 {
5195 { "(bad)", { XX } },
5196 { "(bad)", { XX } },
9e30b8e0 5197 { VEX_W_TABLE (VEX_W_3A05_P_2) },
c0f3af97
L		 5198 { "(bad)", { XX } },
5199 },
5200
0bfee649 5201 /* PREFIX_VEX_3A06 */
c0f3af97
L		 5202 {
5203 { "(bad)", { XX } },
5204 { "(bad)", { XX } },
0bfee649 5205 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
c0f3af97
L		 5206 { "(bad)", { XX } },
5207 },
5208
0bfee649 5209 /* PREFIX_VEX_3A08 */
c0f3af97
L		 5210 {
5211 { "(bad)", { XX } },
5212 { "(bad)", { XX } },
9e30b8e0 5213 { VEX_W_TABLE (VEX_W_3A08_P_2) },
c0f3af97
L		 5214 { "(bad)", { XX } },
5215 },
5216
0bfee649 5217 /* PREFIX_VEX_3A09 */
c0f3af97
L		 5218 {
5219 { "(bad)", { XX } },
5220 { "(bad)", { XX } },
9e30b8e0 5221 { VEX_W_TABLE (VEX_W_3A09_P_2) },
c0f3af97
L		 5222 { "(bad)", { XX } },
5223 },
5224
0bfee649 5225 /* PREFIX_VEX_3A0A */
c0f3af97
L		 5226 {
5227 { "(bad)", { XX } },
5228 { "(bad)", { XX } },
0bfee649
L		 5229 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
5230 { "(bad)", { XX } },
5231 },
5232
5233 /* PREFIX_VEX_3A0B */
5234 {
5235 { "(bad)", { XX } },
5236 { "(bad)", { XX } },
5237 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
5238 { "(bad)", { XX } },
5239 },
5240
5241 /* PREFIX_VEX_3A0C */
5242 {
5243 { "(bad)", { XX } },
5244 { "(bad)", { XX } },
9e30b8e0 5245 { VEX_W_TABLE (VEX_W_3A0C_P_2) },
0bfee649
L		 5246 { "(bad)", { XX } },
5247 },
5248
5249 /* PREFIX_VEX_3A0D */
5250 {
5251 { "(bad)", { XX } },
5252 { "(bad)", { XX } },
9e30b8e0 5253 { VEX_W_TABLE (VEX_W_3A0D_P_2) },
c0f3af97
L		 5254 { "(bad)", { XX } },
5255 },
5256
0bfee649
L		 5257 /* PREFIX_VEX_3A0E */
5258 {
5259 { "(bad)", { XX } },
5260 { "(bad)", { XX } },
5261 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5262 { "(bad)", { XX } },
5263 },
5264
5265 /* PREFIX_VEX_3A0F */
5266 {
5267 { "(bad)", { XX } },
5268 { "(bad)", { XX } },
5269 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5270 { "(bad)", { XX } },
5271 },
5272
5273 /* PREFIX_VEX_3A14 */
5274 {
5275 { "(bad)", { XX } },
5276 { "(bad)", { XX } },
5277 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5278 { "(bad)", { XX } },
5279 },
5280
5281 /* PREFIX_VEX_3A15 */
5282 {
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5286 { "(bad)", { XX } },
5287 },
5288
5289 /* PREFIX_VEX_3A16 */
c0f3af97
L		 5290 {
5291 { "(bad)", { XX } },
5292 { "(bad)", { XX } },
0bfee649 5293 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
c0f3af97
L		 5294 { "(bad)", { XX } },
5295 },
5296
0bfee649 5297 /* PREFIX_VEX_3A17 */
c0f3af97
L		 5298 {
5299 { "(bad)", { XX } },
5300 { "(bad)", { XX } },
0bfee649 5301 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
c0f3af97
L		 5302 { "(bad)", { XX } },
5303 },
5304
0bfee649 5305 /* PREFIX_VEX_3A18 */
c0f3af97
L		 5306 {
5307 { "(bad)", { XX } },
5308 { "(bad)", { XX } },
0bfee649 5309 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
c0f3af97
L		 5310 { "(bad)", { XX } },
5311 },
5312
0bfee649 5313 /* PREFIX_VEX_3A19 */
c0f3af97
L		 5314 {
5315 { "(bad)", { XX } },
5316 { "(bad)", { XX } },
0bfee649 5317 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
c0f3af97
L		 5318 { "(bad)", { XX } },
5319 },
5320
0bfee649 5321 /* PREFIX_VEX_3A20 */
c0f3af97
L		 5322 {
5323 { "(bad)", { XX } },
5324 { "(bad)", { XX } },
0bfee649 5325 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
c0f3af97
L		 5326 { "(bad)", { XX } },
5327 },
5328
0bfee649 5329 /* PREFIX_VEX_3A21 */
c0f3af97
L		 5330 {
5331 { "(bad)", { XX } },
5332 { "(bad)", { XX } },
0bfee649 5333 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
c0f3af97
L		 5334 { "(bad)", { XX } },
5335 },
5336
0bfee649
L		 5337 /* PREFIX_VEX_3A22 */
5338 {
5339 { "(bad)", { XX } },
5340 { "(bad)", { XX } },
5341 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5342 { "(bad)", { XX } },
5343 },
5344
5345 /* PREFIX_VEX_3A40 */
c0f3af97
L		 5346 {
5347 { "(bad)", { XX } },
5348 { "(bad)", { XX } },
9e30b8e0 5349 { VEX_W_TABLE (VEX_W_3A40_P_2) },
c0f3af97
L		 5350 { "(bad)", { XX } },
5351 },
5352
0bfee649 5353 /* PREFIX_VEX_3A41 */
c0f3af97
L		 5354 {
5355 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
0bfee649 5357 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
c0f3af97
L		 5358 { "(bad)", { XX } },
5359 },
5360
0bfee649 5361 /* PREFIX_VEX_3A42 */
c0f3af97
L		 5362 {
5363 { "(bad)", { XX } },
5364 { "(bad)", { XX } },
0bfee649 5365 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
c0f3af97
L		 5366 { "(bad)", { XX } },
5367 },
5368
ce2f5b3c
L		 5369 /* PREFIX_VEX_3A44 */
5370 {
5371 { "(bad)", { XX } },
5372 { "(bad)", { XX } },
5373 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5374 { "(bad)", { XX } },
5375 },
5376
0bfee649 5377 /* PREFIX_VEX_3A4A */
c0f3af97
L		 5378 {
5379 { "(bad)", { XX } },
5380 { "(bad)", { XX } },
9e30b8e0 5381 { VEX_W_TABLE (VEX_W_3A4A_P_2) },
c0f3af97
L		 5382 { "(bad)", { XX } },
5383 },
5384
0bfee649 5385 /* PREFIX_VEX_3A4B */
c0f3af97
L		 5386 {
5387 { "(bad)", { XX } },
5388 { "(bad)", { XX } },
9e30b8e0 5389 { VEX_W_TABLE (VEX_W_3A4B_P_2) },
c0f3af97
L		 5390 { "(bad)", { XX } },
5391 },
5392
0bfee649 5393 /* PREFIX_VEX_3A4C */
c0f3af97
L		 5394 {
5395 { "(bad)", { XX } },
5396 { "(bad)", { XX } },
0bfee649 5397 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
c0f3af97
L		 5398 { "(bad)", { XX } },
5399 },
5400
922d8de8
DR		 5401 /* PREFIX_VEX_3A5C */
5402 {
5403 { "(bad)", { XX } },
5404 { "(bad)", { XX } },
206c2556 5405 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5406 { "(bad)", { XX } },
5407 },
5408
5409 /* PREFIX_VEX_3A5D */
5410 {
5411 { "(bad)", { XX } },
5412 { "(bad)", { XX } },
206c2556 5413 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5414 { "(bad)", { XX } },
5415 },
5416
5417 /* PREFIX_VEX_3A5E */
5418 {
5419 { "(bad)", { XX } },
5420 { "(bad)", { XX } },
206c2556 5421 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5422 { "(bad)", { XX } },
5423 },
5424
5425 /* PREFIX_VEX_3A5F */
5426 {
5427 { "(bad)", { XX } },
5428 { "(bad)", { XX } },
206c2556 5429 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5430 { "(bad)", { XX } },
5431 },
5432
0bfee649 5433 /* PREFIX_VEX_3A60 */
c0f3af97
L		 5434 {
5435 { "(bad)", { XX } },
5436 { "(bad)", { XX } },
0bfee649 5437 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
c0f3af97
L		 5438 { "(bad)", { XX } },
5439 },
5440
0bfee649 5441 /* PREFIX_VEX_3A61 */
c0f3af97
L		 5442 {
5443 { "(bad)", { XX } },
5444 { "(bad)", { XX } },
0bfee649 5445 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
c0f3af97
L		 5446 { "(bad)", { XX } },
5447 },
5448
0bfee649 5449 /* PREFIX_VEX_3A62 */
c0f3af97
L		 5450 {
5451 { "(bad)", { XX } },
5452 { "(bad)", { XX } },
0bfee649 5453 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
c0f3af97
L		 5454 { "(bad)", { XX } },
5455 },
5456
0bfee649 5457 /* PREFIX_VEX_3A63 */
c0f3af97
L		 5458 {
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
0bfee649 5461 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
c0f3af97
L		 5462 { "(bad)", { XX } },
5463 },
a5ff0eb2 5464
922d8de8
DR		 5465 /* PREFIX_VEX_3A68 */
5466 {
5467 { "(bad)", { XX } },
5468 { "(bad)", { XX } },
206c2556 5469 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5470 { "(bad)", { XX } },
5471 },
5472
5473 /* PREFIX_VEX_3A69 */
5474 {
5475 { "(bad)", { XX } },
5476 { "(bad)", { XX } },
206c2556 5477 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5478 { "(bad)", { XX } },
5479 },
5480
5481 /* PREFIX_VEX_3A6A */
5482 {
5483 { "(bad)", { XX } },
5484 { "(bad)", { XX } },
5485 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5486 { "(bad)", { XX } },
5487 },
5488
5489 /* PREFIX_VEX_3A6B */
5490 {
5491 { "(bad)", { XX } },
5492 { "(bad)", { XX } },
5493 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5494 { "(bad)", { XX } },
5495 },
5496
5497 /* PREFIX_VEX_3A6C */
5498 {
5499 { "(bad)", { XX } },
5500 { "(bad)", { XX } },
206c2556 5501 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5502 { "(bad)", { XX } },
5503 },
5504
5505 /* PREFIX_VEX_3A6D */
5506 {
5507 { "(bad)", { XX } },
5508 { "(bad)", { XX } },
206c2556 5509 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5510 { "(bad)", { XX } },
5511 },
5512
5513 /* PREFIX_VEX_3A6E */
5514 {
5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
5517 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5518 { "(bad)", { XX } },
5519 },
5520
5521 /* PREFIX_VEX_3A6F */
5522 {
5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5526 { "(bad)", { XX } },
5527 },
5528
5529 /* PREFIX_VEX_3A78 */
5530 {
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
206c2556 5533 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5534 { "(bad)", { XX } },
5535 },
5536
5537 /* PREFIX_VEX_3A79 */
5538 {
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
206c2556 5541 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5542 { "(bad)", { XX } },
5543 },
5544
5545 /* PREFIX_VEX_3A7A */
5546 {
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5550 { "(bad)", { XX } },
5551 },
5552
5553 /* PREFIX_VEX_3A7B */
5554 {
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5558 { "(bad)", { XX } },
5559 },
5560
5561 /* PREFIX_VEX_3A7C */
5562 {
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
206c2556 5565 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5566 { "(bad)", { XX } },
5567 },
5568
5569 /* PREFIX_VEX_3A7D */
5570 {
5571 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
206c2556 5573 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5574 { "(bad)", { XX } },
5575 },
5576
5577 /* PREFIX_VEX_3A7E */
5578 {
5579 { "(bad)", { XX } },
5580 { "(bad)", { XX } },
5581 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5582 { "(bad)", { XX } },
5583 },
5584
5585 /* PREFIX_VEX_3A7F */
5586 {
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5590 { "(bad)", { XX } },
5591 },
5592
a5ff0eb2
L		 5593 /* PREFIX_VEX_3ADF */
5594 {
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5598 { "(bad)", { XX } },
5599 },
c0f3af97
L		 5600};
5601
5602static const struct dis386 x86_64_table[][2] = {
5603 /* X86_64_06 */
5604 {
5605 { "push{T|}", { es } },
5606 { "(bad)", { XX } },
5607 },
5608
5609 /* X86_64_07 */
5610 {
5611 { "pop{T|}", { es } },
5612 { "(bad)", { XX } },
5613 },
5614
5615 /* X86_64_0D */
5616 {
5617 { "push{T|}", { cs } },
5618 { "(bad)", { XX } },
5619 },
5620
5621 /* X86_64_16 */
5622 {
5623 { "push{T|}", { ss } },
5624 { "(bad)", { XX } },
5625 },
5626
5627 /* X86_64_17 */
5628 {
5629 { "pop{T|}", { ss } },
5630 { "(bad)", { XX } },
5631 },
5632
5633 /* X86_64_1E */
5634 {
5635 { "push{T|}", { ds } },
5636 { "(bad)", { XX } },
5637 },
5638
5639 /* X86_64_1F */
5640 {
5641 { "pop{T|}", { ds } },
5642 { "(bad)", { XX } },
5643 },
5644
5645 /* X86_64_27 */
5646 {
5647 { "daa", { XX } },
5648 { "(bad)", { XX } },
5649 },
5650
5651 /* X86_64_2F */
5652 {
5653 { "das", { XX } },
5654 { "(bad)", { XX } },
5655 },
5656
5657 /* X86_64_37 */
5658 {
5659 { "aaa", { XX } },
5660 { "(bad)", { XX } },
5661 },
5662
5663 /* X86_64_3F */
5664 {
5665 { "aas", { XX } },
5666 { "(bad)", { XX } },
5667 },
5668
5669 /* X86_64_60 */
5670 {
5671 { "pusha{P|}", { XX } },
5672 { "(bad)", { XX } },
5673 },
5674
5675 /* X86_64_61 */
5676 {
5677 { "popa{P|}", { XX } },
5678 { "(bad)", { XX } },
5679 },
5680
5681 /* X86_64_62 */
5682 {
5683 { MOD_TABLE (MOD_62_32BIT) },
5684 { "(bad)", { XX } },
5685 },
5686
5687 /* X86_64_63 */
5688 {
5689 { "arpl", { Ew, Gw } },
5690 { "movs{lq|xd}", { Gv, Ed } },
5691 },
5692
5693 /* X86_64_6D */
5694 {
5695 { "ins{R|}", { Yzr, indirDX } },
5696 { "ins{G|}", { Yzr, indirDX } },
5697 },
5698
5699 /* X86_64_6F */
5700 {
5701 { "outs{R|}", { indirDXr, Xz } },
5702 { "outs{G|}", { indirDXr, Xz } },
5703 },
5704
5705 /* X86_64_9A */
5706 {
5707 { "Jcall{T|}", { Ap } },
5708 { "(bad)", { XX } },
5709 },
5710
5711 /* X86_64_C4 */
5712 {
5713 { MOD_TABLE (MOD_C4_32BIT) },
5714 { VEX_C4_TABLE (VEX_0F) },
5715 },
5716
5717 /* X86_64_C5 */
5718 {
5719 { MOD_TABLE (MOD_C5_32BIT) },
5720 { VEX_C5_TABLE (VEX_0F) },
5721 },
5722
5723 /* X86_64_CE */
5724 {
5725 { "into", { XX } },
5726 { "(bad)", { XX } },
5727 },
5728
5729 /* X86_64_D4 */
5730 {
5731 { "aam", { sIb } },
5732 { "(bad)", { XX } },
5733 },
5734
5735 /* X86_64_D5 */
5736 {
5737 { "aad", { sIb } },
5738 { "(bad)", { XX } },
5739 },
5740
5741 /* X86_64_EA */
5742 {
5743 { "Jjmp{T|}", { Ap } },
5744 { "(bad)", { XX } },
5745 },
5746
5747 /* X86_64_0F01_REG_0 */
5748 {
5749 { "sgdt{Q|IQ}", { M } },
5750 { "sgdt", { M } },
5751 },
5752
5753 /* X86_64_0F01_REG_1 */
5754 {
5755 { "sidt{Q|IQ}", { M } },
5756 { "sidt", { M } },
5757 },
5758
5759 /* X86_64_0F01_REG_2 */
5760 {
5761 { "lgdt{Q|Q}", { M } },
5762 { "lgdt", { M } },
5763 },
5764
5765 /* X86_64_0F01_REG_3 */
5766 {
5767 { "lidt{Q|Q}", { M } },
5768 { "lidt", { M } },
5769 },
5770};
5771
5772static const struct dis386 three_byte_table[][256] = {
c1e679ec
DR		 5773
5774 /* THREE_BYTE_0F38 */
c0f3af97
L		 5775 {
5776 /* 00 */
c1e679ec
DR		 5777 { "pshufb", { MX, EM } },
5778 { "phaddw", { MX, EM } },
5779 { "phaddd", { MX, EM } },
5780 { "phaddsw", { MX, EM } },
5781 { "pmaddubsw", { MX, EM } },
5782 { "phsubw", { MX, EM } },
5783 { "phsubd", { MX, EM } },
5784 { "phsubsw", { MX, EM } },
c0f3af97 5785 /* 08 */
c1e679ec
DR		 5786 { "psignb", { MX, EM } },
5787 { "psignw", { MX, EM } },
5788 { "psignd", { MX, EM } },
5789 { "pmulhrsw", { MX, EM } },
c0f3af97
L		 5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
f88c9eb0
SP		 5794 /* 10 */
5795 { PREFIX_TABLE (PREFIX_0F3810) },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
5799 { PREFIX_TABLE (PREFIX_0F3814) },
5800 { PREFIX_TABLE (PREFIX_0F3815) },
5801 { "(bad)", { XX } },
5802 { PREFIX_TABLE (PREFIX_0F3817) },
5803 /* 18 */
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5808 { "pabsb", { MX, EM } },
5809 { "pabsw", { MX, EM } },
5810 { "pabsd", { MX, EM } },
5811 { "(bad)", { XX } },
5812 /* 20 */
5813 { PREFIX_TABLE (PREFIX_0F3820) },
5814 { PREFIX_TABLE (PREFIX_0F3821) },
5815 { PREFIX_TABLE (PREFIX_0F3822) },
5816 { PREFIX_TABLE (PREFIX_0F3823) },
5817 { PREFIX_TABLE (PREFIX_0F3824) },
5818 { PREFIX_TABLE (PREFIX_0F3825) },
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 /* 28 */
5822 { PREFIX_TABLE (PREFIX_0F3828) },
5823 { PREFIX_TABLE (PREFIX_0F3829) },
5824 { PREFIX_TABLE (PREFIX_0F382A) },
5825 { PREFIX_TABLE (PREFIX_0F382B) },
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 /* 30 */
5831 { PREFIX_TABLE (PREFIX_0F3830) },
5832 { PREFIX_TABLE (PREFIX_0F3831) },
5833 { PREFIX_TABLE (PREFIX_0F3832) },
5834 { PREFIX_TABLE (PREFIX_0F3833) },
5835 { PREFIX_TABLE (PREFIX_0F3834) },
5836 { PREFIX_TABLE (PREFIX_0F3835) },
5837 { "(bad)", { XX } },
5838 { PREFIX_TABLE (PREFIX_0F3837) },
5839 /* 38 */
5840 { PREFIX_TABLE (PREFIX_0F3838) },
5841 { PREFIX_TABLE (PREFIX_0F3839) },
5842 { PREFIX_TABLE (PREFIX_0F383A) },
5843 { PREFIX_TABLE (PREFIX_0F383B) },
5844 { PREFIX_TABLE (PREFIX_0F383C) },
5845 { PREFIX_TABLE (PREFIX_0F383D) },
5846 { PREFIX_TABLE (PREFIX_0F383E) },
5847 { PREFIX_TABLE (PREFIX_0F383F) },
5848 /* 40 */
5849 { PREFIX_TABLE (PREFIX_0F3840) },
5850 { PREFIX_TABLE (PREFIX_0F3841) },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
5857 /* 48 */
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 /* 50 */
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 { "(bad)", { XX } },
5874 { "(bad)", { XX } },
5875 /* 58 */
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 /* 60 */
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 /* 68 */
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 /* 70 */
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 /* 78 */
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 /* 80 */
5921 { PREFIX_TABLE (PREFIX_0F3880) },
5922 { PREFIX_TABLE (PREFIX_0F3881) },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 /* 88 */
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 /* 90 */
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 /* 98 */
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 /* a0 */
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 /* a8 */
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 /* b0 */
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 /* b8 */
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 /* c0 */
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 /* c8 */
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 /* d0 */
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 /* d8 */
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { PREFIX_TABLE (PREFIX_0F38DB) },
6024 { PREFIX_TABLE (PREFIX_0F38DC) },
6025 { PREFIX_TABLE (PREFIX_0F38DD) },
6026 { PREFIX_TABLE (PREFIX_0F38DE) },
6027 { PREFIX_TABLE (PREFIX_0F38DF) },
6028 /* e0 */
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 /* e8 */
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 /* f0 */
6047 { PREFIX_TABLE (PREFIX_0F38F0) },
6048 { PREFIX_TABLE (PREFIX_0F38F1) },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 /* f8 */
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
6064 },
6065 /* THREE_BYTE_0F3A */
6066 {
6067 /* 00 */
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 /* 08 */
6077 { PREFIX_TABLE (PREFIX_0F3A08) },
6078 { PREFIX_TABLE (PREFIX_0F3A09) },
6079 { PREFIX_TABLE (PREFIX_0F3A0A) },
6080 { PREFIX_TABLE (PREFIX_0F3A0B) },
6081 { PREFIX_TABLE (PREFIX_0F3A0C) },
6082 { PREFIX_TABLE (PREFIX_0F3A0D) },
6083 { PREFIX_TABLE (PREFIX_0F3A0E) },
6084 { "palignr", { MX, EM, Ib } },
6085 /* 10 */
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
6090 { PREFIX_TABLE (PREFIX_0F3A14) },
6091 { PREFIX_TABLE (PREFIX_0F3A15) },
6092 { PREFIX_TABLE (PREFIX_0F3A16) },
6093 { PREFIX_TABLE (PREFIX_0F3A17) },
6094 /* 18 */
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6100 { "(bad)", { XX } },
6101 { "(bad)", { XX } },
6102 { "(bad)", { XX } },
6103 /* 20 */
6104 { PREFIX_TABLE (PREFIX_0F3A20) },
6105 { PREFIX_TABLE (PREFIX_0F3A21) },
6106 { PREFIX_TABLE (PREFIX_0F3A22) },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 { "(bad)", { XX } },
6111 { "(bad)", { XX } },
6112 /* 28 */
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 /* 30 */
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 { "(bad)", { XX } },
6130 /* 38 */
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
6139 /* 40 */
6140 { PREFIX_TABLE (PREFIX_0F3A40) },
6141 { PREFIX_TABLE (PREFIX_0F3A41) },
6142 { PREFIX_TABLE (PREFIX_0F3A42) },
6143 { "(bad)", { XX } },
6144 { PREFIX_TABLE (PREFIX_0F3A44) },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 /* 48 */
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6152 { "(bad)", { XX } },
6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 /* 50 */
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
6164 { "(bad)", { XX } },
6165 { "(bad)", { XX } },
6166 /* 58 */
6167 { "(bad)", { XX } },
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 /* 60 */
6176 { PREFIX_TABLE (PREFIX_0F3A60) },
6177 { PREFIX_TABLE (PREFIX_0F3A61) },
6178 { PREFIX_TABLE (PREFIX_0F3A62) },
6179 { PREFIX_TABLE (PREFIX_0F3A63) },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 /* 68 */
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 /* 70 */
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 /* 78 */
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 /* 80 */
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 /* 88 */
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 /* 90 */
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 /* 98 */
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 /* a0 */
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 /* a8 */
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 /* b0 */
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 /* b8 */
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 /* c0 */
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 /* c8 */
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 /* d0 */
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 /* d8 */
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
6318 { PREFIX_TABLE (PREFIX_0F3ADF) },
6319 /* e0 */
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
6328 /* e8 */
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 /* f0 */
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 { "(bad)", { XX } },
6345 { "(bad)", { XX } },
6346 /* f8 */
6347 { "(bad)", { XX } },
6348 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 },
6356
6357 /* THREE_BYTE_0F7A */
6358 {
6359 /* 00 */
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6368 /* 08 */
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
6371 { "(bad)", { XX } },
6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6375 { "(bad)", { XX } },
6376 { "(bad)", { XX } },
6377 /* 10 */
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6384 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
6386 /* 18 */
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 /* 20 */
6396 { "ptest", { XX } },
6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
c0f3af97
L		 6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
f88c9eb0 6404 /* 28 */
c0f3af97
L		 6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
c0f3af97
L		 6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
f88c9eb0 6413 /* 30 */
c0f3af97
L		 6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
4e7d34a6
L		 6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
c0f3af97 6419 { "(bad)", { XX } },
c0f3af97
L		 6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
f88c9eb0 6422 /* 38 */
c0f3af97 6423 { "(bad)", { XX } },
4e7d34a6
L		 6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
4e7d34a6
L		 6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
f88c9eb0 6431 /* 40 */
4e7d34a6 6432 { "(bad)", { XX } },
f88c9eb0
SP		 6433 { "phaddbw", { XM, EXq } },
6434 { "phaddbd", { XM, EXq } },
6435 { "phaddbq", { XM, EXq } },
4e7d34a6
L		 6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
f88c9eb0
SP		 6438 { "phaddwd", { XM, EXq } },
6439 { "phaddwq", { XM, EXq } },
6440 /* 48 */
4e7d34a6
L		 6441 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
4e7d34a6 6443 { "(bad)", { XX } },
f88c9eb0 6444 { "phadddq", { XM, EXq } },
4e7d34a6
L		 6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
f88c9eb0 6449 /* 50 */
4e7d34a6 6450 { "(bad)", { XX } },
f88c9eb0
SP		 6451 { "phaddubw", { XM, EXq } },
6452 { "phaddubd", { XM, EXq } },
6453 { "phaddubq", { XM, EXq } },
4e7d34a6
L		 6454 { "(bad)", { XX } },
6455 { "(bad)", { XX } },
f88c9eb0
SP		 6456 { "phadduwd", { XM, EXq } },
6457 { "phadduwq", { XM, EXq } },
6458 /* 58 */
4e7d34a6
L		 6459 { "(bad)", { XX } },
6460 { "(bad)", { XX } },
6461 { "(bad)", { XX } },
f88c9eb0 6462 { "phaddudq", { XM, EXq } },
4e7d34a6 6463 { "(bad)", { XX } },
c1e679ec
DR		 6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
f88c9eb0 6467 /* 60 */
c1e679ec 6468 { "(bad)", { XX } },
f88c9eb0
SP		 6469 { "phsubbw", { XM, EXq } },
6470 { "phsubbd", { XM, EXq } },
6471 { "phsubbq", { XM, EXq } },
4e7d34a6
L		 6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 /* 68 */
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
85f10a01 6485 /* 70 */
4e7d34a6
L		 6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
85f10a01 6494 /* 78 */
4e7d34a6
L		 6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
85f10a01 6503 /* 80 */
f88c9eb0
SP		 6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
4e7d34a6
L		 6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
c0f3af97
L		 6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
85f10a01 6512 /* 88 */
4e7d34a6
L		 6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
c0f3af97
L		 6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
85f10a01 6521 /* 90 */
4e7d34a6
L		 6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
c0f3af97
L		 6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
85f10a01 6530 /* 98 */
4e7d34a6
L		 6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
c0f3af97
L		 6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
85f10a01 6539 /* a0 */
4e7d34a6
L		 6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
c0f3af97 6546 { "(bad)", { XX } },
4e7d34a6 6547 { "(bad)", { XX } },
85f10a01 6548 /* a8 */
4e7d34a6
L		 6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
85f10a01 6557 /* b0 */
4e7d34a6
L		 6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
c0f3af97 6564 { "(bad)", { XX } },
4e7d34a6 6565 { "(bad)", { XX } },
85f10a01 6566 /* b8 */
4e7d34a6
L		 6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
85f10a01 6575 /* c0 */
4e7d34a6
L		 6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
85f10a01 6584 /* c8 */
4e7d34a6
L		 6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
85f10a01 6593 /* d0 */
4e7d34a6
L		 6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
85f10a01 6602 /* d8 */
4e7d34a6
L		 6603 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
f88c9eb0
SP		 6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
85f10a01 6611 /* e0 */
4e7d34a6
L		 6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
85f10a01 6620 /* e8 */
4e7d34a6
L		 6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
85f10a01 6629 /* f0 */
f88c9eb0
SP		 6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
4e7d34a6
L		 6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
6637 { "(bad)", { XX } },
85f10a01 6638 /* f8 */
4e7d34a6
L		 6639 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
6645 { "(bad)", { XX } },
6646 { "(bad)", { XX } },
85f10a01 6647 },
f88c9eb0
SP		 6648};
6649
6650static const struct dis386 xop_table[][256] = {
5dd85c99 6651 /* XOP_08 */
85f10a01
MM		 6652 {
6653 /* 00 */
4e7d34a6
L		 6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6657 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
85f10a01 6662 /* 08 */
f88c9eb0
SP		 6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 { "(bad)", { XX } },
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
85f10a01 6671 /* 10 */
4e7d34a6
L		 6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
5dd85c99 6674 { "(bad)", { XX } },
f88c9eb0
SP		 6675 { "(bad)", { XX } },
6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
4e7d34a6
L		 6678 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
85f10a01 6680 /* 18 */
4e7d34a6
L		 6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
85f10a01 6689 /* 20 */
f88c9eb0
SP		 6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
4e7d34a6
L		 6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
85f10a01 6698 /* 28 */
4e7d34a6
L		 6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
4e7d34a6
L		 6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
c0f3af97 6707 /* 30 */
c1e679ec
DR		 6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
4e7d34a6 6710 { "(bad)", { XX } },
4e7d34a6
L		 6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6714 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
c0f3af97 6716 /* 38 */
4e7d34a6
L		 6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
4e7d34a6
L		 6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
c0f3af97 6725 /* 40 */
c1e679ec 6726 { "(bad)", { XX } },
f88c9eb0
SP		 6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
4e7d34a6
L		 6731 { "(bad)", { XX } },
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
85f10a01 6734 /* 48 */
4e7d34a6
L		 6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
c1e679ec 6738 { "(bad)", { XX } },
4e7d34a6
L		 6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
c0f3af97 6743 /* 50 */
4e7d34a6
L		 6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
c1e679ec
DR		 6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
85f10a01 6752 /* 58 */
4e7d34a6
L		 6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
4e7d34a6
L		 6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
6759 { "(bad)", { XX } },
4e7d34a6 6760 { "(bad)", { XX } },
c1e679ec 6761 /* 60 */
f88c9eb0
SP		 6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
4e7d34a6
L		 6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
c0f3af97
L		 6770 /* 68 */
6771 { "(bad)", { XX } },
4e7d34a6
L		 6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
4e7d34a6
L		 6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
85f10a01 6779 /* 70 */
4e7d34a6
L		 6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
85f10a01 6788 /* 78 */
4e7d34a6
L		 6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
85f10a01 6797 /* 80 */
4e7d34a6
L		 6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
5dd85c99
SP		 6803 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6804 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6805 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6806 /* 88 */
4e7d34a6
L		 6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
4e7d34a6
L		 6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
5dd85c99
SP		 6813 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6814 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6815 /* 90 */
4e7d34a6
L		 6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
5dd85c99
SP		 6821 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6822 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6823 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6824 /* 98 */
4e7d34a6
L		 6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
5dd85c99
SP		 6831 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6832 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6833 /* a0 */
f0ae4a24
SP		 6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
5dd85c99
SP		 6836 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6837 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6
L		 6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
5dd85c99 6840 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6 6841 { "(bad)", { XX } },
5dd85c99 6842 /* a8 */
4e7d34a6
L		 6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
6849 { "(bad)", { XX } },
4e7d34a6 6850 { "(bad)", { XX } },
5dd85c99 6851 /* b0 */
4e7d34a6
L		 6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
6857 { "(bad)", { XX } },
5dd85c99 6858 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
4e7d34a6 6859 { "(bad)", { XX } },
5dd85c99 6860 /* b8 */
4e7d34a6
L		 6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
5dd85c99
SP		 6869 /* c0 */
6870 { "vprotb", { XM, Vex_2src_1, Ib } },
6871 { "vprotw", { XM, Vex_2src_1, Ib } },
6872 { "vprotd", { XM, Vex_2src_1, Ib } },
6873 { "vprotq", { XM, Vex_2src_1, Ib } },
4e7d34a6
L		 6874 { "(bad)", { XX } },
6875 { "(bad)", { XX } },
6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
5dd85c99 6878 /* c8 */
4e7d34a6
L		 6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
5dd85c99
SP		 6883 { "vpcomb", { XM, Vex128, EXx, Ib } },
6884 { "vpcomw", { XM, Vex128, EXx, Ib } },
6885 { "vpcomd", { XM, Vex128, EXx, Ib } },
6886 { "vpcomq", { XM, Vex128, EXx, Ib } },
6887 /* d0 */
4e7d34a6
L		 6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
5dd85c99 6896 /* d8 */
4e7d34a6
L		 6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 { "(bad)", { XX } },
6903 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
5dd85c99 6905 /* e0 */
4e7d34a6
L		 6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 { "(bad)", { XX } },
6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
5dd85c99 6914 /* e8 */
4e7d34a6
L		 6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
5dd85c99
SP		 6919 { "vpcomub", { XM, Vex128, EXx, Ib } },
6920 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6921 { "vpcomud", { XM, Vex128, EXx, Ib } },
6922 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6923 /* f0 */
4e7d34a6
L		 6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
4e7d34a6
L		 6928 { "(bad)", { XX } },
6929 { "(bad)", { XX } },
6930 { "(bad)", { XX } },
6931 { "(bad)", { XX } },
5dd85c99
SP		 6932 /* f8 */
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
6939 { "(bad)", { XX } },
6940 { "(bad)", { XX } },
6941 },
6942 /* XOP_09 */
6943 {
6944 /* 00 */
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
6948 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 /* 08 */
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
6957 { "(bad)", { XX } },
6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 /* 10 */
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { REG_TABLE (REG_XOP_LWPCB) },
6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6968 { "(bad)", { XX } },
6969 { "(bad)", { XX } },
6970 { "(bad)", { XX } },
6971 /* 18 */
6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
6980 /* 20 */
4e7d34a6
L		 6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
f88c9eb0 6984 { "(bad)", { XX } },
4e7d34a6
L		 6985 { "(bad)", { XX } },
6986 { "(bad)", { XX } },
6987 { "(bad)", { XX } },
6988 { "(bad)", { XX } },
5dd85c99
SP		 6989 /* 28 */
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { "(bad)", { XX } },
6998 /* 30 */
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 /* 38 */
7008 { "(bad)", { XX } },
7009 { "(bad)", { XX } },
7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7013 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
7016 /* 40 */
7017 { "(bad)", { XX } },
7018 { "(bad)", { XX } },
7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7022 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 /* 48 */
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 /* 50 */
7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 /* 58 */
7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 /* 60 */
7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 /* 68 */
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7065 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
7067 { "(bad)", { XX } },
7068 { "(bad)", { XX } },
7069 { "(bad)", { XX } },
7070 /* 70 */
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
7073 { "(bad)", { XX } },
7074 { "(bad)", { XX } },
7075 { "(bad)", { XX } },
7076 { "(bad)", { XX } },
7077 { "(bad)", { XX } },
7078 { "(bad)", { XX } },
7079 /* 78 */
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7085 { "(bad)", { XX } },
7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 /* 80 */
7089 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
7090 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
7091 { "vfrczss", { XM, EXd } },
7092 { "vfrczsd", { XM, EXq } },
7093 { "(bad)", { XX } },
7094 { "(bad)", { XX } },
7095 { "(bad)", { XX } },
7096 { "(bad)", { XX } },
7097 /* 88 */
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7103 { "(bad)", { XX } },
7104 { "(bad)", { XX } },
7105 { "(bad)", { XX } },
7106 /* 90 */
7107 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7108 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7109 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7110 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7111 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7112 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7113 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7114 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7115 /* 98 */
7116 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7117 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7118 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7119 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7120 { "(bad)", { XX } },
7121 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
7124 /* a0 */
7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 /* a8 */
7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
7142 /* b0 */
7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 /* b8 */
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
7160 /* c0 */
7161 { "(bad)", { XX } },
7162 { "vphaddbw", { XM, EXxmm } },
7163 { "vphaddbd", { XM, EXxmm } },
7164 { "vphaddbq", { XM, EXxmm } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
7167 { "vphaddwd", { XM, EXxmm } },
7168 { "vphaddwq", { XM, EXxmm } },
7169 /* c8 */
7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "vphadddq", { XM, EXxmm } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 /* d0 */
7179 { "(bad)", { XX } },
7180 { "vphaddubw", { XM, EXxmm } },
7181 { "vphaddubd", { XM, EXxmm } },
7182 { "vphaddubq", { XM, EXxmm } },
7183 { "(bad)", { XX } },
7184 { "(bad)", { XX } },
7185 { "vphadduwd", { XM, EXxmm } },
7186 { "vphadduwq", { XM, EXxmm } },
7187 /* d8 */
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7191 { "vphaddudq", { XM, EXxmm } },
7192 { "(bad)", { XX } },
7193 { "(bad)", { XX } },
7194 { "(bad)", { XX } },
7195 { "(bad)", { XX } },
7196 /* e0 */
7197 { "(bad)", { XX } },
7198 { "vphsubbw", { XM, EXxmm } },
7199 { "vphsubwd", { XM, EXxmm } },
7200 { "vphsubdq", { XM, EXxmm } },
4e7d34a6
L		 7201 { "(bad)", { XX } },
7202 { "(bad)", { XX } },
7203 { "(bad)", { XX } },
7204 { "(bad)", { XX } },
7205 /* e8 */
7206 { "(bad)", { XX } },
7207 { "(bad)", { XX } },
7208 { "(bad)", { XX } },
7209 { "(bad)", { XX } },
7210 { "(bad)", { XX } },
7211 { "(bad)", { XX } },
7212 { "(bad)", { XX } },
7213 { "(bad)", { XX } },
7214 /* f0 */
7215 { "(bad)", { XX } },
7216 { "(bad)", { XX } },
7217 { "(bad)", { XX } },
7218 { "(bad)", { XX } },
7219 { "(bad)", { XX } },
7220 { "(bad)", { XX } },
7221 { "(bad)", { XX } },
7222 { "(bad)", { XX } },
7223 /* f8 */
7224 { "(bad)", { XX } },
7225 { "(bad)", { XX } },
7226 { "(bad)", { XX } },
7227 { "(bad)", { XX } },
7228 { "(bad)", { XX } },
7229 { "(bad)", { XX } },
7230 { "(bad)", { XX } },
7231 { "(bad)", { XX } },
7232 },
f88c9eb0 7233 /* XOP_0A */
4e7d34a6
L		 7234 {
7235 /* 00 */
c0f3af97
L		 7236 { "(bad)", { XX } },
7237 { "(bad)", { XX } },
7238 { "(bad)", { XX } },
7239 { "(bad)", { XX } },
7240 { "(bad)", { XX } },
7241 { "(bad)", { XX } },
7242 { "(bad)", { XX } },
7243 { "(bad)", { XX } },
4e7d34a6 7244 /* 08 */
c0f3af97
L		 7245 { "(bad)", { XX } },
7246 { "(bad)", { XX } },
7247 { "(bad)", { XX } },
7248 { "(bad)", { XX } },
d5d7db8e
L		 7249 { "(bad)", { XX } },
7250 { "(bad)", { XX } },
7251 { "(bad)", { XX } },
7252 { "(bad)", { XX } },
4e7d34a6 7253 /* 10 */
d5d7db8e
L		 7254 { "(bad)", { XX } },
7255 { "(bad)", { XX } },
f88c9eb0 7256 { REG_TABLE (REG_XOP_LWP) },
d5d7db8e 7257 { "(bad)", { XX } },
c0f3af97
L		 7258 { "(bad)", { XX } },
7259 { "(bad)", { XX } },
7260 { "(bad)", { XX } },
7261 { "(bad)", { XX } },
4e7d34a6 7262 /* 18 */
d5d7db8e
L		 7263 { "(bad)", { XX } },
7264 { "(bad)", { XX } },
7265 { "(bad)", { XX } },
7266 { "(bad)", { XX } },
c0f3af97
L		 7267 { "(bad)", { XX } },
7268 { "(bad)", { XX } },
7269 { "(bad)", { XX } },
d5d7db8e 7270 { "(bad)", { XX } },
4e7d34a6 7271 /* 20 */
f88c9eb0 7272 { "(bad)", { XX } },
c0f3af97
L		 7273 { "(bad)", { XX } },
7274 { "(bad)", { XX } },
7275 { "(bad)", { XX } },
7276 { "(bad)", { XX } },
7277 { "(bad)", { XX } },
d5d7db8e
L		 7278 { "(bad)", { XX } },
7279 { "(bad)", { XX } },
4e7d34a6 7280 /* 28 */
c0f3af97
L		 7281 { "(bad)", { XX } },
7282 { "(bad)", { XX } },
7283 { "(bad)", { XX } },
7284 { "(bad)", { XX } },
d5d7db8e
L		 7285 { "(bad)", { XX } },
7286 { "(bad)", { XX } },
7287 { "(bad)", { XX } },
7288 { "(bad)", { XX } },
4e7d34a6 7289 /* 30 */
d5d7db8e 7290 { "(bad)", { XX } },
d5d7db8e
L		 7291 { "(bad)", { XX } },
7292 { "(bad)", { XX } },
7293 { "(bad)", { XX } },
7294 { "(bad)", { XX } },
7295 { "(bad)", { XX } },
7296 { "(bad)", { XX } },
c0f3af97
L		 7297 { "(bad)", { XX } },
7298 /* 38 */
7299 { "(bad)", { XX } },
7300 { "(bad)", { XX } },
7301 { "(bad)", { XX } },
7302 { "(bad)", { XX } },
d5d7db8e
L		 7303 { "(bad)", { XX } },
7304 { "(bad)", { XX } },
7305 { "(bad)", { XX } },
7306 { "(bad)", { XX } },
c0f3af97 7307 /* 40 */
c1e679ec 7308 { "(bad)", { XX } },
d5d7db8e
L		 7309 { "(bad)", { XX } },
7310 { "(bad)", { XX } },
f88c9eb0
SP		 7311 { "(bad)", { XX } },
7312 { "(bad)", { XX } },
7313 { "(bad)", { XX } },
7314 { "(bad)", { XX } },
7315 { "(bad)", { XX } },
c1e679ec 7316 /* 48 */
d5d7db8e
L		 7317 { "(bad)", { XX } },
7318 { "(bad)", { XX } },
d5d7db8e 7319 { "(bad)", { XX } },
f88c9eb0 7320 { "(bad)", { XX } },
d5d7db8e
L		 7321 { "(bad)", { XX } },
7322 { "(bad)", { XX } },
7323 { "(bad)", { XX } },
7324 { "(bad)", { XX } },
c1e679ec 7325 /* 50 */
d5d7db8e
L		 7326 { "(bad)", { XX } },
7327 { "(bad)", { XX } },
7328 { "(bad)", { XX } },
f88c9eb0
SP		 7329 { "(bad)", { XX } },
7330 { "(bad)", { XX } },
7331 { "(bad)", { XX } },
7332 { "(bad)", { XX } },
7333 { "(bad)", { XX } },
4e7d34a6 7334 /* 58 */
d5d7db8e
L		 7335 { "(bad)", { XX } },
7336 { "(bad)", { XX } },
7337 { "(bad)", { XX } },
f88c9eb0 7338 { "(bad)", { XX } },
d5d7db8e
L		 7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
4e7d34a6 7343 /* 60 */
d5d7db8e 7344 { "(bad)", { XX } },
f88c9eb0
SP		 7345 { "(bad)", { XX } },
7346 { "(bad)", { XX } },
7347 { "(bad)", { XX } },
d5d7db8e
L		 7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
4e7d34a6 7352 /* 68 */
d5d7db8e
L		 7353 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
7356 { "(bad)", { XX } },
7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
4e7d34a6 7361 /* 70 */
d5d7db8e
L		 7362 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
7365 { "(bad)", { XX } },
7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
4e7d34a6 7370 /* 78 */
d5d7db8e
L		 7371 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
7373 { "(bad)", { XX } },
7374 { "(bad)", { XX } },
7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
4e7d34a6 7379 /* 80 */
d5d7db8e
L		 7380 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
4e7d34a6 7388 /* 88 */
d5d7db8e
L		 7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
4e7d34a6 7397 /* 90 */
d5d7db8e
L		 7398 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
4e7d34a6 7406 /* 98 */
d5d7db8e
L		 7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
4e7d34a6 7415 /* a0 */
d5d7db8e
L		 7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
4e7d34a6 7424 /* a8 */
d5d7db8e
L		 7425 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
7432 { "(bad)", { XX } },
7433 /* b0 */
7434 { "(bad)", { XX } },
7435 { "(bad)", { XX } },
7436 { "(bad)", { XX } },
7437 { "(bad)", { XX } },
7438 { "(bad)", { XX } },
7439 { "(bad)", { XX } },
7440 { "(bad)", { XX } },
7441 { "(bad)", { XX } },
85f10a01 7442 /* b8 */
d5d7db8e
L		 7443 { "(bad)", { XX } },
7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
7449 { "(bad)", { XX } },
7450 { "(bad)", { XX } },
85f10a01 7451 /* c0 */
d5d7db8e
L		 7452 { "(bad)", { XX } },
7453 { "(bad)", { XX } },
7454 { "(bad)", { XX } },
7455 { "(bad)", { XX } },
7456 { "(bad)", { XX } },
7457 { "(bad)", { XX } },
7458 { "(bad)", { XX } },
7459 { "(bad)", { XX } },
85f10a01 7460 /* c8 */
d5d7db8e
L		 7461 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
7467 { "(bad)", { XX } },
7468 { "(bad)", { XX } },
85f10a01 7469 /* d0 */
d5d7db8e
L		 7470 { "(bad)", { XX } },
7471 { "(bad)", { XX } },
7472 { "(bad)", { XX } },
7473 { "(bad)", { XX } },
7474 { "(bad)", { XX } },
7475 { "(bad)", { XX } },
7476 { "(bad)", { XX } },
7477 { "(bad)", { XX } },
85f10a01 7478 /* d8 */
d5d7db8e
L		 7479 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
7483 { "(bad)", { XX } },
7484 { "(bad)", { XX } },
7485 { "(bad)", { XX } },
7486 { "(bad)", { XX } },
85f10a01 7487 /* e0 */
d5d7db8e
L		 7488 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
7493 { "(bad)", { XX } },
7494 { "(bad)", { XX } },
7495 { "(bad)", { XX } },
85f10a01 7496 /* e8 */
d5d7db8e
L		 7497 { "(bad)", { XX } },
7498 { "(bad)", { XX } },
7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 { "(bad)", { XX } },
7503 { "(bad)", { XX } },
7504 { "(bad)", { XX } },
85f10a01 7505 /* f0 */
c0f3af97
L		 7506 { "(bad)", { XX } },
7507 { "(bad)", { XX } },
d5d7db8e
L		 7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 { "(bad)", { XX } },
7512 { "(bad)", { XX } },
7513 { "(bad)", { XX } },
85f10a01 7514 /* f8 */
d5d7db8e
L		 7515 { "(bad)", { XX } },
7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 { "(bad)", { XX } },
7521 { "(bad)", { XX } },
7522 { "(bad)", { XX } },
85f10a01 7523 },
c0f3af97
L		 7524};
7525
7526static const struct dis386 vex_table[][256] = {
7527 /* VEX_0F */
85f10a01
MM		 7528 {
7529 /* 00 */
d5d7db8e
L		 7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 { "(bad)", { XX } },
7533 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
85f10a01 7538 /* 08 */
d5d7db8e
L		 7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
7541 { "(bad)", { XX } },
7542 { "(bad)", { XX } },
d5d7db8e
L		 7543 { "(bad)", { XX } },
7544 { "(bad)", { XX } },
7545 { "(bad)", { XX } },
7546 { "(bad)", { XX } },
c0f3af97
L		 7547 /* 10 */
7548 { PREFIX_TABLE (PREFIX_VEX_10) },
7549 { PREFIX_TABLE (PREFIX_VEX_11) },
7550 { PREFIX_TABLE (PREFIX_VEX_12) },
7551 { MOD_TABLE (MOD_VEX_13) },
9e30b8e0
L		 7552 { VEX_W_TABLE (VEX_W_14) },
7553 { VEX_W_TABLE (VEX_W_15) },
c0f3af97
L		 7554 { PREFIX_TABLE (PREFIX_VEX_16) },
7555 { MOD_TABLE (MOD_VEX_17) },
7556 /* 18 */
d5d7db8e
L		 7557 { "(bad)", { XX } },
7558 { "(bad)", { XX } },
7559 { "(bad)", { XX } },
d5d7db8e
L		 7560 { "(bad)", { XX } },
7561 { "(bad)", { XX } },
7562 { "(bad)", { XX } },
7563 { "(bad)", { XX } },
7564 { "(bad)", { XX } },
c0f3af97 7565 /* 20 */
d5d7db8e
L		 7566 { "(bad)", { XX } },
7567 { "(bad)", { XX } },
7568 { "(bad)", { XX } },
7569 { "(bad)", { XX } },
7570 { "(bad)", { XX } },
7571 { "(bad)", { XX } },
7572 { "(bad)", { XX } },
7573 { "(bad)", { XX } },
c0f3af97 7574 /* 28 */
9e30b8e0
L		 7575 { VEX_W_TABLE (VEX_W_28) },
7576 { VEX_W_TABLE (VEX_W_29) },
c0f3af97
L		 7577 { PREFIX_TABLE (PREFIX_VEX_2A) },
7578 { MOD_TABLE (MOD_VEX_2B) },
7579 { PREFIX_TABLE (PREFIX_VEX_2C) },
7580 { PREFIX_TABLE (PREFIX_VEX_2D) },
7581 { PREFIX_TABLE (PREFIX_VEX_2E) },
7582 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 7583 /* 30 */
d5d7db8e
L		 7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
7590 { "(bad)", { XX } },
7591 { "(bad)", { XX } },
4e7d34a6 7592 /* 38 */
d5d7db8e
L		 7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
7598 { "(bad)", { XX } },
7599 { "(bad)", { XX } },
7600 { "(bad)", { XX } },
7601 /* 40 */
c0f3af97
L		 7602 { "(bad)", { XX } },
7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
d5d7db8e
L		 7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
7608 { "(bad)", { XX } },
7609 { "(bad)", { XX } },
85f10a01 7610 /* 48 */
85f10a01
MM		 7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
7617 { "(bad)", { XX } },
7618 { "(bad)", { XX } },
d5d7db8e 7619 /* 50 */
976f1fde 7620 { MOD_TABLE (MOD_VEX_50) },
c0f3af97
L		 7621 { PREFIX_TABLE (PREFIX_VEX_51) },
7622 { PREFIX_TABLE (PREFIX_VEX_52) },
7623 { PREFIX_TABLE (PREFIX_VEX_53) },
7624 { "vandpX", { XM, Vex, EXx } },
7625 { "vandnpX", { XM, Vex, EXx } },
7626 { "vorpX", { XM, Vex, EXx } },
7627 { "vxorpX", { XM, Vex, EXx } },
7628 /* 58 */
7629 { PREFIX_TABLE (PREFIX_VEX_58) },
7630 { PREFIX_TABLE (PREFIX_VEX_59) },
7631 { PREFIX_TABLE (PREFIX_VEX_5A) },
7632 { PREFIX_TABLE (PREFIX_VEX_5B) },
7633 { PREFIX_TABLE (PREFIX_VEX_5C) },
7634 { PREFIX_TABLE (PREFIX_VEX_5D) },
7635 { PREFIX_TABLE (PREFIX_VEX_5E) },
7636 { PREFIX_TABLE (PREFIX_VEX_5F) },
7637 /* 60 */
7638 { PREFIX_TABLE (PREFIX_VEX_60) },
7639 { PREFIX_TABLE (PREFIX_VEX_61) },
7640 { PREFIX_TABLE (PREFIX_VEX_62) },
7641 { PREFIX_TABLE (PREFIX_VEX_63) },
7642 { PREFIX_TABLE (PREFIX_VEX_64) },
7643 { PREFIX_TABLE (PREFIX_VEX_65) },
7644 { PREFIX_TABLE (PREFIX_VEX_66) },
7645 { PREFIX_TABLE (PREFIX_VEX_67) },
7646 /* 68 */
7647 { PREFIX_TABLE (PREFIX_VEX_68) },
7648 { PREFIX_TABLE (PREFIX_VEX_69) },
7649 { PREFIX_TABLE (PREFIX_VEX_6A) },
7650 { PREFIX_TABLE (PREFIX_VEX_6B) },
7651 { PREFIX_TABLE (PREFIX_VEX_6C) },
7652 { PREFIX_TABLE (PREFIX_VEX_6D) },
7653 { PREFIX_TABLE (PREFIX_VEX_6E) },
7654 { PREFIX_TABLE (PREFIX_VEX_6F) },
7655 /* 70 */
7656 { PREFIX_TABLE (PREFIX_VEX_70) },
7657 { REG_TABLE (REG_VEX_71) },
7658 { REG_TABLE (REG_VEX_72) },
7659 { REG_TABLE (REG_VEX_73) },
7660 { PREFIX_TABLE (PREFIX_VEX_74) },
7661 { PREFIX_TABLE (PREFIX_VEX_75) },
7662 { PREFIX_TABLE (PREFIX_VEX_76) },
7663 { PREFIX_TABLE (PREFIX_VEX_77) },
7664 /* 78 */
85f10a01
MM		 7665 { "(bad)", { XX } },
7666 { "(bad)", { XX } },
7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
c0f3af97
L		 7669 { PREFIX_TABLE (PREFIX_VEX_7C) },
7670 { PREFIX_TABLE (PREFIX_VEX_7D) },
7671 { PREFIX_TABLE (PREFIX_VEX_7E) },
7672 { PREFIX_TABLE (PREFIX_VEX_7F) },
7673 /* 80 */
85f10a01
MM		 7674 { "(bad)", { XX } },
7675 { "(bad)", { XX } },
7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
85f10a01
MM		 7678 { "(bad)", { XX } },
7679 { "(bad)", { XX } },
7680 { "(bad)", { XX } },
7681 { "(bad)", { XX } },
c0f3af97 7682 /* 88 */
85f10a01
MM		 7683 { "(bad)", { XX } },
7684 { "(bad)", { XX } },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
7688 { "(bad)", { XX } },
7689 { "(bad)", { XX } },
7690 { "(bad)", { XX } },
c0f3af97 7691 /* 90 */
85f10a01
MM		 7692 { "(bad)", { XX } },
7693 { "(bad)", { XX } },
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
7697 { "(bad)", { XX } },
7698 { "(bad)", { XX } },
85f10a01 7699 { "(bad)", { XX } },
c0f3af97 7700 /* 98 */
85f10a01
MM		 7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
d5d7db8e
L		 7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
7707 { "(bad)", { XX } },
7708 { "(bad)", { XX } },
c0f3af97 7709 /* a0 */
d5d7db8e
L		 7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
7716 { "(bad)", { XX } },
7717 { "(bad)", { XX } },
c0f3af97 7718 /* a8 */
d5d7db8e
L		 7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 { "(bad)", { XX } },
c0f3af97 7725 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 7726 { "(bad)", { XX } },
c0f3af97 7727 /* b0 */
d5d7db8e 7728 { "(bad)", { XX } },
d5d7db8e
L		 7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 { "(bad)", { XX } },
7734 { "(bad)", { XX } },
7735 { "(bad)", { XX } },
c0f3af97 7736 /* b8 */
d5d7db8e 7737 { "(bad)", { XX } },
d5d7db8e
L		 7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 { "(bad)", { XX } },
7743 { "(bad)", { XX } },
7744 { "(bad)", { XX } },
c0f3af97 7745 /* c0 */
d5d7db8e 7746 { "(bad)", { XX } },
d5d7db8e 7747 { "(bad)", { XX } },
c0f3af97 7748 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 7749 { "(bad)", { XX } },
c0f3af97
L		 7750 { PREFIX_TABLE (PREFIX_VEX_C4) },
7751 { PREFIX_TABLE (PREFIX_VEX_C5) },
7752 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 7753 { "(bad)", { XX } },
c0f3af97 7754 /* c8 */
d5d7db8e
L		 7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
d5d7db8e
L		 7760 { "(bad)", { XX } },
7761 { "(bad)", { XX } },
7762 { "(bad)", { XX } },
c0f3af97
L		 7763 /* d0 */
7764 { PREFIX_TABLE (PREFIX_VEX_D0) },
7765 { PREFIX_TABLE (PREFIX_VEX_D1) },
7766 { PREFIX_TABLE (PREFIX_VEX_D2) },
7767 { PREFIX_TABLE (PREFIX_VEX_D3) },
7768 { PREFIX_TABLE (PREFIX_VEX_D4) },
7769 { PREFIX_TABLE (PREFIX_VEX_D5) },
7770 { PREFIX_TABLE (PREFIX_VEX_D6) },
7771 { PREFIX_TABLE (PREFIX_VEX_D7) },
7772 /* d8 */
7773 { PREFIX_TABLE (PREFIX_VEX_D8) },
7774 { PREFIX_TABLE (PREFIX_VEX_D9) },
7775 { PREFIX_TABLE (PREFIX_VEX_DA) },
7776 { PREFIX_TABLE (PREFIX_VEX_DB) },
7777 { PREFIX_TABLE (PREFIX_VEX_DC) },
7778 { PREFIX_TABLE (PREFIX_VEX_DD) },
7779 { PREFIX_TABLE (PREFIX_VEX_DE) },
7780 { PREFIX_TABLE (PREFIX_VEX_DF) },
7781 /* e0 */
7782 { PREFIX_TABLE (PREFIX_VEX_E0) },
7783 { PREFIX_TABLE (PREFIX_VEX_E1) },
7784 { PREFIX_TABLE (PREFIX_VEX_E2) },
7785 { PREFIX_TABLE (PREFIX_VEX_E3) },
7786 { PREFIX_TABLE (PREFIX_VEX_E4) },
7787 { PREFIX_TABLE (PREFIX_VEX_E5) },
7788 { PREFIX_TABLE (PREFIX_VEX_E6) },
7789 { PREFIX_TABLE (PREFIX_VEX_E7) },
7790 /* e8 */
7791 { PREFIX_TABLE (PREFIX_VEX_E8) },
7792 { PREFIX_TABLE (PREFIX_VEX_E9) },
7793 { PREFIX_TABLE (PREFIX_VEX_EA) },
7794 { PREFIX_TABLE (PREFIX_VEX_EB) },
7795 { PREFIX_TABLE (PREFIX_VEX_EC) },
7796 { PREFIX_TABLE (PREFIX_VEX_ED) },
7797 { PREFIX_TABLE (PREFIX_VEX_EE) },
7798 { PREFIX_TABLE (PREFIX_VEX_EF) },
7799 /* f0 */
7800 { PREFIX_TABLE (PREFIX_VEX_F0) },
7801 { PREFIX_TABLE (PREFIX_VEX_F1) },
7802 { PREFIX_TABLE (PREFIX_VEX_F2) },
7803 { PREFIX_TABLE (PREFIX_VEX_F3) },
7804 { PREFIX_TABLE (PREFIX_VEX_F4) },
7805 { PREFIX_TABLE (PREFIX_VEX_F5) },
7806 { PREFIX_TABLE (PREFIX_VEX_F6) },
7807 { PREFIX_TABLE (PREFIX_VEX_F7) },
7808 /* f8 */
7809 { PREFIX_TABLE (PREFIX_VEX_F8) },
7810 { PREFIX_TABLE (PREFIX_VEX_F9) },
7811 { PREFIX_TABLE (PREFIX_VEX_FA) },
7812 { PREFIX_TABLE (PREFIX_VEX_FB) },
7813 { PREFIX_TABLE (PREFIX_VEX_FC) },
7814 { PREFIX_TABLE (PREFIX_VEX_FD) },
7815 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 7816 { "(bad)", { XX } },
c0f3af97
L		 7817 },
7818 /* VEX_0F38 */
7819 {
7820 /* 00 */
7821 { PREFIX_TABLE (PREFIX_VEX_3800) },
7822 { PREFIX_TABLE (PREFIX_VEX_3801) },
7823 { PREFIX_TABLE (PREFIX_VEX_3802) },
7824 { PREFIX_TABLE (PREFIX_VEX_3803) },
7825 { PREFIX_TABLE (PREFIX_VEX_3804) },
7826 { PREFIX_TABLE (PREFIX_VEX_3805) },
7827 { PREFIX_TABLE (PREFIX_VEX_3806) },
7828 { PREFIX_TABLE (PREFIX_VEX_3807) },
7829 /* 08 */
7830 { PREFIX_TABLE (PREFIX_VEX_3808) },
7831 { PREFIX_TABLE (PREFIX_VEX_3809) },
7832 { PREFIX_TABLE (PREFIX_VEX_380A) },
7833 { PREFIX_TABLE (PREFIX_VEX_380B) },
7834 { PREFIX_TABLE (PREFIX_VEX_380C) },
7835 { PREFIX_TABLE (PREFIX_VEX_380D) },
7836 { PREFIX_TABLE (PREFIX_VEX_380E) },
7837 { PREFIX_TABLE (PREFIX_VEX_380F) },
7838 /* 10 */
d5d7db8e
L		 7839 { "(bad)", { XX } },
7840 { "(bad)", { XX } },
7841 { "(bad)", { XX } },
7842 { "(bad)", { XX } },
d5d7db8e
L		 7843 { "(bad)", { XX } },
7844 { "(bad)", { XX } },
7845 { "(bad)", { XX } },
c0f3af97
L		 7846 { PREFIX_TABLE (PREFIX_VEX_3817) },
7847 /* 18 */
7848 { PREFIX_TABLE (PREFIX_VEX_3818) },
7849 { PREFIX_TABLE (PREFIX_VEX_3819) },
7850 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 7851 { "(bad)", { XX } },
c0f3af97
L		 7852 { PREFIX_TABLE (PREFIX_VEX_381C) },
7853 { PREFIX_TABLE (PREFIX_VEX_381D) },
7854 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 7855 { "(bad)", { XX } },
c0f3af97
L		 7856 /* 20 */
7857 { PREFIX_TABLE (PREFIX_VEX_3820) },
7858 { PREFIX_TABLE (PREFIX_VEX_3821) },
7859 { PREFIX_TABLE (PREFIX_VEX_3822) },
7860 { PREFIX_TABLE (PREFIX_VEX_3823) },
7861 { PREFIX_TABLE (PREFIX_VEX_3824) },
7862 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 7863 { "(bad)", { XX } },
7864 { "(bad)", { XX } },
c0f3af97
L		 7865 /* 28 */
7866 { PREFIX_TABLE (PREFIX_VEX_3828) },
7867 { PREFIX_TABLE (PREFIX_VEX_3829) },
7868 { PREFIX_TABLE (PREFIX_VEX_382A) },
7869 { PREFIX_TABLE (PREFIX_VEX_382B) },
7870 { PREFIX_TABLE (PREFIX_VEX_382C) },
7871 { PREFIX_TABLE (PREFIX_VEX_382D) },
7872 { PREFIX_TABLE (PREFIX_VEX_382E) },
7873 { PREFIX_TABLE (PREFIX_VEX_382F) },
7874 /* 30 */
7875 { PREFIX_TABLE (PREFIX_VEX_3830) },
7876 { PREFIX_TABLE (PREFIX_VEX_3831) },
7877 { PREFIX_TABLE (PREFIX_VEX_3832) },
7878 { PREFIX_TABLE (PREFIX_VEX_3833) },
7879 { PREFIX_TABLE (PREFIX_VEX_3834) },
7880 { PREFIX_TABLE (PREFIX_VEX_3835) },
7881 { "(bad)", { XX } },
7882 { PREFIX_TABLE (PREFIX_VEX_3837) },
7883 /* 38 */
7884 { PREFIX_TABLE (PREFIX_VEX_3838) },
7885 { PREFIX_TABLE (PREFIX_VEX_3839) },
7886 { PREFIX_TABLE (PREFIX_VEX_383A) },
7887 { PREFIX_TABLE (PREFIX_VEX_383B) },
7888 { PREFIX_TABLE (PREFIX_VEX_383C) },
7889 { PREFIX_TABLE (PREFIX_VEX_383D) },
7890 { PREFIX_TABLE (PREFIX_VEX_383E) },
7891 { PREFIX_TABLE (PREFIX_VEX_383F) },
7892 /* 40 */
7893 { PREFIX_TABLE (PREFIX_VEX_3840) },
7894 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 7895 { "(bad)", { XX } },
d5d7db8e
L		 7896 { "(bad)", { XX } },
7897 { "(bad)", { XX } },
7898 { "(bad)", { XX } },
7899 { "(bad)", { XX } },
7900 { "(bad)", { XX } },
c0f3af97 7901 /* 48 */
d5d7db8e
L		 7902 { "(bad)", { XX } },
7903 { "(bad)", { XX } },
7904 { "(bad)", { XX } },
d5d7db8e
L		 7905 { "(bad)", { XX } },
7906 { "(bad)", { XX } },
7907 { "(bad)", { XX } },
7908 { "(bad)", { XX } },
7909 { "(bad)", { XX } },
c0f3af97 7910 /* 50 */
d5d7db8e
L		 7911 { "(bad)", { XX } },
7912 { "(bad)", { XX } },
7913 { "(bad)", { XX } },
d5d7db8e
L		 7914 { "(bad)", { XX } },
7915 { "(bad)", { XX } },
7916 { "(bad)", { XX } },
7917 { "(bad)", { XX } },
7918 { "(bad)", { XX } },
c0f3af97 7919 /* 58 */
d5d7db8e
L		 7920 { "(bad)", { XX } },
7921 { "(bad)", { XX } },
7922 { "(bad)", { XX } },
d5d7db8e
L		 7923 { "(bad)", { XX } },
7924 { "(bad)", { XX } },
7925 { "(bad)", { XX } },
7926 { "(bad)", { XX } },
7927 { "(bad)", { XX } },
c0f3af97 7928 /* 60 */
d5d7db8e
L		 7929 { "(bad)", { XX } },
7930 { "(bad)", { XX } },
7931 { "(bad)", { XX } },
d5d7db8e
L		 7932 { "(bad)", { XX } },
7933 { "(bad)", { XX } },
7934 { "(bad)", { XX } },
7935 { "(bad)", { XX } },
7936 { "(bad)", { XX } },
c0f3af97 7937 /* 68 */
d5d7db8e
L		 7938 { "(bad)", { XX } },
7939 { "(bad)", { XX } },
7940 { "(bad)", { XX } },
d5d7db8e
L		 7941 { "(bad)", { XX } },
7942 { "(bad)", { XX } },
7943 { "(bad)", { XX } },
7944 { "(bad)", { XX } },
7945 { "(bad)", { XX } },
c0f3af97 7946 /* 70 */
d5d7db8e
L		 7947 { "(bad)", { XX } },
7948 { "(bad)", { XX } },
7949 { "(bad)", { XX } },
d5d7db8e
L		 7950 { "(bad)", { XX } },
7951 { "(bad)", { XX } },
7952 { "(bad)", { XX } },
7953 { "(bad)", { XX } },
7954 { "(bad)", { XX } },
c0f3af97 7955 /* 78 */
d5d7db8e
L		 7956 { "(bad)", { XX } },
7957 { "(bad)", { XX } },
7958 { "(bad)", { XX } },
d5d7db8e
L		 7959 { "(bad)", { XX } },
7960 { "(bad)", { XX } },
7961 { "(bad)", { XX } },
7962 { "(bad)", { XX } },
7963 { "(bad)", { XX } },
c0f3af97 7964 /* 80 */
d5d7db8e
L		 7965 { "(bad)", { XX } },
7966 { "(bad)", { XX } },
7967 { "(bad)", { XX } },
d5d7db8e
L		 7968 { "(bad)", { XX } },
7969 { "(bad)", { XX } },
7970 { "(bad)", { XX } },
7971 { "(bad)", { XX } },
7972 { "(bad)", { XX } },
c0f3af97 7973 /* 88 */
d5d7db8e
L		 7974 { "(bad)", { XX } },
7975 { "(bad)", { XX } },
7976 { "(bad)", { XX } },
d5d7db8e
L		 7977 { "(bad)", { XX } },
7978 { "(bad)", { XX } },
7979 { "(bad)", { XX } },
7980 { "(bad)", { XX } },
7981 { "(bad)", { XX } },
c0f3af97 7982 /* 90 */
d5d7db8e
L		 7983 { "(bad)", { XX } },
7984 { "(bad)", { XX } },
7985 { "(bad)", { XX } },
d5d7db8e
L		 7986 { "(bad)", { XX } },
7987 { "(bad)", { XX } },
7988 { "(bad)", { XX } },
0bfee649
L		 7989 { PREFIX_TABLE (PREFIX_VEX_3896) },
7990 { PREFIX_TABLE (PREFIX_VEX_3897) },
c0f3af97 7991 /* 98 */
0bfee649
L		 7992 { PREFIX_TABLE (PREFIX_VEX_3898) },
7993 { PREFIX_TABLE (PREFIX_VEX_3899) },
7994 { PREFIX_TABLE (PREFIX_VEX_389A) },
7995 { PREFIX_TABLE (PREFIX_VEX_389B) },
7996 { PREFIX_TABLE (PREFIX_VEX_389C) },
7997 { PREFIX_TABLE (PREFIX_VEX_389D) },
7998 { PREFIX_TABLE (PREFIX_VEX_389E) },
7999 { PREFIX_TABLE (PREFIX_VEX_389F) },
c0f3af97 8000 /* a0 */
d5d7db8e
L		 8001 { "(bad)", { XX } },
8002 { "(bad)", { XX } },
8003 { "(bad)", { XX } },
d5d7db8e
L		 8004 { "(bad)", { XX } },
8005 { "(bad)", { XX } },
8006 { "(bad)", { XX } },
0bfee649
L		 8007 { PREFIX_TABLE (PREFIX_VEX_38A6) },
8008 { PREFIX_TABLE (PREFIX_VEX_38A7) },
c0f3af97 8009 /* a8 */
0bfee649
L		 8010 { PREFIX_TABLE (PREFIX_VEX_38A8) },
8011 { PREFIX_TABLE (PREFIX_VEX_38A9) },
8012 { PREFIX_TABLE (PREFIX_VEX_38AA) },
8013 { PREFIX_TABLE (PREFIX_VEX_38AB) },
8014 { PREFIX_TABLE (PREFIX_VEX_38AC) },
8015 { PREFIX_TABLE (PREFIX_VEX_38AD) },
8016 { PREFIX_TABLE (PREFIX_VEX_38AE) },
8017 { PREFIX_TABLE (PREFIX_VEX_38AF) },
c0f3af97 8018 /* b0 */
d5d7db8e
L		 8019 { "(bad)", { XX } },
8020 { "(bad)", { XX } },
8021 { "(bad)", { XX } },
8022 { "(bad)", { XX } },
8023 { "(bad)", { XX } },
8024 { "(bad)", { XX } },
0bfee649
L		 8025 { PREFIX_TABLE (PREFIX_VEX_38B6) },
8026 { PREFIX_TABLE (PREFIX_VEX_38B7) },
c0f3af97 8027 /* b8 */
0bfee649
L		 8028 { PREFIX_TABLE (PREFIX_VEX_38B8) },
8029 { PREFIX_TABLE (PREFIX_VEX_38B9) },
8030 { PREFIX_TABLE (PREFIX_VEX_38BA) },
8031 { PREFIX_TABLE (PREFIX_VEX_38BB) },
8032 { PREFIX_TABLE (PREFIX_VEX_38BC) },
8033 { PREFIX_TABLE (PREFIX_VEX_38BD) },
8034 { PREFIX_TABLE (PREFIX_VEX_38BE) },
8035 { PREFIX_TABLE (PREFIX_VEX_38BF) },
c0f3af97 8036 /* c0 */
d5d7db8e
L		 8037 { "(bad)", { XX } },
8038 { "(bad)", { XX } },
8039 { "(bad)", { XX } },
8040 { "(bad)", { XX } },
d5d7db8e
L		 8041 { "(bad)", { XX } },
8042 { "(bad)", { XX } },
8043 { "(bad)", { XX } },
8044 { "(bad)", { XX } },
c0f3af97 8045 /* c8 */
d5d7db8e
L		 8046 { "(bad)", { XX } },
8047 { "(bad)", { XX } },
8048 { "(bad)", { XX } },
8049 { "(bad)", { XX } },
d5d7db8e 8050 { "(bad)", { XX } },
d5d7db8e
L		 8051 { "(bad)", { XX } },
8052 { "(bad)", { XX } },
d5d7db8e 8053 { "(bad)", { XX } },
c0f3af97 8054 /* d0 */
d5d7db8e
L		 8055 { "(bad)", { XX } },
8056 { "(bad)", { XX } },
d5d7db8e
L		 8057 { "(bad)", { XX } },
8058 { "(bad)", { XX } },
8059 { "(bad)", { XX } },
8060 { "(bad)", { XX } },
d5d7db8e 8061 { "(bad)", { XX } },
d5d7db8e 8062 { "(bad)", { XX } },
c0f3af97 8063 /* d8 */
d5d7db8e 8064 { "(bad)", { XX } },
d5d7db8e
L		 8065 { "(bad)", { XX } },
8066 { "(bad)", { XX } },
a5ff0eb2
L		 8067 { PREFIX_TABLE (PREFIX_VEX_38DB) },
8068 { PREFIX_TABLE (PREFIX_VEX_38DC) },
8069 { PREFIX_TABLE (PREFIX_VEX_38DD) },
8070 { PREFIX_TABLE (PREFIX_VEX_38DE) },
8071 { PREFIX_TABLE (PREFIX_VEX_38DF) },
c0f3af97 8072 /* e0 */
d5d7db8e 8073 { "(bad)", { XX } },
d5d7db8e
L		 8074 { "(bad)", { XX } },
8075 { "(bad)", { XX } },
8076 { "(bad)", { XX } },
8077 { "(bad)", { XX } },
d5d7db8e
L		 8078 { "(bad)", { XX } },
8079 { "(bad)", { XX } },
8080 { "(bad)", { XX } },
c0f3af97 8081 /* e8 */
d5d7db8e
L		 8082 { "(bad)", { XX } },
8083 { "(bad)", { XX } },
8084 { "(bad)", { XX } },
8085 { "(bad)", { XX } },
8086 { "(bad)", { XX } },
d5d7db8e
L		 8087 { "(bad)", { XX } },
8088 { "(bad)", { XX } },
8089 { "(bad)", { XX } },
c0f3af97 8090 /* f0 */
d5d7db8e
L		 8091 { "(bad)", { XX } },
8092 { "(bad)", { XX } },
8093 { "(bad)", { XX } },
8094 { "(bad)", { XX } },
8095 { "(bad)", { XX } },
d5d7db8e
L		 8096 { "(bad)", { XX } },
8097 { "(bad)", { XX } },
8098 { "(bad)", { XX } },
c0f3af97 8099 /* f8 */
d5d7db8e
L		 8100 { "(bad)", { XX } },
8101 { "(bad)", { XX } },
8102 { "(bad)", { XX } },
8103 { "(bad)", { XX } },
8104 { "(bad)", { XX } },
d5d7db8e
L		 8105 { "(bad)", { XX } },
8106 { "(bad)", { XX } },
8107 { "(bad)", { XX } },
c0f3af97
L		 8108 },
8109 /* VEX_0F3A */
8110 {
8111 /* 00 */
d5d7db8e
L		 8112 { "(bad)", { XX } },
8113 { "(bad)", { XX } },
8114 { "(bad)", { XX } },
8115 { "(bad)", { XX } },
c0f3af97
L		 8116 { PREFIX_TABLE (PREFIX_VEX_3A04) },
8117 { PREFIX_TABLE (PREFIX_VEX_3A05) },
8118 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 8119 { "(bad)", { XX } },
c0f3af97
L		 8120 /* 08 */
8121 { PREFIX_TABLE (PREFIX_VEX_3A08) },
8122 { PREFIX_TABLE (PREFIX_VEX_3A09) },
8123 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
8124 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
8125 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
8126 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
8127 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
8128 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
8129 /* 10 */
d5d7db8e
L		 8130 { "(bad)", { XX } },
8131 { "(bad)", { XX } },
8132 { "(bad)", { XX } },
8133 { "(bad)", { XX } },
c0f3af97
L		 8134 { PREFIX_TABLE (PREFIX_VEX_3A14) },
8135 { PREFIX_TABLE (PREFIX_VEX_3A15) },
8136 { PREFIX_TABLE (PREFIX_VEX_3A16) },
8137 { PREFIX_TABLE (PREFIX_VEX_3A17) },
8138 /* 18 */
8139 { PREFIX_TABLE (PREFIX_VEX_3A18) },
8140 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 8141 { "(bad)", { XX } },
8142 { "(bad)", { XX } },
8143 { "(bad)", { XX } },
8144 { "(bad)", { XX } },
d5d7db8e
L		 8145 { "(bad)", { XX } },
8146 { "(bad)", { XX } },
c0f3af97
L		 8147 /* 20 */
8148 { PREFIX_TABLE (PREFIX_VEX_3A20) },
8149 { PREFIX_TABLE (PREFIX_VEX_3A21) },
8150 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 8151 { "(bad)", { XX } },
8152 { "(bad)", { XX } },
8153 { "(bad)", { XX } },
8154 { "(bad)", { XX } },
8155 { "(bad)", { XX } },
c0f3af97 8156 /* 28 */
d5d7db8e 8157 { "(bad)", { XX } },
d5d7db8e
L		 8158 { "(bad)", { XX } },
8159 { "(bad)", { XX } },
8160 { "(bad)", { XX } },
8161 { "(bad)", { XX } },
8162 { "(bad)", { XX } },
8163 { "(bad)", { XX } },
8164 { "(bad)", { XX } },
c0f3af97 8165 /* 30 */
d5d7db8e 8166 { "(bad)", { XX } },
d5d7db8e
L		 8167 { "(bad)", { XX } },
8168 { "(bad)", { XX } },
8169 { "(bad)", { XX } },
8170 { "(bad)", { XX } },
8171 { "(bad)", { XX } },
8172 { "(bad)", { XX } },
8173 { "(bad)", { XX } },
c0f3af97 8174 /* 38 */
d5d7db8e 8175 { "(bad)", { XX } },
d5d7db8e
L		 8176 { "(bad)", { XX } },
8177 { "(bad)", { XX } },
8178 { "(bad)", { XX } },
8179 { "(bad)", { XX } },
8180 { "(bad)", { XX } },
8181 { "(bad)", { XX } },
8182 { "(bad)", { XX } },
c0f3af97
L		 8183 /* 40 */
8184 { PREFIX_TABLE (PREFIX_VEX_3A40) },
8185 { PREFIX_TABLE (PREFIX_VEX_3A41) },
8186 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 8187 { "(bad)", { XX } },
ce2f5b3c 8188 { PREFIX_TABLE (PREFIX_VEX_3A44) },
d5d7db8e
L		 8189 { "(bad)", { XX } },
8190 { "(bad)", { XX } },
8191 { "(bad)", { XX } },
c0f3af97 8192 /* 48 */
0bfee649
L		 8193 { "(bad)", { XX } },
8194 { "(bad)", { XX } },
c0f3af97
L		 8195 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
8196 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
8197 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 8198 { "(bad)", { XX } },
8199 { "(bad)", { XX } },
8200 { "(bad)", { XX } },
c0f3af97 8201 /* 50 */
d5d7db8e 8202 { "(bad)", { XX } },
d5d7db8e
L		 8203 { "(bad)", { XX } },
8204 { "(bad)", { XX } },
8205 { "(bad)", { XX } },
8206 { "(bad)", { XX } },
8207 { "(bad)", { XX } },
8208 { "(bad)", { XX } },
8209 { "(bad)", { XX } },
c0f3af97 8210 /* 58 */
d5d7db8e 8211 { "(bad)", { XX } },
d5d7db8e
L		 8212 { "(bad)", { XX } },
8213 { "(bad)", { XX } },
8214 { "(bad)", { XX } },
922d8de8
DR		 8215 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
8216 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
8217 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
8218 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
c0f3af97
L		 8219 /* 60 */
8220 { PREFIX_TABLE (PREFIX_VEX_3A60) },
8221 { PREFIX_TABLE (PREFIX_VEX_3A61) },
8222 { PREFIX_TABLE (PREFIX_VEX_3A62) },
8223 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 8224 { "(bad)", { XX } },
8225 { "(bad)", { XX } },
8226 { "(bad)", { XX } },
8227 { "(bad)", { XX } },
c0f3af97 8228 /* 68 */
922d8de8
DR		 8229 { PREFIX_TABLE (PREFIX_VEX_3A68) },
8230 { PREFIX_TABLE (PREFIX_VEX_3A69) },
8231 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
8232 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
8233 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
8234 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
8235 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
8236 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
c0f3af97 8237 /* 70 */
d5d7db8e 8238 { "(bad)", { XX } },
d5d7db8e
L		 8239 { "(bad)", { XX } },
8240 { "(bad)", { XX } },
8241 { "(bad)", { XX } },
8242 { "(bad)", { XX } },
8243 { "(bad)", { XX } },
8244 { "(bad)", { XX } },
8245 { "(bad)", { XX } },
c0f3af97 8246 /* 78 */
922d8de8
DR		 8247 { PREFIX_TABLE (PREFIX_VEX_3A78) },
8248 { PREFIX_TABLE (PREFIX_VEX_3A79) },
8249 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
8250 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
8251 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
8252 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
8253 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
8254 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
c0f3af97 8255 /* 80 */
d5d7db8e 8256 { "(bad)", { XX } },
d5d7db8e
L		 8257 { "(bad)", { XX } },
8258 { "(bad)", { XX } },
8259 { "(bad)", { XX } },
8260 { "(bad)", { XX } },
8261 { "(bad)", { XX } },
8262 { "(bad)", { XX } },
8263 { "(bad)", { XX } },
c0f3af97 8264 /* 88 */
d5d7db8e 8265 { "(bad)", { XX } },
d5d7db8e
L		 8266 { "(bad)", { XX } },
8267 { "(bad)", { XX } },
8268 { "(bad)", { XX } },
8269 { "(bad)", { XX } },
8270 { "(bad)", { XX } },
8271 { "(bad)", { XX } },
8272 { "(bad)", { XX } },
c0f3af97 8273 /* 90 */
d5d7db8e 8274 { "(bad)", { XX } },
d5d7db8e
L		 8275 { "(bad)", { XX } },
8276 { "(bad)", { XX } },
8277 { "(bad)", { XX } },
8278 { "(bad)", { XX } },
8279 { "(bad)", { XX } },
8280 { "(bad)", { XX } },
8281 { "(bad)", { XX } },
c0f3af97 8282 /* 98 */
d5d7db8e 8283 { "(bad)", { XX } },
d5d7db8e
L		 8284 { "(bad)", { XX } },
8285 { "(bad)", { XX } },
8286 { "(bad)", { XX } },
8287 { "(bad)", { XX } },
8288 { "(bad)", { XX } },
8289 { "(bad)", { XX } },
8290 { "(bad)", { XX } },
c0f3af97 8291 /* a0 */
d5d7db8e 8292 { "(bad)", { XX } },
85f10a01
MM		 8293 { "(bad)", { XX } },
8294 { "(bad)", { XX } },
d5d7db8e
L		 8295 { "(bad)", { XX } },
8296 { "(bad)", { XX } },
8297 { "(bad)", { XX } },
8298 { "(bad)", { XX } },
8299 { "(bad)", { XX } },
c0f3af97 8300 /* a8 */
d5d7db8e 8301 { "(bad)", { XX } },
d5d7db8e
L		 8302 { "(bad)", { XX } },
8303 { "(bad)", { XX } },
8304 { "(bad)", { XX } },
8305 { "(bad)", { XX } },
8306 { "(bad)", { XX } },
8307 { "(bad)", { XX } },
8308 { "(bad)", { XX } },
c0f3af97
L		 8309 /* b0 */
8310 { "(bad)", { XX } },
8311 { "(bad)", { XX } },
8312 { "(bad)", { XX } },
8313 { "(bad)", { XX } },
8314 { "(bad)", { XX } },
8315 { "(bad)", { XX } },
8316 { "(bad)", { XX } },
8317 { "(bad)", { XX } },
8318 /* b8 */
8319 { "(bad)", { XX } },
8320 { "(bad)", { XX } },
8321 { "(bad)", { XX } },
8322 { "(bad)", { XX } },
8323 { "(bad)", { XX } },
8324 { "(bad)", { XX } },
8325 { "(bad)", { XX } },
8326 { "(bad)", { XX } },
8327 /* c0 */
8328 { "(bad)", { XX } },
8329 { "(bad)", { XX } },
8330 { "(bad)", { XX } },
8331 { "(bad)", { XX } },
8332 { "(bad)", { XX } },
8333 { "(bad)", { XX } },
8334 { "(bad)", { XX } },
8335 { "(bad)", { XX } },
8336 /* c8 */
8337 { "(bad)", { XX } },
8338 { "(bad)", { XX } },
d5d7db8e 8339 { "(bad)", { XX } },
d5d7db8e
L		 8340 { "(bad)", { XX } },
8341 { "(bad)", { XX } },
8342 { "(bad)", { XX } },
8343 { "(bad)", { XX } },
8344 { "(bad)", { XX } },
c0f3af97
L		 8345 /* d0 */
8346 { "(bad)", { XX } },
8347 { "(bad)", { XX } },
8348 { "(bad)", { XX } },
d5d7db8e
L		 8349 { "(bad)", { XX } },
8350 { "(bad)", { XX } },
8351 { "(bad)", { XX } },
c0f3af97
L		 8352 { "(bad)", { XX } },
8353 { "(bad)", { XX } },
8354 /* d8 */
8355 { "(bad)", { XX } },
d5d7db8e
L		 8356 { "(bad)", { XX } },
8357 { "(bad)", { XX } },
8358 { "(bad)", { XX } },
8359 { "(bad)", { XX } },
8360 { "(bad)", { XX } },
8361 { "(bad)", { XX } },
a5ff0eb2 8362 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
c0f3af97 8363 /* e0 */
d5d7db8e 8364 { "(bad)", { XX } },
d5d7db8e
L		 8365 { "(bad)", { XX } },
8366 { "(bad)", { XX } },
8367 { "(bad)", { XX } },
8368 { "(bad)", { XX } },
8369 { "(bad)", { XX } },
8370 { "(bad)", { XX } },
8371 { "(bad)", { XX } },
c0f3af97 8372 /* e8 */
d5d7db8e 8373 { "(bad)", { XX } },
d5d7db8e
L		 8374 { "(bad)", { XX } },
8375 { "(bad)", { XX } },
8376 { "(bad)", { XX } },
8377 { "(bad)", { XX } },
8378 { "(bad)", { XX } },
8379 { "(bad)", { XX } },
8380 { "(bad)", { XX } },
c0f3af97 8381 /* f0 */
d5d7db8e 8382 { "(bad)", { XX } },
d5d7db8e
L		 8383 { "(bad)", { XX } },
8384 { "(bad)", { XX } },
8385 { "(bad)", { XX } },
8386 { "(bad)", { XX } },
8387 { "(bad)", { XX } },
8388 { "(bad)", { XX } },
8389 { "(bad)", { XX } },
c0f3af97 8390 /* f8 */
d5d7db8e 8391 { "(bad)", { XX } },
d5d7db8e
L		 8392 { "(bad)", { XX } },
8393 { "(bad)", { XX } },
8394 { "(bad)", { XX } },
8395 { "(bad)", { XX } },
8396 { "(bad)", { XX } },
8397 { "(bad)", { XX } },
8398 { "(bad)", { XX } },
c0f3af97
L		 8399 },
8400};
8401
8402static const struct dis386 vex_len_table[][2] = {
8403 /* VEX_LEN_10_P_1 */
8404 {
9e30b8e0 8405 { VEX_W_TABLE (VEX_W_10_P_1) },
d5d7db8e 8406 { "(bad)", { XX } },
c0f3af97
L		 8407 },
8408
8409 /* VEX_LEN_10_P_3 */
8410 {
9e30b8e0 8411 { VEX_W_TABLE (VEX_W_10_P_3) },
d5d7db8e 8412 { "(bad)", { XX } },
c0f3af97
L		 8413 },
8414
8415 /* VEX_LEN_11_P_1 */
8416 {
9e30b8e0 8417 { VEX_W_TABLE (VEX_W_11_P_1) },
d5d7db8e 8418 { "(bad)", { XX } },
c0f3af97
L		 8419 },
8420
8421 /* VEX_LEN_11_P_3 */
8422 {
9e30b8e0 8423 { VEX_W_TABLE (VEX_W_11_P_3) },
d5d7db8e 8424 { "(bad)", { XX } },
c0f3af97
L		 8425 },
8426
8427 /* VEX_LEN_12_P_0_M_0 */
8428 {
9e30b8e0 8429 { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
d5d7db8e 8430 { "(bad)", { XX } },
c0f3af97
L		 8431 },
8432
8433 /* VEX_LEN_12_P_0_M_1 */
8434 {
9e30b8e0 8435 { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
d5d7db8e 8436 { "(bad)", { XX } },
c0f3af97
L		 8437 },
8438
8439 /* VEX_LEN_12_P_2 */
8440 {
9e30b8e0 8441 { VEX_W_TABLE (VEX_W_12_P_2) },
d5d7db8e 8442 { "(bad)", { XX } },
c0f3af97
L		 8443 },
8444
8445 /* VEX_LEN_13_M_0 */
8446 {
9e30b8e0 8447 { VEX_W_TABLE (VEX_W_13_M_0) },
85f10a01 8448 { "(bad)", { XX } },
c0f3af97
L		 8449 },
8450
8451 /* VEX_LEN_16_P_0_M_0 */
8452 {
9e30b8e0 8453 { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
85f10a01 8454 { "(bad)", { XX } },
c0f3af97
L		 8455 },
8456
8457 /* VEX_LEN_16_P_0_M_1 */
8458 {
9e30b8e0 8459 { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
85f10a01 8460 { "(bad)", { XX } },
c0f3af97
L		 8461 },
8462
8463 /* VEX_LEN_16_P_2 */
8464 {
9e30b8e0 8465 { VEX_W_TABLE (VEX_W_16_P_2) },
85f10a01 8466 { "(bad)", { XX } },
c0f3af97
L		 8467 },
8468
8469 /* VEX_LEN_17_M_0 */
8470 {
9e30b8e0 8471 { VEX_W_TABLE (VEX_W_17_M_0) },
85f10a01 8472 { "(bad)", { XX } },
c0f3af97
L		 8473 },
8474
8475 /* VEX_LEN_2A_P_1 */
8476 {
8477 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 8478 { "(bad)", { XX } },
c0f3af97
L		 8479 },
8480
8481 /* VEX_LEN_2A_P_3 */
8482 {
8483 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 8484 { "(bad)", { XX } },
c0f3af97
L		 8485 },
8486
c0f3af97
L		 8487 /* VEX_LEN_2C_P_1 */
8488 {
8489 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 8490 { "(bad)", { XX } },
c0f3af97
L		 8491 },
8492
8493 /* VEX_LEN_2C_P_3 */
8494 {
8495 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 8496 { "(bad)", { XX } },
c0f3af97
L		 8497 },
8498
8499 /* VEX_LEN_2D_P_1 */
8500 {
8501 { "vcvtss2siY", { Gv, EXd } },
85f10a01 8502 { "(bad)", { XX } },
c0f3af97
L		 8503 },
8504
8505 /* VEX_LEN_2D_P_3 */
8506 {
8507 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 8508 { "(bad)", { XX } },
c0f3af97
L		 8509 },
8510
8511 /* VEX_LEN_2E_P_0 */
8512 {
9e30b8e0 8513 { VEX_W_TABLE (VEX_W_2E_P_0) },
d5d7db8e 8514 { "(bad)", { XX } },
c0f3af97
L		 8515 },
8516
8517 /* VEX_LEN_2E_P_2 */
8518 {
9e30b8e0 8519 { VEX_W_TABLE (VEX_W_2E_P_2) },
d5d7db8e 8520 { "(bad)", { XX } },
c0f3af97
L		 8521 },
8522
8523 /* VEX_LEN_2F_P_0 */
8524 {
9e30b8e0 8525 { VEX_W_TABLE (VEX_W_2F_P_0) },
d5d7db8e 8526 { "(bad)", { XX } },
c0f3af97
L		 8527 },
8528
8529 /* VEX_LEN_2F_P_2 */
8530 {
9e30b8e0 8531 { VEX_W_TABLE (VEX_W_2F_P_2) },
d5d7db8e 8532 { "(bad)", { XX } },
c0f3af97
L		 8533 },
8534
8535 /* VEX_LEN_51_P_1 */
8536 {
9e30b8e0 8537 { VEX_W_TABLE (VEX_W_51_P_1) },
d5d7db8e 8538 { "(bad)", { XX } },
c0f3af97
L		 8539 },
8540
8541 /* VEX_LEN_51_P_3 */
8542 {
9e30b8e0 8543 { VEX_W_TABLE (VEX_W_51_P_3) },
d5d7db8e 8544 { "(bad)", { XX } },
c0f3af97
L		 8545 },
8546
8547 /* VEX_LEN_52_P_1 */
8548 {
9e30b8e0 8549 { VEX_W_TABLE (VEX_W_52_P_1) },
d5d7db8e 8550 { "(bad)", { XX } },
c0f3af97
L		 8551 },
8552
8553 /* VEX_LEN_53_P_1 */
8554 {
9e30b8e0 8555 { VEX_W_TABLE (VEX_W_53_P_1) },
d5d7db8e 8556 { "(bad)", { XX } },
c0f3af97
L		 8557 },
8558
8559 /* VEX_LEN_58_P_1 */
8560 {
9e30b8e0 8561 { VEX_W_TABLE (VEX_W_58_P_1) },
d5d7db8e 8562 { "(bad)", { XX } },
c0f3af97
L		 8563 },
8564
8565 /* VEX_LEN_58_P_3 */
8566 {
9e30b8e0 8567 { VEX_W_TABLE (VEX_W_58_P_3) },
d5d7db8e 8568 { "(bad)", { XX } },
c0f3af97
L		 8569 },
8570
8571 /* VEX_LEN_59_P_1 */
8572 {
9e30b8e0 8573 { VEX_W_TABLE (VEX_W_59_P_1) },
d5d7db8e 8574 { "(bad)", { XX } },
c0f3af97
L		 8575 },
8576
8577 /* VEX_LEN_59_P_3 */
8578 {
9e30b8e0 8579 { VEX_W_TABLE (VEX_W_59_P_3) },
d5d7db8e 8580 { "(bad)", { XX } },
c0f3af97
L		 8581 },
8582
8583 /* VEX_LEN_5A_P_1 */
8584 {
9e30b8e0 8585 { VEX_W_TABLE (VEX_W_5A_P_1) },
d5d7db8e 8586 { "(bad)", { XX } },
c0f3af97
L		 8587 },
8588
8589 /* VEX_LEN_5A_P_3 */
8590 {
9e30b8e0 8591 { VEX_W_TABLE (VEX_W_5A_P_3) },
d5d7db8e 8592 { "(bad)", { XX } },
c0f3af97
L		 8593 },
8594
8595 /* VEX_LEN_5C_P_1 */
8596 {
9e30b8e0 8597 { VEX_W_TABLE (VEX_W_5C_P_1) },
d5d7db8e 8598 { "(bad)", { XX } },
c0f3af97
L		 8599 },
8600
8601 /* VEX_LEN_5C_P_3 */
8602 {
9e30b8e0 8603 { VEX_W_TABLE (VEX_W_5C_P_3) },
d5d7db8e 8604 { "(bad)", { XX } },
c0f3af97
L		 8605 },
8606
8607 /* VEX_LEN_5D_P_1 */
8608 {
9e30b8e0 8609 { VEX_W_TABLE (VEX_W_5D_P_1) },
d5d7db8e 8610 { "(bad)", { XX } },
c0f3af97
L		 8611 },
8612
8613 /* VEX_LEN_5D_P_3 */
8614 {
9e30b8e0 8615 { VEX_W_TABLE (VEX_W_5D_P_3) },
d5d7db8e 8616 { "(bad)", { XX } },
c0f3af97
L		 8617 },
8618
8619 /* VEX_LEN_5E_P_1 */
8620 {
9e30b8e0 8621 { VEX_W_TABLE (VEX_W_5E_P_1) },
85f10a01 8622 { "(bad)", { XX } },
c0f3af97
L		 8623 },
8624
8625 /* VEX_LEN_5E_P_3 */
8626 {
9e30b8e0 8627 { VEX_W_TABLE (VEX_W_5E_P_3) },
85f10a01 8628 { "(bad)", { XX } },
c0f3af97
L		 8629 },
8630
8631 /* VEX_LEN_5F_P_1 */
8632 {
9e30b8e0 8633 { VEX_W_TABLE (VEX_W_5F_P_1) },
85f10a01 8634 { "(bad)", { XX } },
c0f3af97
L		 8635 },
8636
8637 /* VEX_LEN_5F_P_3 */
8638 {
9e30b8e0 8639 { VEX_W_TABLE (VEX_W_5F_P_3) },
85f10a01 8640 { "(bad)", { XX } },
c0f3af97
L		 8641 },
8642
8643 /* VEX_LEN_60_P_2 */
8644 {
9e30b8e0 8645 { VEX_W_TABLE (VEX_W_60_P_2) },
d5d7db8e 8646 { "(bad)", { XX } },
c0f3af97
L		 8647 },
8648
8649 /* VEX_LEN_61_P_2 */
8650 {
9e30b8e0 8651 { VEX_W_TABLE (VEX_W_61_P_2) },
d5d7db8e 8652 { "(bad)", { XX } },
c0f3af97
L		 8653 },
8654
8655 /* VEX_LEN_62_P_2 */
8656 {
9e30b8e0 8657 { VEX_W_TABLE (VEX_W_62_P_2) },
d5d7db8e 8658 { "(bad)", { XX } },
c0f3af97
L		 8659 },
8660
8661 /* VEX_LEN_63_P_2 */
8662 {
9e30b8e0 8663 { VEX_W_TABLE (VEX_W_63_P_2) },
d5d7db8e 8664 { "(bad)", { XX } },
c0f3af97
L		 8665 },
8666
8667 /* VEX_LEN_64_P_2 */
8668 {
9e30b8e0 8669 { VEX_W_TABLE (VEX_W_64_P_2) },
d5d7db8e 8670 { "(bad)", { XX } },
c0f3af97
L		 8671 },
8672
8673 /* VEX_LEN_65_P_2 */
8674 {
9e30b8e0 8675 { VEX_W_TABLE (VEX_W_65_P_2) },
d5d7db8e 8676 { "(bad)", { XX } },
c0f3af97
L		 8677 },
8678
8679 /* VEX_LEN_66_P_2 */
8680 {
9e30b8e0 8681 { VEX_W_TABLE (VEX_W_66_P_2) },
d5d7db8e 8682 { "(bad)", { XX } },
c0f3af97
L		 8683 },
8684
8685 /* VEX_LEN_67_P_2 */
8686 {
9e30b8e0 8687 { VEX_W_TABLE (VEX_W_67_P_2) },
d5d7db8e 8688 { "(bad)", { XX } },
c0f3af97
L		 8689 },
8690
8691 /* VEX_LEN_68_P_2 */
8692 {
9e30b8e0 8693 { VEX_W_TABLE (VEX_W_68_P_2) },
d5d7db8e 8694 { "(bad)", { XX } },
c0f3af97
L		 8695 },
8696
8697 /* VEX_LEN_69_P_2 */
8698 {
9e30b8e0 8699 { VEX_W_TABLE (VEX_W_69_P_2) },
d5d7db8e 8700 { "(bad)", { XX } },
c0f3af97
L		 8701 },
8702
8703 /* VEX_LEN_6A_P_2 */
8704 {
9e30b8e0 8705 { VEX_W_TABLE (VEX_W_6A_P_2) },
d5d7db8e 8706 { "(bad)", { XX } },
c0f3af97
L		 8707 },
8708
8709 /* VEX_LEN_6B_P_2 */
8710 {
9e30b8e0 8711 { VEX_W_TABLE (VEX_W_6B_P_2) },
d5d7db8e 8712 { "(bad)", { XX } },
c0f3af97
L		 8713 },
8714
8715 /* VEX_LEN_6C_P_2 */
8716 {
9e30b8e0 8717 { VEX_W_TABLE (VEX_W_6C_P_2) },
d5d7db8e 8718 { "(bad)", { XX } },
c0f3af97
L		 8719 },
8720
8721 /* VEX_LEN_6D_P_2 */
8722 {
9e30b8e0 8723 { VEX_W_TABLE (VEX_W_6D_P_2) },
d5d7db8e 8724 { "(bad)", { XX } },
c0f3af97
L		 8725 },
8726
8727 /* VEX_LEN_6E_P_2 */
8728 {
8729 { "vmovK", { XM, Edq } },
d5d7db8e 8730 { "(bad)", { XX } },
c0f3af97
L		 8731 },
8732
8733 /* VEX_LEN_70_P_1 */
8734 {
9e30b8e0 8735 { VEX_W_TABLE (VEX_W_70_P_1) },
d5d7db8e 8736 { "(bad)", { XX } },
c0f3af97
L		 8737 },
8738
8739 /* VEX_LEN_70_P_2 */
8740 {
9e30b8e0 8741 { VEX_W_TABLE (VEX_W_70_P_2) },
d5d7db8e 8742 { "(bad)", { XX } },
c0f3af97
L		 8743 },
8744
8745 /* VEX_LEN_70_P_3 */
8746 {
9e30b8e0 8747 { VEX_W_TABLE (VEX_W_70_P_3) },
d5d7db8e 8748 { "(bad)", { XX } },
c0f3af97
L		 8749 },
8750
8751 /* VEX_LEN_71_R_2_P_2 */
8752 {
9e30b8e0 8753 { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
d5d7db8e 8754 { "(bad)", { XX } },
c0f3af97
L		 8755 },
8756
8757 /* VEX_LEN_71_R_4_P_2 */
8758 {
9e30b8e0 8759 { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
d5d7db8e 8760 { "(bad)", { XX } },
c0f3af97
L		 8761 },
8762
8763 /* VEX_LEN_71_R_6_P_2 */
8764 {
9e30b8e0 8765 { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
d5d7db8e 8766 { "(bad)", { XX } },
c0f3af97
L		 8767 },
8768
8769 /* VEX_LEN_72_R_2_P_2 */
8770 {
9e30b8e0 8771 { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
d5d7db8e 8772 { "(bad)", { XX } },
c0f3af97
L		 8773 },
8774
8775 /* VEX_LEN_72_R_4_P_2 */
8776 {
9e30b8e0 8777 { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
d5d7db8e 8778 { "(bad)", { XX } },
c0f3af97
L		 8779 },
8780
8781 /* VEX_LEN_72_R_6_P_2 */
8782 {
9e30b8e0 8783 { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
d5d7db8e 8784 { "(bad)", { XX } },
c0f3af97
L		 8785 },
8786
8787 /* VEX_LEN_73_R_2_P_2 */
8788 {
9e30b8e0 8789 { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
d5d7db8e 8790 { "(bad)", { XX } },
c0f3af97
L		 8791 },
8792
8793 /* VEX_LEN_73_R_3_P_2 */
8794 {
9e30b8e0 8795 { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
d5d7db8e 8796 { "(bad)", { XX } },
c0f3af97
L		 8797 },
8798
8799 /* VEX_LEN_73_R_6_P_2 */
8800 {
9e30b8e0 8801 { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
d5d7db8e 8802 { "(bad)", { XX } },
c0f3af97
L		 8803 },
8804
8805 /* VEX_LEN_73_R_7_P_2 */
8806 {
9e30b8e0 8807 { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
d5d7db8e 8808 { "(bad)", { XX } },
c0f3af97
L		 8809 },
8810
8811 /* VEX_LEN_74_P_2 */
8812 {
9e30b8e0 8813 { VEX_W_TABLE (VEX_W_74_P_2) },
d5d7db8e 8814 { "(bad)", { XX } },
c0f3af97
L		 8815 },
8816
8817 /* VEX_LEN_75_P_2 */
8818 {
9e30b8e0 8819 { VEX_W_TABLE (VEX_W_75_P_2) },
d5d7db8e 8820 { "(bad)", { XX } },
c0f3af97
L		 8821 },
8822
8823 /* VEX_LEN_76_P_2 */
8824 {
9e30b8e0 8825 { VEX_W_TABLE (VEX_W_76_P_2) },
d5d7db8e 8826 { "(bad)", { XX } },
c0f3af97
L		 8827 },
8828
8829 /* VEX_LEN_7E_P_1 */
8830 {
9e30b8e0 8831 { VEX_W_TABLE (VEX_W_7E_P_1) },
d5d7db8e 8832 { "(bad)", { XX } },
c0f3af97
L		 8833 },
8834
8835 /* VEX_LEN_7E_P_2 */
8836 {
8837 { "vmovK", { Edq, XM } },
d5d7db8e 8838 { "(bad)", { XX } },
c0f3af97
L		 8839 },
8840
9daa0d29 8841 /* VEX_LEN_AE_R_2_M_0 */
c0f3af97 8842 {
9e30b8e0 8843 { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
d5d7db8e 8844 { "(bad)", { XX } },
c0f3af97
L		 8845 },
8846
9daa0d29 8847 /* VEX_LEN_AE_R_3_M_0 */
c0f3af97 8848 {
9e30b8e0 8849 { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
d5d7db8e 8850 { "(bad)", { XX } },
c0f3af97
L		 8851 },
8852
8853 /* VEX_LEN_C2_P_1 */
8854 {
9e30b8e0 8855 { VEX_W_TABLE (VEX_W_C2_P_1) },
d5d7db8e 8856 { "(bad)", { XX } },
c0f3af97
L		 8857 },
8858
8859 /* VEX_LEN_C2_P_3 */
8860 {
9e30b8e0 8861 { VEX_W_TABLE (VEX_W_C2_P_3) },
d5d7db8e 8862 { "(bad)", { XX } },
c0f3af97
L		 8863 },
8864
8865 /* VEX_LEN_C4_P_2 */
8866 {
9e30b8e0 8867 { VEX_W_TABLE (VEX_W_C4_P_2) },
d5d7db8e 8868 { "(bad)", { XX } },
c0f3af97
L		 8869 },
8870
8871 /* VEX_LEN_C5_P_2 */
8872 {
9e30b8e0 8873 { VEX_W_TABLE (VEX_W_C5_P_2) },
d5d7db8e 8874 { "(bad)", { XX } },
c0f3af97
L		 8875 },
8876
8877 /* VEX_LEN_D1_P_2 */
8878 {
9e30b8e0 8879 { VEX_W_TABLE (VEX_W_D1_P_2) },
d5d7db8e 8880 { "(bad)", { XX } },
c0f3af97
L		 8881 },
8882
8883 /* VEX_LEN_D2_P_2 */
8884 {
9e30b8e0 8885 { VEX_W_TABLE (VEX_W_D2_P_2) },
d5d7db8e 8886 { "(bad)", { XX } },
c0f3af97
L		 8887 },
8888
8889 /* VEX_LEN_D3_P_2 */
8890 {
9e30b8e0 8891 { VEX_W_TABLE (VEX_W_D3_P_2) },
d5d7db8e 8892 { "(bad)", { XX } },
c0f3af97
L		 8893 },
8894
8895 /* VEX_LEN_D4_P_2 */
8896 {
9e30b8e0 8897 { VEX_W_TABLE (VEX_W_D4_P_2) },
d5d7db8e 8898 { "(bad)", { XX } },
c0f3af97
L		 8899 },
8900
8901 /* VEX_LEN_D5_P_2 */
8902 {
9e30b8e0 8903 { VEX_W_TABLE (VEX_W_D5_P_2) },
d5d7db8e 8904 { "(bad)", { XX } },
c0f3af97
L		 8905 },
8906
8907 /* VEX_LEN_D6_P_2 */
8908 {
9e30b8e0 8909 { VEX_W_TABLE (VEX_W_D6_P_2) },
d5d7db8e 8910 { "(bad)", { XX } },
c0f3af97
L		 8911 },
8912
8913 /* VEX_LEN_D7_P_2_M_1 */
8914 {
9e30b8e0 8915 { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
d5d7db8e 8916 { "(bad)", { XX } },
c0f3af97
L		 8917 },
8918
8919 /* VEX_LEN_D8_P_2 */
8920 {
9e30b8e0 8921 { VEX_W_TABLE (VEX_W_D8_P_2) },
d5d7db8e 8922 { "(bad)", { XX } },
c0f3af97
L		 8923 },
8924
8925 /* VEX_LEN_D9_P_2 */
8926 {
9e30b8e0 8927 { VEX_W_TABLE (VEX_W_D9_P_2) },
d5d7db8e 8928 { "(bad)", { XX } },
c0f3af97
L		 8929 },
8930
8931 /* VEX_LEN_DA_P_2 */
8932 {
9e30b8e0 8933 { VEX_W_TABLE (VEX_W_DA_P_2) },
d5d7db8e 8934 { "(bad)", { XX } },
c0f3af97
L		 8935 },
8936
8937 /* VEX_LEN_DB_P_2 */
8938 {
9e30b8e0 8939 { VEX_W_TABLE (VEX_W_DB_P_2) },
d5d7db8e 8940 { "(bad)", { XX } },
c0f3af97
L		 8941 },
8942
8943 /* VEX_LEN_DC_P_2 */
8944 {
9e30b8e0 8945 { VEX_W_TABLE (VEX_W_DC_P_2) },
d5d7db8e 8946 { "(bad)", { XX } },
c0f3af97
L		 8947 },
8948
8949 /* VEX_LEN_DD_P_2 */
8950 {
9e30b8e0 8951 { VEX_W_TABLE (VEX_W_DD_P_2) },
d5d7db8e 8952 { "(bad)", { XX } },
c0f3af97
L		 8953 },
8954
8955 /* VEX_LEN_DE_P_2 */
8956 {
9e30b8e0 8957 { VEX_W_TABLE (VEX_W_DE_P_2) },
d5d7db8e 8958 { "(bad)", { XX } },
c0f3af97
L		 8959 },
8960
8961 /* VEX_LEN_DF_P_2 */
8962 {
9e30b8e0 8963 { VEX_W_TABLE (VEX_W_DF_P_2) },
d5d7db8e 8964 { "(bad)", { XX } },
c0f3af97
L		 8965 },
8966
8967 /* VEX_LEN_E0_P_2 */
8968 {
9e30b8e0 8969 { VEX_W_TABLE (VEX_W_E0_P_2) },
d5d7db8e 8970 { "(bad)", { XX } },
c0f3af97
L		 8971 },
8972
8973 /* VEX_LEN_E1_P_2 */
8974 {
9e30b8e0 8975 { VEX_W_TABLE (VEX_W_E1_P_2) },
d5d7db8e 8976 { "(bad)", { XX } },
c0f3af97
L		 8977 },
8978
8979 /* VEX_LEN_E2_P_2 */
8980 {
9e30b8e0 8981 { VEX_W_TABLE (VEX_W_E2_P_2) },
d5d7db8e 8982 { "(bad)", { XX } },
c0f3af97
L		 8983 },
8984
8985 /* VEX_LEN_E3_P_2 */
8986 {
9e30b8e0 8987 { VEX_W_TABLE (VEX_W_E3_P_2) },
d5d7db8e 8988 { "(bad)", { XX } },
c0f3af97
L		 8989 },
8990
8991 /* VEX_LEN_E4_P_2 */
8992 {
9e30b8e0 8993 { VEX_W_TABLE (VEX_W_E4_P_2) },
d5d7db8e 8994 { "(bad)", { XX } },
c0f3af97
L		 8995 },
8996
8997 /* VEX_LEN_E5_P_2 */
8998 {
9e30b8e0 8999 { VEX_W_TABLE (VEX_W_E5_P_2) },
d5d7db8e 9000 { "(bad)", { XX } },
c0f3af97
L		 9001 },
9002
c0f3af97
L		 9003 /* VEX_LEN_E8_P_2 */
9004 {
9e30b8e0 9005 { VEX_W_TABLE (VEX_W_E8_P_2) },
d5d7db8e 9006 { "(bad)", { XX } },
c0f3af97
L		 9007 },
9008
9009 /* VEX_LEN_E9_P_2 */
9010 {
9e30b8e0 9011 { VEX_W_TABLE (VEX_W_E9_P_2) },
d5d7db8e 9012 { "(bad)", { XX } },
c0f3af97
L		 9013 },
9014
9015 /* VEX_LEN_EA_P_2 */
9016 {
9e30b8e0 9017 { VEX_W_TABLE (VEX_W_EA_P_2) },
d5d7db8e 9018 { "(bad)", { XX } },
c0f3af97
L		 9019 },
9020
9021 /* VEX_LEN_EB_P_2 */
9022 {
9e30b8e0 9023 { VEX_W_TABLE (VEX_W_EB_P_2) },
d5d7db8e 9024 { "(bad)", { XX } },
c0f3af97
L		 9025 },
9026
9027 /* VEX_LEN_EC_P_2 */
9028 {
9e30b8e0 9029 { VEX_W_TABLE (VEX_W_EC_P_2) },
d5d7db8e 9030 { "(bad)", { XX } },
c0f3af97
L		 9031 },
9032
9033 /* VEX_LEN_ED_P_2 */
9034 {
9e30b8e0 9035 { VEX_W_TABLE (VEX_W_ED_P_2) },
d5d7db8e 9036 { "(bad)", { XX } },
c0f3af97
L		 9037 },
9038
9039 /* VEX_LEN_EE_P_2 */
9040 {
9e30b8e0 9041 { VEX_W_TABLE (VEX_W_EE_P_2) },
d5d7db8e 9042 { "(bad)", { XX } },
c0f3af97
L		 9043 },
9044
9045 /* VEX_LEN_EF_P_2 */
9046 {
9e30b8e0 9047 { VEX_W_TABLE (VEX_W_EF_P_2) },
d5d7db8e 9048 { "(bad)", { XX } },
c0f3af97
L		 9049 },
9050
9051 /* VEX_LEN_F1_P_2 */
9052 {
9e30b8e0 9053 { VEX_W_TABLE (VEX_W_F1_P_2) },
d5d7db8e 9054 { "(bad)", { XX } },
c0f3af97
L		 9055 },
9056
9057 /* VEX_LEN_F2_P_2 */
9058 {
9e30b8e0 9059 { VEX_W_TABLE (VEX_W_F2_P_2) },
d5d7db8e 9060 { "(bad)", { XX } },
c0f3af97
L		 9061 },
9062
9063 /* VEX_LEN_F3_P_2 */
9064 {
9e30b8e0 9065 { VEX_W_TABLE (VEX_W_F3_P_2) },
d5d7db8e 9066 { "(bad)", { XX } },
c0f3af97
L		 9067 },
9068
9069 /* VEX_LEN_F4_P_2 */
9070 {
9e30b8e0 9071 { VEX_W_TABLE (VEX_W_F4_P_2) },
d5d7db8e 9072 { "(bad)", { XX } },
c0f3af97
L		 9073 },
9074
9075 /* VEX_LEN_F5_P_2 */
9076 {
9e30b8e0 9077 { VEX_W_TABLE (VEX_W_F5_P_2) },
d5d7db8e 9078 { "(bad)", { XX } },
c0f3af97
L		 9079 },
9080
9081 /* VEX_LEN_F6_P_2 */
9082 {
9e30b8e0 9083 { VEX_W_TABLE (VEX_W_F6_P_2) },
d5d7db8e 9084 { "(bad)", { XX } },
c0f3af97
L		 9085 },
9086
9087 /* VEX_LEN_F7_P_2 */
9088 {
9e30b8e0 9089 { VEX_W_TABLE (VEX_W_F7_P_2) },
d5d7db8e 9090 { "(bad)", { XX } },
c0f3af97
L		 9091 },
9092
9093 /* VEX_LEN_F8_P_2 */
9094 {
9e30b8e0 9095 { VEX_W_TABLE (VEX_W_F8_P_2) },
d5d7db8e 9096 { "(bad)", { XX } },
c0f3af97
L		 9097 },
9098
9099 /* VEX_LEN_F9_P_2 */
9100 {
9e30b8e0 9101 { VEX_W_TABLE (VEX_W_F9_P_2) },
d5d7db8e 9102 { "(bad)", { XX } },
c0f3af97
L		 9103 },
9104
9105 /* VEX_LEN_FA_P_2 */
9106 {
9e30b8e0 9107 { VEX_W_TABLE (VEX_W_FA_P_2) },
d5d7db8e 9108 { "(bad)", { XX } },
c0f3af97
L		 9109 },
9110
9111 /* VEX_LEN_FB_P_2 */
9112 {
9e30b8e0 9113 { VEX_W_TABLE (VEX_W_FB_P_2) },
d5d7db8e 9114 { "(bad)", { XX } },
c0f3af97
L		 9115 },
9116
9117 /* VEX_LEN_FC_P_2 */
9118 {
9e30b8e0 9119 { VEX_W_TABLE (VEX_W_FC_P_2) },
d5d7db8e 9120 { "(bad)", { XX } },
c0f3af97
L		 9121 },
9122
9123 /* VEX_LEN_FD_P_2 */
9124 {
9e30b8e0 9125 { VEX_W_TABLE (VEX_W_FD_P_2) },
d5d7db8e 9126 { "(bad)", { XX } },
c0f3af97
L		 9127 },
9128
9129 /* VEX_LEN_FE_P_2 */
9130 {
9e30b8e0 9131 { VEX_W_TABLE (VEX_W_FE_P_2) },
d5d7db8e 9132 { "(bad)", { XX } },
c0f3af97
L		 9133 },
9134
9135 /* VEX_LEN_3800_P_2 */
9136 {
9e30b8e0 9137 { VEX_W_TABLE (VEX_W_3800_P_2) },
d5d7db8e 9138 { "(bad)", { XX } },
c0f3af97
L		 9139 },
9140
9141 /* VEX_LEN_3801_P_2 */
9142 {
9e30b8e0 9143 { VEX_W_TABLE (VEX_W_3801_P_2) },
d5d7db8e 9144 { "(bad)", { XX } },
c0f3af97
L		 9145 },
9146
9147 /* VEX_LEN_3802_P_2 */
9148 {
9e30b8e0 9149 { VEX_W_TABLE (VEX_W_3802_P_2) },
d5d7db8e 9150 { "(bad)", { XX } },
c0f3af97
L		 9151 },
9152
9153 /* VEX_LEN_3803_P_2 */
9154 {
9e30b8e0 9155 { VEX_W_TABLE (VEX_W_3803_P_2) },
d5d7db8e 9156 { "(bad)", { XX } },
c0f3af97
L		 9157 },
9158
9159 /* VEX_LEN_3804_P_2 */
9160 {
9e30b8e0 9161 { VEX_W_TABLE (VEX_W_3804_P_2) },
d5d7db8e 9162 { "(bad)", { XX } },
c0f3af97
L		 9163 },
9164
9165 /* VEX_LEN_3805_P_2 */
9166 {
9e30b8e0 9167 { VEX_W_TABLE (VEX_W_3805_P_2) },
d5d7db8e 9168 { "(bad)", { XX } },
c0f3af97
L		 9169 },
9170
9171 /* VEX_LEN_3806_P_2 */
9172 {
9e30b8e0 9173 { VEX_W_TABLE (VEX_W_3806_P_2) },
d5d7db8e 9174 { "(bad)", { XX } },
c0f3af97
L		 9175 },
9176
9177 /* VEX_LEN_3807_P_2 */
9178 {
9e30b8e0 9179 { VEX_W_TABLE (VEX_W_3807_P_2) },
d5d7db8e 9180 { "(bad)", { XX } },
c0f3af97
L		 9181 },
9182
9183 /* VEX_LEN_3808_P_2 */
9184 {
9e30b8e0 9185 { VEX_W_TABLE (VEX_W_3808_P_2) },
d5d7db8e 9186 { "(bad)", { XX } },
c0f3af97
L		 9187 },
9188
9189 /* VEX_LEN_3809_P_2 */
9190 {
9e30b8e0 9191 { VEX_W_TABLE (VEX_W_3809_P_2) },
d5d7db8e 9192 { "(bad)", { XX } },
c0f3af97
L		 9193 },
9194
9195 /* VEX_LEN_380A_P_2 */
9196 {
9e30b8e0 9197 { VEX_W_TABLE (VEX_W_380A_P_2) },
d5d7db8e 9198 { "(bad)", { XX } },
c0f3af97
L		 9199 },
9200
9201 /* VEX_LEN_380B_P_2 */
9202 {
9e30b8e0 9203 { VEX_W_TABLE (VEX_W_380B_P_2) },
d5d7db8e 9204 { "(bad)", { XX } },
c0f3af97
L		 9205 },
9206
9207 /* VEX_LEN_3819_P_2_M_0 */
9208 {
d5d7db8e 9209 { "(bad)", { XX } },
9e30b8e0 9210 { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
c0f3af97
L		 9211 },
9212
9213 /* VEX_LEN_381A_P_2_M_0 */
9214 {
d5d7db8e 9215 { "(bad)", { XX } },
9e30b8e0 9216 { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
c0f3af97
L		 9217 },
9218
9219 /* VEX_LEN_381C_P_2 */
9220 {
9e30b8e0 9221 { VEX_W_TABLE (VEX_W_381C_P_2) },
d5d7db8e 9222 { "(bad)", { XX } },
c0f3af97
L		 9223 },
9224
9225 /* VEX_LEN_381D_P_2 */
9226 {
9e30b8e0 9227 { VEX_W_TABLE (VEX_W_381D_P_2) },
d5d7db8e 9228 { "(bad)", { XX } },
c0f3af97
L		 9229 },
9230
9231 /* VEX_LEN_381E_P_2 */
9232 {
9e30b8e0 9233 { VEX_W_TABLE (VEX_W_381E_P_2) },
d5d7db8e 9234 { "(bad)", { XX } },
c0f3af97
L		 9235 },
9236
9237 /* VEX_LEN_3820_P_2 */
9238 {
9e30b8e0 9239 { VEX_W_TABLE (VEX_W_3820_P_2) },
d5d7db8e 9240 { "(bad)", { XX } },
c0f3af97
L		 9241 },
9242
9243 /* VEX_LEN_3821_P_2 */
9244 {
9e30b8e0 9245 { VEX_W_TABLE (VEX_W_3821_P_2) },
d5d7db8e 9246 { "(bad)", { XX } },
c0f3af97
L		 9247 },
9248
9249 /* VEX_LEN_3822_P_2 */
9250 {
9e30b8e0 9251 { VEX_W_TABLE (VEX_W_3822_P_2) },
d5d7db8e 9252 { "(bad)", { XX } },
c0f3af97
L		 9253 },
9254
9255 /* VEX_LEN_3823_P_2 */
9256 {
9e30b8e0 9257 { VEX_W_TABLE (VEX_W_3823_P_2) },
d5d7db8e 9258 { "(bad)", { XX } },
c0f3af97
L		 9259 },
9260
9261 /* VEX_LEN_3824_P_2 */
9262 {
9e30b8e0 9263 { VEX_W_TABLE (VEX_W_3824_P_2) },
d5d7db8e 9264 { "(bad)", { XX } },
c0f3af97
L		 9265 },
9266
9267 /* VEX_LEN_3825_P_2 */
9268 {
9e30b8e0 9269 { VEX_W_TABLE (VEX_W_3825_P_2) },
d5d7db8e 9270 { "(bad)", { XX } },
c0f3af97
L		 9271 },
9272
9273 /* VEX_LEN_3828_P_2 */
9274 {
9e30b8e0 9275 { VEX_W_TABLE (VEX_W_3828_P_2) },
d5d7db8e 9276 { "(bad)", { XX } },
c0f3af97
L		 9277 },
9278
9279 /* VEX_LEN_3829_P_2 */
9280 {
9e30b8e0 9281 { VEX_W_TABLE (VEX_W_3829_P_2) },
d5d7db8e 9282 { "(bad)", { XX } },
c0f3af97
L		 9283 },
9284
9285 /* VEX_LEN_382A_P_2_M_0 */
9286 {
9e30b8e0 9287 { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
d5d7db8e 9288 { "(bad)", { XX } },
c0f3af97
L		 9289 },
9290
9291 /* VEX_LEN_382B_P_2 */
9292 {
9e30b8e0 9293 { VEX_W_TABLE (VEX_W_382B_P_2) },
d5d7db8e 9294 { "(bad)", { XX } },
c0f3af97
L		 9295 },
9296
9297 /* VEX_LEN_3830_P_2 */
9298 {
9e30b8e0 9299 { VEX_W_TABLE (VEX_W_3830_P_2) },
d5d7db8e 9300 { "(bad)", { XX } },
c0f3af97
L		 9301 },
9302
9303 /* VEX_LEN_3831_P_2 */
9304 {
9e30b8e0 9305 { VEX_W_TABLE (VEX_W_3831_P_2) },
d5d7db8e 9306 { "(bad)", { XX } },
c0f3af97
L		 9307 },
9308
9309 /* VEX_LEN_3832_P_2 */
9310 {
9e30b8e0 9311 { VEX_W_TABLE (VEX_W_3832_P_2) },
d5d7db8e 9312 { "(bad)", { XX } },
c0f3af97
L		 9313 },
9314
9315 /* VEX_LEN_3833_P_2 */
9316 {
9e30b8e0 9317 { VEX_W_TABLE (VEX_W_3833_P_2) },
d5d7db8e 9318 { "(bad)", { XX } },
c0f3af97
L		 9319 },
9320
9321 /* VEX_LEN_3834_P_2 */
9322 {
9e30b8e0 9323 { VEX_W_TABLE (VEX_W_3834_P_2) },
d5d7db8e 9324 { "(bad)", { XX } },
c0f3af97
L		 9325 },
9326
9327 /* VEX_LEN_3835_P_2 */
9328 {
9e30b8e0 9329 { VEX_W_TABLE (VEX_W_3835_P_2) },
d5d7db8e 9330 { "(bad)", { XX } },
c0f3af97
L		 9331 },
9332
9333 /* VEX_LEN_3837_P_2 */
9334 {
9e30b8e0 9335 { VEX_W_TABLE (VEX_W_3837_P_2) },
d5d7db8e 9336 { "(bad)", { XX } },
c0f3af97
L		 9337 },
9338
9339 /* VEX_LEN_3838_P_2 */
9340 {
9e30b8e0 9341 { VEX_W_TABLE (VEX_W_3838_P_2) },
d5d7db8e 9342 { "(bad)", { XX } },
c0f3af97
L		 9343 },
9344
9345 /* VEX_LEN_3839_P_2 */
9346 {
9e30b8e0 9347 { VEX_W_TABLE (VEX_W_3839_P_2) },
d5d7db8e 9348 { "(bad)", { XX } },
c0f3af97
L		 9349 },
9350
9351 /* VEX_LEN_383A_P_2 */
9352 {
9e30b8e0 9353 { VEX_W_TABLE (VEX_W_383A_P_2) },
d5d7db8e 9354 { "(bad)", { XX } },
c0f3af97
L		 9355 },
9356
9357 /* VEX_LEN_383B_P_2 */
9358 {
9e30b8e0 9359 { VEX_W_TABLE (VEX_W_383B_P_2) },
d5d7db8e 9360 { "(bad)", { XX } },
c0f3af97
L		 9361 },
9362
9363 /* VEX_LEN_383C_P_2 */
9364 {
9e30b8e0 9365 { VEX_W_TABLE (VEX_W_383C_P_2) },
d5d7db8e 9366 { "(bad)", { XX } },
c0f3af97
L		 9367 },
9368
9369 /* VEX_LEN_383D_P_2 */
9370 {
9e30b8e0 9371 { VEX_W_TABLE (VEX_W_383D_P_2) },
d5d7db8e 9372 { "(bad)", { XX } },
c0f3af97
L		 9373 },
9374
9375 /* VEX_LEN_383E_P_2 */
9376 {
9e30b8e0 9377 { VEX_W_TABLE (VEX_W_383E_P_2) },
d5d7db8e 9378 { "(bad)", { XX } },
c0f3af97
L		 9379 },
9380
9381 /* VEX_LEN_383F_P_2 */
9382 {
9e30b8e0 9383 { VEX_W_TABLE (VEX_W_383F_P_2) },
d5d7db8e 9384 { "(bad)", { XX } },
c0f3af97
L		 9385 },
9386
9387 /* VEX_LEN_3840_P_2 */
9388 {
9e30b8e0 9389 { VEX_W_TABLE (VEX_W_3840_P_2) },
d5d7db8e 9390 { "(bad)", { XX } },
c0f3af97
L		 9391 },
9392
9393 /* VEX_LEN_3841_P_2 */
9394 {
9e30b8e0 9395 { VEX_W_TABLE (VEX_W_3841_P_2) },
d5d7db8e 9396 { "(bad)", { XX } },
c0f3af97
L		 9397 },
9398
a5ff0eb2
L		 9399 /* VEX_LEN_38DB_P_2 */
9400 {
9e30b8e0 9401 { VEX_W_TABLE (VEX_W_38DB_P_2) },
a5ff0eb2
L		 9402 { "(bad)", { XX } },
9403 },
9404
9405 /* VEX_LEN_38DC_P_2 */
9406 {
9e30b8e0 9407 { VEX_W_TABLE (VEX_W_38DC_P_2) },
a5ff0eb2
L		 9408 { "(bad)", { XX } },
9409 },
9410
9411 /* VEX_LEN_38DD_P_2 */
9412 {
9e30b8e0 9413 { VEX_W_TABLE (VEX_W_38DD_P_2) },
a5ff0eb2
L		 9414 { "(bad)", { XX } },
9415 },
9416
9417 /* VEX_LEN_38DE_P_2 */
9418 {
9e30b8e0 9419 { VEX_W_TABLE (VEX_W_38DE_P_2) },
a5ff0eb2
L		 9420 { "(bad)", { XX } },
9421 },
9422
9423 /* VEX_LEN_38DF_P_2 */
9424 {
9e30b8e0 9425 { VEX_W_TABLE (VEX_W_38DF_P_2) },
a5ff0eb2
L		 9426 { "(bad)", { XX } },
9427 },
9428
c0f3af97
L		 9429 /* VEX_LEN_3A06_P_2 */
9430 {
d5d7db8e 9431 { "(bad)", { XX } },
9e30b8e0 9432 { VEX_W_TABLE (VEX_W_3A06_P_2) },
c0f3af97
L		 9433 },
9434
9435 /* VEX_LEN_3A0A_P_2 */
9436 {
9e30b8e0 9437 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
d5d7db8e 9438 { "(bad)", { XX } },
c0f3af97
L		 9439 },
9440
9441 /* VEX_LEN_3A0B_P_2 */
9442 {
9e30b8e0 9443 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
d5d7db8e 9444 { "(bad)", { XX } },
c0f3af97
L		 9445 },
9446
9447 /* VEX_LEN_3A0E_P_2 */
9448 {
9e30b8e0 9449 { VEX_W_TABLE (VEX_W_3A0E_P_2) },
d5d7db8e 9450 { "(bad)", { XX } },
c0f3af97
L		 9451 },
9452
9453 /* VEX_LEN_3A0F_P_2 */
9454 {
9e30b8e0 9455 { VEX_W_TABLE (VEX_W_3A0F_P_2) },
d5d7db8e 9456 { "(bad)", { XX } },
c0f3af97
L		 9457 },
9458
9459 /* VEX_LEN_3A14_P_2 */
9460 {
9e30b8e0 9461 { VEX_W_TABLE (VEX_W_3A14_P_2) },
d5d7db8e 9462 { "(bad)", { XX } },
c0f3af97
L		 9463 },
9464
9465 /* VEX_LEN_3A15_P_2 */
9466 {
9e30b8e0 9467 { VEX_W_TABLE (VEX_W_3A15_P_2) },
d5d7db8e 9468 { "(bad)", { XX } },
c0f3af97
L		 9469 },
9470
9471 /* VEX_LEN_3A16_P_2 */
9472 {
9473 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 9474 { "(bad)", { XX } },
c0f3af97
L		 9475 },
9476
9477 /* VEX_LEN_3A17_P_2 */
9478 {
9479 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 9480 { "(bad)", { XX } },
c0f3af97
L		 9481 },
9482
9483 /* VEX_LEN_3A18_P_2 */
9484 {
d5d7db8e 9485 { "(bad)", { XX } },
9e30b8e0 9486 { VEX_W_TABLE (VEX_W_3A18_P_2) },
c0f3af97
L		 9487 },
9488
9489 /* VEX_LEN_3A19_P_2 */
9490 {
d5d7db8e 9491 { "(bad)", { XX } },
9e30b8e0 9492 { VEX_W_TABLE (VEX_W_3A19_P_2) },
c0f3af97
L		 9493 },
9494
9495 /* VEX_LEN_3A20_P_2 */
9496 {
9e30b8e0 9497 { VEX_W_TABLE (VEX_W_3A20_P_2) },
d5d7db8e 9498 { "(bad)", { XX } },
c0f3af97
L		 9499 },
9500
9501 /* VEX_LEN_3A21_P_2 */
9502 {
9e30b8e0 9503 { VEX_W_TABLE (VEX_W_3A21_P_2) },
d5d7db8e 9504 { "(bad)", { XX } },
c0f3af97
L		 9505 },
9506
9507 /* VEX_LEN_3A22_P_2 */
9508 {
9509 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 9510 { "(bad)", { XX } },
c0f3af97
L		 9511 },
9512
9513 /* VEX_LEN_3A41_P_2 */
9514 {
9e30b8e0 9515 { VEX_W_TABLE (VEX_W_3A41_P_2) },
d5d7db8e 9516 { "(bad)", { XX } },
c0f3af97
L		 9517 },
9518
9519 /* VEX_LEN_3A42_P_2 */
9520 {
9e30b8e0 9521 { VEX_W_TABLE (VEX_W_3A42_P_2) },
d5d7db8e 9522 { "(bad)", { XX } },
c0f3af97
L		 9523 },
9524
ce2f5b3c
L		 9525 /* VEX_LEN_3A44_P_2 */
9526 {
9e30b8e0 9527 { VEX_W_TABLE (VEX_W_3A44_P_2) },
ce2f5b3c
L		 9528 { "(bad)", { XX } },
9529 },
9530
c0f3af97
L		 9531 /* VEX_LEN_3A4C_P_2 */
9532 {
9e30b8e0 9533 { VEX_W_TABLE (VEX_W_3A4C_P_2) },
d5d7db8e 9534 { "(bad)", { XX } },
c0f3af97
L		 9535 },
9536
9537 /* VEX_LEN_3A60_P_2 */
9538 {
9e30b8e0 9539 { VEX_W_TABLE (VEX_W_3A60_P_2) },
d5d7db8e 9540 { "(bad)", { XX } },
c0f3af97
L		 9541 },
9542
9543 /* VEX_LEN_3A61_P_2 */
9544 {
9e30b8e0 9545 { VEX_W_TABLE (VEX_W_3A61_P_2) },
d5d7db8e 9546 { "(bad)", { XX } },
c0f3af97
L		 9547 },
9548
9549 /* VEX_LEN_3A62_P_2 */
9550 {
9e30b8e0 9551 { VEX_W_TABLE (VEX_W_3A62_P_2) },
d5d7db8e 9552 { "(bad)", { XX } },
c0f3af97
L		 9553 },
9554
9555 /* VEX_LEN_3A63_P_2 */
9556 {
9e30b8e0 9557 { VEX_W_TABLE (VEX_W_3A63_P_2) },
d5d7db8e 9558 { "(bad)", { XX } },
c0f3af97
L		 9559 },
9560
922d8de8
DR		 9561 /* VEX_LEN_3A6A_P_2 */
9562 {
206c2556 9563 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9564 { "(bad)", { XX } },
9565 },
9566
9567 /* VEX_LEN_3A6B_P_2 */
9568 {
206c2556 9569 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9570 { "(bad)", { XX } },
9571 },
9572
9573 /* VEX_LEN_3A6E_P_2 */
9574 {
206c2556 9575 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9576 { "(bad)", { XX } },
9577 },
9578
9579 /* VEX_LEN_3A6F_P_2 */
9580 {
206c2556 9581 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9582 { "(bad)", { XX } },
9583 },
9584
9585 /* VEX_LEN_3A7A_P_2 */
9586 {
206c2556 9587 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9588 { "(bad)", { XX } },
9589 },
9590
9591 /* VEX_LEN_3A7B_P_2 */
9592 {
206c2556 9593 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9594 { "(bad)", { XX } },
9595 },
9596
9597 /* VEX_LEN_3A7E_P_2 */
9598 {
206c2556 9599 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9600 { "(bad)", { XX } },
9601 },
9602
9603 /* VEX_LEN_3A7F_P_2 */
9604 {
206c2556 9605 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9606 { "(bad)", { XX } },
9607 },
9608
a5ff0eb2
L		 9609 /* VEX_LEN_3ADF_P_2 */
9610 {
9e30b8e0 9611 { VEX_W_TABLE (VEX_W_3ADF_P_2) },
a5ff0eb2
L		 9612 { "(bad)", { XX } },
9613 },
4c807e72 9614
5dd85c99
SP		 9615 /* VEX_LEN_XOP_09_80 */
9616 {
4c807e72
L		 9617 { "vfrczps", { XM, EXxmm } },
9618 { "vfrczps", { XM, EXymmq } },
5dd85c99 9619 },
4c807e72 9620
5dd85c99
SP		 9621 /* VEX_LEN_XOP_09_81 */
9622 {
4c807e72
L		 9623 { "vfrczpd", { XM, EXxmm } },
9624 { "vfrczpd", { XM, EXymmq } },
5dd85c99 9625 },
331d2d0d
L		 9626};
9627
9e30b8e0 9628static const struct dis386 vex_w_table[][2] = {
b844680a 9629 {
9e30b8e0
L		 9630 /* VEX_W_10_P_0 */
9631 { "vmovups", { XM, EXx } },
d8faab4e
L		 9632 { "(bad)", { XX } },
9633 },
9634 {
9e30b8e0
L		 9635 /* VEX_W_10_P_1 */
9636 { "vmovss", { XMVex, Vex128, EXd } },
9637 { "(bad)", { XX } },
d8faab4e
L		 9638 },
9639 {
9e30b8e0
L		 9640 /* VEX_W_10_P_2 */
9641 { "vmovupd", { XM, EXx } },
9642 { "(bad)", { XX } },
d8faab4e
L		 9643 },
9644 {
9e30b8e0
L		 9645 /* VEX_W_10_P_3 */
9646 { "vmovsd", { XMVex, Vex128, EXq } },
9647 { "(bad)", { XX } },
d8faab4e
L		 9648 },
9649 {
9e30b8e0
L		 9650 /* VEX_W_11_P_0 */
9651 { "vmovups", { EXxS, XM } },
9652 { "(bad)", { XX } },
d8faab4e
L		 9653 },
9654 {
9e30b8e0
L		 9655 /* VEX_W_11_P_1 */
9656 { "vmovss", { EXdVexS, Vex128, XM } },
9657 { "(bad)", { XX } },
b844680a
L		 9658 },
9659 {
9e30b8e0
L		 9660 /* VEX_W_11_P_2 */
9661 { "vmovupd", { EXxS, XM } },
9662 { "(bad)", { XX } },
b844680a
L		 9663 },
9664 {
9e30b8e0
L		 9665 /* VEX_W_11_P_3 */
9666 { "vmovsd", { EXqVexS, Vex128, XM } },
d8faab4e
L		 9667 { "(bad)", { XX } },
9668 },
9669 {
9e30b8e0
L		 9670 /* VEX_W_12_P_0_M_0 */
9671 { "vmovlps", { XM, Vex128, EXq } },
9672 { "(bad)", { XX } },
b844680a
L		 9673 },
9674 {
9e30b8e0
L		 9675 /* VEX_W_12_P_0_M_1 */
9676 { "vmovhlps", { XM, Vex128, EXq } },
b844680a
L		 9677 { "(bad)", { XX } },
9678 },
9679 {
9e30b8e0
L		 9680 /* VEX_W_12_P_1 */
9681 { "vmovsldup", { XM, EXx } },
b844680a 9682 { "(bad)", { XX } },
b844680a
L		 9683 },
9684 {
9e30b8e0
L		 9685 /* VEX_W_12_P_2 */
9686 { "vmovlpd", { XM, Vex128, EXq } },
92fddf8e 9687 { "(bad)", { XX } },
b844680a
L		 9688 },
9689 {
9e30b8e0
L		 9690 /* VEX_W_12_P_3 */
9691 { "vmovddup", { XM, EXymmq } },
92fddf8e 9692 { "(bad)", { XX } },
b844680a
L		 9693 },
9694 {
9e30b8e0
L		 9695 /* VEX_W_13_M_0 */
9696 { "vmovlpX", { EXq, XM } },
b844680a 9697 { "(bad)", { XX } },
b844680a
L		 9698 },
9699 {
9e30b8e0
L		 9700 /* VEX_W_14 */
9701 { "vunpcklpX", { XM, Vex, EXx } },
92fddf8e 9702 { "(bad)", { XX } },
b844680a
L		 9703 },
9704 {
9e30b8e0
L		 9705 /* VEX_W_15 */
9706 { "vunpckhpX", { XM, Vex, EXx } },
92fddf8e 9707 { "(bad)", { XX } },
b844680a
L		 9708 },
9709 {
9e30b8e0
L		 9710 /* VEX_W_16_P_0_M_0 */
9711 { "vmovhps", { XM, Vex128, EXq } },
b844680a 9712 { "(bad)", { XX } },
9e30b8e0
L		 9713 },
9714 {
9715 /* VEX_W_16_P_0_M_1 */
9716 { "vmovlhps", { XM, Vex128, EXq } },
9717 { "(bad)", { XX } },
9718 },
9719 {
9720 /* VEX_W_16_P_1 */
9721 { "vmovshdup", { XM, EXx } },
9722 { "(bad)", { XX } },
9723 },
9724 {
9725 /* VEX_W_16_P_2 */
9726 { "vmovhpd", { XM, Vex128, EXq } },
9727 { "(bad)", { XX } },
9728 },
9729 {
9730 /* VEX_W_17_M_0 */
9731 { "vmovhpX", { EXq, XM } },
9732 { "(bad)", { XX } },
9733 },
9734 {
9735 /* VEX_W_28 */
9736 { "vmovapX", { XM, EXx } },
9737 { "(bad)", { XX } },
9738 },
9739 {
9740 /* VEX_W_29 */
9741 { "vmovapX", { EXxS, XM } },
9742 { "(bad)", { XX } },
9743 },
9744 {
9745 /* VEX_W_2B_M_0 */
9746 { "vmovntpX", { Mx, XM } },
9747 { "(bad)", { XX } },
9748 },
9749 {
9750 /* VEX_W_2E_P_0 */
9751 { "vucomiss", { XM, EXd } },
9752 { "(bad)", { XX } },
9753 },
9754 {
9755 /* VEX_W_2E_P_2 */
9756 { "vucomisd", { XM, EXq } },
9757 { "(bad)", { XX } },
9758 },
9759 {
9760 /* VEX_W_2F_P_0 */
9761 { "vcomiss", { XM, EXd } },
9762 { "(bad)", { XX } },
9763 },
9764 {
9765 /* VEX_W_2F_P_2 */
9766 { "vcomisd", { XM, EXq } },
9767 { "(bad)", { XX } },
9768 },
9769 {
9770 /* VEX_W_50_M_0 */
9771 { "vmovmskpX", { Gdq, XS } },
9772 { "(bad)", { XX } },
9773 },
9774 {
9775 /* VEX_W_51_P_0 */
9776 { "vsqrtps", { XM, EXx } },
9777 { "(bad)", { XX } },
9778 },
9779 {
9780 /* VEX_W_51_P_1 */
9781 { "vsqrtss", { XM, Vex128, EXd } },
9782 { "(bad)", { XX } },
9783 },
9784 {
9785 /* VEX_W_51_P_2 */
9786 { "vsqrtpd", { XM, EXx } },
9787 { "(bad)", { XX } },
9788 },
9789 {
9790 /* VEX_W_51_P_3 */
9791 { "vsqrtsd", { XM, Vex128, EXq } },
9792 { "(bad)", { XX } },
9793 },
9794 {
9795 /* VEX_W_52_P_0 */
9796 { "vrsqrtps", { XM, EXx } },
9797 { "(bad)", { XX } },
9798 },
9799 {
9800 /* VEX_W_52_P_1 */
9801 { "vrsqrtss", { XM, Vex128, EXd } },
9802 { "(bad)", { XX } },
9803 },
9804 {
9805 /* VEX_W_53_P_0 */
9806 { "vrcpps", { XM, EXx } },
9807 { "(bad)", { XX } },
9808 },
9809 {
9810 /* VEX_W_53_P_1 */
9811 { "vrcpss", { XM, Vex128, EXd } },
9812 { "(bad)", { XX } },
9813 },
9814 {
9815 /* VEX_W_58_P_0 */
9816 { "vaddps", { XM, Vex, EXx } },
9817 { "(bad)", { XX } },
9818 },
9819 {
9820 /* VEX_W_58_P_1 */
9821 { "vaddss", { XM, Vex128, EXd } },
9822 { "(bad)", { XX } },
9823 },
9824 {
9825 /* VEX_W_58_P_2 */
9826 { "vaddpd", { XM, Vex, EXx } },
9827 { "(bad)", { XX } },
9828 },
9829 {
9830 /* VEX_W_58_P_3 */
9831 { "vaddsd", { XM, Vex128, EXq } },
9832 { "(bad)", { XX } },
9833 },
9834 {
9835 /* VEX_W_59_P_0 */
9836 { "vmulps", { XM, Vex, EXx } },
9837 { "(bad)", { XX } },
9838 },
9839 {
9840 /* VEX_W_59_P_1 */
9841 { "vmulss", { XM, Vex128, EXd } },
9842 { "(bad)", { XX } },
9843 },
9844 {
9845 /* VEX_W_59_P_2 */
9846 { "vmulpd", { XM, Vex, EXx } },
9847 { "(bad)", { XX } },
9848 },
9849 {
9850 /* VEX_W_59_P_3 */
9851 { "vmulsd", { XM, Vex128, EXq } },
9852 { "(bad)", { XX } },
9853 },
9854 {
9855 /* VEX_W_5A_P_0 */
9856 { "vcvtps2pd", { XM, EXxmmq } },
9857 { "(bad)", { XX } },
9858 },
9859 {
9860 /* VEX_W_5A_P_1 */
9861 { "vcvtss2sd", { XM, Vex128, EXd } },
9862 { "(bad)", { XX } },
9863 },
9864 {
9865 /* VEX_W_5A_P_3 */
9866 { "vcvtsd2ss", { XM, Vex128, EXq } },
9867 { "(bad)", { XX } },
9868 },
9869 {
9870 /* VEX_W_5B_P_0 */
9871 { "vcvtdq2ps", { XM, EXx } },
9872 { "(bad)", { XX } },
9873 },
9874 {
9875 /* VEX_W_5B_P_1 */
9876 { "vcvttps2dq", { XM, EXx } },
9877 { "(bad)", { XX } },
9878 },
9879 {
9880 /* VEX_W_5B_P_2 */
9881 { "vcvtps2dq", { XM, EXx } },
9882 { "(bad)", { XX } },
9883 },
9884 {
9885 /* VEX_W_5C_P_0 */
9886 { "vsubps", { XM, Vex, EXx } },
9887 { "(bad)", { XX } },
9888 },
9889 {
9890 /* VEX_W_5C_P_1 */
9891 { "vsubss", { XM, Vex128, EXd } },
9892 { "(bad)", { XX } },
9893 },
9894 {
9895 /* VEX_W_5C_P_2 */
9896 { "vsubpd", { XM, Vex, EXx } },
9897 { "(bad)", { XX } },
9898 },
9899 {
9900 /* VEX_W_5C_P_3 */
9901 { "vsubsd", { XM, Vex128, EXq } },
9902 { "(bad)", { XX } },
9903 },
9904 {
9905 /* VEX_W_5D_P_0 */
9906 { "vminps", { XM, Vex, EXx } },
9907 { "(bad)", { XX } },
9908 },
9909 {
9910 /* VEX_W_5D_P_1 */
9911 { "vminss", { XM, Vex128, EXd } },
9912 { "(bad)", { XX } },
9913 },
9914 {
9915 /* VEX_W_5D_P_2 */
9916 { "vminpd", { XM, Vex, EXx } },
9917 { "(bad)", { XX } },
9918 },
9919 {
9920 /* VEX_W_5D_P_3 */
9921 { "vminsd", { XM, Vex128, EXq } },
9922 { "(bad)", { XX } },
9923 },
9924 {
9925 /* VEX_W_5E_P_0 */
9926 { "vdivps", { XM, Vex, EXx } },
9927 { "(bad)", { XX } },
9928 },
9929 {
9930 /* VEX_W_5E_P_1 */
9931 { "vdivss", { XM, Vex128, EXd } },
9932 { "(bad)", { XX } },
9933 },
9934 {
9935 /* VEX_W_5E_P_2 */
9936 { "vdivpd", { XM, Vex, EXx } },
9937 { "(bad)", { XX } },
9938 },
9939 {
9940 /* VEX_W_5E_P_3 */
9941 { "vdivsd", { XM, Vex128, EXq } },
9942 { "(bad)", { XX } },
9943 },
9944 {
9945 /* VEX_W_5F_P_0 */
9946 { "vmaxps", { XM, Vex, EXx } },
9947 { "(bad)", { XX } },
9948 },
9949 {
9950 /* VEX_W_5F_P_1 */
9951 { "vmaxss", { XM, Vex128, EXd } },
9952 { "(bad)", { XX } },
9953 },
9954 {
9955 /* VEX_W_5F_P_2 */
9956 { "vmaxpd", { XM, Vex, EXx } },
9957 { "(bad)", { XX } },
9958 },
9959 {
9960 /* VEX_W_5F_P_3 */
9961 { "vmaxsd", { XM, Vex128, EXq } },
9962 { "(bad)", { XX } },
9963 },
9964 {
9965 /* VEX_W_60_P_2 */
9966 { "vpunpcklbw", { XM, Vex128, EXx } },
9967 { "(bad)", { XX } },
9968 },
9969 {
9970 /* VEX_W_61_P_2 */
9971 { "vpunpcklwd", { XM, Vex128, EXx } },
9972 { "(bad)", { XX } },
9973 },
9974 {
9975 /* VEX_W_62_P_2 */
9976 { "vpunpckldq", { XM, Vex128, EXx } },
9977 { "(bad)", { XX } },
9978 },
9979 {
9980 /* VEX_W_63_P_2 */
9981 { "vpacksswb", { XM, Vex128, EXx } },
9982 { "(bad)", { XX } },
9983 },
9984 {
9985 /* VEX_W_64_P_2 */
9986 { "vpcmpgtb", { XM, Vex128, EXx } },
9987 { "(bad)", { XX } },
9988 },
9989 {
9990 /* VEX_W_65_P_2 */
9991 { "vpcmpgtw", { XM, Vex128, EXx } },
9992 { "(bad)", { XX } },
9993 },
9994 {
9995 /* VEX_W_66_P_2 */
9996 { "vpcmpgtd", { XM, Vex128, EXx } },
9997 { "(bad)", { XX } },
9998 },
9999 {
10000 /* VEX_W_67_P_2 */
10001 { "vpackuswb", { XM, Vex128, EXx } },
10002 { "(bad)", { XX } },
10003 },
10004 {
10005 /* VEX_W_68_P_2 */
10006 { "vpunpckhbw", { XM, Vex128, EXx } },
10007 { "(bad)", { XX } },
10008 },
10009 {
10010 /* VEX_W_69_P_2 */
10011 { "vpunpckhwd", { XM, Vex128, EXx } },
10012 { "(bad)", { XX } },
10013 },
10014 {
10015 /* VEX_W_6A_P_2 */
10016 { "vpunpckhdq", { XM, Vex128, EXx } },
10017 { "(bad)", { XX } },
10018 },
10019 {
10020 /* VEX_W_6B_P_2 */
10021 { "vpackssdw", { XM, Vex128, EXx } },
10022 { "(bad)", { XX } },
10023 },
10024 {
10025 /* VEX_W_6C_P_2 */
10026 { "vpunpcklqdq", { XM, Vex128, EXx } },
10027 { "(bad)", { XX } },
10028 },
10029 {
10030 /* VEX_W_6D_P_2 */
10031 { "vpunpckhqdq", { XM, Vex128, EXx } },
10032 { "(bad)", { XX } },
10033 },
10034 {
10035 /* VEX_W_6F_P_1 */
efdb52b7 10036 { "vmovdqu", { XM, EXx } },
9e30b8e0
L		 10037 { "(bad)", { XX } },
10038 },
10039 {
10040 /* VEX_W_6F_P_2 */
efdb52b7 10041 { "vmovdqa", { XM, EXx } },
9e30b8e0
L		 10042 { "(bad)", { XX } },
10043 },
10044 {
10045 /* VEX_W_70_P_1 */
10046 { "vpshufhw", { XM, EXx, Ib } },
10047 { "(bad)", { XX } },
10048 },
10049 {
10050 /* VEX_W_70_P_2 */
10051 { "vpshufd", { XM, EXx, Ib } },
10052 { "(bad)", { XX } },
10053 },
10054 {
10055 /* VEX_W_70_P_3 */
10056 { "vpshuflw", { XM, EXx, Ib } },
10057 { "(bad)", { XX } },
10058 },
10059 {
10060 /* VEX_W_71_R_2_P_2 */
10061 { "vpsrlw", { Vex128, XS, Ib } },
10062 { "(bad)", { XX } },
10063 },
10064 {
10065 /* VEX_W_71_R_4_P_2 */
10066 { "vpsraw", { Vex128, XS, Ib } },
10067 { "(bad)", { XX } },
10068 },
10069 {
10070 /* VEX_W_71_R_6_P_2 */
10071 { "vpsllw", { Vex128, XS, Ib } },
10072 { "(bad)", { XX } },
10073 },
10074 {
10075 /* VEX_W_72_R_2_P_2 */
10076 { "vpsrld", { Vex128, XS, Ib } },
10077 { "(bad)", { XX } },
10078 },
10079 {
10080 /* VEX_W_72_R_4_P_2 */
10081 { "vpsrad", { Vex128, XS, Ib } },
10082 { "(bad)", { XX } },
10083 },
10084 {
10085 /* VEX_W_72_R_6_P_2 */
10086 { "vpslld", { Vex128, XS, Ib } },
10087 { "(bad)", { XX } },
10088 },
10089 {
10090 /* VEX_W_73_R_2_P_2 */
10091 { "vpsrlq", { Vex128, XS, Ib } },
10092 { "(bad)", { XX } },
10093 },
10094 {
10095 /* VEX_W_73_R_3_P_2 */
10096 { "vpsrldq", { Vex128, XS, Ib } },
10097 { "(bad)", { XX } },
10098 },
10099 {
10100 /* VEX_W_73_R_6_P_2 */
10101 { "vpsllq", { Vex128, XS, Ib } },
10102 { "(bad)", { XX } },
10103 },
10104 {
10105 /* VEX_W_73_R_7_P_2 */
10106 { "vpslldq", { Vex128, XS, Ib } },
10107 { "(bad)", { XX } },
10108 },
10109 {
10110 /* VEX_W_74_P_2 */
10111 { "vpcmpeqb", { XM, Vex128, EXx } },
10112 { "(bad)", { XX } },
10113 },
10114 {
10115 /* VEX_W_75_P_2 */
10116 { "vpcmpeqw", { XM, Vex128, EXx } },
10117 { "(bad)", { XX } },
10118 },
10119 {
10120 /* VEX_W_76_P_2 */
10121 { "vpcmpeqd", { XM, Vex128, EXx } },
10122 { "(bad)", { XX } },
10123 },
10124 {
10125 /* VEX_W_77_P_0 */
10126 { "", { VZERO } },
10127 { "(bad)", { XX } },
10128 },
10129 {
10130 /* VEX_W_7C_P_2 */
10131 { "vhaddpd", { XM, Vex, EXx } },
10132 { "(bad)", { XX } },
10133 },
10134 {
10135 /* VEX_W_7C_P_3 */
10136 { "vhaddps", { XM, Vex, EXx } },
10137 { "(bad)", { XX } },
10138 },
10139 {
10140 /* VEX_W_7D_P_2 */
10141 { "vhsubpd", { XM, Vex, EXx } },
10142 { "(bad)", { XX } },
10143 },
10144 {
10145 /* VEX_W_7D_P_3 */
10146 { "vhsubps", { XM, Vex, EXx } },
10147 { "(bad)", { XX } },
10148 },
10149 {
10150 /* VEX_W_7E_P_1 */
10151 { "vmovq", { XM, EXq } },
10152 { "(bad)", { XX } },
10153 },
10154 {
10155 /* VEX_W_7F_P_1 */
10156 { "vmovdqu", { EXxS, XM } },
10157 { "(bad)", { XX } },
10158 },
10159 {
10160 /* VEX_W_7F_P_2 */
10161 { "vmovdqa", { EXxS, XM } },
10162 { "(bad)", { XX } },
10163 },
10164 {
10165 /* VEX_W_AE_R_2_M_0 */
10166 { "vldmxcsr", { Md } },
10167 { "(bad)", { XX } },
10168 },
10169 {
10170 /* VEX_W_AE_R_3_M_0 */
10171 { "vstmxcsr", { Md } },
10172 { "(bad)", { XX } },
10173 },
10174 {
10175 /* VEX_W_C2_P_0 */
10176 { "vcmpps", { XM, Vex, EXx, VCMP } },
10177 { "(bad)", { XX } },
10178 },
10179 {
10180 /* VEX_W_C2_P_1 */
10181 { "vcmpss", { XM, Vex128, EXd, VCMP } },
10182 { "(bad)", { XX } },
10183 },
10184 {
10185 /* VEX_W_C2_P_2 */
10186 { "vcmppd", { XM, Vex, EXx, VCMP } },
10187 { "(bad)", { XX } },
10188 },
10189 {
10190 /* VEX_W_C2_P_3 */
10191 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
10192 { "(bad)", { XX } },
10193 },
10194 {
10195 /* VEX_W_C4_P_2 */
10196 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10197 { "(bad)", { XX } },
10198 },
10199 {
10200 /* VEX_W_C5_P_2 */
10201 { "vpextrw", { Gdq, XS, Ib } },
10202 { "(bad)", { XX } },
10203 },
10204 {
10205 /* VEX_W_D0_P_2 */
10206 { "vaddsubpd", { XM, Vex, EXx } },
10207 { "(bad)", { XX } },
10208 },
10209 {
10210 /* VEX_W_D0_P_3 */
10211 { "vaddsubps", { XM, Vex, EXx } },
10212 { "(bad)", { XX } },
10213 },
10214 {
10215 /* VEX_W_D1_P_2 */
10216 { "vpsrlw", { XM, Vex128, EXx } },
10217 { "(bad)", { XX } },
10218 },
10219 {
10220 /* VEX_W_D2_P_2 */
10221 { "vpsrld", { XM, Vex128, EXx } },
10222 { "(bad)", { XX } },
10223 },
10224 {
10225 /* VEX_W_D3_P_2 */
10226 { "vpsrlq", { XM, Vex128, EXx } },
10227 { "(bad)", { XX } },
10228 },
10229 {
10230 /* VEX_W_D4_P_2 */
10231 { "vpaddq", { XM, Vex128, EXx } },
10232 { "(bad)", { XX } },
10233 },
10234 {
10235 /* VEX_W_D5_P_2 */
10236 { "vpmullw", { XM, Vex128, EXx } },
10237 { "(bad)", { XX } },
10238 },
10239 {
10240 /* VEX_W_D6_P_2 */
10241 { "vmovq", { EXqS, XM } },
10242 { "(bad)", { XX } },
10243 },
10244 {
10245 /* VEX_W_D7_P_2_M_1 */
10246 { "vpmovmskb", { Gdq, XS } },
10247 { "(bad)", { XX } },
10248 },
10249 {
10250 /* VEX_W_D8_P_2 */
10251 { "vpsubusb", { XM, Vex128, EXx } },
10252 { "(bad)", { XX } },
10253 },
10254 {
10255 /* VEX_W_D9_P_2 */
10256 { "vpsubusw", { XM, Vex128, EXx } },
10257 { "(bad)", { XX } },
10258 },
10259 {
10260 /* VEX_W_DA_P_2 */
10261 { "vpminub", { XM, Vex128, EXx } },
10262 { "(bad)", { XX } },
10263 },
10264 {
10265 /* VEX_W_DB_P_2 */
10266 { "vpand", { XM, Vex128, EXx } },
10267 { "(bad)", { XX } },
10268 },
10269 {
10270 /* VEX_W_DC_P_2 */
10271 { "vpaddusb", { XM, Vex128, EXx } },
10272 { "(bad)", { XX } },
10273 },
10274 {
10275 /* VEX_W_DD_P_2 */
10276 { "vpaddusw", { XM, Vex128, EXx } },
10277 { "(bad)", { XX } },
10278 },
10279 {
10280 /* VEX_W_DE_P_2 */
10281 { "vpmaxub", { XM, Vex128, EXx } },
10282 { "(bad)", { XX } },
10283 },
10284 {
10285 /* VEX_W_DF_P_2 */
10286 { "vpandn", { XM, Vex128, EXx } },
10287 { "(bad)", { XX } },
10288 },
10289 {
10290 /* VEX_W_E0_P_2 */
10291 { "vpavgb", { XM, Vex128, EXx } },
10292 { "(bad)", { XX } },
10293 },
10294 {
10295 /* VEX_W_E1_P_2 */
10296 { "vpsraw", { XM, Vex128, EXx } },
10297 { "(bad)", { XX } },
10298 },
10299 {
10300 /* VEX_W_E2_P_2 */
10301 { "vpsrad", { XM, Vex128, EXx } },
10302 { "(bad)", { XX } },
10303 },
10304 {
10305 /* VEX_W_E3_P_2 */
10306 { "vpavgw", { XM, Vex128, EXx } },
10307 { "(bad)", { XX } },
10308 },
10309 {
10310 /* VEX_W_E4_P_2 */
10311 { "vpmulhuw", { XM, Vex128, EXx } },
10312 { "(bad)", { XX } },
10313 },
10314 {
10315 /* VEX_W_E5_P_2 */
10316 { "vpmulhw", { XM, Vex128, EXx } },
10317 { "(bad)", { XX } },
10318 },
10319 {
10320 /* VEX_W_E6_P_1 */
efdb52b7 10321 { "vcvtdq2pd", { XM, EXxmmq } },
9e30b8e0
L		 10322 { "(bad)", { XX } },
10323 },
10324 {
10325 /* VEX_W_E6_P_2 */
a179a9fd 10326 { "vcvttpd2dq%XY", { XMM, EXx } },
9e30b8e0
L		 10327 { "(bad)", { XX } },
10328 },
10329 {
10330 /* VEX_W_E6_P_3 */
a179a9fd 10331 { "vcvtpd2dq%XY", { XMM, EXx } },
9e30b8e0
L		 10332 { "(bad)", { XX } },
10333 },
10334 {
10335 /* VEX_W_E7_P_2_M_0 */
10336 { "vmovntdq", { Mx, XM } },
10337 { "(bad)", { XX } },
10338 },
10339 {
10340 /* VEX_W_E8_P_2 */
10341 { "vpsubsb", { XM, Vex128, EXx } },
10342 { "(bad)", { XX } },
10343 },
10344 {
10345 /* VEX_W_E9_P_2 */
10346 { "vpsubsw", { XM, Vex128, EXx } },
10347 { "(bad)", { XX } },
10348 },
10349 {
10350 /* VEX_W_EA_P_2 */
10351 { "vpminsw", { XM, Vex128, EXx } },
10352 { "(bad)", { XX } },
10353 },
10354 {
10355 /* VEX_W_EB_P_2 */
10356 { "vpor", { XM, Vex128, EXx } },
10357 { "(bad)", { XX } },
10358 },
10359 {
10360 /* VEX_W_EC_P_2 */
10361 { "vpaddsb", { XM, Vex128, EXx } },
10362 { "(bad)", { XX } },
10363 },
10364 {
10365 /* VEX_W_ED_P_2 */
10366 { "vpaddsw", { XM, Vex128, EXx } },
10367 { "(bad)", { XX } },
10368 },
10369 {
10370 /* VEX_W_EE_P_2 */
10371 { "vpmaxsw", { XM, Vex128, EXx } },
10372 { "(bad)", { XX } },
10373 },
10374 {
10375 /* VEX_W_EF_P_2 */
10376 { "vpxor", { XM, Vex128, EXx } },
10377 { "(bad)", { XX } },
10378 },
10379 {
10380 /* VEX_W_F0_P_3_M_0 */
10381 { "vlddqu", { XM, M } },
10382 { "(bad)", { XX } },
10383 },
10384 {
10385 /* VEX_W_F1_P_2 */
10386 { "vpsllw", { XM, Vex128, EXx } },
10387 { "(bad)", { XX } },
10388 },
10389 {
10390 /* VEX_W_F2_P_2 */
10391 { "vpslld", { XM, Vex128, EXx } },
10392 { "(bad)", { XX } },
10393 },
10394 {
10395 /* VEX_W_F3_P_2 */
10396 { "vpsllq", { XM, Vex128, EXx } },
10397 { "(bad)", { XX } },
10398 },
10399 {
10400 /* VEX_W_F4_P_2 */
10401 { "vpmuludq", { XM, Vex128, EXx } },
10402 { "(bad)", { XX } },
10403 },
10404 {
10405 /* VEX_W_F5_P_2 */
10406 { "vpmaddwd", { XM, Vex128, EXx } },
10407 { "(bad)", { XX } },
10408 },
10409 {
10410 /* VEX_W_F6_P_2 */
10411 { "vpsadbw", { XM, Vex128, EXx } },
10412 { "(bad)", { XX } },
10413 },
10414 {
10415 /* VEX_W_F7_P_2 */
10416 { "vmaskmovdqu", { XM, XS } },
10417 { "(bad)", { XX } },
10418 },
10419 {
10420 /* VEX_W_F8_P_2 */
10421 { "vpsubb", { XM, Vex128, EXx } },
10422 { "(bad)", { XX } },
10423 },
10424 {
10425 /* VEX_W_F9_P_2 */
10426 { "vpsubw", { XM, Vex128, EXx } },
10427 { "(bad)", { XX } },
10428 },
10429 {
10430 /* VEX_W_FA_P_2 */
10431 { "vpsubd", { XM, Vex128, EXx } },
10432 { "(bad)", { XX } },
10433 },
10434 {
10435 /* VEX_W_FB_P_2 */
10436 { "vpsubq", { XM, Vex128, EXx } },
10437 { "(bad)", { XX } },
10438 },
10439 {
10440 /* VEX_W_FC_P_2 */
10441 { "vpaddb", { XM, Vex128, EXx } },
10442 { "(bad)", { XX } },
10443 },
10444 {
10445 /* VEX_W_FD_P_2 */
10446 { "vpaddw", { XM, Vex128, EXx } },
10447 { "(bad)", { XX } },
10448 },
10449 {
10450 /* VEX_W_FE_P_2 */
10451 { "vpaddd", { XM, Vex128, EXx } },
10452 { "(bad)", { XX } },
10453 },
10454 {
10455 /* VEX_W_3800_P_2 */
10456 { "vpshufb", { XM, Vex128, EXx } },
10457 { "(bad)", { XX } },
10458 },
10459 {
10460 /* VEX_W_3801_P_2 */
10461 { "vphaddw", { XM, Vex128, EXx } },
10462 { "(bad)", { XX } },
10463 },
10464 {
10465 /* VEX_W_3802_P_2 */
10466 { "vphaddd", { XM, Vex128, EXx } },
10467 { "(bad)", { XX } },
10468 },
10469 {
10470 /* VEX_W_3803_P_2 */
10471 { "vphaddsw", { XM, Vex128, EXx } },
10472 { "(bad)", { XX } },
10473 },
10474 {
10475 /* VEX_W_3804_P_2 */
10476 { "vpmaddubsw", { XM, Vex128, EXx } },
10477 { "(bad)", { XX } },
10478 },
10479 {
10480 /* VEX_W_3805_P_2 */
10481 { "vphsubw", { XM, Vex128, EXx } },
10482 { "(bad)", { XX } },
10483 },
10484 {
10485 /* VEX_W_3806_P_2 */
10486 { "vphsubd", { XM, Vex128, EXx } },
10487 { "(bad)", { XX } },
10488 },
10489 {
10490 /* VEX_W_3807_P_2 */
10491 { "vphsubsw", { XM, Vex128, EXx } },
10492 { "(bad)", { XX } },
10493 },
10494 {
10495 /* VEX_W_3808_P_2 */
10496 { "vpsignb", { XM, Vex128, EXx } },
10497 { "(bad)", { XX } },
10498 },
10499 {
10500 /* VEX_W_3809_P_2 */
10501 { "vpsignw", { XM, Vex128, EXx } },
10502 { "(bad)", { XX } },
10503 },
10504 {
10505 /* VEX_W_380A_P_2 */
10506 { "vpsignd", { XM, Vex128, EXx } },
10507 { "(bad)", { XX } },
10508 },
10509 {
10510 /* VEX_W_380B_P_2 */
10511 { "vpmulhrsw", { XM, Vex128, EXx } },
10512 { "(bad)", { XX } },
10513 },
10514 {
10515 /* VEX_W_380C_P_2 */
10516 { "vpermilps", { XM, Vex, EXx } },
10517 { "(bad)", { XX } },
10518 },
10519 {
10520 /* VEX_W_380D_P_2 */
10521 { "vpermilpd", { XM, Vex, EXx } },
10522 { "(bad)", { XX } },
10523 },
10524 {
10525 /* VEX_W_380E_P_2 */
10526 { "vtestps", { XM, EXx } },
10527 { "(bad)", { XX } },
10528 },
10529 {
10530 /* VEX_W_380F_P_2 */
10531 { "vtestpd", { XM, EXx } },
10532 { "(bad)", { XX } },
10533 },
10534 {
10535 /* VEX_W_3817_P_2 */
10536 { "vptest", { XM, EXx } },
10537 { "(bad)", { XX } },
10538 },
10539 {
10540 /* VEX_W_3819_P_2_M_0 */
10541 { "vbroadcastsd", { XM, Mq } },
10542 { "(bad)", { XX } },
10543 },
10544 {
10545 /* VEX_W_381A_P_2_M_0 */
10546 { "vbroadcastf128", { XM, Mxmm } },
10547 { "(bad)", { XX } },
10548 },
10549 {
10550 /* VEX_W_381C_P_2 */
10551 { "vpabsb", { XM, EXx } },
10552 { "(bad)", { XX } },
10553 },
10554 {
10555 /* VEX_W_381D_P_2 */
10556 { "vpabsw", { XM, EXx } },
10557 { "(bad)", { XX } },
10558 },
10559 {
10560 /* VEX_W_381E_P_2 */
10561 { "vpabsd", { XM, EXx } },
10562 { "(bad)", { XX } },
10563 },
10564 {
10565 /* VEX_W_3820_P_2 */
10566 { "vpmovsxbw", { XM, EXq } },
10567 { "(bad)", { XX } },
10568 },
10569 {
10570 /* VEX_W_3821_P_2 */
10571 { "vpmovsxbd", { XM, EXd } },
10572 { "(bad)", { XX } },
10573 },
10574 {
10575 /* VEX_W_3822_P_2 */
10576 { "vpmovsxbq", { XM, EXw } },
10577 { "(bad)", { XX } },
10578 },
10579 {
10580 /* VEX_W_3823_P_2 */
10581 { "vpmovsxwd", { XM, EXq } },
10582 { "(bad)", { XX } },
10583 },
10584 {
10585 /* VEX_W_3824_P_2 */
10586 { "vpmovsxwq", { XM, EXd } },
10587 { "(bad)", { XX } },
10588 },
10589 {
10590 /* VEX_W_3825_P_2 */
10591 { "vpmovsxdq", { XM, EXq } },
10592 { "(bad)", { XX } },
10593 },
10594 {
10595 /* VEX_W_3828_P_2 */
10596 { "vpmuldq", { XM, Vex128, EXx } },
10597 { "(bad)", { XX } },
10598 },
10599 {
10600 /* VEX_W_3829_P_2 */
10601 { "vpcmpeqq", { XM, Vex128, EXx } },
10602 { "(bad)", { XX } },
10603 },
10604 {
10605 /* VEX_W_382A_P_2_M_0 */
10606 { "vmovntdqa", { XM, Mx } },
10607 { "(bad)", { XX } },
10608 },
10609 {
10610 /* VEX_W_382B_P_2 */
10611 { "vpackusdw", { XM, Vex128, EXx } },
10612 { "(bad)", { XX } },
10613 },
53aa04a0
L		 10614 {
10615 /* VEX_W_382C_P_2_M_0 */
10616 { "vmaskmovps", { XM, Vex, Mx } },
10617 { "(bad)", { XX } },
10618 },
10619 {
10620 /* VEX_W_382D_P_2_M_0 */
10621 { "vmaskmovpd", { XM, Vex, Mx } },
10622 { "(bad)", { XX } },
10623 },
10624 {
10625 /* VEX_W_382E_P_2_M_0 */
10626 { "vmaskmovps", { Mx, Vex, XM } },
10627 { "(bad)", { XX } },
10628 },
10629 {
10630 /* VEX_W_382F_P_2_M_0 */
10631 { "vmaskmovpd", { Mx, Vex, XM } },
10632 { "(bad)", { XX } },
10633 },
9e30b8e0
L		 10634 {
10635 /* VEX_W_3830_P_2 */
10636 { "vpmovzxbw", { XM, EXq } },
10637 { "(bad)", { XX } },
10638 },
10639 {
10640 /* VEX_W_3831_P_2 */
10641 { "vpmovzxbd", { XM, EXd } },
10642 { "(bad)", { XX } },
10643 },
10644 {
10645 /* VEX_W_3832_P_2 */
10646 { "vpmovzxbq", { XM, EXw } },
10647 { "(bad)", { XX } },
10648 },
10649 {
10650 /* VEX_W_3833_P_2 */
10651 { "vpmovzxwd", { XM, EXq } },
10652 { "(bad)", { XX } },
10653 },
10654 {
10655 /* VEX_W_3834_P_2 */
10656 { "vpmovzxwq", { XM, EXd } },
10657 { "(bad)", { XX } },
10658 },
10659 {
10660 /* VEX_W_3835_P_2 */
10661 { "vpmovzxdq", { XM, EXq } },
10662 { "(bad)", { XX } },
10663 },
10664 {
10665 /* VEX_W_3837_P_2 */
10666 { "vpcmpgtq", { XM, Vex128, EXx } },
10667 { "(bad)", { XX } },
10668 },
10669 {
10670 /* VEX_W_3838_P_2 */
10671 { "vpminsb", { XM, Vex128, EXx } },
10672 { "(bad)", { XX } },
10673 },
10674 {
10675 /* VEX_W_3839_P_2 */
10676 { "vpminsd", { XM, Vex128, EXx } },
10677 { "(bad)", { XX } },
10678 },
10679 {
10680 /* VEX_W_383A_P_2 */
10681 { "vpminuw", { XM, Vex128, EXx } },
10682 { "(bad)", { XX } },
10683 },
10684 {
10685 /* VEX_W_383B_P_2 */
10686 { "vpminud", { XM, Vex128, EXx } },
10687 { "(bad)", { XX } },
10688 },
10689 {
10690 /* VEX_W_383C_P_2 */
10691 { "vpmaxsb", { XM, Vex128, EXx } },
10692 { "(bad)", { XX } },
10693 },
10694 {
10695 /* VEX_W_383D_P_2 */
10696 { "vpmaxsd", { XM, Vex128, EXx } },
10697 { "(bad)", { XX } },
10698 },
10699 {
10700 /* VEX_W_383E_P_2 */
10701 { "vpmaxuw", { XM, Vex128, EXx } },
10702 { "(bad)", { XX } },
10703 },
10704 {
10705 /* VEX_W_383F_P_2 */
10706 { "vpmaxud", { XM, Vex128, EXx } },
10707 { "(bad)", { XX } },
10708 },
10709 {
10710 /* VEX_W_3840_P_2 */
10711 { "vpmulld", { XM, Vex128, EXx } },
10712 { "(bad)", { XX } },
10713 },
10714 {
10715 /* VEX_W_3841_P_2 */
10716 { "vphminposuw", { XM, EXx } },
10717 { "(bad)", { XX } },
10718 },
10719 {
10720 /* VEX_W_38DB_P_2 */
10721 { "vaesimc", { XM, EXx } },
10722 { "(bad)", { XX } },
10723 },
10724 {
10725 /* VEX_W_38DC_P_2 */
10726 { "vaesenc", { XM, Vex128, EXx } },
10727 { "(bad)", { XX } },
10728 },
10729 {
10730 /* VEX_W_38DD_P_2 */
10731 { "vaesenclast", { XM, Vex128, EXx } },
10732 { "(bad)", { XX } },
10733 },
10734 {
10735 /* VEX_W_38DE_P_2 */
10736 { "vaesdec", { XM, Vex128, EXx } },
10737 { "(bad)", { XX } },
10738 },
10739 {
10740 /* VEX_W_38DF_P_2 */
10741 { "vaesdeclast", { XM, Vex128, EXx } },
10742 { "(bad)", { XX } },
10743 },
10744 {
10745 /* VEX_W_3A04_P_2 */
10746 { "vpermilps", { XM, EXx, Ib } },
10747 { "(bad)", { XX } },
10748 },
10749 {
10750 /* VEX_W_3A05_P_2 */
10751 { "vpermilpd", { XM, EXx, Ib } },
10752 { "(bad)", { XX } },
10753 },
10754 {
10755 /* VEX_W_3A06_P_2 */
10756 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10757 { "(bad)", { XX } },
10758 },
10759 {
10760 /* VEX_W_3A08_P_2 */
10761 { "vroundps", { XM, EXx, Ib } },
10762 { "(bad)", { XX } },
10763 },
10764 {
10765 /* VEX_W_3A09_P_2 */
10766 { "vroundpd", { XM, EXx, Ib } },
10767 { "(bad)", { XX } },
10768 },
10769 {
10770 /* VEX_W_3A0A_P_2 */
10771 { "vroundss", { XM, Vex128, EXd, Ib } },
10772 { "(bad)", { XX } },
10773 },
10774 {
10775 /* VEX_W_3A0B_P_2 */
10776 { "vroundsd", { XM, Vex128, EXq, Ib } },
10777 { "(bad)", { XX } },
10778 },
10779 {
10780 /* VEX_W_3A0C_P_2 */
10781 { "vblendps", { XM, Vex, EXx, Ib } },
10782 { "(bad)", { XX } },
10783 },
10784 {
10785 /* VEX_W_3A0D_P_2 */
10786 { "vblendpd", { XM, Vex, EXx, Ib } },
10787 { "(bad)", { XX } },
10788 },
10789 {
10790 /* VEX_W_3A0E_P_2 */
10791 { "vpblendw", { XM, Vex128, EXx, Ib } },
10792 { "(bad)", { XX } },
10793 },
10794 {
10795 /* VEX_W_3A0F_P_2 */
10796 { "vpalignr", { XM, Vex128, EXx, Ib } },
10797 { "(bad)", { XX } },
10798 },
10799 {
10800 /* VEX_W_3A14_P_2 */
10801 { "vpextrb", { Edqb, XM, Ib } },
10802 { "(bad)", { XX } },
10803 },
10804 {
10805 /* VEX_W_3A15_P_2 */
10806 { "vpextrw", { Edqw, XM, Ib } },
10807 { "(bad)", { XX } },
10808 },
10809 {
10810 /* VEX_W_3A18_P_2 */
10811 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10812 { "(bad)", { XX } },
10813 },
10814 {
10815 /* VEX_W_3A19_P_2 */
10816 { "vextractf128", { EXxmm, XM, Ib } },
10817 { "(bad)", { XX } },
10818 },
10819 {
10820 /* VEX_W_3A20_P_2 */
10821 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10822 { "(bad)", { XX } },
10823 },
10824 {
10825 /* VEX_W_3A21_P_2 */
10826 { "vinsertps", { XM, Vex128, EXd, Ib } },
10827 { "(bad)", { XX } },
10828 },
10829 {
10830 /* VEX_W_3A40_P_2 */
10831 { "vdpps", { XM, Vex, EXx, Ib } },
10832 { "(bad)", { XX } },
10833 },
10834 {
10835 /* VEX_W_3A41_P_2 */
10836 { "vdppd", { XM, Vex128, EXx, Ib } },
10837 { "(bad)", { XX } },
10838 },
10839 {
10840 /* VEX_W_3A42_P_2 */
10841 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
10842 { "(bad)", { XX } },
10843 },
10844 {
10845 /* VEX_W_3A44_P_2 */
10846 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10847 { "(bad)", { XX } },
10848 },
10849 {
10850 /* VEX_W_3A4A_P_2 */
10851 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10852 { "(bad)", { XX } },
10853 },
10854 {
10855 /* VEX_W_3A4B_P_2 */
10856 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10857 { "(bad)", { XX } },
10858 },
10859 {
10860 /* VEX_W_3A4C_P_2 */
10861 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
10862 { "(bad)", { XX } },
10863 },
10864 {
10865 /* VEX_W_3A60_P_2 */
10866 { "vpcmpestrm", { XM, EXx, Ib } },
10867 { "(bad)", { XX } },
10868 },
10869 {
10870 /* VEX_W_3A61_P_2 */
10871 { "vpcmpestri", { XM, EXx, Ib } },
10872 { "(bad)", { XX } },
10873 },
10874 {
10875 /* VEX_W_3A62_P_2 */
10876 { "vpcmpistrm", { XM, EXx, Ib } },
10877 { "(bad)", { XX } },
10878 },
10879 {
10880 /* VEX_W_3A63_P_2 */
10881 { "vpcmpistri", { XM, EXx, Ib } },
10882 { "(bad)", { XX } },
10883 },
10884 {
10885 /* VEX_W_3ADF_P_2 */
10886 { "vaeskeygenassist", { XM, EXx, Ib } },
10887 { "(bad)", { XX } },
10888 },
10889};
10890
10891static const struct dis386 mod_table[][2] = {
10892 {
10893 /* MOD_8D */
10894 { "leaS", { Gv, M } },
10895 { "(bad)", { XX } },
10896 },
10897 {
10898 /* MOD_0F01_REG_0 */
10899 { X86_64_TABLE (X86_64_0F01_REG_0) },
10900 { RM_TABLE (RM_0F01_REG_0) },
10901 },
10902 {
10903 /* MOD_0F01_REG_1 */
10904 { X86_64_TABLE (X86_64_0F01_REG_1) },
10905 { RM_TABLE (RM_0F01_REG_1) },
10906 },
10907 {
10908 /* MOD_0F01_REG_2 */
10909 { X86_64_TABLE (X86_64_0F01_REG_2) },
10910 { RM_TABLE (RM_0F01_REG_2) },
10911 },
10912 {
10913 /* MOD_0F01_REG_3 */
10914 { X86_64_TABLE (X86_64_0F01_REG_3) },
10915 { RM_TABLE (RM_0F01_REG_3) },
10916 },
10917 {
10918 /* MOD_0F01_REG_7 */
10919 { "invlpg", { Mb } },
10920 { RM_TABLE (RM_0F01_REG_7) },
10921 },
10922 {
10923 /* MOD_0F12_PREFIX_0 */
10924 { "movlps", { XM, EXq } },
10925 { "movhlps", { XM, EXq } },
10926 },
10927 {
10928 /* MOD_0F13 */
10929 { "movlpX", { EXq, XM } },
10930 { "(bad)", { XX } },
10931 },
10932 {
10933 /* MOD_0F16_PREFIX_0 */
10934 { "movhps", { XM, EXq } },
10935 { "movlhps", { XM, EXq } },
10936 },
10937 {
10938 /* MOD_0F17 */
10939 { "movhpX", { EXq, XM } },
10940 { "(bad)", { XX } },
10941 },
10942 {
10943 /* MOD_0F18_REG_0 */
10944 { "prefetchnta", { Mb } },
10945 { "(bad)", { XX } },
10946 },
10947 {
10948 /* MOD_0F18_REG_1 */
10949 { "prefetcht0", { Mb } },
10950 { "(bad)", { XX } },
10951 },
10952 {
10953 /* MOD_0F18_REG_2 */
10954 { "prefetcht1", { Mb } },
10955 { "(bad)", { XX } },
10956 },
10957 {
10958 /* MOD_0F18_REG_3 */
10959 { "prefetcht2", { Mb } },
10960 { "(bad)", { XX } },
10961 },
10962 {
10963 /* MOD_0F20 */
10964 { "(bad)", { XX } },
10965 { "movZ", { Rm, Cm } },
10966 },
10967 {
10968 /* MOD_0F21 */
10969 { "(bad)", { XX } },
10970 { "movZ", { Rm, Dm } },
10971 },
10972 {
10973 /* MOD_0F22 */
10974 { "(bad)", { XX } },
10975 { "movZ", { Cm, Rm } },
b844680a
L		 10976 },
10977 {
92fddf8e 10978 /* MOD_0F23 */
b844680a 10979 { "(bad)", { XX } },
92fddf8e 10980 { "movZ", { Dm, Rm } },
b844680a
L		 10981 },
10982 {
92fddf8e 10983 /* MOD_0F24 */
c1e679ec 10984 { "(bad)", { XX } },
92fddf8e 10985 { "movL", { Rd, Td } },
b844680a
L		 10986 },
10987 {
92fddf8e 10988 /* MOD_0F26 */
b844680a 10989 { "(bad)", { XX } },
92fddf8e 10990 { "movL", { Td, Rd } },
b844680a 10991 },
75c135a8
L		 10992 {
10993 /* MOD_0F2B_PREFIX_0 */
4ee52178 10994 {"movntps", { Mx, XM } },
75c135a8
L		 10995 { "(bad)", { XX } },
10996 },
10997 {
10998 /* MOD_0F2B_PREFIX_1 */
4ee52178 10999 {"movntss", { Md, XM } },
75c135a8
L		 11000 { "(bad)", { XX } },
11001 },
11002 {
11003 /* MOD_0F2B_PREFIX_2 */
4ee52178 11004 {"movntpd", { Mx, XM } },
75c135a8
L		 11005 { "(bad)", { XX } },
11006 },
11007 {
11008 /* MOD_0F2B_PREFIX_3 */
4ee52178 11009 {"movntsd", { Mq, XM } },
75c135a8
L		 11010 { "(bad)", { XX } },
11011 },
11012 {
11013 /* MOD_0F51 */
11014 { "(bad)", { XX } },
11015 { "movmskpX", { Gdq, XS } },
11016 },
b844680a 11017 {
1ceb70f8 11018 /* MOD_0F71_REG_2 */
b844680a 11019 { "(bad)", { XX } },
4e7d34a6 11020 { "psrlw", { MS, Ib } },
b844680a
L		 11021 },
11022 {
1ceb70f8 11023 /* MOD_0F71_REG_4 */
b844680a 11024 { "(bad)", { XX } },
4e7d34a6 11025 { "psraw", { MS, Ib } },
b844680a
L		 11026 },
11027 {
1ceb70f8 11028 /* MOD_0F71_REG_6 */
b844680a 11029 { "(bad)", { XX } },
4e7d34a6 11030 { "psllw", { MS, Ib } },
b844680a
L		 11031 },
11032 {
1ceb70f8 11033 /* MOD_0F72_REG_2 */
b844680a 11034 { "(bad)", { XX } },
4e7d34a6 11035 { "psrld", { MS, Ib } },
b844680a
L		 11036 },
11037 {
1ceb70f8 11038 /* MOD_0F72_REG_4 */
b844680a 11039 { "(bad)", { XX } },
4e7d34a6 11040 { "psrad", { MS, Ib } },
b844680a
L		 11041 },
11042 {
1ceb70f8 11043 /* MOD_0F72_REG_6 */
b844680a 11044 { "(bad)", { XX } },
4e7d34a6 11045 { "pslld", { MS, Ib } },
b844680a
L		 11046 },
11047 {
1ceb70f8 11048 /* MOD_0F73_REG_2 */
4e7d34a6
L		 11049 { "(bad)", { XX } },
11050 { "psrlq", { MS, Ib } },
b844680a
L		 11051 },
11052 {
1ceb70f8 11053 /* MOD_0F73_REG_3 */
b844680a 11054 { "(bad)", { XX } },
c0f3af97
L		 11055 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11056 },
11057 {
11058 /* MOD_0F73_REG_6 */
11059 { "(bad)", { XX } },
11060 { "psllq", { MS, Ib } },
11061 },
11062 {
11063 /* MOD_0F73_REG_7 */
11064 { "(bad)", { XX } },
11065 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11066 },
11067 {
11068 /* MOD_0FAE_REG_0 */
eacc9c89 11069 { "fxsave", { FXSAVE } },
c0f3af97
L		 11070 { "(bad)", { XX } },
11071 },
11072 {
11073 /* MOD_0FAE_REG_1 */
eacc9c89 11074 { "fxrstor", { FXSAVE } },
c0f3af97
L		 11075 { "(bad)", { XX } },
11076 },
11077 {
11078 /* MOD_0FAE_REG_2 */
11079 { "ldmxcsr", { Md } },
11080 { "(bad)", { XX } },
11081 },
11082 {
11083 /* MOD_0FAE_REG_3 */
11084 { "stmxcsr", { Md } },
11085 { "(bad)", { XX } },
11086 },
11087 {
11088 /* MOD_0FAE_REG_4 */
11089 { "xsave", { M } },
11090 { "(bad)", { XX } },
11091 },
11092 {
11093 /* MOD_0FAE_REG_5 */
11094 { "xrstor", { M } },
11095 { RM_TABLE (RM_0FAE_REG_5) },
11096 },
11097 {
11098 /* MOD_0FAE_REG_6 */
11099 { "xsaveopt", { M } },
11100 { RM_TABLE (RM_0FAE_REG_6) },
11101 },
11102 {
11103 /* MOD_0FAE_REG_7 */
11104 { "clflush", { Mb } },
11105 { RM_TABLE (RM_0FAE_REG_7) },
11106 },
11107 {
11108 /* MOD_0FB2 */
11109 { "lssS", { Gv, Mp } },
11110 { "(bad)", { XX } },
11111 },
11112 {
11113 /* MOD_0FB4 */
11114 { "lfsS", { Gv, Mp } },
11115 { "(bad)", { XX } },
11116 },
11117 {
11118 /* MOD_0FB5 */
11119 { "lgsS", { Gv, Mp } },
11120 { "(bad)", { XX } },
11121 },
11122 {
11123 /* MOD_0FC7_REG_6 */
11124 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11125 { "(bad)", { XX } },
11126 },
11127 {
11128 /* MOD_0FC7_REG_7 */
11129 { "vmptrst", { Mq } },
11130 { "(bad)", { XX } },
11131 },
11132 {
11133 /* MOD_0FD7 */
11134 { "(bad)", { XX } },
11135 { "pmovmskb", { Gdq, MS } },
11136 },
11137 {
11138 /* MOD_0FE7_PREFIX_2 */
11139 { "movntdq", { Mx, XM } },
11140 { "(bad)", { XX } },
11141 },
11142 {
11143 /* MOD_0FF0_PREFIX_3 */
11144 { "lddqu", { XM, M } },
11145 { "(bad)", { XX } },
11146 },
11147 {
11148 /* MOD_0F382A_PREFIX_2 */
11149 { "movntdqa", { XM, Mx } },
11150 { "(bad)", { XX } },
11151 },
11152 {
11153 /* MOD_62_32BIT */
11154 { "bound{S|}", { Gv, Ma } },
11155 { "(bad)", { XX } },
11156 },
11157 {
11158 /* MOD_C4_32BIT */
11159 { "lesS", { Gv, Mp } },
11160 { VEX_C4_TABLE (VEX_0F) },
11161 },
11162 {
11163 /* MOD_C5_32BIT */
11164 { "ldsS", { Gv, Mp } },
11165 { VEX_C5_TABLE (VEX_0F) },
11166 },
11167 {
11168 /* MOD_VEX_12_PREFIX_0 */
11169 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
11170 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
11171 },
11172 {
11173 /* MOD_VEX_13 */
11174 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
11175 { "(bad)", { XX } },
11176 },
11177 {
11178 /* MOD_VEX_16_PREFIX_0 */
11179 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
11180 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
11181 },
11182 {
11183 /* MOD_VEX_17 */
11184 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
11185 { "(bad)", { XX } },
11186 },
11187 {
11188 /* MOD_VEX_2B */
9e30b8e0 11189 { VEX_W_TABLE (VEX_W_2B_M_0) },
c0f3af97
L		 11190 { "(bad)", { XX } },
11191 },
11192 {
976f1fde 11193 /* MOD_VEX_50 */
c0f3af97 11194 { "(bad)", { XX } },
9e30b8e0 11195 { VEX_W_TABLE (VEX_W_50_M_0) },
c0f3af97
L		 11196 },
11197 {
11198 /* MOD_VEX_71_REG_2 */
11199 { "(bad)", { XX } },
11200 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 11201 },
11202 {
c0f3af97 11203 /* MOD_VEX_71_REG_4 */
b844680a 11204 { "(bad)", { XX } },
c0f3af97 11205 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 11206 },
11207 {
c0f3af97 11208 /* MOD_VEX_71_REG_6 */
b844680a 11209 { "(bad)", { XX } },
c0f3af97 11210 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 11211 },
11212 {
c0f3af97 11213 /* MOD_VEX_72_REG_2 */
b844680a 11214 { "(bad)", { XX } },
c0f3af97 11215 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 11216 },
d8faab4e 11217 {
c0f3af97 11218 /* MOD_VEX_72_REG_4 */
d8faab4e 11219 { "(bad)", { XX } },
c0f3af97 11220 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 11221 },
11222 {
c0f3af97 11223 /* MOD_VEX_72_REG_6 */
d8faab4e 11224 { "(bad)", { XX } },
c0f3af97 11225 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 11226 },
876d4bfa 11227 {
c0f3af97 11228 /* MOD_VEX_73_REG_2 */
876d4bfa 11229 { "(bad)", { XX } },
c0f3af97 11230 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 11231 },
11232 {
c0f3af97 11233 /* MOD_VEX_73_REG_3 */
876d4bfa 11234 { "(bad)", { XX } },
c0f3af97 11235 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 11236 },
11237 {
c0f3af97
L		 11238 /* MOD_VEX_73_REG_6 */
11239 { "(bad)", { XX } },
11240 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 11241 },
11242 {
c0f3af97 11243 /* MOD_VEX_73_REG_7 */
4e7d34a6 11244 { "(bad)", { XX } },
c0f3af97 11245 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 11246 },
11247 {
c0f3af97
L		 11248 /* MOD_VEX_AE_REG_2 */
11249 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
11250 { "(bad)", { XX } },
876d4bfa 11251 },
bbedc832 11252 {
c0f3af97
L		 11253 /* MOD_VEX_AE_REG_3 */
11254 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 11255 { "(bad)", { XX } },
bbedc832 11256 },
144c41d9 11257 {
c0f3af97 11258 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 11259 { "(bad)", { XX } },
c0f3af97 11260 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 11261 },
1afd85e3 11262 {
c0f3af97 11263 /* MOD_VEX_E7_PREFIX_2 */
9e30b8e0 11264 { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
92fddf8e 11265 { "(bad)", { XX } },
1afd85e3
L		 11266 },
11267 {
c0f3af97 11268 /* MOD_VEX_F0_PREFIX_3 */
9e30b8e0 11269 { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
92fddf8e
L		 11270 { "(bad)", { XX } },
11271 },
11272 {
c0f3af97
L		 11273 /* MOD_VEX_3818_PREFIX_2 */
11274 { "vbroadcastss", { XM, Md } },
92fddf8e 11275 { "(bad)", { XX } },
1afd85e3 11276 },
75c135a8 11277 {
c0f3af97
L		 11278 /* MOD_VEX_3819_PREFIX_2 */
11279 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 11280 { "(bad)", { XX } },
75c135a8
L		 11281 },
11282 {
c0f3af97
L		 11283 /* MOD_VEX_381A_PREFIX_2 */
11284 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 11285 { "(bad)", { XX } },
11286 },
1afd85e3 11287 {
c0f3af97
L		 11288 /* MOD_VEX_382A_PREFIX_2 */
11289 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 11290 { "(bad)", { XX } },
1afd85e3 11291 },
75c135a8 11292 {
c0f3af97 11293 /* MOD_VEX_382C_PREFIX_2 */
53aa04a0 11294 { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
75c135a8
L		 11295 { "(bad)", { XX } },
11296 },
1afd85e3 11297 {
c0f3af97 11298 /* MOD_VEX_382D_PREFIX_2 */
53aa04a0 11299 { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
1afd85e3 11300 { "(bad)", { XX } },
1afd85e3
L		 11301 },
11302 {
c0f3af97 11303 /* MOD_VEX_382E_PREFIX_2 */
53aa04a0 11304 { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
4e7d34a6 11305 { "(bad)", { XX } },
1afd85e3
L		 11306 },
11307 {
c0f3af97 11308 /* MOD_VEX_382F_PREFIX_2 */
53aa04a0 11309 { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
1afd85e3 11310 { "(bad)", { XX } },
1afd85e3 11311 },
b844680a
L		 11312};
11313
1ceb70f8 11314static const struct dis386 rm_table[][8] = {
b844680a 11315 {
1ceb70f8 11316 /* RM_0F01_REG_0 */
b844680a
L		 11317 { "(bad)", { XX } },
11318 { "vmcall", { Skip_MODRM } },
11319 { "vmlaunch", { Skip_MODRM } },
11320 { "vmresume", { Skip_MODRM } },
11321 { "vmxoff", { Skip_MODRM } },
11322 { "(bad)", { XX } },
11323 { "(bad)", { XX } },
11324 { "(bad)", { XX } },
11325 },
11326 {
1ceb70f8 11327 /* RM_0F01_REG_1 */
b844680a
L		 11328 { "monitor", { { OP_Monitor, 0 } } },
11329 { "mwait", { { OP_Mwait, 0 } } },
11330 { "(bad)", { XX } },
11331 { "(bad)", { XX } },
11332 { "(bad)", { XX } },
11333 { "(bad)", { XX } },
11334 { "(bad)", { XX } },
11335 { "(bad)", { XX } },
11336 },
475a2301
L		 11337 {
11338 /* RM_0F01_REG_2 */
11339 { "xgetbv", { Skip_MODRM } },
11340 { "xsetbv", { Skip_MODRM } },
11341 { "(bad)", { XX } },
11342 { "(bad)", { XX } },
11343 { "(bad)", { XX } },
11344 { "(bad)", { XX } },
11345 { "(bad)", { XX } },
11346 { "(bad)", { XX } },
11347 },
b844680a 11348 {
1ceb70f8 11349 /* RM_0F01_REG_3 */
4e7d34a6
L		 11350 { "vmrun", { Skip_MODRM } },
11351 { "vmmcall", { Skip_MODRM } },
11352 { "vmload", { Skip_MODRM } },
11353 { "vmsave", { Skip_MODRM } },
11354 { "stgi", { Skip_MODRM } },
11355 { "clgi", { Skip_MODRM } },
11356 { "skinit", { Skip_MODRM } },
11357 { "invlpga", { Skip_MODRM } },
11358 },
11359 {
1ceb70f8 11360 /* RM_0F01_REG_7 */
4e7d34a6
L		 11361 { "swapgs", { Skip_MODRM } },
11362 { "rdtscp", { Skip_MODRM } },
b844680a
L		 11363 { "(bad)", { XX } },
11364 { "(bad)", { XX } },
11365 { "(bad)", { XX } },
11366 { "(bad)", { XX } },
11367 { "(bad)", { XX } },
11368 { "(bad)", { XX } },
11369 },
11370 {
1ceb70f8 11371 /* RM_0FAE_REG_5 */
4e7d34a6 11372 { "lfence", { Skip_MODRM } },
b844680a
L		 11373 { "(bad)", { XX } },
11374 { "(bad)", { XX } },
11375 { "(bad)", { XX } },
11376 { "(bad)", { XX } },
11377 { "(bad)", { XX } },
11378 { "(bad)", { XX } },
11379 { "(bad)", { XX } },
11380 },
11381 {
1ceb70f8 11382 /* RM_0FAE_REG_6 */
4e7d34a6 11383 { "mfence", { Skip_MODRM } },
b844680a
L		 11384 { "(bad)", { XX } },
11385 { "(bad)", { XX } },
11386 { "(bad)", { XX } },
11387 { "(bad)", { XX } },
11388 { "(bad)", { XX } },
11389 { "(bad)", { XX } },
11390 { "(bad)", { XX } },
11391 },
bbedc832 11392 {
1ceb70f8 11393 /* RM_0FAE_REG_7 */
4e7d34a6
L		 11394 { "sfence", { Skip_MODRM } },
11395 { "(bad)", { XX } },
bbedc832
L		 11396 { "(bad)", { XX } },
11397 { "(bad)", { XX } },
11398 { "(bad)", { XX } },
11399 { "(bad)", { XX } },
11400 { "(bad)", { XX } },
11401 { "(bad)", { XX } },
144c41d9 11402 },
b844680a
L		 11403};
11404
c608c12e
AM		 11405#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11406
f16cd0d5
L		 11407/* We use the high bit to indicate different name for the same
11408 prefix. */
11409#define ADDR16_PREFIX (0x67 | 0x100)
11410#define ADDR32_PREFIX (0x67 | 0x200)
11411#define DATA16_PREFIX (0x66 | 0x100)
11412#define DATA32_PREFIX (0x66 | 0x200)
11413#define REP_PREFIX (0xf3 | 0x100)
11414
11415static int
26ca5450 11416ckprefix (void)
252b5132 11417{
f16cd0d5 11418 int newrex, i, length;
52b15da3 11419 rex = 0;
c0f3af97
L		 11420 rex_original = 0;
11421 rex_ignored = 0;
252b5132 11422 prefixes = 0;
7d421014 11423 used_prefixes = 0;
52b15da3 11424 rex_used = 0;
f16cd0d5
L		 11425 last_lock_prefix = -1;
11426 last_repz_prefix = -1;
11427 last_repnz_prefix = -1;
11428 last_data_prefix = -1;
11429 last_addr_prefix = -1;
11430 last_rex_prefix = -1;
11431 last_seg_prefix = -1;
f310f33d
L		 11432 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11433 all_prefixes[i] = 0;
11434 i = 0;
f16cd0d5
L		 11435 length = 0;
11436 /* The maximum instruction length is 15bytes. */
11437 while (length < MAX_CODE_LENGTH - 1)
252b5132
RH		 11438 {
11439 FETCH_DATA (the_info, codep + 1);
52b15da3 11440 newrex = 0;
252b5132
RH		 11441 switch (*codep)
11442 {
52b15da3
JH		 11443 /* REX prefixes family. */
11444 case 0x40:
11445 case 0x41:
11446 case 0x42:
11447 case 0x43:
11448 case 0x44:
11449 case 0x45:
11450 case 0x46:
11451 case 0x47:
11452 case 0x48:
11453 case 0x49:
11454 case 0x4a:
11455 case 0x4b:
11456 case 0x4c:
11457 case 0x4d:
11458 case 0x4e:
11459 case 0x4f:
f16cd0d5
L		 11460 if (address_mode == mode_64bit)
11461 newrex = *codep;
11462 else
11463 return 1;
11464 last_rex_prefix = i;
52b15da3 11465 break;
252b5132
RH		 11466 case 0xf3:
11467 prefixes |= PREFIX_REPZ;
f16cd0d5 11468 last_repz_prefix = i;
252b5132
RH		 11469 break;
11470 case 0xf2:
11471 prefixes |= PREFIX_REPNZ;
f16cd0d5 11472 last_repnz_prefix = i;
252b5132
RH		 11473 break;
11474 case 0xf0:
11475 prefixes |= PREFIX_LOCK;
f16cd0d5 11476 last_lock_prefix = i;
252b5132
RH		 11477 break;
11478 case 0x2e:
11479 prefixes |= PREFIX_CS;
f16cd0d5 11480 last_seg_prefix = i;
252b5132
RH		 11481 break;
11482 case 0x36:
11483 prefixes |= PREFIX_SS;
f16cd0d5 11484 last_seg_prefix = i;
252b5132
RH		 11485 break;
11486 case 0x3e:
11487 prefixes |= PREFIX_DS;
f16cd0d5 11488 last_seg_prefix = i;
252b5132
RH		 11489 break;
11490 case 0x26:
11491 prefixes |= PREFIX_ES;
f16cd0d5 11492 last_seg_prefix = i;
252b5132
RH		 11493 break;
11494 case 0x64:
11495 prefixes |= PREFIX_FS;
f16cd0d5 11496 last_seg_prefix = i;
252b5132
RH		 11497 break;
11498 case 0x65:
11499 prefixes |= PREFIX_GS;
f16cd0d5 11500 last_seg_prefix = i;
252b5132
RH		 11501 break;
11502 case 0x66:
11503 prefixes |= PREFIX_DATA;
f16cd0d5 11504 last_data_prefix = i;
252b5132
RH		 11505 break;
11506 case 0x67:
11507 prefixes |= PREFIX_ADDR;
f16cd0d5 11508 last_addr_prefix = i;
252b5132 11509 break;
5076851f 11510 case FWAIT_OPCODE:
252b5132
RH		 11511 /* fwait is really an instruction. If there are prefixes
11512 before the fwait, they belong to the fwait, *not* to the
11513 following instruction. */
3e7d61b2 11514 if (prefixes || rex)
252b5132
RH		 11515 {
11516 prefixes |= PREFIX_FWAIT;
11517 codep++;
f16cd0d5 11518 return 1;
252b5132
RH		 11519 }
11520 prefixes = PREFIX_FWAIT;
11521 break;
11522 default:
f16cd0d5 11523 return 1;
252b5132 11524 }
52b15da3
JH		 11525 /* Rex is ignored when followed by another prefix. */
11526 if (rex)
11527 {
3e7d61b2 11528 rex_used = rex;
f16cd0d5 11529 return 1;
52b15da3 11530 }
f16cd0d5
L		 11531 if (*codep != FWAIT_OPCODE)
11532 all_prefixes[i++] = *codep;
52b15da3 11533 rex = newrex;
c0f3af97 11534 rex_original = rex;
252b5132 11535 codep++;
f16cd0d5
L		 11536 length++;
11537 }
11538 return 0;
11539}
11540
11541static int
11542seg_prefix (int pref)
11543{
11544 switch (pref)
11545 {
11546 case 0x2e:
11547 return PREFIX_CS;
11548 case 0x36:
11549 return PREFIX_SS;
11550 case 0x3e:
11551 return PREFIX_DS;
11552 case 0x26:
11553 return PREFIX_ES;
11554 case 0x64:
11555 return PREFIX_FS;
11556 case 0x65:
11557 return PREFIX_GS;
11558 default:
11559 return 0;
252b5132
RH		 11560 }
11561}
11562
7d421014
ILT		 11563/* Return the name of the prefix byte PREF, or NULL if PREF is not a
11564 prefix byte. */
11565
11566static const char *
26ca5450 11567prefix_name (int pref, int sizeflag)
7d421014 11568{
0003779b
L		 11569 static const char *rexes [16] =
11570 {
11571 "rex", /* 0x40 */
11572 "rex.B", /* 0x41 */
11573 "rex.X", /* 0x42 */
11574 "rex.XB", /* 0x43 */
11575 "rex.R", /* 0x44 */
11576 "rex.RB", /* 0x45 */
11577 "rex.RX", /* 0x46 */
11578 "rex.RXB", /* 0x47 */
11579 "rex.W", /* 0x48 */
11580 "rex.WB", /* 0x49 */
11581 "rex.WX", /* 0x4a */
11582 "rex.WXB", /* 0x4b */
11583 "rex.WR", /* 0x4c */
11584 "rex.WRB", /* 0x4d */
11585 "rex.WRX", /* 0x4e */
11586 "rex.WRXB", /* 0x4f */
11587 };
11588
7d421014
ILT		 11589 switch (pref)
11590 {
52b15da3
JH		 11591 /* REX prefixes family. */
11592 case 0x40:
52b15da3 11593 case 0x41:
52b15da3 11594 case 0x42:
52b15da3 11595 case 0x43:
52b15da3 11596 case 0x44:
52b15da3 11597 case 0x45:
52b15da3 11598 case 0x46:
52b15da3 11599 case 0x47:
52b15da3 11600 case 0x48:
52b15da3 11601 case 0x49:
52b15da3 11602 case 0x4a:
52b15da3 11603 case 0x4b:
52b15da3 11604 case 0x4c:
52b15da3 11605 case 0x4d:
52b15da3 11606 case 0x4e:
52b15da3 11607 case 0x4f:
0003779b 11608 return rexes [pref - 0x40];
7d421014
ILT		 11609 case 0xf3:
11610 return "repz";
11611 case 0xf2:
11612 return "repnz";
11613 case 0xf0:
11614 return "lock";
11615 case 0x2e:
11616 return "cs";
11617 case 0x36:
11618 return "ss";
11619 case 0x3e:
11620 return "ds";
11621 case 0x26:
11622 return "es";
11623 case 0x64:
11624 return "fs";
11625 case 0x65:
11626 return "gs";
11627 case 0x66:
11628 return (sizeflag & DFLAG) ? "data16" : "data32";
11629 case 0x67:
cb712a9e 11630 if (address_mode == mode_64bit)
db6eb5be 11631 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 11632 else
2888cb7a 11633 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 11634 case FWAIT_OPCODE:
11635 return "fwait";
f16cd0d5
L		 11636 case ADDR16_PREFIX:
11637 return "addr16";
11638 case ADDR32_PREFIX:
11639 return "addr32";
11640 case DATA16_PREFIX:
11641 return "data16";
11642 case DATA32_PREFIX:
11643 return "data32";
11644 case REP_PREFIX:
11645 return "rep";
7d421014
ILT		 11646 default:
11647 return NULL;
11648 }
11649}
11650
ce518a5f
L		 11651static char op_out[MAX_OPERANDS][100];
11652static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 11653static int two_source_ops;
ce518a5f
L		 11654static bfd_vma op_address[MAX_OPERANDS];
11655static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 11656static bfd_vma start_pc;
ce518a5f 11657
252b5132
RH		 11658/*
11659 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11660 * (see topic "Redundant prefixes" in the "Differences from 8086"
11661 * section of the "Virtual 8086 Mode" chapter.)
11662 * 'pc' should be the address of this instruction, it will
11663 * be used to print the target address if this is a relative jump or call
11664 * The function returns the length of this instruction in bytes.
11665 */
11666
252b5132 11667static char intel_syntax;
9d141669 11668static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 11669static char open_char;
11670static char close_char;
11671static char separator_char;
11672static char scale_char;
11673
e396998b
AM		 11674/* Here for backwards compatibility. When gdb stops using
11675 print_insn_i386_att and print_insn_i386_intel these functions can
11676 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 11677int
26ca5450 11678print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 11679{
11680 intel_syntax = 0;
e396998b
AM		 11681
11682 return print_insn (pc, info);
252b5132
RH		 11683}
11684
11685int
26ca5450 11686print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 11687{
11688 intel_syntax = 1;
e396998b
AM		 11689
11690 return print_insn (pc, info);
252b5132
RH		 11691}
11692
e396998b 11693int
26ca5450 11694print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 11695{
11696 intel_syntax = -1;
11697
11698 return print_insn (pc, info);
11699}
11700
f59a29b9
L		 11701void
11702print_i386_disassembler_options (FILE *stream)
11703{
11704 fprintf (stream, _("\n\
11705The following i386/x86-64 specific disassembler options are supported for use\n\
11706with the -M switch (multiple options should be separated by commas):\n"));
11707
11708 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11709 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11710 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11711 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11712 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 11713 fprintf (stream, _(" att-mnemonic\n"
11714 " Display instruction in AT&T mnemonic\n"));
11715 fprintf (stream, _(" intel-mnemonic\n"
11716 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 11717 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11718 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11719 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11720 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11721 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11722 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11723}
11724
b844680a
L		 11725/* Get a pointer to struct dis386 with a valid name. */
11726
11727static const struct dis386 *
8bb15339 11728get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 11729{
91d6fa6a 11730 int vindex, vex_table_index;
b844680a
L		 11731
11732 if (dp->name != NULL)
11733 return dp;
11734
11735 switch (dp->op[0].bytemode)
11736 {
1ceb70f8
L		 11737 case USE_REG_TABLE:
11738 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11739 break;
11740
11741 case USE_MOD_TABLE:
91d6fa6a
NC		 11742 vindex = modrm.mod == 0x3 ? 1 : 0;
11743 dp = &mod_table[dp->op[1].bytemode][vindex];
1ceb70f8
L		 11744 break;
11745
11746 case USE_RM_TABLE:
11747 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 11748 break;
11749
4e7d34a6 11750 case USE_PREFIX_TABLE:
c0f3af97 11751 if (need_vex)
b844680a 11752 {
c0f3af97
L		 11753 /* The prefix in VEX is implicit. */
11754 switch (vex.prefix)
11755 {
11756 case 0:
91d6fa6a 11757 vindex = 0;
c0f3af97
L		 11758 break;
11759 case REPE_PREFIX_OPCODE:
91d6fa6a 11760 vindex = 1;
c0f3af97
L		 11761 break;
11762 case DATA_PREFIX_OPCODE:
91d6fa6a 11763 vindex = 2;
c0f3af97
L		 11764 break;
11765 case REPNE_PREFIX_OPCODE:
91d6fa6a 11766 vindex = 3;
c0f3af97
L		 11767 break;
11768 default:
11769 abort ();
11770 break;
11771 }
b844680a 11772 }
c0f3af97 11773 else
b844680a 11774 {
91d6fa6a 11775 vindex = 0;
c0f3af97
L		 11776 used_prefixes |= (prefixes & PREFIX_REPZ);
11777 if (prefixes & PREFIX_REPZ)
b844680a 11778 {
91d6fa6a 11779 vindex = 1;
f16cd0d5 11780 all_prefixes[last_repz_prefix] = 0;
b844680a
L		 11781 }
11782 else
11783 {
c0f3af97
L		 11784 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11785 PREFIX_DATA. */
11786 used_prefixes |= (prefixes & PREFIX_REPNZ);
11787 if (prefixes & PREFIX_REPNZ)
11788 {
91d6fa6a 11789 vindex = 3;
f16cd0d5 11790 all_prefixes[last_repnz_prefix] = 0;
c0f3af97
L		 11791 }
11792 else
b844680a 11793 {
c0f3af97
L		 11794 used_prefixes |= (prefixes & PREFIX_DATA);
11795 if (prefixes & PREFIX_DATA)
11796 {
91d6fa6a 11797 vindex = 2;
f16cd0d5 11798 all_prefixes[last_data_prefix] = 0;
c0f3af97 11799 }
b844680a
L		 11800 }
11801 }
11802 }
91d6fa6a 11803 dp = &prefix_table[dp->op[1].bytemode][vindex];
b844680a
L		 11804 break;
11805
4e7d34a6 11806 case USE_X86_64_TABLE:
91d6fa6a
NC		 11807 vindex = address_mode == mode_64bit ? 1 : 0;
11808 dp = &x86_64_table[dp->op[1].bytemode][vindex];
b844680a
L		 11809 break;
11810
4e7d34a6 11811 case USE_3BYTE_TABLE:
8bb15339 11812 FETCH_DATA (info, codep + 2);
91d6fa6a
NC		 11813 vindex = *codep++;
11814 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8bb15339
L		 11815 modrm.mod = (*codep >> 6) & 3;
11816 modrm.reg = (*codep >> 3) & 7;
11817 modrm.rm = *codep & 7;
11818 break;
11819
c0f3af97
L		 11820 case USE_VEX_LEN_TABLE:
11821 if (!need_vex)
11822 abort ();
11823
11824 switch (vex.length)
11825 {
11826 case 128:
91d6fa6a 11827 vindex = 0;
c0f3af97
L		 11828 break;
11829 case 256:
91d6fa6a 11830 vindex = 1;
c0f3af97
L		 11831 break;
11832 default:
11833 abort ();
11834 break;
11835 }
11836
91d6fa6a 11837 dp = &vex_len_table[dp->op[1].bytemode][vindex];
c0f3af97
L		 11838 break;
11839
f88c9eb0
SP		 11840 case USE_XOP_8F_TABLE:
11841 FETCH_DATA (info, codep + 3);
11842 /* All bits in the REX prefix are ignored. */
11843 rex_ignored = rex;
11844 rex = ~(*codep >> 5) & 0x7;
11845
11846 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11847 switch ((*codep & 0x1f))
11848 {
11849 default:
11850 BadOp ();
5dd85c99
SP		 11851 case 0x8:
11852 vex_table_index = XOP_08;
11853 break;
f88c9eb0
SP		 11854 case 0x9:
11855 vex_table_index = XOP_09;
11856 break;
11857 case 0xa:
11858 vex_table_index = XOP_0A;
11859 break;
11860 }
11861 codep++;
11862 vex.w = *codep & 0x80;
11863 if (vex.w && address_mode == mode_64bit)
11864 rex |= REX_W;
11865
11866 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11867 if (address_mode != mode_64bit
11868 && vex.register_specifier > 0x7)
11869 BadOp ();
11870
11871 vex.length = (*codep & 0x4) ? 256 : 128;
11872 switch ((*codep & 0x3))
11873 {
11874 case 0:
11875 vex.prefix = 0;
11876 break;
11877 case 1:
11878 vex.prefix = DATA_PREFIX_OPCODE;
11879 break;
11880 case 2:
11881 vex.prefix = REPE_PREFIX_OPCODE;
11882 break;
11883 case 3:
11884 vex.prefix = REPNE_PREFIX_OPCODE;
11885 break;
11886 }
11887 need_vex = 1;
11888 need_vex_reg = 1;
11889 codep++;
91d6fa6a
NC		 11890 vindex = *codep++;
11891 dp = &xop_table[vex_table_index][vindex];
c48244a5
SP		 11892
11893 FETCH_DATA (info, codep + 1);
11894 modrm.mod = (*codep >> 6) & 3;
11895 modrm.reg = (*codep >> 3) & 7;
11896 modrm.rm = *codep & 7;
f88c9eb0
SP		 11897 break;
11898
c0f3af97
L		 11899 case USE_VEX_C4_TABLE:
11900 FETCH_DATA (info, codep + 3);
11901 /* All bits in the REX prefix are ignored. */
11902 rex_ignored = rex;
11903 rex = ~(*codep >> 5) & 0x7;
11904 switch ((*codep & 0x1f))
11905 {
11906 default:
11907 BadOp ();
11908 case 0x1:
f88c9eb0 11909 vex_table_index = VEX_0F;
c0f3af97
L		 11910 break;
11911 case 0x2:
f88c9eb0 11912 vex_table_index = VEX_0F38;
c0f3af97
L		 11913 break;
11914 case 0x3:
f88c9eb0 11915 vex_table_index = VEX_0F3A;
c0f3af97
L		 11916 break;
11917 }
11918 codep++;
11919 vex.w = *codep & 0x80;
11920 if (vex.w && address_mode == mode_64bit)
11921 rex |= REX_W;
11922
11923 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11924 if (address_mode != mode_64bit
11925 && vex.register_specifier > 0x7)
11926 BadOp ();
11927
11928 vex.length = (*codep & 0x4) ? 256 : 128;
11929 switch ((*codep & 0x3))
11930 {
11931 case 0:
11932 vex.prefix = 0;
11933 break;
11934 case 1:
11935 vex.prefix = DATA_PREFIX_OPCODE;
11936 break;
11937 case 2:
11938 vex.prefix = REPE_PREFIX_OPCODE;
11939 break;
11940 case 3:
11941 vex.prefix = REPNE_PREFIX_OPCODE;
11942 break;
11943 }
11944 need_vex = 1;
11945 need_vex_reg = 1;
11946 codep++;
91d6fa6a
NC		 11947 vindex = *codep++;
11948 dp = &vex_table[vex_table_index][vindex];
c0f3af97 11949 /* There is no MODRM byte for VEX [82|77]. */
91d6fa6a 11950 if (vindex != 0x77 && vindex != 0x82)
c0f3af97
L		 11951 {
11952 FETCH_DATA (info, codep + 1);
11953 modrm.mod = (*codep >> 6) & 3;
11954 modrm.reg = (*codep >> 3) & 7;
11955 modrm.rm = *codep & 7;
11956 }
11957 break;
11958
11959 case USE_VEX_C5_TABLE:
11960 FETCH_DATA (info, codep + 2);
11961 /* All bits in the REX prefix are ignored. */
11962 rex_ignored = rex;
11963 rex = (*codep & 0x80) ? 0 : REX_R;
11964
11965 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11966 if (address_mode != mode_64bit
11967 && vex.register_specifier > 0x7)
11968 BadOp ();
11969
759a05ce
L		 11970 vex.w = 0;
11971
c0f3af97
L		 11972 vex.length = (*codep & 0x4) ? 256 : 128;
11973 switch ((*codep & 0x3))
11974 {
11975 case 0:
11976 vex.prefix = 0;
11977 break;
11978 case 1:
11979 vex.prefix = DATA_PREFIX_OPCODE;
11980 break;
11981 case 2:
11982 vex.prefix = REPE_PREFIX_OPCODE;
11983 break;
11984 case 3:
11985 vex.prefix = REPNE_PREFIX_OPCODE;
11986 break;
11987 }
11988 need_vex = 1;
11989 need_vex_reg = 1;
11990 codep++;
91d6fa6a
NC		 11991 vindex = *codep++;
11992 dp = &vex_table[dp->op[1].bytemode][vindex];
c0f3af97 11993 /* There is no MODRM byte for VEX [82|77]. */
91d6fa6a 11994 if (vindex != 0x77 && vindex != 0x82)
c0f3af97
L		 11995 {
11996 FETCH_DATA (info, codep + 1);
11997 modrm.mod = (*codep >> 6) & 3;
11998 modrm.reg = (*codep >> 3) & 7;
11999 modrm.rm = *codep & 7;
12000 }
12001 break;
12002
9e30b8e0
L		 12003 case USE_VEX_W_TABLE:
12004 if (!need_vex)
12005 abort ();
12006
12007 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12008 break;
12009
b844680a 12010 default:
d34b5006 12011 abort ();
b844680a
L		 12012 }
12013
12014 if (dp->name != NULL)
12015 return dp;
12016 else
8bb15339 12017 return get_valid_dis386 (dp, info);
b844680a
L		 12018}
12019
e396998b 12020static int
26ca5450 12021print_insn (bfd_vma pc, disassemble_info *info)
252b5132 12022{
2da11e11 12023 const struct dis386 *dp;
252b5132 12024 int i;
ce518a5f 12025 char *op_txt[MAX_OPERANDS];
252b5132 12026 int needcomma;
e396998b
AM		 12027 int sizeflag;
12028 const char *p;
252b5132 12029 struct dis_private priv;
eec0f4ca 12030 unsigned char op;
f16cd0d5
L		 12031 int prefix_length;
12032 int default_prefixes;
252b5132 12033
cb712a9e 12034 if (info->mach == bfd_mach_x86_64_intel_syntax
8a9036a4
L		 12035 || info->mach == bfd_mach_x86_64
12036 || info->mach == bfd_mach_l1om
12037 || info->mach == bfd_mach_l1om_intel_syntax)
cb712a9e
L		 12038 address_mode = mode_64bit;
12039 else
12040 address_mode = mode_32bit;
52b15da3 12041
8373f971 12042 if (intel_syntax == (char) -1)
e396998b 12043 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 12044 || info->mach == bfd_mach_x86_64_intel_syntax
12045 || info->mach == bfd_mach_l1om_intel_syntax);
e396998b 12046
2da11e11 12047 if (info->mach == bfd_mach_i386_i386
52b15da3 12048 || info->mach == bfd_mach_x86_64
8a9036a4 12049 || info->mach == bfd_mach_l1om
52b15da3 12050 || info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 12051 || info->mach == bfd_mach_x86_64_intel_syntax
12052 || info->mach == bfd_mach_l1om_intel_syntax)
e396998b 12053 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 12054 else if (info->mach == bfd_mach_i386_i8086)
e396998b 12055 priv.orig_sizeflag = 0;
2da11e11
AM		 12056 else
12057 abort ();
e396998b
AM		 12058
12059 for (p = info->disassembler_options; p != NULL; )
12060 {
0112cd26 12061 if (CONST_STRNEQ (p, "x86-64"))
e396998b 12062 {
cb712a9e 12063 address_mode = mode_64bit;
e396998b
AM		 12064 priv.orig_sizeflag = AFLAG | DFLAG;
12065 }
0112cd26 12066 else if (CONST_STRNEQ (p, "i386"))
e396998b 12067 {
cb712a9e 12068 address_mode = mode_32bit;
e396998b
AM		 12069 priv.orig_sizeflag = AFLAG | DFLAG;
12070 }
0112cd26 12071 else if (CONST_STRNEQ (p, "i8086"))
e396998b 12072 {
cb712a9e 12073 address_mode = mode_16bit;
e396998b
AM		 12074 priv.orig_sizeflag = 0;
12075 }
0112cd26 12076 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 12077 {
12078 intel_syntax = 1;
9d141669
L		 12079 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12080 intel_mnemonic = 1;
e396998b 12081 }
0112cd26 12082 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 12083 {
12084 intel_syntax = 0;
9d141669
L		 12085 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12086 intel_mnemonic = 0;
e396998b 12087 }
0112cd26 12088 else if (CONST_STRNEQ (p, "addr"))
e396998b 12089 {
f59a29b9
L		 12090 if (address_mode == mode_64bit)
12091 {
12092 if (p[4] == '3' && p[5] == '2')
12093 priv.orig_sizeflag &= ~AFLAG;
12094 else if (p[4] == '6' && p[5] == '4')
12095 priv.orig_sizeflag |= AFLAG;
12096 }
12097 else
12098 {
12099 if (p[4] == '1' && p[5] == '6')
12100 priv.orig_sizeflag &= ~AFLAG;
12101 else if (p[4] == '3' && p[5] == '2')
12102 priv.orig_sizeflag |= AFLAG;
12103 }
e396998b 12104 }
0112cd26 12105 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 12106 {
12107 if (p[4] == '1' && p[5] == '6')
12108 priv.orig_sizeflag &= ~DFLAG;
12109 else if (p[4] == '3' && p[5] == '2')
12110 priv.orig_sizeflag |= DFLAG;
12111 }
0112cd26 12112 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 12113 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12114
12115 p = strchr (p, ',');
12116 if (p != NULL)
12117 p++;
12118 }
12119
12120 if (intel_syntax)
12121 {
12122 names64 = intel_names64;
12123 names32 = intel_names32;
12124 names16 = intel_names16;
12125 names8 = intel_names8;
12126 names8rex = intel_names8rex;
12127 names_seg = intel_names_seg;
db51cc60
L		 12128 index64 = intel_index64;
12129 index32 = intel_index32;
e396998b
AM		 12130 index16 = intel_index16;
12131 open_char = '[';
12132 close_char = ']';
12133 separator_char = '+';
12134 scale_char = '*';
12135 }
12136 else
12137 {
12138 names64 = att_names64;
12139 names32 = att_names32;
12140 names16 = att_names16;
12141 names8 = att_names8;
12142 names8rex = att_names8rex;
12143 names_seg = att_names_seg;
db51cc60
L		 12144 index64 = att_index64;
12145 index32 = att_index32;
e396998b
AM		 12146 index16 = att_index16;
12147 open_char = '(';
12148 close_char = ')';
12149 separator_char = ',';
12150 scale_char = ',';
12151 }
2da11e11 12152
4fe53c98 12153 /* The output looks better if we put 7 bytes on a line, since that
8a9036a4
L		 12154 puts most long word instructions on a single line. Use 8 bytes
12155 for Intel L1OM. */
12156 if (info->mach == bfd_mach_l1om
12157 || info->mach == bfd_mach_l1om_intel_syntax)
12158 info->bytes_per_line = 8;
12159 else
12160 info->bytes_per_line = 7;
252b5132 12161
26ca5450 12162 info->private_data = &priv;
252b5132
RH		 12163 priv.max_fetched = priv.the_buffer;
12164 priv.insn_start = pc;
252b5132
RH		 12165
12166 obuf[0] = 0;
ce518a5f
L		 12167 for (i = 0; i < MAX_OPERANDS; ++i)
12168 {
12169 op_out[i][0] = 0;
12170 op_index[i] = -1;
12171 }
252b5132
RH		 12172
12173 the_info = info;
12174 start_pc = pc;
e396998b
AM		 12175 start_codep = priv.the_buffer;
12176 codep = priv.the_buffer;
252b5132 12177
5076851f
ILT		 12178 if (setjmp (priv.bailout) != 0)
12179 {
7d421014
ILT		 12180 const char *name;
12181
5076851f 12182 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 12183 means we have an incomplete instruction of some sort. Just
12184 print the first byte as a prefix or a .byte pseudo-op. */
12185 if (codep > priv.the_buffer)
5076851f 12186 {
e396998b 12187 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 12188 if (name != NULL)
12189 (*info->fprintf_func) (info->stream, "%s", name);
12190 else
5076851f 12191 {
7d421014
ILT		 12192 /* Just print the first byte as a .byte instruction. */
12193 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 12194 (unsigned int) priv.the_buffer[0]);
5076851f 12195 }
5076851f 12196
7d421014 12197 return 1;
5076851f
ILT		 12198 }
12199
12200 return -1;
12201 }
12202
52b15da3 12203 obufp = obuf;
f16cd0d5
L		 12204 sizeflag = priv.orig_sizeflag;
12205
12206 if (!ckprefix () || rex_used)
12207 {
12208 /* Too many prefixes or unused REX prefixes. */
12209 for (i = 0;
12210 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
12211 i++)
12212 (*info->fprintf_func) (info->stream, "%s",
12213 prefix_name (all_prefixes[i], sizeflag));
12214 return 1;
12215 }
252b5132
RH		 12216
12217 insn_codep = codep;
12218
12219 FETCH_DATA (info, codep + 1);
12220 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12221
3e7d61b2 12222 if (((prefixes & PREFIX_FWAIT)
f16cd0d5 12223 && ((*codep < 0xd8) || (*codep > 0xdf))))
252b5132 12224 {
f16cd0d5 12225 (*info->fprintf_func) (info->stream, "fwait");
7d421014 12226 return 1;
252b5132
RH		 12227 }
12228
eec0f4ca 12229 op = 0;
c1e679ec 12230
252b5132
RH		 12231 if (*codep == 0x0f)
12232 {
eec0f4ca 12233 unsigned char threebyte;
252b5132 12234 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 12235 threebyte = *++codep;
12236 dp = &dis386_twobyte[threebyte];
252b5132 12237 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 12238 codep++;
252b5132
RH		 12239 }
12240 else
12241 {
6439fc28 12242 dp = &dis386[*codep];
252b5132 12243 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 12244 codep++;
252b5132 12245 }
246c51aa 12246
b844680a 12247 if ((prefixes & PREFIX_REPZ))
f16cd0d5 12248 used_prefixes |= PREFIX_REPZ;
b844680a 12249 if ((prefixes & PREFIX_REPNZ))
f16cd0d5 12250 used_prefixes |= PREFIX_REPNZ;
b844680a 12251 if ((prefixes & PREFIX_LOCK))
f16cd0d5 12252 used_prefixes |= PREFIX_LOCK;
c608c12e 12253
f16cd0d5 12254 default_prefixes = 0;
c608c12e
AM		 12255 if (prefixes & PREFIX_ADDR)
12256 {
12257 sizeflag ^= AFLAG;
ce518a5f 12258 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 12259 {
cb712a9e 12260 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
f16cd0d5 12261 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
3ffd33cf 12262 else
f16cd0d5
L		 12263 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12264 default_prefixes |= PREFIX_ADDR;
3ffd33cf
AM		 12265 }
12266 }
12267
b844680a 12268 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 12269 {
12270 sizeflag ^= DFLAG;
ce518a5f
L		 12271 if (dp->op[2].bytemode == cond_jump_mode
12272 && dp->op[0].bytemode == v_mode
6439fc28 12273 && !intel_syntax)
3ffd33cf
AM		 12274 {
12275 if (sizeflag & DFLAG)
f16cd0d5 12276 all_prefixes[last_data_prefix] = DATA32_PREFIX;
3ffd33cf 12277 else
f16cd0d5
L		 12278 all_prefixes[last_data_prefix] = DATA16_PREFIX;
12279 default_prefixes |= PREFIX_DATA;
12280 }
12281 else if (rex & REX_W)
12282 {
12283 /* REX_W will override PREFIX_DATA. */
12284 default_prefixes |= PREFIX_DATA;
3ffd33cf
AM		 12285 }
12286 }
12287
8bb15339 12288 if (need_modrm)
252b5132
RH		 12289 {
12290 FETCH_DATA (info, codep + 1);
7967e09e
L		 12291 modrm.mod = (*codep >> 6) & 3;
12292 modrm.reg = (*codep >> 3) & 7;
12293 modrm.rm = *codep & 7;
252b5132
RH		 12294 }
12295
55b126d4
L		 12296 need_vex = 0;
12297 need_vex_reg = 0;
12298 vex_w_done = 0;
12299
ce518a5f 12300 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 12301 {
12302 dofloat (sizeflag);
12303 }
12304 else
12305 {
8bb15339 12306 dp = get_valid_dis386 (dp, info);
b844680a 12307 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 12308 {
12309 for (i = 0; i < MAX_OPERANDS; ++i)
12310 {
246c51aa 12311 obufp = op_out[i];
ce518a5f
L		 12312 op_ad = MAX_OPERANDS - 1 - i;
12313 if (dp->op[i].rtn)
12314 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12315 }
6439fc28 12316 }
252b5132
RH		 12317 }
12318
7d421014
ILT		 12319 /* See if any prefixes were not used. If so, print the first one
12320 separately. If we don't do this, we'll wind up printing an
12321 instruction stream which does not precisely correspond to the
12322 bytes we are disassembling. */
f16cd0d5 12323 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
7d421014 12324 {
f16cd0d5
L		 12325 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12326 if (all_prefixes[i])
12327 {
12328 const char *name;
12329 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12330 if (name == NULL)
12331 name = INTERNAL_DISASSEMBLER_ERROR;
12332 (*info->fprintf_func) (info->stream, "%s", name);
12333 return 1;
12334 }
52b15da3 12335 }
7d421014 12336
f16cd0d5 12337 /* Check if the REX prefix used. */
2a70cca4 12338 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
f16cd0d5
L		 12339 all_prefixes[last_rex_prefix] = 0;
12340
12341 /* Check if the SEG prefix used. */
12342 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12343 | PREFIX_FS | PREFIX_GS)) != 0
12344 && (used_prefixes
12345 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12346 all_prefixes[last_seg_prefix] = 0;
12347
12348 /* Check if the ADDR prefix used. */
12349 if ((prefixes & PREFIX_ADDR) != 0
12350 && (used_prefixes & PREFIX_ADDR) != 0)
12351 all_prefixes[last_addr_prefix] = 0;
12352
12353 /* Check if the DATA prefix used. */
12354 if ((prefixes & PREFIX_DATA) != 0
12355 && (used_prefixes & PREFIX_DATA) != 0)
12356 all_prefixes[last_data_prefix] = 0;
12357
12358 prefix_length = 0;
f310f33d 12359 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
f16cd0d5
L		 12360 if (all_prefixes[i])
12361 {
12362 const char *name;
12363 name = prefix_name (all_prefixes[i], sizeflag);
12364 if (name == NULL)
12365 abort ();
12366 prefix_length += strlen (name) + 1;
12367 (*info->fprintf_func) (info->stream, "%s ", name);
12368 }
b844680a 12369
f16cd0d5
L		 12370 /* Check maximum code length. */
12371 if ((codep - start_codep) > MAX_CODE_LENGTH)
12372 {
12373 (*info->fprintf_func) (info->stream, "(bad)");
12374 return MAX_CODE_LENGTH;
12375 }
b844680a 12376
ea397f5b 12377 obufp = mnemonicendp;
f16cd0d5 12378 for (i = strlen (obuf) + prefix_length; i < 6; i++)
252b5132
RH		 12379 oappend (" ");
12380 oappend (" ");
12381 (*info->fprintf_func) (info->stream, "%s", obuf);
12382
12383 /* The enter and bound instructions are printed with operands in the same
12384 order as the intel book; everything else is printed in reverse order. */
2da11e11 12385 if (intel_syntax || two_source_ops)
252b5132 12386 {
185b1163
L		 12387 bfd_vma riprel;
12388
ce518a5f
L		 12389 for (i = 0; i < MAX_OPERANDS; ++i)
12390 op_txt[i] = op_out[i];
246c51aa 12391
ce518a5f
L		 12392 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12393 {
12394 op_ad = op_index[i];
12395 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12396 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 12397 riprel = op_riprel[i];
12398 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12399 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 12400 }
252b5132
RH		 12401 }
12402 else
12403 {
ce518a5f
L		 12404 for (i = 0; i < MAX_OPERANDS; ++i)
12405 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 12406 }
12407
ce518a5f
L		 12408 needcomma = 0;
12409 for (i = 0; i < MAX_OPERANDS; ++i)
12410 if (*op_txt[i])
12411 {
12412 if (needcomma)
12413 (*info->fprintf_func) (info->stream, ",");
12414 if (op_index[i] != -1 && !op_riprel[i])
12415 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12416 else
12417 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12418 needcomma = 1;
12419 }
050dfa73 12420
ce518a5f 12421 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 12422 if (op_index[i] != -1 && op_riprel[i])
12423 {
12424 (*info->fprintf_func) (info->stream, " # ");
12425 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12426 + op_address[op_index[i]]), info);
185b1163 12427 break;
52b15da3 12428 }
e396998b 12429 return codep - priv.the_buffer;
252b5132
RH		 12430}
12431
6439fc28 12432static const char *float_mem[] = {
252b5132 12433 /* d8 */
7c52e0e8
L		 12434 "fadd{s|}",
12435 "fmul{s|}",
12436 "fcom{s|}",
12437 "fcomp{s|}",
12438 "fsub{s|}",
12439 "fsubr{s|}",
12440 "fdiv{s|}",
12441 "fdivr{s|}",
db6eb5be 12442 /* d9 */
7c52e0e8 12443 "fld{s|}",
252b5132 12444 "(bad)",
7c52e0e8
L		 12445 "fst{s|}",
12446 "fstp{s|}",
9306ca4a 12447 "fldenvIC",
252b5132 12448 "fldcw",
9306ca4a 12449 "fNstenvIC",
252b5132
RH		 12450 "fNstcw",
12451 /* da */
7c52e0e8
L		 12452 "fiadd{l|}",
12453 "fimul{l|}",
12454 "ficom{l|}",
12455 "ficomp{l|}",
12456 "fisub{l|}",
12457 "fisubr{l|}",
12458 "fidiv{l|}",
12459 "fidivr{l|}",
252b5132 12460 /* db */
7c52e0e8
L		 12461 "fild{l|}",
12462 "fisttp{l|}",
12463 "fist{l|}",
12464 "fistp{l|}",
252b5132 12465 "(bad)",
6439fc28 12466 "fld{t||t|}",
252b5132 12467 "(bad)",
6439fc28 12468 "fstp{t||t|}",
252b5132 12469 /* dc */
7c52e0e8
L		 12470 "fadd{l|}",
12471 "fmul{l|}",
12472 "fcom{l|}",
12473 "fcomp{l|}",
12474 "fsub{l|}",
12475 "fsubr{l|}",
12476 "fdiv{l|}",
12477 "fdivr{l|}",
252b5132 12478 /* dd */
7c52e0e8
L		 12479 "fld{l|}",
12480 "fisttp{ll|}",
12481 "fst{l||}",
12482 "fstp{l|}",
9306ca4a 12483 "frstorIC",
252b5132 12484 "(bad)",
9306ca4a 12485 "fNsaveIC",
252b5132
RH		 12486 "fNstsw",
12487 /* de */
12488 "fiadd",
12489 "fimul",
12490 "ficom",
12491 "ficomp",
12492 "fisub",
12493 "fisubr",
12494 "fidiv",
12495 "fidivr",
12496 /* df */
12497 "fild",
ca164297 12498 "fisttp",
252b5132
RH		 12499 "fist",
12500 "fistp",
12501 "fbld",
7c52e0e8 12502 "fild{ll|}",
252b5132 12503 "fbstp",
7c52e0e8 12504 "fistp{ll|}",
1d9f512f
AM		 12505};
12506
12507static const unsigned char float_mem_mode[] = {
12508 /* d8 */
12509 d_mode,
12510 d_mode,
12511 d_mode,
12512 d_mode,
12513 d_mode,
12514 d_mode,
12515 d_mode,
12516 d_mode,
12517 /* d9 */
12518 d_mode,
12519 0,
12520 d_mode,
12521 d_mode,
12522 0,
12523 w_mode,
12524 0,
12525 w_mode,
12526 /* da */
12527 d_mode,
12528 d_mode,
12529 d_mode,
12530 d_mode,
12531 d_mode,
12532 d_mode,
12533 d_mode,
12534 d_mode,
12535 /* db */
12536 d_mode,
12537 d_mode,
12538 d_mode,
12539 d_mode,
12540 0,
9306ca4a 12541 t_mode,
1d9f512f 12542 0,
9306ca4a 12543 t_mode,
1d9f512f
AM		 12544 /* dc */
12545 q_mode,
12546 q_mode,
12547 q_mode,
12548 q_mode,
12549 q_mode,
12550 q_mode,
12551 q_mode,
12552 q_mode,
12553 /* dd */
12554 q_mode,
12555 q_mode,
12556 q_mode,
12557 q_mode,
12558 0,
12559 0,
12560 0,
12561 w_mode,
12562 /* de */
12563 w_mode,
12564 w_mode,
12565 w_mode,
12566 w_mode,
12567 w_mode,
12568 w_mode,
12569 w_mode,
12570 w_mode,
12571 /* df */
12572 w_mode,
12573 w_mode,
12574 w_mode,
12575 w_mode,
9306ca4a 12576 t_mode,
1d9f512f 12577 q_mode,
9306ca4a 12578 t_mode,
1d9f512f 12579 q_mode
252b5132
RH		 12580};
12581
ce518a5f
L		 12582#define ST { OP_ST, 0 }
12583#define STi { OP_STi, 0 }
252b5132 12584
4efba78c
L		 12585#define FGRPd9_2 NULL, { { NULL, 0 } }
12586#define FGRPd9_4 NULL, { { NULL, 1 } }
12587#define FGRPd9_5 NULL, { { NULL, 2 } }
12588#define FGRPd9_6 NULL, { { NULL, 3 } }
12589#define FGRPd9_7 NULL, { { NULL, 4 } }
12590#define FGRPda_5 NULL, { { NULL, 5 } }
12591#define FGRPdb_4 NULL, { { NULL, 6 } }
12592#define FGRPde_3 NULL, { { NULL, 7 } }
12593#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 12594
2da11e11 12595static const struct dis386 float_reg[][8] = {
252b5132
RH		 12596 /* d8 */
12597 {
ce518a5f
L		 12598 { "fadd", { ST, STi } },
12599 { "fmul", { ST, STi } },
12600 { "fcom", { STi } },
12601 { "fcomp", { STi } },
12602 { "fsub", { ST, STi } },
12603 { "fsubr", { ST, STi } },
12604 { "fdiv", { ST, STi } },
12605 { "fdivr", { ST, STi } },
252b5132
RH		 12606 },
12607 /* d9 */
12608 {
ce518a5f
L		 12609 { "fld", { STi } },
12610 { "fxch", { STi } },
252b5132 12611 { FGRPd9_2 },
ce518a5f 12612 { "(bad)", { XX } },
252b5132
RH		 12613 { FGRPd9_4 },
12614 { FGRPd9_5 },
12615 { FGRPd9_6 },
12616 { FGRPd9_7 },
12617 },
12618 /* da */
12619 {
ce518a5f
L		 12620 { "fcmovb", { ST, STi } },
12621 { "fcmove", { ST, STi } },
12622 { "fcmovbe",{ ST, STi } },
12623 { "fcmovu", { ST, STi } },
12624 { "(bad)", { XX } },
252b5132 12625 { FGRPda_5 },
ce518a5f
L		 12626 { "(bad)", { XX } },
12627 { "(bad)", { XX } },
252b5132
RH		 12628 },
12629 /* db */
12630 {
ce518a5f
L		 12631 { "fcmovnb",{ ST, STi } },
12632 { "fcmovne",{ ST, STi } },
12633 { "fcmovnbe",{ ST, STi } },
12634 { "fcmovnu",{ ST, STi } },
252b5132 12635 { FGRPdb_4 },
ce518a5f
L		 12636 { "fucomi", { ST, STi } },
12637 { "fcomi", { ST, STi } },
12638 { "(bad)", { XX } },
252b5132
RH		 12639 },
12640 /* dc */
12641 {
ce518a5f
L		 12642 { "fadd", { STi, ST } },
12643 { "fmul", { STi, ST } },
12644 { "(bad)", { XX } },
12645 { "(bad)", { XX } },
9d141669
L		 12646 { "fsub!M", { STi, ST } },
12647 { "fsubM", { STi, ST } },
12648 { "fdiv!M", { STi, ST } },
12649 { "fdivM", { STi, ST } },
252b5132
RH		 12650 },
12651 /* dd */
12652 {
ce518a5f
L		 12653 { "ffree", { STi } },
12654 { "(bad)", { XX } },
12655 { "fst", { STi } },
12656 { "fstp", { STi } },
12657 { "fucom", { STi } },
12658 { "fucomp", { STi } },
12659 { "(bad)", { XX } },
12660 { "(bad)", { XX } },
252b5132
RH		 12661 },
12662 /* de */
12663 {
ce518a5f
L		 12664 { "faddp", { STi, ST } },
12665 { "fmulp", { STi, ST } },
12666 { "(bad)", { XX } },
252b5132 12667 { FGRPde_3 },
9d141669
L		 12668 { "fsub!Mp", { STi, ST } },
12669 { "fsubMp", { STi, ST } },
12670 { "fdiv!Mp", { STi, ST } },
12671 { "fdivMp", { STi, ST } },
252b5132
RH		 12672 },
12673 /* df */
12674 {
ce518a5f
L		 12675 { "ffreep", { STi } },
12676 { "(bad)", { XX } },
12677 { "(bad)", { XX } },
12678 { "(bad)", { XX } },
252b5132 12679 { FGRPdf_4 },
ce518a5f
L		 12680 { "fucomip", { ST, STi } },
12681 { "fcomip", { ST, STi } },
12682 { "(bad)", { XX } },
252b5132
RH		 12683 },
12684};
12685
252b5132
RH		 12686static char *fgrps[][8] = {
12687 /* d9_2 0 */
12688 {
12689 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12690 },
12691
12692 /* d9_4 1 */
12693 {
12694 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12695 },
12696
12697 /* d9_5 2 */
12698 {
12699 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12700 },
12701
12702 /* d9_6 3 */
12703 {
12704 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12705 },
12706
12707 /* d9_7 4 */
12708 {
12709 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12710 },
12711
12712 /* da_5 5 */
12713 {
12714 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12715 },
12716
12717 /* db_4 6 */
12718 {
309d3373
JB		 12719 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12720 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
252b5132
RH		 12721 },
12722
12723 /* de_3 7 */
12724 {
12725 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12726 },
12727
12728 /* df_4 8 */
12729 {
12730 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12731 },
12732};
12733
b6169b20
L		 12734static void
12735swap_operand (void)
12736{
12737 mnemonicendp[0] = '.';
12738 mnemonicendp[1] = 's';
12739 mnemonicendp += 2;
12740}
12741
b844680a
L		 12742static void
12743OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12744 int sizeflag ATTRIBUTE_UNUSED)
12745{
12746 /* Skip mod/rm byte. */
12747 MODRM_CHECK;
12748 codep++;
12749}
12750
252b5132 12751static void
26ca5450 12752dofloat (int sizeflag)
252b5132 12753{
2da11e11 12754 const struct dis386 *dp;
252b5132
RH		 12755 unsigned char floatop;
12756
12757 floatop = codep[-1];
12758
7967e09e 12759 if (modrm.mod != 3)
252b5132 12760 {
7967e09e 12761 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 12762
12763 putop (float_mem[fp_indx], sizeflag);
ce518a5f 12764 obufp = op_out[0];
6e50d963 12765 op_ad = 2;
1d9f512f 12766 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 12767 return;
12768 }
6608db57 12769 /* Skip mod/rm byte. */
4bba6815 12770 MODRM_CHECK;
252b5132
RH		 12771 codep++;
12772
7967e09e 12773 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 12774 if (dp->name == NULL)
12775 {
7967e09e 12776 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 12777
6608db57 12778 /* Instruction fnstsw is only one with strange arg. */
252b5132 12779 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 12780 strcpy (op_out[0], names16[0]);
252b5132
RH		 12781 }
12782 else
12783 {
12784 putop (dp->name, sizeflag);
12785
ce518a5f 12786 obufp = op_out[0];
6e50d963 12787 op_ad = 2;
ce518a5f
L		 12788 if (dp->op[0].rtn)
12789 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 12790
ce518a5f 12791 obufp = op_out[1];
6e50d963 12792 op_ad = 1;
ce518a5f
L		 12793 if (dp->op[1].rtn)
12794 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 12795 }
12796}
12797
252b5132 12798static void
26ca5450 12799OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12800{
422673a9 12801 oappend ("%st" + intel_syntax);
252b5132
RH		 12802}
12803
252b5132 12804static void
26ca5450 12805OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12806{
7967e09e 12807 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 12808 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12809}
12810
6608db57 12811/* Capital letters in template are macros. */
6439fc28 12812static int
d3ce72d0 12813putop (const char *in_template, int sizeflag)
252b5132 12814{
2da11e11 12815 const char *p;
9306ca4a 12816 int alt = 0;
9d141669 12817 int cond = 1;
98b528ac
L		 12818 unsigned int l = 0, len = 1;
12819 char last[4];
12820
12821#define SAVE_LAST(c) \
12822 if (l < len && l < sizeof (last)) \
12823 last[l++] = c; \
12824 else \
12825 abort ();
252b5132 12826
d3ce72d0 12827 for (p = in_template; *p; p++)
252b5132
RH		 12828 {
12829 switch (*p)
12830 {
12831 default:
12832 *obufp++ = *p;
12833 break;
98b528ac
L		 12834 case '%':
12835 len++;
12836 break;
9d141669
L		 12837 case '!':
12838 cond = 0;
12839 break;
6439fc28
AM		 12840 case '{':
12841 alt = 0;
12842 if (intel_syntax)
6439fc28
AM		 12843 {
12844 while (*++p != '|')
7c52e0e8
L		 12845 if (*p == '}' || *p == '\0')
12846 abort ();
6439fc28 12847 }
9306ca4a
JB		 12848 /* Fall through. */
12849 case 'I':
12850 alt = 1;
12851 continue;
6439fc28
AM		 12852 case '|':
12853 while (*++p != '}')
12854 {
12855 if (*p == '\0')
12856 abort ();
12857 }
12858 break;
12859 case '}':
12860 break;
252b5132 12861 case 'A':
db6eb5be
AM		 12862 if (intel_syntax)
12863 break;
7967e09e 12864 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 12865 *obufp++ = 'b';
12866 break;
12867 case 'B':
4b06377f
L		 12868 if (l == 0 && len == 1)
12869 {
12870case_B:
12871 if (intel_syntax)
12872 break;
12873 if (sizeflag & SUFFIX_ALWAYS)
12874 *obufp++ = 'b';
12875 }
12876 else
12877 {
12878 if (l != 1
12879 || len != 2
12880 || last[0] != 'L')
12881 {
12882 SAVE_LAST (*p);
12883 break;
12884 }
12885
12886 if (address_mode == mode_64bit
12887 && !(prefixes & PREFIX_ADDR))
12888 {
12889 *obufp++ = 'a';
12890 *obufp++ = 'b';
12891 *obufp++ = 's';
12892 }
12893
12894 goto case_B;
12895 }
252b5132 12896 break;
9306ca4a
JB		 12897 case 'C':
12898 if (intel_syntax && !alt)
12899 break;
12900 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12901 {
12902 if (sizeflag & DFLAG)
12903 *obufp++ = intel_syntax ? 'd' : 'l';
12904 else
12905 *obufp++ = intel_syntax ? 'w' : 's';
12906 used_prefixes |= (prefixes & PREFIX_DATA);
12907 }
12908 break;
ed7841b3
JB		 12909 case 'D':
12910 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12911 break;
161a04f6 12912 USED_REX (REX_W);
7967e09e 12913 if (modrm.mod == 3)
ed7841b3 12914 {
161a04f6 12915 if (rex & REX_W)
ed7841b3 12916 *obufp++ = 'q';
ed7841b3 12917 else
f16cd0d5
L		 12918 {
12919 if (sizeflag & DFLAG)
12920 *obufp++ = intel_syntax ? 'd' : 'l';
12921 else
12922 *obufp++ = 'w';
12923 used_prefixes |= (prefixes & PREFIX_DATA);
12924 }
ed7841b3
JB		 12925 }
12926 else
12927 *obufp++ = 'w';
12928 break;
252b5132 12929 case 'E': /* For jcxz/jecxz */
cb712a9e 12930 if (address_mode == mode_64bit)
c1a64871
JH		 12931 {
12932 if (sizeflag & AFLAG)
12933 *obufp++ = 'r';
12934 else
12935 *obufp++ = 'e';
12936 }
12937 else
12938 if (sizeflag & AFLAG)
12939 *obufp++ = 'e';
3ffd33cf
AM		 12940 used_prefixes |= (prefixes & PREFIX_ADDR);
12941 break;
12942 case 'F':
db6eb5be
AM		 12943 if (intel_syntax)
12944 break;
e396998b 12945 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 12946 {
12947 if (sizeflag & AFLAG)
cb712a9e 12948 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 12949 else
cb712a9e 12950 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 12951 used_prefixes |= (prefixes & PREFIX_ADDR);
12952 }
252b5132 12953 break;
52fd6d94
JB		 12954 case 'G':
12955 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12956 break;
161a04f6 12957 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 12958 *obufp++ = 'l';
12959 else
12960 *obufp++ = 'w';
161a04f6 12961 if (!(rex & REX_W))
52fd6d94
JB		 12962 used_prefixes |= (prefixes & PREFIX_DATA);
12963 break;
5dd0794d 12964 case 'H':
db6eb5be
AM		 12965 if (intel_syntax)
12966 break;
5dd0794d
AM		 12967 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12968 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12969 {
12970 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12971 *obufp++ = ',';
12972 *obufp++ = 'p';
12973 if (prefixes & PREFIX_DS)
12974 *obufp++ = 't';
12975 else
12976 *obufp++ = 'n';
12977 }
12978 break;
9306ca4a
JB		 12979 case 'J':
12980 if (intel_syntax)
12981 break;
12982 *obufp++ = 'l';
12983 break;
42903f7f
L		 12984 case 'K':
12985 USED_REX (REX_W);
12986 if (rex & REX_W)
12987 *obufp++ = 'q';
12988 else
12989 *obufp++ = 'd';
12990 break;
6dd5059a
L		 12991 case 'Z':
12992 if (intel_syntax)
12993 break;
12994 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12995 {
12996 *obufp++ = 'q';
12997 break;
12998 }
12999 /* Fall through. */
98b528ac 13000 goto case_L;
252b5132 13001 case 'L':
98b528ac
L		 13002 if (l != 0 || len != 1)
13003 {
13004 SAVE_LAST (*p);
13005 break;
13006 }
13007case_L:
db6eb5be
AM		 13008 if (intel_syntax)
13009 break;
252b5132
RH		 13010 if (sizeflag & SUFFIX_ALWAYS)
13011 *obufp++ = 'l';
252b5132 13012 break;
9d141669
L		 13013 case 'M':
13014 if (intel_mnemonic != cond)
13015 *obufp++ = 'r';
13016 break;
252b5132
RH		 13017 case 'N':
13018 if ((prefixes & PREFIX_FWAIT) == 0)
13019 *obufp++ = 'n';
7d421014
ILT		 13020 else
13021 used_prefixes |= PREFIX_FWAIT;
252b5132 13022 break;
52b15da3 13023 case 'O':
161a04f6
L		 13024 USED_REX (REX_W);
13025 if (rex & REX_W)
6439fc28 13026 *obufp++ = 'o';
a35ca55a
JB		 13027 else if (intel_syntax && (sizeflag & DFLAG))
13028 *obufp++ = 'q';
52b15da3
JH		 13029 else
13030 *obufp++ = 'd';
161a04f6 13031 if (!(rex & REX_W))
a35ca55a 13032 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 13033 break;
6439fc28 13034 case 'T':
db6eb5be
AM		 13035 if (intel_syntax)
13036 break;
cb712a9e 13037 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 13038 {
13039 *obufp++ = 'q';
13040 break;
13041 }
6608db57 13042 /* Fall through. */
252b5132 13043 case 'P':
db6eb5be
AM		 13044 if (intel_syntax)
13045 break;
252b5132 13046 if ((prefixes & PREFIX_DATA)
161a04f6 13047 || (rex & REX_W)
e396998b 13048 || (sizeflag & SUFFIX_ALWAYS))
252b5132 13049 {
161a04f6
L		 13050 USED_REX (REX_W);
13051 if (rex & REX_W)
52b15da3 13052 *obufp++ = 'q';
c2419411 13053 else
52b15da3
JH		 13054 {
13055 if (sizeflag & DFLAG)
13056 *obufp++ = 'l';
13057 else
13058 *obufp++ = 'w';
f16cd0d5 13059 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 13060 }
252b5132
RH		 13061 }
13062 break;
6439fc28 13063 case 'U':
db6eb5be
AM		 13064 if (intel_syntax)
13065 break;
cb712a9e 13066 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 13067 {
7967e09e 13068 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 13069 *obufp++ = 'q';
6439fc28
AM		 13070 break;
13071 }
6608db57 13072 /* Fall through. */
98b528ac 13073 goto case_Q;
252b5132 13074 case 'Q':
98b528ac 13075 if (l == 0 && len == 1)
252b5132 13076 {
98b528ac
L		 13077case_Q:
13078 if (intel_syntax && !alt)
13079 break;
13080 USED_REX (REX_W);
13081 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 13082 {
98b528ac
L		 13083 if (rex & REX_W)
13084 *obufp++ = 'q';
52b15da3 13085 else
98b528ac
L		 13086 {
13087 if (sizeflag & DFLAG)
13088 *obufp++ = intel_syntax ? 'd' : 'l';
13089 else
13090 *obufp++ = 'w';
f16cd0d5 13091 used_prefixes |= (prefixes & PREFIX_DATA);
98b528ac 13092 }
52b15da3 13093 }
98b528ac
L		 13094 }
13095 else
13096 {
13097 if (l != 1 || len != 2 || last[0] != 'L')
13098 {
13099 SAVE_LAST (*p);
13100 break;
13101 }
13102 if (intel_syntax
13103 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13104 break;
13105 if ((rex & REX_W))
13106 {
13107 USED_REX (REX_W);
13108 *obufp++ = 'q';
13109 }
13110 else
13111 *obufp++ = 'l';
252b5132
RH		 13112 }
13113 break;
13114 case 'R':
161a04f6
L		 13115 USED_REX (REX_W);
13116 if (rex & REX_W)
a35ca55a
JB		 13117 *obufp++ = 'q';
13118 else if (sizeflag & DFLAG)
c608c12e 13119 {
a35ca55a 13120 if (intel_syntax)
c608c12e 13121 *obufp++ = 'd';
c608c12e 13122 else
a35ca55a 13123 *obufp++ = 'l';
c608c12e 13124 }
252b5132 13125 else
a35ca55a
JB		 13126 *obufp++ = 'w';
13127 if (intel_syntax && !p[1]
161a04f6 13128 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 13129 *obufp++ = 'e';
161a04f6 13130 if (!(rex & REX_W))
52b15da3 13131 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 13132 break;
1a114b12 13133 case 'V':
4b06377f 13134 if (l == 0 && len == 1)
1a114b12 13135 {
4b06377f
L		 13136 if (intel_syntax)
13137 break;
13138 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13139 {
13140 if (sizeflag & SUFFIX_ALWAYS)
13141 *obufp++ = 'q';
13142 break;
13143 }
13144 }
13145 else
13146 {
13147 if (l != 1
13148 || len != 2
13149 || last[0] != 'L')
13150 {
13151 SAVE_LAST (*p);
13152 break;
13153 }
13154
13155 if (rex & REX_W)
13156 {
13157 *obufp++ = 'a';
13158 *obufp++ = 'b';
13159 *obufp++ = 's';
13160 }
1a114b12
JB		 13161 }
13162 /* Fall through. */
4b06377f 13163 goto case_S;
252b5132 13164 case 'S':
4b06377f 13165 if (l == 0 && len == 1)
252b5132 13166 {
4b06377f
L		 13167case_S:
13168 if (intel_syntax)
13169 break;
13170 if (sizeflag & SUFFIX_ALWAYS)
52b15da3 13171 {
4b06377f
L		 13172 if (rex & REX_W)
13173 *obufp++ = 'q';
52b15da3 13174 else
4b06377f
L		 13175 {
13176 if (sizeflag & DFLAG)
13177 *obufp++ = 'l';
13178 else
13179 *obufp++ = 'w';
13180 used_prefixes |= (prefixes & PREFIX_DATA);
13181 }
13182 }
13183 }
13184 else
13185 {
13186 if (l != 1
13187 || len != 2
13188 || last[0] != 'L')
13189 {
13190 SAVE_LAST (*p);
13191 break;
52b15da3 13192 }
4b06377f
L		 13193
13194 if (address_mode == mode_64bit
13195 && !(prefixes & PREFIX_ADDR))
13196 {
13197 *obufp++ = 'a';
13198 *obufp++ = 'b';
13199 *obufp++ = 's';
13200 }
13201
13202 goto case_S;
252b5132 13203 }
252b5132 13204 break;
041bd2e0 13205 case 'X':
c0f3af97
L		 13206 if (l != 0 || len != 1)
13207 {
13208 SAVE_LAST (*p);
13209 break;
13210 }
13211 if (need_vex && vex.prefix)
13212 {
13213 if (vex.prefix == DATA_PREFIX_OPCODE)
13214 *obufp++ = 'd';
13215 else
13216 *obufp++ = 's';
13217 }
041bd2e0 13218 else
f16cd0d5
L		 13219 {
13220 if (prefixes & PREFIX_DATA)
13221 *obufp++ = 'd';
13222 else
13223 *obufp++ = 's';
13224 used_prefixes |= (prefixes & PREFIX_DATA);
13225 }
041bd2e0 13226 break;
76f227a5 13227 case 'Y':
c0f3af97 13228 if (l == 0 && len == 1)
76f227a5 13229 {
c0f3af97
L		 13230 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13231 break;
13232 if (rex & REX_W)
13233 {
13234 USED_REX (REX_W);
13235 *obufp++ = 'q';
13236 }
13237 break;
13238 }
13239 else
13240 {
13241 if (l != 1 || len != 2 || last[0] != 'X')
13242 {
13243 SAVE_LAST (*p);
13244 break;
13245 }
13246 if (!need_vex)
13247 abort ();
13248 if (intel_syntax
13249 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13250 break;
13251 switch (vex.length)
13252 {
13253 case 128:
13254 *obufp++ = 'x';
13255 break;
13256 case 256:
13257 *obufp++ = 'y';
13258 break;
13259 default:
13260 abort ();
13261 }
76f227a5
JH		 13262 }
13263 break;
252b5132 13264 case 'W':
0bfee649 13265 if (l == 0 && len == 1)
a35ca55a 13266 {
0bfee649
L		 13267 /* operand size flag for cwtl, cbtw */
13268 USED_REX (REX_W);
13269 if (rex & REX_W)
13270 {
13271 if (intel_syntax)
13272 *obufp++ = 'd';
13273 else
13274 *obufp++ = 'l';
13275 }
13276 else if (sizeflag & DFLAG)
13277 *obufp++ = 'w';
a35ca55a 13278 else
0bfee649
L		 13279 *obufp++ = 'b';
13280 if (!(rex & REX_W))
13281 used_prefixes |= (prefixes & PREFIX_DATA);
a35ca55a 13282 }
252b5132 13283 else
0bfee649
L		 13284 {
13285 if (l != 1 || len != 2 || last[0] != 'X')
13286 {
13287 SAVE_LAST (*p);
13288 break;
13289 }
13290 if (!need_vex)
13291 abort ();
13292 *obufp++ = vex.w ? 'd': 's';
13293 }
252b5132
RH		 13294 break;
13295 }
9306ca4a 13296 alt = 0;
252b5132
RH		 13297 }
13298 *obufp = 0;
ea397f5b 13299 mnemonicendp = obufp;
6439fc28 13300 return 0;
252b5132
RH		 13301}
13302
13303static void
26ca5450 13304oappend (const char *s)
252b5132 13305{
ea397f5b 13306 obufp = stpcpy (obufp, s);
252b5132
RH		 13307}
13308
13309static void
26ca5450 13310append_seg (void)
252b5132
RH		 13311{
13312 if (prefixes & PREFIX_CS)
7d421014 13313 {
7d421014 13314 used_prefixes |= PREFIX_CS;
d708bcba 13315 oappend ("%cs:" + intel_syntax);
7d421014 13316 }
252b5132 13317 if (prefixes & PREFIX_DS)
7d421014 13318 {
7d421014 13319 used_prefixes |= PREFIX_DS;
d708bcba 13320 oappend ("%ds:" + intel_syntax);
7d421014 13321 }
252b5132 13322 if (prefixes & PREFIX_SS)
7d421014 13323 {
7d421014 13324 used_prefixes |= PREFIX_SS;
d708bcba 13325 oappend ("%ss:" + intel_syntax);
7d421014 13326 }
252b5132 13327 if (prefixes & PREFIX_ES)
7d421014 13328 {
7d421014 13329 used_prefixes |= PREFIX_ES;
d708bcba 13330 oappend ("%es:" + intel_syntax);
7d421014 13331 }
252b5132 13332 if (prefixes & PREFIX_FS)
7d421014 13333 {
7d421014 13334 used_prefixes |= PREFIX_FS;
d708bcba 13335 oappend ("%fs:" + intel_syntax);
7d421014 13336 }
252b5132 13337 if (prefixes & PREFIX_GS)
7d421014 13338 {
7d421014 13339 used_prefixes |= PREFIX_GS;
d708bcba 13340 oappend ("%gs:" + intel_syntax);
7d421014 13341 }
252b5132
RH		 13342}
13343
13344static void
26ca5450 13345OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 13346{
13347 if (!intel_syntax)
13348 oappend ("*");
13349 OP_E (bytemode, sizeflag);
13350}
13351
52b15da3 13352static void
26ca5450 13353print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 13354{
cb712a9e 13355 if (address_mode == mode_64bit)
52b15da3
JH		 13356 {
13357 if (hex)
13358 {
13359 char tmp[30];
13360 int i;
13361 buf[0] = '0';
13362 buf[1] = 'x';
13363 sprintf_vma (tmp, disp);
6608db57 13364 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 13365 strcpy (buf + 2, tmp + i);
13366 }
13367 else
13368 {
13369 bfd_signed_vma v = disp;
13370 char tmp[30];
13371 int i;
13372 if (v < 0)
13373 {
13374 *(buf++) = '-';
13375 v = -disp;
6608db57 13376 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 13377 if (v < 0)
13378 {
13379 strcpy (buf, "9223372036854775808");
13380 return;
13381 }
13382 }
13383 if (!v)
13384 {
13385 strcpy (buf, "0");
13386 return;
13387 }
13388
13389 i = 0;
13390 tmp[29] = 0;
13391 while (v)
13392 {
6608db57 13393 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 13394 v /= 10;
13395 i++;
13396 }
13397 strcpy (buf, tmp + 29 - i);
13398 }
13399 }
13400 else
13401 {
13402 if (hex)
13403 sprintf (buf, "0x%x", (unsigned int) disp);
13404 else
13405 sprintf (buf, "%d", (int) disp);
13406 }
13407}
13408
5d669648
L		 13409/* Put DISP in BUF as signed hex number. */
13410
13411static void
13412print_displacement (char *buf, bfd_vma disp)
13413{
13414 bfd_signed_vma val = disp;
13415 char tmp[30];
13416 int i, j = 0;
13417
13418 if (val < 0)
13419 {
13420 buf[j++] = '-';
13421 val = -disp;
13422
13423 /* Check for possible overflow. */
13424 if (val < 0)
13425 {
13426 switch (address_mode)
13427 {
13428 case mode_64bit:
13429 strcpy (buf + j, "0x8000000000000000");
13430 break;
13431 case mode_32bit:
13432 strcpy (buf + j, "0x80000000");
13433 break;
13434 case mode_16bit:
13435 strcpy (buf + j, "0x8000");
13436 break;
13437 }
13438 return;
13439 }
13440 }
13441
13442 buf[j++] = '0';
13443 buf[j++] = 'x';
13444
0af1713e 13445 sprintf_vma (tmp, (bfd_vma) val);
5d669648
L		 13446 for (i = 0; tmp[i] == '0'; i++)
13447 continue;
13448 if (tmp[i] == '\0')
13449 i--;
13450 strcpy (buf + j, tmp + i);
13451}
13452
3f31e633
JB		 13453static void
13454intel_operand_size (int bytemode, int sizeflag)
13455{
13456 switch (bytemode)
13457 {
13458 case b_mode:
b6169b20 13459 case b_swap_mode:
42903f7f 13460 case dqb_mode:
3f31e633
JB		 13461 oappend ("BYTE PTR ");
13462 break;
13463 case w_mode:
13464 case dqw_mode:
13465 oappend ("WORD PTR ");
13466 break;
1a114b12 13467 case stack_v_mode:
cb712a9e 13468 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 13469 {
13470 oappend ("QWORD PTR ");
3f31e633
JB		 13471 break;
13472 }
13473 /* FALLTHRU */
13474 case v_mode:
b6169b20 13475 case v_swap_mode:
3f31e633 13476 case dq_mode:
161a04f6
L		 13477 USED_REX (REX_W);
13478 if (rex & REX_W)
3f31e633 13479 oappend ("QWORD PTR ");
3f31e633 13480 else
f16cd0d5
L		 13481 {
13482 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13483 oappend ("DWORD PTR ");
13484 else
13485 oappend ("WORD PTR ");
13486 used_prefixes |= (prefixes & PREFIX_DATA);
13487 }
3f31e633 13488 break;
52fd6d94 13489 case z_mode:
161a04f6 13490 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 13491 *obufp++ = 'D';
13492 oappend ("WORD PTR ");
161a04f6 13493 if (!(rex & REX_W))
52fd6d94
JB		 13494 used_prefixes |= (prefixes & PREFIX_DATA);
13495 break;
34b772a6
JB		 13496 case a_mode:
13497 if (sizeflag & DFLAG)
13498 oappend ("QWORD PTR ");
13499 else
13500 oappend ("DWORD PTR ");
13501 used_prefixes |= (prefixes & PREFIX_DATA);
13502 break;
3f31e633 13503 case d_mode:
fa99fab2 13504 case d_swap_mode:
42903f7f 13505 case dqd_mode:
3f31e633
JB		 13506 oappend ("DWORD PTR ");
13507 break;
13508 case q_mode:
b6169b20 13509 case q_swap_mode:
3f31e633
JB		 13510 oappend ("QWORD PTR ");
13511 break;
13512 case m_mode:
cb712a9e 13513 if (address_mode == mode_64bit)
3f31e633
JB		 13514 oappend ("QWORD PTR ");
13515 else
13516 oappend ("DWORD PTR ");
13517 break;
13518 case f_mode:
13519 if (sizeflag & DFLAG)
13520 oappend ("FWORD PTR ");
13521 else
13522 oappend ("DWORD PTR ");
13523 used_prefixes |= (prefixes & PREFIX_DATA);
13524 break;
13525 case t_mode:
13526 oappend ("TBYTE PTR ");
13527 break;
13528 case x_mode:
b6169b20 13529 case x_swap_mode:
c0f3af97
L		 13530 if (need_vex)
13531 {
13532 switch (vex.length)
13533 {
13534 case 128:
13535 oappend ("XMMWORD PTR ");
13536 break;
13537 case 256:
13538 oappend ("YMMWORD PTR ");
13539 break;
13540 default:
13541 abort ();
13542 }
13543 }
13544 else
13545 oappend ("XMMWORD PTR ");
13546 break;
13547 case xmm_mode:
3f31e633
JB		 13548 oappend ("XMMWORD PTR ");
13549 break;
c0f3af97
L		 13550 case xmmq_mode:
13551 if (!need_vex)
13552 abort ();
13553
13554 switch (vex.length)
13555 {
13556 case 128:
13557 oappend ("QWORD PTR ");
13558 break;
13559 case 256:
13560 oappend ("XMMWORD PTR ");
13561 break;
13562 default:
13563 abort ();
13564 }
13565 break;
13566 case ymmq_mode:
13567 if (!need_vex)
13568 abort ();
13569
13570 switch (vex.length)
13571 {
13572 case 128:
13573 oappend ("QWORD PTR ");
13574 break;
13575 case 256:
13576 oappend ("YMMWORD PTR ");
13577 break;
13578 default:
13579 abort ();
13580 }
13581 break;
fb9c77c7
L		 13582 case o_mode:
13583 oappend ("OWORD PTR ");
13584 break;
0bfee649
L		 13585 case vex_w_dq_mode:
13586 if (!need_vex)
13587 abort ();
13588
13589 if (vex.w)
13590 oappend ("QWORD PTR ");
13591 else
13592 oappend ("DWORD PTR ");
13593 break;
3f31e633
JB		 13594 default:
13595 break;
13596 }
13597}
13598
252b5132 13599static void
c0f3af97 13600OP_E_register (int bytemode, int sizeflag)
252b5132 13601{
c0f3af97
L		 13602 int reg = modrm.rm;
13603 const char **names;
252b5132 13604
c0f3af97
L		 13605 USED_REX (REX_B);
13606 if ((rex & REX_B))
13607 reg += 8;
252b5132 13608
b6169b20
L		 13609 if ((sizeflag & SUFFIX_ALWAYS)
13610 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13611 swap_operand ();
13612
c0f3af97 13613 switch (bytemode)
252b5132 13614 {
c0f3af97 13615 case b_mode:
b6169b20 13616 case b_swap_mode:
c0f3af97
L		 13617 USED_REX (0);
13618 if (rex)
13619 names = names8rex;
13620 else
13621 names = names8;
13622 break;
13623 case w_mode:
13624 names = names16;
13625 break;
13626 case d_mode:
13627 names = names32;
13628 break;
13629 case q_mode:
13630 names = names64;
13631 break;
13632 case m_mode:
13633 names = address_mode == mode_64bit ? names64 : names32;
13634 break;
13635 case stack_v_mode:
13636 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 13637 {
c0f3af97 13638 names = names64;
252b5132 13639 break;
252b5132 13640 }
c0f3af97
L		 13641 bytemode = v_mode;
13642 /* FALLTHRU */
13643 case v_mode:
b6169b20 13644 case v_swap_mode:
c0f3af97
L		 13645 case dq_mode:
13646 case dqb_mode:
13647 case dqd_mode:
13648 case dqw_mode:
13649 USED_REX (REX_W);
13650 if (rex & REX_W)
13651 names = names64;
c0f3af97 13652 else
f16cd0d5
L		 13653 {
13654 if ((sizeflag & DFLAG)
13655 || (bytemode != v_mode
13656 && bytemode != v_swap_mode))
13657 names = names32;
13658 else
13659 names = names16;
13660 used_prefixes |= (prefixes & PREFIX_DATA);
13661 }
c0f3af97
L		 13662 break;
13663 case 0:
13664 return;
13665 default:
13666 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 13667 return;
13668 }
c0f3af97
L		 13669 oappend (names[reg]);
13670}
13671
13672static void
c1e679ec 13673OP_E_memory (int bytemode, int sizeflag)
c0f3af97
L		 13674{
13675 bfd_vma disp = 0;
13676 int add = (rex & REX_B) ? 8 : 0;
13677 int riprel = 0;
252b5132 13678
c0f3af97 13679 USED_REX (REX_B);
3f31e633
JB		 13680 if (intel_syntax)
13681 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 13682 append_seg ();
13683
5d669648 13684 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 13685 {
5d669648
L		 13686 /* 32/64 bit address mode */
13687 int havedisp;
252b5132
RH		 13688 int havesib;
13689 int havebase;
0f7da397 13690 int haveindex;
20afcfb7 13691 int needindex;
82c18208 13692 int base, rbase;
91d6fa6a 13693 int vindex = 0;
252b5132
RH		 13694 int scale = 0;
13695
13696 havesib = 0;
13697 havebase = 1;
0f7da397 13698 haveindex = 0;
7967e09e 13699 base = modrm.rm;
252b5132
RH		 13700
13701 if (base == 4)
13702 {
13703 havesib = 1;
13704 FETCH_DATA (the_info, codep + 1);
91d6fa6a 13705 vindex = (*codep >> 3) & 7;
db51cc60 13706 scale = (*codep >> 6) & 3;
252b5132 13707 base = *codep & 7;
161a04f6
L		 13708 USED_REX (REX_X);
13709 if (rex & REX_X)
91d6fa6a
NC		 13710 vindex += 8;
13711 haveindex = vindex != 4;
252b5132
RH		 13712 codep++;
13713 }
82c18208 13714 rbase = base + add;
252b5132 13715
7967e09e 13716 switch (modrm.mod)
252b5132
RH		 13717 {
13718 case 0:
82c18208 13719 if (base == 5)
252b5132
RH		 13720 {
13721 havebase = 0;
cb712a9e 13722 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 13723 riprel = 1;
13724 disp = get32s ();
252b5132
RH		 13725 }
13726 break;
13727 case 1:
13728 FETCH_DATA (the_info, codep + 1);
13729 disp = *codep++;
13730 if ((disp & 0x80) != 0)
13731 disp -= 0x100;
13732 break;
13733 case 2:
52b15da3 13734 disp = get32s ();
252b5132
RH		 13735 break;
13736 }
13737
20afcfb7
L		 13738 /* In 32bit mode, we need index register to tell [offset] from
13739 [eiz*1 + offset]. */
13740 needindex = (havesib
13741 && !havebase
13742 && !haveindex
13743 && address_mode == mode_32bit);
13744 havedisp = (havebase
13745 || needindex
13746 || (havesib && (haveindex || scale != 0)));
5d669648 13747
252b5132 13748 if (!intel_syntax)
82c18208 13749 if (modrm.mod != 0 || base == 5)
db6eb5be 13750 {
5d669648
L		 13751 if (havedisp || riprel)
13752 print_displacement (scratchbuf, disp);
13753 else
13754 print_operand_value (scratchbuf, 1, disp);
db6eb5be 13755 oappend (scratchbuf);
52b15da3
JH		 13756 if (riprel)
13757 {
13758 set_op (disp, 1);
87767711 13759 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 13760 }
db6eb5be 13761 }
2da11e11 13762
87767711
JB		 13763 if (havebase || haveindex || riprel)
13764 used_prefixes |= PREFIX_ADDR;
13765
5d669648 13766 if (havedisp || (intel_syntax && riprel))
252b5132 13767 {
252b5132 13768 *obufp++ = open_char;
52b15da3 13769 if (intel_syntax && riprel)
185b1163
L		 13770 {
13771 set_op (disp, 1);
87767711 13772 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 13773 }
db6eb5be 13774 *obufp = '\0';
252b5132 13775 if (havebase)
cb712a9e 13776 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 13777 ? names64[rbase] : names32[rbase]);
252b5132
RH		 13778 if (havesib)
13779 {
db51cc60
L		 13780 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13781 print index to tell base + index from base. */
13782 if (scale != 0
20afcfb7 13783 || needindex
db51cc60
L		 13784 || haveindex
13785 || (havebase && base != ESP_REG_NUM))
252b5132 13786 {
9306ca4a 13787 if (!intel_syntax || havebase)
db6eb5be 13788 {
9306ca4a
JB		 13789 *obufp++ = separator_char;
13790 *obufp = '\0';
db6eb5be 13791 }
db51cc60
L		 13792 if (haveindex)
13793 oappend (address_mode == mode_64bit
13794 && (sizeflag & AFLAG)
91d6fa6a 13795 ? names64[vindex] : names32[vindex]);
db51cc60
L		 13796 else
13797 oappend (address_mode == mode_64bit
13798 && (sizeflag & AFLAG)
13799 ? index64 : index32);
13800
db6eb5be
AM		 13801 *obufp++ = scale_char;
13802 *obufp = '\0';
13803 sprintf (scratchbuf, "%d", 1 << scale);
13804 oappend (scratchbuf);
13805 }
252b5132 13806 }
185b1163 13807 if (intel_syntax
82c18208 13808 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 13809 {
db51cc60 13810 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 13811 {
13812 *obufp++ = '+';
13813 *obufp = '\0';
13814 }
05203043 13815 else if (modrm.mod != 1 && disp != -disp)
3d456fa1
JB		 13816 {
13817 *obufp++ = '-';
13818 *obufp = '\0';
13819 disp = - (bfd_signed_vma) disp;
13820 }
13821
db51cc60
L		 13822 if (havedisp)
13823 print_displacement (scratchbuf, disp);
13824 else
13825 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 13826 oappend (scratchbuf);
13827 }
252b5132
RH		 13828
13829 *obufp++ = close_char;
db6eb5be 13830 *obufp = '\0';
252b5132
RH		 13831 }
13832 else if (intel_syntax)
db6eb5be 13833 {
82c18208 13834 if (modrm.mod != 0 || base == 5)
db6eb5be 13835 {
252b5132
RH		 13836 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13837 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13838 ;
13839 else
13840 {
d708bcba 13841 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 13842 oappend (":");
13843 }
52b15da3 13844 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 13845 oappend (scratchbuf);
13846 }
13847 }
252b5132
RH		 13848 }
13849 else
f16cd0d5
L		 13850 {
13851 /* 16 bit address mode */
13852 used_prefixes |= prefixes & PREFIX_ADDR;
7967e09e 13853 switch (modrm.mod)
252b5132
RH		 13854 {
13855 case 0:
7967e09e 13856 if (modrm.rm == 6)
252b5132
RH		 13857 {
13858 disp = get16 ();
13859 if ((disp & 0x8000) != 0)
13860 disp -= 0x10000;
13861 }
13862 break;
13863 case 1:
13864 FETCH_DATA (the_info, codep + 1);
13865 disp = *codep++;
13866 if ((disp & 0x80) != 0)
13867 disp -= 0x100;
13868 break;
13869 case 2:
13870 disp = get16 ();
13871 if ((disp & 0x8000) != 0)
13872 disp -= 0x10000;
13873 break;
13874 }
13875
13876 if (!intel_syntax)
7967e09e 13877 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 13878 {
5d669648 13879 print_displacement (scratchbuf, disp);
db6eb5be
AM		 13880 oappend (scratchbuf);
13881 }
252b5132 13882
7967e09e 13883 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 13884 {
13885 *obufp++ = open_char;
db6eb5be 13886 *obufp = '\0';
7967e09e 13887 oappend (index16[modrm.rm]);
5d669648
L		 13888 if (intel_syntax
13889 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 13890 {
5d669648 13891 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 13892 {
13893 *obufp++ = '+';
13894 *obufp = '\0';
13895 }
7967e09e 13896 else if (modrm.mod != 1)
3d456fa1
JB		 13897 {
13898 *obufp++ = '-';
13899 *obufp = '\0';
13900 disp = - (bfd_signed_vma) disp;
13901 }
13902
5d669648 13903 print_displacement (scratchbuf, disp);
3d456fa1
JB		 13904 oappend (scratchbuf);
13905 }
13906
db6eb5be
AM		 13907 *obufp++ = close_char;
13908 *obufp = '\0';
252b5132 13909 }
3d456fa1
JB		 13910 else if (intel_syntax)
13911 {
13912 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13913 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13914 ;
13915 else
13916 {
13917 oappend (names_seg[ds_reg - es_reg]);
13918 oappend (":");
13919 }
13920 print_operand_value (scratchbuf, 1, disp & 0xffff);
13921 oappend (scratchbuf);
13922 }
252b5132
RH		 13923 }
13924}
13925
c0f3af97 13926static void
8b3f93e7 13927OP_E (int bytemode, int sizeflag)
c0f3af97
L		 13928{
13929 /* Skip mod/rm byte. */
13930 MODRM_CHECK;
13931 codep++;
13932
13933 if (modrm.mod == 3)
13934 OP_E_register (bytemode, sizeflag);
13935 else
c1e679ec 13936 OP_E_memory (bytemode, sizeflag);
c0f3af97
L		 13937}
13938
252b5132 13939static void
26ca5450 13940OP_G (int bytemode, int sizeflag)
252b5132 13941{
52b15da3 13942 int add = 0;
161a04f6
L		 13943 USED_REX (REX_R);
13944 if (rex & REX_R)
52b15da3 13945 add += 8;
252b5132
RH		 13946 switch (bytemode)
13947 {
13948 case b_mode:
52b15da3
JH		 13949 USED_REX (0);
13950 if (rex)
7967e09e 13951 oappend (names8rex[modrm.reg + add]);
52b15da3 13952 else
7967e09e 13953 oappend (names8[modrm.reg + add]);
252b5132
RH		 13954 break;
13955 case w_mode:
7967e09e 13956 oappend (names16[modrm.reg + add]);
252b5132
RH		 13957 break;
13958 case d_mode:
7967e09e 13959 oappend (names32[modrm.reg + add]);
52b15da3
JH		 13960 break;
13961 case q_mode:
7967e09e 13962 oappend (names64[modrm.reg + add]);
252b5132
RH		 13963 break;
13964 case v_mode:
9306ca4a 13965 case dq_mode:
42903f7f
L		 13966 case dqb_mode:
13967 case dqd_mode:
9306ca4a 13968 case dqw_mode:
161a04f6
L		 13969 USED_REX (REX_W);
13970 if (rex & REX_W)
7967e09e 13971 oappend (names64[modrm.reg + add]);
252b5132 13972 else
f16cd0d5
L		 13973 {
13974 if ((sizeflag & DFLAG) || bytemode != v_mode)
13975 oappend (names32[modrm.reg + add]);
13976 else
13977 oappend (names16[modrm.reg + add]);
13978 used_prefixes |= (prefixes & PREFIX_DATA);
13979 }
252b5132 13980 break;
90700ea2 13981 case m_mode:
cb712a9e 13982 if (address_mode == mode_64bit)
7967e09e 13983 oappend (names64[modrm.reg + add]);
90700ea2 13984 else
7967e09e 13985 oappend (names32[modrm.reg + add]);
90700ea2 13986 break;
252b5132
RH		 13987 default:
13988 oappend (INTERNAL_DISASSEMBLER_ERROR);
13989 break;
13990 }
13991}
13992
52b15da3 13993static bfd_vma
26ca5450 13994get64 (void)
52b15da3 13995{
5dd0794d 13996 bfd_vma x;
52b15da3 13997#ifdef BFD64
5dd0794d
AM		 13998 unsigned int a;
13999 unsigned int b;
14000
52b15da3
JH		 14001 FETCH_DATA (the_info, codep + 8);
14002 a = *codep++ & 0xff;
14003 a |= (*codep++ & 0xff) << 8;
14004 a |= (*codep++ & 0xff) << 16;
14005 a |= (*codep++ & 0xff) << 24;
5dd0794d 14006 b = *codep++ & 0xff;
52b15da3
JH		 14007 b |= (*codep++ & 0xff) << 8;
14008 b |= (*codep++ & 0xff) << 16;
14009 b |= (*codep++ & 0xff) << 24;
14010 x = a + ((bfd_vma) b << 32);
14011#else
6608db57 14012 abort ();
5dd0794d 14013 x = 0;
52b15da3
JH		 14014#endif
14015 return x;
14016}
14017
14018static bfd_signed_vma
26ca5450 14019get32 (void)
252b5132 14020{
52b15da3 14021 bfd_signed_vma x = 0;
252b5132
RH		 14022
14023 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 14024 x = *codep++ & (bfd_signed_vma) 0xff;
14025 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14026 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14027 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14028 return x;
14029}
14030
14031static bfd_signed_vma
26ca5450 14032get32s (void)
52b15da3
JH		 14033{
14034 bfd_signed_vma x = 0;
14035
14036 FETCH_DATA (the_info, codep + 4);
14037 x = *codep++ & (bfd_signed_vma) 0xff;
14038 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14039 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14040 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14041
14042 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14043
252b5132
RH		 14044 return x;
14045}
14046
14047static int
26ca5450 14048get16 (void)
252b5132
RH		 14049{
14050 int x = 0;
14051
14052 FETCH_DATA (the_info, codep + 2);
14053 x = *codep++ & 0xff;
14054 x |= (*codep++ & 0xff) << 8;
14055 return x;
14056}
14057
14058static void
26ca5450 14059set_op (bfd_vma op, int riprel)
252b5132
RH		 14060{
14061 op_index[op_ad] = op_ad;
cb712a9e 14062 if (address_mode == mode_64bit)
7081ff04
AJ		 14063 {
14064 op_address[op_ad] = op;
14065 op_riprel[op_ad] = riprel;
14066 }
14067 else
14068 {
14069 /* Mask to get a 32-bit address. */
14070 op_address[op_ad] = op & 0xffffffff;
14071 op_riprel[op_ad] = riprel & 0xffffffff;
14072 }
252b5132
RH		 14073}
14074
14075static void
26ca5450 14076OP_REG (int code, int sizeflag)
252b5132 14077{
2da11e11 14078 const char *s;
9b60702d 14079 int add;
161a04f6
L		 14080 USED_REX (REX_B);
14081 if (rex & REX_B)
52b15da3 14082 add = 8;
9b60702d
L		 14083 else
14084 add = 0;
52b15da3
JH		 14085
14086 switch (code)
14087 {
52b15da3
JH		 14088 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14089 case sp_reg: case bp_reg: case si_reg: case di_reg:
14090 s = names16[code - ax_reg + add];
14091 break;
14092 case es_reg: case ss_reg: case cs_reg:
14093 case ds_reg: case fs_reg: case gs_reg:
14094 s = names_seg[code - es_reg + add];
14095 break;
14096 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14097 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14098 USED_REX (0);
14099 if (rex)
14100 s = names8rex[code - al_reg + add];
14101 else
14102 s = names8[code - al_reg];
14103 break;
6439fc28
AM		 14104 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14105 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 14106 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 14107 {
14108 s = names64[code - rAX_reg + add];
14109 break;
14110 }
14111 code += eAX_reg - rAX_reg;
6608db57 14112 /* Fall through. */
52b15da3
JH		 14113 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14114 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 14115 USED_REX (REX_W);
14116 if (rex & REX_W)
52b15da3 14117 s = names64[code - eAX_reg + add];
52b15da3 14118 else
f16cd0d5
L		 14119 {
14120 if (sizeflag & DFLAG)
14121 s = names32[code - eAX_reg + add];
14122 else
14123 s = names16[code - eAX_reg + add];
14124 used_prefixes |= (prefixes & PREFIX_DATA);
14125 }
52b15da3 14126 break;
52b15da3
JH		 14127 default:
14128 s = INTERNAL_DISASSEMBLER_ERROR;
14129 break;
14130 }
14131 oappend (s);
14132}
14133
14134static void
26ca5450 14135OP_IMREG (int code, int sizeflag)
52b15da3
JH		 14136{
14137 const char *s;
252b5132
RH		 14138
14139 switch (code)
14140 {
14141 case indir_dx_reg:
d708bcba 14142 if (intel_syntax)
52fd6d94 14143 s = "dx";
d708bcba 14144 else
db6eb5be 14145 s = "(%dx)";
252b5132
RH		 14146 break;
14147 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14148 case sp_reg: case bp_reg: case si_reg: case di_reg:
14149 s = names16[code - ax_reg];
14150 break;
14151 case es_reg: case ss_reg: case cs_reg:
14152 case ds_reg: case fs_reg: case gs_reg:
14153 s = names_seg[code - es_reg];
14154 break;
14155 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14156 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 14157 USED_REX (0);
14158 if (rex)
14159 s = names8rex[code - al_reg];
14160 else
14161 s = names8[code - al_reg];
252b5132
RH		 14162 break;
14163 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14164 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 14165 USED_REX (REX_W);
14166 if (rex & REX_W)
52b15da3 14167 s = names64[code - eAX_reg];
252b5132 14168 else
f16cd0d5
L		 14169 {
14170 if (sizeflag & DFLAG)
14171 s = names32[code - eAX_reg];
14172 else
14173 s = names16[code - eAX_reg];
14174 used_prefixes |= (prefixes & PREFIX_DATA);
14175 }
252b5132 14176 break;
52fd6d94 14177 case z_mode_ax_reg:
161a04f6 14178 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 14179 s = *names32;
14180 else
14181 s = *names16;
161a04f6 14182 if (!(rex & REX_W))
52fd6d94
JB		 14183 used_prefixes |= (prefixes & PREFIX_DATA);
14184 break;
252b5132
RH		 14185 default:
14186 s = INTERNAL_DISASSEMBLER_ERROR;
14187 break;
14188 }
14189 oappend (s);
14190}
14191
14192static void
26ca5450 14193OP_I (int bytemode, int sizeflag)
252b5132 14194{
52b15da3
JH		 14195 bfd_signed_vma op;
14196 bfd_signed_vma mask = -1;
252b5132
RH		 14197
14198 switch (bytemode)
14199 {
14200 case b_mode:
14201 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 14202 op = *codep++;
14203 mask = 0xff;
14204 break;
14205 case q_mode:
cb712a9e 14206 if (address_mode == mode_64bit)
6439fc28
AM		 14207 {
14208 op = get32s ();
14209 break;
14210 }
6608db57 14211 /* Fall through. */
252b5132 14212 case v_mode:
161a04f6
L		 14213 USED_REX (REX_W);
14214 if (rex & REX_W)
52b15da3 14215 op = get32s ();
252b5132 14216 else
52b15da3 14217 {
f16cd0d5
L		 14218 if (sizeflag & DFLAG)
14219 {
14220 op = get32 ();
14221 mask = 0xffffffff;
14222 }
14223 else
14224 {
14225 op = get16 ();
14226 mask = 0xfffff;
14227 }
14228 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 14229 }
252b5132
RH		 14230 break;
14231 case w_mode:
52b15da3 14232 mask = 0xfffff;
252b5132
RH		 14233 op = get16 ();
14234 break;
9306ca4a
JB		 14235 case const_1_mode:
14236 if (intel_syntax)
14237 oappend ("1");
14238 return;
252b5132
RH		 14239 default:
14240 oappend (INTERNAL_DISASSEMBLER_ERROR);
14241 return;
14242 }
14243
52b15da3
JH		 14244 op &= mask;
14245 scratchbuf[0] = '$';
d708bcba
AM		 14246 print_operand_value (scratchbuf + 1, 1, op);
14247 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 14248 scratchbuf[0] = '\0';
14249}
14250
14251static void
26ca5450 14252OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 14253{
14254 bfd_signed_vma op;
14255 bfd_signed_vma mask = -1;
14256
cb712a9e 14257 if (address_mode != mode_64bit)
6439fc28
AM		 14258 {
14259 OP_I (bytemode, sizeflag);
14260 return;
14261 }
14262
52b15da3
JH		 14263 switch (bytemode)
14264 {
14265 case b_mode:
14266 FETCH_DATA (the_info, codep + 1);
14267 op = *codep++;
14268 mask = 0xff;
14269 break;
14270 case v_mode:
161a04f6
L		 14271 USED_REX (REX_W);
14272 if (rex & REX_W)
52b15da3 14273 op = get64 ();
52b15da3
JH		 14274 else
14275 {
f16cd0d5
L		 14276 if (sizeflag & DFLAG)
14277 {
14278 op = get32 ();
14279 mask = 0xffffffff;
14280 }
14281 else
14282 {
14283 op = get16 ();
14284 mask = 0xfffff;
14285 }
14286 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 14287 }
52b15da3
JH		 14288 break;
14289 case w_mode:
14290 mask = 0xfffff;
14291 op = get16 ();
14292 break;
14293 default:
14294 oappend (INTERNAL_DISASSEMBLER_ERROR);
14295 return;
14296 }
14297
14298 op &= mask;
14299 scratchbuf[0] = '$';
d708bcba
AM		 14300 print_operand_value (scratchbuf + 1, 1, op);
14301 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14302 scratchbuf[0] = '\0';
14303}
14304
14305static void
26ca5450 14306OP_sI (int bytemode, int sizeflag)
252b5132 14307{
52b15da3
JH		 14308 bfd_signed_vma op;
14309 bfd_signed_vma mask = -1;
252b5132
RH		 14310
14311 switch (bytemode)
14312 {
14313 case b_mode:
14314 FETCH_DATA (the_info, codep + 1);
14315 op = *codep++;
14316 if ((op & 0x80) != 0)
14317 op -= 0x100;
52b15da3 14318 mask = 0xffffffff;
252b5132
RH		 14319 break;
14320 case v_mode:
161a04f6
L		 14321 USED_REX (REX_W);
14322 if (rex & REX_W)
52b15da3 14323 op = get32s ();
252b5132
RH		 14324 else
14325 {
f16cd0d5
L		 14326 if (sizeflag & DFLAG)
14327 {
14328 op = get32s ();
14329 mask = 0xffffffff;
14330 }
14331 else
14332 {
14333 mask = 0xffffffff;
14334 op = get16 ();
14335 if ((op & 0x8000) != 0)
14336 op -= 0x10000;
14337 }
14338 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 14339 }
14340 break;
14341 case w_mode:
14342 op = get16 ();
52b15da3 14343 mask = 0xffffffff;
252b5132
RH		 14344 if ((op & 0x8000) != 0)
14345 op -= 0x10000;
14346 break;
14347 default:
14348 oappend (INTERNAL_DISASSEMBLER_ERROR);
14349 return;
14350 }
52b15da3
JH		 14351
14352 scratchbuf[0] = '$';
14353 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 14354 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14355}
14356
14357static void
26ca5450 14358OP_J (int bytemode, int sizeflag)
252b5132 14359{
52b15da3 14360 bfd_vma disp;
7081ff04 14361 bfd_vma mask = -1;
65ca155d 14362 bfd_vma segment = 0;
252b5132
RH		 14363
14364 switch (bytemode)
14365 {
14366 case b_mode:
14367 FETCH_DATA (the_info, codep + 1);
14368 disp = *codep++;
14369 if ((disp & 0x80) != 0)
14370 disp -= 0x100;
14371 break;
14372 case v_mode:
f16cd0d5 14373 USED_REX (REX_W);
161a04f6 14374 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 14375 disp = get32s ();
252b5132
RH		 14376 else
14377 {
14378 disp = get16 ();
206717e8
L		 14379 if ((disp & 0x8000) != 0)
14380 disp -= 0x10000;
65ca155d
L		 14381 /* In 16bit mode, address is wrapped around at 64k within
14382 the same segment. Otherwise, a data16 prefix on a jump
14383 instruction means that the pc is masked to 16 bits after
14384 the displacement is added! */
14385 mask = 0xffff;
14386 if ((prefixes & PREFIX_DATA) == 0)
14387 segment = ((start_pc + codep - start_codep)
14388 & ~((bfd_vma) 0xffff));
252b5132 14389 }
f16cd0d5
L		 14390 if (!(rex & REX_W))
14391 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 14392 break;
14393 default:
14394 oappend (INTERNAL_DISASSEMBLER_ERROR);
14395 return;
14396 }
65ca155d 14397 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 14398 set_op (disp, 0);
14399 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 14400 oappend (scratchbuf);
14401}
14402
252b5132 14403static void
ed7841b3 14404OP_SEG (int bytemode, int sizeflag)
252b5132 14405{
ed7841b3 14406 if (bytemode == w_mode)
7967e09e 14407 oappend (names_seg[modrm.reg]);
ed7841b3 14408 else
7967e09e 14409 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 14410}
14411
14412static void
26ca5450 14413OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 14414{
14415 int seg, offset;
14416
c608c12e 14417 if (sizeflag & DFLAG)
252b5132 14418 {
c608c12e
AM		 14419 offset = get32 ();
14420 seg = get16 ();
252b5132 14421 }
c608c12e
AM		 14422 else
14423 {
14424 offset = get16 ();
14425 seg = get16 ();
14426 }
7d421014 14427 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 14428 if (intel_syntax)
3f31e633 14429 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 14430 else
14431 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 14432 oappend (scratchbuf);
252b5132
RH		 14433}
14434
252b5132 14435static void
3f31e633 14436OP_OFF (int bytemode, int sizeflag)
252b5132 14437{
52b15da3 14438 bfd_vma off;
252b5132 14439
3f31e633
JB		 14440 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14441 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 14442 append_seg ();
14443
cb712a9e 14444 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 14445 off = get32 ();
14446 else
14447 off = get16 ();
14448
14449 if (intel_syntax)
14450 {
14451 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 14452 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 14453 {
d708bcba 14454 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 14455 oappend (":");
14456 }
14457 }
52b15da3
JH		 14458 print_operand_value (scratchbuf, 1, off);
14459 oappend (scratchbuf);
14460}
6439fc28 14461
52b15da3 14462static void
3f31e633 14463OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 14464{
14465 bfd_vma off;
14466
539e75ad
L		 14467 if (address_mode != mode_64bit
14468 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 14469 {
14470 OP_OFF (bytemode, sizeflag);
14471 return;
14472 }
14473
3f31e633
JB		 14474 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14475 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 14476 append_seg ();
14477
6608db57 14478 off = get64 ();
52b15da3
JH		 14479
14480 if (intel_syntax)
14481 {
14482 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 14483 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 14484 {
d708bcba 14485 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 14486 oappend (":");
14487 }
14488 }
14489 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 14490 oappend (scratchbuf);
14491}
14492
14493static void
26ca5450 14494ptr_reg (int code, int sizeflag)
252b5132 14495{
2da11e11 14496 const char *s;
d708bcba 14497
1d9f512f 14498 *obufp++ = open_char;
20f0a1fc 14499 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 14500 if (address_mode == mode_64bit)
c1a64871
JH		 14501 {
14502 if (!(sizeflag & AFLAG))
db6eb5be 14503 s = names32[code - eAX_reg];
c1a64871 14504 else
db6eb5be 14505 s = names64[code - eAX_reg];
c1a64871 14506 }
52b15da3 14507 else if (sizeflag & AFLAG)
252b5132
RH		 14508 s = names32[code - eAX_reg];
14509 else
14510 s = names16[code - eAX_reg];
14511 oappend (s);
1d9f512f
AM		 14512 *obufp++ = close_char;
14513 *obufp = 0;
252b5132
RH		 14514}
14515
14516static void
26ca5450 14517OP_ESreg (int code, int sizeflag)
252b5132 14518{
9306ca4a 14519 if (intel_syntax)
52fd6d94
JB		 14520 {
14521 switch (codep[-1])
14522 {
14523 case 0x6d: /* insw/insl */
14524 intel_operand_size (z_mode, sizeflag);
14525 break;
14526 case 0xa5: /* movsw/movsl/movsq */
14527 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14528 case 0xab: /* stosw/stosl */
14529 case 0xaf: /* scasw/scasl */
14530 intel_operand_size (v_mode, sizeflag);
14531 break;
14532 default:
14533 intel_operand_size (b_mode, sizeflag);
14534 }
14535 }
d708bcba 14536 oappend ("%es:" + intel_syntax);
252b5132
RH		 14537 ptr_reg (code, sizeflag);
14538}
14539
14540static void
26ca5450 14541OP_DSreg (int code, int sizeflag)
252b5132 14542{
9306ca4a 14543 if (intel_syntax)
52fd6d94
JB		 14544 {
14545 switch (codep[-1])
14546 {
14547 case 0x6f: /* outsw/outsl */
14548 intel_operand_size (z_mode, sizeflag);
14549 break;
14550 case 0xa5: /* movsw/movsl/movsq */
14551 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14552 case 0xad: /* lodsw/lodsl/lodsq */
14553 intel_operand_size (v_mode, sizeflag);
14554 break;
14555 default:
14556 intel_operand_size (b_mode, sizeflag);
14557 }
14558 }
252b5132
RH		 14559 if ((prefixes
14560 & (PREFIX_CS
14561 | PREFIX_DS
14562 | PREFIX_SS
14563 | PREFIX_ES
14564 | PREFIX_FS
14565 | PREFIX_GS)) == 0)
14566 prefixes |= PREFIX_DS;
6608db57 14567 append_seg ();
252b5132
RH		 14568 ptr_reg (code, sizeflag);
14569}
14570
252b5132 14571static void
26ca5450 14572OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14573{
9b60702d 14574 int add;
161a04f6 14575 if (rex & REX_R)
c4a530c5 14576 {
161a04f6 14577 USED_REX (REX_R);
c4a530c5
JB		 14578 add = 8;
14579 }
cb712a9e 14580 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 14581 {
f16cd0d5 14582 all_prefixes[last_lock_prefix] = 0;
c4a530c5
JB		 14583 used_prefixes |= PREFIX_LOCK;
14584 add = 8;
14585 }
9b60702d
L		 14586 else
14587 add = 0;
7967e09e 14588 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 14589 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14590}
14591
252b5132 14592static void
26ca5450 14593OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14594{
9b60702d 14595 int add;
161a04f6
L		 14596 USED_REX (REX_R);
14597 if (rex & REX_R)
52b15da3 14598 add = 8;
9b60702d
L		 14599 else
14600 add = 0;
d708bcba 14601 if (intel_syntax)
7967e09e 14602 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 14603 else
7967e09e 14604 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 14605 oappend (scratchbuf);
14606}
14607
252b5132 14608static void
26ca5450 14609OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14610{
7967e09e 14611 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 14612 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14613}
14614
14615static void
6f74c397 14616OP_R (int bytemode, int sizeflag)
252b5132 14617{
7967e09e 14618 if (modrm.mod == 3)
2da11e11
AM		 14619 OP_E (bytemode, sizeflag);
14620 else
6608db57 14621 BadOp ();
252b5132
RH		 14622}
14623
14624static void
26ca5450 14625OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 14626{
041bd2e0
JH		 14627 used_prefixes |= (prefixes & PREFIX_DATA);
14628 if (prefixes & PREFIX_DATA)
20f0a1fc 14629 {
9b60702d 14630 int add;
161a04f6
L		 14631 USED_REX (REX_R);
14632 if (rex & REX_R)
20f0a1fc 14633 add = 8;
9b60702d
L		 14634 else
14635 add = 0;
7967e09e 14636 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 14637 }
041bd2e0 14638 else
7967e09e 14639 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 14640 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14641}
14642
c608c12e 14643static void
c0f3af97 14644OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 14645{
9b60702d 14646 int add;
161a04f6
L		 14647 USED_REX (REX_R);
14648 if (rex & REX_R)
041bd2e0 14649 add = 8;
9b60702d
L		 14650 else
14651 add = 0;
c0f3af97
L		 14652 if (need_vex && bytemode != xmm_mode)
14653 {
14654 switch (vex.length)
14655 {
14656 case 128:
14657 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
14658 break;
14659 case 256:
14660 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
14661 break;
14662 default:
14663 abort ();
14664 }
14665 }
14666 else
14667 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 14668 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 14669}
14670
252b5132 14671static void
26ca5450 14672OP_EM (int bytemode, int sizeflag)
252b5132 14673{
7967e09e 14674 if (modrm.mod != 3)
252b5132 14675 {
b6169b20
L		 14676 if (intel_syntax
14677 && (bytemode == v_mode || bytemode == v_swap_mode))
9306ca4a
JB		 14678 {
14679 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14680 used_prefixes |= (prefixes & PREFIX_DATA);
14681 }
252b5132
RH		 14682 OP_E (bytemode, sizeflag);
14683 return;
14684 }
14685
b6169b20
L		 14686 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14687 swap_operand ();
14688
6608db57 14689 /* Skip mod/rm byte. */
4bba6815 14690 MODRM_CHECK;
252b5132 14691 codep++;
041bd2e0
JH		 14692 used_prefixes |= (prefixes & PREFIX_DATA);
14693 if (prefixes & PREFIX_DATA)
20f0a1fc 14694 {
9b60702d 14695 int add;
20f0a1fc 14696
161a04f6
L		 14697 USED_REX (REX_B);
14698 if (rex & REX_B)
20f0a1fc 14699 add = 8;
9b60702d
L		 14700 else
14701 add = 0;
7967e09e 14702 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 14703 }
041bd2e0 14704 else
7967e09e 14705 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 14706 oappend (scratchbuf + intel_syntax);
252b5132
RH		 14707}
14708
246c51aa
L		 14709/* cvt* are the only instructions in sse2 which have
14710 both SSE and MMX operands and also have 0x66 prefix
14711 in their opcode. 0x66 was originally used to differentiate
14712 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 14713 cvt* separately using OP_EMC and OP_MXC */
14714static void
14715OP_EMC (int bytemode, int sizeflag)
14716{
7967e09e 14717 if (modrm.mod != 3)
4d9567e0
MM		 14718 {
14719 if (intel_syntax && bytemode == v_mode)
14720 {
14721 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14722 used_prefixes |= (prefixes & PREFIX_DATA);
14723 }
14724 OP_E (bytemode, sizeflag);
14725 return;
14726 }
246c51aa 14727
4d9567e0
MM		 14728 /* Skip mod/rm byte. */
14729 MODRM_CHECK;
14730 codep++;
14731 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 14732 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 14733 oappend (scratchbuf + intel_syntax);
14734}
14735
14736static void
14737OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14738{
14739 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 14740 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 14741 oappend (scratchbuf + intel_syntax);
14742}
14743
c608c12e 14744static void
26ca5450 14745OP_EX (int bytemode, int sizeflag)
c608c12e 14746{
9b60702d 14747 int add;
d6f574e0
L		 14748
14749 /* Skip mod/rm byte. */
14750 MODRM_CHECK;
14751 codep++;
14752
7967e09e 14753 if (modrm.mod != 3)
c608c12e 14754 {
c1e679ec 14755 OP_E_memory (bytemode, sizeflag);
c608c12e
AM		 14756 return;
14757 }
d6f574e0 14758
161a04f6
L		 14759 USED_REX (REX_B);
14760 if (rex & REX_B)
041bd2e0 14761 add = 8;
9b60702d
L		 14762 else
14763 add = 0;
c608c12e 14764
b6169b20 14765 if ((sizeflag & SUFFIX_ALWAYS)
fa99fab2
L		 14766 && (bytemode == x_swap_mode
14767 || bytemode == d_swap_mode
14768 || bytemode == q_swap_mode))
b6169b20
L		 14769 swap_operand ();
14770
c0f3af97
L		 14771 if (need_vex
14772 && bytemode != xmm_mode
14773 && bytemode != xmmq_mode)
14774 {
14775 switch (vex.length)
14776 {
14777 case 128:
14778 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
14779 break;
14780 case 256:
14781 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
14782 break;
14783 default:
14784 abort ();
14785 }
14786 }
14787 else
14788 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 14789 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 14790}
14791
252b5132 14792static void
26ca5450 14793OP_MS (int bytemode, int sizeflag)
252b5132 14794{
7967e09e 14795 if (modrm.mod == 3)
2da11e11
AM		 14796 OP_EM (bytemode, sizeflag);
14797 else
6608db57 14798 BadOp ();
252b5132
RH		 14799}
14800
992aaec9 14801static void
26ca5450 14802OP_XS (int bytemode, int sizeflag)
992aaec9 14803{
7967e09e 14804 if (modrm.mod == 3)
992aaec9
AM		 14805 OP_EX (bytemode, sizeflag);
14806 else
6608db57 14807 BadOp ();
992aaec9
AM		 14808}
14809
cc0ec051
AM		 14810static void
14811OP_M (int bytemode, int sizeflag)
14812{
7967e09e 14813 if (modrm.mod == 3)
75413a22
L		 14814 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14815 BadOp ();
cc0ec051
AM		 14816 else
14817 OP_E (bytemode, sizeflag);
14818}
14819
14820static void
14821OP_0f07 (int bytemode, int sizeflag)
14822{
7967e09e 14823 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 14824 BadOp ();
14825 else
14826 OP_E (bytemode, sizeflag);
14827}
14828
46e883c5 14829/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 14830 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 14831
cc0ec051 14832static void
46e883c5 14833NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 14834{
8b38ad71
L		 14835 if ((prefixes & PREFIX_DATA) != 0
14836 || (rex != 0
14837 && rex != 0x48
14838 && address_mode == mode_64bit))
46e883c5
L		 14839 OP_REG (bytemode, sizeflag);
14840 else
14841 strcpy (obuf, "nop");
14842}
14843
14844static void
14845NOP_Fixup2 (int bytemode, int sizeflag)
14846{
8b38ad71
L		 14847 if ((prefixes & PREFIX_DATA) != 0
14848 || (rex != 0
14849 && rex != 0x48
14850 && address_mode == mode_64bit))
46e883c5 14851 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 14852}
14853
84037f8c 14854static const char *const Suffix3DNow[] = {
252b5132
RH		 14855/* 00 */ NULL, NULL, NULL, NULL,
14856/* 04 */ NULL, NULL, NULL, NULL,
14857/* 08 */ NULL, NULL, NULL, NULL,
9e525108 14858/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 14859/* 10 */ NULL, NULL, NULL, NULL,
14860/* 14 */ NULL, NULL, NULL, NULL,
14861/* 18 */ NULL, NULL, NULL, NULL,
9e525108 14862/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 14863/* 20 */ NULL, NULL, NULL, NULL,
14864/* 24 */ NULL, NULL, NULL, NULL,
14865/* 28 */ NULL, NULL, NULL, NULL,
14866/* 2C */ NULL, NULL, NULL, NULL,
14867/* 30 */ NULL, NULL, NULL, NULL,
14868/* 34 */ NULL, NULL, NULL, NULL,
14869/* 38 */ NULL, NULL, NULL, NULL,
14870/* 3C */ NULL, NULL, NULL, NULL,
14871/* 40 */ NULL, NULL, NULL, NULL,
14872/* 44 */ NULL, NULL, NULL, NULL,
14873/* 48 */ NULL, NULL, NULL, NULL,
14874/* 4C */ NULL, NULL, NULL, NULL,
14875/* 50 */ NULL, NULL, NULL, NULL,
14876/* 54 */ NULL, NULL, NULL, NULL,
14877/* 58 */ NULL, NULL, NULL, NULL,
14878/* 5C */ NULL, NULL, NULL, NULL,
14879/* 60 */ NULL, NULL, NULL, NULL,
14880/* 64 */ NULL, NULL, NULL, NULL,
14881/* 68 */ NULL, NULL, NULL, NULL,
14882/* 6C */ NULL, NULL, NULL, NULL,
14883/* 70 */ NULL, NULL, NULL, NULL,
14884/* 74 */ NULL, NULL, NULL, NULL,
14885/* 78 */ NULL, NULL, NULL, NULL,
14886/* 7C */ NULL, NULL, NULL, NULL,
14887/* 80 */ NULL, NULL, NULL, NULL,
14888/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 14889/* 88 */ NULL, NULL, "pfnacc", NULL,
14890/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 14891/* 90 */ "pfcmpge", NULL, NULL, NULL,
14892/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14893/* 98 */ NULL, NULL, "pfsub", NULL,
14894/* 9C */ NULL, NULL, "pfadd", NULL,
14895/* A0 */ "pfcmpgt", NULL, NULL, NULL,
14896/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14897/* A8 */ NULL, NULL, "pfsubr", NULL,
14898/* AC */ NULL, NULL, "pfacc", NULL,
14899/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 14900/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 14901/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 14902/* BC */ NULL, NULL, NULL, "pavgusb",
14903/* C0 */ NULL, NULL, NULL, NULL,
14904/* C4 */ NULL, NULL, NULL, NULL,
14905/* C8 */ NULL, NULL, NULL, NULL,
14906/* CC */ NULL, NULL, NULL, NULL,
14907/* D0 */ NULL, NULL, NULL, NULL,
14908/* D4 */ NULL, NULL, NULL, NULL,
14909/* D8 */ NULL, NULL, NULL, NULL,
14910/* DC */ NULL, NULL, NULL, NULL,
14911/* E0 */ NULL, NULL, NULL, NULL,
14912/* E4 */ NULL, NULL, NULL, NULL,
14913/* E8 */ NULL, NULL, NULL, NULL,
14914/* EC */ NULL, NULL, NULL, NULL,
14915/* F0 */ NULL, NULL, NULL, NULL,
14916/* F4 */ NULL, NULL, NULL, NULL,
14917/* F8 */ NULL, NULL, NULL, NULL,
14918/* FC */ NULL, NULL, NULL, NULL,
14919};
14920
14921static void
26ca5450 14922OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 14923{
14924 const char *mnemonic;
14925
14926 FETCH_DATA (the_info, codep + 1);
14927 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14928 place where an 8-bit immediate would normally go. ie. the last
14929 byte of the instruction. */
ea397f5b 14930 obufp = mnemonicendp;
c608c12e 14931 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 14932 if (mnemonic)
2da11e11 14933 oappend (mnemonic);
252b5132
RH		 14934 else
14935 {
14936 /* Since a variable sized modrm/sib chunk is between the start
14937 of the opcode (0x0f0f) and the opcode suffix, we need to do
14938 all the modrm processing first, and don't know until now that
14939 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 14940 op_out[0][0] = '\0';
14941 op_out[1][0] = '\0';
6608db57 14942 BadOp ();
252b5132 14943 }
ea397f5b 14944 mnemonicendp = obufp;
252b5132 14945}
c608c12e 14946
ea397f5b
L		 14947static struct op simd_cmp_op[] =
14948{
14949 { STRING_COMMA_LEN ("eq") },
14950 { STRING_COMMA_LEN ("lt") },
14951 { STRING_COMMA_LEN ("le") },
14952 { STRING_COMMA_LEN ("unord") },
14953 { STRING_COMMA_LEN ("neq") },
14954 { STRING_COMMA_LEN ("nlt") },
14955 { STRING_COMMA_LEN ("nle") },
14956 { STRING_COMMA_LEN ("ord") }
c608c12e
AM		 14957};
14958
14959static void
ad19981d 14960CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 14961{
14962 unsigned int cmp_type;
14963
14964 FETCH_DATA (the_info, codep + 1);
14965 cmp_type = *codep++ & 0xff;
c0f3af97 14966 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 14967 {
ad19981d 14968 char suffix [3];
ea397f5b 14969 char *p = mnemonicendp - 2;
ad19981d
L		 14970 suffix[0] = p[0];
14971 suffix[1] = p[1];
14972 suffix[2] = '\0';
ea397f5b
L		 14973 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14974 mnemonicendp += simd_cmp_op[cmp_type].len;
c608c12e
AM		 14975 }
14976 else
14977 {
ad19981d
L		 14978 /* We have a reserved extension byte. Output it directly. */
14979 scratchbuf[0] = '$';
14980 print_operand_value (scratchbuf + 1, 1, cmp_type);
14981 oappend (scratchbuf + intel_syntax);
14982 scratchbuf[0] = '\0';
c608c12e
AM		 14983 }
14984}
14985
ca164297 14986static void
b844680a
L		 14987OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14988 int sizeflag ATTRIBUTE_UNUSED)
14989{
14990 /* mwait %eax,%ecx */
14991 if (!intel_syntax)
14992 {
14993 const char **names = (address_mode == mode_64bit
14994 ? names64 : names32);
14995 strcpy (op_out[0], names[0]);
14996 strcpy (op_out[1], names[1]);
14997 two_source_ops = 1;
14998 }
14999 /* Skip mod/rm byte. */
15000 MODRM_CHECK;
15001 codep++;
15002}
15003
15004static void
15005OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15006 int sizeflag ATTRIBUTE_UNUSED)
ca164297 15007{
b844680a
L		 15008 /* monitor %eax,%ecx,%edx" */
15009 if (!intel_syntax)
ca164297 15010 {
b844680a 15011 const char **op1_names;
cb712a9e
L		 15012 const char **names = (address_mode == mode_64bit
15013 ? names64 : names32);
1d9f512f 15014
b844680a
L		 15015 if (!(prefixes & PREFIX_ADDR))
15016 op1_names = (address_mode == mode_16bit
15017 ? names16 : names);
ca164297
L		 15018 else
15019 {
b844680a 15020 /* Remove "addr16/addr32". */
f16cd0d5 15021 all_prefixes[last_addr_prefix] = 0;
b844680a
L		 15022 op1_names = (address_mode != mode_32bit
15023 ? names32 : names16);
15024 used_prefixes |= PREFIX_ADDR;
ca164297 15025 }
b844680a
L		 15026 strcpy (op_out[0], op1_names[0]);
15027 strcpy (op_out[1], names[1]);
15028 strcpy (op_out[2], names[2]);
15029 two_source_ops = 1;
ca164297 15030 }
b844680a
L		 15031 /* Skip mod/rm byte. */
15032 MODRM_CHECK;
15033 codep++;
30123838
JB		 15034}
15035
6608db57
KH		 15036static void
15037BadOp (void)
2da11e11 15038{
6608db57
KH		 15039 /* Throw away prefixes and 1st. opcode byte. */
15040 codep = insn_codep + 1;
2da11e11
AM		 15041 oappend ("(bad)");
15042}
4cc91dba 15043
35c52694
L		 15044static void
15045REP_Fixup (int bytemode, int sizeflag)
15046{
15047 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15048 lods and stos. */
35c52694 15049 if (prefixes & PREFIX_REPZ)
f16cd0d5 15050 all_prefixes[last_repz_prefix] = REP_PREFIX;
35c52694
L		 15051
15052 switch (bytemode)
15053 {
15054 case al_reg:
15055 case eAX_reg:
15056 case indir_dx_reg:
15057 OP_IMREG (bytemode, sizeflag);
15058 break;
15059 case eDI_reg:
15060 OP_ESreg (bytemode, sizeflag);
15061 break;
15062 case eSI_reg:
15063 OP_DSreg (bytemode, sizeflag);
15064 break;
15065 default:
15066 abort ();
15067 break;
15068 }
15069}
f5804c90
L		 15070
15071static void
15072CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15073{
161a04f6
L		 15074 USED_REX (REX_W);
15075 if (rex & REX_W)
f5804c90
L		 15076 {
15077 /* Change cmpxchg8b to cmpxchg16b. */
ea397f5b
L		 15078 char *p = mnemonicendp - 2;
15079 mnemonicendp = stpcpy (p, "16b");
fb9c77c7 15080 bytemode = o_mode;
f5804c90
L		 15081 }
15082 OP_M (bytemode, sizeflag);
15083}
42903f7f
L		 15084
15085static void
15086XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15087{
c0f3af97
L		 15088 if (need_vex)
15089 {
15090 switch (vex.length)
15091 {
15092 case 128:
15093 sprintf (scratchbuf, "%%xmm%d", reg);
15094 break;
15095 case 256:
15096 sprintf (scratchbuf, "%%ymm%d", reg);
15097 break;
15098 default:
15099 abort ();
15100 }
15101 }
15102 else
15103 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 15104 oappend (scratchbuf + intel_syntax);
15105}
381d071f
L		 15106
15107static void
15108CRC32_Fixup (int bytemode, int sizeflag)
15109{
15110 /* Add proper suffix to "crc32". */
ea397f5b 15111 char *p = mnemonicendp;
381d071f
L		 15112
15113 switch (bytemode)
15114 {
15115 case b_mode:
20592a94 15116 if (intel_syntax)
ea397f5b 15117 goto skip;
20592a94 15118
381d071f
L		 15119 *p++ = 'b';
15120 break;
15121 case v_mode:
20592a94 15122 if (intel_syntax)
ea397f5b 15123 goto skip;
20592a94 15124
381d071f
L		 15125 USED_REX (REX_W);
15126 if (rex & REX_W)
15127 *p++ = 'q';
f16cd0d5
L		 15128 else
15129 {
15130 if (sizeflag & DFLAG)
15131 *p++ = 'l';
15132 else
15133 *p++ = 'w';
15134 used_prefixes |= (prefixes & PREFIX_DATA);
15135 }
381d071f
L		 15136 break;
15137 default:
15138 oappend (INTERNAL_DISASSEMBLER_ERROR);
15139 break;
15140 }
ea397f5b 15141 mnemonicendp = p;
381d071f
L		 15142 *p = '\0';
15143
ea397f5b 15144skip:
381d071f
L		 15145 if (modrm.mod == 3)
15146 {
15147 int add;
15148
15149 /* Skip mod/rm byte. */
15150 MODRM_CHECK;
15151 codep++;
15152
15153 USED_REX (REX_B);
15154 add = (rex & REX_B) ? 8 : 0;
15155 if (bytemode == b_mode)
15156 {
15157 USED_REX (0);
15158 if (rex)
15159 oappend (names8rex[modrm.rm + add]);
15160 else
15161 oappend (names8[modrm.rm + add]);
15162 }
15163 else
15164 {
15165 USED_REX (REX_W);
15166 if (rex & REX_W)
15167 oappend (names64[modrm.rm + add]);
15168 else if ((prefixes & PREFIX_DATA))
15169 oappend (names16[modrm.rm + add]);
15170 else
15171 oappend (names32[modrm.rm + add]);
15172 }
15173 }
15174 else
9344ff29 15175 OP_E (bytemode, sizeflag);
381d071f 15176}
85f10a01 15177
eacc9c89
L		 15178static void
15179FXSAVE_Fixup (int bytemode, int sizeflag)
15180{
15181 /* Add proper suffix to "fxsave" and "fxrstor". */
15182 USED_REX (REX_W);
15183 if (rex & REX_W)
15184 {
15185 char *p = mnemonicendp;
15186 *p++ = '6';
15187 *p++ = '4';
15188 *p = '\0';
15189 mnemonicendp = p;
15190 }
15191 OP_M (bytemode, sizeflag);
15192}
15193
c0f3af97
L		 15194/* Display the destination register operand for instructions with
15195 VEX. */
15196
15197static void
15198OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15199{
15200 if (!need_vex)
15201 abort ();
15202
15203 if (!need_vex_reg)
15204 return;
15205
15206 switch (vex.length)
15207 {
15208 case 128:
15209 switch (bytemode)
15210 {
15211 case vex_mode:
15212 case vex128_mode:
15213 break;
15214 default:
15215 abort ();
15216 return;
15217 }
15218
15219 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15220 break;
15221 case 256:
15222 switch (bytemode)
15223 {
15224 case vex_mode:
15225 case vex256_mode:
15226 break;
15227 default:
15228 abort ();
15229 return;
15230 }
15231
15232 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
15233 break;
15234 default:
15235 abort ();
15236 break;
15237 }
15238 oappend (scratchbuf + intel_syntax);
15239}
15240
922d8de8
DR		 15241/* Get the VEX immediate byte without moving codep. */
15242
15243static unsigned char
ccc5981b 15244get_vex_imm8 (int sizeflag, int opnum)
922d8de8
DR		 15245{
15246 int bytes_before_imm = 0;
15247
922d8de8
DR		 15248 if (modrm.mod != 3)
15249 {
15250 /* There are SIB/displacement bytes. */
15251 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
02e647f9 15252 {
922d8de8 15253 /* 32/64 bit address mode */
02e647f9 15254 int base = modrm.rm;
922d8de8
DR		 15255
15256 /* Check SIB byte. */
02e647f9
SP		 15257 if (base == 4)
15258 {
15259 FETCH_DATA (the_info, codep + 1);
15260 base = *codep & 7;
15261 /* When decoding the third source, don't increase
15262 bytes_before_imm as this has already been incremented
15263 by one in OP_E_memory while decoding the second
15264 source operand. */
ccc5981b
SP		 15265 if (opnum == 0)
15266 bytes_before_imm++;
02e647f9
SP		 15267 }
15268
15269 /* Don't increase bytes_before_imm when decoding the third source,
15270 it has already been incremented by OP_E_memory while decoding
15271 the second source operand. */
15272 if (opnum == 0)
15273 {
15274 switch (modrm.mod)
15275 {
15276 case 0:
15277 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15278 SIB == 5, there is a 4 byte displacement. */
15279 if (base != 5)
15280 /* No displacement. */
15281 break;
15282 case 2:
15283 /* 4 byte displacement. */
15284 bytes_before_imm += 4;
15285 break;
15286 case 1:
15287 /* 1 byte displacement. */
15288 bytes_before_imm++;
15289 break;
15290 }
15291 }
15292 }
922d8de8 15293 else
02e647f9
SP		 15294 {
15295 /* 16 bit address mode */
15296 /* Don't increase bytes_before_imm when decoding the third source,
15297 it has already been incremented by OP_E_memory while decoding
15298 the second source operand. */
15299 if (opnum == 0)
15300 {
15301 switch (modrm.mod)
15302 {
15303 case 0:
15304 /* When modrm.rm == 6, there is a 2 byte displacement. */
15305 if (modrm.rm != 6)
15306 /* No displacement. */
15307 break;
15308 case 2:
15309 /* 2 byte displacement. */
15310 bytes_before_imm += 2;
15311 break;
15312 case 1:
15313 /* 1 byte displacement: when decoding the third source,
15314 don't increase bytes_before_imm as this has already
15315 been incremented by one in OP_E_memory while decoding
15316 the second source operand. */
15317 if (opnum == 0)
15318 bytes_before_imm++;
ccc5981b 15319
02e647f9
SP		 15320 break;
15321 }
922d8de8
DR		 15322 }
15323 }
15324 }
15325
15326 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15327 return codep [bytes_before_imm];
15328}
15329
15330static void
15331OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15332{
15333 if (reg == -1 && modrm.mod != 3)
15334 {
15335 OP_E_memory (bytemode, sizeflag);
15336 return;
15337 }
15338 else
15339 {
15340 if (reg == -1)
15341 {
15342 reg = modrm.rm;
15343 USED_REX (REX_B);
15344 if (rex & REX_B)
15345 reg += 8;
15346 }
15347 else if (reg > 7 && address_mode != mode_64bit)
15348 BadOp ();
15349 }
15350
15351 switch (vex.length)
15352 {
15353 case 128:
15354 sprintf (scratchbuf, "%%xmm%d", reg);
15355 break;
15356 case 256:
15357 sprintf (scratchbuf, "%%ymm%d", reg);
15358 break;
15359 default:
15360 abort ();
15361 }
15362 oappend (scratchbuf + intel_syntax);
15363}
15364
5dd85c99
SP		 15365static void
15366OP_Vex_2src (int bytemode, int sizeflag)
15367{
15368 if (modrm.mod == 3)
15369 {
15370 USED_REX (REX_B);
15371 sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm);
15372 oappend (scratchbuf + intel_syntax);
15373 }
15374 else
15375 {
15376 if (intel_syntax
15377 && (bytemode == v_mode || bytemode == v_swap_mode))
15378 {
15379 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15380 used_prefixes |= (prefixes & PREFIX_DATA);
15381 }
15382 OP_E (bytemode, sizeflag);
15383 }
15384}
15385
15386static void
15387OP_Vex_2src_1 (int bytemode, int sizeflag)
15388{
15389 if (modrm.mod == 3)
15390 {
15391 /* Skip mod/rm byte. */
15392 MODRM_CHECK;
15393 codep++;
15394 }
15395
15396 if (vex.w)
15397 {
15398 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15399 oappend (scratchbuf + intel_syntax);
15400 }
15401 else
15402 OP_Vex_2src (bytemode, sizeflag);
15403}
15404
15405static void
15406OP_Vex_2src_2 (int bytemode, int sizeflag)
15407{
15408 if (vex.w)
15409 OP_Vex_2src (bytemode, sizeflag);
15410 else
15411 {
15412 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
15413 oappend (scratchbuf + intel_syntax);
15414 }
15415}
15416
922d8de8
DR		 15417static void
15418OP_EX_VexW (int bytemode, int sizeflag)
15419{
15420 int reg = -1;
15421
15422 if (!vex_w_done)
15423 {
15424 vex_w_done = 1;
41effecb
SP		 15425
15426 /* Skip mod/rm byte. */
15427 MODRM_CHECK;
15428 codep++;
15429
922d8de8 15430 if (vex.w)
ccc5981b 15431 reg = get_vex_imm8 (sizeflag, 0) >> 4;
922d8de8
DR		 15432 }
15433 else
15434 {
15435 if (!vex.w)
ccc5981b 15436 reg = get_vex_imm8 (sizeflag, 1) >> 4;
922d8de8
DR		 15437 }
15438
15439 OP_EX_VexReg (bytemode, sizeflag, reg);
15440}
15441
922d8de8
DR		 15442static void
15443VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
15444 int sizeflag ATTRIBUTE_UNUSED)
15445{
15446 /* Skip the immediate byte and check for invalid bits. */
15447 FETCH_DATA (the_info, codep + 1);
15448 if (*codep++ & 0xf)
15449 BadOp ();
15450}
15451
c0f3af97
L		 15452static void
15453OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15454{
15455 int reg;
15456 FETCH_DATA (the_info, codep + 1);
15457 reg = *codep++;
15458
15459 if (bytemode != x_mode)
15460 abort ();
15461
15462 if (reg & 0xf)
15463 BadOp ();
15464
15465 reg >>= 4;
dae39acc
L		 15466 if (reg > 7 && address_mode != mode_64bit)
15467 BadOp ();
15468
c0f3af97
L		 15469 switch (vex.length)
15470 {
15471 case 128:
15472 sprintf (scratchbuf, "%%xmm%d", reg);
15473 break;
15474 case 256:
15475 sprintf (scratchbuf, "%%ymm%d", reg);
15476 break;
15477 default:
15478 abort ();
15479 }
15480 oappend (scratchbuf + intel_syntax);
15481}
15482
922d8de8
DR		 15483static void
15484OP_XMM_VexW (int bytemode, int sizeflag)
15485{
15486 /* Turn off the REX.W bit since it is used for swapping operands
15487 now. */
15488 rex &= ~REX_W;
15489 OP_XMM (bytemode, sizeflag);
15490}
15491
c0f3af97
L		 15492static void
15493OP_EX_Vex (int bytemode, int sizeflag)
15494{
15495 if (modrm.mod != 3)
15496 {
15497 if (vex.register_specifier != 0)
15498 BadOp ();
15499 need_vex_reg = 0;
15500 }
15501 OP_EX (bytemode, sizeflag);
15502}
15503
15504static void
15505OP_XMM_Vex (int bytemode, int sizeflag)
15506{
15507 if (modrm.mod != 3)
15508 {
15509 if (vex.register_specifier != 0)
15510 BadOp ();
15511 need_vex_reg = 0;
15512 }
15513 OP_XMM (bytemode, sizeflag);
15514}
15515
15516static void
15517VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15518{
15519 switch (vex.length)
15520 {
15521 case 128:
ea397f5b 15522 mnemonicendp = stpcpy (obuf, "vzeroupper");
c0f3af97
L		 15523 break;
15524 case 256:
ea397f5b 15525 mnemonicendp = stpcpy (obuf, "vzeroall");
c0f3af97
L		 15526 break;
15527 default:
15528 abort ();
15529 }
15530}
15531
ea397f5b
L		 15532static struct op vex_cmp_op[] =
15533{
15534 { STRING_COMMA_LEN ("eq") },
15535 { STRING_COMMA_LEN ("lt") },
15536 { STRING_COMMA_LEN ("le") },
15537 { STRING_COMMA_LEN ("unord") },
15538 { STRING_COMMA_LEN ("neq") },
15539 { STRING_COMMA_LEN ("nlt") },
15540 { STRING_COMMA_LEN ("nle") },
15541 { STRING_COMMA_LEN ("ord") },
15542 { STRING_COMMA_LEN ("eq_uq") },
15543 { STRING_COMMA_LEN ("nge") },
15544 { STRING_COMMA_LEN ("ngt") },
15545 { STRING_COMMA_LEN ("false") },
15546 { STRING_COMMA_LEN ("neq_oq") },
15547 { STRING_COMMA_LEN ("ge") },
15548 { STRING_COMMA_LEN ("gt") },
15549 { STRING_COMMA_LEN ("true") },
15550 { STRING_COMMA_LEN ("eq_os") },
15551 { STRING_COMMA_LEN ("lt_oq") },
15552 { STRING_COMMA_LEN ("le_oq") },
15553 { STRING_COMMA_LEN ("unord_s") },
15554 { STRING_COMMA_LEN ("neq_us") },
15555 { STRING_COMMA_LEN ("nlt_uq") },
15556 { STRING_COMMA_LEN ("nle_uq") },
15557 { STRING_COMMA_LEN ("ord_s") },
15558 { STRING_COMMA_LEN ("eq_us") },
15559 { STRING_COMMA_LEN ("nge_uq") },
15560 { STRING_COMMA_LEN ("ngt_uq") },
15561 { STRING_COMMA_LEN ("false_os") },
15562 { STRING_COMMA_LEN ("neq_os") },
15563 { STRING_COMMA_LEN ("ge_oq") },
15564 { STRING_COMMA_LEN ("gt_oq") },
15565 { STRING_COMMA_LEN ("true_us") },
c0f3af97
L		 15566};
15567
15568static void
15569VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15570{
15571 unsigned int cmp_type;
15572
15573 FETCH_DATA (the_info, codep + 1);
15574 cmp_type = *codep++ & 0xff;
15575 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15576 {
15577 char suffix [3];
ea397f5b 15578 char *p = mnemonicendp - 2;
c0f3af97
L		 15579 suffix[0] = p[0];
15580 suffix[1] = p[1];
15581 suffix[2] = '\0';
ea397f5b
L		 15582 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15583 mnemonicendp += vex_cmp_op[cmp_type].len;
c0f3af97
L		 15584 }
15585 else
15586 {
15587 /* We have a reserved extension byte. Output it directly. */
15588 scratchbuf[0] = '$';
15589 print_operand_value (scratchbuf + 1, 1, cmp_type);
15590 oappend (scratchbuf + intel_syntax);
15591 scratchbuf[0] = '\0';
15592 }
15593}
15594
ea397f5b
L		 15595static const struct op pclmul_op[] =
15596{
15597 { STRING_COMMA_LEN ("lql") },
15598 { STRING_COMMA_LEN ("hql") },
15599 { STRING_COMMA_LEN ("lqh") },
15600 { STRING_COMMA_LEN ("hqh") }
c0f3af97
L		 15601};
15602
15603static void
15604PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15605 int sizeflag ATTRIBUTE_UNUSED)
15606{
15607 unsigned int pclmul_type;
15608
15609 FETCH_DATA (the_info, codep + 1);
15610 pclmul_type = *codep++ & 0xff;
15611 switch (pclmul_type)
15612 {
15613 case 0x10:
15614 pclmul_type = 2;
15615 break;
15616 case 0x11:
15617 pclmul_type = 3;
15618 break;
15619 default:
15620 break;
15621 }
15622 if (pclmul_type < ARRAY_SIZE (pclmul_op))
15623 {
15624 char suffix [4];
ea397f5b 15625 char *p = mnemonicendp - 3;
c0f3af97
L		 15626 suffix[0] = p[0];
15627 suffix[1] = p[1];
15628 suffix[2] = p[2];
15629 suffix[3] = '\0';
ea397f5b
L		 15630 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15631 mnemonicendp += pclmul_op[pclmul_type].len;
c0f3af97
L		 15632 }
15633 else
15634 {
15635 /* We have a reserved extension byte. Output it directly. */
15636 scratchbuf[0] = '$';
15637 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15638 oappend (scratchbuf + intel_syntax);
15639 scratchbuf[0] = '\0';
15640 }
15641}
15642
f1f8f695
L		 15643static void
15644MOVBE_Fixup (int bytemode, int sizeflag)
15645{
15646 /* Add proper suffix to "movbe". */
ea397f5b 15647 char *p = mnemonicendp;
f1f8f695
L		 15648
15649 switch (bytemode)
15650 {
15651 case v_mode:
15652 if (intel_syntax)
ea397f5b 15653 goto skip;
f1f8f695
L		 15654
15655 USED_REX (REX_W);
15656 if (sizeflag & SUFFIX_ALWAYS)
15657 {
15658 if (rex & REX_W)
15659 *p++ = 'q';
f1f8f695 15660 else
f16cd0d5
L		 15661 {
15662 if (sizeflag & DFLAG)
15663 *p++ = 'l';
15664 else
15665 *p++ = 'w';
15666 used_prefixes |= (prefixes & PREFIX_DATA);
15667 }
f1f8f695 15668 }
f1f8f695
L		 15669 break;
15670 default:
15671 oappend (INTERNAL_DISASSEMBLER_ERROR);
15672 break;
15673 }
ea397f5b 15674 mnemonicendp = p;
f1f8f695
L		 15675 *p = '\0';
15676
ea397f5b 15677skip:
f1f8f695
L		 15678 OP_M (bytemode, sizeflag);
15679}
f88c9eb0
SP		 15680
15681static void
15682OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15683{
15684 int reg;
15685 const char **names;
15686
15687 /* Skip mod/rm byte. */
15688 MODRM_CHECK;
15689 codep++;
15690
15691 if (vex.w)
15692 names = names64;
15693 else if (vex.length == 256)
15694 names = names32;
15695 else
15696 names = names16;
15697
15698 reg = modrm.rm;
15699 USED_REX (REX_B);
15700 if (rex & REX_B)
15701 reg += 8;
15702
15703 oappend (names[reg]);
15704}
15705
15706static void
15707OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15708{
15709 const char **names;
15710
15711 if (vex.w)
15712 names = names64;
15713 else if (vex.length == 256)
15714 names = names32;
15715 else
15716 names = names16;
15717
15718 oappend (names[vex.register_specifier]);
15719}
15720
15721static void
15722OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
15723{
15724 if (vex.w || vex.length == 256)
15725 OP_I (q_mode, sizeflag);
15726 else
15727 OP_I (w_mode, sizeflag);
15728}
15729
GDB Binutils - Deliverables
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