Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
219d1afa | 2 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 L |
98 | static void VZERO_Fixup (int, int); |
99 | static void VCMP_Fixup (int, int); | |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 251 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 252 | #define Ev { OP_E, v_mode } |
de89d0a3 | 253 | #define Eva { OP_E, va_mode } |
7e8b059b | 254 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 255 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
256 | #define Ed { OP_E, d_mode } |
257 | #define Edq { OP_E, dq_mode } | |
258 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 259 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
260 | #define Edb { OP_E, db_mode } |
261 | #define Edw { OP_E, dw_mode } | |
42903f7f | 262 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 263 | #define Eq { OP_E, q_mode } |
07f5af7d | 264 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
265 | #define indirEp { OP_indirE, f_mode } |
266 | #define stackEv { OP_E, stack_v_mode } | |
267 | #define Em { OP_E, m_mode } | |
268 | #define Ew { OP_E, w_mode } | |
269 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 270 | #define Ma { OP_M, a_mode } |
b844680a | 271 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 272 | #define Md { OP_M, d_mode } |
f1f8f695 | 273 | #define Mo { OP_M, o_mode } |
ce518a5f L |
274 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
275 | #define Mq { OP_M, q_mode } | |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
284 | #define Gw { OP_G, w_mode } | |
6f74c397 | 285 | #define Rd { OP_R, d_mode } |
43234a1e | 286 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 287 | #define Rm { OP_R, m_mode } |
ce518a5f L |
288 | #define Ib { OP_I, b_mode } |
289 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 290 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 291 | #define Iv { OP_I, v_mode } |
7bb15c6f | 292 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
293 | #define Iq { OP_I, q_mode } |
294 | #define Iv64 { OP_I64, v_mode } | |
295 | #define Iw { OP_I, w_mode } | |
296 | #define I1 { OP_I, const_1_mode } | |
297 | #define Jb { OP_J, b_mode } | |
298 | #define Jv { OP_J, v_mode } | |
299 | #define Cm { OP_C, m_mode } | |
300 | #define Dm { OP_D, m_mode } | |
301 | #define Td { OP_T, d_mode } | |
b844680a | 302 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
303 | |
304 | #define RMeAX { OP_REG, eAX_reg } | |
305 | #define RMeBX { OP_REG, eBX_reg } | |
306 | #define RMeCX { OP_REG, eCX_reg } | |
307 | #define RMeDX { OP_REG, eDX_reg } | |
308 | #define RMeSP { OP_REG, eSP_reg } | |
309 | #define RMeBP { OP_REG, eBP_reg } | |
310 | #define RMeSI { OP_REG, eSI_reg } | |
311 | #define RMeDI { OP_REG, eDI_reg } | |
312 | #define RMrAX { OP_REG, rAX_reg } | |
313 | #define RMrBX { OP_REG, rBX_reg } | |
314 | #define RMrCX { OP_REG, rCX_reg } | |
315 | #define RMrDX { OP_REG, rDX_reg } | |
316 | #define RMrSP { OP_REG, rSP_reg } | |
317 | #define RMrBP { OP_REG, rBP_reg } | |
318 | #define RMrSI { OP_REG, rSI_reg } | |
319 | #define RMrDI { OP_REG, rDI_reg } | |
320 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
321 | #define RMCL { OP_REG, cl_reg } |
322 | #define RMDL { OP_REG, dl_reg } | |
323 | #define RMBL { OP_REG, bl_reg } | |
324 | #define RMAH { OP_REG, ah_reg } | |
325 | #define RMCH { OP_REG, ch_reg } | |
326 | #define RMDH { OP_REG, dh_reg } | |
327 | #define RMBH { OP_REG, bh_reg } | |
328 | #define RMAX { OP_REG, ax_reg } | |
329 | #define RMDX { OP_REG, dx_reg } | |
330 | ||
331 | #define eAX { OP_IMREG, eAX_reg } | |
332 | #define eBX { OP_IMREG, eBX_reg } | |
333 | #define eCX { OP_IMREG, eCX_reg } | |
334 | #define eDX { OP_IMREG, eDX_reg } | |
335 | #define eSP { OP_IMREG, eSP_reg } | |
336 | #define eBP { OP_IMREG, eBP_reg } | |
337 | #define eSI { OP_IMREG, eSI_reg } | |
338 | #define eDI { OP_IMREG, eDI_reg } | |
339 | #define AL { OP_IMREG, al_reg } | |
340 | #define CL { OP_IMREG, cl_reg } | |
341 | #define DL { OP_IMREG, dl_reg } | |
342 | #define BL { OP_IMREG, bl_reg } | |
343 | #define AH { OP_IMREG, ah_reg } | |
344 | #define CH { OP_IMREG, ch_reg } | |
345 | #define DH { OP_IMREG, dh_reg } | |
346 | #define BH { OP_IMREG, bh_reg } | |
347 | #define AX { OP_IMREG, ax_reg } | |
348 | #define DX { OP_IMREG, dx_reg } | |
349 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
350 | #define indirDX { OP_IMREG, indir_dx_reg } | |
351 | ||
352 | #define Sw { OP_SEG, w_mode } | |
353 | #define Sv { OP_SEG, v_mode } | |
354 | #define Ap { OP_DIR, 0 } | |
355 | #define Ob { OP_OFF64, b_mode } | |
356 | #define Ov { OP_OFF64, v_mode } | |
357 | #define Xb { OP_DSreg, eSI_reg } | |
358 | #define Xv { OP_DSreg, eSI_reg } | |
359 | #define Xz { OP_DSreg, eSI_reg } | |
360 | #define Yb { OP_ESreg, eDI_reg } | |
361 | #define Yv { OP_ESreg, eDI_reg } | |
362 | #define DSBX { OP_DSreg, eBX_reg } | |
363 | ||
364 | #define es { OP_REG, es_reg } | |
365 | #define ss { OP_REG, ss_reg } | |
366 | #define cs { OP_REG, cs_reg } | |
367 | #define ds { OP_REG, ds_reg } | |
368 | #define fs { OP_REG, fs_reg } | |
369 | #define gs { OP_REG, gs_reg } | |
370 | ||
371 | #define MX { OP_MMX, 0 } | |
372 | #define XM { OP_XMM, 0 } | |
539f890d | 373 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 374 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 375 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 376 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 377 | #define EM { OP_EM, v_mode } |
b6169b20 | 378 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 379 | #define EMd { OP_EM, d_mode } |
14051056 | 380 | #define EMx { OP_EM, x_mode } |
53467f57 | 381 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 382 | #define EXw { OP_EX, w_mode } |
53467f57 | 383 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 384 | #define EXd { OP_EX, d_mode } |
539f890d | 385 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 386 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 387 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
539f890d L |
389 | #define EXqScalar { OP_EX, q_scalar_mode } |
390 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 391 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 392 | #define EXx { OP_EX, x_mode } |
b6169b20 | 393 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 394 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 395 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 396 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 397 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
398 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
399 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
400 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
401 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 402 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
403 | #define EXxmmdw { OP_EX, xmmdw_mode } |
404 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 405 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 406 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 407 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
408 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
409 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
410 | #define MS { OP_MS, v_mode } |
411 | #define XS { OP_XS, v_mode } | |
09335d05 | 412 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 413 | #define MXC { OP_MXC, 0 } |
ce518a5f | 414 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 415 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 416 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 417 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
418 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
419 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 420 | |
c0f3af97 | 421 | #define Vex { OP_VEX, vex_mode } |
539f890d | 422 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 423 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
424 | #define Vex128 { OP_VEX, vex128_mode } |
425 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 426 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 427 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 428 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 429 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 430 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 431 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 432 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
433 | #define EXVexW { OP_EX_VexW, x_mode } |
434 | #define EXdVexW { OP_EX_VexW, d_mode } | |
435 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 436 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 437 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 438 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 439 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
440 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
441 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
442 | #define VZERO { VZERO_Fixup, 0 } | |
443 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e | 444 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 445 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
446 | |
447 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
448 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
449 | ||
450 | #define XMask { OP_Mask, mask_mode } | |
451 | #define MaskG { OP_G, mask_mode } | |
452 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 453 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
454 | #define MaskR { OP_R, mask_mode } |
455 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 456 | |
6c30d220 | 457 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 458 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 459 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 460 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 461 | |
35c52694 | 462 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
463 | #define Xbr { REP_Fixup, eSI_reg } |
464 | #define Xvr { REP_Fixup, eSI_reg } | |
465 | #define Ybr { REP_Fixup, eDI_reg } | |
466 | #define Yvr { REP_Fixup, eDI_reg } | |
467 | #define Yzr { REP_Fixup, eDI_reg } | |
468 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
469 | #define ALr { REP_Fixup, al_reg } | |
470 | #define eAXr { REP_Fixup, eAX_reg } | |
471 | ||
42164a71 L |
472 | /* Used handle HLE prefix for lockable instructions. */ |
473 | #define Ebh1 { HLE_Fixup1, b_mode } | |
474 | #define Evh1 { HLE_Fixup1, v_mode } | |
475 | #define Ebh2 { HLE_Fixup2, b_mode } | |
476 | #define Evh2 { HLE_Fixup2, v_mode } | |
477 | #define Ebh3 { HLE_Fixup3, b_mode } | |
478 | #define Evh3 { HLE_Fixup3, v_mode } | |
479 | ||
7e8b059b | 480 | #define BND { BND_Fixup, 0 } |
04ef582a | 481 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 482 | |
ce518a5f L |
483 | #define cond_jump_flag { NULL, cond_jump_mode } |
484 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 485 | |
252b5132 | 486 | /* bits in sizeflag */ |
252b5132 | 487 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
488 | #define AFLAG 2 |
489 | #define DFLAG 1 | |
490 | ||
51e7da1b L |
491 | enum |
492 | { | |
493 | /* byte operand */ | |
494 | b_mode = 1, | |
495 | /* byte operand with operand swapped */ | |
3873ba12 | 496 | b_swap_mode, |
e3949f17 L |
497 | /* byte operand, sign extend like 'T' suffix */ |
498 | b_T_mode, | |
51e7da1b | 499 | /* operand size depends on prefixes */ |
3873ba12 | 500 | v_mode, |
51e7da1b | 501 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 502 | v_swap_mode, |
de89d0a3 IT |
503 | /* operand size depends on address prefix */ |
504 | va_mode, | |
51e7da1b | 505 | /* word operand */ |
3873ba12 | 506 | w_mode, |
51e7da1b | 507 | /* double word operand */ |
3873ba12 | 508 | d_mode, |
51e7da1b | 509 | /* double word operand with operand swapped */ |
3873ba12 | 510 | d_swap_mode, |
51e7da1b | 511 | /* quad word operand */ |
3873ba12 | 512 | q_mode, |
51e7da1b | 513 | /* quad word operand with operand swapped */ |
3873ba12 | 514 | q_swap_mode, |
51e7da1b | 515 | /* ten-byte operand */ |
3873ba12 | 516 | t_mode, |
43234a1e L |
517 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
518 | broadcast enabled. */ | |
3873ba12 | 519 | x_mode, |
43234a1e L |
520 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
521 | evex_x_gscat_mode, | |
522 | /* Similar to x_mode, but with disabled broadcast. */ | |
523 | evex_x_nobcst_mode, | |
524 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
525 | in EVEX. */ | |
3873ba12 | 526 | x_swap_mode, |
51e7da1b | 527 | /* 16-byte XMM operand */ |
3873ba12 | 528 | xmm_mode, |
43234a1e L |
529 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
530 | memory operand (depending on vector length). Broadcast isn't | |
531 | allowed. */ | |
3873ba12 | 532 | xmmq_mode, |
43234a1e L |
533 | /* Same as xmmq_mode, but broadcast is allowed. */ |
534 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
535 | /* XMM register or byte memory operand */ |
536 | xmm_mb_mode, | |
537 | /* XMM register or word memory operand */ | |
538 | xmm_mw_mode, | |
539 | /* XMM register or double word memory operand */ | |
540 | xmm_md_mode, | |
541 | /* XMM register or quad word memory operand */ | |
542 | xmm_mq_mode, | |
43234a1e L |
543 | /* XMM register or double/quad word memory operand, depending on |
544 | VEX.W. */ | |
545 | xmm_mdq_mode, | |
546 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 547 | xmmdw_mode, |
43234a1e | 548 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 549 | xmmqd_mode, |
43234a1e L |
550 | /* 32-byte YMM operand */ |
551 | ymm_mode, | |
552 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 553 | ymmq_mode, |
6c30d220 L |
554 | /* 32-byte YMM or 16-byte word operand */ |
555 | ymmxmm_mode, | |
51e7da1b | 556 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 557 | m_mode, |
51e7da1b | 558 | /* pair of v_mode operands */ |
3873ba12 L |
559 | a_mode, |
560 | cond_jump_mode, | |
561 | loop_jcxz_mode, | |
7e8b059b | 562 | v_bnd_mode, |
51e7da1b | 563 | /* operand size depends on REX prefixes. */ |
3873ba12 | 564 | dq_mode, |
51e7da1b | 565 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 566 | dqw_mode, |
9f79e886 | 567 | /* bounds operand */ |
7e8b059b | 568 | bnd_mode, |
9f79e886 JB |
569 | /* bounds operand with operand swapped */ |
570 | bnd_swap_mode, | |
51e7da1b | 571 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
572 | f_mode, |
573 | const_1_mode, | |
07f5af7d L |
574 | /* v_mode for indirect branch opcodes. */ |
575 | indir_v_mode, | |
51e7da1b | 576 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 577 | stack_v_mode, |
51e7da1b | 578 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 579 | z_mode, |
51e7da1b | 580 | /* 16-byte operand */ |
3873ba12 | 581 | o_mode, |
51e7da1b | 582 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 583 | dqb_mode, |
1ba585e8 IT |
584 | /* registers like d_mode, memory like b_mode. */ |
585 | db_mode, | |
586 | /* registers like d_mode, memory like w_mode. */ | |
587 | dw_mode, | |
51e7da1b | 588 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 589 | dqd_mode, |
51e7da1b | 590 | /* normal vex mode */ |
3873ba12 | 591 | vex_mode, |
51e7da1b | 592 | /* 128bit vex mode */ |
3873ba12 | 593 | vex128_mode, |
51e7da1b | 594 | /* 256bit vex mode */ |
3873ba12 | 595 | vex256_mode, |
51e7da1b | 596 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 597 | vex_w_dq_mode, |
d55ee72f | 598 | |
6c30d220 L |
599 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
600 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
601 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
602 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
603 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
604 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
605 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
606 | vex_vsib_q_w_d_mode, | |
6c30d220 | 607 | |
539f890d L |
608 | /* scalar, ignore vector length. */ |
609 | scalar_mode, | |
53467f57 IT |
610 | /* like b_mode, ignore vector length. */ |
611 | b_scalar_mode, | |
612 | /* like w_mode, ignore vector length. */ | |
613 | w_scalar_mode, | |
539f890d L |
614 | /* like d_mode, ignore vector length. */ |
615 | d_scalar_mode, | |
616 | /* like d_swap_mode, ignore vector length. */ | |
617 | d_scalar_swap_mode, | |
618 | /* like q_mode, ignore vector length. */ | |
619 | q_scalar_mode, | |
620 | /* like q_swap_mode, ignore vector length. */ | |
621 | q_scalar_swap_mode, | |
622 | /* like vex_mode, ignore vector length. */ | |
623 | vex_scalar_mode, | |
1c480963 L |
624 | /* like vex_w_dq_mode, ignore vector length. */ |
625 | vex_scalar_w_dq_mode, | |
539f890d | 626 | |
43234a1e L |
627 | /* Static rounding. */ |
628 | evex_rounding_mode, | |
629 | /* Supress all exceptions. */ | |
630 | evex_sae_mode, | |
631 | ||
632 | /* Mask register operand. */ | |
633 | mask_mode, | |
1ba585e8 IT |
634 | /* Mask register operand. */ |
635 | mask_bd_mode, | |
43234a1e | 636 | |
3873ba12 L |
637 | es_reg, |
638 | cs_reg, | |
639 | ss_reg, | |
640 | ds_reg, | |
641 | fs_reg, | |
642 | gs_reg, | |
d55ee72f | 643 | |
3873ba12 L |
644 | eAX_reg, |
645 | eCX_reg, | |
646 | eDX_reg, | |
647 | eBX_reg, | |
648 | eSP_reg, | |
649 | eBP_reg, | |
650 | eSI_reg, | |
651 | eDI_reg, | |
d55ee72f | 652 | |
3873ba12 L |
653 | al_reg, |
654 | cl_reg, | |
655 | dl_reg, | |
656 | bl_reg, | |
657 | ah_reg, | |
658 | ch_reg, | |
659 | dh_reg, | |
660 | bh_reg, | |
d55ee72f | 661 | |
3873ba12 L |
662 | ax_reg, |
663 | cx_reg, | |
664 | dx_reg, | |
665 | bx_reg, | |
666 | sp_reg, | |
667 | bp_reg, | |
668 | si_reg, | |
669 | di_reg, | |
d55ee72f | 670 | |
3873ba12 L |
671 | rAX_reg, |
672 | rCX_reg, | |
673 | rDX_reg, | |
674 | rBX_reg, | |
675 | rSP_reg, | |
676 | rBP_reg, | |
677 | rSI_reg, | |
678 | rDI_reg, | |
d55ee72f | 679 | |
3873ba12 L |
680 | z_mode_ax_reg, |
681 | indir_dx_reg | |
51e7da1b | 682 | }; |
252b5132 | 683 | |
51e7da1b L |
684 | enum |
685 | { | |
686 | FLOATCODE = 1, | |
3873ba12 L |
687 | USE_REG_TABLE, |
688 | USE_MOD_TABLE, | |
689 | USE_RM_TABLE, | |
690 | USE_PREFIX_TABLE, | |
691 | USE_X86_64_TABLE, | |
692 | USE_3BYTE_TABLE, | |
f88c9eb0 | 693 | USE_XOP_8F_TABLE, |
3873ba12 L |
694 | USE_VEX_C4_TABLE, |
695 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 696 | USE_VEX_LEN_TABLE, |
43234a1e L |
697 | USE_VEX_W_TABLE, |
698 | USE_EVEX_TABLE | |
51e7da1b | 699 | }; |
6439fc28 | 700 | |
bf890a93 | 701 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 702 | |
bf890a93 IT |
703 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
704 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
705 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
706 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
707 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
708 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
709 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
710 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 711 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 712 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
713 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
714 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
715 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 716 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 717 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 718 | |
51e7da1b L |
719 | enum |
720 | { | |
721 | REG_80 = 0, | |
3873ba12 | 722 | REG_81, |
7148c369 | 723 | REG_83, |
3873ba12 L |
724 | REG_8F, |
725 | REG_C0, | |
726 | REG_C1, | |
727 | REG_C6, | |
728 | REG_C7, | |
729 | REG_D0, | |
730 | REG_D1, | |
731 | REG_D2, | |
732 | REG_D3, | |
733 | REG_F6, | |
734 | REG_F7, | |
735 | REG_FE, | |
736 | REG_FF, | |
737 | REG_0F00, | |
738 | REG_0F01, | |
739 | REG_0F0D, | |
740 | REG_0F18, | |
603555e5 | 741 | REG_0F1E_MOD_3, |
3873ba12 L |
742 | REG_0F71, |
743 | REG_0F72, | |
744 | REG_0F73, | |
745 | REG_0FA6, | |
746 | REG_0FA7, | |
747 | REG_0FAE, | |
748 | REG_0FBA, | |
749 | REG_0FC7, | |
592a252b L |
750 | REG_VEX_0F71, |
751 | REG_VEX_0F72, | |
752 | REG_VEX_0F73, | |
753 | REG_VEX_0FAE, | |
f12dc422 | 754 | REG_VEX_0F38F3, |
f88c9eb0 | 755 | REG_XOP_LWPCB, |
2a2a0f38 QN |
756 | REG_XOP_LWP, |
757 | REG_XOP_TBM_01, | |
43234a1e L |
758 | REG_XOP_TBM_02, |
759 | ||
1ba585e8 | 760 | REG_EVEX_0F71, |
43234a1e L |
761 | REG_EVEX_0F72, |
762 | REG_EVEX_0F73, | |
763 | REG_EVEX_0F38C6, | |
764 | REG_EVEX_0F38C7 | |
51e7da1b | 765 | }; |
1ceb70f8 | 766 | |
51e7da1b L |
767 | enum |
768 | { | |
769 | MOD_8D = 0, | |
42164a71 L |
770 | MOD_C6_REG_7, |
771 | MOD_C7_REG_7, | |
4a357820 MZ |
772 | MOD_FF_REG_3, |
773 | MOD_FF_REG_5, | |
3873ba12 L |
774 | MOD_0F01_REG_0, |
775 | MOD_0F01_REG_1, | |
776 | MOD_0F01_REG_2, | |
777 | MOD_0F01_REG_3, | |
8eab4136 | 778 | MOD_0F01_REG_5, |
3873ba12 L |
779 | MOD_0F01_REG_7, |
780 | MOD_0F12_PREFIX_0, | |
781 | MOD_0F13, | |
782 | MOD_0F16_PREFIX_0, | |
783 | MOD_0F17, | |
784 | MOD_0F18_REG_0, | |
785 | MOD_0F18_REG_1, | |
786 | MOD_0F18_REG_2, | |
787 | MOD_0F18_REG_3, | |
d7189fa5 RM |
788 | MOD_0F18_REG_4, |
789 | MOD_0F18_REG_5, | |
790 | MOD_0F18_REG_6, | |
791 | MOD_0F18_REG_7, | |
7e8b059b L |
792 | MOD_0F1A_PREFIX_0, |
793 | MOD_0F1B_PREFIX_0, | |
794 | MOD_0F1B_PREFIX_1, | |
603555e5 | 795 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
796 | MOD_0F24, |
797 | MOD_0F26, | |
798 | MOD_0F2B_PREFIX_0, | |
799 | MOD_0F2B_PREFIX_1, | |
800 | MOD_0F2B_PREFIX_2, | |
801 | MOD_0F2B_PREFIX_3, | |
802 | MOD_0F51, | |
803 | MOD_0F71_REG_2, | |
804 | MOD_0F71_REG_4, | |
805 | MOD_0F71_REG_6, | |
806 | MOD_0F72_REG_2, | |
807 | MOD_0F72_REG_4, | |
808 | MOD_0F72_REG_6, | |
809 | MOD_0F73_REG_2, | |
810 | MOD_0F73_REG_3, | |
811 | MOD_0F73_REG_6, | |
812 | MOD_0F73_REG_7, | |
813 | MOD_0FAE_REG_0, | |
814 | MOD_0FAE_REG_1, | |
815 | MOD_0FAE_REG_2, | |
816 | MOD_0FAE_REG_3, | |
817 | MOD_0FAE_REG_4, | |
818 | MOD_0FAE_REG_5, | |
819 | MOD_0FAE_REG_6, | |
820 | MOD_0FAE_REG_7, | |
821 | MOD_0FB2, | |
822 | MOD_0FB4, | |
823 | MOD_0FB5, | |
a8484f96 | 824 | MOD_0FC3, |
963f3586 IT |
825 | MOD_0FC7_REG_3, |
826 | MOD_0FC7_REG_4, | |
827 | MOD_0FC7_REG_5, | |
3873ba12 L |
828 | MOD_0FC7_REG_6, |
829 | MOD_0FC7_REG_7, | |
830 | MOD_0FD7, | |
831 | MOD_0FE7_PREFIX_2, | |
832 | MOD_0FF0_PREFIX_3, | |
833 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
834 | MOD_0F38F5_PREFIX_2, |
835 | MOD_0F38F6_PREFIX_0, | |
3873ba12 L |
836 | MOD_62_32BIT, |
837 | MOD_C4_32BIT, | |
838 | MOD_C5_32BIT, | |
592a252b L |
839 | MOD_VEX_0F12_PREFIX_0, |
840 | MOD_VEX_0F13, | |
841 | MOD_VEX_0F16_PREFIX_0, | |
842 | MOD_VEX_0F17, | |
843 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
844 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
845 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
846 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
847 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
848 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
849 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
850 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
851 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
852 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
853 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
854 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
855 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
856 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
857 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
858 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
859 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
860 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
861 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
862 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
863 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
864 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
865 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
866 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
867 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
868 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
869 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
870 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
871 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
872 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
873 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
874 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
875 | MOD_VEX_0F50, |
876 | MOD_VEX_0F71_REG_2, | |
877 | MOD_VEX_0F71_REG_4, | |
878 | MOD_VEX_0F71_REG_6, | |
879 | MOD_VEX_0F72_REG_2, | |
880 | MOD_VEX_0F72_REG_4, | |
881 | MOD_VEX_0F72_REG_6, | |
882 | MOD_VEX_0F73_REG_2, | |
883 | MOD_VEX_0F73_REG_3, | |
884 | MOD_VEX_0F73_REG_6, | |
885 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
886 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
887 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
888 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
889 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
890 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
891 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
892 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
893 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
894 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
895 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
896 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
897 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
898 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
899 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
900 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
901 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
902 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
903 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
904 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
905 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
906 | MOD_VEX_0FAE_REG_2, |
907 | MOD_VEX_0FAE_REG_3, | |
908 | MOD_VEX_0FD7_PREFIX_2, | |
909 | MOD_VEX_0FE7_PREFIX_2, | |
910 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
911 | MOD_VEX_0F381A_PREFIX_2, |
912 | MOD_VEX_0F382A_PREFIX_2, | |
913 | MOD_VEX_0F382C_PREFIX_2, | |
914 | MOD_VEX_0F382D_PREFIX_2, | |
915 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
916 | MOD_VEX_0F382F_PREFIX_2, |
917 | MOD_VEX_0F385A_PREFIX_2, | |
918 | MOD_VEX_0F388C_PREFIX_2, | |
919 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
920 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
921 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
922 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
923 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
924 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
925 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
926 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
927 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
928 | |
929 | MOD_EVEX_0F10_PREFIX_1, | |
930 | MOD_EVEX_0F10_PREFIX_3, | |
931 | MOD_EVEX_0F11_PREFIX_1, | |
932 | MOD_EVEX_0F11_PREFIX_3, | |
933 | MOD_EVEX_0F12_PREFIX_0, | |
934 | MOD_EVEX_0F16_PREFIX_0, | |
935 | MOD_EVEX_0F38C6_REG_1, | |
936 | MOD_EVEX_0F38C6_REG_2, | |
937 | MOD_EVEX_0F38C6_REG_5, | |
938 | MOD_EVEX_0F38C6_REG_6, | |
939 | MOD_EVEX_0F38C7_REG_1, | |
940 | MOD_EVEX_0F38C7_REG_2, | |
941 | MOD_EVEX_0F38C7_REG_5, | |
942 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 943 | }; |
1ceb70f8 | 944 | |
51e7da1b L |
945 | enum |
946 | { | |
42164a71 L |
947 | RM_C6_REG_7 = 0, |
948 | RM_C7_REG_7, | |
949 | RM_0F01_REG_0, | |
3873ba12 L |
950 | RM_0F01_REG_1, |
951 | RM_0F01_REG_2, | |
952 | RM_0F01_REG_3, | |
8eab4136 | 953 | RM_0F01_REG_5, |
3873ba12 | 954 | RM_0F01_REG_7, |
603555e5 | 955 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
956 | RM_0FAE_REG_6, |
957 | RM_0FAE_REG_7 | |
51e7da1b | 958 | }; |
1ceb70f8 | 959 | |
51e7da1b L |
960 | enum |
961 | { | |
962 | PREFIX_90 = 0, | |
603555e5 | 963 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 964 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 965 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 966 | PREFIX_0F09, |
3873ba12 L |
967 | PREFIX_0F10, |
968 | PREFIX_0F11, | |
969 | PREFIX_0F12, | |
970 | PREFIX_0F16, | |
7e8b059b L |
971 | PREFIX_0F1A, |
972 | PREFIX_0F1B, | |
603555e5 | 973 | PREFIX_0F1E, |
3873ba12 L |
974 | PREFIX_0F2A, |
975 | PREFIX_0F2B, | |
976 | PREFIX_0F2C, | |
977 | PREFIX_0F2D, | |
978 | PREFIX_0F2E, | |
979 | PREFIX_0F2F, | |
980 | PREFIX_0F51, | |
981 | PREFIX_0F52, | |
982 | PREFIX_0F53, | |
983 | PREFIX_0F58, | |
984 | PREFIX_0F59, | |
985 | PREFIX_0F5A, | |
986 | PREFIX_0F5B, | |
987 | PREFIX_0F5C, | |
988 | PREFIX_0F5D, | |
989 | PREFIX_0F5E, | |
990 | PREFIX_0F5F, | |
991 | PREFIX_0F60, | |
992 | PREFIX_0F61, | |
993 | PREFIX_0F62, | |
994 | PREFIX_0F6C, | |
995 | PREFIX_0F6D, | |
996 | PREFIX_0F6F, | |
997 | PREFIX_0F70, | |
998 | PREFIX_0F73_REG_3, | |
999 | PREFIX_0F73_REG_7, | |
1000 | PREFIX_0F78, | |
1001 | PREFIX_0F79, | |
1002 | PREFIX_0F7C, | |
1003 | PREFIX_0F7D, | |
1004 | PREFIX_0F7E, | |
1005 | PREFIX_0F7F, | |
c7b8aa3a L |
1006 | PREFIX_0FAE_REG_0, |
1007 | PREFIX_0FAE_REG_1, | |
1008 | PREFIX_0FAE_REG_2, | |
1009 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1010 | PREFIX_MOD_0_0FAE_REG_4, |
1011 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1012 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1013 | PREFIX_MOD_3_0FAE_REG_5, |
de89d0a3 IT |
1014 | PREFIX_MOD_0_0FAE_REG_6, |
1015 | PREFIX_MOD_1_0FAE_REG_6, | |
963f3586 | 1016 | PREFIX_0FAE_REG_7, |
3873ba12 | 1017 | PREFIX_0FB8, |
f12dc422 | 1018 | PREFIX_0FBC, |
3873ba12 L |
1019 | PREFIX_0FBD, |
1020 | PREFIX_0FC2, | |
a8484f96 | 1021 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1022 | PREFIX_MOD_0_0FC7_REG_6, |
1023 | PREFIX_MOD_3_0FC7_REG_6, | |
1024 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1025 | PREFIX_0FD0, |
1026 | PREFIX_0FD6, | |
1027 | PREFIX_0FE6, | |
1028 | PREFIX_0FE7, | |
1029 | PREFIX_0FF0, | |
1030 | PREFIX_0FF7, | |
1031 | PREFIX_0F3810, | |
1032 | PREFIX_0F3814, | |
1033 | PREFIX_0F3815, | |
1034 | PREFIX_0F3817, | |
1035 | PREFIX_0F3820, | |
1036 | PREFIX_0F3821, | |
1037 | PREFIX_0F3822, | |
1038 | PREFIX_0F3823, | |
1039 | PREFIX_0F3824, | |
1040 | PREFIX_0F3825, | |
1041 | PREFIX_0F3828, | |
1042 | PREFIX_0F3829, | |
1043 | PREFIX_0F382A, | |
1044 | PREFIX_0F382B, | |
1045 | PREFIX_0F3830, | |
1046 | PREFIX_0F3831, | |
1047 | PREFIX_0F3832, | |
1048 | PREFIX_0F3833, | |
1049 | PREFIX_0F3834, | |
1050 | PREFIX_0F3835, | |
1051 | PREFIX_0F3837, | |
1052 | PREFIX_0F3838, | |
1053 | PREFIX_0F3839, | |
1054 | PREFIX_0F383A, | |
1055 | PREFIX_0F383B, | |
1056 | PREFIX_0F383C, | |
1057 | PREFIX_0F383D, | |
1058 | PREFIX_0F383E, | |
1059 | PREFIX_0F383F, | |
1060 | PREFIX_0F3840, | |
1061 | PREFIX_0F3841, | |
1062 | PREFIX_0F3880, | |
1063 | PREFIX_0F3881, | |
6c30d220 | 1064 | PREFIX_0F3882, |
a0046408 L |
1065 | PREFIX_0F38C8, |
1066 | PREFIX_0F38C9, | |
1067 | PREFIX_0F38CA, | |
1068 | PREFIX_0F38CB, | |
1069 | PREFIX_0F38CC, | |
1070 | PREFIX_0F38CD, | |
48521003 | 1071 | PREFIX_0F38CF, |
3873ba12 L |
1072 | PREFIX_0F38DB, |
1073 | PREFIX_0F38DC, | |
1074 | PREFIX_0F38DD, | |
1075 | PREFIX_0F38DE, | |
1076 | PREFIX_0F38DF, | |
1077 | PREFIX_0F38F0, | |
1078 | PREFIX_0F38F1, | |
603555e5 | 1079 | PREFIX_0F38F5, |
e2e1fcde | 1080 | PREFIX_0F38F6, |
3873ba12 L |
1081 | PREFIX_0F3A08, |
1082 | PREFIX_0F3A09, | |
1083 | PREFIX_0F3A0A, | |
1084 | PREFIX_0F3A0B, | |
1085 | PREFIX_0F3A0C, | |
1086 | PREFIX_0F3A0D, | |
1087 | PREFIX_0F3A0E, | |
1088 | PREFIX_0F3A14, | |
1089 | PREFIX_0F3A15, | |
1090 | PREFIX_0F3A16, | |
1091 | PREFIX_0F3A17, | |
1092 | PREFIX_0F3A20, | |
1093 | PREFIX_0F3A21, | |
1094 | PREFIX_0F3A22, | |
1095 | PREFIX_0F3A40, | |
1096 | PREFIX_0F3A41, | |
1097 | PREFIX_0F3A42, | |
1098 | PREFIX_0F3A44, | |
1099 | PREFIX_0F3A60, | |
1100 | PREFIX_0F3A61, | |
1101 | PREFIX_0F3A62, | |
1102 | PREFIX_0F3A63, | |
a0046408 | 1103 | PREFIX_0F3ACC, |
48521003 IT |
1104 | PREFIX_0F3ACE, |
1105 | PREFIX_0F3ACF, | |
3873ba12 | 1106 | PREFIX_0F3ADF, |
592a252b L |
1107 | PREFIX_VEX_0F10, |
1108 | PREFIX_VEX_0F11, | |
1109 | PREFIX_VEX_0F12, | |
1110 | PREFIX_VEX_0F16, | |
1111 | PREFIX_VEX_0F2A, | |
1112 | PREFIX_VEX_0F2C, | |
1113 | PREFIX_VEX_0F2D, | |
1114 | PREFIX_VEX_0F2E, | |
1115 | PREFIX_VEX_0F2F, | |
43234a1e L |
1116 | PREFIX_VEX_0F41, |
1117 | PREFIX_VEX_0F42, | |
1118 | PREFIX_VEX_0F44, | |
1119 | PREFIX_VEX_0F45, | |
1120 | PREFIX_VEX_0F46, | |
1121 | PREFIX_VEX_0F47, | |
1ba585e8 | 1122 | PREFIX_VEX_0F4A, |
43234a1e | 1123 | PREFIX_VEX_0F4B, |
592a252b L |
1124 | PREFIX_VEX_0F51, |
1125 | PREFIX_VEX_0F52, | |
1126 | PREFIX_VEX_0F53, | |
1127 | PREFIX_VEX_0F58, | |
1128 | PREFIX_VEX_0F59, | |
1129 | PREFIX_VEX_0F5A, | |
1130 | PREFIX_VEX_0F5B, | |
1131 | PREFIX_VEX_0F5C, | |
1132 | PREFIX_VEX_0F5D, | |
1133 | PREFIX_VEX_0F5E, | |
1134 | PREFIX_VEX_0F5F, | |
1135 | PREFIX_VEX_0F60, | |
1136 | PREFIX_VEX_0F61, | |
1137 | PREFIX_VEX_0F62, | |
1138 | PREFIX_VEX_0F63, | |
1139 | PREFIX_VEX_0F64, | |
1140 | PREFIX_VEX_0F65, | |
1141 | PREFIX_VEX_0F66, | |
1142 | PREFIX_VEX_0F67, | |
1143 | PREFIX_VEX_0F68, | |
1144 | PREFIX_VEX_0F69, | |
1145 | PREFIX_VEX_0F6A, | |
1146 | PREFIX_VEX_0F6B, | |
1147 | PREFIX_VEX_0F6C, | |
1148 | PREFIX_VEX_0F6D, | |
1149 | PREFIX_VEX_0F6E, | |
1150 | PREFIX_VEX_0F6F, | |
1151 | PREFIX_VEX_0F70, | |
1152 | PREFIX_VEX_0F71_REG_2, | |
1153 | PREFIX_VEX_0F71_REG_4, | |
1154 | PREFIX_VEX_0F71_REG_6, | |
1155 | PREFIX_VEX_0F72_REG_2, | |
1156 | PREFIX_VEX_0F72_REG_4, | |
1157 | PREFIX_VEX_0F72_REG_6, | |
1158 | PREFIX_VEX_0F73_REG_2, | |
1159 | PREFIX_VEX_0F73_REG_3, | |
1160 | PREFIX_VEX_0F73_REG_6, | |
1161 | PREFIX_VEX_0F73_REG_7, | |
1162 | PREFIX_VEX_0F74, | |
1163 | PREFIX_VEX_0F75, | |
1164 | PREFIX_VEX_0F76, | |
1165 | PREFIX_VEX_0F77, | |
1166 | PREFIX_VEX_0F7C, | |
1167 | PREFIX_VEX_0F7D, | |
1168 | PREFIX_VEX_0F7E, | |
1169 | PREFIX_VEX_0F7F, | |
43234a1e L |
1170 | PREFIX_VEX_0F90, |
1171 | PREFIX_VEX_0F91, | |
1172 | PREFIX_VEX_0F92, | |
1173 | PREFIX_VEX_0F93, | |
1174 | PREFIX_VEX_0F98, | |
1ba585e8 | 1175 | PREFIX_VEX_0F99, |
592a252b L |
1176 | PREFIX_VEX_0FC2, |
1177 | PREFIX_VEX_0FC4, | |
1178 | PREFIX_VEX_0FC5, | |
1179 | PREFIX_VEX_0FD0, | |
1180 | PREFIX_VEX_0FD1, | |
1181 | PREFIX_VEX_0FD2, | |
1182 | PREFIX_VEX_0FD3, | |
1183 | PREFIX_VEX_0FD4, | |
1184 | PREFIX_VEX_0FD5, | |
1185 | PREFIX_VEX_0FD6, | |
1186 | PREFIX_VEX_0FD7, | |
1187 | PREFIX_VEX_0FD8, | |
1188 | PREFIX_VEX_0FD9, | |
1189 | PREFIX_VEX_0FDA, | |
1190 | PREFIX_VEX_0FDB, | |
1191 | PREFIX_VEX_0FDC, | |
1192 | PREFIX_VEX_0FDD, | |
1193 | PREFIX_VEX_0FDE, | |
1194 | PREFIX_VEX_0FDF, | |
1195 | PREFIX_VEX_0FE0, | |
1196 | PREFIX_VEX_0FE1, | |
1197 | PREFIX_VEX_0FE2, | |
1198 | PREFIX_VEX_0FE3, | |
1199 | PREFIX_VEX_0FE4, | |
1200 | PREFIX_VEX_0FE5, | |
1201 | PREFIX_VEX_0FE6, | |
1202 | PREFIX_VEX_0FE7, | |
1203 | PREFIX_VEX_0FE8, | |
1204 | PREFIX_VEX_0FE9, | |
1205 | PREFIX_VEX_0FEA, | |
1206 | PREFIX_VEX_0FEB, | |
1207 | PREFIX_VEX_0FEC, | |
1208 | PREFIX_VEX_0FED, | |
1209 | PREFIX_VEX_0FEE, | |
1210 | PREFIX_VEX_0FEF, | |
1211 | PREFIX_VEX_0FF0, | |
1212 | PREFIX_VEX_0FF1, | |
1213 | PREFIX_VEX_0FF2, | |
1214 | PREFIX_VEX_0FF3, | |
1215 | PREFIX_VEX_0FF4, | |
1216 | PREFIX_VEX_0FF5, | |
1217 | PREFIX_VEX_0FF6, | |
1218 | PREFIX_VEX_0FF7, | |
1219 | PREFIX_VEX_0FF8, | |
1220 | PREFIX_VEX_0FF9, | |
1221 | PREFIX_VEX_0FFA, | |
1222 | PREFIX_VEX_0FFB, | |
1223 | PREFIX_VEX_0FFC, | |
1224 | PREFIX_VEX_0FFD, | |
1225 | PREFIX_VEX_0FFE, | |
1226 | PREFIX_VEX_0F3800, | |
1227 | PREFIX_VEX_0F3801, | |
1228 | PREFIX_VEX_0F3802, | |
1229 | PREFIX_VEX_0F3803, | |
1230 | PREFIX_VEX_0F3804, | |
1231 | PREFIX_VEX_0F3805, | |
1232 | PREFIX_VEX_0F3806, | |
1233 | PREFIX_VEX_0F3807, | |
1234 | PREFIX_VEX_0F3808, | |
1235 | PREFIX_VEX_0F3809, | |
1236 | PREFIX_VEX_0F380A, | |
1237 | PREFIX_VEX_0F380B, | |
1238 | PREFIX_VEX_0F380C, | |
1239 | PREFIX_VEX_0F380D, | |
1240 | PREFIX_VEX_0F380E, | |
1241 | PREFIX_VEX_0F380F, | |
1242 | PREFIX_VEX_0F3813, | |
6c30d220 | 1243 | PREFIX_VEX_0F3816, |
592a252b L |
1244 | PREFIX_VEX_0F3817, |
1245 | PREFIX_VEX_0F3818, | |
1246 | PREFIX_VEX_0F3819, | |
1247 | PREFIX_VEX_0F381A, | |
1248 | PREFIX_VEX_0F381C, | |
1249 | PREFIX_VEX_0F381D, | |
1250 | PREFIX_VEX_0F381E, | |
1251 | PREFIX_VEX_0F3820, | |
1252 | PREFIX_VEX_0F3821, | |
1253 | PREFIX_VEX_0F3822, | |
1254 | PREFIX_VEX_0F3823, | |
1255 | PREFIX_VEX_0F3824, | |
1256 | PREFIX_VEX_0F3825, | |
1257 | PREFIX_VEX_0F3828, | |
1258 | PREFIX_VEX_0F3829, | |
1259 | PREFIX_VEX_0F382A, | |
1260 | PREFIX_VEX_0F382B, | |
1261 | PREFIX_VEX_0F382C, | |
1262 | PREFIX_VEX_0F382D, | |
1263 | PREFIX_VEX_0F382E, | |
1264 | PREFIX_VEX_0F382F, | |
1265 | PREFIX_VEX_0F3830, | |
1266 | PREFIX_VEX_0F3831, | |
1267 | PREFIX_VEX_0F3832, | |
1268 | PREFIX_VEX_0F3833, | |
1269 | PREFIX_VEX_0F3834, | |
1270 | PREFIX_VEX_0F3835, | |
6c30d220 | 1271 | PREFIX_VEX_0F3836, |
592a252b L |
1272 | PREFIX_VEX_0F3837, |
1273 | PREFIX_VEX_0F3838, | |
1274 | PREFIX_VEX_0F3839, | |
1275 | PREFIX_VEX_0F383A, | |
1276 | PREFIX_VEX_0F383B, | |
1277 | PREFIX_VEX_0F383C, | |
1278 | PREFIX_VEX_0F383D, | |
1279 | PREFIX_VEX_0F383E, | |
1280 | PREFIX_VEX_0F383F, | |
1281 | PREFIX_VEX_0F3840, | |
1282 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1283 | PREFIX_VEX_0F3845, |
1284 | PREFIX_VEX_0F3846, | |
1285 | PREFIX_VEX_0F3847, | |
1286 | PREFIX_VEX_0F3858, | |
1287 | PREFIX_VEX_0F3859, | |
1288 | PREFIX_VEX_0F385A, | |
1289 | PREFIX_VEX_0F3878, | |
1290 | PREFIX_VEX_0F3879, | |
1291 | PREFIX_VEX_0F388C, | |
1292 | PREFIX_VEX_0F388E, | |
1293 | PREFIX_VEX_0F3890, | |
1294 | PREFIX_VEX_0F3891, | |
1295 | PREFIX_VEX_0F3892, | |
1296 | PREFIX_VEX_0F3893, | |
592a252b L |
1297 | PREFIX_VEX_0F3896, |
1298 | PREFIX_VEX_0F3897, | |
1299 | PREFIX_VEX_0F3898, | |
1300 | PREFIX_VEX_0F3899, | |
1301 | PREFIX_VEX_0F389A, | |
1302 | PREFIX_VEX_0F389B, | |
1303 | PREFIX_VEX_0F389C, | |
1304 | PREFIX_VEX_0F389D, | |
1305 | PREFIX_VEX_0F389E, | |
1306 | PREFIX_VEX_0F389F, | |
1307 | PREFIX_VEX_0F38A6, | |
1308 | PREFIX_VEX_0F38A7, | |
1309 | PREFIX_VEX_0F38A8, | |
1310 | PREFIX_VEX_0F38A9, | |
1311 | PREFIX_VEX_0F38AA, | |
1312 | PREFIX_VEX_0F38AB, | |
1313 | PREFIX_VEX_0F38AC, | |
1314 | PREFIX_VEX_0F38AD, | |
1315 | PREFIX_VEX_0F38AE, | |
1316 | PREFIX_VEX_0F38AF, | |
1317 | PREFIX_VEX_0F38B6, | |
1318 | PREFIX_VEX_0F38B7, | |
1319 | PREFIX_VEX_0F38B8, | |
1320 | PREFIX_VEX_0F38B9, | |
1321 | PREFIX_VEX_0F38BA, | |
1322 | PREFIX_VEX_0F38BB, | |
1323 | PREFIX_VEX_0F38BC, | |
1324 | PREFIX_VEX_0F38BD, | |
1325 | PREFIX_VEX_0F38BE, | |
1326 | PREFIX_VEX_0F38BF, | |
48521003 | 1327 | PREFIX_VEX_0F38CF, |
592a252b L |
1328 | PREFIX_VEX_0F38DB, |
1329 | PREFIX_VEX_0F38DC, | |
1330 | PREFIX_VEX_0F38DD, | |
1331 | PREFIX_VEX_0F38DE, | |
1332 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1333 | PREFIX_VEX_0F38F2, |
1334 | PREFIX_VEX_0F38F3_REG_1, | |
1335 | PREFIX_VEX_0F38F3_REG_2, | |
1336 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1337 | PREFIX_VEX_0F38F5, |
1338 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1339 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1340 | PREFIX_VEX_0F3A00, |
1341 | PREFIX_VEX_0F3A01, | |
1342 | PREFIX_VEX_0F3A02, | |
592a252b L |
1343 | PREFIX_VEX_0F3A04, |
1344 | PREFIX_VEX_0F3A05, | |
1345 | PREFIX_VEX_0F3A06, | |
1346 | PREFIX_VEX_0F3A08, | |
1347 | PREFIX_VEX_0F3A09, | |
1348 | PREFIX_VEX_0F3A0A, | |
1349 | PREFIX_VEX_0F3A0B, | |
1350 | PREFIX_VEX_0F3A0C, | |
1351 | PREFIX_VEX_0F3A0D, | |
1352 | PREFIX_VEX_0F3A0E, | |
1353 | PREFIX_VEX_0F3A0F, | |
1354 | PREFIX_VEX_0F3A14, | |
1355 | PREFIX_VEX_0F3A15, | |
1356 | PREFIX_VEX_0F3A16, | |
1357 | PREFIX_VEX_0F3A17, | |
1358 | PREFIX_VEX_0F3A18, | |
1359 | PREFIX_VEX_0F3A19, | |
1360 | PREFIX_VEX_0F3A1D, | |
1361 | PREFIX_VEX_0F3A20, | |
1362 | PREFIX_VEX_0F3A21, | |
1363 | PREFIX_VEX_0F3A22, | |
43234a1e | 1364 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1365 | PREFIX_VEX_0F3A31, |
43234a1e | 1366 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1367 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1368 | PREFIX_VEX_0F3A38, |
1369 | PREFIX_VEX_0F3A39, | |
592a252b L |
1370 | PREFIX_VEX_0F3A40, |
1371 | PREFIX_VEX_0F3A41, | |
1372 | PREFIX_VEX_0F3A42, | |
1373 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1374 | PREFIX_VEX_0F3A46, |
592a252b L |
1375 | PREFIX_VEX_0F3A48, |
1376 | PREFIX_VEX_0F3A49, | |
1377 | PREFIX_VEX_0F3A4A, | |
1378 | PREFIX_VEX_0F3A4B, | |
1379 | PREFIX_VEX_0F3A4C, | |
1380 | PREFIX_VEX_0F3A5C, | |
1381 | PREFIX_VEX_0F3A5D, | |
1382 | PREFIX_VEX_0F3A5E, | |
1383 | PREFIX_VEX_0F3A5F, | |
1384 | PREFIX_VEX_0F3A60, | |
1385 | PREFIX_VEX_0F3A61, | |
1386 | PREFIX_VEX_0F3A62, | |
1387 | PREFIX_VEX_0F3A63, | |
1388 | PREFIX_VEX_0F3A68, | |
1389 | PREFIX_VEX_0F3A69, | |
1390 | PREFIX_VEX_0F3A6A, | |
1391 | PREFIX_VEX_0F3A6B, | |
1392 | PREFIX_VEX_0F3A6C, | |
1393 | PREFIX_VEX_0F3A6D, | |
1394 | PREFIX_VEX_0F3A6E, | |
1395 | PREFIX_VEX_0F3A6F, | |
1396 | PREFIX_VEX_0F3A78, | |
1397 | PREFIX_VEX_0F3A79, | |
1398 | PREFIX_VEX_0F3A7A, | |
1399 | PREFIX_VEX_0F3A7B, | |
1400 | PREFIX_VEX_0F3A7C, | |
1401 | PREFIX_VEX_0F3A7D, | |
1402 | PREFIX_VEX_0F3A7E, | |
1403 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1404 | PREFIX_VEX_0F3ACE, |
1405 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1406 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1407 | PREFIX_VEX_0F3AF0, |
1408 | ||
1409 | PREFIX_EVEX_0F10, | |
1410 | PREFIX_EVEX_0F11, | |
1411 | PREFIX_EVEX_0F12, | |
1412 | PREFIX_EVEX_0F13, | |
1413 | PREFIX_EVEX_0F14, | |
1414 | PREFIX_EVEX_0F15, | |
1415 | PREFIX_EVEX_0F16, | |
1416 | PREFIX_EVEX_0F17, | |
1417 | PREFIX_EVEX_0F28, | |
1418 | PREFIX_EVEX_0F29, | |
1419 | PREFIX_EVEX_0F2A, | |
1420 | PREFIX_EVEX_0F2B, | |
1421 | PREFIX_EVEX_0F2C, | |
1422 | PREFIX_EVEX_0F2D, | |
1423 | PREFIX_EVEX_0F2E, | |
1424 | PREFIX_EVEX_0F2F, | |
1425 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1426 | PREFIX_EVEX_0F54, |
1427 | PREFIX_EVEX_0F55, | |
1428 | PREFIX_EVEX_0F56, | |
1429 | PREFIX_EVEX_0F57, | |
43234a1e L |
1430 | PREFIX_EVEX_0F58, |
1431 | PREFIX_EVEX_0F59, | |
1432 | PREFIX_EVEX_0F5A, | |
1433 | PREFIX_EVEX_0F5B, | |
1434 | PREFIX_EVEX_0F5C, | |
1435 | PREFIX_EVEX_0F5D, | |
1436 | PREFIX_EVEX_0F5E, | |
1437 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1438 | PREFIX_EVEX_0F60, |
1439 | PREFIX_EVEX_0F61, | |
43234a1e | 1440 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1441 | PREFIX_EVEX_0F63, |
1442 | PREFIX_EVEX_0F64, | |
1443 | PREFIX_EVEX_0F65, | |
43234a1e | 1444 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1445 | PREFIX_EVEX_0F67, |
1446 | PREFIX_EVEX_0F68, | |
1447 | PREFIX_EVEX_0F69, | |
43234a1e | 1448 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1449 | PREFIX_EVEX_0F6B, |
43234a1e L |
1450 | PREFIX_EVEX_0F6C, |
1451 | PREFIX_EVEX_0F6D, | |
1452 | PREFIX_EVEX_0F6E, | |
1453 | PREFIX_EVEX_0F6F, | |
1454 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1455 | PREFIX_EVEX_0F71_REG_2, |
1456 | PREFIX_EVEX_0F71_REG_4, | |
1457 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1458 | PREFIX_EVEX_0F72_REG_0, |
1459 | PREFIX_EVEX_0F72_REG_1, | |
1460 | PREFIX_EVEX_0F72_REG_2, | |
1461 | PREFIX_EVEX_0F72_REG_4, | |
1462 | PREFIX_EVEX_0F72_REG_6, | |
1463 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1464 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1465 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1466 | PREFIX_EVEX_0F73_REG_7, |
1467 | PREFIX_EVEX_0F74, | |
1468 | PREFIX_EVEX_0F75, | |
43234a1e L |
1469 | PREFIX_EVEX_0F76, |
1470 | PREFIX_EVEX_0F78, | |
1471 | PREFIX_EVEX_0F79, | |
1472 | PREFIX_EVEX_0F7A, | |
1473 | PREFIX_EVEX_0F7B, | |
1474 | PREFIX_EVEX_0F7E, | |
1475 | PREFIX_EVEX_0F7F, | |
1476 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1477 | PREFIX_EVEX_0FC4, |
1478 | PREFIX_EVEX_0FC5, | |
43234a1e | 1479 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1480 | PREFIX_EVEX_0FD1, |
43234a1e L |
1481 | PREFIX_EVEX_0FD2, |
1482 | PREFIX_EVEX_0FD3, | |
1483 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1484 | PREFIX_EVEX_0FD5, |
43234a1e | 1485 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1486 | PREFIX_EVEX_0FD8, |
1487 | PREFIX_EVEX_0FD9, | |
1488 | PREFIX_EVEX_0FDA, | |
43234a1e | 1489 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1490 | PREFIX_EVEX_0FDC, |
1491 | PREFIX_EVEX_0FDD, | |
1492 | PREFIX_EVEX_0FDE, | |
43234a1e | 1493 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1494 | PREFIX_EVEX_0FE0, |
1495 | PREFIX_EVEX_0FE1, | |
43234a1e | 1496 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1497 | PREFIX_EVEX_0FE3, |
1498 | PREFIX_EVEX_0FE4, | |
1499 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1500 | PREFIX_EVEX_0FE6, |
1501 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1502 | PREFIX_EVEX_0FE8, |
1503 | PREFIX_EVEX_0FE9, | |
1504 | PREFIX_EVEX_0FEA, | |
43234a1e | 1505 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1506 | PREFIX_EVEX_0FEC, |
1507 | PREFIX_EVEX_0FED, | |
1508 | PREFIX_EVEX_0FEE, | |
43234a1e | 1509 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1510 | PREFIX_EVEX_0FF1, |
43234a1e L |
1511 | PREFIX_EVEX_0FF2, |
1512 | PREFIX_EVEX_0FF3, | |
1513 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1514 | PREFIX_EVEX_0FF5, |
1515 | PREFIX_EVEX_0FF6, | |
1516 | PREFIX_EVEX_0FF8, | |
1517 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1518 | PREFIX_EVEX_0FFA, |
1519 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1520 | PREFIX_EVEX_0FFC, |
1521 | PREFIX_EVEX_0FFD, | |
43234a1e | 1522 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1523 | PREFIX_EVEX_0F3800, |
1524 | PREFIX_EVEX_0F3804, | |
1525 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1526 | PREFIX_EVEX_0F380C, |
1527 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1528 | PREFIX_EVEX_0F3810, |
43234a1e L |
1529 | PREFIX_EVEX_0F3811, |
1530 | PREFIX_EVEX_0F3812, | |
1531 | PREFIX_EVEX_0F3813, | |
1532 | PREFIX_EVEX_0F3814, | |
1533 | PREFIX_EVEX_0F3815, | |
1534 | PREFIX_EVEX_0F3816, | |
1535 | PREFIX_EVEX_0F3818, | |
1536 | PREFIX_EVEX_0F3819, | |
1537 | PREFIX_EVEX_0F381A, | |
1538 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1539 | PREFIX_EVEX_0F381C, |
1540 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1541 | PREFIX_EVEX_0F381E, |
1542 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1543 | PREFIX_EVEX_0F3820, |
43234a1e L |
1544 | PREFIX_EVEX_0F3821, |
1545 | PREFIX_EVEX_0F3822, | |
1546 | PREFIX_EVEX_0F3823, | |
1547 | PREFIX_EVEX_0F3824, | |
1548 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1549 | PREFIX_EVEX_0F3826, |
43234a1e L |
1550 | PREFIX_EVEX_0F3827, |
1551 | PREFIX_EVEX_0F3828, | |
1552 | PREFIX_EVEX_0F3829, | |
1553 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1554 | PREFIX_EVEX_0F382B, |
43234a1e L |
1555 | PREFIX_EVEX_0F382C, |
1556 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1557 | PREFIX_EVEX_0F3830, |
43234a1e L |
1558 | PREFIX_EVEX_0F3831, |
1559 | PREFIX_EVEX_0F3832, | |
1560 | PREFIX_EVEX_0F3833, | |
1561 | PREFIX_EVEX_0F3834, | |
1562 | PREFIX_EVEX_0F3835, | |
1563 | PREFIX_EVEX_0F3836, | |
1564 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1565 | PREFIX_EVEX_0F3838, |
43234a1e L |
1566 | PREFIX_EVEX_0F3839, |
1567 | PREFIX_EVEX_0F383A, | |
1568 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1569 | PREFIX_EVEX_0F383C, |
43234a1e | 1570 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1571 | PREFIX_EVEX_0F383E, |
43234a1e L |
1572 | PREFIX_EVEX_0F383F, |
1573 | PREFIX_EVEX_0F3840, | |
1574 | PREFIX_EVEX_0F3842, | |
1575 | PREFIX_EVEX_0F3843, | |
1576 | PREFIX_EVEX_0F3844, | |
1577 | PREFIX_EVEX_0F3845, | |
1578 | PREFIX_EVEX_0F3846, | |
1579 | PREFIX_EVEX_0F3847, | |
1580 | PREFIX_EVEX_0F384C, | |
1581 | PREFIX_EVEX_0F384D, | |
1582 | PREFIX_EVEX_0F384E, | |
1583 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1584 | PREFIX_EVEX_0F3850, |
1585 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1586 | PREFIX_EVEX_0F3852, |
1587 | PREFIX_EVEX_0F3853, | |
ee6872be | 1588 | PREFIX_EVEX_0F3854, |
620214f7 | 1589 | PREFIX_EVEX_0F3855, |
43234a1e L |
1590 | PREFIX_EVEX_0F3858, |
1591 | PREFIX_EVEX_0F3859, | |
1592 | PREFIX_EVEX_0F385A, | |
1593 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1594 | PREFIX_EVEX_0F3862, |
1595 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1596 | PREFIX_EVEX_0F3864, |
1597 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1598 | PREFIX_EVEX_0F3866, |
53467f57 IT |
1599 | PREFIX_EVEX_0F3870, |
1600 | PREFIX_EVEX_0F3871, | |
1601 | PREFIX_EVEX_0F3872, | |
1602 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1603 | PREFIX_EVEX_0F3875, |
43234a1e L |
1604 | PREFIX_EVEX_0F3876, |
1605 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1606 | PREFIX_EVEX_0F3878, |
1607 | PREFIX_EVEX_0F3879, | |
1608 | PREFIX_EVEX_0F387A, | |
1609 | PREFIX_EVEX_0F387B, | |
43234a1e | 1610 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1611 | PREFIX_EVEX_0F387D, |
43234a1e L |
1612 | PREFIX_EVEX_0F387E, |
1613 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1614 | PREFIX_EVEX_0F3883, |
43234a1e L |
1615 | PREFIX_EVEX_0F3888, |
1616 | PREFIX_EVEX_0F3889, | |
1617 | PREFIX_EVEX_0F388A, | |
1618 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1619 | PREFIX_EVEX_0F388D, |
ee6872be | 1620 | PREFIX_EVEX_0F388F, |
43234a1e L |
1621 | PREFIX_EVEX_0F3890, |
1622 | PREFIX_EVEX_0F3891, | |
1623 | PREFIX_EVEX_0F3892, | |
1624 | PREFIX_EVEX_0F3893, | |
1625 | PREFIX_EVEX_0F3896, | |
1626 | PREFIX_EVEX_0F3897, | |
1627 | PREFIX_EVEX_0F3898, | |
1628 | PREFIX_EVEX_0F3899, | |
1629 | PREFIX_EVEX_0F389A, | |
1630 | PREFIX_EVEX_0F389B, | |
1631 | PREFIX_EVEX_0F389C, | |
1632 | PREFIX_EVEX_0F389D, | |
1633 | PREFIX_EVEX_0F389E, | |
1634 | PREFIX_EVEX_0F389F, | |
1635 | PREFIX_EVEX_0F38A0, | |
1636 | PREFIX_EVEX_0F38A1, | |
1637 | PREFIX_EVEX_0F38A2, | |
1638 | PREFIX_EVEX_0F38A3, | |
1639 | PREFIX_EVEX_0F38A6, | |
1640 | PREFIX_EVEX_0F38A7, | |
1641 | PREFIX_EVEX_0F38A8, | |
1642 | PREFIX_EVEX_0F38A9, | |
1643 | PREFIX_EVEX_0F38AA, | |
1644 | PREFIX_EVEX_0F38AB, | |
1645 | PREFIX_EVEX_0F38AC, | |
1646 | PREFIX_EVEX_0F38AD, | |
1647 | PREFIX_EVEX_0F38AE, | |
1648 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1649 | PREFIX_EVEX_0F38B4, |
1650 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1651 | PREFIX_EVEX_0F38B6, |
1652 | PREFIX_EVEX_0F38B7, | |
1653 | PREFIX_EVEX_0F38B8, | |
1654 | PREFIX_EVEX_0F38B9, | |
1655 | PREFIX_EVEX_0F38BA, | |
1656 | PREFIX_EVEX_0F38BB, | |
1657 | PREFIX_EVEX_0F38BC, | |
1658 | PREFIX_EVEX_0F38BD, | |
1659 | PREFIX_EVEX_0F38BE, | |
1660 | PREFIX_EVEX_0F38BF, | |
1661 | PREFIX_EVEX_0F38C4, | |
1662 | PREFIX_EVEX_0F38C6_REG_1, | |
1663 | PREFIX_EVEX_0F38C6_REG_2, | |
1664 | PREFIX_EVEX_0F38C6_REG_5, | |
1665 | PREFIX_EVEX_0F38C6_REG_6, | |
1666 | PREFIX_EVEX_0F38C7_REG_1, | |
1667 | PREFIX_EVEX_0F38C7_REG_2, | |
1668 | PREFIX_EVEX_0F38C7_REG_5, | |
1669 | PREFIX_EVEX_0F38C7_REG_6, | |
1670 | PREFIX_EVEX_0F38C8, | |
1671 | PREFIX_EVEX_0F38CA, | |
1672 | PREFIX_EVEX_0F38CB, | |
1673 | PREFIX_EVEX_0F38CC, | |
1674 | PREFIX_EVEX_0F38CD, | |
48521003 | 1675 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1676 | PREFIX_EVEX_0F38DC, |
1677 | PREFIX_EVEX_0F38DD, | |
1678 | PREFIX_EVEX_0F38DE, | |
1679 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1680 | |
1681 | PREFIX_EVEX_0F3A00, | |
1682 | PREFIX_EVEX_0F3A01, | |
1683 | PREFIX_EVEX_0F3A03, | |
1684 | PREFIX_EVEX_0F3A04, | |
1685 | PREFIX_EVEX_0F3A05, | |
1686 | PREFIX_EVEX_0F3A08, | |
1687 | PREFIX_EVEX_0F3A09, | |
1688 | PREFIX_EVEX_0F3A0A, | |
1689 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1690 | PREFIX_EVEX_0F3A0F, |
1691 | PREFIX_EVEX_0F3A14, | |
1692 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1693 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1694 | PREFIX_EVEX_0F3A17, |
1695 | PREFIX_EVEX_0F3A18, | |
1696 | PREFIX_EVEX_0F3A19, | |
1697 | PREFIX_EVEX_0F3A1A, | |
1698 | PREFIX_EVEX_0F3A1B, | |
1699 | PREFIX_EVEX_0F3A1D, | |
1700 | PREFIX_EVEX_0F3A1E, | |
1701 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1702 | PREFIX_EVEX_0F3A20, |
43234a1e | 1703 | PREFIX_EVEX_0F3A21, |
90a915bf | 1704 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1705 | PREFIX_EVEX_0F3A23, |
1706 | PREFIX_EVEX_0F3A25, | |
1707 | PREFIX_EVEX_0F3A26, | |
1708 | PREFIX_EVEX_0F3A27, | |
1709 | PREFIX_EVEX_0F3A38, | |
1710 | PREFIX_EVEX_0F3A39, | |
1711 | PREFIX_EVEX_0F3A3A, | |
1712 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1713 | PREFIX_EVEX_0F3A3E, |
1714 | PREFIX_EVEX_0F3A3F, | |
1715 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1716 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1717 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1718 | PREFIX_EVEX_0F3A50, |
1719 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1720 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1721 | PREFIX_EVEX_0F3A55, |
1722 | PREFIX_EVEX_0F3A56, | |
1723 | PREFIX_EVEX_0F3A57, | |
1724 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1725 | PREFIX_EVEX_0F3A67, |
1726 | PREFIX_EVEX_0F3A70, | |
1727 | PREFIX_EVEX_0F3A71, | |
1728 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1729 | PREFIX_EVEX_0F3A73, |
1730 | PREFIX_EVEX_0F3ACE, | |
1731 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1732 | }; |
4e7d34a6 | 1733 | |
51e7da1b L |
1734 | enum |
1735 | { | |
1736 | X86_64_06 = 0, | |
3873ba12 L |
1737 | X86_64_07, |
1738 | X86_64_0D, | |
1739 | X86_64_16, | |
1740 | X86_64_17, | |
1741 | X86_64_1E, | |
1742 | X86_64_1F, | |
1743 | X86_64_27, | |
1744 | X86_64_2F, | |
1745 | X86_64_37, | |
1746 | X86_64_3F, | |
1747 | X86_64_60, | |
1748 | X86_64_61, | |
1749 | X86_64_62, | |
1750 | X86_64_63, | |
1751 | X86_64_6D, | |
1752 | X86_64_6F, | |
d039fef3 | 1753 | X86_64_82, |
3873ba12 L |
1754 | X86_64_9A, |
1755 | X86_64_C4, | |
1756 | X86_64_C5, | |
1757 | X86_64_CE, | |
1758 | X86_64_D4, | |
1759 | X86_64_D5, | |
a72d2af2 L |
1760 | X86_64_E8, |
1761 | X86_64_E9, | |
3873ba12 L |
1762 | X86_64_EA, |
1763 | X86_64_0F01_REG_0, | |
1764 | X86_64_0F01_REG_1, | |
1765 | X86_64_0F01_REG_2, | |
1766 | X86_64_0F01_REG_3 | |
51e7da1b | 1767 | }; |
4e7d34a6 | 1768 | |
51e7da1b L |
1769 | enum |
1770 | { | |
1771 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1772 | THREE_BYTE_0F3A |
51e7da1b | 1773 | }; |
4e7d34a6 | 1774 | |
f88c9eb0 SP |
1775 | enum |
1776 | { | |
5dd85c99 SP |
1777 | XOP_08 = 0, |
1778 | XOP_09, | |
f88c9eb0 SP |
1779 | XOP_0A |
1780 | }; | |
1781 | ||
51e7da1b L |
1782 | enum |
1783 | { | |
1784 | VEX_0F = 0, | |
3873ba12 L |
1785 | VEX_0F38, |
1786 | VEX_0F3A | |
51e7da1b | 1787 | }; |
c0f3af97 | 1788 | |
43234a1e L |
1789 | enum |
1790 | { | |
1791 | EVEX_0F = 0, | |
1792 | EVEX_0F38, | |
1793 | EVEX_0F3A | |
1794 | }; | |
1795 | ||
51e7da1b L |
1796 | enum |
1797 | { | |
592a252b L |
1798 | VEX_LEN_0F10_P_1 = 0, |
1799 | VEX_LEN_0F10_P_3, | |
1800 | VEX_LEN_0F11_P_1, | |
1801 | VEX_LEN_0F11_P_3, | |
1802 | VEX_LEN_0F12_P_0_M_0, | |
1803 | VEX_LEN_0F12_P_0_M_1, | |
1804 | VEX_LEN_0F12_P_2, | |
1805 | VEX_LEN_0F13_M_0, | |
1806 | VEX_LEN_0F16_P_0_M_0, | |
1807 | VEX_LEN_0F16_P_0_M_1, | |
1808 | VEX_LEN_0F16_P_2, | |
1809 | VEX_LEN_0F17_M_0, | |
1810 | VEX_LEN_0F2A_P_1, | |
1811 | VEX_LEN_0F2A_P_3, | |
1812 | VEX_LEN_0F2C_P_1, | |
1813 | VEX_LEN_0F2C_P_3, | |
1814 | VEX_LEN_0F2D_P_1, | |
1815 | VEX_LEN_0F2D_P_3, | |
1816 | VEX_LEN_0F2E_P_0, | |
1817 | VEX_LEN_0F2E_P_2, | |
1818 | VEX_LEN_0F2F_P_0, | |
1819 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1820 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1821 | VEX_LEN_0F41_P_2, |
43234a1e | 1822 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1823 | VEX_LEN_0F42_P_2, |
43234a1e | 1824 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1825 | VEX_LEN_0F44_P_2, |
43234a1e | 1826 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1827 | VEX_LEN_0F45_P_2, |
43234a1e | 1828 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1829 | VEX_LEN_0F46_P_2, |
43234a1e | 1830 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1831 | VEX_LEN_0F47_P_2, |
1832 | VEX_LEN_0F4A_P_0, | |
1833 | VEX_LEN_0F4A_P_2, | |
1834 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1835 | VEX_LEN_0F4B_P_2, |
592a252b L |
1836 | VEX_LEN_0F51_P_1, |
1837 | VEX_LEN_0F51_P_3, | |
1838 | VEX_LEN_0F52_P_1, | |
1839 | VEX_LEN_0F53_P_1, | |
1840 | VEX_LEN_0F58_P_1, | |
1841 | VEX_LEN_0F58_P_3, | |
1842 | VEX_LEN_0F59_P_1, | |
1843 | VEX_LEN_0F59_P_3, | |
1844 | VEX_LEN_0F5A_P_1, | |
1845 | VEX_LEN_0F5A_P_3, | |
1846 | VEX_LEN_0F5C_P_1, | |
1847 | VEX_LEN_0F5C_P_3, | |
1848 | VEX_LEN_0F5D_P_1, | |
1849 | VEX_LEN_0F5D_P_3, | |
1850 | VEX_LEN_0F5E_P_1, | |
1851 | VEX_LEN_0F5E_P_3, | |
1852 | VEX_LEN_0F5F_P_1, | |
1853 | VEX_LEN_0F5F_P_3, | |
592a252b | 1854 | VEX_LEN_0F6E_P_2, |
592a252b L |
1855 | VEX_LEN_0F7E_P_1, |
1856 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1857 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1858 | VEX_LEN_0F90_P_2, |
43234a1e | 1859 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1860 | VEX_LEN_0F91_P_2, |
43234a1e | 1861 | VEX_LEN_0F92_P_0, |
90a915bf | 1862 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1863 | VEX_LEN_0F92_P_3, |
43234a1e | 1864 | VEX_LEN_0F93_P_0, |
90a915bf | 1865 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1866 | VEX_LEN_0F93_P_3, |
43234a1e | 1867 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1868 | VEX_LEN_0F98_P_2, |
1869 | VEX_LEN_0F99_P_0, | |
1870 | VEX_LEN_0F99_P_2, | |
592a252b L |
1871 | VEX_LEN_0FAE_R_2_M_0, |
1872 | VEX_LEN_0FAE_R_3_M_0, | |
1873 | VEX_LEN_0FC2_P_1, | |
1874 | VEX_LEN_0FC2_P_3, | |
1875 | VEX_LEN_0FC4_P_2, | |
1876 | VEX_LEN_0FC5_P_2, | |
592a252b | 1877 | VEX_LEN_0FD6_P_2, |
592a252b | 1878 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1879 | VEX_LEN_0F3816_P_2, |
1880 | VEX_LEN_0F3819_P_2, | |
592a252b | 1881 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1882 | VEX_LEN_0F3836_P_2, |
592a252b | 1883 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1884 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1885 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1886 | VEX_LEN_0F38F2_P_0, |
1887 | VEX_LEN_0F38F3_R_1_P_0, | |
1888 | VEX_LEN_0F38F3_R_2_P_0, | |
1889 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1890 | VEX_LEN_0F38F5_P_0, |
1891 | VEX_LEN_0F38F5_P_1, | |
1892 | VEX_LEN_0F38F5_P_3, | |
1893 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1894 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1895 | VEX_LEN_0F38F7_P_1, |
1896 | VEX_LEN_0F38F7_P_2, | |
1897 | VEX_LEN_0F38F7_P_3, | |
1898 | VEX_LEN_0F3A00_P_2, | |
1899 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1900 | VEX_LEN_0F3A06_P_2, |
1901 | VEX_LEN_0F3A0A_P_2, | |
1902 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1903 | VEX_LEN_0F3A14_P_2, |
1904 | VEX_LEN_0F3A15_P_2, | |
1905 | VEX_LEN_0F3A16_P_2, | |
1906 | VEX_LEN_0F3A17_P_2, | |
1907 | VEX_LEN_0F3A18_P_2, | |
1908 | VEX_LEN_0F3A19_P_2, | |
1909 | VEX_LEN_0F3A20_P_2, | |
1910 | VEX_LEN_0F3A21_P_2, | |
1911 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1912 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1913 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1914 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1915 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1916 | VEX_LEN_0F3A38_P_2, |
1917 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1918 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1919 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1920 | VEX_LEN_0F3A60_P_2, |
1921 | VEX_LEN_0F3A61_P_2, | |
1922 | VEX_LEN_0F3A62_P_2, | |
1923 | VEX_LEN_0F3A63_P_2, | |
1924 | VEX_LEN_0F3A6A_P_2, | |
1925 | VEX_LEN_0F3A6B_P_2, | |
1926 | VEX_LEN_0F3A6E_P_2, | |
1927 | VEX_LEN_0F3A6F_P_2, | |
1928 | VEX_LEN_0F3A7A_P_2, | |
1929 | VEX_LEN_0F3A7B_P_2, | |
1930 | VEX_LEN_0F3A7E_P_2, | |
1931 | VEX_LEN_0F3A7F_P_2, | |
1932 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1933 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1934 | VEX_LEN_0FXOP_08_CC, |
1935 | VEX_LEN_0FXOP_08_CD, | |
1936 | VEX_LEN_0FXOP_08_CE, | |
1937 | VEX_LEN_0FXOP_08_CF, | |
1938 | VEX_LEN_0FXOP_08_EC, | |
1939 | VEX_LEN_0FXOP_08_ED, | |
1940 | VEX_LEN_0FXOP_08_EE, | |
1941 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1942 | VEX_LEN_0FXOP_09_80, |
1943 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1944 | }; |
c0f3af97 | 1945 | |
9e30b8e0 L |
1946 | enum |
1947 | { | |
592a252b L |
1948 | VEX_W_0F10_P_0 = 0, |
1949 | VEX_W_0F10_P_1, | |
1950 | VEX_W_0F10_P_2, | |
1951 | VEX_W_0F10_P_3, | |
1952 | VEX_W_0F11_P_0, | |
1953 | VEX_W_0F11_P_1, | |
1954 | VEX_W_0F11_P_2, | |
1955 | VEX_W_0F11_P_3, | |
1956 | VEX_W_0F12_P_0_M_0, | |
1957 | VEX_W_0F12_P_0_M_1, | |
1958 | VEX_W_0F12_P_1, | |
1959 | VEX_W_0F12_P_2, | |
1960 | VEX_W_0F12_P_3, | |
1961 | VEX_W_0F13_M_0, | |
1962 | VEX_W_0F14, | |
1963 | VEX_W_0F15, | |
1964 | VEX_W_0F16_P_0_M_0, | |
1965 | VEX_W_0F16_P_0_M_1, | |
1966 | VEX_W_0F16_P_1, | |
1967 | VEX_W_0F16_P_2, | |
1968 | VEX_W_0F17_M_0, | |
1969 | VEX_W_0F28, | |
1970 | VEX_W_0F29, | |
1971 | VEX_W_0F2B_M_0, | |
1972 | VEX_W_0F2E_P_0, | |
1973 | VEX_W_0F2E_P_2, | |
1974 | VEX_W_0F2F_P_0, | |
1975 | VEX_W_0F2F_P_2, | |
43234a1e | 1976 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1977 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1978 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1979 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1980 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1981 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1982 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1983 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1984 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1985 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1986 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1987 | VEX_W_0F47_P_2_LEN_1, |
1988 | VEX_W_0F4A_P_0_LEN_1, | |
1989 | VEX_W_0F4A_P_2_LEN_1, | |
1990 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1991 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1992 | VEX_W_0F50_M_0, |
1993 | VEX_W_0F51_P_0, | |
1994 | VEX_W_0F51_P_1, | |
1995 | VEX_W_0F51_P_2, | |
1996 | VEX_W_0F51_P_3, | |
1997 | VEX_W_0F52_P_0, | |
1998 | VEX_W_0F52_P_1, | |
1999 | VEX_W_0F53_P_0, | |
2000 | VEX_W_0F53_P_1, | |
2001 | VEX_W_0F58_P_0, | |
2002 | VEX_W_0F58_P_1, | |
2003 | VEX_W_0F58_P_2, | |
2004 | VEX_W_0F58_P_3, | |
2005 | VEX_W_0F59_P_0, | |
2006 | VEX_W_0F59_P_1, | |
2007 | VEX_W_0F59_P_2, | |
2008 | VEX_W_0F59_P_3, | |
2009 | VEX_W_0F5A_P_0, | |
2010 | VEX_W_0F5A_P_1, | |
2011 | VEX_W_0F5A_P_3, | |
2012 | VEX_W_0F5B_P_0, | |
2013 | VEX_W_0F5B_P_1, | |
2014 | VEX_W_0F5B_P_2, | |
2015 | VEX_W_0F5C_P_0, | |
2016 | VEX_W_0F5C_P_1, | |
2017 | VEX_W_0F5C_P_2, | |
2018 | VEX_W_0F5C_P_3, | |
2019 | VEX_W_0F5D_P_0, | |
2020 | VEX_W_0F5D_P_1, | |
2021 | VEX_W_0F5D_P_2, | |
2022 | VEX_W_0F5D_P_3, | |
2023 | VEX_W_0F5E_P_0, | |
2024 | VEX_W_0F5E_P_1, | |
2025 | VEX_W_0F5E_P_2, | |
2026 | VEX_W_0F5E_P_3, | |
2027 | VEX_W_0F5F_P_0, | |
2028 | VEX_W_0F5F_P_1, | |
2029 | VEX_W_0F5F_P_2, | |
2030 | VEX_W_0F5F_P_3, | |
2031 | VEX_W_0F60_P_2, | |
2032 | VEX_W_0F61_P_2, | |
2033 | VEX_W_0F62_P_2, | |
2034 | VEX_W_0F63_P_2, | |
2035 | VEX_W_0F64_P_2, | |
2036 | VEX_W_0F65_P_2, | |
2037 | VEX_W_0F66_P_2, | |
2038 | VEX_W_0F67_P_2, | |
2039 | VEX_W_0F68_P_2, | |
2040 | VEX_W_0F69_P_2, | |
2041 | VEX_W_0F6A_P_2, | |
2042 | VEX_W_0F6B_P_2, | |
2043 | VEX_W_0F6C_P_2, | |
2044 | VEX_W_0F6D_P_2, | |
2045 | VEX_W_0F6F_P_1, | |
2046 | VEX_W_0F6F_P_2, | |
2047 | VEX_W_0F70_P_1, | |
2048 | VEX_W_0F70_P_2, | |
2049 | VEX_W_0F70_P_3, | |
2050 | VEX_W_0F71_R_2_P_2, | |
2051 | VEX_W_0F71_R_4_P_2, | |
2052 | VEX_W_0F71_R_6_P_2, | |
2053 | VEX_W_0F72_R_2_P_2, | |
2054 | VEX_W_0F72_R_4_P_2, | |
2055 | VEX_W_0F72_R_6_P_2, | |
2056 | VEX_W_0F73_R_2_P_2, | |
2057 | VEX_W_0F73_R_3_P_2, | |
2058 | VEX_W_0F73_R_6_P_2, | |
2059 | VEX_W_0F73_R_7_P_2, | |
2060 | VEX_W_0F74_P_2, | |
2061 | VEX_W_0F75_P_2, | |
2062 | VEX_W_0F76_P_2, | |
2063 | VEX_W_0F77_P_0, | |
2064 | VEX_W_0F7C_P_2, | |
2065 | VEX_W_0F7C_P_3, | |
2066 | VEX_W_0F7D_P_2, | |
2067 | VEX_W_0F7D_P_3, | |
2068 | VEX_W_0F7E_P_1, | |
2069 | VEX_W_0F7F_P_1, | |
2070 | VEX_W_0F7F_P_2, | |
43234a1e | 2071 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2072 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2073 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2074 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2075 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2076 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2077 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2078 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2079 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2080 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2081 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2082 | VEX_W_0F98_P_2_LEN_0, |
2083 | VEX_W_0F99_P_0_LEN_0, | |
2084 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2085 | VEX_W_0FAE_R_2_M_0, |
2086 | VEX_W_0FAE_R_3_M_0, | |
2087 | VEX_W_0FC2_P_0, | |
2088 | VEX_W_0FC2_P_1, | |
2089 | VEX_W_0FC2_P_2, | |
2090 | VEX_W_0FC2_P_3, | |
2091 | VEX_W_0FC4_P_2, | |
2092 | VEX_W_0FC5_P_2, | |
2093 | VEX_W_0FD0_P_2, | |
2094 | VEX_W_0FD0_P_3, | |
2095 | VEX_W_0FD1_P_2, | |
2096 | VEX_W_0FD2_P_2, | |
2097 | VEX_W_0FD3_P_2, | |
2098 | VEX_W_0FD4_P_2, | |
2099 | VEX_W_0FD5_P_2, | |
2100 | VEX_W_0FD6_P_2, | |
2101 | VEX_W_0FD7_P_2_M_1, | |
2102 | VEX_W_0FD8_P_2, | |
2103 | VEX_W_0FD9_P_2, | |
2104 | VEX_W_0FDA_P_2, | |
2105 | VEX_W_0FDB_P_2, | |
2106 | VEX_W_0FDC_P_2, | |
2107 | VEX_W_0FDD_P_2, | |
2108 | VEX_W_0FDE_P_2, | |
2109 | VEX_W_0FDF_P_2, | |
2110 | VEX_W_0FE0_P_2, | |
2111 | VEX_W_0FE1_P_2, | |
2112 | VEX_W_0FE2_P_2, | |
2113 | VEX_W_0FE3_P_2, | |
2114 | VEX_W_0FE4_P_2, | |
2115 | VEX_W_0FE5_P_2, | |
2116 | VEX_W_0FE6_P_1, | |
2117 | VEX_W_0FE6_P_2, | |
2118 | VEX_W_0FE6_P_3, | |
2119 | VEX_W_0FE7_P_2_M_0, | |
2120 | VEX_W_0FE8_P_2, | |
2121 | VEX_W_0FE9_P_2, | |
2122 | VEX_W_0FEA_P_2, | |
2123 | VEX_W_0FEB_P_2, | |
2124 | VEX_W_0FEC_P_2, | |
2125 | VEX_W_0FED_P_2, | |
2126 | VEX_W_0FEE_P_2, | |
2127 | VEX_W_0FEF_P_2, | |
2128 | VEX_W_0FF0_P_3_M_0, | |
2129 | VEX_W_0FF1_P_2, | |
2130 | VEX_W_0FF2_P_2, | |
2131 | VEX_W_0FF3_P_2, | |
2132 | VEX_W_0FF4_P_2, | |
2133 | VEX_W_0FF5_P_2, | |
2134 | VEX_W_0FF6_P_2, | |
2135 | VEX_W_0FF7_P_2, | |
2136 | VEX_W_0FF8_P_2, | |
2137 | VEX_W_0FF9_P_2, | |
2138 | VEX_W_0FFA_P_2, | |
2139 | VEX_W_0FFB_P_2, | |
2140 | VEX_W_0FFC_P_2, | |
2141 | VEX_W_0FFD_P_2, | |
2142 | VEX_W_0FFE_P_2, | |
2143 | VEX_W_0F3800_P_2, | |
2144 | VEX_W_0F3801_P_2, | |
2145 | VEX_W_0F3802_P_2, | |
2146 | VEX_W_0F3803_P_2, | |
2147 | VEX_W_0F3804_P_2, | |
2148 | VEX_W_0F3805_P_2, | |
2149 | VEX_W_0F3806_P_2, | |
2150 | VEX_W_0F3807_P_2, | |
2151 | VEX_W_0F3808_P_2, | |
2152 | VEX_W_0F3809_P_2, | |
2153 | VEX_W_0F380A_P_2, | |
2154 | VEX_W_0F380B_P_2, | |
2155 | VEX_W_0F380C_P_2, | |
2156 | VEX_W_0F380D_P_2, | |
2157 | VEX_W_0F380E_P_2, | |
2158 | VEX_W_0F380F_P_2, | |
6c30d220 | 2159 | VEX_W_0F3816_P_2, |
592a252b | 2160 | VEX_W_0F3817_P_2, |
6c30d220 L |
2161 | VEX_W_0F3818_P_2, |
2162 | VEX_W_0F3819_P_2, | |
592a252b L |
2163 | VEX_W_0F381A_P_2_M_0, |
2164 | VEX_W_0F381C_P_2, | |
2165 | VEX_W_0F381D_P_2, | |
2166 | VEX_W_0F381E_P_2, | |
2167 | VEX_W_0F3820_P_2, | |
2168 | VEX_W_0F3821_P_2, | |
2169 | VEX_W_0F3822_P_2, | |
2170 | VEX_W_0F3823_P_2, | |
2171 | VEX_W_0F3824_P_2, | |
2172 | VEX_W_0F3825_P_2, | |
2173 | VEX_W_0F3828_P_2, | |
2174 | VEX_W_0F3829_P_2, | |
2175 | VEX_W_0F382A_P_2_M_0, | |
2176 | VEX_W_0F382B_P_2, | |
2177 | VEX_W_0F382C_P_2_M_0, | |
2178 | VEX_W_0F382D_P_2_M_0, | |
2179 | VEX_W_0F382E_P_2_M_0, | |
2180 | VEX_W_0F382F_P_2_M_0, | |
2181 | VEX_W_0F3830_P_2, | |
2182 | VEX_W_0F3831_P_2, | |
2183 | VEX_W_0F3832_P_2, | |
2184 | VEX_W_0F3833_P_2, | |
2185 | VEX_W_0F3834_P_2, | |
2186 | VEX_W_0F3835_P_2, | |
6c30d220 | 2187 | VEX_W_0F3836_P_2, |
592a252b L |
2188 | VEX_W_0F3837_P_2, |
2189 | VEX_W_0F3838_P_2, | |
2190 | VEX_W_0F3839_P_2, | |
2191 | VEX_W_0F383A_P_2, | |
2192 | VEX_W_0F383B_P_2, | |
2193 | VEX_W_0F383C_P_2, | |
2194 | VEX_W_0F383D_P_2, | |
2195 | VEX_W_0F383E_P_2, | |
2196 | VEX_W_0F383F_P_2, | |
2197 | VEX_W_0F3840_P_2, | |
2198 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2199 | VEX_W_0F3846_P_2, |
2200 | VEX_W_0F3858_P_2, | |
2201 | VEX_W_0F3859_P_2, | |
2202 | VEX_W_0F385A_P_2_M_0, | |
2203 | VEX_W_0F3878_P_2, | |
2204 | VEX_W_0F3879_P_2, | |
48521003 | 2205 | VEX_W_0F38CF_P_2, |
592a252b | 2206 | VEX_W_0F38DB_P_2, |
6c30d220 L |
2207 | VEX_W_0F3A00_P_2, |
2208 | VEX_W_0F3A01_P_2, | |
2209 | VEX_W_0F3A02_P_2, | |
592a252b L |
2210 | VEX_W_0F3A04_P_2, |
2211 | VEX_W_0F3A05_P_2, | |
2212 | VEX_W_0F3A06_P_2, | |
2213 | VEX_W_0F3A08_P_2, | |
2214 | VEX_W_0F3A09_P_2, | |
2215 | VEX_W_0F3A0A_P_2, | |
2216 | VEX_W_0F3A0B_P_2, | |
2217 | VEX_W_0F3A0C_P_2, | |
2218 | VEX_W_0F3A0D_P_2, | |
2219 | VEX_W_0F3A0E_P_2, | |
2220 | VEX_W_0F3A0F_P_2, | |
2221 | VEX_W_0F3A14_P_2, | |
2222 | VEX_W_0F3A15_P_2, | |
2223 | VEX_W_0F3A18_P_2, | |
2224 | VEX_W_0F3A19_P_2, | |
2225 | VEX_W_0F3A20_P_2, | |
2226 | VEX_W_0F3A21_P_2, | |
43234a1e | 2227 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2228 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2229 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2230 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2231 | VEX_W_0F3A38_P_2, |
2232 | VEX_W_0F3A39_P_2, | |
592a252b L |
2233 | VEX_W_0F3A40_P_2, |
2234 | VEX_W_0F3A41_P_2, | |
2235 | VEX_W_0F3A42_P_2, | |
6c30d220 | 2236 | VEX_W_0F3A46_P_2, |
592a252b L |
2237 | VEX_W_0F3A48_P_2, |
2238 | VEX_W_0F3A49_P_2, | |
2239 | VEX_W_0F3A4A_P_2, | |
2240 | VEX_W_0F3A4B_P_2, | |
2241 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2242 | VEX_W_0F3A62_P_2, |
2243 | VEX_W_0F3A63_P_2, | |
48521003 IT |
2244 | VEX_W_0F3ACE_P_2, |
2245 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2246 | VEX_W_0F3ADF_P_2, |
2247 | ||
2248 | EVEX_W_0F10_P_0, | |
2249 | EVEX_W_0F10_P_1_M_0, | |
2250 | EVEX_W_0F10_P_1_M_1, | |
2251 | EVEX_W_0F10_P_2, | |
2252 | EVEX_W_0F10_P_3_M_0, | |
2253 | EVEX_W_0F10_P_3_M_1, | |
2254 | EVEX_W_0F11_P_0, | |
2255 | EVEX_W_0F11_P_1_M_0, | |
2256 | EVEX_W_0F11_P_1_M_1, | |
2257 | EVEX_W_0F11_P_2, | |
2258 | EVEX_W_0F11_P_3_M_0, | |
2259 | EVEX_W_0F11_P_3_M_1, | |
2260 | EVEX_W_0F12_P_0_M_0, | |
2261 | EVEX_W_0F12_P_0_M_1, | |
2262 | EVEX_W_0F12_P_1, | |
2263 | EVEX_W_0F12_P_2, | |
2264 | EVEX_W_0F12_P_3, | |
2265 | EVEX_W_0F13_P_0, | |
2266 | EVEX_W_0F13_P_2, | |
2267 | EVEX_W_0F14_P_0, | |
2268 | EVEX_W_0F14_P_2, | |
2269 | EVEX_W_0F15_P_0, | |
2270 | EVEX_W_0F15_P_2, | |
2271 | EVEX_W_0F16_P_0_M_0, | |
2272 | EVEX_W_0F16_P_0_M_1, | |
2273 | EVEX_W_0F16_P_1, | |
2274 | EVEX_W_0F16_P_2, | |
2275 | EVEX_W_0F17_P_0, | |
2276 | EVEX_W_0F17_P_2, | |
2277 | EVEX_W_0F28_P_0, | |
2278 | EVEX_W_0F28_P_2, | |
2279 | EVEX_W_0F29_P_0, | |
2280 | EVEX_W_0F29_P_2, | |
2281 | EVEX_W_0F2A_P_1, | |
2282 | EVEX_W_0F2A_P_3, | |
2283 | EVEX_W_0F2B_P_0, | |
2284 | EVEX_W_0F2B_P_2, | |
2285 | EVEX_W_0F2E_P_0, | |
2286 | EVEX_W_0F2E_P_2, | |
2287 | EVEX_W_0F2F_P_0, | |
2288 | EVEX_W_0F2F_P_2, | |
2289 | EVEX_W_0F51_P_0, | |
2290 | EVEX_W_0F51_P_1, | |
2291 | EVEX_W_0F51_P_2, | |
2292 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2293 | EVEX_W_0F54_P_0, |
2294 | EVEX_W_0F54_P_2, | |
2295 | EVEX_W_0F55_P_0, | |
2296 | EVEX_W_0F55_P_2, | |
2297 | EVEX_W_0F56_P_0, | |
2298 | EVEX_W_0F56_P_2, | |
2299 | EVEX_W_0F57_P_0, | |
2300 | EVEX_W_0F57_P_2, | |
43234a1e L |
2301 | EVEX_W_0F58_P_0, |
2302 | EVEX_W_0F58_P_1, | |
2303 | EVEX_W_0F58_P_2, | |
2304 | EVEX_W_0F58_P_3, | |
2305 | EVEX_W_0F59_P_0, | |
2306 | EVEX_W_0F59_P_1, | |
2307 | EVEX_W_0F59_P_2, | |
2308 | EVEX_W_0F59_P_3, | |
2309 | EVEX_W_0F5A_P_0, | |
2310 | EVEX_W_0F5A_P_1, | |
2311 | EVEX_W_0F5A_P_2, | |
2312 | EVEX_W_0F5A_P_3, | |
2313 | EVEX_W_0F5B_P_0, | |
2314 | EVEX_W_0F5B_P_1, | |
2315 | EVEX_W_0F5B_P_2, | |
2316 | EVEX_W_0F5C_P_0, | |
2317 | EVEX_W_0F5C_P_1, | |
2318 | EVEX_W_0F5C_P_2, | |
2319 | EVEX_W_0F5C_P_3, | |
2320 | EVEX_W_0F5D_P_0, | |
2321 | EVEX_W_0F5D_P_1, | |
2322 | EVEX_W_0F5D_P_2, | |
2323 | EVEX_W_0F5D_P_3, | |
2324 | EVEX_W_0F5E_P_0, | |
2325 | EVEX_W_0F5E_P_1, | |
2326 | EVEX_W_0F5E_P_2, | |
2327 | EVEX_W_0F5E_P_3, | |
2328 | EVEX_W_0F5F_P_0, | |
2329 | EVEX_W_0F5F_P_1, | |
2330 | EVEX_W_0F5F_P_2, | |
2331 | EVEX_W_0F5F_P_3, | |
2332 | EVEX_W_0F62_P_2, | |
2333 | EVEX_W_0F66_P_2, | |
2334 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2335 | EVEX_W_0F6B_P_2, |
43234a1e L |
2336 | EVEX_W_0F6C_P_2, |
2337 | EVEX_W_0F6D_P_2, | |
2338 | EVEX_W_0F6E_P_2, | |
2339 | EVEX_W_0F6F_P_1, | |
2340 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2341 | EVEX_W_0F6F_P_3, |
43234a1e L |
2342 | EVEX_W_0F70_P_2, |
2343 | EVEX_W_0F72_R_2_P_2, | |
2344 | EVEX_W_0F72_R_6_P_2, | |
2345 | EVEX_W_0F73_R_2_P_2, | |
2346 | EVEX_W_0F73_R_6_P_2, | |
2347 | EVEX_W_0F76_P_2, | |
2348 | EVEX_W_0F78_P_0, | |
90a915bf | 2349 | EVEX_W_0F78_P_2, |
43234a1e | 2350 | EVEX_W_0F79_P_0, |
90a915bf | 2351 | EVEX_W_0F79_P_2, |
43234a1e | 2352 | EVEX_W_0F7A_P_1, |
90a915bf | 2353 | EVEX_W_0F7A_P_2, |
43234a1e L |
2354 | EVEX_W_0F7A_P_3, |
2355 | EVEX_W_0F7B_P_1, | |
90a915bf | 2356 | EVEX_W_0F7B_P_2, |
43234a1e L |
2357 | EVEX_W_0F7B_P_3, |
2358 | EVEX_W_0F7E_P_1, | |
2359 | EVEX_W_0F7E_P_2, | |
2360 | EVEX_W_0F7F_P_1, | |
2361 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2362 | EVEX_W_0F7F_P_3, |
43234a1e L |
2363 | EVEX_W_0FC2_P_0, |
2364 | EVEX_W_0FC2_P_1, | |
2365 | EVEX_W_0FC2_P_2, | |
2366 | EVEX_W_0FC2_P_3, | |
2367 | EVEX_W_0FC6_P_0, | |
2368 | EVEX_W_0FC6_P_2, | |
2369 | EVEX_W_0FD2_P_2, | |
2370 | EVEX_W_0FD3_P_2, | |
2371 | EVEX_W_0FD4_P_2, | |
2372 | EVEX_W_0FD6_P_2, | |
2373 | EVEX_W_0FE6_P_1, | |
2374 | EVEX_W_0FE6_P_2, | |
2375 | EVEX_W_0FE6_P_3, | |
2376 | EVEX_W_0FE7_P_2, | |
2377 | EVEX_W_0FF2_P_2, | |
2378 | EVEX_W_0FF3_P_2, | |
2379 | EVEX_W_0FF4_P_2, | |
2380 | EVEX_W_0FFA_P_2, | |
2381 | EVEX_W_0FFB_P_2, | |
2382 | EVEX_W_0FFE_P_2, | |
2383 | EVEX_W_0F380C_P_2, | |
2384 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2385 | EVEX_W_0F3810_P_1, |
2386 | EVEX_W_0F3810_P_2, | |
43234a1e | 2387 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2388 | EVEX_W_0F3811_P_2, |
43234a1e | 2389 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2390 | EVEX_W_0F3812_P_2, |
43234a1e L |
2391 | EVEX_W_0F3813_P_1, |
2392 | EVEX_W_0F3813_P_2, | |
2393 | EVEX_W_0F3814_P_1, | |
2394 | EVEX_W_0F3815_P_1, | |
2395 | EVEX_W_0F3818_P_2, | |
2396 | EVEX_W_0F3819_P_2, | |
2397 | EVEX_W_0F381A_P_2, | |
2398 | EVEX_W_0F381B_P_2, | |
2399 | EVEX_W_0F381E_P_2, | |
2400 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2401 | EVEX_W_0F3820_P_1, |
43234a1e L |
2402 | EVEX_W_0F3821_P_1, |
2403 | EVEX_W_0F3822_P_1, | |
2404 | EVEX_W_0F3823_P_1, | |
2405 | EVEX_W_0F3824_P_1, | |
2406 | EVEX_W_0F3825_P_1, | |
2407 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2408 | EVEX_W_0F3826_P_1, |
2409 | EVEX_W_0F3826_P_2, | |
2410 | EVEX_W_0F3828_P_1, | |
43234a1e | 2411 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2412 | EVEX_W_0F3829_P_1, |
43234a1e L |
2413 | EVEX_W_0F3829_P_2, |
2414 | EVEX_W_0F382A_P_1, | |
2415 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2416 | EVEX_W_0F382B_P_2, |
2417 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2418 | EVEX_W_0F3831_P_1, |
2419 | EVEX_W_0F3832_P_1, | |
2420 | EVEX_W_0F3833_P_1, | |
2421 | EVEX_W_0F3834_P_1, | |
2422 | EVEX_W_0F3835_P_1, | |
2423 | EVEX_W_0F3835_P_2, | |
2424 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2425 | EVEX_W_0F3838_P_1, |
2426 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2427 | EVEX_W_0F383A_P_1, |
2428 | EVEX_W_0F3840_P_2, | |
ee6872be | 2429 | EVEX_W_0F3854_P_2, |
620214f7 | 2430 | EVEX_W_0F3855_P_2, |
43234a1e L |
2431 | EVEX_W_0F3858_P_2, |
2432 | EVEX_W_0F3859_P_2, | |
2433 | EVEX_W_0F385A_P_2, | |
2434 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2435 | EVEX_W_0F3862_P_2, |
2436 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2437 | EVEX_W_0F3866_P_2, |
53467f57 IT |
2438 | EVEX_W_0F3870_P_2, |
2439 | EVEX_W_0F3871_P_2, | |
2440 | EVEX_W_0F3872_P_2, | |
2441 | EVEX_W_0F3873_P_2, | |
1ba585e8 IT |
2442 | EVEX_W_0F3875_P_2, |
2443 | EVEX_W_0F3878_P_2, | |
2444 | EVEX_W_0F3879_P_2, | |
2445 | EVEX_W_0F387A_P_2, | |
2446 | EVEX_W_0F387B_P_2, | |
2447 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2448 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2449 | EVEX_W_0F388D_P_2, |
43234a1e L |
2450 | EVEX_W_0F3891_P_2, |
2451 | EVEX_W_0F3893_P_2, | |
2452 | EVEX_W_0F38A1_P_2, | |
2453 | EVEX_W_0F38A3_P_2, | |
2454 | EVEX_W_0F38C7_R_1_P_2, | |
2455 | EVEX_W_0F38C7_R_2_P_2, | |
2456 | EVEX_W_0F38C7_R_5_P_2, | |
2457 | EVEX_W_0F38C7_R_6_P_2, | |
2458 | ||
2459 | EVEX_W_0F3A00_P_2, | |
2460 | EVEX_W_0F3A01_P_2, | |
2461 | EVEX_W_0F3A04_P_2, | |
2462 | EVEX_W_0F3A05_P_2, | |
2463 | EVEX_W_0F3A08_P_2, | |
2464 | EVEX_W_0F3A09_P_2, | |
2465 | EVEX_W_0F3A0A_P_2, | |
2466 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2467 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2468 | EVEX_W_0F3A18_P_2, |
2469 | EVEX_W_0F3A19_P_2, | |
2470 | EVEX_W_0F3A1A_P_2, | |
2471 | EVEX_W_0F3A1B_P_2, | |
2472 | EVEX_W_0F3A1D_P_2, | |
2473 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2474 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2475 | EVEX_W_0F3A23_P_2, |
2476 | EVEX_W_0F3A38_P_2, | |
2477 | EVEX_W_0F3A39_P_2, | |
2478 | EVEX_W_0F3A3A_P_2, | |
2479 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2480 | EVEX_W_0F3A3E_P_2, |
2481 | EVEX_W_0F3A3F_P_2, | |
2482 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2483 | EVEX_W_0F3A43_P_2, |
2484 | EVEX_W_0F3A50_P_2, | |
2485 | EVEX_W_0F3A51_P_2, | |
2486 | EVEX_W_0F3A56_P_2, | |
2487 | EVEX_W_0F3A57_P_2, | |
2488 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2489 | EVEX_W_0F3A67_P_2, |
2490 | EVEX_W_0F3A70_P_2, | |
2491 | EVEX_W_0F3A71_P_2, | |
2492 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2493 | EVEX_W_0F3A73_P_2, |
2494 | EVEX_W_0F3ACE_P_2, | |
2495 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2496 | }; |
2497 | ||
26ca5450 | 2498 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2499 | |
2500 | struct dis386 { | |
2da11e11 | 2501 | const char *name; |
ce518a5f L |
2502 | struct |
2503 | { | |
2504 | op_rtn rtn; | |
2505 | int bytemode; | |
2506 | } op[MAX_OPERANDS]; | |
bf890a93 | 2507 | unsigned int prefix_requirement; |
252b5132 RH |
2508 | }; |
2509 | ||
2510 | /* Upper case letters in the instruction names here are macros. | |
2511 | 'A' => print 'b' if no register operands or suffix_always is true | |
2512 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2513 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2514 | size prefix |
ed7841b3 | 2515 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2516 | suffix_always is true |
252b5132 | 2517 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2518 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2519 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2520 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2521 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2522 | for some of the macro letters) |
9306ca4a | 2523 | 'J' => print 'l' |
42903f7f | 2524 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2525 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2526 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2527 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2528 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2529 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2530 | or suffix_always is true. print 'q' if rex prefix is present. |
2531 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2532 | is true | |
a35ca55a | 2533 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2534 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2535 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2536 | prefix and behave as 'P' otherwise | |
2537 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2538 | prefix and behave as 'Q' otherwise | |
2539 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2540 | prefix and behave as 'S' otherwise | |
a35ca55a | 2541 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2542 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2543 | 'Y' unused. |
6dd5059a | 2544 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2545 | '!' => change condition from true to false or from false to true. |
98b528ac | 2546 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2547 | '^' => print 'w' or 'l' depending on operand size prefix or |
2548 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2549 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2550 | on operand size prefix. | |
07f5af7d L |
2551 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2552 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2553 | otherwise | |
98b528ac L |
2554 | |
2555 | 2 upper case letter macros: | |
04d824a4 JB |
2556 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2557 | operands and no broadcast. | |
2558 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2559 | register operands and no broadcast. | |
4b06377f L |
2560 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2561 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2562 | or suffix_always is true |
4b06377f L |
2563 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2564 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2565 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2566 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2567 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2568 | an operand size prefix, or suffix_always is true. print | |
2569 | 'q' if rex prefix is present. | |
52b15da3 | 2570 | |
6439fc28 AM |
2571 | Many of the above letters print nothing in Intel mode. See "putop" |
2572 | for the details. | |
52b15da3 | 2573 | |
6439fc28 | 2574 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2575 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2576 | |
6439fc28 | 2577 | static const struct dis386 dis386[] = { |
252b5132 | 2578 | /* 00 */ |
bf890a93 IT |
2579 | { "addB", { Ebh1, Gb }, 0 }, |
2580 | { "addS", { Evh1, Gv }, 0 }, | |
2581 | { "addB", { Gb, EbS }, 0 }, | |
2582 | { "addS", { Gv, EvS }, 0 }, | |
2583 | { "addB", { AL, Ib }, 0 }, | |
2584 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2585 | { X86_64_TABLE (X86_64_06) }, |
2586 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2587 | /* 08 */ |
bf890a93 IT |
2588 | { "orB", { Ebh1, Gb }, 0 }, |
2589 | { "orS", { Evh1, Gv }, 0 }, | |
2590 | { "orB", { Gb, EbS }, 0 }, | |
2591 | { "orS", { Gv, EvS }, 0 }, | |
2592 | { "orB", { AL, Ib }, 0 }, | |
2593 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2594 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2595 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2596 | /* 10 */ |
bf890a93 IT |
2597 | { "adcB", { Ebh1, Gb }, 0 }, |
2598 | { "adcS", { Evh1, Gv }, 0 }, | |
2599 | { "adcB", { Gb, EbS }, 0 }, | |
2600 | { "adcS", { Gv, EvS }, 0 }, | |
2601 | { "adcB", { AL, Ib }, 0 }, | |
2602 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2603 | { X86_64_TABLE (X86_64_16) }, |
2604 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2605 | /* 18 */ |
bf890a93 IT |
2606 | { "sbbB", { Ebh1, Gb }, 0 }, |
2607 | { "sbbS", { Evh1, Gv }, 0 }, | |
2608 | { "sbbB", { Gb, EbS }, 0 }, | |
2609 | { "sbbS", { Gv, EvS }, 0 }, | |
2610 | { "sbbB", { AL, Ib }, 0 }, | |
2611 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2612 | { X86_64_TABLE (X86_64_1E) }, |
2613 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2614 | /* 20 */ |
bf890a93 IT |
2615 | { "andB", { Ebh1, Gb }, 0 }, |
2616 | { "andS", { Evh1, Gv }, 0 }, | |
2617 | { "andB", { Gb, EbS }, 0 }, | |
2618 | { "andS", { Gv, EvS }, 0 }, | |
2619 | { "andB", { AL, Ib }, 0 }, | |
2620 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2621 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2622 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2623 | /* 28 */ |
bf890a93 IT |
2624 | { "subB", { Ebh1, Gb }, 0 }, |
2625 | { "subS", { Evh1, Gv }, 0 }, | |
2626 | { "subB", { Gb, EbS }, 0 }, | |
2627 | { "subS", { Gv, EvS }, 0 }, | |
2628 | { "subB", { AL, Ib }, 0 }, | |
2629 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2630 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2631 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2632 | /* 30 */ |
bf890a93 IT |
2633 | { "xorB", { Ebh1, Gb }, 0 }, |
2634 | { "xorS", { Evh1, Gv }, 0 }, | |
2635 | { "xorB", { Gb, EbS }, 0 }, | |
2636 | { "xorS", { Gv, EvS }, 0 }, | |
2637 | { "xorB", { AL, Ib }, 0 }, | |
2638 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2639 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2640 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2641 | /* 38 */ |
bf890a93 IT |
2642 | { "cmpB", { Eb, Gb }, 0 }, |
2643 | { "cmpS", { Ev, Gv }, 0 }, | |
2644 | { "cmpB", { Gb, EbS }, 0 }, | |
2645 | { "cmpS", { Gv, EvS }, 0 }, | |
2646 | { "cmpB", { AL, Ib }, 0 }, | |
2647 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2648 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2649 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2650 | /* 40 */ |
bf890a93 IT |
2651 | { "inc{S|}", { RMeAX }, 0 }, |
2652 | { "inc{S|}", { RMeCX }, 0 }, | |
2653 | { "inc{S|}", { RMeDX }, 0 }, | |
2654 | { "inc{S|}", { RMeBX }, 0 }, | |
2655 | { "inc{S|}", { RMeSP }, 0 }, | |
2656 | { "inc{S|}", { RMeBP }, 0 }, | |
2657 | { "inc{S|}", { RMeSI }, 0 }, | |
2658 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2659 | /* 48 */ |
bf890a93 IT |
2660 | { "dec{S|}", { RMeAX }, 0 }, |
2661 | { "dec{S|}", { RMeCX }, 0 }, | |
2662 | { "dec{S|}", { RMeDX }, 0 }, | |
2663 | { "dec{S|}", { RMeBX }, 0 }, | |
2664 | { "dec{S|}", { RMeSP }, 0 }, | |
2665 | { "dec{S|}", { RMeBP }, 0 }, | |
2666 | { "dec{S|}", { RMeSI }, 0 }, | |
2667 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2668 | /* 50 */ |
bf890a93 IT |
2669 | { "pushV", { RMrAX }, 0 }, |
2670 | { "pushV", { RMrCX }, 0 }, | |
2671 | { "pushV", { RMrDX }, 0 }, | |
2672 | { "pushV", { RMrBX }, 0 }, | |
2673 | { "pushV", { RMrSP }, 0 }, | |
2674 | { "pushV", { RMrBP }, 0 }, | |
2675 | { "pushV", { RMrSI }, 0 }, | |
2676 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2677 | /* 58 */ |
bf890a93 IT |
2678 | { "popV", { RMrAX }, 0 }, |
2679 | { "popV", { RMrCX }, 0 }, | |
2680 | { "popV", { RMrDX }, 0 }, | |
2681 | { "popV", { RMrBX }, 0 }, | |
2682 | { "popV", { RMrSP }, 0 }, | |
2683 | { "popV", { RMrBP }, 0 }, | |
2684 | { "popV", { RMrSI }, 0 }, | |
2685 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2686 | /* 60 */ |
4e7d34a6 L |
2687 | { X86_64_TABLE (X86_64_60) }, |
2688 | { X86_64_TABLE (X86_64_61) }, | |
2689 | { X86_64_TABLE (X86_64_62) }, | |
2690 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2691 | { Bad_Opcode }, /* seg fs */ |
2692 | { Bad_Opcode }, /* seg gs */ | |
2693 | { Bad_Opcode }, /* op size prefix */ | |
2694 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2695 | /* 68 */ |
bf890a93 IT |
2696 | { "pushT", { sIv }, 0 }, |
2697 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2698 | { "pushT", { sIbT }, 0 }, | |
2699 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2700 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2701 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2702 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2703 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2704 | /* 70 */ |
bf890a93 IT |
2705 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2706 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2707 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2708 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2709 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2710 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2711 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2712 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2713 | /* 78 */ |
bf890a93 IT |
2714 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2715 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2716 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2717 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2718 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2719 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2720 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2721 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2722 | /* 80 */ |
1ceb70f8 L |
2723 | { REG_TABLE (REG_80) }, |
2724 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2725 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2726 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2727 | { "testB", { Eb, Gb }, 0 }, |
2728 | { "testS", { Ev, Gv }, 0 }, | |
2729 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2730 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2731 | /* 88 */ |
bf890a93 IT |
2732 | { "movB", { Ebh3, Gb }, 0 }, |
2733 | { "movS", { Evh3, Gv }, 0 }, | |
2734 | { "movB", { Gb, EbS }, 0 }, | |
2735 | { "movS", { Gv, EvS }, 0 }, | |
2736 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2737 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2738 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2739 | { REG_TABLE (REG_8F) }, |
252b5132 | 2740 | /* 90 */ |
1ceb70f8 | 2741 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2742 | { "xchgS", { RMeCX, eAX }, 0 }, |
2743 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2744 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2745 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2746 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2747 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2748 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2749 | /* 98 */ |
bf890a93 IT |
2750 | { "cW{t|}R", { XX }, 0 }, |
2751 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2752 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2753 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2754 | { "pushfT", { XX }, 0 }, |
2755 | { "popfT", { XX }, 0 }, | |
2756 | { "sahf", { XX }, 0 }, | |
2757 | { "lahf", { XX }, 0 }, | |
252b5132 | 2758 | /* a0 */ |
bf890a93 IT |
2759 | { "mov%LB", { AL, Ob }, 0 }, |
2760 | { "mov%LS", { eAX, Ov }, 0 }, | |
2761 | { "mov%LB", { Ob, AL }, 0 }, | |
2762 | { "mov%LS", { Ov, eAX }, 0 }, | |
2763 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2764 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2765 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2766 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2767 | /* a8 */ |
bf890a93 IT |
2768 | { "testB", { AL, Ib }, 0 }, |
2769 | { "testS", { eAX, Iv }, 0 }, | |
2770 | { "stosB", { Ybr, AL }, 0 }, | |
2771 | { "stosS", { Yvr, eAX }, 0 }, | |
2772 | { "lodsB", { ALr, Xb }, 0 }, | |
2773 | { "lodsS", { eAXr, Xv }, 0 }, | |
2774 | { "scasB", { AL, Yb }, 0 }, | |
2775 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2776 | /* b0 */ |
bf890a93 IT |
2777 | { "movB", { RMAL, Ib }, 0 }, |
2778 | { "movB", { RMCL, Ib }, 0 }, | |
2779 | { "movB", { RMDL, Ib }, 0 }, | |
2780 | { "movB", { RMBL, Ib }, 0 }, | |
2781 | { "movB", { RMAH, Ib }, 0 }, | |
2782 | { "movB", { RMCH, Ib }, 0 }, | |
2783 | { "movB", { RMDH, Ib }, 0 }, | |
2784 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2785 | /* b8 */ |
bf890a93 IT |
2786 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2787 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2788 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2789 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2790 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2791 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2792 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2793 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2794 | /* c0 */ |
1ceb70f8 L |
2795 | { REG_TABLE (REG_C0) }, |
2796 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2797 | { "retT", { Iw, BND }, 0 }, |
2798 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2799 | { X86_64_TABLE (X86_64_C4) }, |
2800 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2801 | { REG_TABLE (REG_C6) }, |
2802 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2803 | /* c8 */ |
bf890a93 IT |
2804 | { "enterT", { Iw, Ib }, 0 }, |
2805 | { "leaveT", { XX }, 0 }, | |
2806 | { "Jret{|f}P", { Iw }, 0 }, | |
2807 | { "Jret{|f}P", { XX }, 0 }, | |
2808 | { "int3", { XX }, 0 }, | |
2809 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2810 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2811 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2812 | /* d0 */ |
1ceb70f8 L |
2813 | { REG_TABLE (REG_D0) }, |
2814 | { REG_TABLE (REG_D1) }, | |
2815 | { REG_TABLE (REG_D2) }, | |
2816 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2817 | { X86_64_TABLE (X86_64_D4) }, |
2818 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2819 | { Bad_Opcode }, |
bf890a93 | 2820 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2821 | /* d8 */ |
2822 | { FLOAT }, | |
2823 | { FLOAT }, | |
2824 | { FLOAT }, | |
2825 | { FLOAT }, | |
2826 | { FLOAT }, | |
2827 | { FLOAT }, | |
2828 | { FLOAT }, | |
2829 | { FLOAT }, | |
2830 | /* e0 */ | |
bf890a93 IT |
2831 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2832 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2833 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2834 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2835 | { "inB", { AL, Ib }, 0 }, | |
2836 | { "inG", { zAX, Ib }, 0 }, | |
2837 | { "outB", { Ib, AL }, 0 }, | |
2838 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2839 | /* e8 */ |
a72d2af2 L |
2840 | { X86_64_TABLE (X86_64_E8) }, |
2841 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2842 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2843 | { "jmp", { Jb, BND }, 0 }, |
2844 | { "inB", { AL, indirDX }, 0 }, | |
2845 | { "inG", { zAX, indirDX }, 0 }, | |
2846 | { "outB", { indirDX, AL }, 0 }, | |
2847 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2848 | /* f0 */ |
592d1631 | 2849 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2850 | { "icebp", { XX }, 0 }, |
592d1631 L |
2851 | { Bad_Opcode }, /* repne */ |
2852 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2853 | { "hlt", { XX }, 0 }, |
2854 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2855 | { REG_TABLE (REG_F6) }, |
2856 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2857 | /* f8 */ |
bf890a93 IT |
2858 | { "clc", { XX }, 0 }, |
2859 | { "stc", { XX }, 0 }, | |
2860 | { "cli", { XX }, 0 }, | |
2861 | { "sti", { XX }, 0 }, | |
2862 | { "cld", { XX }, 0 }, | |
2863 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2864 | { REG_TABLE (REG_FE) }, |
2865 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2866 | }; |
2867 | ||
6439fc28 | 2868 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2869 | /* 00 */ |
1ceb70f8 L |
2870 | { REG_TABLE (REG_0F00 ) }, |
2871 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2872 | { "larS", { Gv, Ew }, 0 }, |
2873 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2874 | { Bad_Opcode }, |
bf890a93 IT |
2875 | { "syscall", { XX }, 0 }, |
2876 | { "clts", { XX }, 0 }, | |
2877 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2878 | /* 08 */ |
bf890a93 | 2879 | { "invd", { XX }, 0 }, |
3233d7d0 | 2880 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2881 | { Bad_Opcode }, |
bf890a93 | 2882 | { "ud2", { XX }, 0 }, |
592d1631 | 2883 | { Bad_Opcode }, |
b5b1fc4f | 2884 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2885 | { "femms", { XX }, 0 }, |
2886 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2887 | /* 10 */ |
1ceb70f8 L |
2888 | { PREFIX_TABLE (PREFIX_0F10) }, |
2889 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2890 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2891 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2892 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2893 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2894 | { PREFIX_TABLE (PREFIX_0F16) }, |
2895 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2896 | /* 18 */ |
1ceb70f8 | 2897 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2898 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2899 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2900 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2901 | { "nopQ", { Ev }, 0 }, |
2902 | { "nopQ", { Ev }, 0 }, | |
603555e5 | 2903 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2904 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2905 | /* 20 */ |
bf890a93 IT |
2906 | { "movZ", { Rm, Cm }, 0 }, |
2907 | { "movZ", { Rm, Dm }, 0 }, | |
2908 | { "movZ", { Cm, Rm }, 0 }, | |
2909 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2910 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2911 | { Bad_Opcode }, |
1ceb70f8 | 2912 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2913 | { Bad_Opcode }, |
252b5132 | 2914 | /* 28 */ |
507bd325 L |
2915 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2916 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2917 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2918 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2919 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2920 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2921 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2922 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2923 | /* 30 */ |
bf890a93 IT |
2924 | { "wrmsr", { XX }, 0 }, |
2925 | { "rdtsc", { XX }, 0 }, | |
2926 | { "rdmsr", { XX }, 0 }, | |
2927 | { "rdpmc", { XX }, 0 }, | |
2928 | { "sysenter", { XX }, 0 }, | |
2929 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2930 | { Bad_Opcode }, |
bf890a93 | 2931 | { "getsec", { XX }, 0 }, |
252b5132 | 2932 | /* 38 */ |
507bd325 | 2933 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2934 | { Bad_Opcode }, |
507bd325 | 2935 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2936 | { Bad_Opcode }, |
2937 | { Bad_Opcode }, | |
2938 | { Bad_Opcode }, | |
2939 | { Bad_Opcode }, | |
2940 | { Bad_Opcode }, | |
252b5132 | 2941 | /* 40 */ |
bf890a93 IT |
2942 | { "cmovoS", { Gv, Ev }, 0 }, |
2943 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2944 | { "cmovbS", { Gv, Ev }, 0 }, | |
2945 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2946 | { "cmoveS", { Gv, Ev }, 0 }, | |
2947 | { "cmovneS", { Gv, Ev }, 0 }, | |
2948 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2949 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2950 | /* 48 */ |
bf890a93 IT |
2951 | { "cmovsS", { Gv, Ev }, 0 }, |
2952 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2953 | { "cmovpS", { Gv, Ev }, 0 }, | |
2954 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2955 | { "cmovlS", { Gv, Ev }, 0 }, | |
2956 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2957 | { "cmovleS", { Gv, Ev }, 0 }, | |
2958 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2959 | /* 50 */ |
75c135a8 | 2960 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2961 | { PREFIX_TABLE (PREFIX_0F51) }, |
2962 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2963 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2964 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2965 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2966 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2967 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2968 | /* 58 */ |
1ceb70f8 L |
2969 | { PREFIX_TABLE (PREFIX_0F58) }, |
2970 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2971 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2972 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2973 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2974 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2975 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2976 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2977 | /* 60 */ |
1ceb70f8 L |
2978 | { PREFIX_TABLE (PREFIX_0F60) }, |
2979 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2980 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2981 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2982 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2983 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2984 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2985 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2986 | /* 68 */ |
507bd325 L |
2987 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2988 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2989 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2990 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2991 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2992 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2993 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2994 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2995 | /* 70 */ |
1ceb70f8 L |
2996 | { PREFIX_TABLE (PREFIX_0F70) }, |
2997 | { REG_TABLE (REG_0F71) }, | |
2998 | { REG_TABLE (REG_0F72) }, | |
2999 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
3000 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
3001 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
3002 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
3003 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 3004 | /* 78 */ |
1ceb70f8 L |
3005 | { PREFIX_TABLE (PREFIX_0F78) }, |
3006 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 3007 | { Bad_Opcode }, |
592d1631 | 3008 | { Bad_Opcode }, |
1ceb70f8 L |
3009 | { PREFIX_TABLE (PREFIX_0F7C) }, |
3010 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
3011 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
3012 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 3013 | /* 80 */ |
bf890a93 IT |
3014 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
3015 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
3016 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
3017 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3018 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3019 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
3020 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3021 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3022 | /* 88 */ |
bf890a93 IT |
3023 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
3024 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
3025 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3026 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3027 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
3028 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3029 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
3030 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3031 | /* 90 */ |
bf890a93 IT |
3032 | { "seto", { Eb }, 0 }, |
3033 | { "setno", { Eb }, 0 }, | |
3034 | { "setb", { Eb }, 0 }, | |
3035 | { "setae", { Eb }, 0 }, | |
3036 | { "sete", { Eb }, 0 }, | |
3037 | { "setne", { Eb }, 0 }, | |
3038 | { "setbe", { Eb }, 0 }, | |
3039 | { "seta", { Eb }, 0 }, | |
252b5132 | 3040 | /* 98 */ |
bf890a93 IT |
3041 | { "sets", { Eb }, 0 }, |
3042 | { "setns", { Eb }, 0 }, | |
3043 | { "setp", { Eb }, 0 }, | |
3044 | { "setnp", { Eb }, 0 }, | |
3045 | { "setl", { Eb }, 0 }, | |
3046 | { "setge", { Eb }, 0 }, | |
3047 | { "setle", { Eb }, 0 }, | |
3048 | { "setg", { Eb }, 0 }, | |
252b5132 | 3049 | /* a0 */ |
bf890a93 IT |
3050 | { "pushT", { fs }, 0 }, |
3051 | { "popT", { fs }, 0 }, | |
3052 | { "cpuid", { XX }, 0 }, | |
3053 | { "btS", { Ev, Gv }, 0 }, | |
3054 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
3055 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
3056 | { REG_TABLE (REG_0FA6) }, |
3057 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 3058 | /* a8 */ |
bf890a93 IT |
3059 | { "pushT", { gs }, 0 }, |
3060 | { "popT", { gs }, 0 }, | |
3061 | { "rsm", { XX }, 0 }, | |
3062 | { "btsS", { Evh1, Gv }, 0 }, | |
3063 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3064 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3065 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3066 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3067 | /* b0 */ |
bf890a93 IT |
3068 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3069 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3070 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3071 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3072 | { MOD_TABLE (MOD_0FB4) }, |
3073 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3074 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3075 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3076 | /* b8 */ |
1ceb70f8 | 3077 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 3078 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 3079 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3080 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3081 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3082 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3083 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3084 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3085 | /* c0 */ |
bf890a93 IT |
3086 | { "xaddB", { Ebh1, Gb }, 0 }, |
3087 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3088 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3089 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3090 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3091 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3092 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3093 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3094 | /* c8 */ |
bf890a93 IT |
3095 | { "bswap", { RMeAX }, 0 }, |
3096 | { "bswap", { RMeCX }, 0 }, | |
3097 | { "bswap", { RMeDX }, 0 }, | |
3098 | { "bswap", { RMeBX }, 0 }, | |
3099 | { "bswap", { RMeSP }, 0 }, | |
3100 | { "bswap", { RMeBP }, 0 }, | |
3101 | { "bswap", { RMeSI }, 0 }, | |
3102 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3103 | /* d0 */ |
1ceb70f8 | 3104 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3105 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3106 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3107 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3108 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3109 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3110 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3111 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3112 | /* d8 */ |
507bd325 L |
3113 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3114 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3115 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3116 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3117 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3118 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3119 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3120 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3121 | /* e0 */ |
507bd325 L |
3122 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3123 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3124 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3125 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3126 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3127 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3128 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3129 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3130 | /* e8 */ |
507bd325 L |
3131 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3132 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3133 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3134 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3135 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3136 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3137 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3138 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3139 | /* f0 */ |
1ceb70f8 | 3140 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3141 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3142 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3143 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3144 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3145 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3146 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3147 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3148 | /* f8 */ |
507bd325 L |
3149 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3150 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3151 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3152 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3153 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3154 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3155 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 3156 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
3157 | }; |
3158 | ||
3159 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3160 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3161 | /* ------------------------------- */ | |
3162 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3163 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3164 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3165 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3166 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3167 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3168 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3169 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3170 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3171 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3172 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3173 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3174 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3175 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3176 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3177 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3178 | /* ------------------------------- */ | |
3179 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3180 | }; |
3181 | ||
3182 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3183 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3184 | /* ------------------------------- */ | |
252b5132 | 3185 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3186 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3187 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3188 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3189 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3190 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3191 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3192 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3193 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3194 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3195 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 3196 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 3197 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3198 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3199 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 3200 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
3201 | /* ------------------------------- */ |
3202 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3203 | }; | |
3204 | ||
252b5132 RH |
3205 | static char obuf[100]; |
3206 | static char *obufp; | |
ea397f5b | 3207 | static char *mnemonicendp; |
252b5132 RH |
3208 | static char scratchbuf[100]; |
3209 | static unsigned char *start_codep; | |
3210 | static unsigned char *insn_codep; | |
3211 | static unsigned char *codep; | |
285ca992 | 3212 | static unsigned char *end_codep; |
f16cd0d5 L |
3213 | static int last_lock_prefix; |
3214 | static int last_repz_prefix; | |
3215 | static int last_repnz_prefix; | |
3216 | static int last_data_prefix; | |
3217 | static int last_addr_prefix; | |
3218 | static int last_rex_prefix; | |
3219 | static int last_seg_prefix; | |
d9949a36 | 3220 | static int fwait_prefix; |
285ca992 L |
3221 | /* The active segment register prefix. */ |
3222 | static int active_seg_prefix; | |
f16cd0d5 L |
3223 | #define MAX_CODE_LENGTH 15 |
3224 | /* We can up to 14 prefixes since the maximum instruction length is | |
3225 | 15bytes. */ | |
3226 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3227 | static disassemble_info *the_info; |
7967e09e L |
3228 | static struct |
3229 | { | |
3230 | int mod; | |
7967e09e | 3231 | int reg; |
484c222e | 3232 | int rm; |
7967e09e L |
3233 | } |
3234 | modrm; | |
4bba6815 | 3235 | static unsigned char need_modrm; |
dfc8cf43 L |
3236 | static struct |
3237 | { | |
3238 | int scale; | |
3239 | int index; | |
3240 | int base; | |
3241 | } | |
3242 | sib; | |
c0f3af97 L |
3243 | static struct |
3244 | { | |
3245 | int register_specifier; | |
3246 | int length; | |
3247 | int prefix; | |
3248 | int w; | |
43234a1e L |
3249 | int evex; |
3250 | int r; | |
3251 | int v; | |
3252 | int mask_register_specifier; | |
3253 | int zeroing; | |
3254 | int ll; | |
3255 | int b; | |
c0f3af97 L |
3256 | } |
3257 | vex; | |
3258 | static unsigned char need_vex; | |
3259 | static unsigned char need_vex_reg; | |
dae39acc | 3260 | static unsigned char vex_w_done; |
252b5132 | 3261 | |
ea397f5b L |
3262 | struct op |
3263 | { | |
3264 | const char *name; | |
3265 | unsigned int len; | |
3266 | }; | |
3267 | ||
4bba6815 AM |
3268 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3269 | values are stale. Hitting this abort likely indicates that you | |
3270 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3271 | #define MODRM_CHECK if (!need_modrm) abort () | |
3272 | ||
d708bcba AM |
3273 | static const char **names64; |
3274 | static const char **names32; | |
3275 | static const char **names16; | |
3276 | static const char **names8; | |
3277 | static const char **names8rex; | |
3278 | static const char **names_seg; | |
db51cc60 L |
3279 | static const char *index64; |
3280 | static const char *index32; | |
d708bcba | 3281 | static const char **index16; |
7e8b059b | 3282 | static const char **names_bnd; |
d708bcba AM |
3283 | |
3284 | static const char *intel_names64[] = { | |
3285 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3286 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3287 | }; | |
3288 | static const char *intel_names32[] = { | |
3289 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3290 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3291 | }; | |
3292 | static const char *intel_names16[] = { | |
3293 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3294 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3295 | }; | |
3296 | static const char *intel_names8[] = { | |
3297 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3298 | }; | |
3299 | static const char *intel_names8rex[] = { | |
3300 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3301 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3302 | }; | |
3303 | static const char *intel_names_seg[] = { | |
3304 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3305 | }; | |
db51cc60 L |
3306 | static const char *intel_index64 = "riz"; |
3307 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3308 | static const char *intel_index16[] = { |
3309 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3310 | }; | |
3311 | ||
3312 | static const char *att_names64[] = { | |
3313 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3314 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3315 | }; | |
d708bcba AM |
3316 | static const char *att_names32[] = { |
3317 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3318 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3319 | }; |
d708bcba AM |
3320 | static const char *att_names16[] = { |
3321 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3322 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3323 | }; |
d708bcba AM |
3324 | static const char *att_names8[] = { |
3325 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3326 | }; |
d708bcba AM |
3327 | static const char *att_names8rex[] = { |
3328 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3329 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3330 | }; | |
d708bcba AM |
3331 | static const char *att_names_seg[] = { |
3332 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3333 | }; |
db51cc60 L |
3334 | static const char *att_index64 = "%riz"; |
3335 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3336 | static const char *att_index16[] = { |
3337 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3338 | }; |
3339 | ||
b9733481 L |
3340 | static const char **names_mm; |
3341 | static const char *intel_names_mm[] = { | |
3342 | "mm0", "mm1", "mm2", "mm3", | |
3343 | "mm4", "mm5", "mm6", "mm7" | |
3344 | }; | |
3345 | static const char *att_names_mm[] = { | |
3346 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3347 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3348 | }; | |
3349 | ||
7e8b059b L |
3350 | static const char *intel_names_bnd[] = { |
3351 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3352 | }; | |
3353 | ||
3354 | static const char *att_names_bnd[] = { | |
3355 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3356 | }; | |
3357 | ||
b9733481 L |
3358 | static const char **names_xmm; |
3359 | static const char *intel_names_xmm[] = { | |
3360 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3361 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3362 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3363 | "xmm12", "xmm13", "xmm14", "xmm15", |
3364 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3365 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3366 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3367 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3368 | }; |
3369 | static const char *att_names_xmm[] = { | |
3370 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3371 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3372 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3373 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3374 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3375 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3376 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3377 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3378 | }; |
3379 | ||
3380 | static const char **names_ymm; | |
3381 | static const char *intel_names_ymm[] = { | |
3382 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3383 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3384 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3385 | "ymm12", "ymm13", "ymm14", "ymm15", |
3386 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3387 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3388 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3389 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3390 | }; |
3391 | static const char *att_names_ymm[] = { | |
3392 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3393 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3394 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3395 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3396 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3397 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3398 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3399 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3400 | }; | |
3401 | ||
3402 | static const char **names_zmm; | |
3403 | static const char *intel_names_zmm[] = { | |
3404 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3405 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3406 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3407 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3408 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3409 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3410 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3411 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3412 | }; | |
3413 | static const char *att_names_zmm[] = { | |
3414 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3415 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3416 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3417 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3418 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3419 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3420 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3421 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3422 | }; | |
3423 | ||
3424 | static const char **names_mask; | |
3425 | static const char *intel_names_mask[] = { | |
3426 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3427 | }; | |
3428 | static const char *att_names_mask[] = { | |
3429 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3430 | }; | |
3431 | ||
3432 | static const char *names_rounding[] = | |
3433 | { | |
3434 | "{rn-sae}", | |
3435 | "{rd-sae}", | |
3436 | "{ru-sae}", | |
3437 | "{rz-sae}" | |
b9733481 L |
3438 | }; |
3439 | ||
1ceb70f8 L |
3440 | static const struct dis386 reg_table[][8] = { |
3441 | /* REG_80 */ | |
252b5132 | 3442 | { |
bf890a93 IT |
3443 | { "addA", { Ebh1, Ib }, 0 }, |
3444 | { "orA", { Ebh1, Ib }, 0 }, | |
3445 | { "adcA", { Ebh1, Ib }, 0 }, | |
3446 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3447 | { "andA", { Ebh1, Ib }, 0 }, | |
3448 | { "subA", { Ebh1, Ib }, 0 }, | |
3449 | { "xorA", { Ebh1, Ib }, 0 }, | |
3450 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3451 | }, |
1ceb70f8 | 3452 | /* REG_81 */ |
252b5132 | 3453 | { |
bf890a93 IT |
3454 | { "addQ", { Evh1, Iv }, 0 }, |
3455 | { "orQ", { Evh1, Iv }, 0 }, | |
3456 | { "adcQ", { Evh1, Iv }, 0 }, | |
3457 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3458 | { "andQ", { Evh1, Iv }, 0 }, | |
3459 | { "subQ", { Evh1, Iv }, 0 }, | |
3460 | { "xorQ", { Evh1, Iv }, 0 }, | |
3461 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3462 | }, |
7148c369 | 3463 | /* REG_83 */ |
252b5132 | 3464 | { |
bf890a93 IT |
3465 | { "addQ", { Evh1, sIb }, 0 }, |
3466 | { "orQ", { Evh1, sIb }, 0 }, | |
3467 | { "adcQ", { Evh1, sIb }, 0 }, | |
3468 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3469 | { "andQ", { Evh1, sIb }, 0 }, | |
3470 | { "subQ", { Evh1, sIb }, 0 }, | |
3471 | { "xorQ", { Evh1, sIb }, 0 }, | |
3472 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3473 | }, |
1ceb70f8 | 3474 | /* REG_8F */ |
4e7d34a6 | 3475 | { |
bf890a93 | 3476 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3477 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3478 | { Bad_Opcode }, |
3479 | { Bad_Opcode }, | |
3480 | { Bad_Opcode }, | |
f88c9eb0 | 3481 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3482 | }, |
1ceb70f8 | 3483 | /* REG_C0 */ |
252b5132 | 3484 | { |
bf890a93 IT |
3485 | { "rolA", { Eb, Ib }, 0 }, |
3486 | { "rorA", { Eb, Ib }, 0 }, | |
3487 | { "rclA", { Eb, Ib }, 0 }, | |
3488 | { "rcrA", { Eb, Ib }, 0 }, | |
3489 | { "shlA", { Eb, Ib }, 0 }, | |
3490 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3491 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3492 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3493 | }, |
1ceb70f8 | 3494 | /* REG_C1 */ |
252b5132 | 3495 | { |
bf890a93 IT |
3496 | { "rolQ", { Ev, Ib }, 0 }, |
3497 | { "rorQ", { Ev, Ib }, 0 }, | |
3498 | { "rclQ", { Ev, Ib }, 0 }, | |
3499 | { "rcrQ", { Ev, Ib }, 0 }, | |
3500 | { "shlQ", { Ev, Ib }, 0 }, | |
3501 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3502 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3503 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3504 | }, |
1ceb70f8 | 3505 | /* REG_C6 */ |
4e7d34a6 | 3506 | { |
bf890a93 | 3507 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3508 | { Bad_Opcode }, |
3509 | { Bad_Opcode }, | |
3510 | { Bad_Opcode }, | |
3511 | { Bad_Opcode }, | |
3512 | { Bad_Opcode }, | |
3513 | { Bad_Opcode }, | |
3514 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3515 | }, |
1ceb70f8 | 3516 | /* REG_C7 */ |
4e7d34a6 | 3517 | { |
bf890a93 | 3518 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3519 | { Bad_Opcode }, |
3520 | { Bad_Opcode }, | |
3521 | { Bad_Opcode }, | |
3522 | { Bad_Opcode }, | |
3523 | { Bad_Opcode }, | |
3524 | { Bad_Opcode }, | |
3525 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3526 | }, |
1ceb70f8 | 3527 | /* REG_D0 */ |
252b5132 | 3528 | { |
bf890a93 IT |
3529 | { "rolA", { Eb, I1 }, 0 }, |
3530 | { "rorA", { Eb, I1 }, 0 }, | |
3531 | { "rclA", { Eb, I1 }, 0 }, | |
3532 | { "rcrA", { Eb, I1 }, 0 }, | |
3533 | { "shlA", { Eb, I1 }, 0 }, | |
3534 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3535 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3536 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3537 | }, |
1ceb70f8 | 3538 | /* REG_D1 */ |
252b5132 | 3539 | { |
bf890a93 IT |
3540 | { "rolQ", { Ev, I1 }, 0 }, |
3541 | { "rorQ", { Ev, I1 }, 0 }, | |
3542 | { "rclQ", { Ev, I1 }, 0 }, | |
3543 | { "rcrQ", { Ev, I1 }, 0 }, | |
3544 | { "shlQ", { Ev, I1 }, 0 }, | |
3545 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3546 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3547 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3548 | }, |
1ceb70f8 | 3549 | /* REG_D2 */ |
252b5132 | 3550 | { |
bf890a93 IT |
3551 | { "rolA", { Eb, CL }, 0 }, |
3552 | { "rorA", { Eb, CL }, 0 }, | |
3553 | { "rclA", { Eb, CL }, 0 }, | |
3554 | { "rcrA", { Eb, CL }, 0 }, | |
3555 | { "shlA", { Eb, CL }, 0 }, | |
3556 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3557 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3558 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3559 | }, |
1ceb70f8 | 3560 | /* REG_D3 */ |
252b5132 | 3561 | { |
bf890a93 IT |
3562 | { "rolQ", { Ev, CL }, 0 }, |
3563 | { "rorQ", { Ev, CL }, 0 }, | |
3564 | { "rclQ", { Ev, CL }, 0 }, | |
3565 | { "rcrQ", { Ev, CL }, 0 }, | |
3566 | { "shlQ", { Ev, CL }, 0 }, | |
3567 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3568 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3569 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3570 | }, |
1ceb70f8 | 3571 | /* REG_F6 */ |
252b5132 | 3572 | { |
bf890a93 | 3573 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3574 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3575 | { "notA", { Ebh1 }, 0 }, |
3576 | { "negA", { Ebh1 }, 0 }, | |
3577 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3578 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3579 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3580 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3581 | }, |
1ceb70f8 | 3582 | /* REG_F7 */ |
252b5132 | 3583 | { |
bf890a93 | 3584 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3585 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3586 | { "notQ", { Evh1 }, 0 }, |
3587 | { "negQ", { Evh1 }, 0 }, | |
3588 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3589 | { "imulQ", { Ev }, 0 }, | |
3590 | { "divQ", { Ev }, 0 }, | |
3591 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3592 | }, |
1ceb70f8 | 3593 | /* REG_FE */ |
252b5132 | 3594 | { |
bf890a93 IT |
3595 | { "incA", { Ebh1 }, 0 }, |
3596 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3597 | }, |
1ceb70f8 | 3598 | /* REG_FF */ |
252b5132 | 3599 | { |
bf890a93 IT |
3600 | { "incQ", { Evh1 }, 0 }, |
3601 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3602 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3603 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3604 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3605 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3606 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3607 | { Bad_Opcode }, |
252b5132 | 3608 | }, |
1ceb70f8 | 3609 | /* REG_0F00 */ |
252b5132 | 3610 | { |
bf890a93 IT |
3611 | { "sldtD", { Sv }, 0 }, |
3612 | { "strD", { Sv }, 0 }, | |
3613 | { "lldt", { Ew }, 0 }, | |
3614 | { "ltr", { Ew }, 0 }, | |
3615 | { "verr", { Ew }, 0 }, | |
3616 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3617 | { Bad_Opcode }, |
3618 | { Bad_Opcode }, | |
252b5132 | 3619 | }, |
1ceb70f8 | 3620 | /* REG_0F01 */ |
252b5132 | 3621 | { |
1ceb70f8 L |
3622 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3623 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3624 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3625 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3626 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3627 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3628 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3629 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3630 | }, |
b5b1fc4f | 3631 | /* REG_0F0D */ |
252b5132 | 3632 | { |
bf890a93 IT |
3633 | { "prefetch", { Mb }, 0 }, |
3634 | { "prefetchw", { Mb }, 0 }, | |
3635 | { "prefetchwt1", { Mb }, 0 }, | |
3636 | { "prefetch", { Mb }, 0 }, | |
3637 | { "prefetch", { Mb }, 0 }, | |
3638 | { "prefetch", { Mb }, 0 }, | |
3639 | { "prefetch", { Mb }, 0 }, | |
3640 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3641 | }, |
1ceb70f8 | 3642 | /* REG_0F18 */ |
252b5132 | 3643 | { |
1ceb70f8 L |
3644 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3645 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3646 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3647 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3648 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3649 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3650 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3651 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3652 | }, |
603555e5 L |
3653 | /* REG_0F1E_MOD_3 */ |
3654 | { | |
3655 | { "nopQ", { Ev }, 0 }, | |
3656 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3657 | { "nopQ", { Ev }, 0 }, | |
3658 | { "nopQ", { Ev }, 0 }, | |
3659 | { "nopQ", { Ev }, 0 }, | |
3660 | { "nopQ", { Ev }, 0 }, | |
3661 | { "nopQ", { Ev }, 0 }, | |
3662 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3663 | }, | |
1ceb70f8 | 3664 | /* REG_0F71 */ |
a6bd098c | 3665 | { |
592d1631 L |
3666 | { Bad_Opcode }, |
3667 | { Bad_Opcode }, | |
1ceb70f8 | 3668 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3669 | { Bad_Opcode }, |
1ceb70f8 | 3670 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3671 | { Bad_Opcode }, |
1ceb70f8 | 3672 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3673 | }, |
1ceb70f8 | 3674 | /* REG_0F72 */ |
a6bd098c | 3675 | { |
592d1631 L |
3676 | { Bad_Opcode }, |
3677 | { Bad_Opcode }, | |
1ceb70f8 | 3678 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3679 | { Bad_Opcode }, |
1ceb70f8 | 3680 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3681 | { Bad_Opcode }, |
1ceb70f8 | 3682 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3683 | }, |
1ceb70f8 | 3684 | /* REG_0F73 */ |
252b5132 | 3685 | { |
592d1631 L |
3686 | { Bad_Opcode }, |
3687 | { Bad_Opcode }, | |
1ceb70f8 L |
3688 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3689 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3690 | { Bad_Opcode }, |
3691 | { Bad_Opcode }, | |
1ceb70f8 L |
3692 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3693 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3694 | }, |
1ceb70f8 | 3695 | /* REG_0FA6 */ |
252b5132 | 3696 | { |
bf890a93 IT |
3697 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3698 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3699 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3700 | }, |
1ceb70f8 | 3701 | /* REG_0FA7 */ |
4e7d34a6 | 3702 | { |
bf890a93 IT |
3703 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3704 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3705 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3706 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3707 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3708 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3709 | }, |
1ceb70f8 | 3710 | /* REG_0FAE */ |
4e7d34a6 | 3711 | { |
1ceb70f8 L |
3712 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3713 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3714 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3715 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3716 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3717 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3718 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3719 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3720 | }, |
1ceb70f8 | 3721 | /* REG_0FBA */ |
252b5132 | 3722 | { |
592d1631 L |
3723 | { Bad_Opcode }, |
3724 | { Bad_Opcode }, | |
3725 | { Bad_Opcode }, | |
3726 | { Bad_Opcode }, | |
bf890a93 IT |
3727 | { "btQ", { Ev, Ib }, 0 }, |
3728 | { "btsQ", { Evh1, Ib }, 0 }, | |
3729 | { "btrQ", { Evh1, Ib }, 0 }, | |
3730 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3731 | }, |
1ceb70f8 | 3732 | /* REG_0FC7 */ |
c608c12e | 3733 | { |
592d1631 | 3734 | { Bad_Opcode }, |
bf890a93 | 3735 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3736 | { Bad_Opcode }, |
963f3586 IT |
3737 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3738 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3739 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3740 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3741 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3742 | }, |
592a252b | 3743 | /* REG_VEX_0F71 */ |
c0f3af97 | 3744 | { |
592d1631 L |
3745 | { Bad_Opcode }, |
3746 | { Bad_Opcode }, | |
592a252b | 3747 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3748 | { Bad_Opcode }, |
592a252b | 3749 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3750 | { Bad_Opcode }, |
592a252b | 3751 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3752 | }, |
592a252b | 3753 | /* REG_VEX_0F72 */ |
c0f3af97 | 3754 | { |
592d1631 L |
3755 | { Bad_Opcode }, |
3756 | { Bad_Opcode }, | |
592a252b | 3757 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3758 | { Bad_Opcode }, |
592a252b | 3759 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3760 | { Bad_Opcode }, |
592a252b | 3761 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3762 | }, |
592a252b | 3763 | /* REG_VEX_0F73 */ |
c0f3af97 | 3764 | { |
592d1631 L |
3765 | { Bad_Opcode }, |
3766 | { Bad_Opcode }, | |
592a252b L |
3767 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3768 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3769 | { Bad_Opcode }, |
3770 | { Bad_Opcode }, | |
592a252b L |
3771 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3772 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3773 | }, |
592a252b | 3774 | /* REG_VEX_0FAE */ |
c0f3af97 | 3775 | { |
592d1631 L |
3776 | { Bad_Opcode }, |
3777 | { Bad_Opcode }, | |
592a252b L |
3778 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3779 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3780 | }, |
f12dc422 L |
3781 | /* REG_VEX_0F38F3 */ |
3782 | { | |
3783 | { Bad_Opcode }, | |
3784 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3785 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3786 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3787 | }, | |
f88c9eb0 SP |
3788 | /* REG_XOP_LWPCB */ |
3789 | { | |
bf890a93 IT |
3790 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3791 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3792 | }, |
3793 | /* REG_XOP_LWP */ | |
3794 | { | |
bf890a93 IT |
3795 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3796 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3797 | }, |
2a2a0f38 QN |
3798 | /* REG_XOP_TBM_01 */ |
3799 | { | |
3800 | { Bad_Opcode }, | |
bf890a93 IT |
3801 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3802 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3803 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3804 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3805 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3806 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3807 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3808 | }, |
3809 | /* REG_XOP_TBM_02 */ | |
3810 | { | |
3811 | { Bad_Opcode }, | |
bf890a93 | 3812 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3813 | { Bad_Opcode }, |
3814 | { Bad_Opcode }, | |
3815 | { Bad_Opcode }, | |
3816 | { Bad_Opcode }, | |
bf890a93 | 3817 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3818 | }, |
43234a1e L |
3819 | #define NEED_REG_TABLE |
3820 | #include "i386-dis-evex.h" | |
3821 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3822 | }; |
3823 | ||
1ceb70f8 L |
3824 | static const struct dis386 prefix_table[][4] = { |
3825 | /* PREFIX_90 */ | |
252b5132 | 3826 | { |
bf890a93 IT |
3827 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3828 | { "pause", { XX }, 0 }, | |
3829 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3830 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3831 | }, |
4e7d34a6 | 3832 | |
603555e5 L |
3833 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3834 | { | |
3835 | { Bad_Opcode }, | |
3836 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3837 | }, | |
3838 | ||
2234eee6 | 3839 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3840 | { |
3841 | { Bad_Opcode }, | |
2234eee6 | 3842 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3843 | }, |
3844 | ||
3845 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3846 | { | |
3847 | { Bad_Opcode }, | |
c2f76402 | 3848 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3849 | }, |
3850 | ||
3233d7d0 IT |
3851 | /* PREFIX_0F09 */ |
3852 | { | |
3853 | { "wbinvd", { XX }, 0 }, | |
3854 | { "wbnoinvd", { XX }, 0 }, | |
3855 | }, | |
3856 | ||
1ceb70f8 | 3857 | /* PREFIX_0F10 */ |
cc0ec051 | 3858 | { |
507bd325 L |
3859 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3860 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3861 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3862 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3863 | }, |
4e7d34a6 | 3864 | |
1ceb70f8 | 3865 | /* PREFIX_0F11 */ |
30d1c836 | 3866 | { |
507bd325 L |
3867 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3868 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3869 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3870 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3871 | }, |
252b5132 | 3872 | |
1ceb70f8 | 3873 | /* PREFIX_0F12 */ |
c608c12e | 3874 | { |
1ceb70f8 | 3875 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3876 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3877 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3878 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3879 | }, |
4e7d34a6 | 3880 | |
1ceb70f8 | 3881 | /* PREFIX_0F16 */ |
c608c12e | 3882 | { |
1ceb70f8 | 3883 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3884 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3885 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3886 | }, |
4e7d34a6 | 3887 | |
7e8b059b L |
3888 | /* PREFIX_0F1A */ |
3889 | { | |
3890 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3891 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3892 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3893 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3894 | }, |
3895 | ||
3896 | /* PREFIX_0F1B */ | |
3897 | { | |
3898 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3899 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3900 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3901 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3902 | }, |
3903 | ||
603555e5 L |
3904 | /* PREFIX_0F1E */ |
3905 | { | |
3906 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3907 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3908 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3909 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3910 | }, | |
3911 | ||
1ceb70f8 | 3912 | /* PREFIX_0F2A */ |
c608c12e | 3913 | { |
507bd325 L |
3914 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3915 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3916 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3917 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3918 | }, |
4e7d34a6 | 3919 | |
1ceb70f8 | 3920 | /* PREFIX_0F2B */ |
c608c12e | 3921 | { |
75c135a8 L |
3922 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3923 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3924 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3925 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3926 | }, |
4e7d34a6 | 3927 | |
1ceb70f8 | 3928 | /* PREFIX_0F2C */ |
c608c12e | 3929 | { |
507bd325 | 3930 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3931 | { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3932 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3933 | { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3934 | }, |
4e7d34a6 | 3935 | |
1ceb70f8 | 3936 | /* PREFIX_0F2D */ |
c608c12e | 3937 | { |
507bd325 | 3938 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3939 | { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3940 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3941 | { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3942 | }, |
4e7d34a6 | 3943 | |
1ceb70f8 | 3944 | /* PREFIX_0F2E */ |
c608c12e | 3945 | { |
bf890a93 | 3946 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3947 | { Bad_Opcode }, |
bf890a93 | 3948 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3949 | }, |
4e7d34a6 | 3950 | |
1ceb70f8 | 3951 | /* PREFIX_0F2F */ |
c608c12e | 3952 | { |
bf890a93 | 3953 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3954 | { Bad_Opcode }, |
bf890a93 | 3955 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3956 | }, |
4e7d34a6 | 3957 | |
1ceb70f8 | 3958 | /* PREFIX_0F51 */ |
c608c12e | 3959 | { |
507bd325 L |
3960 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3961 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3962 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3963 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3964 | }, |
4e7d34a6 | 3965 | |
1ceb70f8 | 3966 | /* PREFIX_0F52 */ |
c608c12e | 3967 | { |
507bd325 L |
3968 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3969 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3970 | }, |
4e7d34a6 | 3971 | |
1ceb70f8 | 3972 | /* PREFIX_0F53 */ |
c608c12e | 3973 | { |
507bd325 L |
3974 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3975 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3976 | }, |
4e7d34a6 | 3977 | |
1ceb70f8 | 3978 | /* PREFIX_0F58 */ |
c608c12e | 3979 | { |
507bd325 L |
3980 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3981 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3982 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3983 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3984 | }, |
4e7d34a6 | 3985 | |
1ceb70f8 | 3986 | /* PREFIX_0F59 */ |
c608c12e | 3987 | { |
507bd325 L |
3988 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3989 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3990 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3991 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3992 | }, |
4e7d34a6 | 3993 | |
1ceb70f8 | 3994 | /* PREFIX_0F5A */ |
041bd2e0 | 3995 | { |
507bd325 L |
3996 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3997 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3998 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3999 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4000 | }, |
4e7d34a6 | 4001 | |
1ceb70f8 | 4002 | /* PREFIX_0F5B */ |
041bd2e0 | 4003 | { |
507bd325 L |
4004 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
4005 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4006 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 4007 | }, |
4e7d34a6 | 4008 | |
1ceb70f8 | 4009 | /* PREFIX_0F5C */ |
041bd2e0 | 4010 | { |
507bd325 L |
4011 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
4012 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
4013 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
4014 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4015 | }, |
4e7d34a6 | 4016 | |
1ceb70f8 | 4017 | /* PREFIX_0F5D */ |
041bd2e0 | 4018 | { |
507bd325 L |
4019 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
4020 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
4021 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
4022 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4023 | }, |
4e7d34a6 | 4024 | |
1ceb70f8 | 4025 | /* PREFIX_0F5E */ |
041bd2e0 | 4026 | { |
507bd325 L |
4027 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
4028 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
4029 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
4030 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4031 | }, |
4e7d34a6 | 4032 | |
1ceb70f8 | 4033 | /* PREFIX_0F5F */ |
041bd2e0 | 4034 | { |
507bd325 L |
4035 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
4036 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
4037 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
4038 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4039 | }, |
4e7d34a6 | 4040 | |
1ceb70f8 | 4041 | /* PREFIX_0F60 */ |
041bd2e0 | 4042 | { |
507bd325 | 4043 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4044 | { Bad_Opcode }, |
507bd325 | 4045 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4046 | }, |
4e7d34a6 | 4047 | |
1ceb70f8 | 4048 | /* PREFIX_0F61 */ |
041bd2e0 | 4049 | { |
507bd325 | 4050 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4051 | { Bad_Opcode }, |
507bd325 | 4052 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4053 | }, |
4e7d34a6 | 4054 | |
1ceb70f8 | 4055 | /* PREFIX_0F62 */ |
041bd2e0 | 4056 | { |
507bd325 | 4057 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4058 | { Bad_Opcode }, |
507bd325 | 4059 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4060 | }, |
4e7d34a6 | 4061 | |
1ceb70f8 | 4062 | /* PREFIX_0F6C */ |
041bd2e0 | 4063 | { |
592d1631 L |
4064 | { Bad_Opcode }, |
4065 | { Bad_Opcode }, | |
507bd325 | 4066 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 4067 | }, |
4e7d34a6 | 4068 | |
1ceb70f8 | 4069 | /* PREFIX_0F6D */ |
0f17484f | 4070 | { |
592d1631 L |
4071 | { Bad_Opcode }, |
4072 | { Bad_Opcode }, | |
507bd325 | 4073 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 4074 | }, |
4e7d34a6 | 4075 | |
1ceb70f8 | 4076 | /* PREFIX_0F6F */ |
ca164297 | 4077 | { |
507bd325 L |
4078 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
4079 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
4080 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4081 | }, |
4e7d34a6 | 4082 | |
1ceb70f8 | 4083 | /* PREFIX_0F70 */ |
4e7d34a6 | 4084 | { |
507bd325 L |
4085 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
4086 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4087 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
4088 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4089 | }, |
4090 | ||
92fddf8e L |
4091 | /* PREFIX_0F73_REG_3 */ |
4092 | { | |
592d1631 L |
4093 | { Bad_Opcode }, |
4094 | { Bad_Opcode }, | |
bf890a93 | 4095 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
4096 | }, |
4097 | ||
4098 | /* PREFIX_0F73_REG_7 */ | |
4099 | { | |
592d1631 L |
4100 | { Bad_Opcode }, |
4101 | { Bad_Opcode }, | |
bf890a93 | 4102 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
4103 | }, |
4104 | ||
1ceb70f8 | 4105 | /* PREFIX_0F78 */ |
4e7d34a6 | 4106 | { |
bf890a93 | 4107 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4108 | { Bad_Opcode }, |
bf890a93 IT |
4109 | {"extrq", { XS, Ib, Ib }, 0 }, |
4110 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4111 | }, |
4112 | ||
1ceb70f8 | 4113 | /* PREFIX_0F79 */ |
4e7d34a6 | 4114 | { |
bf890a93 | 4115 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4116 | { Bad_Opcode }, |
bf890a93 IT |
4117 | {"extrq", { XM, XS }, 0 }, |
4118 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4119 | }, |
4120 | ||
1ceb70f8 | 4121 | /* PREFIX_0F7C */ |
ca164297 | 4122 | { |
592d1631 L |
4123 | { Bad_Opcode }, |
4124 | { Bad_Opcode }, | |
507bd325 L |
4125 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4126 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4127 | }, |
4e7d34a6 | 4128 | |
1ceb70f8 | 4129 | /* PREFIX_0F7D */ |
ca164297 | 4130 | { |
592d1631 L |
4131 | { Bad_Opcode }, |
4132 | { Bad_Opcode }, | |
507bd325 L |
4133 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4134 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4135 | }, |
4e7d34a6 | 4136 | |
1ceb70f8 | 4137 | /* PREFIX_0F7E */ |
ca164297 | 4138 | { |
507bd325 L |
4139 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4140 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4141 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4142 | }, |
4e7d34a6 | 4143 | |
1ceb70f8 | 4144 | /* PREFIX_0F7F */ |
ca164297 | 4145 | { |
507bd325 L |
4146 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4147 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4148 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4149 | }, |
4e7d34a6 | 4150 | |
c7b8aa3a L |
4151 | /* PREFIX_0FAE_REG_0 */ |
4152 | { | |
4153 | { Bad_Opcode }, | |
bf890a93 | 4154 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4155 | }, |
4156 | ||
4157 | /* PREFIX_0FAE_REG_1 */ | |
4158 | { | |
4159 | { Bad_Opcode }, | |
bf890a93 | 4160 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4161 | }, |
4162 | ||
4163 | /* PREFIX_0FAE_REG_2 */ | |
4164 | { | |
4165 | { Bad_Opcode }, | |
bf890a93 | 4166 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4167 | }, |
4168 | ||
4169 | /* PREFIX_0FAE_REG_3 */ | |
4170 | { | |
4171 | { Bad_Opcode }, | |
bf890a93 | 4172 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4173 | }, |
4174 | ||
6b40c462 L |
4175 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4176 | { | |
4177 | { "xsave", { FXSAVE }, 0 }, | |
4178 | { "ptwrite%LQ", { Edq }, 0 }, | |
4179 | }, | |
4180 | ||
4181 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4182 | { | |
4183 | { Bad_Opcode }, | |
4184 | { "ptwrite%LQ", { Edq }, 0 }, | |
4185 | }, | |
4186 | ||
603555e5 L |
4187 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
4188 | { | |
4189 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4190 | }, |
4191 | ||
4192 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
4193 | { | |
4194 | { "lfence", { Skip_MODRM }, 0 }, | |
4195 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4196 | }, |
4197 | ||
de89d0a3 | 4198 | /* PREFIX_MOD_0_0FAE_REG_6 */ |
c5e7287a | 4199 | { |
603555e5 L |
4200 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4201 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4202 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4203 | }, |
4204 | ||
de89d0a3 IT |
4205 | /* PREFIX_MOD_1_0FAE_REG_6 */ |
4206 | { | |
4207 | { RM_TABLE (RM_0FAE_REG_6) }, | |
4208 | { "umonitor", { Eva }, PREFIX_OPCODE }, | |
4209 | { "tpause", { Em }, PREFIX_OPCODE }, | |
4210 | { "umwait", { Em }, PREFIX_OPCODE }, | |
4211 | }, | |
4212 | ||
963f3586 IT |
4213 | /* PREFIX_0FAE_REG_7 */ |
4214 | { | |
bf890a93 | 4215 | { "clflush", { Mb }, 0 }, |
963f3586 | 4216 | { Bad_Opcode }, |
bf890a93 | 4217 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4218 | }, |
4219 | ||
1ceb70f8 | 4220 | /* PREFIX_0FB8 */ |
ca164297 | 4221 | { |
592d1631 | 4222 | { Bad_Opcode }, |
bf890a93 | 4223 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4224 | }, |
4e7d34a6 | 4225 | |
f12dc422 L |
4226 | /* PREFIX_0FBC */ |
4227 | { | |
bf890a93 IT |
4228 | { "bsfS", { Gv, Ev }, 0 }, |
4229 | { "tzcntS", { Gv, Ev }, 0 }, | |
4230 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4231 | }, |
4232 | ||
1ceb70f8 | 4233 | /* PREFIX_0FBD */ |
050dfa73 | 4234 | { |
bf890a93 IT |
4235 | { "bsrS", { Gv, Ev }, 0 }, |
4236 | { "lzcntS", { Gv, Ev }, 0 }, | |
4237 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4238 | }, |
4239 | ||
1ceb70f8 | 4240 | /* PREFIX_0FC2 */ |
050dfa73 | 4241 | { |
507bd325 L |
4242 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4243 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4244 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4245 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4246 | }, |
246c51aa | 4247 | |
a8484f96 | 4248 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4249 | { |
a8484f96 | 4250 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4251 | }, |
4252 | ||
f24bcbaa | 4253 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4254 | { |
bf890a93 IT |
4255 | { "vmptrld",{ Mq }, 0 }, |
4256 | { "vmxon", { Mq }, 0 }, | |
4257 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4258 | }, |
4259 | ||
f24bcbaa L |
4260 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4261 | { | |
4262 | { "rdrand", { Ev }, 0 }, | |
4263 | { Bad_Opcode }, | |
4264 | { "rdrand", { Ev }, 0 } | |
4265 | }, | |
4266 | ||
4267 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4268 | { | |
4269 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4270 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4271 | { "rdseed", { Ev }, 0 }, |
4272 | }, | |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0FD0 */ |
050dfa73 | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
bf890a93 IT |
4278 | { "addsubpd", { XM, EXx }, 0 }, |
4279 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4280 | }, |
050dfa73 | 4281 | |
1ceb70f8 | 4282 | /* PREFIX_0FD6 */ |
050dfa73 | 4283 | { |
592d1631 | 4284 | { Bad_Opcode }, |
bf890a93 IT |
4285 | { "movq2dq",{ XM, MS }, 0 }, |
4286 | { "movq", { EXqS, XM }, 0 }, | |
4287 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4288 | }, |
4289 | ||
1ceb70f8 | 4290 | /* PREFIX_0FE6 */ |
7918206c | 4291 | { |
592d1631 | 4292 | { Bad_Opcode }, |
507bd325 L |
4293 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4294 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4295 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4296 | }, |
8b38ad71 | 4297 | |
1ceb70f8 | 4298 | /* PREFIX_0FE7 */ |
8b38ad71 | 4299 | { |
507bd325 | 4300 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4301 | { Bad_Opcode }, |
75c135a8 | 4302 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4303 | }, |
4304 | ||
1ceb70f8 | 4305 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4306 | { |
592d1631 L |
4307 | { Bad_Opcode }, |
4308 | { Bad_Opcode }, | |
4309 | { Bad_Opcode }, | |
1ceb70f8 | 4310 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4311 | }, |
4312 | ||
1ceb70f8 | 4313 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4314 | { |
507bd325 | 4315 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4316 | { Bad_Opcode }, |
507bd325 | 4317 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4318 | }, |
42903f7f | 4319 | |
1ceb70f8 | 4320 | /* PREFIX_0F3810 */ |
42903f7f | 4321 | { |
592d1631 L |
4322 | { Bad_Opcode }, |
4323 | { Bad_Opcode }, | |
507bd325 | 4324 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4325 | }, |
4326 | ||
1ceb70f8 | 4327 | /* PREFIX_0F3814 */ |
42903f7f | 4328 | { |
592d1631 L |
4329 | { Bad_Opcode }, |
4330 | { Bad_Opcode }, | |
507bd325 | 4331 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4332 | }, |
4333 | ||
1ceb70f8 | 4334 | /* PREFIX_0F3815 */ |
42903f7f | 4335 | { |
592d1631 L |
4336 | { Bad_Opcode }, |
4337 | { Bad_Opcode }, | |
507bd325 | 4338 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4339 | }, |
4340 | ||
1ceb70f8 | 4341 | /* PREFIX_0F3817 */ |
42903f7f | 4342 | { |
592d1631 L |
4343 | { Bad_Opcode }, |
4344 | { Bad_Opcode }, | |
507bd325 | 4345 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4346 | }, |
4347 | ||
1ceb70f8 | 4348 | /* PREFIX_0F3820 */ |
42903f7f | 4349 | { |
592d1631 L |
4350 | { Bad_Opcode }, |
4351 | { Bad_Opcode }, | |
507bd325 | 4352 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4353 | }, |
4354 | ||
1ceb70f8 | 4355 | /* PREFIX_0F3821 */ |
42903f7f | 4356 | { |
592d1631 L |
4357 | { Bad_Opcode }, |
4358 | { Bad_Opcode }, | |
507bd325 | 4359 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4360 | }, |
4361 | ||
1ceb70f8 | 4362 | /* PREFIX_0F3822 */ |
42903f7f | 4363 | { |
592d1631 L |
4364 | { Bad_Opcode }, |
4365 | { Bad_Opcode }, | |
507bd325 | 4366 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4367 | }, |
4368 | ||
1ceb70f8 | 4369 | /* PREFIX_0F3823 */ |
42903f7f | 4370 | { |
592d1631 L |
4371 | { Bad_Opcode }, |
4372 | { Bad_Opcode }, | |
507bd325 | 4373 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4374 | }, |
4375 | ||
1ceb70f8 | 4376 | /* PREFIX_0F3824 */ |
42903f7f | 4377 | { |
592d1631 L |
4378 | { Bad_Opcode }, |
4379 | { Bad_Opcode }, | |
507bd325 | 4380 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4381 | }, |
4382 | ||
1ceb70f8 | 4383 | /* PREFIX_0F3825 */ |
42903f7f | 4384 | { |
592d1631 L |
4385 | { Bad_Opcode }, |
4386 | { Bad_Opcode }, | |
507bd325 | 4387 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4388 | }, |
4389 | ||
1ceb70f8 | 4390 | /* PREFIX_0F3828 */ |
42903f7f | 4391 | { |
592d1631 L |
4392 | { Bad_Opcode }, |
4393 | { Bad_Opcode }, | |
507bd325 | 4394 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4395 | }, |
4396 | ||
1ceb70f8 | 4397 | /* PREFIX_0F3829 */ |
42903f7f | 4398 | { |
592d1631 L |
4399 | { Bad_Opcode }, |
4400 | { Bad_Opcode }, | |
507bd325 | 4401 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4402 | }, |
4403 | ||
1ceb70f8 | 4404 | /* PREFIX_0F382A */ |
42903f7f | 4405 | { |
592d1631 L |
4406 | { Bad_Opcode }, |
4407 | { Bad_Opcode }, | |
75c135a8 | 4408 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4409 | }, |
4410 | ||
1ceb70f8 | 4411 | /* PREFIX_0F382B */ |
42903f7f | 4412 | { |
592d1631 L |
4413 | { Bad_Opcode }, |
4414 | { Bad_Opcode }, | |
507bd325 | 4415 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4416 | }, |
4417 | ||
1ceb70f8 | 4418 | /* PREFIX_0F3830 */ |
42903f7f | 4419 | { |
592d1631 L |
4420 | { Bad_Opcode }, |
4421 | { Bad_Opcode }, | |
507bd325 | 4422 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4423 | }, |
4424 | ||
1ceb70f8 | 4425 | /* PREFIX_0F3831 */ |
42903f7f | 4426 | { |
592d1631 L |
4427 | { Bad_Opcode }, |
4428 | { Bad_Opcode }, | |
507bd325 | 4429 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4430 | }, |
4431 | ||
1ceb70f8 | 4432 | /* PREFIX_0F3832 */ |
42903f7f | 4433 | { |
592d1631 L |
4434 | { Bad_Opcode }, |
4435 | { Bad_Opcode }, | |
507bd325 | 4436 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4437 | }, |
4438 | ||
1ceb70f8 | 4439 | /* PREFIX_0F3833 */ |
42903f7f | 4440 | { |
592d1631 L |
4441 | { Bad_Opcode }, |
4442 | { Bad_Opcode }, | |
507bd325 | 4443 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4444 | }, |
4445 | ||
1ceb70f8 | 4446 | /* PREFIX_0F3834 */ |
42903f7f | 4447 | { |
592d1631 L |
4448 | { Bad_Opcode }, |
4449 | { Bad_Opcode }, | |
507bd325 | 4450 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4451 | }, |
4452 | ||
1ceb70f8 | 4453 | /* PREFIX_0F3835 */ |
42903f7f | 4454 | { |
592d1631 L |
4455 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, | |
507bd325 | 4457 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4458 | }, |
4459 | ||
1ceb70f8 | 4460 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4461 | { |
592d1631 L |
4462 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, | |
507bd325 | 4464 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4465 | }, |
4466 | ||
1ceb70f8 | 4467 | /* PREFIX_0F3838 */ |
42903f7f | 4468 | { |
592d1631 L |
4469 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, | |
507bd325 | 4471 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4472 | }, |
4473 | ||
1ceb70f8 | 4474 | /* PREFIX_0F3839 */ |
42903f7f | 4475 | { |
592d1631 L |
4476 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, | |
507bd325 | 4478 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4479 | }, |
4480 | ||
1ceb70f8 | 4481 | /* PREFIX_0F383A */ |
42903f7f | 4482 | { |
592d1631 L |
4483 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, | |
507bd325 | 4485 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4486 | }, |
4487 | ||
1ceb70f8 | 4488 | /* PREFIX_0F383B */ |
42903f7f | 4489 | { |
592d1631 L |
4490 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, | |
507bd325 | 4492 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4493 | }, |
4494 | ||
1ceb70f8 | 4495 | /* PREFIX_0F383C */ |
42903f7f | 4496 | { |
592d1631 L |
4497 | { Bad_Opcode }, |
4498 | { Bad_Opcode }, | |
507bd325 | 4499 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4500 | }, |
4501 | ||
1ceb70f8 | 4502 | /* PREFIX_0F383D */ |
42903f7f | 4503 | { |
592d1631 L |
4504 | { Bad_Opcode }, |
4505 | { Bad_Opcode }, | |
507bd325 | 4506 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4507 | }, |
4508 | ||
1ceb70f8 | 4509 | /* PREFIX_0F383E */ |
42903f7f | 4510 | { |
592d1631 L |
4511 | { Bad_Opcode }, |
4512 | { Bad_Opcode }, | |
507bd325 | 4513 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4514 | }, |
4515 | ||
1ceb70f8 | 4516 | /* PREFIX_0F383F */ |
42903f7f | 4517 | { |
592d1631 L |
4518 | { Bad_Opcode }, |
4519 | { Bad_Opcode }, | |
507bd325 | 4520 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4521 | }, |
4522 | ||
1ceb70f8 | 4523 | /* PREFIX_0F3840 */ |
42903f7f | 4524 | { |
592d1631 L |
4525 | { Bad_Opcode }, |
4526 | { Bad_Opcode }, | |
507bd325 | 4527 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4528 | }, |
4529 | ||
1ceb70f8 | 4530 | /* PREFIX_0F3841 */ |
42903f7f | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
507bd325 | 4534 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4535 | }, |
4536 | ||
f1f8f695 L |
4537 | /* PREFIX_0F3880 */ |
4538 | { | |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
507bd325 | 4541 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4542 | }, |
4543 | ||
4544 | /* PREFIX_0F3881 */ | |
4545 | { | |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
507bd325 | 4548 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4549 | }, |
4550 | ||
6c30d220 L |
4551 | /* PREFIX_0F3882 */ |
4552 | { | |
4553 | { Bad_Opcode }, | |
4554 | { Bad_Opcode }, | |
507bd325 | 4555 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4556 | }, |
4557 | ||
a0046408 L |
4558 | /* PREFIX_0F38C8 */ |
4559 | { | |
507bd325 | 4560 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4561 | }, |
4562 | ||
4563 | /* PREFIX_0F38C9 */ | |
4564 | { | |
507bd325 | 4565 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4566 | }, |
4567 | ||
4568 | /* PREFIX_0F38CA */ | |
4569 | { | |
507bd325 | 4570 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4571 | }, |
4572 | ||
4573 | /* PREFIX_0F38CB */ | |
4574 | { | |
507bd325 | 4575 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4576 | }, |
4577 | ||
4578 | /* PREFIX_0F38CC */ | |
4579 | { | |
507bd325 | 4580 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4581 | }, |
4582 | ||
4583 | /* PREFIX_0F38CD */ | |
4584 | { | |
507bd325 | 4585 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4586 | }, |
4587 | ||
48521003 IT |
4588 | /* PREFIX_0F38CF */ |
4589 | { | |
4590 | { Bad_Opcode }, | |
4591 | { Bad_Opcode }, | |
4592 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4593 | }, | |
4594 | ||
c0f3af97 L |
4595 | /* PREFIX_0F38DB */ |
4596 | { | |
592d1631 L |
4597 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, | |
507bd325 | 4599 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4600 | }, |
4601 | ||
4602 | /* PREFIX_0F38DC */ | |
4603 | { | |
592d1631 L |
4604 | { Bad_Opcode }, |
4605 | { Bad_Opcode }, | |
507bd325 | 4606 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4607 | }, |
4608 | ||
4609 | /* PREFIX_0F38DD */ | |
4610 | { | |
592d1631 L |
4611 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, | |
507bd325 | 4613 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4614 | }, |
4615 | ||
4616 | /* PREFIX_0F38DE */ | |
4617 | { | |
592d1631 L |
4618 | { Bad_Opcode }, |
4619 | { Bad_Opcode }, | |
507bd325 | 4620 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4621 | }, |
4622 | ||
4623 | /* PREFIX_0F38DF */ | |
4624 | { | |
592d1631 L |
4625 | { Bad_Opcode }, |
4626 | { Bad_Opcode }, | |
507bd325 | 4627 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4628 | }, |
4629 | ||
1ceb70f8 | 4630 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4631 | { |
507bd325 | 4632 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4633 | { Bad_Opcode }, |
507bd325 L |
4634 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4635 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4636 | }, |
4637 | ||
1ceb70f8 | 4638 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4639 | { |
507bd325 | 4640 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4641 | { Bad_Opcode }, |
507bd325 L |
4642 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4643 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4644 | }, |
4645 | ||
603555e5 | 4646 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4647 | { |
4648 | { Bad_Opcode }, | |
603555e5 L |
4649 | { Bad_Opcode }, |
4650 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4651 | }, | |
4652 | ||
4653 | /* PREFIX_0F38F6 */ | |
4654 | { | |
4655 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4656 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4657 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4658 | { Bad_Opcode }, |
4659 | }, | |
4660 | ||
1ceb70f8 | 4661 | /* PREFIX_0F3A08 */ |
42903f7f | 4662 | { |
592d1631 L |
4663 | { Bad_Opcode }, |
4664 | { Bad_Opcode }, | |
507bd325 | 4665 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4666 | }, |
4667 | ||
1ceb70f8 | 4668 | /* PREFIX_0F3A09 */ |
42903f7f | 4669 | { |
592d1631 L |
4670 | { Bad_Opcode }, |
4671 | { Bad_Opcode }, | |
507bd325 | 4672 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4673 | }, |
4674 | ||
1ceb70f8 | 4675 | /* PREFIX_0F3A0A */ |
42903f7f | 4676 | { |
592d1631 L |
4677 | { Bad_Opcode }, |
4678 | { Bad_Opcode }, | |
507bd325 | 4679 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4680 | }, |
4681 | ||
1ceb70f8 | 4682 | /* PREFIX_0F3A0B */ |
42903f7f | 4683 | { |
592d1631 L |
4684 | { Bad_Opcode }, |
4685 | { Bad_Opcode }, | |
507bd325 | 4686 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4687 | }, |
4688 | ||
1ceb70f8 | 4689 | /* PREFIX_0F3A0C */ |
42903f7f | 4690 | { |
592d1631 L |
4691 | { Bad_Opcode }, |
4692 | { Bad_Opcode }, | |
507bd325 | 4693 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4694 | }, |
4695 | ||
1ceb70f8 | 4696 | /* PREFIX_0F3A0D */ |
42903f7f | 4697 | { |
592d1631 L |
4698 | { Bad_Opcode }, |
4699 | { Bad_Opcode }, | |
507bd325 | 4700 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4701 | }, |
4702 | ||
1ceb70f8 | 4703 | /* PREFIX_0F3A0E */ |
42903f7f | 4704 | { |
592d1631 L |
4705 | { Bad_Opcode }, |
4706 | { Bad_Opcode }, | |
507bd325 | 4707 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4708 | }, |
4709 | ||
1ceb70f8 | 4710 | /* PREFIX_0F3A14 */ |
42903f7f | 4711 | { |
592d1631 L |
4712 | { Bad_Opcode }, |
4713 | { Bad_Opcode }, | |
507bd325 | 4714 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4715 | }, |
4716 | ||
1ceb70f8 | 4717 | /* PREFIX_0F3A15 */ |
42903f7f | 4718 | { |
592d1631 L |
4719 | { Bad_Opcode }, |
4720 | { Bad_Opcode }, | |
507bd325 | 4721 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4722 | }, |
4723 | ||
1ceb70f8 | 4724 | /* PREFIX_0F3A16 */ |
42903f7f | 4725 | { |
592d1631 L |
4726 | { Bad_Opcode }, |
4727 | { Bad_Opcode }, | |
507bd325 | 4728 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4729 | }, |
4730 | ||
1ceb70f8 | 4731 | /* PREFIX_0F3A17 */ |
42903f7f | 4732 | { |
592d1631 L |
4733 | { Bad_Opcode }, |
4734 | { Bad_Opcode }, | |
507bd325 | 4735 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4736 | }, |
4737 | ||
1ceb70f8 | 4738 | /* PREFIX_0F3A20 */ |
42903f7f | 4739 | { |
592d1631 L |
4740 | { Bad_Opcode }, |
4741 | { Bad_Opcode }, | |
507bd325 | 4742 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4743 | }, |
4744 | ||
1ceb70f8 | 4745 | /* PREFIX_0F3A21 */ |
42903f7f | 4746 | { |
592d1631 L |
4747 | { Bad_Opcode }, |
4748 | { Bad_Opcode }, | |
507bd325 | 4749 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4750 | }, |
4751 | ||
1ceb70f8 | 4752 | /* PREFIX_0F3A22 */ |
42903f7f | 4753 | { |
592d1631 L |
4754 | { Bad_Opcode }, |
4755 | { Bad_Opcode }, | |
507bd325 | 4756 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4757 | }, |
4758 | ||
1ceb70f8 | 4759 | /* PREFIX_0F3A40 */ |
42903f7f | 4760 | { |
592d1631 L |
4761 | { Bad_Opcode }, |
4762 | { Bad_Opcode }, | |
507bd325 | 4763 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4764 | }, |
4765 | ||
1ceb70f8 | 4766 | /* PREFIX_0F3A41 */ |
42903f7f | 4767 | { |
592d1631 L |
4768 | { Bad_Opcode }, |
4769 | { Bad_Opcode }, | |
507bd325 | 4770 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4771 | }, |
4772 | ||
1ceb70f8 | 4773 | /* PREFIX_0F3A42 */ |
42903f7f | 4774 | { |
592d1631 L |
4775 | { Bad_Opcode }, |
4776 | { Bad_Opcode }, | |
507bd325 | 4777 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4778 | }, |
381d071f | 4779 | |
c0f3af97 L |
4780 | /* PREFIX_0F3A44 */ |
4781 | { | |
592d1631 L |
4782 | { Bad_Opcode }, |
4783 | { Bad_Opcode }, | |
507bd325 | 4784 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4785 | }, |
4786 | ||
1ceb70f8 | 4787 | /* PREFIX_0F3A60 */ |
381d071f | 4788 | { |
592d1631 L |
4789 | { Bad_Opcode }, |
4790 | { Bad_Opcode }, | |
15c7c1d8 | 4791 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4792 | }, |
4793 | ||
1ceb70f8 | 4794 | /* PREFIX_0F3A61 */ |
381d071f | 4795 | { |
592d1631 L |
4796 | { Bad_Opcode }, |
4797 | { Bad_Opcode }, | |
15c7c1d8 | 4798 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4799 | }, |
4800 | ||
1ceb70f8 | 4801 | /* PREFIX_0F3A62 */ |
381d071f | 4802 | { |
592d1631 L |
4803 | { Bad_Opcode }, |
4804 | { Bad_Opcode }, | |
507bd325 | 4805 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4806 | }, |
4807 | ||
1ceb70f8 | 4808 | /* PREFIX_0F3A63 */ |
381d071f | 4809 | { |
592d1631 L |
4810 | { Bad_Opcode }, |
4811 | { Bad_Opcode }, | |
507bd325 | 4812 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4813 | }, |
09a2c6cf | 4814 | |
a0046408 L |
4815 | /* PREFIX_0F3ACC */ |
4816 | { | |
507bd325 | 4817 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4818 | }, |
4819 | ||
48521003 IT |
4820 | /* PREFIX_0F3ACE */ |
4821 | { | |
4822 | { Bad_Opcode }, | |
4823 | { Bad_Opcode }, | |
4824 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4825 | }, | |
4826 | ||
4827 | /* PREFIX_0F3ACF */ | |
4828 | { | |
4829 | { Bad_Opcode }, | |
4830 | { Bad_Opcode }, | |
4831 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4832 | }, | |
4833 | ||
c0f3af97 | 4834 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4835 | { |
592d1631 L |
4836 | { Bad_Opcode }, |
4837 | { Bad_Opcode }, | |
507bd325 | 4838 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4839 | }, |
4840 | ||
592a252b | 4841 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4842 | { |
592a252b L |
4843 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4844 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4845 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4846 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4847 | }, |
4848 | ||
592a252b | 4849 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4850 | { |
592a252b L |
4851 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4852 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4853 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4854 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4855 | }, |
4856 | ||
592a252b | 4857 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4858 | { |
592a252b L |
4859 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4860 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4861 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4862 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4863 | }, |
4864 | ||
592a252b | 4865 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4866 | { |
592a252b L |
4867 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4868 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4869 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4870 | }, |
7c52e0e8 | 4871 | |
592a252b | 4872 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4873 | { |
592d1631 | 4874 | { Bad_Opcode }, |
592a252b | 4875 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4876 | { Bad_Opcode }, |
592a252b | 4877 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4878 | }, |
7c52e0e8 | 4879 | |
592a252b | 4880 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4881 | { |
592d1631 | 4882 | { Bad_Opcode }, |
592a252b | 4883 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4884 | { Bad_Opcode }, |
592a252b | 4885 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4886 | }, |
7c52e0e8 | 4887 | |
592a252b | 4888 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4889 | { |
592d1631 | 4890 | { Bad_Opcode }, |
592a252b | 4891 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4892 | { Bad_Opcode }, |
592a252b | 4893 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4894 | }, |
4895 | ||
592a252b | 4896 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4897 | { |
592a252b | 4898 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4899 | { Bad_Opcode }, |
592a252b | 4900 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4901 | }, |
4902 | ||
592a252b | 4903 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4904 | { |
592a252b | 4905 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4906 | { Bad_Opcode }, |
592a252b | 4907 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4908 | }, |
4909 | ||
43234a1e L |
4910 | /* PREFIX_VEX_0F41 */ |
4911 | { | |
4912 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4913 | { Bad_Opcode }, |
4914 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4915 | }, |
4916 | ||
4917 | /* PREFIX_VEX_0F42 */ | |
4918 | { | |
4919 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4920 | { Bad_Opcode }, |
4921 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4922 | }, |
4923 | ||
4924 | /* PREFIX_VEX_0F44 */ | |
4925 | { | |
4926 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4927 | { Bad_Opcode }, |
4928 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4929 | }, |
4930 | ||
4931 | /* PREFIX_VEX_0F45 */ | |
4932 | { | |
4933 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4934 | { Bad_Opcode }, |
4935 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4936 | }, |
4937 | ||
4938 | /* PREFIX_VEX_0F46 */ | |
4939 | { | |
4940 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4941 | { Bad_Opcode }, |
4942 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4943 | }, |
4944 | ||
4945 | /* PREFIX_VEX_0F47 */ | |
4946 | { | |
4947 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4948 | { Bad_Opcode }, |
4949 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4950 | }, |
4951 | ||
1ba585e8 | 4952 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4953 | { |
1ba585e8 | 4954 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4955 | { Bad_Opcode }, |
1ba585e8 IT |
4956 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4957 | }, | |
4958 | ||
4959 | /* PREFIX_VEX_0F4B */ | |
4960 | { | |
4961 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4962 | { Bad_Opcode }, |
4963 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4964 | }, | |
4965 | ||
592a252b | 4966 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4967 | { |
592a252b L |
4968 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4969 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4970 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4971 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4972 | }, |
4973 | ||
592a252b | 4974 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4975 | { |
592a252b L |
4976 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4977 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4978 | }, |
4979 | ||
592a252b | 4980 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4981 | { |
592a252b L |
4982 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4983 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4987 | { |
592a252b L |
4988 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4989 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4990 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4991 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4992 | }, |
4993 | ||
592a252b | 4994 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4995 | { |
592a252b L |
4996 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4997 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4998 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4999 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
5000 | }, |
5001 | ||
592a252b | 5002 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 5003 | { |
592a252b L |
5004 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
5005 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 5006 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 5007 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
5008 | }, |
5009 | ||
592a252b | 5010 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 5011 | { |
592a252b L |
5012 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
5013 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
5014 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
5015 | }, |
5016 | ||
592a252b | 5017 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 5018 | { |
592a252b L |
5019 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
5020 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
5021 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
5022 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 5026 | { |
592a252b L |
5027 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
5028 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
5029 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
5030 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
5031 | }, |
5032 | ||
592a252b | 5033 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 5034 | { |
592a252b L |
5035 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
5036 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
5037 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
5038 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
5039 | }, |
5040 | ||
592a252b | 5041 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 5042 | { |
592a252b L |
5043 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
5044 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
5045 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
5046 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 5050 | { |
592d1631 L |
5051 | { Bad_Opcode }, |
5052 | { Bad_Opcode }, | |
6c30d220 | 5053 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 5057 | { |
592d1631 L |
5058 | { Bad_Opcode }, |
5059 | { Bad_Opcode }, | |
6c30d220 | 5060 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 5064 | { |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
6c30d220 | 5067 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
5068 | }, |
5069 | ||
592a252b | 5070 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 5071 | { |
592d1631 L |
5072 | { Bad_Opcode }, |
5073 | { Bad_Opcode }, | |
6c30d220 | 5074 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
5075 | }, |
5076 | ||
592a252b | 5077 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 5078 | { |
592d1631 L |
5079 | { Bad_Opcode }, |
5080 | { Bad_Opcode }, | |
6c30d220 | 5081 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
5082 | }, |
5083 | ||
592a252b | 5084 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 5085 | { |
592d1631 L |
5086 | { Bad_Opcode }, |
5087 | { Bad_Opcode }, | |
6c30d220 | 5088 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
5089 | }, |
5090 | ||
592a252b | 5091 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 5092 | { |
592d1631 L |
5093 | { Bad_Opcode }, |
5094 | { Bad_Opcode }, | |
6c30d220 | 5095 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 5096 | }, |
6439fc28 | 5097 | |
592a252b | 5098 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 5099 | { |
592d1631 L |
5100 | { Bad_Opcode }, |
5101 | { Bad_Opcode }, | |
6c30d220 | 5102 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
5103 | }, |
5104 | ||
592a252b | 5105 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 5106 | { |
592d1631 L |
5107 | { Bad_Opcode }, |
5108 | { Bad_Opcode }, | |
6c30d220 | 5109 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
5110 | }, |
5111 | ||
592a252b | 5112 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 5113 | { |
592d1631 L |
5114 | { Bad_Opcode }, |
5115 | { Bad_Opcode }, | |
6c30d220 | 5116 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
5117 | }, |
5118 | ||
592a252b | 5119 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 5120 | { |
592d1631 L |
5121 | { Bad_Opcode }, |
5122 | { Bad_Opcode }, | |
6c30d220 | 5123 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
5124 | }, |
5125 | ||
592a252b | 5126 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 5127 | { |
592d1631 L |
5128 | { Bad_Opcode }, |
5129 | { Bad_Opcode }, | |
6c30d220 | 5130 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
5131 | }, |
5132 | ||
592a252b | 5133 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 5134 | { |
592d1631 L |
5135 | { Bad_Opcode }, |
5136 | { Bad_Opcode }, | |
6c30d220 | 5137 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
5138 | }, |
5139 | ||
592a252b | 5140 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 5141 | { |
592d1631 L |
5142 | { Bad_Opcode }, |
5143 | { Bad_Opcode }, | |
6c30d220 | 5144 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5145 | }, |
5146 | ||
592a252b | 5147 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5148 | { |
592d1631 L |
5149 | { Bad_Opcode }, |
5150 | { Bad_Opcode }, | |
592a252b | 5151 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5152 | }, |
5153 | ||
592a252b | 5154 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5155 | { |
592d1631 | 5156 | { Bad_Opcode }, |
592a252b L |
5157 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5158 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5162 | { |
592d1631 | 5163 | { Bad_Opcode }, |
6c30d220 L |
5164 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5165 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5166 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5167 | }, |
5168 | ||
592a252b | 5169 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5170 | { |
592d1631 L |
5171 | { Bad_Opcode }, |
5172 | { Bad_Opcode }, | |
6c30d220 | 5173 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5174 | }, |
5175 | ||
592a252b | 5176 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5177 | { |
592d1631 L |
5178 | { Bad_Opcode }, |
5179 | { Bad_Opcode }, | |
6c30d220 | 5180 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5181 | }, |
5182 | ||
592a252b | 5183 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5184 | { |
592d1631 L |
5185 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, | |
6c30d220 | 5187 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5188 | }, |
5189 | ||
592a252b | 5190 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5191 | { |
592d1631 L |
5192 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, | |
6c30d220 | 5194 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5195 | }, |
5196 | ||
592a252b | 5197 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5198 | { |
592d1631 L |
5199 | { Bad_Opcode }, |
5200 | { Bad_Opcode }, | |
6c30d220 | 5201 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5202 | }, |
5203 | ||
592a252b | 5204 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5205 | { |
592d1631 L |
5206 | { Bad_Opcode }, |
5207 | { Bad_Opcode }, | |
6c30d220 | 5208 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5209 | }, |
5210 | ||
592a252b | 5211 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5212 | { |
592d1631 L |
5213 | { Bad_Opcode }, |
5214 | { Bad_Opcode }, | |
6c30d220 | 5215 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
6c30d220 | 5222 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
6c30d220 | 5229 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
6c30d220 | 5236 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
6c30d220 | 5243 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
6c30d220 | 5250 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
6c30d220 | 5257 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5261 | { |
592a252b | 5262 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5263 | }, |
5264 | ||
592a252b | 5265 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5266 | { |
592d1631 L |
5267 | { Bad_Opcode }, |
5268 | { Bad_Opcode }, | |
592a252b L |
5269 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5270 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5271 | }, |
5272 | ||
592a252b | 5273 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5274 | { |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
592a252b L |
5277 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5278 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5279 | }, |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5282 | { |
592d1631 | 5283 | { Bad_Opcode }, |
592a252b L |
5284 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5285 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5289 | { |
592d1631 | 5290 | { Bad_Opcode }, |
592a252b L |
5291 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5292 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5293 | }, |
5294 | ||
43234a1e L |
5295 | /* PREFIX_VEX_0F90 */ |
5296 | { | |
5297 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5298 | { Bad_Opcode }, |
5299 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5300 | }, |
5301 | ||
5302 | /* PREFIX_VEX_0F91 */ | |
5303 | { | |
5304 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5305 | { Bad_Opcode }, |
5306 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5307 | }, |
5308 | ||
5309 | /* PREFIX_VEX_0F92 */ | |
5310 | { | |
5311 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5312 | { Bad_Opcode }, |
90a915bf | 5313 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5314 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5315 | }, |
5316 | ||
5317 | /* PREFIX_VEX_0F93 */ | |
5318 | { | |
5319 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5320 | { Bad_Opcode }, |
90a915bf | 5321 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5322 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5323 | }, |
5324 | ||
5325 | /* PREFIX_VEX_0F98 */ | |
5326 | { | |
5327 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5328 | { Bad_Opcode }, |
5329 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5330 | }, | |
5331 | ||
5332 | /* PREFIX_VEX_0F99 */ | |
5333 | { | |
5334 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5335 | { Bad_Opcode }, | |
5336 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5337 | }, |
5338 | ||
592a252b | 5339 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5340 | { |
592a252b L |
5341 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5342 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5343 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5344 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5345 | }, |
5346 | ||
592a252b | 5347 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5348 | { |
592d1631 L |
5349 | { Bad_Opcode }, |
5350 | { Bad_Opcode }, | |
592a252b | 5351 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5352 | }, |
5353 | ||
592a252b | 5354 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5355 | { |
592d1631 L |
5356 | { Bad_Opcode }, |
5357 | { Bad_Opcode }, | |
592a252b | 5358 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5359 | }, |
5360 | ||
592a252b | 5361 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5362 | { |
592d1631 L |
5363 | { Bad_Opcode }, |
5364 | { Bad_Opcode }, | |
592a252b L |
5365 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5366 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5367 | }, |
5368 | ||
592a252b | 5369 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5370 | { |
592d1631 L |
5371 | { Bad_Opcode }, |
5372 | { Bad_Opcode }, | |
6c30d220 | 5373 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5374 | }, |
5375 | ||
592a252b | 5376 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5377 | { |
592d1631 L |
5378 | { Bad_Opcode }, |
5379 | { Bad_Opcode }, | |
6c30d220 | 5380 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5381 | }, |
5382 | ||
592a252b | 5383 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5384 | { |
592d1631 L |
5385 | { Bad_Opcode }, |
5386 | { Bad_Opcode }, | |
6c30d220 | 5387 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5388 | }, |
5389 | ||
592a252b | 5390 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5391 | { |
592d1631 L |
5392 | { Bad_Opcode }, |
5393 | { Bad_Opcode }, | |
6c30d220 | 5394 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5395 | }, |
5396 | ||
592a252b | 5397 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5398 | { |
592d1631 L |
5399 | { Bad_Opcode }, |
5400 | { Bad_Opcode }, | |
6c30d220 | 5401 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5402 | }, |
5403 | ||
592a252b | 5404 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5405 | { |
592d1631 L |
5406 | { Bad_Opcode }, |
5407 | { Bad_Opcode }, | |
592a252b | 5408 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5409 | }, |
5410 | ||
592a252b | 5411 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5412 | { |
592d1631 L |
5413 | { Bad_Opcode }, |
5414 | { Bad_Opcode }, | |
592a252b | 5415 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5416 | }, |
5417 | ||
592a252b | 5418 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5419 | { |
592d1631 L |
5420 | { Bad_Opcode }, |
5421 | { Bad_Opcode }, | |
6c30d220 | 5422 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5423 | }, |
5424 | ||
592a252b | 5425 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5426 | { |
592d1631 L |
5427 | { Bad_Opcode }, |
5428 | { Bad_Opcode }, | |
6c30d220 | 5429 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5430 | }, |
5431 | ||
592a252b | 5432 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5433 | { |
592d1631 L |
5434 | { Bad_Opcode }, |
5435 | { Bad_Opcode }, | |
6c30d220 | 5436 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5437 | }, |
5438 | ||
592a252b | 5439 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5440 | { |
592d1631 L |
5441 | { Bad_Opcode }, |
5442 | { Bad_Opcode }, | |
6c30d220 | 5443 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5444 | }, |
5445 | ||
592a252b | 5446 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5447 | { |
592d1631 L |
5448 | { Bad_Opcode }, |
5449 | { Bad_Opcode }, | |
6c30d220 | 5450 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5451 | }, |
5452 | ||
592a252b | 5453 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5454 | { |
592d1631 L |
5455 | { Bad_Opcode }, |
5456 | { Bad_Opcode }, | |
6c30d220 | 5457 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5458 | }, |
5459 | ||
592a252b | 5460 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5461 | { |
592d1631 L |
5462 | { Bad_Opcode }, |
5463 | { Bad_Opcode }, | |
6c30d220 | 5464 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5465 | }, |
5466 | ||
592a252b | 5467 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5468 | { |
592d1631 L |
5469 | { Bad_Opcode }, |
5470 | { Bad_Opcode }, | |
6c30d220 | 5471 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5472 | }, |
5473 | ||
592a252b | 5474 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5475 | { |
592d1631 L |
5476 | { Bad_Opcode }, |
5477 | { Bad_Opcode }, | |
6c30d220 | 5478 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5479 | }, |
5480 | ||
592a252b | 5481 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5482 | { |
592d1631 L |
5483 | { Bad_Opcode }, |
5484 | { Bad_Opcode }, | |
6c30d220 | 5485 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5486 | }, |
5487 | ||
592a252b | 5488 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5489 | { |
592d1631 L |
5490 | { Bad_Opcode }, |
5491 | { Bad_Opcode }, | |
6c30d220 | 5492 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5493 | }, |
5494 | ||
592a252b | 5495 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5496 | { |
592d1631 L |
5497 | { Bad_Opcode }, |
5498 | { Bad_Opcode }, | |
6c30d220 | 5499 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5500 | }, |
5501 | ||
592a252b | 5502 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5503 | { |
592d1631 L |
5504 | { Bad_Opcode }, |
5505 | { Bad_Opcode }, | |
6c30d220 | 5506 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5507 | }, |
5508 | ||
592a252b | 5509 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5510 | { |
592d1631 L |
5511 | { Bad_Opcode }, |
5512 | { Bad_Opcode }, | |
6c30d220 | 5513 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5514 | }, |
5515 | ||
592a252b | 5516 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5517 | { |
592d1631 | 5518 | { Bad_Opcode }, |
592a252b L |
5519 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5520 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5521 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5522 | }, |
5523 | ||
592a252b | 5524 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5525 | { |
592d1631 L |
5526 | { Bad_Opcode }, |
5527 | { Bad_Opcode }, | |
592a252b | 5528 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5529 | }, |
5530 | ||
592a252b | 5531 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5532 | { |
592d1631 L |
5533 | { Bad_Opcode }, |
5534 | { Bad_Opcode }, | |
6c30d220 | 5535 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5536 | }, |
5537 | ||
592a252b | 5538 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5539 | { |
592d1631 L |
5540 | { Bad_Opcode }, |
5541 | { Bad_Opcode }, | |
6c30d220 | 5542 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5543 | }, |
5544 | ||
592a252b | 5545 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5546 | { |
592d1631 L |
5547 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, | |
6c30d220 | 5549 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5550 | }, |
5551 | ||
592a252b | 5552 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5553 | { |
592d1631 L |
5554 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, | |
6c30d220 | 5556 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5557 | }, |
5558 | ||
592a252b | 5559 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5560 | { |
592d1631 L |
5561 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, | |
6c30d220 | 5563 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5564 | }, |
5565 | ||
592a252b | 5566 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5567 | { |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
6c30d220 | 5570 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5571 | }, |
5572 | ||
592a252b | 5573 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5574 | { |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
6c30d220 | 5577 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5578 | }, |
5579 | ||
592a252b | 5580 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5581 | { |
592d1631 L |
5582 | { Bad_Opcode }, |
5583 | { Bad_Opcode }, | |
6c30d220 | 5584 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5585 | }, |
5586 | ||
592a252b | 5587 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5588 | { |
592d1631 L |
5589 | { Bad_Opcode }, |
5590 | { Bad_Opcode }, | |
5591 | { Bad_Opcode }, | |
592a252b | 5592 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5593 | }, |
5594 | ||
592a252b | 5595 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5596 | { |
592d1631 L |
5597 | { Bad_Opcode }, |
5598 | { Bad_Opcode }, | |
6c30d220 | 5599 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5600 | }, |
5601 | ||
592a252b | 5602 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5603 | { |
592d1631 L |
5604 | { Bad_Opcode }, |
5605 | { Bad_Opcode }, | |
6c30d220 | 5606 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5607 | }, |
5608 | ||
592a252b | 5609 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5610 | { |
592d1631 L |
5611 | { Bad_Opcode }, |
5612 | { Bad_Opcode }, | |
6c30d220 | 5613 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5614 | }, |
5615 | ||
592a252b | 5616 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5617 | { |
592d1631 L |
5618 | { Bad_Opcode }, |
5619 | { Bad_Opcode }, | |
6c30d220 | 5620 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5621 | }, |
5622 | ||
592a252b | 5623 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5624 | { |
592d1631 L |
5625 | { Bad_Opcode }, |
5626 | { Bad_Opcode }, | |
6c30d220 | 5627 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5628 | }, |
5629 | ||
592a252b | 5630 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5631 | { |
592d1631 L |
5632 | { Bad_Opcode }, |
5633 | { Bad_Opcode }, | |
6c30d220 | 5634 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5635 | }, |
5636 | ||
592a252b | 5637 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5638 | { |
592d1631 L |
5639 | { Bad_Opcode }, |
5640 | { Bad_Opcode }, | |
592a252b | 5641 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5642 | }, |
5643 | ||
592a252b | 5644 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5645 | { |
592d1631 L |
5646 | { Bad_Opcode }, |
5647 | { Bad_Opcode }, | |
6c30d220 | 5648 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5649 | }, |
5650 | ||
592a252b | 5651 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5652 | { |
592d1631 L |
5653 | { Bad_Opcode }, |
5654 | { Bad_Opcode }, | |
6c30d220 | 5655 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5656 | }, |
5657 | ||
592a252b | 5658 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5659 | { |
592d1631 L |
5660 | { Bad_Opcode }, |
5661 | { Bad_Opcode }, | |
6c30d220 | 5662 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5663 | }, |
5664 | ||
592a252b | 5665 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5666 | { |
592d1631 L |
5667 | { Bad_Opcode }, |
5668 | { Bad_Opcode }, | |
6c30d220 | 5669 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5670 | }, |
5671 | ||
592a252b | 5672 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5673 | { |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
6c30d220 | 5676 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5677 | }, |
5678 | ||
592a252b | 5679 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5680 | { |
592d1631 L |
5681 | { Bad_Opcode }, |
5682 | { Bad_Opcode }, | |
6c30d220 | 5683 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5684 | }, |
5685 | ||
592a252b | 5686 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5687 | { |
592d1631 L |
5688 | { Bad_Opcode }, |
5689 | { Bad_Opcode }, | |
6c30d220 | 5690 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5691 | }, |
5692 | ||
592a252b | 5693 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5694 | { |
592d1631 L |
5695 | { Bad_Opcode }, |
5696 | { Bad_Opcode }, | |
6c30d220 | 5697 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5698 | }, |
5699 | ||
592a252b | 5700 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5701 | { |
592d1631 L |
5702 | { Bad_Opcode }, |
5703 | { Bad_Opcode }, | |
6c30d220 | 5704 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5705 | }, |
5706 | ||
592a252b | 5707 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5708 | { |
592d1631 L |
5709 | { Bad_Opcode }, |
5710 | { Bad_Opcode }, | |
6c30d220 | 5711 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5712 | }, |
5713 | ||
592a252b | 5714 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5715 | { |
592d1631 L |
5716 | { Bad_Opcode }, |
5717 | { Bad_Opcode }, | |
6c30d220 | 5718 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5719 | }, |
5720 | ||
592a252b | 5721 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5722 | { |
592d1631 L |
5723 | { Bad_Opcode }, |
5724 | { Bad_Opcode }, | |
6c30d220 | 5725 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5726 | }, |
5727 | ||
592a252b | 5728 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5729 | { |
592d1631 L |
5730 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, | |
6c30d220 | 5732 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5733 | }, |
5734 | ||
592a252b | 5735 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5736 | { |
592d1631 L |
5737 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, | |
6c30d220 | 5739 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5740 | }, |
5741 | ||
592a252b | 5742 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5743 | { |
592d1631 L |
5744 | { Bad_Opcode }, |
5745 | { Bad_Opcode }, | |
6c30d220 | 5746 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5747 | }, |
5748 | ||
592a252b | 5749 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5750 | { |
592d1631 L |
5751 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, | |
6c30d220 | 5753 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5754 | }, |
5755 | ||
592a252b | 5756 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5757 | { |
592d1631 L |
5758 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, | |
6c30d220 | 5760 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5761 | }, |
5762 | ||
592a252b | 5763 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5764 | { |
592d1631 L |
5765 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, | |
6c30d220 | 5767 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5768 | }, |
5769 | ||
592a252b | 5770 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5771 | { |
592d1631 L |
5772 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, | |
6c30d220 | 5774 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5775 | }, |
5776 | ||
592a252b | 5777 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5778 | { |
592d1631 L |
5779 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, | |
592a252b | 5781 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5782 | }, |
5783 | ||
592a252b | 5784 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5785 | { |
592d1631 L |
5786 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, | |
592a252b | 5788 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5789 | }, |
5790 | ||
592a252b | 5791 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5792 | { |
592d1631 L |
5793 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, | |
592a252b | 5795 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5796 | }, |
5797 | ||
592a252b | 5798 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5799 | { |
592d1631 L |
5800 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, | |
592a252b | 5802 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5803 | }, |
5804 | ||
592a252b | 5805 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5806 | { |
5807 | { Bad_Opcode }, | |
5808 | { Bad_Opcode }, | |
bf890a93 | 5809 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5810 | }, |
5811 | ||
6c30d220 L |
5812 | /* PREFIX_VEX_0F3816 */ |
5813 | { | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
5816 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5817 | }, | |
5818 | ||
592a252b | 5819 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5820 | { |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
592a252b | 5823 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5824 | }, |
5825 | ||
592a252b | 5826 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5827 | { |
592d1631 L |
5828 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, | |
6c30d220 | 5830 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5831 | }, |
5832 | ||
592a252b | 5833 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5834 | { |
592d1631 L |
5835 | { Bad_Opcode }, |
5836 | { Bad_Opcode }, | |
6c30d220 | 5837 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5838 | }, |
5839 | ||
592a252b | 5840 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5841 | { |
592d1631 L |
5842 | { Bad_Opcode }, |
5843 | { Bad_Opcode }, | |
592a252b | 5844 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5845 | }, |
5846 | ||
592a252b | 5847 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5848 | { |
592d1631 L |
5849 | { Bad_Opcode }, |
5850 | { Bad_Opcode }, | |
6c30d220 | 5851 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5852 | }, |
5853 | ||
592a252b | 5854 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5855 | { |
592d1631 L |
5856 | { Bad_Opcode }, |
5857 | { Bad_Opcode }, | |
6c30d220 | 5858 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5859 | }, |
5860 | ||
592a252b | 5861 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5862 | { |
592d1631 L |
5863 | { Bad_Opcode }, |
5864 | { Bad_Opcode }, | |
6c30d220 | 5865 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5866 | }, |
5867 | ||
592a252b | 5868 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5869 | { |
592d1631 L |
5870 | { Bad_Opcode }, |
5871 | { Bad_Opcode }, | |
6c30d220 | 5872 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5873 | }, |
5874 | ||
592a252b | 5875 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5876 | { |
592d1631 L |
5877 | { Bad_Opcode }, |
5878 | { Bad_Opcode }, | |
6c30d220 | 5879 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5880 | }, |
5881 | ||
592a252b | 5882 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5883 | { |
592d1631 L |
5884 | { Bad_Opcode }, |
5885 | { Bad_Opcode }, | |
6c30d220 | 5886 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5887 | }, |
5888 | ||
592a252b | 5889 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5890 | { |
592d1631 L |
5891 | { Bad_Opcode }, |
5892 | { Bad_Opcode }, | |
6c30d220 | 5893 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5894 | }, |
5895 | ||
592a252b | 5896 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5897 | { |
592d1631 L |
5898 | { Bad_Opcode }, |
5899 | { Bad_Opcode }, | |
6c30d220 | 5900 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5901 | }, |
5902 | ||
592a252b | 5903 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5904 | { |
592d1631 L |
5905 | { Bad_Opcode }, |
5906 | { Bad_Opcode }, | |
6c30d220 | 5907 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5908 | }, |
5909 | ||
592a252b | 5910 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5911 | { |
592d1631 L |
5912 | { Bad_Opcode }, |
5913 | { Bad_Opcode }, | |
6c30d220 | 5914 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5915 | }, |
5916 | ||
592a252b | 5917 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5918 | { |
592d1631 L |
5919 | { Bad_Opcode }, |
5920 | { Bad_Opcode }, | |
6c30d220 | 5921 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5922 | }, |
5923 | ||
592a252b | 5924 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5925 | { |
592d1631 L |
5926 | { Bad_Opcode }, |
5927 | { Bad_Opcode }, | |
592a252b | 5928 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5929 | }, |
5930 | ||
592a252b | 5931 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5932 | { |
592d1631 L |
5933 | { Bad_Opcode }, |
5934 | { Bad_Opcode }, | |
6c30d220 | 5935 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5936 | }, |
5937 | ||
592a252b | 5938 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5939 | { |
592d1631 L |
5940 | { Bad_Opcode }, |
5941 | { Bad_Opcode }, | |
592a252b | 5942 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5943 | }, |
5944 | ||
592a252b | 5945 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5946 | { |
592d1631 L |
5947 | { Bad_Opcode }, |
5948 | { Bad_Opcode }, | |
592a252b | 5949 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5950 | }, |
5951 | ||
592a252b | 5952 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5953 | { |
592d1631 L |
5954 | { Bad_Opcode }, |
5955 | { Bad_Opcode }, | |
592a252b | 5956 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5957 | }, |
5958 | ||
592a252b | 5959 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5960 | { |
592d1631 L |
5961 | { Bad_Opcode }, |
5962 | { Bad_Opcode }, | |
592a252b | 5963 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5964 | }, |
5965 | ||
592a252b | 5966 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5967 | { |
592d1631 L |
5968 | { Bad_Opcode }, |
5969 | { Bad_Opcode }, | |
6c30d220 | 5970 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5971 | }, |
5972 | ||
592a252b | 5973 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5974 | { |
592d1631 L |
5975 | { Bad_Opcode }, |
5976 | { Bad_Opcode }, | |
6c30d220 | 5977 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5978 | }, |
5979 | ||
592a252b | 5980 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5981 | { |
592d1631 L |
5982 | { Bad_Opcode }, |
5983 | { Bad_Opcode }, | |
6c30d220 | 5984 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5985 | }, |
5986 | ||
592a252b | 5987 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5988 | { |
592d1631 L |
5989 | { Bad_Opcode }, |
5990 | { Bad_Opcode }, | |
6c30d220 | 5991 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5992 | }, |
5993 | ||
592a252b | 5994 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5995 | { |
592d1631 L |
5996 | { Bad_Opcode }, |
5997 | { Bad_Opcode }, | |
6c30d220 | 5998 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5999 | }, |
6000 | ||
592a252b | 6001 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 6002 | { |
592d1631 L |
6003 | { Bad_Opcode }, |
6004 | { Bad_Opcode }, | |
6c30d220 L |
6005 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
6006 | }, | |
6007 | ||
6008 | /* PREFIX_VEX_0F3836 */ | |
6009 | { | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
6012 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
6013 | }, |
6014 | ||
592a252b | 6015 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 6016 | { |
592d1631 L |
6017 | { Bad_Opcode }, |
6018 | { Bad_Opcode }, | |
6c30d220 | 6019 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
6020 | }, |
6021 | ||
592a252b | 6022 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 6023 | { |
592d1631 L |
6024 | { Bad_Opcode }, |
6025 | { Bad_Opcode }, | |
6c30d220 | 6026 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
6027 | }, |
6028 | ||
592a252b | 6029 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 6030 | { |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
6c30d220 | 6033 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
6034 | }, |
6035 | ||
592a252b | 6036 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 6037 | { |
592d1631 L |
6038 | { Bad_Opcode }, |
6039 | { Bad_Opcode }, | |
6c30d220 | 6040 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
6c30d220 | 6047 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
6c30d220 | 6054 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
6055 | }, |
6056 | ||
592a252b | 6057 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 6058 | { |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
6c30d220 | 6061 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
6062 | }, |
6063 | ||
592a252b | 6064 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 6065 | { |
592d1631 L |
6066 | { Bad_Opcode }, |
6067 | { Bad_Opcode }, | |
6c30d220 | 6068 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
6069 | }, |
6070 | ||
592a252b | 6071 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 6072 | { |
592d1631 L |
6073 | { Bad_Opcode }, |
6074 | { Bad_Opcode }, | |
6c30d220 | 6075 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
6076 | }, |
6077 | ||
592a252b | 6078 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 6079 | { |
592d1631 L |
6080 | { Bad_Opcode }, |
6081 | { Bad_Opcode }, | |
6c30d220 | 6082 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
6083 | }, |
6084 | ||
592a252b | 6085 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 6086 | { |
592d1631 L |
6087 | { Bad_Opcode }, |
6088 | { Bad_Opcode }, | |
592a252b | 6089 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
6090 | }, |
6091 | ||
6c30d220 L |
6092 | /* PREFIX_VEX_0F3845 */ |
6093 | { | |
6094 | { Bad_Opcode }, | |
6095 | { Bad_Opcode }, | |
bf890a93 | 6096 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6097 | }, |
6098 | ||
6099 | /* PREFIX_VEX_0F3846 */ | |
6100 | { | |
6101 | { Bad_Opcode }, | |
6102 | { Bad_Opcode }, | |
6103 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
6104 | }, | |
6105 | ||
6106 | /* PREFIX_VEX_0F3847 */ | |
6107 | { | |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
bf890a93 | 6110 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6111 | }, |
6112 | ||
6113 | /* PREFIX_VEX_0F3858 */ | |
6114 | { | |
6115 | { Bad_Opcode }, | |
6116 | { Bad_Opcode }, | |
6117 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
6118 | }, | |
6119 | ||
6120 | /* PREFIX_VEX_0F3859 */ | |
6121 | { | |
6122 | { Bad_Opcode }, | |
6123 | { Bad_Opcode }, | |
6124 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
6125 | }, | |
6126 | ||
6127 | /* PREFIX_VEX_0F385A */ | |
6128 | { | |
6129 | { Bad_Opcode }, | |
6130 | { Bad_Opcode }, | |
6131 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
6132 | }, | |
6133 | ||
6134 | /* PREFIX_VEX_0F3878 */ | |
6135 | { | |
6136 | { Bad_Opcode }, | |
6137 | { Bad_Opcode }, | |
6138 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
6139 | }, | |
6140 | ||
6141 | /* PREFIX_VEX_0F3879 */ | |
6142 | { | |
6143 | { Bad_Opcode }, | |
6144 | { Bad_Opcode }, | |
6145 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6146 | }, | |
6147 | ||
6148 | /* PREFIX_VEX_0F388C */ | |
6149 | { | |
6150 | { Bad_Opcode }, | |
6151 | { Bad_Opcode }, | |
f7002f42 | 6152 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6153 | }, |
6154 | ||
6155 | /* PREFIX_VEX_0F388E */ | |
6156 | { | |
6157 | { Bad_Opcode }, | |
6158 | { Bad_Opcode }, | |
f7002f42 | 6159 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6160 | }, |
6161 | ||
6162 | /* PREFIX_VEX_0F3890 */ | |
6163 | { | |
6164 | { Bad_Opcode }, | |
6165 | { Bad_Opcode }, | |
bf890a93 | 6166 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6167 | }, |
6168 | ||
6169 | /* PREFIX_VEX_0F3891 */ | |
6170 | { | |
6171 | { Bad_Opcode }, | |
6172 | { Bad_Opcode }, | |
bf890a93 | 6173 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6174 | }, |
6175 | ||
6176 | /* PREFIX_VEX_0F3892 */ | |
6177 | { | |
6178 | { Bad_Opcode }, | |
6179 | { Bad_Opcode }, | |
bf890a93 | 6180 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6181 | }, |
6182 | ||
6183 | /* PREFIX_VEX_0F3893 */ | |
6184 | { | |
6185 | { Bad_Opcode }, | |
6186 | { Bad_Opcode }, | |
bf890a93 | 6187 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6188 | }, |
6189 | ||
592a252b | 6190 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6191 | { |
592d1631 L |
6192 | { Bad_Opcode }, |
6193 | { Bad_Opcode }, | |
bf890a93 | 6194 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6195 | }, |
6196 | ||
592a252b | 6197 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6198 | { |
592d1631 L |
6199 | { Bad_Opcode }, |
6200 | { Bad_Opcode }, | |
bf890a93 | 6201 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6202 | }, |
6203 | ||
592a252b | 6204 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6205 | { |
592d1631 L |
6206 | { Bad_Opcode }, |
6207 | { Bad_Opcode }, | |
bf890a93 | 6208 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6209 | }, |
6210 | ||
592a252b | 6211 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6212 | { |
592d1631 L |
6213 | { Bad_Opcode }, |
6214 | { Bad_Opcode }, | |
bf890a93 | 6215 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6216 | }, |
6217 | ||
592a252b | 6218 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6219 | { |
592d1631 L |
6220 | { Bad_Opcode }, |
6221 | { Bad_Opcode }, | |
bf890a93 | 6222 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6223 | }, |
6224 | ||
592a252b | 6225 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6226 | { |
592d1631 L |
6227 | { Bad_Opcode }, |
6228 | { Bad_Opcode }, | |
bf890a93 | 6229 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6230 | }, |
6231 | ||
592a252b | 6232 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6233 | { |
592d1631 L |
6234 | { Bad_Opcode }, |
6235 | { Bad_Opcode }, | |
bf890a93 | 6236 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6237 | }, |
6238 | ||
592a252b | 6239 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6240 | { |
592d1631 L |
6241 | { Bad_Opcode }, |
6242 | { Bad_Opcode }, | |
bf890a93 | 6243 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6244 | }, |
6245 | ||
592a252b | 6246 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6247 | { |
592d1631 L |
6248 | { Bad_Opcode }, |
6249 | { Bad_Opcode }, | |
bf890a93 | 6250 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6251 | }, |
6252 | ||
592a252b | 6253 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6254 | { |
592d1631 L |
6255 | { Bad_Opcode }, |
6256 | { Bad_Opcode }, | |
bf890a93 | 6257 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6258 | }, |
6259 | ||
592a252b | 6260 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6261 | { |
592d1631 L |
6262 | { Bad_Opcode }, |
6263 | { Bad_Opcode }, | |
bf890a93 | 6264 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6265 | { Bad_Opcode }, |
c0f3af97 L |
6266 | }, |
6267 | ||
592a252b | 6268 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6269 | { |
592d1631 L |
6270 | { Bad_Opcode }, |
6271 | { Bad_Opcode }, | |
bf890a93 | 6272 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6273 | }, |
6274 | ||
592a252b | 6275 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6276 | { |
592d1631 L |
6277 | { Bad_Opcode }, |
6278 | { Bad_Opcode }, | |
bf890a93 | 6279 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6280 | }, |
6281 | ||
592a252b | 6282 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6283 | { |
592d1631 L |
6284 | { Bad_Opcode }, |
6285 | { Bad_Opcode }, | |
bf890a93 | 6286 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6287 | }, |
6288 | ||
592a252b | 6289 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6290 | { |
592d1631 L |
6291 | { Bad_Opcode }, |
6292 | { Bad_Opcode }, | |
bf890a93 | 6293 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6294 | }, |
6295 | ||
592a252b | 6296 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6297 | { |
592d1631 L |
6298 | { Bad_Opcode }, |
6299 | { Bad_Opcode }, | |
bf890a93 | 6300 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6301 | }, |
6302 | ||
592a252b | 6303 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6304 | { |
592d1631 L |
6305 | { Bad_Opcode }, |
6306 | { Bad_Opcode }, | |
bf890a93 | 6307 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6308 | }, |
6309 | ||
592a252b | 6310 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6311 | { |
592d1631 L |
6312 | { Bad_Opcode }, |
6313 | { Bad_Opcode }, | |
bf890a93 | 6314 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6315 | }, |
6316 | ||
592a252b | 6317 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6318 | { |
592d1631 L |
6319 | { Bad_Opcode }, |
6320 | { Bad_Opcode }, | |
bf890a93 | 6321 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6322 | }, |
6323 | ||
592a252b | 6324 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6325 | { |
592d1631 L |
6326 | { Bad_Opcode }, |
6327 | { Bad_Opcode }, | |
bf890a93 | 6328 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6329 | }, |
6330 | ||
592a252b | 6331 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6332 | { |
592d1631 L |
6333 | { Bad_Opcode }, |
6334 | { Bad_Opcode }, | |
bf890a93 | 6335 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6336 | }, |
6337 | ||
592a252b | 6338 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6339 | { |
592d1631 L |
6340 | { Bad_Opcode }, |
6341 | { Bad_Opcode }, | |
bf890a93 | 6342 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6343 | }, |
6344 | ||
592a252b | 6345 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6346 | { |
592d1631 L |
6347 | { Bad_Opcode }, |
6348 | { Bad_Opcode }, | |
bf890a93 | 6349 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6350 | }, |
6351 | ||
592a252b | 6352 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6353 | { |
592d1631 L |
6354 | { Bad_Opcode }, |
6355 | { Bad_Opcode }, | |
bf890a93 | 6356 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6357 | }, |
6358 | ||
592a252b | 6359 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6360 | { |
592d1631 L |
6361 | { Bad_Opcode }, |
6362 | { Bad_Opcode }, | |
bf890a93 | 6363 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6364 | }, |
6365 | ||
592a252b | 6366 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6367 | { |
592d1631 L |
6368 | { Bad_Opcode }, |
6369 | { Bad_Opcode }, | |
bf890a93 | 6370 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6371 | }, |
6372 | ||
592a252b | 6373 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6374 | { |
592d1631 L |
6375 | { Bad_Opcode }, |
6376 | { Bad_Opcode }, | |
bf890a93 | 6377 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6378 | }, |
6379 | ||
592a252b | 6380 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6381 | { |
592d1631 L |
6382 | { Bad_Opcode }, |
6383 | { Bad_Opcode }, | |
bf890a93 | 6384 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6385 | }, |
6386 | ||
592a252b | 6387 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6388 | { |
592d1631 L |
6389 | { Bad_Opcode }, |
6390 | { Bad_Opcode }, | |
bf890a93 | 6391 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6392 | }, |
6393 | ||
592a252b | 6394 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6395 | { |
592d1631 L |
6396 | { Bad_Opcode }, |
6397 | { Bad_Opcode }, | |
bf890a93 | 6398 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6399 | }, |
6400 | ||
48521003 IT |
6401 | /* PREFIX_VEX_0F38CF */ |
6402 | { | |
6403 | { Bad_Opcode }, | |
6404 | { Bad_Opcode }, | |
6405 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6406 | }, | |
6407 | ||
592a252b | 6408 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6409 | { |
592d1631 L |
6410 | { Bad_Opcode }, |
6411 | { Bad_Opcode }, | |
592a252b | 6412 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6413 | }, |
6414 | ||
592a252b | 6415 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6416 | { |
592d1631 L |
6417 | { Bad_Opcode }, |
6418 | { Bad_Opcode }, | |
8dcf1fad | 6419 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6420 | }, |
6421 | ||
592a252b | 6422 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6423 | { |
592d1631 L |
6424 | { Bad_Opcode }, |
6425 | { Bad_Opcode }, | |
8dcf1fad | 6426 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6427 | }, |
6428 | ||
592a252b | 6429 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6430 | { |
592d1631 L |
6431 | { Bad_Opcode }, |
6432 | { Bad_Opcode }, | |
8dcf1fad | 6433 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6434 | }, |
6435 | ||
592a252b | 6436 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6437 | { |
592d1631 L |
6438 | { Bad_Opcode }, |
6439 | { Bad_Opcode }, | |
8dcf1fad | 6440 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6441 | }, |
6442 | ||
f12dc422 L |
6443 | /* PREFIX_VEX_0F38F2 */ |
6444 | { | |
6445 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6446 | }, | |
6447 | ||
6448 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6449 | { | |
6450 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6451 | }, | |
6452 | ||
6453 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6454 | { | |
6455 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6456 | }, | |
6457 | ||
6458 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6459 | { | |
6460 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6461 | }, | |
6462 | ||
6c30d220 L |
6463 | /* PREFIX_VEX_0F38F5 */ |
6464 | { | |
6465 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6466 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6467 | { Bad_Opcode }, | |
6468 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6469 | }, | |
6470 | ||
6471 | /* PREFIX_VEX_0F38F6 */ | |
6472 | { | |
6473 | { Bad_Opcode }, | |
6474 | { Bad_Opcode }, | |
6475 | { Bad_Opcode }, | |
6476 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6477 | }, | |
6478 | ||
f12dc422 L |
6479 | /* PREFIX_VEX_0F38F7 */ |
6480 | { | |
6481 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6482 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6483 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6484 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6485 | }, | |
6486 | ||
6487 | /* PREFIX_VEX_0F3A00 */ | |
6488 | { | |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6492 | }, | |
6493 | ||
6494 | /* PREFIX_VEX_0F3A01 */ | |
6495 | { | |
6496 | { Bad_Opcode }, | |
6497 | { Bad_Opcode }, | |
6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6499 | }, | |
6500 | ||
6501 | /* PREFIX_VEX_0F3A02 */ | |
6502 | { | |
6503 | { Bad_Opcode }, | |
6504 | { Bad_Opcode }, | |
6505 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6506 | }, |
6507 | ||
592a252b | 6508 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6509 | { |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
592a252b | 6512 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6513 | }, |
6514 | ||
592a252b | 6515 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6516 | { |
592d1631 L |
6517 | { Bad_Opcode }, |
6518 | { Bad_Opcode }, | |
592a252b | 6519 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6520 | }, |
6521 | ||
592a252b | 6522 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6523 | { |
592d1631 L |
6524 | { Bad_Opcode }, |
6525 | { Bad_Opcode }, | |
592a252b | 6526 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6527 | }, |
6528 | ||
592a252b | 6529 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6530 | { |
592d1631 L |
6531 | { Bad_Opcode }, |
6532 | { Bad_Opcode }, | |
592a252b | 6533 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6534 | }, |
6535 | ||
592a252b | 6536 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6537 | { |
592d1631 L |
6538 | { Bad_Opcode }, |
6539 | { Bad_Opcode }, | |
592a252b | 6540 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6541 | }, |
6542 | ||
592a252b | 6543 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6544 | { |
592d1631 L |
6545 | { Bad_Opcode }, |
6546 | { Bad_Opcode }, | |
592a252b | 6547 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6548 | }, |
6549 | ||
592a252b | 6550 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6551 | { |
592d1631 L |
6552 | { Bad_Opcode }, |
6553 | { Bad_Opcode }, | |
592a252b | 6554 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6555 | }, |
6556 | ||
592a252b | 6557 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6558 | { |
592d1631 L |
6559 | { Bad_Opcode }, |
6560 | { Bad_Opcode }, | |
592a252b | 6561 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6562 | }, |
6563 | ||
592a252b | 6564 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6565 | { |
592d1631 L |
6566 | { Bad_Opcode }, |
6567 | { Bad_Opcode }, | |
592a252b | 6568 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6572 | { |
592d1631 L |
6573 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, | |
6c30d220 | 6575 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6576 | }, |
6577 | ||
592a252b | 6578 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6579 | { |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
6c30d220 | 6582 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6583 | }, |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6586 | { |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
592a252b | 6589 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6590 | }, |
6591 | ||
592a252b | 6592 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6593 | { |
592d1631 L |
6594 | { Bad_Opcode }, |
6595 | { Bad_Opcode }, | |
592a252b | 6596 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6597 | }, |
6598 | ||
592a252b | 6599 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6600 | { |
592d1631 L |
6601 | { Bad_Opcode }, |
6602 | { Bad_Opcode }, | |
592a252b | 6603 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6604 | }, |
6605 | ||
592a252b | 6606 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6607 | { |
592d1631 L |
6608 | { Bad_Opcode }, |
6609 | { Bad_Opcode }, | |
592a252b | 6610 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6611 | }, |
6612 | ||
592a252b | 6613 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6614 | { |
592d1631 L |
6615 | { Bad_Opcode }, |
6616 | { Bad_Opcode }, | |
592a252b | 6617 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6618 | }, |
6619 | ||
592a252b | 6620 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6621 | { |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
592a252b | 6624 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6625 | }, |
6626 | ||
592a252b | 6627 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6628 | { |
6629 | { Bad_Opcode }, | |
6630 | { Bad_Opcode }, | |
bf890a93 | 6631 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6632 | }, |
6633 | ||
592a252b | 6634 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6635 | { |
592d1631 L |
6636 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, | |
592a252b | 6638 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6639 | }, |
6640 | ||
592a252b | 6641 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6642 | { |
592d1631 L |
6643 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, | |
592a252b | 6645 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6646 | }, |
6647 | ||
592a252b | 6648 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6649 | { |
592d1631 L |
6650 | { Bad_Opcode }, |
6651 | { Bad_Opcode }, | |
592a252b | 6652 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6653 | }, |
6654 | ||
43234a1e L |
6655 | /* PREFIX_VEX_0F3A30 */ |
6656 | { | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
6659 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6660 | }, | |
6661 | ||
1ba585e8 IT |
6662 | /* PREFIX_VEX_0F3A31 */ |
6663 | { | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6667 | }, | |
6668 | ||
43234a1e L |
6669 | /* PREFIX_VEX_0F3A32 */ |
6670 | { | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6674 | }, | |
6675 | ||
1ba585e8 IT |
6676 | /* PREFIX_VEX_0F3A33 */ |
6677 | { | |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
6680 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6681 | }, | |
6682 | ||
6c30d220 L |
6683 | /* PREFIX_VEX_0F3A38 */ |
6684 | { | |
6685 | { Bad_Opcode }, | |
6686 | { Bad_Opcode }, | |
6687 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6688 | }, | |
6689 | ||
6690 | /* PREFIX_VEX_0F3A39 */ | |
6691 | { | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6695 | }, | |
6696 | ||
592a252b | 6697 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6698 | { |
592d1631 L |
6699 | { Bad_Opcode }, |
6700 | { Bad_Opcode }, | |
592a252b | 6701 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6702 | }, |
6703 | ||
592a252b | 6704 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6705 | { |
592d1631 L |
6706 | { Bad_Opcode }, |
6707 | { Bad_Opcode }, | |
592a252b | 6708 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6709 | }, |
6710 | ||
592a252b | 6711 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6712 | { |
592d1631 L |
6713 | { Bad_Opcode }, |
6714 | { Bad_Opcode }, | |
6c30d220 | 6715 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6716 | }, |
6717 | ||
592a252b | 6718 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6719 | { |
592d1631 L |
6720 | { Bad_Opcode }, |
6721 | { Bad_Opcode }, | |
ff1982d5 | 6722 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6723 | }, |
6724 | ||
6c30d220 L |
6725 | /* PREFIX_VEX_0F3A46 */ |
6726 | { | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6730 | }, | |
6731 | ||
592a252b | 6732 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6733 | { |
6734 | { Bad_Opcode }, | |
6735 | { Bad_Opcode }, | |
592a252b | 6736 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6737 | }, |
6738 | ||
592a252b | 6739 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6740 | { |
6741 | { Bad_Opcode }, | |
6742 | { Bad_Opcode }, | |
592a252b | 6743 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6744 | }, |
6745 | ||
592a252b | 6746 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6747 | { |
592d1631 L |
6748 | { Bad_Opcode }, |
6749 | { Bad_Opcode }, | |
592a252b | 6750 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6751 | }, |
6752 | ||
592a252b | 6753 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6754 | { |
592d1631 L |
6755 | { Bad_Opcode }, |
6756 | { Bad_Opcode }, | |
592a252b | 6757 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6758 | }, |
6759 | ||
592a252b | 6760 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6761 | { |
592d1631 L |
6762 | { Bad_Opcode }, |
6763 | { Bad_Opcode }, | |
6c30d220 | 6764 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6765 | }, |
6766 | ||
592a252b | 6767 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6768 | { |
592d1631 L |
6769 | { Bad_Opcode }, |
6770 | { Bad_Opcode }, | |
3a2430e0 | 6771 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6772 | }, |
6773 | ||
592a252b | 6774 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6775 | { |
592d1631 L |
6776 | { Bad_Opcode }, |
6777 | { Bad_Opcode }, | |
3a2430e0 | 6778 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6779 | }, |
6780 | ||
592a252b | 6781 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6782 | { |
592d1631 L |
6783 | { Bad_Opcode }, |
6784 | { Bad_Opcode }, | |
3a2430e0 | 6785 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6786 | }, |
6787 | ||
592a252b | 6788 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6789 | { |
592d1631 L |
6790 | { Bad_Opcode }, |
6791 | { Bad_Opcode }, | |
3a2430e0 | 6792 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6793 | }, |
6794 | ||
592a252b | 6795 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6796 | { |
592d1631 L |
6797 | { Bad_Opcode }, |
6798 | { Bad_Opcode }, | |
592a252b | 6799 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6800 | { Bad_Opcode }, |
c0f3af97 L |
6801 | }, |
6802 | ||
592a252b | 6803 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6804 | { |
592d1631 L |
6805 | { Bad_Opcode }, |
6806 | { Bad_Opcode }, | |
592a252b | 6807 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6808 | }, |
6809 | ||
592a252b | 6810 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6811 | { |
592d1631 L |
6812 | { Bad_Opcode }, |
6813 | { Bad_Opcode }, | |
592a252b | 6814 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6815 | }, |
6816 | ||
592a252b | 6817 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6818 | { |
592d1631 L |
6819 | { Bad_Opcode }, |
6820 | { Bad_Opcode }, | |
592a252b | 6821 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6822 | }, |
a5ff0eb2 | 6823 | |
592a252b | 6824 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6825 | { |
592d1631 L |
6826 | { Bad_Opcode }, |
6827 | { Bad_Opcode }, | |
3a2430e0 | 6828 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6829 | }, |
6830 | ||
592a252b | 6831 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6832 | { |
592d1631 L |
6833 | { Bad_Opcode }, |
6834 | { Bad_Opcode }, | |
3a2430e0 | 6835 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6836 | }, |
6837 | ||
592a252b | 6838 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6839 | { |
592d1631 L |
6840 | { Bad_Opcode }, |
6841 | { Bad_Opcode }, | |
592a252b | 6842 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6843 | }, |
6844 | ||
592a252b | 6845 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6846 | { |
592d1631 L |
6847 | { Bad_Opcode }, |
6848 | { Bad_Opcode }, | |
592a252b | 6849 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6850 | }, |
6851 | ||
592a252b | 6852 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6853 | { |
592d1631 L |
6854 | { Bad_Opcode }, |
6855 | { Bad_Opcode }, | |
3a2430e0 | 6856 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6857 | }, |
6858 | ||
592a252b | 6859 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6860 | { |
592d1631 L |
6861 | { Bad_Opcode }, |
6862 | { Bad_Opcode }, | |
3a2430e0 | 6863 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6864 | }, |
6865 | ||
592a252b | 6866 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6867 | { |
592d1631 L |
6868 | { Bad_Opcode }, |
6869 | { Bad_Opcode }, | |
592a252b | 6870 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6871 | }, |
6872 | ||
592a252b | 6873 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6874 | { |
592d1631 L |
6875 | { Bad_Opcode }, |
6876 | { Bad_Opcode }, | |
592a252b | 6877 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6878 | }, |
6879 | ||
592a252b | 6880 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6881 | { |
592d1631 L |
6882 | { Bad_Opcode }, |
6883 | { Bad_Opcode }, | |
3a2430e0 | 6884 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6885 | }, |
6886 | ||
592a252b | 6887 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6888 | { |
592d1631 L |
6889 | { Bad_Opcode }, |
6890 | { Bad_Opcode }, | |
3a2430e0 | 6891 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6892 | }, |
6893 | ||
592a252b | 6894 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6895 | { |
592d1631 L |
6896 | { Bad_Opcode }, |
6897 | { Bad_Opcode }, | |
592a252b | 6898 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6899 | }, |
6900 | ||
592a252b | 6901 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6902 | { |
592d1631 L |
6903 | { Bad_Opcode }, |
6904 | { Bad_Opcode }, | |
592a252b | 6905 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6906 | }, |
6907 | ||
592a252b | 6908 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6909 | { |
592d1631 L |
6910 | { Bad_Opcode }, |
6911 | { Bad_Opcode }, | |
3a2430e0 | 6912 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6913 | { Bad_Opcode }, |
922d8de8 DR |
6914 | }, |
6915 | ||
592a252b | 6916 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6917 | { |
592d1631 L |
6918 | { Bad_Opcode }, |
6919 | { Bad_Opcode }, | |
3a2430e0 | 6920 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6921 | }, |
6922 | ||
592a252b | 6923 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6924 | { |
592d1631 L |
6925 | { Bad_Opcode }, |
6926 | { Bad_Opcode }, | |
592a252b | 6927 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6928 | }, |
6929 | ||
592a252b | 6930 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6931 | { |
592d1631 L |
6932 | { Bad_Opcode }, |
6933 | { Bad_Opcode }, | |
592a252b | 6934 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6935 | }, |
6936 | ||
48521003 IT |
6937 | /* PREFIX_VEX_0F3ACE */ |
6938 | { | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6942 | }, | |
6943 | ||
6944 | /* PREFIX_VEX_0F3ACF */ | |
6945 | { | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6949 | }, | |
6950 | ||
592a252b | 6951 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6952 | { |
592d1631 L |
6953 | { Bad_Opcode }, |
6954 | { Bad_Opcode }, | |
592a252b | 6955 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6956 | }, |
6c30d220 L |
6957 | |
6958 | /* PREFIX_VEX_0F3AF0 */ | |
6959 | { | |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6964 | }, | |
43234a1e L |
6965 | |
6966 | #define NEED_PREFIX_TABLE | |
6967 | #include "i386-dis-evex.h" | |
6968 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6969 | }; |
6970 | ||
6971 | static const struct dis386 x86_64_table[][2] = { | |
6972 | /* X86_64_06 */ | |
6973 | { | |
bf890a93 | 6974 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6975 | }, |
6976 | ||
6977 | /* X86_64_07 */ | |
6978 | { | |
bf890a93 | 6979 | { "popP", { es }, 0 }, |
c0f3af97 L |
6980 | }, |
6981 | ||
6982 | /* X86_64_0D */ | |
6983 | { | |
bf890a93 | 6984 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6985 | }, |
6986 | ||
6987 | /* X86_64_16 */ | |
6988 | { | |
bf890a93 | 6989 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6990 | }, |
6991 | ||
6992 | /* X86_64_17 */ | |
6993 | { | |
bf890a93 | 6994 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6995 | }, |
6996 | ||
6997 | /* X86_64_1E */ | |
6998 | { | |
bf890a93 | 6999 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
7000 | }, |
7001 | ||
7002 | /* X86_64_1F */ | |
7003 | { | |
bf890a93 | 7004 | { "popP", { ds }, 0 }, |
c0f3af97 L |
7005 | }, |
7006 | ||
7007 | /* X86_64_27 */ | |
7008 | { | |
bf890a93 | 7009 | { "daa", { XX }, 0 }, |
c0f3af97 L |
7010 | }, |
7011 | ||
7012 | /* X86_64_2F */ | |
7013 | { | |
bf890a93 | 7014 | { "das", { XX }, 0 }, |
c0f3af97 L |
7015 | }, |
7016 | ||
7017 | /* X86_64_37 */ | |
7018 | { | |
bf890a93 | 7019 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
7020 | }, |
7021 | ||
7022 | /* X86_64_3F */ | |
7023 | { | |
bf890a93 | 7024 | { "aas", { XX }, 0 }, |
c0f3af97 L |
7025 | }, |
7026 | ||
7027 | /* X86_64_60 */ | |
7028 | { | |
bf890a93 | 7029 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
7030 | }, |
7031 | ||
7032 | /* X86_64_61 */ | |
7033 | { | |
bf890a93 | 7034 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
7035 | }, |
7036 | ||
7037 | /* X86_64_62 */ | |
7038 | { | |
7039 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 7040 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
7041 | }, |
7042 | ||
7043 | /* X86_64_63 */ | |
7044 | { | |
bf890a93 IT |
7045 | { "arpl", { Ew, Gw }, 0 }, |
7046 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
7047 | }, |
7048 | ||
7049 | /* X86_64_6D */ | |
7050 | { | |
bf890a93 IT |
7051 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
7052 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
7053 | }, |
7054 | ||
7055 | /* X86_64_6F */ | |
7056 | { | |
bf890a93 IT |
7057 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
7058 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
7059 | }, |
7060 | ||
d039fef3 | 7061 | /* X86_64_82 */ |
8b89fe14 | 7062 | { |
de194d85 | 7063 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 7064 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
7065 | }, |
7066 | ||
c0f3af97 L |
7067 | /* X86_64_9A */ |
7068 | { | |
bf890a93 | 7069 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
7070 | }, |
7071 | ||
7072 | /* X86_64_C4 */ | |
7073 | { | |
7074 | { MOD_TABLE (MOD_C4_32BIT) }, | |
7075 | { VEX_C4_TABLE (VEX_0F) }, | |
7076 | }, | |
7077 | ||
7078 | /* X86_64_C5 */ | |
7079 | { | |
7080 | { MOD_TABLE (MOD_C5_32BIT) }, | |
7081 | { VEX_C5_TABLE (VEX_0F) }, | |
7082 | }, | |
7083 | ||
7084 | /* X86_64_CE */ | |
7085 | { | |
bf890a93 | 7086 | { "into", { XX }, 0 }, |
c0f3af97 L |
7087 | }, |
7088 | ||
7089 | /* X86_64_D4 */ | |
7090 | { | |
bf890a93 | 7091 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
7092 | }, |
7093 | ||
7094 | /* X86_64_D5 */ | |
7095 | { | |
bf890a93 | 7096 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
7097 | }, |
7098 | ||
a72d2af2 L |
7099 | /* X86_64_E8 */ |
7100 | { | |
7101 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 7102 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
7103 | }, |
7104 | ||
7105 | /* X86_64_E9 */ | |
7106 | { | |
7107 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 7108 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
7109 | }, |
7110 | ||
c0f3af97 L |
7111 | /* X86_64_EA */ |
7112 | { | |
bf890a93 | 7113 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
7114 | }, |
7115 | ||
7116 | /* X86_64_0F01_REG_0 */ | |
7117 | { | |
bf890a93 IT |
7118 | { "sgdt{Q|IQ}", { M }, 0 }, |
7119 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
7120 | }, |
7121 | ||
7122 | /* X86_64_0F01_REG_1 */ | |
7123 | { | |
bf890a93 IT |
7124 | { "sidt{Q|IQ}", { M }, 0 }, |
7125 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
7126 | }, |
7127 | ||
7128 | /* X86_64_0F01_REG_2 */ | |
7129 | { | |
bf890a93 IT |
7130 | { "lgdt{Q|Q}", { M }, 0 }, |
7131 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
7132 | }, |
7133 | ||
7134 | /* X86_64_0F01_REG_3 */ | |
7135 | { | |
bf890a93 IT |
7136 | { "lidt{Q|Q}", { M }, 0 }, |
7137 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
7138 | }, |
7139 | }; | |
7140 | ||
7141 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7142 | |
7143 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7144 | { |
7145 | /* 00 */ | |
507bd325 L |
7146 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7147 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7148 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7149 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7150 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7151 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7152 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7153 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7154 | /* 08 */ |
507bd325 L |
7155 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7156 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7157 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7158 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
f88c9eb0 SP |
7163 | /* 10 */ |
7164 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7165 | { Bad_Opcode }, |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
f88c9eb0 SP |
7168 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7169 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7170 | { Bad_Opcode }, |
f88c9eb0 SP |
7171 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7172 | /* 18 */ | |
592d1631 L |
7173 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
507bd325 L |
7177 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7178 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7179 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7180 | { Bad_Opcode }, |
f88c9eb0 SP |
7181 | /* 20 */ |
7182 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7183 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7184 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7185 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7186 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7187 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7188 | { Bad_Opcode }, |
7189 | { Bad_Opcode }, | |
f88c9eb0 SP |
7190 | /* 28 */ |
7191 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7192 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7193 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7194 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7195 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
f88c9eb0 SP |
7199 | /* 30 */ |
7200 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7201 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7202 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7203 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7204 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7206 | { Bad_Opcode }, |
f88c9eb0 SP |
7207 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7208 | /* 38 */ | |
7209 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7210 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7211 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7212 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7213 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7214 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7215 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7216 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7217 | /* 40 */ | |
7218 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7219 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7220 | { Bad_Opcode }, |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
f88c9eb0 | 7226 | /* 48 */ |
592d1631 L |
7227 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
f88c9eb0 | 7235 | /* 50 */ |
592d1631 L |
7236 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
f88c9eb0 | 7244 | /* 58 */ |
592d1631 L |
7245 | { Bad_Opcode }, |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
f88c9eb0 | 7253 | /* 60 */ |
592d1631 L |
7254 | { Bad_Opcode }, |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
f88c9eb0 | 7262 | /* 68 */ |
592d1631 L |
7263 | { Bad_Opcode }, |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
f88c9eb0 | 7271 | /* 70 */ |
592d1631 L |
7272 | { Bad_Opcode }, |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
f88c9eb0 | 7280 | /* 78 */ |
592d1631 L |
7281 | { Bad_Opcode }, |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
f88c9eb0 SP |
7289 | /* 80 */ |
7290 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7291 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7292 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
f88c9eb0 | 7298 | /* 88 */ |
592d1631 L |
7299 | { Bad_Opcode }, |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
f88c9eb0 | 7307 | /* 90 */ |
592d1631 L |
7308 | { Bad_Opcode }, |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
f88c9eb0 | 7316 | /* 98 */ |
592d1631 L |
7317 | { Bad_Opcode }, |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
f88c9eb0 | 7325 | /* a0 */ |
592d1631 L |
7326 | { Bad_Opcode }, |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
f88c9eb0 | 7334 | /* a8 */ |
592d1631 L |
7335 | { Bad_Opcode }, |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
f88c9eb0 | 7343 | /* b0 */ |
592d1631 L |
7344 | { Bad_Opcode }, |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
f88c9eb0 | 7352 | /* b8 */ |
592d1631 L |
7353 | { Bad_Opcode }, |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
f88c9eb0 | 7361 | /* c0 */ |
592d1631 L |
7362 | { Bad_Opcode }, |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
f88c9eb0 | 7370 | /* c8 */ |
a0046408 L |
7371 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7372 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7373 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7374 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7375 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7376 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7377 | { Bad_Opcode }, |
48521003 | 7378 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7379 | /* d0 */ |
592d1631 L |
7380 | { Bad_Opcode }, |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
f88c9eb0 | 7388 | /* d8 */ |
592d1631 L |
7389 | { Bad_Opcode }, |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
f88c9eb0 SP |
7392 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7393 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7394 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7395 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7396 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7397 | /* e0 */ | |
592d1631 L |
7398 | { Bad_Opcode }, |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
f88c9eb0 | 7406 | /* e8 */ |
592d1631 L |
7407 | { Bad_Opcode }, |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
f88c9eb0 SP |
7415 | /* f0 */ |
7416 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7417 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7418 | { Bad_Opcode }, |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
603555e5 | 7421 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7422 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7423 | { Bad_Opcode }, |
f88c9eb0 | 7424 | /* f8 */ |
592d1631 L |
7425 | { Bad_Opcode }, |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
f88c9eb0 SP |
7433 | }, |
7434 | /* THREE_BYTE_0F3A */ | |
7435 | { | |
7436 | /* 00 */ | |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
f88c9eb0 SP |
7445 | /* 08 */ |
7446 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7447 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7448 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7449 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7450 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7451 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7452 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7453 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7454 | /* 10 */ |
592d1631 L |
7455 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
f88c9eb0 SP |
7459 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7460 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7461 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7462 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7463 | /* 18 */ | |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
f88c9eb0 SP |
7472 | /* 20 */ |
7473 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7474 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7475 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7476 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
f88c9eb0 | 7481 | /* 28 */ |
592d1631 L |
7482 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
f88c9eb0 | 7490 | /* 30 */ |
592d1631 L |
7491 | { Bad_Opcode }, |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
f88c9eb0 | 7499 | /* 38 */ |
592d1631 L |
7500 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
f88c9eb0 SP |
7508 | /* 40 */ |
7509 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7510 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7511 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7512 | { Bad_Opcode }, |
f88c9eb0 | 7513 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7514 | { Bad_Opcode }, |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
f88c9eb0 | 7517 | /* 48 */ |
592d1631 L |
7518 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
f88c9eb0 | 7526 | /* 50 */ |
592d1631 L |
7527 | { Bad_Opcode }, |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
f88c9eb0 | 7535 | /* 58 */ |
592d1631 L |
7536 | { Bad_Opcode }, |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
f88c9eb0 SP |
7544 | /* 60 */ |
7545 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7546 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7547 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7548 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7549 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
f88c9eb0 | 7553 | /* 68 */ |
592d1631 L |
7554 | { Bad_Opcode }, |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
f88c9eb0 | 7562 | /* 70 */ |
592d1631 L |
7563 | { Bad_Opcode }, |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
f88c9eb0 | 7571 | /* 78 */ |
592d1631 L |
7572 | { Bad_Opcode }, |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
f88c9eb0 | 7580 | /* 80 */ |
592d1631 L |
7581 | { Bad_Opcode }, |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
f88c9eb0 | 7589 | /* 88 */ |
592d1631 L |
7590 | { Bad_Opcode }, |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
f88c9eb0 | 7598 | /* 90 */ |
592d1631 L |
7599 | { Bad_Opcode }, |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
f88c9eb0 | 7607 | /* 98 */ |
592d1631 L |
7608 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
f88c9eb0 | 7616 | /* a0 */ |
592d1631 L |
7617 | { Bad_Opcode }, |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
f88c9eb0 | 7625 | /* a8 */ |
592d1631 L |
7626 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
f88c9eb0 | 7634 | /* b0 */ |
592d1631 L |
7635 | { Bad_Opcode }, |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
f88c9eb0 | 7643 | /* b8 */ |
592d1631 L |
7644 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
f88c9eb0 | 7652 | /* c0 */ |
592d1631 L |
7653 | { Bad_Opcode }, |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
f88c9eb0 | 7661 | /* c8 */ |
592d1631 L |
7662 | { Bad_Opcode }, |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
a0046408 | 7666 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7667 | { Bad_Opcode }, |
48521003 IT |
7668 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7669 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7670 | /* d0 */ |
592d1631 L |
7671 | { Bad_Opcode }, |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
f88c9eb0 | 7679 | /* d8 */ |
592d1631 L |
7680 | { Bad_Opcode }, |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
f88c9eb0 SP |
7687 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7688 | /* e0 */ | |
592d1631 L |
7689 | { Bad_Opcode }, |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
592d1631 L |
7694 | { Bad_Opcode }, |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
85f10a01 | 7697 | /* e8 */ |
592d1631 L |
7698 | { Bad_Opcode }, |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
85f10a01 | 7706 | /* f0 */ |
592d1631 L |
7707 | { Bad_Opcode }, |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
85f10a01 | 7715 | /* f8 */ |
592d1631 L |
7716 | { Bad_Opcode }, |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
85f10a01 | 7724 | }, |
f88c9eb0 SP |
7725 | }; |
7726 | ||
7727 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7728 | /* XOP_08 */ |
85f10a01 MM |
7729 | { |
7730 | /* 00 */ | |
592d1631 L |
7731 | { Bad_Opcode }, |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
85f10a01 | 7739 | /* 08 */ |
592d1631 L |
7740 | { Bad_Opcode }, |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
85f10a01 | 7748 | /* 10 */ |
3929df09 | 7749 | { Bad_Opcode }, |
592d1631 L |
7750 | { Bad_Opcode }, |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
85f10a01 | 7757 | /* 18 */ |
592d1631 L |
7758 | { Bad_Opcode }, |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
85f10a01 | 7766 | /* 20 */ |
592d1631 L |
7767 | { Bad_Opcode }, |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
85f10a01 | 7775 | /* 28 */ |
592d1631 L |
7776 | { Bad_Opcode }, |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
c0f3af97 | 7784 | /* 30 */ |
592d1631 L |
7785 | { Bad_Opcode }, |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
c0f3af97 | 7793 | /* 38 */ |
592d1631 L |
7794 | { Bad_Opcode }, |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
c0f3af97 | 7802 | /* 40 */ |
592d1631 L |
7803 | { Bad_Opcode }, |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
85f10a01 | 7811 | /* 48 */ |
592d1631 L |
7812 | { Bad_Opcode }, |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
c0f3af97 | 7820 | /* 50 */ |
592d1631 L |
7821 | { Bad_Opcode }, |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
85f10a01 | 7829 | /* 58 */ |
592d1631 L |
7830 | { Bad_Opcode }, |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
c1e679ec | 7838 | /* 60 */ |
592d1631 L |
7839 | { Bad_Opcode }, |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
c0f3af97 | 7847 | /* 68 */ |
592d1631 L |
7848 | { Bad_Opcode }, |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
85f10a01 | 7856 | /* 70 */ |
592d1631 L |
7857 | { Bad_Opcode }, |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
85f10a01 | 7865 | /* 78 */ |
592d1631 L |
7866 | { Bad_Opcode }, |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
85f10a01 | 7874 | /* 80 */ |
592d1631 L |
7875 | { Bad_Opcode }, |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
3a2430e0 JB |
7880 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7881 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7882 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7883 | /* 88 */ |
592d1631 L |
7884 | { Bad_Opcode }, |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
3a2430e0 JB |
7890 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7891 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7892 | /* 90 */ |
592d1631 L |
7893 | { Bad_Opcode }, |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
3a2430e0 JB |
7898 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7899 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7900 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7901 | /* 98 */ |
592d1631 L |
7902 | { Bad_Opcode }, |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
3a2430e0 JB |
7908 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7909 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7910 | /* a0 */ |
592d1631 L |
7911 | { Bad_Opcode }, |
7912 | { Bad_Opcode }, | |
3a2430e0 JB |
7913 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7914 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7915 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, | |
3a2430e0 | 7917 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7918 | { Bad_Opcode }, |
5dd85c99 | 7919 | /* a8 */ |
592d1631 L |
7920 | { Bad_Opcode }, |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
5dd85c99 | 7928 | /* b0 */ |
592d1631 L |
7929 | { Bad_Opcode }, |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
3a2430e0 | 7935 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7936 | { Bad_Opcode }, |
5dd85c99 | 7937 | /* b8 */ |
592d1631 L |
7938 | { Bad_Opcode }, |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
5dd85c99 | 7946 | /* c0 */ |
bf890a93 IT |
7947 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7948 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7949 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7950 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7951 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
5dd85c99 | 7955 | /* c8 */ |
592d1631 L |
7956 | { Bad_Opcode }, |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
ff688e1f L |
7960 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7961 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7962 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7963 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7964 | /* d0 */ |
592d1631 L |
7965 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
5dd85c99 | 7973 | /* d8 */ |
592d1631 L |
7974 | { Bad_Opcode }, |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
5dd85c99 | 7982 | /* e0 */ |
592d1631 L |
7983 | { Bad_Opcode }, |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
5dd85c99 | 7991 | /* e8 */ |
592d1631 L |
7992 | { Bad_Opcode }, |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
ff688e1f L |
7996 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7997 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7998 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7999 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8000 | /* f0 */ |
592d1631 L |
8001 | { Bad_Opcode }, |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
5dd85c99 | 8009 | /* f8 */ |
592d1631 L |
8010 | { Bad_Opcode }, |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
5dd85c99 SP |
8018 | }, |
8019 | /* XOP_09 */ | |
8020 | { | |
8021 | /* 00 */ | |
592d1631 | 8022 | { Bad_Opcode }, |
2a2a0f38 QN |
8023 | { REG_TABLE (REG_XOP_TBM_01) }, |
8024 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8025 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
5dd85c99 | 8030 | /* 08 */ |
592d1631 L |
8031 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
5dd85c99 | 8039 | /* 10 */ |
592d1631 L |
8040 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, | |
5dd85c99 | 8042 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8043 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
5dd85c99 | 8048 | /* 18 */ |
592d1631 L |
8049 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
5dd85c99 | 8057 | /* 20 */ |
592d1631 L |
8058 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
5dd85c99 | 8066 | /* 28 */ |
592d1631 L |
8067 | { Bad_Opcode }, |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
5dd85c99 | 8075 | /* 30 */ |
592d1631 L |
8076 | { Bad_Opcode }, |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
5dd85c99 | 8084 | /* 38 */ |
592d1631 L |
8085 | { Bad_Opcode }, |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
5dd85c99 | 8093 | /* 40 */ |
592d1631 L |
8094 | { Bad_Opcode }, |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
5dd85c99 | 8102 | /* 48 */ |
592d1631 L |
8103 | { Bad_Opcode }, |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
5dd85c99 | 8111 | /* 50 */ |
592d1631 L |
8112 | { Bad_Opcode }, |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
5dd85c99 | 8120 | /* 58 */ |
592d1631 L |
8121 | { Bad_Opcode }, |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
5dd85c99 | 8129 | /* 60 */ |
592d1631 L |
8130 | { Bad_Opcode }, |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
5dd85c99 | 8138 | /* 68 */ |
592d1631 L |
8139 | { Bad_Opcode }, |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
5dd85c99 | 8147 | /* 70 */ |
592d1631 L |
8148 | { Bad_Opcode }, |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
5dd85c99 | 8156 | /* 78 */ |
592d1631 L |
8157 | { Bad_Opcode }, |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
5dd85c99 | 8165 | /* 80 */ |
592a252b L |
8166 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8167 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8168 | { "vfrczss", { XM, EXd }, 0 }, |
8169 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8170 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
5dd85c99 | 8174 | /* 88 */ |
592d1631 L |
8175 | { Bad_Opcode }, |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
5dd85c99 | 8183 | /* 90 */ |
bf890a93 IT |
8184 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8185 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8186 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8187 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8188 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8189 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8190 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8191 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8192 | /* 98 */ |
bf890a93 IT |
8193 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8194 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8195 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8196 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8197 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
5dd85c99 | 8201 | /* a0 */ |
592d1631 L |
8202 | { Bad_Opcode }, |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
5dd85c99 | 8210 | /* a8 */ |
592d1631 L |
8211 | { Bad_Opcode }, |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
5dd85c99 | 8219 | /* b0 */ |
592d1631 L |
8220 | { Bad_Opcode }, |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
5dd85c99 | 8228 | /* b8 */ |
592d1631 L |
8229 | { Bad_Opcode }, |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
5dd85c99 | 8237 | /* c0 */ |
592d1631 | 8238 | { Bad_Opcode }, |
bf890a93 IT |
8239 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8240 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8241 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8242 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, | |
bf890a93 IT |
8244 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8245 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8246 | /* c8 */ |
592d1631 L |
8247 | { Bad_Opcode }, |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
bf890a93 | 8250 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8251 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
5dd85c99 | 8255 | /* d0 */ |
592d1631 | 8256 | { Bad_Opcode }, |
bf890a93 IT |
8257 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8258 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8259 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8260 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, | |
bf890a93 IT |
8262 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8263 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8264 | /* d8 */ |
592d1631 L |
8265 | { Bad_Opcode }, |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
bf890a93 | 8268 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8269 | { Bad_Opcode }, |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
5dd85c99 | 8273 | /* e0 */ |
592d1631 | 8274 | { Bad_Opcode }, |
bf890a93 IT |
8275 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8276 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8277 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8278 | { Bad_Opcode }, |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
4e7d34a6 | 8282 | /* e8 */ |
592d1631 L |
8283 | { Bad_Opcode }, |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
4e7d34a6 | 8291 | /* f0 */ |
592d1631 L |
8292 | { Bad_Opcode }, |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
4e7d34a6 | 8300 | /* f8 */ |
592d1631 L |
8301 | { Bad_Opcode }, |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
4e7d34a6 | 8309 | }, |
f88c9eb0 | 8310 | /* XOP_0A */ |
4e7d34a6 L |
8311 | { |
8312 | /* 00 */ | |
592d1631 L |
8313 | { Bad_Opcode }, |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
4e7d34a6 | 8321 | /* 08 */ |
592d1631 L |
8322 | { Bad_Opcode }, |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
4e7d34a6 | 8330 | /* 10 */ |
bf890a93 | 8331 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8332 | { Bad_Opcode }, |
f88c9eb0 | 8333 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8334 | { Bad_Opcode }, |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
4e7d34a6 | 8339 | /* 18 */ |
592d1631 L |
8340 | { Bad_Opcode }, |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
4e7d34a6 | 8348 | /* 20 */ |
592d1631 L |
8349 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
4e7d34a6 | 8357 | /* 28 */ |
592d1631 L |
8358 | { Bad_Opcode }, |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
4e7d34a6 | 8366 | /* 30 */ |
592d1631 L |
8367 | { Bad_Opcode }, |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
c0f3af97 | 8375 | /* 38 */ |
592d1631 L |
8376 | { Bad_Opcode }, |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
c0f3af97 | 8384 | /* 40 */ |
592d1631 L |
8385 | { Bad_Opcode }, |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
c1e679ec | 8393 | /* 48 */ |
592d1631 L |
8394 | { Bad_Opcode }, |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
c1e679ec | 8402 | /* 50 */ |
592d1631 L |
8403 | { Bad_Opcode }, |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
4e7d34a6 | 8411 | /* 58 */ |
592d1631 L |
8412 | { Bad_Opcode }, |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
4e7d34a6 | 8420 | /* 60 */ |
592d1631 L |
8421 | { Bad_Opcode }, |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
4e7d34a6 | 8429 | /* 68 */ |
592d1631 L |
8430 | { Bad_Opcode }, |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
4e7d34a6 | 8438 | /* 70 */ |
592d1631 L |
8439 | { Bad_Opcode }, |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
4e7d34a6 | 8447 | /* 78 */ |
592d1631 L |
8448 | { Bad_Opcode }, |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
4e7d34a6 | 8456 | /* 80 */ |
592d1631 L |
8457 | { Bad_Opcode }, |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
4e7d34a6 | 8465 | /* 88 */ |
592d1631 L |
8466 | { Bad_Opcode }, |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
4e7d34a6 | 8474 | /* 90 */ |
592d1631 L |
8475 | { Bad_Opcode }, |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
4e7d34a6 | 8483 | /* 98 */ |
592d1631 L |
8484 | { Bad_Opcode }, |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
4e7d34a6 | 8492 | /* a0 */ |
592d1631 L |
8493 | { Bad_Opcode }, |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
4e7d34a6 | 8501 | /* a8 */ |
592d1631 L |
8502 | { Bad_Opcode }, |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
d5d7db8e | 8510 | /* b0 */ |
592d1631 L |
8511 | { Bad_Opcode }, |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
85f10a01 | 8519 | /* b8 */ |
592d1631 L |
8520 | { Bad_Opcode }, |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
85f10a01 | 8528 | /* c0 */ |
592d1631 L |
8529 | { Bad_Opcode }, |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
85f10a01 | 8537 | /* c8 */ |
592d1631 L |
8538 | { Bad_Opcode }, |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
85f10a01 | 8546 | /* d0 */ |
592d1631 L |
8547 | { Bad_Opcode }, |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
85f10a01 | 8555 | /* d8 */ |
592d1631 L |
8556 | { Bad_Opcode }, |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
85f10a01 | 8564 | /* e0 */ |
592d1631 L |
8565 | { Bad_Opcode }, |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
85f10a01 | 8573 | /* e8 */ |
592d1631 L |
8574 | { Bad_Opcode }, |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
8578 | { Bad_Opcode }, | |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
85f10a01 | 8582 | /* f0 */ |
592d1631 L |
8583 | { Bad_Opcode }, |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
85f10a01 | 8591 | /* f8 */ |
592d1631 L |
8592 | { Bad_Opcode }, |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
85f10a01 | 8600 | }, |
c0f3af97 L |
8601 | }; |
8602 | ||
8603 | static const struct dis386 vex_table[][256] = { | |
8604 | /* VEX_0F */ | |
85f10a01 MM |
8605 | { |
8606 | /* 00 */ | |
592d1631 L |
8607 | { Bad_Opcode }, |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
85f10a01 | 8615 | /* 08 */ |
592d1631 L |
8616 | { Bad_Opcode }, |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
c0f3af97 | 8624 | /* 10 */ |
592a252b L |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8628 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8629 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8630 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8631 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8632 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8633 | /* 18 */ |
592d1631 L |
8634 | { Bad_Opcode }, |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
c0f3af97 | 8642 | /* 20 */ |
592d1631 L |
8643 | { Bad_Opcode }, |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
c0f3af97 | 8651 | /* 28 */ |
592a252b L |
8652 | { VEX_W_TABLE (VEX_W_0F28) }, |
8653 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8655 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8659 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8660 | /* 30 */ |
592d1631 L |
8661 | { Bad_Opcode }, |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
4e7d34a6 | 8669 | /* 38 */ |
592d1631 L |
8670 | { Bad_Opcode }, |
8671 | { Bad_Opcode }, | |
8672 | { Bad_Opcode }, | |
8673 | { Bad_Opcode }, | |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
d5d7db8e | 8678 | /* 40 */ |
592d1631 | 8679 | { Bad_Opcode }, |
43234a1e L |
8680 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8681 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8682 | { Bad_Opcode }, |
43234a1e L |
8683 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8684 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8687 | /* 48 */ |
592d1631 L |
8688 | { Bad_Opcode }, |
8689 | { Bad_Opcode }, | |
1ba585e8 | 8690 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8691 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8692 | { Bad_Opcode }, |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
d5d7db8e | 8696 | /* 50 */ |
592a252b L |
8697 | { MOD_TABLE (MOD_VEX_0F50) }, |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8701 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8702 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8703 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8704 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8705 | /* 58 */ |
592a252b L |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8714 | /* 60 */ |
592a252b L |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8716 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8719 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8721 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8722 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8723 | /* 68 */ |
592a252b L |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8732 | /* 70 */ |
592a252b L |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8734 | { REG_TABLE (REG_VEX_0F71) }, | |
8735 | { REG_TABLE (REG_VEX_0F72) }, | |
8736 | { REG_TABLE (REG_VEX_0F73) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8741 | /* 78 */ |
592d1631 L |
8742 | { Bad_Opcode }, |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
592a252b L |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8750 | /* 80 */ |
592d1631 L |
8751 | { Bad_Opcode }, |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
8756 | { Bad_Opcode }, | |
8757 | { Bad_Opcode }, | |
8758 | { Bad_Opcode }, | |
c0f3af97 | 8759 | /* 88 */ |
592d1631 L |
8760 | { Bad_Opcode }, |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
8764 | { Bad_Opcode }, | |
8765 | { Bad_Opcode }, | |
8766 | { Bad_Opcode }, | |
8767 | { Bad_Opcode }, | |
c0f3af97 | 8768 | /* 90 */ |
43234a1e L |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8773 | { Bad_Opcode }, |
8774 | { Bad_Opcode }, | |
8775 | { Bad_Opcode }, | |
8776 | { Bad_Opcode }, | |
c0f3af97 | 8777 | /* 98 */ |
43234a1e | 8778 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8779 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8780 | { Bad_Opcode }, |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
c0f3af97 | 8786 | /* a0 */ |
592d1631 L |
8787 | { Bad_Opcode }, |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
c0f3af97 | 8795 | /* a8 */ |
592d1631 L |
8796 | { Bad_Opcode }, |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
592a252b | 8802 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8803 | { Bad_Opcode }, |
c0f3af97 | 8804 | /* b0 */ |
592d1631 L |
8805 | { Bad_Opcode }, |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
c0f3af97 | 8813 | /* b8 */ |
592d1631 L |
8814 | { Bad_Opcode }, |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
c0f3af97 | 8822 | /* c0 */ |
592d1631 L |
8823 | { Bad_Opcode }, |
8824 | { Bad_Opcode }, | |
592a252b | 8825 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8826 | { Bad_Opcode }, |
592a252b L |
8827 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8828 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8829 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8830 | { Bad_Opcode }, |
c0f3af97 | 8831 | /* c8 */ |
592d1631 L |
8832 | { Bad_Opcode }, |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
c0f3af97 | 8840 | /* d0 */ |
592a252b L |
8841 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8842 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8845 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8846 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8847 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8848 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8849 | /* d8 */ |
592a252b L |
8850 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8851 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8854 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8855 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8856 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8857 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8858 | /* e0 */ |
592a252b L |
8859 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8860 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8865 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8866 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8867 | /* e8 */ |
592a252b L |
8868 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8869 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8870 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8872 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8874 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8875 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8876 | /* f0 */ |
592a252b L |
8877 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8878 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8879 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8880 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8881 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8882 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8883 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8884 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8885 | /* f8 */ |
592a252b L |
8886 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8887 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8888 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8893 | { Bad_Opcode }, |
c0f3af97 L |
8894 | }, |
8895 | /* VEX_0F38 */ | |
8896 | { | |
8897 | /* 00 */ | |
592a252b L |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8906 | /* 08 */ |
592a252b L |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8915 | /* 10 */ |
592d1631 L |
8916 | { Bad_Opcode }, |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
592a252b | 8919 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8920 | { Bad_Opcode }, |
8921 | { Bad_Opcode }, | |
6c30d220 | 8922 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8923 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8924 | /* 18 */ |
592a252b L |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8927 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8928 | { Bad_Opcode }, |
592a252b L |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8932 | { Bad_Opcode }, |
c0f3af97 | 8933 | /* 20 */ |
592a252b L |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8940 | { Bad_Opcode }, |
8941 | { Bad_Opcode }, | |
c0f3af97 | 8942 | /* 28 */ |
592a252b L |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8951 | /* 30 */ |
592a252b L |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8958 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8959 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8960 | /* 38 */ |
592a252b L |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8965 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8967 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8969 | /* 40 */ |
592a252b L |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8972 | { Bad_Opcode }, |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
6c30d220 L |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8978 | /* 48 */ |
592d1631 L |
8979 | { Bad_Opcode }, |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
c0f3af97 | 8987 | /* 50 */ |
592d1631 L |
8988 | { Bad_Opcode }, |
8989 | { Bad_Opcode }, | |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
c0f3af97 | 8996 | /* 58 */ |
6c30d220 L |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9000 | { Bad_Opcode }, |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
c0f3af97 | 9005 | /* 60 */ |
592d1631 L |
9006 | { Bad_Opcode }, |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
c0f3af97 | 9014 | /* 68 */ |
592d1631 L |
9015 | { Bad_Opcode }, |
9016 | { Bad_Opcode }, | |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
c0f3af97 | 9023 | /* 70 */ |
592d1631 L |
9024 | { Bad_Opcode }, |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
c0f3af97 | 9032 | /* 78 */ |
6c30d220 L |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9035 | { Bad_Opcode }, |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
c0f3af97 | 9041 | /* 80 */ |
592d1631 L |
9042 | { Bad_Opcode }, |
9043 | { Bad_Opcode }, | |
9044 | { Bad_Opcode }, | |
9045 | { Bad_Opcode }, | |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
c0f3af97 | 9050 | /* 88 */ |
592d1631 L |
9051 | { Bad_Opcode }, |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
6c30d220 | 9055 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9056 | { Bad_Opcode }, |
6c30d220 | 9057 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9058 | { Bad_Opcode }, |
c0f3af97 | 9059 | /* 90 */ |
6c30d220 L |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9064 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, | |
592a252b L |
9066 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9067 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9068 | /* 98 */ |
592a252b L |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9075 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9077 | /* a0 */ |
592d1631 L |
9078 | { Bad_Opcode }, |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
592a252b L |
9084 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9086 | /* a8 */ |
592a252b L |
9087 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9088 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9095 | /* b0 */ |
592d1631 L |
9096 | { Bad_Opcode }, |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
592a252b L |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9103 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9104 | /* b8 */ |
592a252b L |
9105 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9113 | /* c0 */ |
592d1631 L |
9114 | { Bad_Opcode }, |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
c0f3af97 | 9122 | /* c8 */ |
592d1631 L |
9123 | { Bad_Opcode }, |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
48521003 | 9130 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 9131 | /* d0 */ |
592d1631 L |
9132 | { Bad_Opcode }, |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
c0f3af97 | 9140 | /* d8 */ |
592d1631 L |
9141 | { Bad_Opcode }, |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
592a252b L |
9144 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9145 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9146 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9147 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9148 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9149 | /* e0 */ |
592d1631 L |
9150 | { Bad_Opcode }, |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
c0f3af97 | 9158 | /* e8 */ |
592d1631 L |
9159 | { Bad_Opcode }, |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
c0f3af97 | 9167 | /* f0 */ |
592d1631 L |
9168 | { Bad_Opcode }, |
9169 | { Bad_Opcode }, | |
f12dc422 L |
9170 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9171 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9172 | { Bad_Opcode }, |
6c30d220 L |
9173 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9174 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9175 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9176 | /* f8 */ |
592d1631 L |
9177 | { Bad_Opcode }, |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
c0f3af97 L |
9185 | }, |
9186 | /* VEX_0F3A */ | |
9187 | { | |
9188 | /* 00 */ | |
6c30d220 L |
9189 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9192 | { Bad_Opcode }, |
592a252b L |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9196 | { Bad_Opcode }, |
c0f3af97 | 9197 | /* 08 */ |
592a252b L |
9198 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9199 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9200 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9201 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9202 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9203 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9204 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9205 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9206 | /* 10 */ |
592d1631 L |
9207 | { Bad_Opcode }, |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
592a252b L |
9211 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9215 | /* 18 */ |
592a252b L |
9216 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9217 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9218 | { Bad_Opcode }, |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
592a252b | 9221 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9222 | { Bad_Opcode }, |
9223 | { Bad_Opcode }, | |
c0f3af97 | 9224 | /* 20 */ |
592a252b L |
9225 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9226 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9227 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9228 | { Bad_Opcode }, |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
c0f3af97 | 9233 | /* 28 */ |
592d1631 L |
9234 | { Bad_Opcode }, |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
c0f3af97 | 9242 | /* 30 */ |
43234a1e | 9243 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9244 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9245 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9246 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9247 | { Bad_Opcode }, |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
c0f3af97 | 9251 | /* 38 */ |
6c30d220 L |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9253 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9254 | { Bad_Opcode }, |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
c0f3af97 | 9260 | /* 40 */ |
592a252b L |
9261 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9262 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9263 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9264 | { Bad_Opcode }, |
592a252b | 9265 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9266 | { Bad_Opcode }, |
6c30d220 | 9267 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9268 | { Bad_Opcode }, |
c0f3af97 | 9269 | /* 48 */ |
592a252b L |
9270 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9271 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9272 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9273 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9274 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9275 | { Bad_Opcode }, |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
c0f3af97 | 9278 | /* 50 */ |
592d1631 L |
9279 | { Bad_Opcode }, |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
9282 | { Bad_Opcode }, | |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
c0f3af97 | 9287 | /* 58 */ |
592d1631 L |
9288 | { Bad_Opcode }, |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
9291 | { Bad_Opcode }, | |
592a252b L |
9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9294 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9295 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9296 | /* 60 */ |
592a252b L |
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9298 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9299 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9301 | { Bad_Opcode }, |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
c0f3af97 | 9305 | /* 68 */ |
592a252b L |
9306 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9307 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9308 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9309 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9314 | /* 70 */ |
592d1631 L |
9315 | { Bad_Opcode }, |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
9318 | { Bad_Opcode }, | |
9319 | { Bad_Opcode }, | |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
c0f3af97 | 9323 | /* 78 */ |
592a252b L |
9324 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9325 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9326 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9327 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9328 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9329 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9330 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9331 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9332 | /* 80 */ |
592d1631 L |
9333 | { Bad_Opcode }, |
9334 | { Bad_Opcode }, | |
9335 | { Bad_Opcode }, | |
9336 | { Bad_Opcode }, | |
9337 | { Bad_Opcode }, | |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
9340 | { Bad_Opcode }, | |
c0f3af97 | 9341 | /* 88 */ |
592d1631 L |
9342 | { Bad_Opcode }, |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
9345 | { Bad_Opcode }, | |
9346 | { Bad_Opcode }, | |
9347 | { Bad_Opcode }, | |
9348 | { Bad_Opcode }, | |
9349 | { Bad_Opcode }, | |
c0f3af97 | 9350 | /* 90 */ |
592d1631 L |
9351 | { Bad_Opcode }, |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
9354 | { Bad_Opcode }, | |
9355 | { Bad_Opcode }, | |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
c0f3af97 | 9359 | /* 98 */ |
592d1631 L |
9360 | { Bad_Opcode }, |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
9363 | { Bad_Opcode }, | |
9364 | { Bad_Opcode }, | |
9365 | { Bad_Opcode }, | |
9366 | { Bad_Opcode }, | |
9367 | { Bad_Opcode }, | |
c0f3af97 | 9368 | /* a0 */ |
592d1631 L |
9369 | { Bad_Opcode }, |
9370 | { Bad_Opcode }, | |
9371 | { Bad_Opcode }, | |
9372 | { Bad_Opcode }, | |
9373 | { Bad_Opcode }, | |
9374 | { Bad_Opcode }, | |
9375 | { Bad_Opcode }, | |
9376 | { Bad_Opcode }, | |
c0f3af97 | 9377 | /* a8 */ |
592d1631 L |
9378 | { Bad_Opcode }, |
9379 | { Bad_Opcode }, | |
9380 | { Bad_Opcode }, | |
9381 | { Bad_Opcode }, | |
9382 | { Bad_Opcode }, | |
9383 | { Bad_Opcode }, | |
9384 | { Bad_Opcode }, | |
9385 | { Bad_Opcode }, | |
c0f3af97 | 9386 | /* b0 */ |
592d1631 L |
9387 | { Bad_Opcode }, |
9388 | { Bad_Opcode }, | |
9389 | { Bad_Opcode }, | |
9390 | { Bad_Opcode }, | |
9391 | { Bad_Opcode }, | |
9392 | { Bad_Opcode }, | |
9393 | { Bad_Opcode }, | |
9394 | { Bad_Opcode }, | |
c0f3af97 | 9395 | /* b8 */ |
592d1631 L |
9396 | { Bad_Opcode }, |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
9399 | { Bad_Opcode }, | |
9400 | { Bad_Opcode }, | |
9401 | { Bad_Opcode }, | |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
c0f3af97 | 9404 | /* c0 */ |
592d1631 L |
9405 | { Bad_Opcode }, |
9406 | { Bad_Opcode }, | |
9407 | { Bad_Opcode }, | |
9408 | { Bad_Opcode }, | |
9409 | { Bad_Opcode }, | |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
c0f3af97 | 9413 | /* c8 */ |
592d1631 L |
9414 | { Bad_Opcode }, |
9415 | { Bad_Opcode }, | |
9416 | { Bad_Opcode }, | |
9417 | { Bad_Opcode }, | |
9418 | { Bad_Opcode }, | |
9419 | { Bad_Opcode }, | |
48521003 IT |
9420 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9421 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9422 | /* d0 */ |
592d1631 L |
9423 | { Bad_Opcode }, |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
9426 | { Bad_Opcode }, | |
9427 | { Bad_Opcode }, | |
9428 | { Bad_Opcode }, | |
9429 | { Bad_Opcode }, | |
9430 | { Bad_Opcode }, | |
c0f3af97 | 9431 | /* d8 */ |
592d1631 L |
9432 | { Bad_Opcode }, |
9433 | { Bad_Opcode }, | |
9434 | { Bad_Opcode }, | |
9435 | { Bad_Opcode }, | |
9436 | { Bad_Opcode }, | |
9437 | { Bad_Opcode }, | |
9438 | { Bad_Opcode }, | |
592a252b | 9439 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9440 | /* e0 */ |
592d1631 L |
9441 | { Bad_Opcode }, |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
9444 | { Bad_Opcode }, | |
9445 | { Bad_Opcode }, | |
9446 | { Bad_Opcode }, | |
9447 | { Bad_Opcode }, | |
9448 | { Bad_Opcode }, | |
c0f3af97 | 9449 | /* e8 */ |
592d1631 L |
9450 | { Bad_Opcode }, |
9451 | { Bad_Opcode }, | |
9452 | { Bad_Opcode }, | |
9453 | { Bad_Opcode }, | |
9454 | { Bad_Opcode }, | |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
c0f3af97 | 9458 | /* f0 */ |
6c30d220 | 9459 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9460 | { Bad_Opcode }, |
9461 | { Bad_Opcode }, | |
9462 | { Bad_Opcode }, | |
9463 | { Bad_Opcode }, | |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
9466 | { Bad_Opcode }, | |
c0f3af97 | 9467 | /* f8 */ |
592d1631 L |
9468 | { Bad_Opcode }, |
9469 | { Bad_Opcode }, | |
9470 | { Bad_Opcode }, | |
9471 | { Bad_Opcode }, | |
9472 | { Bad_Opcode }, | |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
9475 | { Bad_Opcode }, | |
c0f3af97 L |
9476 | }, |
9477 | }; | |
9478 | ||
43234a1e L |
9479 | #define NEED_OPCODE_TABLE |
9480 | #include "i386-dis-evex.h" | |
9481 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9482 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9483 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9484 | { |
592a252b L |
9485 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9486 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9487 | }, |
9488 | ||
592a252b | 9489 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9490 | { |
592a252b L |
9491 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9492 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9493 | }, |
9494 | ||
592a252b | 9495 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9496 | { |
592a252b L |
9497 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9498 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9499 | }, |
9500 | ||
592a252b | 9501 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9502 | { |
592a252b L |
9503 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9504 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9505 | }, |
9506 | ||
592a252b | 9507 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9508 | { |
592a252b | 9509 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9510 | }, |
9511 | ||
592a252b | 9512 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9513 | { |
592a252b | 9514 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9515 | }, |
9516 | ||
592a252b | 9517 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9518 | { |
592a252b | 9519 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9520 | }, |
9521 | ||
592a252b | 9522 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9523 | { |
592a252b | 9524 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9525 | }, |
9526 | ||
592a252b | 9527 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9528 | { |
592a252b | 9529 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9530 | }, |
9531 | ||
592a252b | 9532 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9533 | { |
592a252b | 9534 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9535 | }, |
9536 | ||
592a252b | 9537 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9538 | { |
592a252b | 9539 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9540 | }, |
9541 | ||
592a252b | 9542 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9543 | { |
592a252b | 9544 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9545 | }, |
9546 | ||
592a252b | 9547 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9548 | { |
bf890a93 IT |
9549 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9550 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9551 | }, |
9552 | ||
592a252b | 9553 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9554 | { |
bf890a93 IT |
9555 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9556 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9557 | }, |
9558 | ||
592a252b | 9559 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9560 | { |
9646c87b JB |
9561 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, |
9562 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9563 | }, |
9564 | ||
592a252b | 9565 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9566 | { |
9646c87b JB |
9567 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, |
9568 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9569 | }, |
9570 | ||
592a252b | 9571 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9572 | { |
9646c87b JB |
9573 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, |
9574 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9575 | }, |
9576 | ||
592a252b | 9577 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9578 | { |
9646c87b JB |
9579 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, |
9580 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9581 | }, |
9582 | ||
592a252b | 9583 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9584 | { |
592a252b L |
9585 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9586 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9587 | }, |
9588 | ||
592a252b | 9589 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9590 | { |
592a252b L |
9591 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9592 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9593 | }, |
9594 | ||
592a252b | 9595 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9596 | { |
592a252b L |
9597 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9598 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9599 | }, |
9600 | ||
592a252b | 9601 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9602 | { |
592a252b L |
9603 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9604 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9605 | }, |
9606 | ||
43234a1e L |
9607 | /* VEX_LEN_0F41_P_0 */ |
9608 | { | |
9609 | { Bad_Opcode }, | |
9610 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9611 | }, | |
1ba585e8 IT |
9612 | /* VEX_LEN_0F41_P_2 */ |
9613 | { | |
9614 | { Bad_Opcode }, | |
9615 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9616 | }, | |
43234a1e L |
9617 | /* VEX_LEN_0F42_P_0 */ |
9618 | { | |
9619 | { Bad_Opcode }, | |
9620 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9621 | }, | |
1ba585e8 IT |
9622 | /* VEX_LEN_0F42_P_2 */ |
9623 | { | |
9624 | { Bad_Opcode }, | |
9625 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9626 | }, | |
43234a1e L |
9627 | /* VEX_LEN_0F44_P_0 */ |
9628 | { | |
9629 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9630 | }, | |
1ba585e8 IT |
9631 | /* VEX_LEN_0F44_P_2 */ |
9632 | { | |
9633 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9634 | }, | |
43234a1e L |
9635 | /* VEX_LEN_0F45_P_0 */ |
9636 | { | |
9637 | { Bad_Opcode }, | |
9638 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9639 | }, | |
1ba585e8 IT |
9640 | /* VEX_LEN_0F45_P_2 */ |
9641 | { | |
9642 | { Bad_Opcode }, | |
9643 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9644 | }, | |
43234a1e L |
9645 | /* VEX_LEN_0F46_P_0 */ |
9646 | { | |
9647 | { Bad_Opcode }, | |
9648 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9649 | }, | |
1ba585e8 IT |
9650 | /* VEX_LEN_0F46_P_2 */ |
9651 | { | |
9652 | { Bad_Opcode }, | |
9653 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9654 | }, | |
43234a1e L |
9655 | /* VEX_LEN_0F47_P_0 */ |
9656 | { | |
9657 | { Bad_Opcode }, | |
9658 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9659 | }, | |
1ba585e8 IT |
9660 | /* VEX_LEN_0F47_P_2 */ |
9661 | { | |
9662 | { Bad_Opcode }, | |
9663 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9664 | }, | |
9665 | /* VEX_LEN_0F4A_P_0 */ | |
9666 | { | |
9667 | { Bad_Opcode }, | |
9668 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9669 | }, | |
9670 | /* VEX_LEN_0F4A_P_2 */ | |
9671 | { | |
9672 | { Bad_Opcode }, | |
9673 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9674 | }, | |
9675 | /* VEX_LEN_0F4B_P_0 */ | |
9676 | { | |
9677 | { Bad_Opcode }, | |
9678 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9679 | }, | |
43234a1e L |
9680 | /* VEX_LEN_0F4B_P_2 */ |
9681 | { | |
9682 | { Bad_Opcode }, | |
9683 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9684 | }, | |
9685 | ||
592a252b | 9686 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9687 | { |
592a252b L |
9688 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9689 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9693 | { |
592a252b L |
9694 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9695 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9696 | }, |
9697 | ||
592a252b | 9698 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9699 | { |
592a252b L |
9700 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9701 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9702 | }, |
9703 | ||
592a252b | 9704 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9705 | { |
592a252b L |
9706 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9707 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9708 | }, |
9709 | ||
592a252b | 9710 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9711 | { |
592a252b L |
9712 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9713 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9714 | }, |
9715 | ||
592a252b | 9716 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9717 | { |
592a252b L |
9718 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9719 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9720 | }, |
9721 | ||
592a252b | 9722 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9723 | { |
592a252b L |
9724 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9725 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9726 | }, |
9727 | ||
592a252b | 9728 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9729 | { |
592a252b L |
9730 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9731 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9732 | }, |
9733 | ||
592a252b | 9734 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9735 | { |
592a252b L |
9736 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9737 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9738 | }, |
9739 | ||
592a252b | 9740 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9741 | { |
592a252b L |
9742 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9743 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9744 | }, |
9745 | ||
592a252b | 9746 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9747 | { |
592a252b L |
9748 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9749 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9750 | }, |
9751 | ||
592a252b | 9752 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9753 | { |
592a252b L |
9754 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9755 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9756 | }, |
9757 | ||
592a252b | 9758 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9759 | { |
592a252b L |
9760 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9761 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9762 | }, |
9763 | ||
592a252b | 9764 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9765 | { |
592a252b L |
9766 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9767 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9768 | }, |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9771 | { |
592a252b L |
9772 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9773 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9774 | }, |
9775 | ||
592a252b | 9776 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9777 | { |
592a252b L |
9778 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9779 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9783 | { |
592a252b L |
9784 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9785 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9786 | }, |
9787 | ||
592a252b | 9788 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9789 | { |
592a252b L |
9790 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9791 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9792 | }, |
9793 | ||
592a252b | 9794 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9795 | { |
bf890a93 IT |
9796 | { "vmovK", { XMScalar, Edq }, 0 }, |
9797 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9798 | }, |
9799 | ||
592a252b | 9800 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9801 | { |
592a252b L |
9802 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9803 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9804 | }, |
9805 | ||
592a252b | 9806 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9807 | { |
bf890a93 IT |
9808 | { "vmovK", { Edq, XMScalar }, 0 }, |
9809 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9810 | }, |
9811 | ||
43234a1e L |
9812 | /* VEX_LEN_0F90_P_0 */ |
9813 | { | |
9814 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9815 | }, | |
9816 | ||
1ba585e8 IT |
9817 | /* VEX_LEN_0F90_P_2 */ |
9818 | { | |
9819 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9820 | }, | |
9821 | ||
43234a1e L |
9822 | /* VEX_LEN_0F91_P_0 */ |
9823 | { | |
9824 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9825 | }, | |
9826 | ||
1ba585e8 IT |
9827 | /* VEX_LEN_0F91_P_2 */ |
9828 | { | |
9829 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9830 | }, | |
9831 | ||
43234a1e L |
9832 | /* VEX_LEN_0F92_P_0 */ |
9833 | { | |
9834 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9835 | }, | |
9836 | ||
90a915bf IT |
9837 | /* VEX_LEN_0F92_P_2 */ |
9838 | { | |
9839 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9840 | }, | |
9841 | ||
1ba585e8 IT |
9842 | /* VEX_LEN_0F92_P_3 */ |
9843 | { | |
9844 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9845 | }, | |
9846 | ||
43234a1e L |
9847 | /* VEX_LEN_0F93_P_0 */ |
9848 | { | |
9849 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9850 | }, | |
9851 | ||
90a915bf IT |
9852 | /* VEX_LEN_0F93_P_2 */ |
9853 | { | |
9854 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9855 | }, | |
9856 | ||
1ba585e8 IT |
9857 | /* VEX_LEN_0F93_P_3 */ |
9858 | { | |
9859 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9860 | }, | |
9861 | ||
43234a1e L |
9862 | /* VEX_LEN_0F98_P_0 */ |
9863 | { | |
9864 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9865 | }, | |
9866 | ||
1ba585e8 IT |
9867 | /* VEX_LEN_0F98_P_2 */ |
9868 | { | |
9869 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9870 | }, | |
9871 | ||
9872 | /* VEX_LEN_0F99_P_0 */ | |
9873 | { | |
9874 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9875 | }, | |
9876 | ||
9877 | /* VEX_LEN_0F99_P_2 */ | |
9878 | { | |
9879 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9880 | }, | |
9881 | ||
6c30d220 | 9882 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9883 | { |
6c30d220 | 9884 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9885 | }, |
9886 | ||
6c30d220 | 9887 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9888 | { |
6c30d220 | 9889 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9890 | }, |
9891 | ||
6c30d220 | 9892 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9893 | { |
6c30d220 L |
9894 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9895 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9896 | }, |
9897 | ||
6c30d220 | 9898 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9899 | { |
6c30d220 L |
9900 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9901 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9902 | }, |
9903 | ||
6c30d220 | 9904 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9905 | { |
6c30d220 | 9906 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9907 | }, |
9908 | ||
6c30d220 | 9909 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9910 | { |
6c30d220 | 9911 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9912 | }, |
9913 | ||
6c30d220 | 9914 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9915 | { |
6c30d220 L |
9916 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9917 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9918 | }, |
9919 | ||
6c30d220 | 9920 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9921 | { |
6c30d220 | 9922 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9923 | }, |
9924 | ||
6c30d220 | 9925 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9926 | { |
6c30d220 L |
9927 | { Bad_Opcode }, |
9928 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9929 | }, |
9930 | ||
6c30d220 | 9931 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9932 | { |
6c30d220 L |
9933 | { Bad_Opcode }, |
9934 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9935 | }, |
9936 | ||
6c30d220 | 9937 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9938 | { |
6c30d220 L |
9939 | { Bad_Opcode }, |
9940 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9941 | }, |
9942 | ||
6c30d220 | 9943 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9944 | { |
6c30d220 L |
9945 | { Bad_Opcode }, |
9946 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9947 | }, |
9948 | ||
592a252b | 9949 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9950 | { |
592a252b | 9951 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9952 | }, |
9953 | ||
6c30d220 L |
9954 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9955 | { | |
9956 | { Bad_Opcode }, | |
9957 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9958 | }, | |
9959 | ||
592a252b | 9960 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9961 | { |
592a252b | 9962 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9963 | }, |
9964 | ||
f12dc422 L |
9965 | /* VEX_LEN_0F38F2_P_0 */ |
9966 | { | |
bf890a93 | 9967 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9968 | }, |
9969 | ||
9970 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9971 | { | |
bf890a93 | 9972 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9973 | }, |
9974 | ||
9975 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9976 | { | |
bf890a93 | 9977 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9978 | }, |
9979 | ||
9980 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9981 | { | |
bf890a93 | 9982 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9983 | }, |
9984 | ||
6c30d220 L |
9985 | /* VEX_LEN_0F38F5_P_0 */ |
9986 | { | |
bf890a93 | 9987 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9988 | }, |
9989 | ||
9990 | /* VEX_LEN_0F38F5_P_1 */ | |
9991 | { | |
bf890a93 | 9992 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9993 | }, |
9994 | ||
9995 | /* VEX_LEN_0F38F5_P_3 */ | |
9996 | { | |
bf890a93 | 9997 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9998 | }, |
9999 | ||
10000 | /* VEX_LEN_0F38F6_P_3 */ | |
10001 | { | |
bf890a93 | 10002 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10003 | }, |
10004 | ||
f12dc422 L |
10005 | /* VEX_LEN_0F38F7_P_0 */ |
10006 | { | |
bf890a93 | 10007 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10008 | }, |
10009 | ||
6c30d220 L |
10010 | /* VEX_LEN_0F38F7_P_1 */ |
10011 | { | |
bf890a93 | 10012 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10013 | }, |
10014 | ||
10015 | /* VEX_LEN_0F38F7_P_2 */ | |
10016 | { | |
bf890a93 | 10017 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10018 | }, |
10019 | ||
10020 | /* VEX_LEN_0F38F7_P_3 */ | |
10021 | { | |
bf890a93 | 10022 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10023 | }, |
10024 | ||
10025 | /* VEX_LEN_0F3A00_P_2 */ | |
10026 | { | |
10027 | { Bad_Opcode }, | |
10028 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10029 | }, | |
10030 | ||
10031 | /* VEX_LEN_0F3A01_P_2 */ | |
10032 | { | |
10033 | { Bad_Opcode }, | |
10034 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10035 | }, | |
10036 | ||
592a252b | 10037 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10038 | { |
592d1631 | 10039 | { Bad_Opcode }, |
592a252b | 10040 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10041 | }, |
10042 | ||
592a252b | 10043 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10044 | { |
592a252b L |
10045 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10046 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10047 | }, |
10048 | ||
592a252b | 10049 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10050 | { |
592a252b L |
10051 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10052 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10053 | }, |
10054 | ||
592a252b | 10055 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10056 | { |
592a252b | 10057 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10058 | }, |
10059 | ||
592a252b | 10060 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10061 | { |
592a252b | 10062 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10063 | }, |
10064 | ||
592a252b | 10065 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10066 | { |
bf890a93 | 10067 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10068 | }, |
10069 | ||
592a252b | 10070 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10071 | { |
bf890a93 | 10072 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10073 | }, |
10074 | ||
592a252b | 10075 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10076 | { |
592d1631 | 10077 | { Bad_Opcode }, |
592a252b | 10078 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10079 | }, |
10080 | ||
592a252b | 10081 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10082 | { |
592d1631 | 10083 | { Bad_Opcode }, |
592a252b | 10084 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10085 | }, |
10086 | ||
592a252b | 10087 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10088 | { |
592a252b | 10089 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10090 | }, |
10091 | ||
592a252b | 10092 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10093 | { |
592a252b | 10094 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10095 | }, |
10096 | ||
592a252b | 10097 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10098 | { |
bf890a93 | 10099 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10100 | }, |
10101 | ||
43234a1e L |
10102 | /* VEX_LEN_0F3A30_P_2 */ |
10103 | { | |
10104 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10105 | }, | |
10106 | ||
1ba585e8 IT |
10107 | /* VEX_LEN_0F3A31_P_2 */ |
10108 | { | |
10109 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10110 | }, | |
10111 | ||
43234a1e L |
10112 | /* VEX_LEN_0F3A32_P_2 */ |
10113 | { | |
10114 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10115 | }, | |
10116 | ||
1ba585e8 IT |
10117 | /* VEX_LEN_0F3A33_P_2 */ |
10118 | { | |
10119 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10120 | }, | |
10121 | ||
6c30d220 | 10122 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10123 | { |
6c30d220 L |
10124 | { Bad_Opcode }, |
10125 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10126 | }, |
10127 | ||
6c30d220 | 10128 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10129 | { |
6c30d220 L |
10130 | { Bad_Opcode }, |
10131 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10132 | }, | |
10133 | ||
10134 | /* VEX_LEN_0F3A41_P_2 */ | |
10135 | { | |
10136 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10137 | }, |
10138 | ||
6c30d220 | 10139 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10140 | { |
6c30d220 L |
10141 | { Bad_Opcode }, |
10142 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10143 | }, |
10144 | ||
592a252b | 10145 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10146 | { |
15c7c1d8 | 10147 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10148 | }, |
10149 | ||
592a252b | 10150 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10151 | { |
15c7c1d8 | 10152 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10153 | }, |
10154 | ||
592a252b | 10155 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10156 | { |
592a252b | 10157 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10158 | }, |
10159 | ||
592a252b | 10160 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10161 | { |
592a252b | 10162 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10163 | }, |
10164 | ||
592a252b | 10165 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10166 | { |
3a2430e0 | 10167 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10168 | }, |
10169 | ||
592a252b | 10170 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10171 | { |
3a2430e0 | 10172 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10173 | }, |
10174 | ||
592a252b | 10175 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10176 | { |
3a2430e0 | 10177 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10178 | }, |
10179 | ||
592a252b | 10180 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10181 | { |
3a2430e0 | 10182 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10183 | }, |
10184 | ||
592a252b | 10185 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10186 | { |
3a2430e0 | 10187 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10188 | }, |
10189 | ||
592a252b | 10190 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10191 | { |
3a2430e0 | 10192 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10193 | }, |
10194 | ||
592a252b | 10195 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10196 | { |
3a2430e0 | 10197 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10198 | }, |
10199 | ||
592a252b | 10200 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10201 | { |
3a2430e0 | 10202 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10203 | }, |
10204 | ||
592a252b | 10205 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10206 | { |
592a252b | 10207 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10208 | }, |
4c807e72 | 10209 | |
6c30d220 L |
10210 | /* VEX_LEN_0F3AF0_P_3 */ |
10211 | { | |
bf890a93 | 10212 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10213 | }, |
10214 | ||
ff688e1f L |
10215 | /* VEX_LEN_0FXOP_08_CC */ |
10216 | { | |
be92cb14 | 10217 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10218 | }, |
10219 | ||
10220 | /* VEX_LEN_0FXOP_08_CD */ | |
10221 | { | |
be92cb14 | 10222 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10223 | }, |
10224 | ||
10225 | /* VEX_LEN_0FXOP_08_CE */ | |
10226 | { | |
be92cb14 | 10227 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10228 | }, |
10229 | ||
10230 | /* VEX_LEN_0FXOP_08_CF */ | |
10231 | { | |
be92cb14 | 10232 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10233 | }, |
10234 | ||
10235 | /* VEX_LEN_0FXOP_08_EC */ | |
10236 | { | |
be92cb14 | 10237 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10238 | }, |
10239 | ||
10240 | /* VEX_LEN_0FXOP_08_ED */ | |
10241 | { | |
be92cb14 | 10242 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10243 | }, |
10244 | ||
10245 | /* VEX_LEN_0FXOP_08_EE */ | |
10246 | { | |
be92cb14 | 10247 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10248 | }, |
10249 | ||
10250 | /* VEX_LEN_0FXOP_08_EF */ | |
10251 | { | |
be92cb14 | 10252 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10253 | }, |
10254 | ||
592a252b | 10255 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10256 | { |
bf890a93 IT |
10257 | { "vfrczps", { XM, EXxmm }, 0 }, |
10258 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10259 | }, |
4c807e72 | 10260 | |
592a252b | 10261 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10262 | { |
bf890a93 IT |
10263 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10264 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10265 | }, |
331d2d0d L |
10266 | }; |
10267 | ||
9e30b8e0 | 10268 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10269 | { |
592a252b | 10270 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10271 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10272 | }, |
10273 | { | |
592a252b | 10274 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10275 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10276 | }, |
10277 | { | |
592a252b | 10278 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10279 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10280 | }, |
10281 | { | |
592a252b | 10282 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10283 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10284 | }, |
10285 | { | |
592a252b | 10286 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10287 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10288 | }, |
10289 | { | |
592a252b | 10290 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10291 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10292 | }, |
10293 | { | |
592a252b | 10294 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10295 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10296 | }, |
10297 | { | |
592a252b | 10298 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10299 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10300 | }, |
10301 | { | |
592a252b | 10302 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10303 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10304 | }, |
10305 | { | |
592a252b | 10306 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10307 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10308 | }, |
10309 | { | |
592a252b | 10310 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10311 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10312 | }, |
10313 | { | |
592a252b | 10314 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10315 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10316 | }, |
10317 | { | |
592a252b | 10318 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10319 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10320 | }, |
10321 | { | |
592a252b | 10322 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10323 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10324 | }, |
10325 | { | |
592a252b | 10326 | /* VEX_W_0F14 */ |
bf890a93 | 10327 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10328 | }, |
10329 | { | |
592a252b | 10330 | /* VEX_W_0F15 */ |
bf890a93 | 10331 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10332 | }, |
10333 | { | |
592a252b | 10334 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10335 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10336 | }, |
10337 | { | |
592a252b | 10338 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10339 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10340 | }, |
10341 | { | |
592a252b | 10342 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10343 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10344 | }, |
10345 | { | |
592a252b | 10346 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10347 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10348 | }, |
10349 | { | |
592a252b | 10350 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10351 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10352 | }, |
10353 | { | |
592a252b | 10354 | /* VEX_W_0F28 */ |
bf890a93 | 10355 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10356 | }, |
10357 | { | |
592a252b | 10358 | /* VEX_W_0F29 */ |
bf890a93 | 10359 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10360 | }, |
10361 | { | |
592a252b | 10362 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10363 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10364 | }, |
10365 | { | |
592a252b | 10366 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10367 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10368 | }, |
10369 | { | |
592a252b | 10370 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10371 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10372 | }, |
10373 | { | |
592a252b | 10374 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10375 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10376 | }, |
10377 | { | |
592a252b | 10378 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10379 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10380 | }, |
43234a1e L |
10381 | { |
10382 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10383 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10384 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10385 | }, |
10386 | { | |
10387 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10388 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10389 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10390 | }, |
10391 | { | |
10392 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10393 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10394 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10395 | }, |
10396 | { | |
10397 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10398 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10399 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10400 | }, |
10401 | { | |
10402 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10403 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10404 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10405 | }, |
10406 | { | |
10407 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10408 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10409 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10410 | }, |
10411 | { | |
10412 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10413 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10414 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10415 | }, |
10416 | { | |
10417 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10418 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10419 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10420 | }, |
10421 | { | |
10422 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10423 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10424 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10425 | }, |
10426 | { | |
10427 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10428 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10429 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10430 | }, |
10431 | { | |
10432 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10433 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10434 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10435 | }, |
10436 | { | |
10437 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10438 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10439 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10440 | }, |
10441 | { | |
10442 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10443 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10444 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10445 | }, |
10446 | { | |
10447 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10448 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10449 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10450 | }, |
10451 | { | |
10452 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10453 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10454 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10455 | }, |
10456 | { | |
10457 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10458 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10459 | }, |
9e30b8e0 | 10460 | { |
592a252b | 10461 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10462 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10463 | }, |
10464 | { | |
592a252b | 10465 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10466 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10467 | }, |
10468 | { | |
592a252b | 10469 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10470 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10471 | }, |
10472 | { | |
592a252b | 10473 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10474 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10475 | }, |
10476 | { | |
592a252b | 10477 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10478 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10479 | }, |
10480 | { | |
592a252b | 10481 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10482 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10483 | }, |
10484 | { | |
592a252b | 10485 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10486 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10487 | }, |
10488 | { | |
592a252b | 10489 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10490 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10491 | }, |
10492 | { | |
592a252b | 10493 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10494 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10495 | }, |
10496 | { | |
592a252b | 10497 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10498 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10499 | }, |
10500 | { | |
592a252b | 10501 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10502 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10503 | }, |
10504 | { | |
592a252b | 10505 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10506 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10507 | }, |
10508 | { | |
592a252b | 10509 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10510 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10511 | }, |
10512 | { | |
592a252b | 10513 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10514 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10515 | }, |
10516 | { | |
592a252b | 10517 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10518 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10519 | }, |
10520 | { | |
592a252b | 10521 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10522 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10523 | }, |
10524 | { | |
592a252b | 10525 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10526 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10527 | }, |
10528 | { | |
592a252b | 10529 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10530 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10531 | }, |
10532 | { | |
592a252b | 10533 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10534 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10535 | }, |
10536 | { | |
592a252b | 10537 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10538 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10539 | }, |
10540 | { | |
592a252b | 10541 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10542 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10543 | }, |
10544 | { | |
592a252b | 10545 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10546 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10547 | }, |
10548 | { | |
592a252b | 10549 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10550 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10551 | }, |
10552 | { | |
592a252b | 10553 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10554 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10555 | }, |
10556 | { | |
592a252b | 10557 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10558 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10559 | }, |
10560 | { | |
592a252b | 10561 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10562 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10563 | }, |
10564 | { | |
592a252b | 10565 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10566 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10567 | }, |
10568 | { | |
592a252b | 10569 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10570 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10571 | }, |
10572 | { | |
592a252b | 10573 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10574 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10575 | }, |
10576 | { | |
592a252b | 10577 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10578 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10579 | }, |
10580 | { | |
592a252b | 10581 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10582 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10583 | }, |
10584 | { | |
592a252b | 10585 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10586 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10587 | }, |
10588 | { | |
592a252b | 10589 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10590 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10591 | }, |
10592 | { | |
592a252b | 10593 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10594 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10595 | }, |
10596 | { | |
592a252b | 10597 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10598 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10599 | }, |
10600 | { | |
592a252b | 10601 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10602 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10603 | }, |
10604 | { | |
592a252b | 10605 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10606 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10607 | }, |
10608 | { | |
592a252b | 10609 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10610 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10611 | }, |
10612 | { | |
592a252b | 10613 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10614 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10615 | }, |
10616 | { | |
592a252b | 10617 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10618 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10619 | }, |
10620 | { | |
592a252b | 10621 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10622 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10623 | }, |
10624 | { | |
592a252b | 10625 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10626 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10627 | }, |
10628 | { | |
592a252b | 10629 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10630 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10631 | }, |
10632 | { | |
592a252b | 10633 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10634 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10635 | }, |
10636 | { | |
592a252b | 10637 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10638 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10639 | }, |
10640 | { | |
592a252b | 10641 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10642 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10643 | }, |
10644 | { | |
592a252b | 10645 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10646 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10647 | }, |
10648 | { | |
592a252b | 10649 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10650 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10651 | }, |
10652 | { | |
592a252b | 10653 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10654 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10655 | }, |
10656 | { | |
592a252b | 10657 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10658 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10659 | }, |
10660 | { | |
592a252b | 10661 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10662 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10663 | }, |
10664 | { | |
592a252b | 10665 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10666 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10667 | }, |
10668 | { | |
592a252b | 10669 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10670 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10671 | }, |
10672 | { | |
592a252b | 10673 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10674 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10675 | }, |
10676 | { | |
592a252b | 10677 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10678 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10679 | }, |
10680 | { | |
592a252b | 10681 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10682 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10683 | }, |
10684 | { | |
592a252b | 10685 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10686 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10687 | }, |
10688 | { | |
592a252b | 10689 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10690 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10691 | }, |
10692 | { | |
592a252b | 10693 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10694 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10695 | }, |
10696 | { | |
592a252b | 10697 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10698 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10699 | }, |
10700 | { | |
592a252b | 10701 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10702 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10703 | }, |
10704 | { | |
592a252b | 10705 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10706 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10707 | }, |
10708 | { | |
592a252b | 10709 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10710 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10711 | }, |
10712 | { | |
592a252b | 10713 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10714 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10715 | }, |
10716 | { | |
592a252b | 10717 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10718 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10719 | }, |
10720 | { | |
592a252b | 10721 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10722 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10723 | }, |
10724 | { | |
592a252b | 10725 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10726 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10727 | }, |
10728 | { | |
592a252b | 10729 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10730 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10731 | }, |
10732 | { | |
592a252b | 10733 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10734 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10735 | }, |
10736 | { | |
592a252b | 10737 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10738 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10739 | }, |
10740 | { | |
592a252b | 10741 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10742 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10743 | }, |
10744 | { | |
592a252b | 10745 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10746 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10747 | }, |
10748 | { | |
592a252b | 10749 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10750 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10751 | }, |
10752 | { | |
592a252b | 10753 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10754 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10755 | }, |
10756 | { | |
592a252b | 10757 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10758 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10759 | }, |
10760 | { | |
592a252b | 10761 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10762 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10763 | }, |
10764 | { | |
592a252b | 10765 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10766 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10767 | }, |
10768 | { | |
592a252b | 10769 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10770 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10771 | }, |
10772 | { | |
592a252b | 10773 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10774 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10775 | }, |
43234a1e L |
10776 | { |
10777 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10778 | { "kmovw", { MaskG, MaskE }, 0 }, |
10779 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10780 | }, |
10781 | { | |
10782 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10783 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10784 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10785 | }, |
10786 | { | |
10787 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10788 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10789 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10790 | }, |
10791 | { | |
10792 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10793 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10794 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10795 | }, |
10796 | { | |
10797 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10798 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10799 | }, |
90a915bf IT |
10800 | { |
10801 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10802 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10803 | }, |
1ba585e8 IT |
10804 | { |
10805 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10806 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10807 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10808 | }, |
43234a1e L |
10809 | { |
10810 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10811 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10812 | }, |
90a915bf IT |
10813 | { |
10814 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10815 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10816 | }, |
1ba585e8 IT |
10817 | { |
10818 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10819 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10820 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10821 | }, |
43234a1e L |
10822 | { |
10823 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10824 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10825 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10826 | }, |
10827 | { | |
10828 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10829 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10830 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10831 | }, |
10832 | { | |
10833 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10834 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10835 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10836 | }, |
10837 | { | |
10838 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10839 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10840 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10841 | }, |
9e30b8e0 | 10842 | { |
592a252b | 10843 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10844 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10845 | }, |
10846 | { | |
592a252b | 10847 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10848 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10849 | }, |
10850 | { | |
592a252b | 10851 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10852 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10853 | }, |
10854 | { | |
592a252b | 10855 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10856 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10857 | }, |
10858 | { | |
592a252b | 10859 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10860 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10861 | }, |
10862 | { | |
592a252b | 10863 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10864 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10865 | }, |
10866 | { | |
592a252b | 10867 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10868 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10869 | }, |
10870 | { | |
592a252b | 10871 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10872 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10873 | }, |
10874 | { | |
592a252b | 10875 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10876 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10877 | }, |
10878 | { | |
592a252b | 10879 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10880 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10881 | }, |
10882 | { | |
592a252b | 10883 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10884 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10885 | }, |
10886 | { | |
592a252b | 10887 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10888 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10889 | }, |
10890 | { | |
592a252b | 10891 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10892 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10893 | }, |
10894 | { | |
592a252b | 10895 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10896 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10897 | }, |
10898 | { | |
592a252b | 10899 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10900 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10901 | }, |
10902 | { | |
592a252b | 10903 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10904 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10905 | }, |
10906 | { | |
592a252b | 10907 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10908 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10909 | }, |
10910 | { | |
592a252b | 10911 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10912 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10913 | }, |
10914 | { | |
592a252b | 10915 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10916 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10917 | }, |
10918 | { | |
592a252b | 10919 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10920 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10921 | }, |
10922 | { | |
592a252b | 10923 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10924 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10925 | }, |
10926 | { | |
592a252b | 10927 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10928 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10929 | }, |
10930 | { | |
592a252b | 10931 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10932 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10933 | }, |
10934 | { | |
592a252b | 10935 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10936 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10937 | }, |
10938 | { | |
592a252b | 10939 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10940 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10941 | }, |
10942 | { | |
592a252b | 10943 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10944 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10945 | }, |
10946 | { | |
592a252b | 10947 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10948 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10949 | }, |
10950 | { | |
592a252b | 10951 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10952 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10953 | }, |
10954 | { | |
592a252b | 10955 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 10956 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10957 | }, |
10958 | { | |
592a252b | 10959 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 10960 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10961 | }, |
10962 | { | |
592a252b | 10963 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 10964 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10965 | }, |
10966 | { | |
592a252b | 10967 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 10968 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10969 | }, |
10970 | { | |
592a252b | 10971 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 10972 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10973 | }, |
10974 | { | |
592a252b | 10975 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 10976 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10977 | }, |
10978 | { | |
592a252b | 10979 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 10980 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
10981 | }, |
10982 | { | |
592a252b | 10983 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 10984 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10985 | }, |
10986 | { | |
592a252b | 10987 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 10988 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10989 | }, |
10990 | { | |
592a252b | 10991 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 10992 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10993 | }, |
10994 | { | |
592a252b | 10995 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 10996 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10997 | }, |
10998 | { | |
592a252b | 10999 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11000 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11001 | }, |
11002 | { | |
592a252b | 11003 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11004 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11005 | }, |
11006 | { | |
592a252b | 11007 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11008 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11009 | }, |
11010 | { | |
592a252b | 11011 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11012 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11013 | }, |
11014 | { | |
592a252b | 11015 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11016 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11017 | }, |
11018 | { | |
592a252b | 11019 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11020 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11021 | }, |
11022 | { | |
592a252b | 11023 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11024 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11025 | }, |
11026 | { | |
592a252b | 11027 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11028 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11029 | }, |
11030 | { | |
592a252b | 11031 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11032 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11033 | }, |
11034 | { | |
592a252b | 11035 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11036 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11037 | }, |
11038 | { | |
592a252b | 11039 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11040 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11041 | }, |
11042 | { | |
592a252b | 11043 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11044 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11045 | }, |
11046 | { | |
592a252b | 11047 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11048 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11049 | }, |
11050 | { | |
592a252b | 11051 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11052 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11053 | }, |
11054 | { | |
592a252b | 11055 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11056 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11057 | }, |
11058 | { | |
592a252b | 11059 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11060 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11061 | }, |
11062 | { | |
592a252b | 11063 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11064 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11065 | }, |
11066 | { | |
592a252b | 11067 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11068 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11069 | }, |
11070 | { | |
592a252b | 11071 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11072 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11073 | }, |
11074 | { | |
592a252b | 11075 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11076 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11077 | }, |
11078 | { | |
592a252b | 11079 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11080 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11081 | }, |
11082 | { | |
592a252b | 11083 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11084 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11085 | }, |
11086 | { | |
592a252b | 11087 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11088 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11089 | }, |
11090 | { | |
592a252b | 11091 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11092 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11093 | }, |
11094 | { | |
592a252b | 11095 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11096 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11097 | }, |
11098 | { | |
592a252b | 11099 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11100 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11101 | }, |
11102 | { | |
592a252b | 11103 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11104 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11105 | }, |
11106 | { | |
592a252b | 11107 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11108 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11109 | }, |
11110 | { | |
592a252b | 11111 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11112 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11113 | }, |
11114 | { | |
592a252b | 11115 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11116 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11117 | }, |
11118 | { | |
592a252b | 11119 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11120 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11121 | }, |
11122 | { | |
592a252b | 11123 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11124 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11125 | }, |
11126 | { | |
592a252b | 11127 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11128 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11129 | }, |
11130 | { | |
592a252b | 11131 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11132 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11133 | }, |
11134 | { | |
592a252b | 11135 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11136 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11137 | }, |
6c30d220 L |
11138 | { |
11139 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11140 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11141 | }, |
9e30b8e0 | 11142 | { |
592a252b | 11143 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11144 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11145 | }, |
bcf2684f | 11146 | { |
6c30d220 | 11147 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11148 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11149 | }, |
9e30b8e0 | 11150 | { |
6c30d220 | 11151 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11152 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11153 | }, |
11154 | { | |
592a252b | 11155 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11156 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11157 | }, |
11158 | { | |
592a252b | 11159 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11160 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11161 | }, |
11162 | { | |
592a252b | 11163 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11164 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11165 | }, |
11166 | { | |
592a252b | 11167 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11168 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11169 | }, |
11170 | { | |
592a252b | 11171 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11172 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11173 | }, |
11174 | { | |
592a252b | 11175 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11176 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11177 | }, |
11178 | { | |
592a252b | 11179 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11180 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11181 | }, |
11182 | { | |
592a252b | 11183 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11184 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11185 | }, |
11186 | { | |
592a252b | 11187 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11188 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11189 | }, |
11190 | { | |
592a252b | 11191 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11192 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11193 | }, |
11194 | { | |
592a252b | 11195 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11196 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11197 | }, |
11198 | { | |
592a252b | 11199 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11200 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11201 | }, |
11202 | { | |
592a252b | 11203 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11204 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11205 | }, |
11206 | { | |
592a252b | 11207 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11208 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11209 | }, |
53aa04a0 | 11210 | { |
592a252b | 11211 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11212 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11213 | }, |
11214 | { | |
592a252b | 11215 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11216 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11217 | }, |
11218 | { | |
592a252b | 11219 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11220 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11221 | }, |
11222 | { | |
592a252b | 11223 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11224 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11225 | }, |
9e30b8e0 | 11226 | { |
592a252b | 11227 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11228 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11229 | }, |
11230 | { | |
592a252b | 11231 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11232 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11233 | }, |
11234 | { | |
592a252b | 11235 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11236 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11237 | }, |
11238 | { | |
592a252b | 11239 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11240 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11241 | }, |
11242 | { | |
592a252b | 11243 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11244 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11245 | }, |
11246 | { | |
592a252b | 11247 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11248 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11249 | }, |
11250 | { | |
11251 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11252 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11253 | }, |
11254 | { | |
592a252b | 11255 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11256 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11257 | }, |
11258 | { | |
592a252b | 11259 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11260 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11261 | }, |
11262 | { | |
592a252b | 11263 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11264 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11265 | }, |
11266 | { | |
592a252b | 11267 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11268 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11269 | }, |
11270 | { | |
592a252b | 11271 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11272 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11273 | }, |
11274 | { | |
592a252b | 11275 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11276 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11277 | }, |
11278 | { | |
592a252b | 11279 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11280 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11281 | }, |
11282 | { | |
592a252b | 11283 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11284 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11285 | }, |
11286 | { | |
592a252b | 11287 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11288 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11289 | }, |
11290 | { | |
592a252b | 11291 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11292 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11293 | }, |
11294 | { | |
592a252b | 11295 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11296 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11297 | }, |
6c30d220 L |
11298 | { |
11299 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11300 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11301 | }, |
11302 | { | |
11303 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11304 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11305 | }, |
11306 | { | |
11307 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11308 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11309 | }, |
11310 | { | |
11311 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11312 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11313 | }, |
11314 | { | |
11315 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11316 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11317 | }, |
11318 | { | |
11319 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11320 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11321 | }, |
48521003 IT |
11322 | { |
11323 | /* VEX_W_0F38CF_P_2 */ | |
11324 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
11325 | }, | |
9e30b8e0 | 11326 | { |
592a252b | 11327 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11328 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 | 11329 | }, |
6c30d220 L |
11330 | { |
11331 | /* VEX_W_0F3A00_P_2 */ | |
11332 | { Bad_Opcode }, | |
bf890a93 | 11333 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11334 | }, |
11335 | { | |
11336 | /* VEX_W_0F3A01_P_2 */ | |
11337 | { Bad_Opcode }, | |
bf890a93 | 11338 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11339 | }, |
11340 | { | |
11341 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11342 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11343 | }, |
9e30b8e0 | 11344 | { |
592a252b | 11345 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11346 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11347 | }, |
11348 | { | |
592a252b | 11349 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11350 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11351 | }, |
11352 | { | |
592a252b | 11353 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11354 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11355 | }, |
11356 | { | |
592a252b | 11357 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11358 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11359 | }, |
11360 | { | |
592a252b | 11361 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11362 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11363 | }, |
11364 | { | |
592a252b | 11365 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11366 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11367 | }, |
11368 | { | |
592a252b | 11369 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11370 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11371 | }, |
11372 | { | |
592a252b | 11373 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11374 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11375 | }, |
11376 | { | |
592a252b | 11377 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11378 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11379 | }, |
11380 | { | |
592a252b | 11381 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11382 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11383 | }, |
11384 | { | |
592a252b | 11385 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11386 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11387 | }, |
11388 | { | |
592a252b | 11389 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11390 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11391 | }, |
11392 | { | |
592a252b | 11393 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11394 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11395 | }, |
11396 | { | |
592a252b | 11397 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11398 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11399 | }, |
11400 | { | |
592a252b | 11401 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11402 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11403 | }, |
11404 | { | |
592a252b | 11405 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11406 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11407 | }, |
11408 | { | |
592a252b | 11409 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11410 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11411 | }, |
43234a1e | 11412 | { |
1ba585e8 | 11413 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11414 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11415 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11416 | }, |
11417 | { | |
1ba585e8 | 11418 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11419 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11420 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11421 | }, |
11422 | { | |
11423 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11424 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11425 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11426 | }, |
1ba585e8 IT |
11427 | { |
11428 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11429 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11430 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11431 | }, |
6c30d220 L |
11432 | { |
11433 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11434 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11435 | }, |
11436 | { | |
11437 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11438 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11439 | }, |
9e30b8e0 | 11440 | { |
592a252b | 11441 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11442 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11443 | }, |
11444 | { | |
592a252b | 11445 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11446 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11447 | }, |
11448 | { | |
592a252b | 11449 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11450 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 | 11451 | }, |
6c30d220 L |
11452 | { |
11453 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11454 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11455 | }, |
a683cc34 | 11456 | { |
592a252b | 11457 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11458 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11459 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11460 | }, |
11461 | { | |
592a252b | 11462 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11463 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11464 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11465 | }, |
9e30b8e0 | 11466 | { |
592a252b | 11467 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11468 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11469 | }, |
11470 | { | |
592a252b | 11471 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11472 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11473 | }, |
11474 | { | |
592a252b | 11475 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11476 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11477 | }, |
9e30b8e0 | 11478 | { |
592a252b | 11479 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11480 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11481 | }, |
11482 | { | |
592a252b | 11483 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11484 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11485 | }, |
48521003 IT |
11486 | { |
11487 | /* VEX_W_0F3ACE_P_2 */ | |
11488 | { Bad_Opcode }, | |
11489 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
11490 | }, | |
11491 | { | |
11492 | /* VEX_W_0F3ACF_P_2 */ | |
11493 | { Bad_Opcode }, | |
11494 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
11495 | }, | |
9e30b8e0 | 11496 | { |
592a252b | 11497 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11498 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11499 | }, |
43234a1e L |
11500 | #define NEED_VEX_W_TABLE |
11501 | #include "i386-dis-evex.h" | |
11502 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11503 | }; |
11504 | ||
11505 | static const struct dis386 mod_table[][2] = { | |
11506 | { | |
11507 | /* MOD_8D */ | |
bf890a93 | 11508 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11509 | }, |
42164a71 L |
11510 | { |
11511 | /* MOD_C6_REG_7 */ | |
11512 | { Bad_Opcode }, | |
11513 | { RM_TABLE (RM_C6_REG_7) }, | |
11514 | }, | |
11515 | { | |
11516 | /* MOD_C7_REG_7 */ | |
11517 | { Bad_Opcode }, | |
11518 | { RM_TABLE (RM_C7_REG_7) }, | |
11519 | }, | |
4a357820 MZ |
11520 | { |
11521 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11522 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11523 | }, |
11524 | { | |
11525 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11526 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11527 | }, |
9e30b8e0 L |
11528 | { |
11529 | /* MOD_0F01_REG_0 */ | |
11530 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11531 | { RM_TABLE (RM_0F01_REG_0) }, | |
11532 | }, | |
11533 | { | |
11534 | /* MOD_0F01_REG_1 */ | |
11535 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11536 | { RM_TABLE (RM_0F01_REG_1) }, | |
11537 | }, | |
11538 | { | |
11539 | /* MOD_0F01_REG_2 */ | |
11540 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11541 | { RM_TABLE (RM_0F01_REG_2) }, | |
11542 | }, | |
11543 | { | |
11544 | /* MOD_0F01_REG_3 */ | |
11545 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11546 | { RM_TABLE (RM_0F01_REG_3) }, | |
11547 | }, | |
8eab4136 L |
11548 | { |
11549 | /* MOD_0F01_REG_5 */ | |
603555e5 | 11550 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
11551 | { RM_TABLE (RM_0F01_REG_5) }, |
11552 | }, | |
9e30b8e0 L |
11553 | { |
11554 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11555 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11556 | { RM_TABLE (RM_0F01_REG_7) }, |
11557 | }, | |
11558 | { | |
11559 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11560 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11561 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11562 | }, |
11563 | { | |
11564 | /* MOD_0F13 */ | |
507bd325 | 11565 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11566 | }, |
11567 | { | |
11568 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11569 | { "movhps", { XM, EXq }, 0 }, |
11570 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11571 | }, |
11572 | { | |
11573 | /* MOD_0F17 */ | |
507bd325 | 11574 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11575 | }, |
11576 | { | |
11577 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11578 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11579 | }, |
11580 | { | |
11581 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11582 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11583 | }, |
11584 | { | |
11585 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11586 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11587 | }, |
11588 | { | |
11589 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11590 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11591 | }, |
d7189fa5 RM |
11592 | { |
11593 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11594 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11595 | }, |
11596 | { | |
11597 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11598 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11599 | }, |
11600 | { | |
11601 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11602 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11603 | }, |
11604 | { | |
11605 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11606 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11607 | }, |
7e8b059b L |
11608 | { |
11609 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11610 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11611 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11612 | }, |
11613 | { | |
11614 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11615 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11616 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11617 | }, |
11618 | { | |
11619 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11620 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11621 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11622 | }, |
603555e5 L |
11623 | { |
11624 | /* MOD_0F1E_PREFIX_1 */ | |
11625 | { "nopQ", { Ev }, 0 }, | |
11626 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
11627 | }, | |
b844680a | 11628 | { |
92fddf8e | 11629 | /* MOD_0F24 */ |
7bb15c6f | 11630 | { Bad_Opcode }, |
bf890a93 | 11631 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11632 | }, |
11633 | { | |
92fddf8e | 11634 | /* MOD_0F26 */ |
592d1631 | 11635 | { Bad_Opcode }, |
bf890a93 | 11636 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11637 | }, |
75c135a8 L |
11638 | { |
11639 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11640 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11641 | }, |
11642 | { | |
11643 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11644 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11645 | }, |
11646 | { | |
11647 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11648 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11649 | }, |
11650 | { | |
11651 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11652 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11653 | }, |
11654 | { | |
11655 | /* MOD_0F51 */ | |
592d1631 | 11656 | { Bad_Opcode }, |
507bd325 | 11657 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11658 | }, |
b844680a | 11659 | { |
1ceb70f8 | 11660 | /* MOD_0F71_REG_2 */ |
592d1631 | 11661 | { Bad_Opcode }, |
bf890a93 | 11662 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11663 | }, |
11664 | { | |
1ceb70f8 | 11665 | /* MOD_0F71_REG_4 */ |
592d1631 | 11666 | { Bad_Opcode }, |
bf890a93 | 11667 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11668 | }, |
11669 | { | |
1ceb70f8 | 11670 | /* MOD_0F71_REG_6 */ |
592d1631 | 11671 | { Bad_Opcode }, |
bf890a93 | 11672 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11673 | }, |
11674 | { | |
1ceb70f8 | 11675 | /* MOD_0F72_REG_2 */ |
592d1631 | 11676 | { Bad_Opcode }, |
bf890a93 | 11677 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11678 | }, |
11679 | { | |
1ceb70f8 | 11680 | /* MOD_0F72_REG_4 */ |
592d1631 | 11681 | { Bad_Opcode }, |
bf890a93 | 11682 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11683 | }, |
11684 | { | |
1ceb70f8 | 11685 | /* MOD_0F72_REG_6 */ |
592d1631 | 11686 | { Bad_Opcode }, |
bf890a93 | 11687 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11688 | }, |
11689 | { | |
1ceb70f8 | 11690 | /* MOD_0F73_REG_2 */ |
592d1631 | 11691 | { Bad_Opcode }, |
bf890a93 | 11692 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11693 | }, |
11694 | { | |
1ceb70f8 | 11695 | /* MOD_0F73_REG_3 */ |
592d1631 | 11696 | { Bad_Opcode }, |
c0f3af97 L |
11697 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11698 | }, | |
11699 | { | |
11700 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11701 | { Bad_Opcode }, |
bf890a93 | 11702 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11703 | }, |
11704 | { | |
11705 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11706 | { Bad_Opcode }, |
c0f3af97 L |
11707 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11708 | }, | |
11709 | { | |
11710 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11711 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11712 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11713 | }, |
11714 | { | |
11715 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11716 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11717 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11718 | }, |
11719 | { | |
11720 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11721 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11722 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11723 | }, |
11724 | { | |
11725 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11726 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11727 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11728 | }, |
11729 | { | |
11730 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11731 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11732 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11733 | }, |
11734 | { | |
11735 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 11736 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 11737 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
11738 | }, |
11739 | { | |
11740 | /* MOD_0FAE_REG_6 */ | |
de89d0a3 IT |
11741 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, |
11742 | { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, | |
c0f3af97 L |
11743 | }, |
11744 | { | |
11745 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11746 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11747 | { RM_TABLE (RM_0FAE_REG_7) }, |
11748 | }, | |
11749 | { | |
11750 | /* MOD_0FB2 */ | |
bf890a93 | 11751 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11752 | }, |
11753 | { | |
11754 | /* MOD_0FB4 */ | |
bf890a93 | 11755 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11756 | }, |
11757 | { | |
11758 | /* MOD_0FB5 */ | |
bf890a93 | 11759 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11760 | }, |
a8484f96 L |
11761 | { |
11762 | /* MOD_0FC3 */ | |
11763 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11764 | }, | |
963f3586 IT |
11765 | { |
11766 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11767 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11768 | }, |
11769 | { | |
11770 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11771 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11772 | }, |
11773 | { | |
11774 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11775 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11776 | }, |
c0f3af97 L |
11777 | { |
11778 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11779 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11780 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11781 | }, |
11782 | { | |
11783 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11784 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11785 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11786 | }, |
11787 | { | |
11788 | /* MOD_0FD7 */ | |
592d1631 | 11789 | { Bad_Opcode }, |
bf890a93 | 11790 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11791 | }, |
11792 | { | |
11793 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11794 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11795 | }, |
11796 | { | |
11797 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11798 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11799 | }, |
11800 | { | |
11801 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11802 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11803 | }, |
603555e5 L |
11804 | { |
11805 | /* MOD_0F38F5_PREFIX_2 */ | |
11806 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11807 | }, | |
11808 | { | |
11809 | /* MOD_0F38F6_PREFIX_0 */ | |
11810 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11811 | }, | |
c0f3af97 L |
11812 | { |
11813 | /* MOD_62_32BIT */ | |
bf890a93 | 11814 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11815 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11816 | }, |
11817 | { | |
11818 | /* MOD_C4_32BIT */ | |
bf890a93 | 11819 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11820 | { VEX_C4_TABLE (VEX_0F) }, |
11821 | }, | |
11822 | { | |
11823 | /* MOD_C5_32BIT */ | |
bf890a93 | 11824 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11825 | { VEX_C5_TABLE (VEX_0F) }, |
11826 | }, | |
11827 | { | |
592a252b L |
11828 | /* MOD_VEX_0F12_PREFIX_0 */ |
11829 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11830 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11831 | }, |
11832 | { | |
592a252b L |
11833 | /* MOD_VEX_0F13 */ |
11834 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11835 | }, |
11836 | { | |
592a252b L |
11837 | /* MOD_VEX_0F16_PREFIX_0 */ |
11838 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11839 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11840 | }, |
11841 | { | |
592a252b L |
11842 | /* MOD_VEX_0F17 */ |
11843 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11844 | }, |
11845 | { | |
592a252b L |
11846 | /* MOD_VEX_0F2B */ |
11847 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11848 | }, |
ab4e4ed5 AF |
11849 | { |
11850 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11851 | { Bad_Opcode }, | |
11852 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11853 | }, | |
11854 | { | |
11855 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11856 | { Bad_Opcode }, | |
11857 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11858 | }, | |
11859 | { | |
11860 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11861 | { Bad_Opcode }, | |
11862 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11863 | }, | |
11864 | { | |
11865 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11866 | { Bad_Opcode }, | |
11867 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11868 | }, | |
11869 | { | |
11870 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11871 | { Bad_Opcode }, | |
11872 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11873 | }, | |
11874 | { | |
11875 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11876 | { Bad_Opcode }, | |
11877 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11878 | }, | |
11879 | { | |
11880 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11881 | { Bad_Opcode }, | |
11882 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11883 | }, | |
11884 | { | |
11885 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11886 | { Bad_Opcode }, | |
11887 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11888 | }, | |
11889 | { | |
11890 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11891 | { Bad_Opcode }, | |
11892 | { "knotw", { MaskG, MaskR }, 0 }, | |
11893 | }, | |
11894 | { | |
11895 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11896 | { Bad_Opcode }, | |
11897 | { "knotq", { MaskG, MaskR }, 0 }, | |
11898 | }, | |
11899 | { | |
11900 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11901 | { Bad_Opcode }, | |
11902 | { "knotb", { MaskG, MaskR }, 0 }, | |
11903 | }, | |
11904 | { | |
11905 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11906 | { Bad_Opcode }, | |
11907 | { "knotd", { MaskG, MaskR }, 0 }, | |
11908 | }, | |
11909 | { | |
11910 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11911 | { Bad_Opcode }, | |
11912 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11913 | }, | |
11914 | { | |
11915 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11916 | { Bad_Opcode }, | |
11917 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11918 | }, | |
11919 | { | |
11920 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11921 | { Bad_Opcode }, | |
11922 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11923 | }, | |
11924 | { | |
11925 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11926 | { Bad_Opcode }, | |
11927 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11928 | }, | |
11929 | { | |
11930 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11931 | { Bad_Opcode }, | |
11932 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11933 | }, | |
11934 | { | |
11935 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11936 | { Bad_Opcode }, | |
11937 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11938 | }, | |
11939 | { | |
11940 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11941 | { Bad_Opcode }, | |
11942 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11943 | }, | |
11944 | { | |
11945 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11946 | { Bad_Opcode }, | |
11947 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11948 | }, | |
11949 | { | |
11950 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11951 | { Bad_Opcode }, | |
11952 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11953 | }, | |
11954 | { | |
11955 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11956 | { Bad_Opcode }, | |
11957 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11958 | }, | |
11959 | { | |
11960 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11961 | { Bad_Opcode }, | |
11962 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11963 | }, | |
11964 | { | |
11965 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11966 | { Bad_Opcode }, | |
11967 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11968 | }, | |
11969 | { | |
11970 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11971 | { Bad_Opcode }, | |
11972 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11973 | }, | |
11974 | { | |
11975 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11976 | { Bad_Opcode }, | |
11977 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11978 | }, | |
11979 | { | |
11980 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11981 | { Bad_Opcode }, | |
11982 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11983 | }, | |
11984 | { | |
11985 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11986 | { Bad_Opcode }, | |
11987 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11988 | }, | |
11989 | { | |
11990 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11991 | { Bad_Opcode }, | |
11992 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11993 | }, | |
11994 | { | |
11995 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11996 | { Bad_Opcode }, | |
11997 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11998 | }, | |
11999 | { | |
12000 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
12001 | { Bad_Opcode }, | |
12002 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
12003 | }, | |
c0f3af97 | 12004 | { |
592a252b | 12005 | /* MOD_VEX_0F50 */ |
592d1631 | 12006 | { Bad_Opcode }, |
592a252b | 12007 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
12008 | }, |
12009 | { | |
592a252b | 12010 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12011 | { Bad_Opcode }, |
592a252b | 12012 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12013 | }, |
12014 | { | |
592a252b | 12015 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12016 | { Bad_Opcode }, |
592a252b | 12017 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12018 | }, |
12019 | { | |
592a252b | 12020 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12021 | { Bad_Opcode }, |
592a252b | 12022 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12023 | }, |
12024 | { | |
592a252b | 12025 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12026 | { Bad_Opcode }, |
592a252b | 12027 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12028 | }, |
d8faab4e | 12029 | { |
592a252b | 12030 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12031 | { Bad_Opcode }, |
592a252b | 12032 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12033 | }, |
12034 | { | |
592a252b | 12035 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12036 | { Bad_Opcode }, |
592a252b | 12037 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12038 | }, |
876d4bfa | 12039 | { |
592a252b | 12040 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12041 | { Bad_Opcode }, |
592a252b | 12042 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12043 | }, |
12044 | { | |
592a252b | 12045 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12046 | { Bad_Opcode }, |
592a252b | 12047 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12048 | }, |
12049 | { | |
592a252b | 12050 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12051 | { Bad_Opcode }, |
592a252b | 12052 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12053 | }, |
12054 | { | |
592a252b | 12055 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12056 | { Bad_Opcode }, |
592a252b | 12057 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12058 | }, |
ab4e4ed5 AF |
12059 | { |
12060 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12061 | { "kmovw", { Ew, MaskG }, 0 }, | |
12062 | { Bad_Opcode }, | |
12063 | }, | |
12064 | { | |
12065 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12066 | { "kmovq", { Eq, MaskG }, 0 }, | |
12067 | { Bad_Opcode }, | |
12068 | }, | |
12069 | { | |
12070 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12071 | { "kmovb", { Eb, MaskG }, 0 }, | |
12072 | { Bad_Opcode }, | |
12073 | }, | |
12074 | { | |
12075 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12076 | { "kmovd", { Ed, MaskG }, 0 }, | |
12077 | { Bad_Opcode }, | |
12078 | }, | |
12079 | { | |
12080 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12081 | { Bad_Opcode }, | |
12082 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12083 | }, | |
12084 | { | |
12085 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12086 | { Bad_Opcode }, | |
12087 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12088 | }, | |
12089 | { | |
12090 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12091 | { Bad_Opcode }, | |
12092 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12093 | }, | |
12094 | { | |
12095 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12096 | { Bad_Opcode }, | |
12097 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12098 | }, | |
12099 | { | |
12100 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12101 | { Bad_Opcode }, | |
12102 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12103 | }, | |
12104 | { | |
12105 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12106 | { Bad_Opcode }, | |
12107 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12108 | }, | |
12109 | { | |
12110 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12111 | { Bad_Opcode }, | |
12112 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12113 | }, | |
12114 | { | |
12115 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12116 | { Bad_Opcode }, | |
12117 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12118 | }, | |
12119 | { | |
12120 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12121 | { Bad_Opcode }, | |
12122 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12123 | }, | |
12124 | { | |
12125 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12126 | { Bad_Opcode }, | |
12127 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12128 | }, | |
12129 | { | |
12130 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12131 | { Bad_Opcode }, | |
12132 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12133 | }, | |
12134 | { | |
12135 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12136 | { Bad_Opcode }, | |
12137 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12138 | }, | |
12139 | { | |
12140 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12141 | { Bad_Opcode }, | |
12142 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12143 | }, | |
12144 | { | |
12145 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12146 | { Bad_Opcode }, | |
12147 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12148 | }, | |
12149 | { | |
12150 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12151 | { Bad_Opcode }, | |
12152 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12153 | }, | |
12154 | { | |
12155 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12156 | { Bad_Opcode }, | |
12157 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12158 | }, | |
876d4bfa | 12159 | { |
592a252b L |
12160 | /* MOD_VEX_0FAE_REG_2 */ |
12161 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12162 | }, |
bbedc832 | 12163 | { |
592a252b L |
12164 | /* MOD_VEX_0FAE_REG_3 */ |
12165 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12166 | }, |
144c41d9 | 12167 | { |
592a252b | 12168 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12169 | { Bad_Opcode }, |
6c30d220 | 12170 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12171 | }, |
1afd85e3 | 12172 | { |
592a252b L |
12173 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12174 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12175 | }, |
12176 | { | |
592a252b L |
12177 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12178 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12179 | }, |
75c135a8 | 12180 | { |
592a252b L |
12181 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12182 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12183 | }, |
1afd85e3 | 12184 | { |
592a252b | 12185 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12186 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12187 | }, |
75c135a8 | 12188 | { |
592a252b L |
12189 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12190 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12191 | }, |
1afd85e3 | 12192 | { |
592a252b L |
12193 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12194 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12195 | }, |
12196 | { | |
592a252b L |
12197 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12198 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12199 | }, |
12200 | { | |
592a252b L |
12201 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12202 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12203 | }, |
6c30d220 L |
12204 | { |
12205 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12206 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12207 | }, | |
12208 | { | |
12209 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12210 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12211 | }, |
12212 | { | |
12213 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12214 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12215 | }, |
ab4e4ed5 AF |
12216 | { |
12217 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12218 | { Bad_Opcode }, | |
12219 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12220 | }, | |
12221 | { | |
12222 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12223 | { Bad_Opcode }, | |
12224 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12225 | }, | |
12226 | { | |
12227 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12228 | { Bad_Opcode }, | |
12229 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12230 | }, | |
12231 | { | |
12232 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12233 | { Bad_Opcode }, | |
12234 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12235 | }, | |
12236 | { | |
12237 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12238 | { Bad_Opcode }, | |
12239 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12240 | }, | |
12241 | { | |
12242 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12243 | { Bad_Opcode }, | |
12244 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12245 | }, | |
12246 | { | |
12247 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12248 | { Bad_Opcode }, | |
12249 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12250 | }, | |
12251 | { | |
12252 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12253 | { Bad_Opcode }, | |
12254 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12255 | }, | |
43234a1e L |
12256 | #define NEED_MOD_TABLE |
12257 | #include "i386-dis-evex.h" | |
12258 | #undef NEED_MOD_TABLE | |
b844680a L |
12259 | }; |
12260 | ||
1ceb70f8 | 12261 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12262 | { |
12263 | /* RM_C6_REG_7 */ | |
bf890a93 | 12264 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12265 | }, |
12266 | { | |
12267 | /* RM_C7_REG_7 */ | |
bf890a93 | 12268 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12269 | }, |
b844680a | 12270 | { |
1ceb70f8 | 12271 | /* RM_0F01_REG_0 */ |
592d1631 | 12272 | { Bad_Opcode }, |
bf890a93 IT |
12273 | { "vmcall", { Skip_MODRM }, 0 }, |
12274 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12275 | { "vmresume", { Skip_MODRM }, 0 }, | |
12276 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 12277 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
12278 | }, |
12279 | { | |
1ceb70f8 | 12280 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12281 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12282 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12283 | { "clac", { Skip_MODRM }, 0 }, | |
12284 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12285 | { Bad_Opcode }, |
12286 | { Bad_Opcode }, | |
12287 | { Bad_Opcode }, | |
bf890a93 | 12288 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12289 | }, |
475a2301 L |
12290 | { |
12291 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12292 | { "xgetbv", { Skip_MODRM }, 0 }, |
12293 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12294 | { Bad_Opcode }, |
12295 | { Bad_Opcode }, | |
bf890a93 IT |
12296 | { "vmfunc", { Skip_MODRM }, 0 }, |
12297 | { "xend", { Skip_MODRM }, 0 }, | |
12298 | { "xtest", { Skip_MODRM }, 0 }, | |
12299 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12300 | }, |
b844680a | 12301 | { |
1ceb70f8 | 12302 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12303 | { "vmrun", { Skip_MODRM }, 0 }, |
12304 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12305 | { "vmload", { Skip_MODRM }, 0 }, | |
12306 | { "vmsave", { Skip_MODRM }, 0 }, | |
12307 | { "stgi", { Skip_MODRM }, 0 }, | |
12308 | { "clgi", { Skip_MODRM }, 0 }, | |
12309 | { "skinit", { Skip_MODRM }, 0 }, | |
12310 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12311 | }, |
8eab4136 L |
12312 | { |
12313 | /* RM_0F01_REG_5 */ | |
2234eee6 | 12314 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 12315 | { Bad_Opcode }, |
603555e5 | 12316 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
12317 | { Bad_Opcode }, |
12318 | { Bad_Opcode }, | |
12319 | { Bad_Opcode }, | |
12320 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12321 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12322 | }, | |
4e7d34a6 | 12323 | { |
1ceb70f8 | 12324 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12325 | { "swapgs", { Skip_MODRM }, 0 }, |
12326 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12327 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12328 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12329 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 12330 | }, |
603555e5 L |
12331 | { |
12332 | /* RM_0F1E_MOD_3_REG_7 */ | |
12333 | { "nopQ", { Ev }, 0 }, | |
12334 | { "nopQ", { Ev }, 0 }, | |
12335 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
12336 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
12337 | { "nopQ", { Ev }, 0 }, | |
12338 | { "nopQ", { Ev }, 0 }, | |
12339 | { "nopQ", { Ev }, 0 }, | |
12340 | { "nopQ", { Ev }, 0 }, | |
12341 | }, | |
b844680a | 12342 | { |
1ceb70f8 | 12343 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12344 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12345 | }, |
bbedc832 | 12346 | { |
1ceb70f8 | 12347 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12348 | { "sfence", { Skip_MODRM }, 0 }, |
12349 | ||
144c41d9 | 12350 | }, |
b844680a L |
12351 | }; |
12352 | ||
c608c12e AM |
12353 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12354 | ||
f16cd0d5 L |
12355 | /* We use the high bit to indicate different name for the same |
12356 | prefix. */ | |
f16cd0d5 | 12357 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12358 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12359 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12360 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 12361 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
12362 | |
12363 | static int | |
26ca5450 | 12364 | ckprefix (void) |
252b5132 | 12365 | { |
f16cd0d5 | 12366 | int newrex, i, length; |
52b15da3 | 12367 | rex = 0; |
c0f3af97 | 12368 | rex_ignored = 0; |
252b5132 | 12369 | prefixes = 0; |
7d421014 | 12370 | used_prefixes = 0; |
52b15da3 | 12371 | rex_used = 0; |
f16cd0d5 L |
12372 | last_lock_prefix = -1; |
12373 | last_repz_prefix = -1; | |
12374 | last_repnz_prefix = -1; | |
12375 | last_data_prefix = -1; | |
12376 | last_addr_prefix = -1; | |
12377 | last_rex_prefix = -1; | |
12378 | last_seg_prefix = -1; | |
d9949a36 | 12379 | fwait_prefix = -1; |
285ca992 | 12380 | active_seg_prefix = 0; |
f310f33d L |
12381 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12382 | all_prefixes[i] = 0; | |
12383 | i = 0; | |
f16cd0d5 L |
12384 | length = 0; |
12385 | /* The maximum instruction length is 15bytes. */ | |
12386 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12387 | { |
12388 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12389 | newrex = 0; |
252b5132 RH |
12390 | switch (*codep) |
12391 | { | |
52b15da3 JH |
12392 | /* REX prefixes family. */ |
12393 | case 0x40: | |
12394 | case 0x41: | |
12395 | case 0x42: | |
12396 | case 0x43: | |
12397 | case 0x44: | |
12398 | case 0x45: | |
12399 | case 0x46: | |
12400 | case 0x47: | |
12401 | case 0x48: | |
12402 | case 0x49: | |
12403 | case 0x4a: | |
12404 | case 0x4b: | |
12405 | case 0x4c: | |
12406 | case 0x4d: | |
12407 | case 0x4e: | |
12408 | case 0x4f: | |
f16cd0d5 L |
12409 | if (address_mode == mode_64bit) |
12410 | newrex = *codep; | |
12411 | else | |
12412 | return 1; | |
12413 | last_rex_prefix = i; | |
52b15da3 | 12414 | break; |
252b5132 RH |
12415 | case 0xf3: |
12416 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12417 | last_repz_prefix = i; |
252b5132 RH |
12418 | break; |
12419 | case 0xf2: | |
12420 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12421 | last_repnz_prefix = i; |
252b5132 RH |
12422 | break; |
12423 | case 0xf0: | |
12424 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12425 | last_lock_prefix = i; |
252b5132 RH |
12426 | break; |
12427 | case 0x2e: | |
12428 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12429 | last_seg_prefix = i; |
285ca992 | 12430 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12431 | break; |
12432 | case 0x36: | |
12433 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12434 | last_seg_prefix = i; |
285ca992 | 12435 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12436 | break; |
12437 | case 0x3e: | |
12438 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12439 | last_seg_prefix = i; |
285ca992 | 12440 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12441 | break; |
12442 | case 0x26: | |
12443 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12444 | last_seg_prefix = i; |
285ca992 | 12445 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12446 | break; |
12447 | case 0x64: | |
12448 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12449 | last_seg_prefix = i; |
285ca992 | 12450 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12451 | break; |
12452 | case 0x65: | |
12453 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12454 | last_seg_prefix = i; |
285ca992 | 12455 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12456 | break; |
12457 | case 0x66: | |
12458 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12459 | last_data_prefix = i; |
252b5132 RH |
12460 | break; |
12461 | case 0x67: | |
12462 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12463 | last_addr_prefix = i; |
252b5132 | 12464 | break; |
5076851f | 12465 | case FWAIT_OPCODE: |
252b5132 RH |
12466 | /* fwait is really an instruction. If there are prefixes |
12467 | before the fwait, they belong to the fwait, *not* to the | |
12468 | following instruction. */ | |
d9949a36 | 12469 | fwait_prefix = i; |
3e7d61b2 | 12470 | if (prefixes || rex) |
252b5132 RH |
12471 | { |
12472 | prefixes |= PREFIX_FWAIT; | |
12473 | codep++; | |
6c067bbb RM |
12474 | /* This ensures that the previous REX prefixes are noticed |
12475 | as unused prefixes, as in the return case below. */ | |
12476 | rex_used = rex; | |
f16cd0d5 | 12477 | return 1; |
252b5132 RH |
12478 | } |
12479 | prefixes = PREFIX_FWAIT; | |
12480 | break; | |
12481 | default: | |
f16cd0d5 | 12482 | return 1; |
252b5132 | 12483 | } |
52b15da3 JH |
12484 | /* Rex is ignored when followed by another prefix. */ |
12485 | if (rex) | |
12486 | { | |
3e7d61b2 | 12487 | rex_used = rex; |
f16cd0d5 | 12488 | return 1; |
52b15da3 | 12489 | } |
f16cd0d5 | 12490 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 12491 | all_prefixes[i++] = *codep; |
52b15da3 | 12492 | rex = newrex; |
252b5132 | 12493 | codep++; |
f16cd0d5 L |
12494 | length++; |
12495 | } | |
12496 | return 0; | |
12497 | } | |
12498 | ||
7d421014 ILT |
12499 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12500 | prefix byte. */ | |
12501 | ||
12502 | static const char * | |
26ca5450 | 12503 | prefix_name (int pref, int sizeflag) |
7d421014 | 12504 | { |
0003779b L |
12505 | static const char *rexes [16] = |
12506 | { | |
12507 | "rex", /* 0x40 */ | |
12508 | "rex.B", /* 0x41 */ | |
12509 | "rex.X", /* 0x42 */ | |
12510 | "rex.XB", /* 0x43 */ | |
12511 | "rex.R", /* 0x44 */ | |
12512 | "rex.RB", /* 0x45 */ | |
12513 | "rex.RX", /* 0x46 */ | |
12514 | "rex.RXB", /* 0x47 */ | |
12515 | "rex.W", /* 0x48 */ | |
12516 | "rex.WB", /* 0x49 */ | |
12517 | "rex.WX", /* 0x4a */ | |
12518 | "rex.WXB", /* 0x4b */ | |
12519 | "rex.WR", /* 0x4c */ | |
12520 | "rex.WRB", /* 0x4d */ | |
12521 | "rex.WRX", /* 0x4e */ | |
12522 | "rex.WRXB", /* 0x4f */ | |
12523 | }; | |
12524 | ||
7d421014 ILT |
12525 | switch (pref) |
12526 | { | |
52b15da3 JH |
12527 | /* REX prefixes family. */ |
12528 | case 0x40: | |
52b15da3 | 12529 | case 0x41: |
52b15da3 | 12530 | case 0x42: |
52b15da3 | 12531 | case 0x43: |
52b15da3 | 12532 | case 0x44: |
52b15da3 | 12533 | case 0x45: |
52b15da3 | 12534 | case 0x46: |
52b15da3 | 12535 | case 0x47: |
52b15da3 | 12536 | case 0x48: |
52b15da3 | 12537 | case 0x49: |
52b15da3 | 12538 | case 0x4a: |
52b15da3 | 12539 | case 0x4b: |
52b15da3 | 12540 | case 0x4c: |
52b15da3 | 12541 | case 0x4d: |
52b15da3 | 12542 | case 0x4e: |
52b15da3 | 12543 | case 0x4f: |
0003779b | 12544 | return rexes [pref - 0x40]; |
7d421014 ILT |
12545 | case 0xf3: |
12546 | return "repz"; | |
12547 | case 0xf2: | |
12548 | return "repnz"; | |
12549 | case 0xf0: | |
12550 | return "lock"; | |
12551 | case 0x2e: | |
12552 | return "cs"; | |
12553 | case 0x36: | |
12554 | return "ss"; | |
12555 | case 0x3e: | |
12556 | return "ds"; | |
12557 | case 0x26: | |
12558 | return "es"; | |
12559 | case 0x64: | |
12560 | return "fs"; | |
12561 | case 0x65: | |
12562 | return "gs"; | |
12563 | case 0x66: | |
12564 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12565 | case 0x67: | |
cb712a9e | 12566 | if (address_mode == mode_64bit) |
db6eb5be | 12567 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12568 | else |
2888cb7a | 12569 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12570 | case FWAIT_OPCODE: |
12571 | return "fwait"; | |
f16cd0d5 L |
12572 | case REP_PREFIX: |
12573 | return "rep"; | |
42164a71 L |
12574 | case XACQUIRE_PREFIX: |
12575 | return "xacquire"; | |
12576 | case XRELEASE_PREFIX: | |
12577 | return "xrelease"; | |
7e8b059b L |
12578 | case BND_PREFIX: |
12579 | return "bnd"; | |
04ef582a L |
12580 | case NOTRACK_PREFIX: |
12581 | return "notrack"; | |
7d421014 ILT |
12582 | default: |
12583 | return NULL; | |
12584 | } | |
12585 | } | |
12586 | ||
ce518a5f L |
12587 | static char op_out[MAX_OPERANDS][100]; |
12588 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12589 | static int two_source_ops; |
ce518a5f L |
12590 | static bfd_vma op_address[MAX_OPERANDS]; |
12591 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12592 | static bfd_vma start_pc; |
ce518a5f | 12593 | |
252b5132 RH |
12594 | /* |
12595 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12596 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12597 | * section of the "Virtual 8086 Mode" chapter.) | |
12598 | * 'pc' should be the address of this instruction, it will | |
12599 | * be used to print the target address if this is a relative jump or call | |
12600 | * The function returns the length of this instruction in bytes. | |
12601 | */ | |
12602 | ||
252b5132 | 12603 | static char intel_syntax; |
9d141669 | 12604 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12605 | static char open_char; |
12606 | static char close_char; | |
12607 | static char separator_char; | |
12608 | static char scale_char; | |
12609 | ||
5db04b09 L |
12610 | enum x86_64_isa |
12611 | { | |
12612 | amd64 = 0, | |
12613 | intel64 | |
12614 | }; | |
12615 | ||
12616 | static enum x86_64_isa isa64; | |
12617 | ||
e396998b AM |
12618 | /* Here for backwards compatibility. When gdb stops using |
12619 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12620 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12621 | int |
26ca5450 | 12622 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12623 | { |
12624 | intel_syntax = 0; | |
e396998b AM |
12625 | |
12626 | return print_insn (pc, info); | |
252b5132 RH |
12627 | } |
12628 | ||
12629 | int | |
26ca5450 | 12630 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12631 | { |
12632 | intel_syntax = 1; | |
e396998b AM |
12633 | |
12634 | return print_insn (pc, info); | |
252b5132 RH |
12635 | } |
12636 | ||
e396998b | 12637 | int |
26ca5450 | 12638 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12639 | { |
12640 | intel_syntax = -1; | |
12641 | ||
12642 | return print_insn (pc, info); | |
12643 | } | |
12644 | ||
f59a29b9 L |
12645 | void |
12646 | print_i386_disassembler_options (FILE *stream) | |
12647 | { | |
12648 | fprintf (stream, _("\n\ | |
12649 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12650 | with the -M switch (multiple options should be separated by commas):\n")); | |
12651 | ||
12652 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12653 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12654 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12655 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12656 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12657 | fprintf (stream, _(" att-mnemonic\n" |
12658 | " Display instruction in AT&T mnemonic\n")); | |
12659 | fprintf (stream, _(" intel-mnemonic\n" | |
12660 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12661 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12662 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12663 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12664 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12665 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12666 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12667 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12668 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12669 | } |
12670 | ||
592d1631 | 12671 | /* Bad opcode. */ |
bf890a93 | 12672 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12673 | |
b844680a L |
12674 | /* Get a pointer to struct dis386 with a valid name. */ |
12675 | ||
12676 | static const struct dis386 * | |
8bb15339 | 12677 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12678 | { |
91d6fa6a | 12679 | int vindex, vex_table_index; |
b844680a L |
12680 | |
12681 | if (dp->name != NULL) | |
12682 | return dp; | |
12683 | ||
12684 | switch (dp->op[0].bytemode) | |
12685 | { | |
1ceb70f8 L |
12686 | case USE_REG_TABLE: |
12687 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12688 | break; | |
12689 | ||
12690 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12691 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12692 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12693 | break; |
12694 | ||
12695 | case USE_RM_TABLE: | |
12696 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12697 | break; |
12698 | ||
4e7d34a6 | 12699 | case USE_PREFIX_TABLE: |
c0f3af97 | 12700 | if (need_vex) |
b844680a | 12701 | { |
c0f3af97 L |
12702 | /* The prefix in VEX is implicit. */ |
12703 | switch (vex.prefix) | |
12704 | { | |
12705 | case 0: | |
91d6fa6a | 12706 | vindex = 0; |
c0f3af97 L |
12707 | break; |
12708 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12709 | vindex = 1; |
c0f3af97 L |
12710 | break; |
12711 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12712 | vindex = 2; |
c0f3af97 L |
12713 | break; |
12714 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12715 | vindex = 3; |
c0f3af97 L |
12716 | break; |
12717 | default: | |
12718 | abort (); | |
12719 | break; | |
12720 | } | |
b844680a | 12721 | } |
7bb15c6f | 12722 | else |
b844680a | 12723 | { |
285ca992 L |
12724 | int last_prefix = -1; |
12725 | int prefix = 0; | |
91d6fa6a | 12726 | vindex = 0; |
285ca992 L |
12727 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12728 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12729 | last one wins. */ | |
12730 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12731 | { |
285ca992 | 12732 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12733 | { |
285ca992 L |
12734 | vindex = 1; |
12735 | prefix = PREFIX_REPZ; | |
12736 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12737 | } |
12738 | else | |
b844680a | 12739 | { |
285ca992 L |
12740 | vindex = 3; |
12741 | prefix = PREFIX_REPNZ; | |
12742 | last_prefix = last_repnz_prefix; | |
b844680a | 12743 | } |
285ca992 | 12744 | |
507bd325 L |
12745 | /* Check if prefix should be ignored. */ |
12746 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12747 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12748 | & prefix) != 0) | |
285ca992 L |
12749 | vindex = 0; |
12750 | } | |
12751 | ||
12752 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12753 | { | |
12754 | vindex = 2; | |
12755 | prefix = PREFIX_DATA; | |
12756 | last_prefix = last_data_prefix; | |
12757 | } | |
12758 | ||
12759 | if (vindex != 0) | |
12760 | { | |
12761 | used_prefixes |= prefix; | |
12762 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12763 | } |
12764 | } | |
91d6fa6a | 12765 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12766 | break; |
12767 | ||
4e7d34a6 | 12768 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12769 | vindex = address_mode == mode_64bit ? 1 : 0; |
12770 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12771 | break; |
12772 | ||
4e7d34a6 | 12773 | case USE_3BYTE_TABLE: |
8bb15339 | 12774 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12775 | vindex = *codep++; |
12776 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12777 | end_codep = codep; |
8bb15339 L |
12778 | modrm.mod = (*codep >> 6) & 3; |
12779 | modrm.reg = (*codep >> 3) & 7; | |
12780 | modrm.rm = *codep & 7; | |
12781 | break; | |
12782 | ||
c0f3af97 L |
12783 | case USE_VEX_LEN_TABLE: |
12784 | if (!need_vex) | |
12785 | abort (); | |
12786 | ||
12787 | switch (vex.length) | |
12788 | { | |
12789 | case 128: | |
91d6fa6a | 12790 | vindex = 0; |
c0f3af97 L |
12791 | break; |
12792 | case 256: | |
91d6fa6a | 12793 | vindex = 1; |
c0f3af97 L |
12794 | break; |
12795 | default: | |
12796 | abort (); | |
12797 | break; | |
12798 | } | |
12799 | ||
91d6fa6a | 12800 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12801 | break; |
12802 | ||
f88c9eb0 SP |
12803 | case USE_XOP_8F_TABLE: |
12804 | FETCH_DATA (info, codep + 3); | |
12805 | /* All bits in the REX prefix are ignored. */ | |
12806 | rex_ignored = rex; | |
12807 | rex = ~(*codep >> 5) & 0x7; | |
12808 | ||
12809 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12810 | switch ((*codep & 0x1f)) | |
12811 | { | |
12812 | default: | |
f07af43e L |
12813 | dp = &bad_opcode; |
12814 | return dp; | |
5dd85c99 SP |
12815 | case 0x8: |
12816 | vex_table_index = XOP_08; | |
12817 | break; | |
f88c9eb0 SP |
12818 | case 0x9: |
12819 | vex_table_index = XOP_09; | |
12820 | break; | |
12821 | case 0xa: | |
12822 | vex_table_index = XOP_0A; | |
12823 | break; | |
12824 | } | |
12825 | codep++; | |
12826 | vex.w = *codep & 0x80; | |
12827 | if (vex.w && address_mode == mode_64bit) | |
12828 | rex |= REX_W; | |
12829 | ||
12830 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12831 | if (address_mode != mode_64bit) |
f07af43e | 12832 | { |
abfcb414 AP |
12833 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12834 | rex &= ~REX_B; | |
f07af43e | 12835 | } |
f88c9eb0 SP |
12836 | |
12837 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12838 | switch ((*codep & 0x3)) | |
12839 | { | |
12840 | case 0: | |
f88c9eb0 SP |
12841 | break; |
12842 | case 1: | |
12843 | vex.prefix = DATA_PREFIX_OPCODE; | |
12844 | break; | |
12845 | case 2: | |
12846 | vex.prefix = REPE_PREFIX_OPCODE; | |
12847 | break; | |
12848 | case 3: | |
12849 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12850 | break; | |
12851 | } | |
12852 | need_vex = 1; | |
12853 | need_vex_reg = 1; | |
12854 | codep++; | |
91d6fa6a NC |
12855 | vindex = *codep++; |
12856 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12857 | |
285ca992 | 12858 | end_codep = codep; |
c48244a5 SP |
12859 | FETCH_DATA (info, codep + 1); |
12860 | modrm.mod = (*codep >> 6) & 3; | |
12861 | modrm.reg = (*codep >> 3) & 7; | |
12862 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12863 | break; |
12864 | ||
c0f3af97 | 12865 | case USE_VEX_C4_TABLE: |
43234a1e | 12866 | /* VEX prefix. */ |
c0f3af97 L |
12867 | FETCH_DATA (info, codep + 3); |
12868 | /* All bits in the REX prefix are ignored. */ | |
12869 | rex_ignored = rex; | |
12870 | rex = ~(*codep >> 5) & 0x7; | |
12871 | switch ((*codep & 0x1f)) | |
12872 | { | |
12873 | default: | |
f07af43e L |
12874 | dp = &bad_opcode; |
12875 | return dp; | |
c0f3af97 | 12876 | case 0x1: |
f88c9eb0 | 12877 | vex_table_index = VEX_0F; |
c0f3af97 L |
12878 | break; |
12879 | case 0x2: | |
f88c9eb0 | 12880 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12881 | break; |
12882 | case 0x3: | |
f88c9eb0 | 12883 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12884 | break; |
12885 | } | |
12886 | codep++; | |
12887 | vex.w = *codep & 0x80; | |
9889cbb1 | 12888 | if (address_mode == mode_64bit) |
f07af43e | 12889 | { |
9889cbb1 L |
12890 | if (vex.w) |
12891 | rex |= REX_W; | |
9889cbb1 L |
12892 | } |
12893 | else | |
12894 | { | |
12895 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12896 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12897 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12898 | rex = 0; |
f07af43e | 12899 | } |
5f847646 | 12900 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12901 | vex.length = (*codep & 0x4) ? 256 : 128; |
12902 | switch ((*codep & 0x3)) | |
12903 | { | |
12904 | case 0: | |
c0f3af97 L |
12905 | break; |
12906 | case 1: | |
12907 | vex.prefix = DATA_PREFIX_OPCODE; | |
12908 | break; | |
12909 | case 2: | |
12910 | vex.prefix = REPE_PREFIX_OPCODE; | |
12911 | break; | |
12912 | case 3: | |
12913 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12914 | break; | |
12915 | } | |
12916 | need_vex = 1; | |
12917 | need_vex_reg = 1; | |
12918 | codep++; | |
91d6fa6a NC |
12919 | vindex = *codep++; |
12920 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12921 | end_codep = codep; |
53c4d625 JB |
12922 | /* There is no MODRM byte for VEX0F 77. */ |
12923 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12924 | { |
12925 | FETCH_DATA (info, codep + 1); | |
12926 | modrm.mod = (*codep >> 6) & 3; | |
12927 | modrm.reg = (*codep >> 3) & 7; | |
12928 | modrm.rm = *codep & 7; | |
12929 | } | |
12930 | break; | |
12931 | ||
12932 | case USE_VEX_C5_TABLE: | |
43234a1e | 12933 | /* VEX prefix. */ |
c0f3af97 L |
12934 | FETCH_DATA (info, codep + 2); |
12935 | /* All bits in the REX prefix are ignored. */ | |
12936 | rex_ignored = rex; | |
12937 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12938 | ||
9889cbb1 L |
12939 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12940 | VEX.vvvv is 1. */ | |
c0f3af97 | 12941 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12942 | vex.length = (*codep & 0x4) ? 256 : 128; |
12943 | switch ((*codep & 0x3)) | |
12944 | { | |
12945 | case 0: | |
c0f3af97 L |
12946 | break; |
12947 | case 1: | |
12948 | vex.prefix = DATA_PREFIX_OPCODE; | |
12949 | break; | |
12950 | case 2: | |
12951 | vex.prefix = REPE_PREFIX_OPCODE; | |
12952 | break; | |
12953 | case 3: | |
12954 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12955 | break; | |
12956 | } | |
12957 | need_vex = 1; | |
12958 | need_vex_reg = 1; | |
12959 | codep++; | |
91d6fa6a NC |
12960 | vindex = *codep++; |
12961 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12962 | end_codep = codep; |
53c4d625 JB |
12963 | /* There is no MODRM byte for VEX 77. */ |
12964 | if (vindex != 0x77) | |
c0f3af97 L |
12965 | { |
12966 | FETCH_DATA (info, codep + 1); | |
12967 | modrm.mod = (*codep >> 6) & 3; | |
12968 | modrm.reg = (*codep >> 3) & 7; | |
12969 | modrm.rm = *codep & 7; | |
12970 | } | |
12971 | break; | |
12972 | ||
9e30b8e0 L |
12973 | case USE_VEX_W_TABLE: |
12974 | if (!need_vex) | |
12975 | abort (); | |
12976 | ||
12977 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12978 | break; | |
12979 | ||
43234a1e L |
12980 | case USE_EVEX_TABLE: |
12981 | two_source_ops = 0; | |
12982 | /* EVEX prefix. */ | |
12983 | vex.evex = 1; | |
12984 | FETCH_DATA (info, codep + 4); | |
12985 | /* All bits in the REX prefix are ignored. */ | |
12986 | rex_ignored = rex; | |
12987 | /* The first byte after 0x62. */ | |
12988 | rex = ~(*codep >> 5) & 0x7; | |
12989 | vex.r = *codep & 0x10; | |
12990 | switch ((*codep & 0xf)) | |
12991 | { | |
12992 | default: | |
12993 | return &bad_opcode; | |
12994 | case 0x1: | |
12995 | vex_table_index = EVEX_0F; | |
12996 | break; | |
12997 | case 0x2: | |
12998 | vex_table_index = EVEX_0F38; | |
12999 | break; | |
13000 | case 0x3: | |
13001 | vex_table_index = EVEX_0F3A; | |
13002 | break; | |
13003 | } | |
13004 | ||
13005 | /* The second byte after 0x62. */ | |
13006 | codep++; | |
13007 | vex.w = *codep & 0x80; | |
13008 | if (vex.w && address_mode == mode_64bit) | |
13009 | rex |= REX_W; | |
13010 | ||
13011 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
13012 | |
13013 | /* The U bit. */ | |
13014 | if (!(*codep & 0x4)) | |
13015 | return &bad_opcode; | |
13016 | ||
13017 | switch ((*codep & 0x3)) | |
13018 | { | |
13019 | case 0: | |
43234a1e L |
13020 | break; |
13021 | case 1: | |
13022 | vex.prefix = DATA_PREFIX_OPCODE; | |
13023 | break; | |
13024 | case 2: | |
13025 | vex.prefix = REPE_PREFIX_OPCODE; | |
13026 | break; | |
13027 | case 3: | |
13028 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13029 | break; | |
13030 | } | |
13031 | ||
13032 | /* The third byte after 0x62. */ | |
13033 | codep++; | |
13034 | ||
13035 | /* Remember the static rounding bits. */ | |
13036 | vex.ll = (*codep >> 5) & 3; | |
13037 | vex.b = (*codep & 0x10) != 0; | |
13038 | ||
13039 | vex.v = *codep & 0x8; | |
13040 | vex.mask_register_specifier = *codep & 0x7; | |
13041 | vex.zeroing = *codep & 0x80; | |
13042 | ||
5f847646 JB |
13043 | if (address_mode != mode_64bit) |
13044 | { | |
13045 | /* In 16/32-bit mode silently ignore following bits. */ | |
13046 | rex &= ~REX_B; | |
13047 | vex.r = 1; | |
13048 | vex.v = 1; | |
13049 | } | |
13050 | ||
43234a1e L |
13051 | need_vex = 1; |
13052 | need_vex_reg = 1; | |
13053 | codep++; | |
13054 | vindex = *codep++; | |
13055 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13056 | end_codep = codep; |
43234a1e L |
13057 | FETCH_DATA (info, codep + 1); |
13058 | modrm.mod = (*codep >> 6) & 3; | |
13059 | modrm.reg = (*codep >> 3) & 7; | |
13060 | modrm.rm = *codep & 7; | |
13061 | ||
13062 | /* Set vector length. */ | |
13063 | if (modrm.mod == 3 && vex.b) | |
13064 | vex.length = 512; | |
13065 | else | |
13066 | { | |
13067 | switch (vex.ll) | |
13068 | { | |
13069 | case 0x0: | |
13070 | vex.length = 128; | |
13071 | break; | |
13072 | case 0x1: | |
13073 | vex.length = 256; | |
13074 | break; | |
13075 | case 0x2: | |
13076 | vex.length = 512; | |
13077 | break; | |
13078 | default: | |
13079 | return &bad_opcode; | |
13080 | } | |
13081 | } | |
13082 | break; | |
13083 | ||
592d1631 L |
13084 | case 0: |
13085 | dp = &bad_opcode; | |
13086 | break; | |
13087 | ||
b844680a | 13088 | default: |
d34b5006 | 13089 | abort (); |
b844680a L |
13090 | } |
13091 | ||
13092 | if (dp->name != NULL) | |
13093 | return dp; | |
13094 | else | |
8bb15339 | 13095 | return get_valid_dis386 (dp, info); |
b844680a L |
13096 | } |
13097 | ||
dfc8cf43 | 13098 | static void |
55cf16e1 | 13099 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13100 | { |
13101 | /* If modrm.mod == 3, operand must be register. */ | |
13102 | if (need_modrm | |
55cf16e1 | 13103 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13104 | && modrm.mod != 3 |
13105 | && modrm.rm == 4) | |
13106 | { | |
13107 | FETCH_DATA (info, codep + 2); | |
13108 | sib.index = (codep [1] >> 3) & 7; | |
13109 | sib.scale = (codep [1] >> 6) & 3; | |
13110 | sib.base = codep [1] & 7; | |
13111 | } | |
13112 | } | |
13113 | ||
e396998b | 13114 | static int |
26ca5450 | 13115 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13116 | { |
2da11e11 | 13117 | const struct dis386 *dp; |
252b5132 | 13118 | int i; |
ce518a5f | 13119 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13120 | int needcomma; |
df18fdba | 13121 | int sizeflag, orig_sizeflag; |
e396998b | 13122 | const char *p; |
252b5132 | 13123 | struct dis_private priv; |
f16cd0d5 | 13124 | int prefix_length; |
252b5132 | 13125 | |
d7921315 L |
13126 | priv.orig_sizeflag = AFLAG | DFLAG; |
13127 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13128 | address_mode = mode_32bit; |
2da11e11 | 13129 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13130 | { |
13131 | address_mode = mode_16bit; | |
13132 | priv.orig_sizeflag = 0; | |
13133 | } | |
2da11e11 | 13134 | else |
d7921315 L |
13135 | address_mode = mode_64bit; |
13136 | ||
13137 | if (intel_syntax == (char) -1) | |
13138 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13139 | |
13140 | for (p = info->disassembler_options; p != NULL; ) | |
13141 | { | |
5db04b09 L |
13142 | if (CONST_STRNEQ (p, "amd64")) |
13143 | isa64 = amd64; | |
13144 | else if (CONST_STRNEQ (p, "intel64")) | |
13145 | isa64 = intel64; | |
13146 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13147 | { |
cb712a9e | 13148 | address_mode = mode_64bit; |
e396998b AM |
13149 | priv.orig_sizeflag = AFLAG | DFLAG; |
13150 | } | |
0112cd26 | 13151 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13152 | { |
cb712a9e | 13153 | address_mode = mode_32bit; |
e396998b AM |
13154 | priv.orig_sizeflag = AFLAG | DFLAG; |
13155 | } | |
0112cd26 | 13156 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13157 | { |
cb712a9e | 13158 | address_mode = mode_16bit; |
e396998b AM |
13159 | priv.orig_sizeflag = 0; |
13160 | } | |
0112cd26 | 13161 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13162 | { |
13163 | intel_syntax = 1; | |
9d141669 L |
13164 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13165 | intel_mnemonic = 1; | |
e396998b | 13166 | } |
0112cd26 | 13167 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13168 | { |
13169 | intel_syntax = 0; | |
9d141669 L |
13170 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13171 | intel_mnemonic = 0; | |
e396998b | 13172 | } |
0112cd26 | 13173 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13174 | { |
f59a29b9 L |
13175 | if (address_mode == mode_64bit) |
13176 | { | |
13177 | if (p[4] == '3' && p[5] == '2') | |
13178 | priv.orig_sizeflag &= ~AFLAG; | |
13179 | else if (p[4] == '6' && p[5] == '4') | |
13180 | priv.orig_sizeflag |= AFLAG; | |
13181 | } | |
13182 | else | |
13183 | { | |
13184 | if (p[4] == '1' && p[5] == '6') | |
13185 | priv.orig_sizeflag &= ~AFLAG; | |
13186 | else if (p[4] == '3' && p[5] == '2') | |
13187 | priv.orig_sizeflag |= AFLAG; | |
13188 | } | |
e396998b | 13189 | } |
0112cd26 | 13190 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13191 | { |
13192 | if (p[4] == '1' && p[5] == '6') | |
13193 | priv.orig_sizeflag &= ~DFLAG; | |
13194 | else if (p[4] == '3' && p[5] == '2') | |
13195 | priv.orig_sizeflag |= DFLAG; | |
13196 | } | |
0112cd26 | 13197 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13198 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13199 | ||
13200 | p = strchr (p, ','); | |
13201 | if (p != NULL) | |
13202 | p++; | |
13203 | } | |
13204 | ||
c0f92bf9 L |
13205 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13206 | { | |
13207 | (*info->fprintf_func) (info->stream, | |
13208 | _("64-bit address is disabled")); | |
13209 | return -1; | |
13210 | } | |
13211 | ||
e396998b AM |
13212 | if (intel_syntax) |
13213 | { | |
13214 | names64 = intel_names64; | |
13215 | names32 = intel_names32; | |
13216 | names16 = intel_names16; | |
13217 | names8 = intel_names8; | |
13218 | names8rex = intel_names8rex; | |
13219 | names_seg = intel_names_seg; | |
b9733481 | 13220 | names_mm = intel_names_mm; |
7e8b059b | 13221 | names_bnd = intel_names_bnd; |
b9733481 L |
13222 | names_xmm = intel_names_xmm; |
13223 | names_ymm = intel_names_ymm; | |
43234a1e | 13224 | names_zmm = intel_names_zmm; |
db51cc60 L |
13225 | index64 = intel_index64; |
13226 | index32 = intel_index32; | |
43234a1e | 13227 | names_mask = intel_names_mask; |
e396998b AM |
13228 | index16 = intel_index16; |
13229 | open_char = '['; | |
13230 | close_char = ']'; | |
13231 | separator_char = '+'; | |
13232 | scale_char = '*'; | |
13233 | } | |
13234 | else | |
13235 | { | |
13236 | names64 = att_names64; | |
13237 | names32 = att_names32; | |
13238 | names16 = att_names16; | |
13239 | names8 = att_names8; | |
13240 | names8rex = att_names8rex; | |
13241 | names_seg = att_names_seg; | |
b9733481 | 13242 | names_mm = att_names_mm; |
7e8b059b | 13243 | names_bnd = att_names_bnd; |
b9733481 L |
13244 | names_xmm = att_names_xmm; |
13245 | names_ymm = att_names_ymm; | |
43234a1e | 13246 | names_zmm = att_names_zmm; |
db51cc60 L |
13247 | index64 = att_index64; |
13248 | index32 = att_index32; | |
43234a1e | 13249 | names_mask = att_names_mask; |
e396998b AM |
13250 | index16 = att_index16; |
13251 | open_char = '('; | |
13252 | close_char = ')'; | |
13253 | separator_char = ','; | |
13254 | scale_char = ','; | |
13255 | } | |
2da11e11 | 13256 | |
4fe53c98 | 13257 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13258 | puts most long word instructions on a single line. Use 8 bytes |
13259 | for Intel L1OM. */ | |
d7921315 | 13260 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13261 | info->bytes_per_line = 8; |
13262 | else | |
13263 | info->bytes_per_line = 7; | |
252b5132 | 13264 | |
26ca5450 | 13265 | info->private_data = &priv; |
252b5132 RH |
13266 | priv.max_fetched = priv.the_buffer; |
13267 | priv.insn_start = pc; | |
252b5132 RH |
13268 | |
13269 | obuf[0] = 0; | |
ce518a5f L |
13270 | for (i = 0; i < MAX_OPERANDS; ++i) |
13271 | { | |
13272 | op_out[i][0] = 0; | |
13273 | op_index[i] = -1; | |
13274 | } | |
252b5132 RH |
13275 | |
13276 | the_info = info; | |
13277 | start_pc = pc; | |
e396998b AM |
13278 | start_codep = priv.the_buffer; |
13279 | codep = priv.the_buffer; | |
252b5132 | 13280 | |
8df14d78 | 13281 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13282 | { |
7d421014 ILT |
13283 | const char *name; |
13284 | ||
5076851f | 13285 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13286 | means we have an incomplete instruction of some sort. Just |
13287 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13288 | if (codep > priv.the_buffer) | |
5076851f | 13289 | { |
e396998b | 13290 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13291 | if (name != NULL) |
13292 | (*info->fprintf_func) (info->stream, "%s", name); | |
13293 | else | |
5076851f | 13294 | { |
7d421014 ILT |
13295 | /* Just print the first byte as a .byte instruction. */ |
13296 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13297 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13298 | } |
5076851f | 13299 | |
7d421014 | 13300 | return 1; |
5076851f ILT |
13301 | } |
13302 | ||
13303 | return -1; | |
13304 | } | |
13305 | ||
52b15da3 | 13306 | obufp = obuf; |
f16cd0d5 L |
13307 | sizeflag = priv.orig_sizeflag; |
13308 | ||
13309 | if (!ckprefix () || rex_used) | |
13310 | { | |
13311 | /* Too many prefixes or unused REX prefixes. */ | |
13312 | for (i = 0; | |
f6dd4781 | 13313 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13314 | i++) |
de882298 | 13315 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13316 | i == 0 ? "" : " ", |
f16cd0d5 | 13317 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13318 | return i; |
f16cd0d5 | 13319 | } |
252b5132 RH |
13320 | |
13321 | insn_codep = codep; | |
13322 | ||
13323 | FETCH_DATA (info, codep + 1); | |
13324 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13325 | ||
3e7d61b2 | 13326 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13327 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13328 | { |
86a80a50 | 13329 | /* Handle prefixes before fwait. */ |
d9949a36 | 13330 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13331 | i++) |
13332 | (*info->fprintf_func) (info->stream, "%s ", | |
13333 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13334 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13335 | return i + 1; |
252b5132 RH |
13336 | } |
13337 | ||
252b5132 RH |
13338 | if (*codep == 0x0f) |
13339 | { | |
eec0f4ca | 13340 | unsigned char threebyte; |
5f40e14d JS |
13341 | |
13342 | codep++; | |
13343 | FETCH_DATA (info, codep + 1); | |
13344 | threebyte = *codep; | |
eec0f4ca | 13345 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13346 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13347 | codep++; |
252b5132 RH |
13348 | } |
13349 | else | |
13350 | { | |
6439fc28 | 13351 | dp = &dis386[*codep]; |
252b5132 | 13352 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13353 | codep++; |
252b5132 | 13354 | } |
246c51aa | 13355 | |
df18fdba L |
13356 | /* Save sizeflag for printing the extra prefixes later before updating |
13357 | it for mnemonic and operand processing. The prefix names depend | |
13358 | only on the address mode. */ | |
13359 | orig_sizeflag = sizeflag; | |
c608c12e | 13360 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13361 | sizeflag ^= AFLAG; |
b844680a | 13362 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13363 | sizeflag ^= DFLAG; |
3ffd33cf | 13364 | |
285ca992 | 13365 | end_codep = codep; |
8bb15339 | 13366 | if (need_modrm) |
252b5132 RH |
13367 | { |
13368 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13369 | modrm.mod = (*codep >> 6) & 3; |
13370 | modrm.reg = (*codep >> 3) & 7; | |
13371 | modrm.rm = *codep & 7; | |
252b5132 RH |
13372 | } |
13373 | ||
42d5f9c6 MS |
13374 | need_vex = 0; |
13375 | need_vex_reg = 0; | |
13376 | vex_w_done = 0; | |
caf0678c | 13377 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 13378 | |
ce518a5f | 13379 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13380 | { |
55cf16e1 | 13381 | get_sib (info, sizeflag); |
252b5132 RH |
13382 | dofloat (sizeflag); |
13383 | } | |
13384 | else | |
13385 | { | |
8bb15339 | 13386 | dp = get_valid_dis386 (dp, info); |
b844680a | 13387 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13388 | { |
55cf16e1 | 13389 | get_sib (info, sizeflag); |
ce518a5f L |
13390 | for (i = 0; i < MAX_OPERANDS; ++i) |
13391 | { | |
246c51aa | 13392 | obufp = op_out[i]; |
ce518a5f L |
13393 | op_ad = MAX_OPERANDS - 1 - i; |
13394 | if (dp->op[i].rtn) | |
13395 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13396 | /* For EVEX instruction after the last operand masking |
13397 | should be printed. */ | |
13398 | if (i == 0 && vex.evex) | |
13399 | { | |
13400 | /* Don't print {%k0}. */ | |
13401 | if (vex.mask_register_specifier) | |
13402 | { | |
13403 | oappend ("{"); | |
13404 | oappend (names_mask[vex.mask_register_specifier]); | |
13405 | oappend ("}"); | |
13406 | } | |
13407 | if (vex.zeroing) | |
13408 | oappend ("{z}"); | |
13409 | } | |
ce518a5f | 13410 | } |
6439fc28 | 13411 | } |
252b5132 RH |
13412 | } |
13413 | ||
d869730d | 13414 | /* Check if the REX prefix is used. */ |
e2e6193d | 13415 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13416 | all_prefixes[last_rex_prefix] = 0; |
13417 | ||
5e6718e4 | 13418 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13419 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13420 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13421 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13422 | all_prefixes[last_seg_prefix] = 0; |
13423 | ||
5e6718e4 | 13424 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13425 | if ((prefixes & PREFIX_ADDR) != 0 |
13426 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13427 | all_prefixes[last_addr_prefix] = 0; | |
13428 | ||
df18fdba L |
13429 | /* Check if the DATA prefix is used. */ |
13430 | if ((prefixes & PREFIX_DATA) != 0 | |
13431 | && (used_prefixes & PREFIX_DATA) != 0) | |
13432 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13433 | |
df18fdba | 13434 | /* Print the extra prefixes. */ |
f16cd0d5 | 13435 | prefix_length = 0; |
f310f33d | 13436 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13437 | if (all_prefixes[i]) |
13438 | { | |
13439 | const char *name; | |
df18fdba | 13440 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13441 | if (name == NULL) |
13442 | abort (); | |
13443 | prefix_length += strlen (name) + 1; | |
13444 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13445 | } | |
b844680a | 13446 | |
285ca992 L |
13447 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13448 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13449 | used by putop and MMX/SSE operand and may be overriden by the | |
13450 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13451 | separately. */ | |
3888916d | 13452 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13453 | && dp != &bad_opcode |
13454 | && (((prefixes | |
13455 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13456 | && (used_prefixes | |
13457 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13458 | || ((((prefixes | |
13459 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13460 | == PREFIX_DATA) | |
13461 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13462 | { | |
13463 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13464 | return end_codep - priv.the_buffer; | |
13465 | } | |
13466 | ||
f16cd0d5 L |
13467 | /* Check maximum code length. */ |
13468 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13469 | { | |
13470 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13471 | return MAX_CODE_LENGTH; | |
13472 | } | |
b844680a | 13473 | |
ea397f5b | 13474 | obufp = mnemonicendp; |
f16cd0d5 | 13475 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13476 | oappend (" "); |
13477 | oappend (" "); | |
13478 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13479 | ||
13480 | /* The enter and bound instructions are printed with operands in the same | |
13481 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13482 | if (intel_syntax || two_source_ops) |
252b5132 | 13483 | { |
185b1163 L |
13484 | bfd_vma riprel; |
13485 | ||
ce518a5f | 13486 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13487 | op_txt[i] = op_out[i]; |
246c51aa | 13488 | |
3a8547d2 JB |
13489 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13490 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13491 | { | |
13492 | op_txt[2] = op_out[3]; | |
13493 | op_txt[3] = op_out[2]; | |
13494 | } | |
13495 | ||
ce518a5f L |
13496 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13497 | { | |
6c067bbb RM |
13498 | op_ad = op_index[i]; |
13499 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13500 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13501 | riprel = op_riprel[i]; |
13502 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13503 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13504 | } |
252b5132 RH |
13505 | } |
13506 | else | |
13507 | { | |
ce518a5f | 13508 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13509 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13510 | } |
13511 | ||
ce518a5f L |
13512 | needcomma = 0; |
13513 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13514 | if (*op_txt[i]) | |
13515 | { | |
13516 | if (needcomma) | |
13517 | (*info->fprintf_func) (info->stream, ","); | |
13518 | if (op_index[i] != -1 && !op_riprel[i]) | |
13519 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13520 | else | |
13521 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13522 | needcomma = 1; | |
13523 | } | |
050dfa73 | 13524 | |
ce518a5f | 13525 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13526 | if (op_index[i] != -1 && op_riprel[i]) |
13527 | { | |
13528 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13529 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13530 | + op_address[op_index[i]]), info); |
185b1163 | 13531 | break; |
52b15da3 | 13532 | } |
e396998b | 13533 | return codep - priv.the_buffer; |
252b5132 RH |
13534 | } |
13535 | ||
6439fc28 | 13536 | static const char *float_mem[] = { |
252b5132 | 13537 | /* d8 */ |
7c52e0e8 L |
13538 | "fadd{s|}", |
13539 | "fmul{s|}", | |
13540 | "fcom{s|}", | |
13541 | "fcomp{s|}", | |
13542 | "fsub{s|}", | |
13543 | "fsubr{s|}", | |
13544 | "fdiv{s|}", | |
13545 | "fdivr{s|}", | |
db6eb5be | 13546 | /* d9 */ |
7c52e0e8 | 13547 | "fld{s|}", |
252b5132 | 13548 | "(bad)", |
7c52e0e8 L |
13549 | "fst{s|}", |
13550 | "fstp{s|}", | |
9306ca4a | 13551 | "fldenvIC", |
252b5132 | 13552 | "fldcw", |
9306ca4a | 13553 | "fNstenvIC", |
252b5132 RH |
13554 | "fNstcw", |
13555 | /* da */ | |
7c52e0e8 L |
13556 | "fiadd{l|}", |
13557 | "fimul{l|}", | |
13558 | "ficom{l|}", | |
13559 | "ficomp{l|}", | |
13560 | "fisub{l|}", | |
13561 | "fisubr{l|}", | |
13562 | "fidiv{l|}", | |
13563 | "fidivr{l|}", | |
252b5132 | 13564 | /* db */ |
7c52e0e8 L |
13565 | "fild{l|}", |
13566 | "fisttp{l|}", | |
13567 | "fist{l|}", | |
13568 | "fistp{l|}", | |
252b5132 | 13569 | "(bad)", |
6439fc28 | 13570 | "fld{t||t|}", |
252b5132 | 13571 | "(bad)", |
6439fc28 | 13572 | "fstp{t||t|}", |
252b5132 | 13573 | /* dc */ |
7c52e0e8 L |
13574 | "fadd{l|}", |
13575 | "fmul{l|}", | |
13576 | "fcom{l|}", | |
13577 | "fcomp{l|}", | |
13578 | "fsub{l|}", | |
13579 | "fsubr{l|}", | |
13580 | "fdiv{l|}", | |
13581 | "fdivr{l|}", | |
252b5132 | 13582 | /* dd */ |
7c52e0e8 L |
13583 | "fld{l|}", |
13584 | "fisttp{ll|}", | |
13585 | "fst{l||}", | |
13586 | "fstp{l|}", | |
9306ca4a | 13587 | "frstorIC", |
252b5132 | 13588 | "(bad)", |
9306ca4a | 13589 | "fNsaveIC", |
252b5132 RH |
13590 | "fNstsw", |
13591 | /* de */ | |
ac465521 JB |
13592 | "fiadd{s|}", |
13593 | "fimul{s|}", | |
13594 | "ficom{s|}", | |
13595 | "ficomp{s|}", | |
13596 | "fisub{s|}", | |
13597 | "fisubr{s|}", | |
13598 | "fidiv{s|}", | |
13599 | "fidivr{s|}", | |
252b5132 | 13600 | /* df */ |
ac465521 JB |
13601 | "fild{s|}", |
13602 | "fisttp{s|}", | |
13603 | "fist{s|}", | |
13604 | "fistp{s|}", | |
252b5132 | 13605 | "fbld", |
7c52e0e8 | 13606 | "fild{ll|}", |
252b5132 | 13607 | "fbstp", |
7c52e0e8 | 13608 | "fistp{ll|}", |
1d9f512f AM |
13609 | }; |
13610 | ||
13611 | static const unsigned char float_mem_mode[] = { | |
13612 | /* d8 */ | |
13613 | d_mode, | |
13614 | d_mode, | |
13615 | d_mode, | |
13616 | d_mode, | |
13617 | d_mode, | |
13618 | d_mode, | |
13619 | d_mode, | |
13620 | d_mode, | |
13621 | /* d9 */ | |
13622 | d_mode, | |
13623 | 0, | |
13624 | d_mode, | |
13625 | d_mode, | |
13626 | 0, | |
13627 | w_mode, | |
13628 | 0, | |
13629 | w_mode, | |
13630 | /* da */ | |
13631 | d_mode, | |
13632 | d_mode, | |
13633 | d_mode, | |
13634 | d_mode, | |
13635 | d_mode, | |
13636 | d_mode, | |
13637 | d_mode, | |
13638 | d_mode, | |
13639 | /* db */ | |
13640 | d_mode, | |
13641 | d_mode, | |
13642 | d_mode, | |
13643 | d_mode, | |
13644 | 0, | |
9306ca4a | 13645 | t_mode, |
1d9f512f | 13646 | 0, |
9306ca4a | 13647 | t_mode, |
1d9f512f AM |
13648 | /* dc */ |
13649 | q_mode, | |
13650 | q_mode, | |
13651 | q_mode, | |
13652 | q_mode, | |
13653 | q_mode, | |
13654 | q_mode, | |
13655 | q_mode, | |
13656 | q_mode, | |
13657 | /* dd */ | |
13658 | q_mode, | |
13659 | q_mode, | |
13660 | q_mode, | |
13661 | q_mode, | |
13662 | 0, | |
13663 | 0, | |
13664 | 0, | |
13665 | w_mode, | |
13666 | /* de */ | |
13667 | w_mode, | |
13668 | w_mode, | |
13669 | w_mode, | |
13670 | w_mode, | |
13671 | w_mode, | |
13672 | w_mode, | |
13673 | w_mode, | |
13674 | w_mode, | |
13675 | /* df */ | |
13676 | w_mode, | |
13677 | w_mode, | |
13678 | w_mode, | |
13679 | w_mode, | |
9306ca4a | 13680 | t_mode, |
1d9f512f | 13681 | q_mode, |
9306ca4a | 13682 | t_mode, |
1d9f512f | 13683 | q_mode |
252b5132 RH |
13684 | }; |
13685 | ||
ce518a5f L |
13686 | #define ST { OP_ST, 0 } |
13687 | #define STi { OP_STi, 0 } | |
252b5132 | 13688 | |
48c97fa1 L |
13689 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13690 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13691 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13692 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13693 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13694 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13695 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13696 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13697 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13698 | |
2da11e11 | 13699 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13700 | /* d8 */ |
13701 | { | |
bf890a93 IT |
13702 | { "fadd", { ST, STi }, 0 }, |
13703 | { "fmul", { ST, STi }, 0 }, | |
13704 | { "fcom", { STi }, 0 }, | |
13705 | { "fcomp", { STi }, 0 }, | |
13706 | { "fsub", { ST, STi }, 0 }, | |
13707 | { "fsubr", { ST, STi }, 0 }, | |
13708 | { "fdiv", { ST, STi }, 0 }, | |
13709 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13710 | }, |
13711 | /* d9 */ | |
13712 | { | |
bf890a93 IT |
13713 | { "fld", { STi }, 0 }, |
13714 | { "fxch", { STi }, 0 }, | |
252b5132 | 13715 | { FGRPd9_2 }, |
592d1631 | 13716 | { Bad_Opcode }, |
252b5132 RH |
13717 | { FGRPd9_4 }, |
13718 | { FGRPd9_5 }, | |
13719 | { FGRPd9_6 }, | |
13720 | { FGRPd9_7 }, | |
13721 | }, | |
13722 | /* da */ | |
13723 | { | |
bf890a93 IT |
13724 | { "fcmovb", { ST, STi }, 0 }, |
13725 | { "fcmove", { ST, STi }, 0 }, | |
13726 | { "fcmovbe",{ ST, STi }, 0 }, | |
13727 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13728 | { Bad_Opcode }, |
252b5132 | 13729 | { FGRPda_5 }, |
592d1631 L |
13730 | { Bad_Opcode }, |
13731 | { Bad_Opcode }, | |
252b5132 RH |
13732 | }, |
13733 | /* db */ | |
13734 | { | |
bf890a93 IT |
13735 | { "fcmovnb",{ ST, STi }, 0 }, |
13736 | { "fcmovne",{ ST, STi }, 0 }, | |
13737 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13738 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13739 | { FGRPdb_4 }, |
bf890a93 IT |
13740 | { "fucomi", { ST, STi }, 0 }, |
13741 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13742 | { Bad_Opcode }, |
252b5132 RH |
13743 | }, |
13744 | /* dc */ | |
13745 | { | |
bf890a93 IT |
13746 | { "fadd", { STi, ST }, 0 }, |
13747 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13748 | { Bad_Opcode }, |
13749 | { Bad_Opcode }, | |
d53e6b98 JB |
13750 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13751 | { "fsub{M|}", { STi, ST }, 0 }, | |
13752 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13753 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13754 | }, |
13755 | /* dd */ | |
13756 | { | |
bf890a93 | 13757 | { "ffree", { STi }, 0 }, |
592d1631 | 13758 | { Bad_Opcode }, |
bf890a93 IT |
13759 | { "fst", { STi }, 0 }, |
13760 | { "fstp", { STi }, 0 }, | |
13761 | { "fucom", { STi }, 0 }, | |
13762 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13763 | { Bad_Opcode }, |
13764 | { Bad_Opcode }, | |
252b5132 RH |
13765 | }, |
13766 | /* de */ | |
13767 | { | |
bf890a93 IT |
13768 | { "faddp", { STi, ST }, 0 }, |
13769 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13770 | { Bad_Opcode }, |
252b5132 | 13771 | { FGRPde_3 }, |
d53e6b98 JB |
13772 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13773 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13774 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13775 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13776 | }, |
13777 | /* df */ | |
13778 | { | |
bf890a93 | 13779 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13780 | { Bad_Opcode }, |
13781 | { Bad_Opcode }, | |
13782 | { Bad_Opcode }, | |
252b5132 | 13783 | { FGRPdf_4 }, |
bf890a93 IT |
13784 | { "fucomip", { ST, STi }, 0 }, |
13785 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13786 | { Bad_Opcode }, |
252b5132 RH |
13787 | }, |
13788 | }; | |
13789 | ||
252b5132 | 13790 | static char *fgrps[][8] = { |
48c97fa1 L |
13791 | /* Bad opcode 0 */ |
13792 | { | |
13793 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13794 | }, | |
13795 | ||
13796 | /* d9_2 1 */ | |
252b5132 RH |
13797 | { |
13798 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13799 | }, | |
13800 | ||
48c97fa1 | 13801 | /* d9_4 2 */ |
252b5132 RH |
13802 | { |
13803 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13804 | }, | |
13805 | ||
48c97fa1 | 13806 | /* d9_5 3 */ |
252b5132 RH |
13807 | { |
13808 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13809 | }, | |
13810 | ||
48c97fa1 | 13811 | /* d9_6 4 */ |
252b5132 RH |
13812 | { |
13813 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13814 | }, | |
13815 | ||
48c97fa1 | 13816 | /* d9_7 5 */ |
252b5132 RH |
13817 | { |
13818 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13819 | }, | |
13820 | ||
48c97fa1 | 13821 | /* da_5 6 */ |
252b5132 RH |
13822 | { |
13823 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13824 | }, | |
13825 | ||
48c97fa1 | 13826 | /* db_4 7 */ |
252b5132 | 13827 | { |
309d3373 JB |
13828 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13829 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13830 | }, |
13831 | ||
48c97fa1 | 13832 | /* de_3 8 */ |
252b5132 RH |
13833 | { |
13834 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13835 | }, | |
13836 | ||
48c97fa1 | 13837 | /* df_4 9 */ |
252b5132 RH |
13838 | { |
13839 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13840 | }, | |
13841 | }; | |
13842 | ||
b6169b20 L |
13843 | static void |
13844 | swap_operand (void) | |
13845 | { | |
13846 | mnemonicendp[0] = '.'; | |
13847 | mnemonicendp[1] = 's'; | |
13848 | mnemonicendp += 2; | |
13849 | } | |
13850 | ||
b844680a L |
13851 | static void |
13852 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13853 | int sizeflag ATTRIBUTE_UNUSED) | |
13854 | { | |
13855 | /* Skip mod/rm byte. */ | |
13856 | MODRM_CHECK; | |
13857 | codep++; | |
13858 | } | |
13859 | ||
252b5132 | 13860 | static void |
26ca5450 | 13861 | dofloat (int sizeflag) |
252b5132 | 13862 | { |
2da11e11 | 13863 | const struct dis386 *dp; |
252b5132 RH |
13864 | unsigned char floatop; |
13865 | ||
13866 | floatop = codep[-1]; | |
13867 | ||
7967e09e | 13868 | if (modrm.mod != 3) |
252b5132 | 13869 | { |
7967e09e | 13870 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13871 | |
13872 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13873 | obufp = op_out[0]; |
6e50d963 | 13874 | op_ad = 2; |
1d9f512f | 13875 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13876 | return; |
13877 | } | |
6608db57 | 13878 | /* Skip mod/rm byte. */ |
4bba6815 | 13879 | MODRM_CHECK; |
252b5132 RH |
13880 | codep++; |
13881 | ||
7967e09e | 13882 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13883 | if (dp->name == NULL) |
13884 | { | |
7967e09e | 13885 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13886 | |
6608db57 | 13887 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13888 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13889 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13890 | } |
13891 | else | |
13892 | { | |
13893 | putop (dp->name, sizeflag); | |
13894 | ||
ce518a5f | 13895 | obufp = op_out[0]; |
6e50d963 | 13896 | op_ad = 2; |
ce518a5f L |
13897 | if (dp->op[0].rtn) |
13898 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13899 | |
ce518a5f | 13900 | obufp = op_out[1]; |
6e50d963 | 13901 | op_ad = 1; |
ce518a5f L |
13902 | if (dp->op[1].rtn) |
13903 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13904 | } |
13905 | } | |
13906 | ||
9ce09ba2 RM |
13907 | /* Like oappend (below), but S is a string starting with '%'. |
13908 | In Intel syntax, the '%' is elided. */ | |
13909 | static void | |
13910 | oappend_maybe_intel (const char *s) | |
13911 | { | |
13912 | oappend (s + intel_syntax); | |
13913 | } | |
13914 | ||
252b5132 | 13915 | static void |
26ca5450 | 13916 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13917 | { |
9ce09ba2 | 13918 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13919 | } |
13920 | ||
252b5132 | 13921 | static void |
26ca5450 | 13922 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13923 | { |
7967e09e | 13924 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13925 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13926 | } |
13927 | ||
6608db57 | 13928 | /* Capital letters in template are macros. */ |
6439fc28 | 13929 | static int |
d3ce72d0 | 13930 | putop (const char *in_template, int sizeflag) |
252b5132 | 13931 | { |
2da11e11 | 13932 | const char *p; |
9306ca4a | 13933 | int alt = 0; |
9d141669 | 13934 | int cond = 1; |
98b528ac L |
13935 | unsigned int l = 0, len = 1; |
13936 | char last[4]; | |
13937 | ||
13938 | #define SAVE_LAST(c) \ | |
13939 | if (l < len && l < sizeof (last)) \ | |
13940 | last[l++] = c; \ | |
13941 | else \ | |
13942 | abort (); | |
252b5132 | 13943 | |
d3ce72d0 | 13944 | for (p = in_template; *p; p++) |
252b5132 RH |
13945 | { |
13946 | switch (*p) | |
13947 | { | |
13948 | default: | |
13949 | *obufp++ = *p; | |
13950 | break; | |
98b528ac L |
13951 | case '%': |
13952 | len++; | |
13953 | break; | |
9d141669 L |
13954 | case '!': |
13955 | cond = 0; | |
13956 | break; | |
6439fc28 | 13957 | case '{': |
6439fc28 | 13958 | if (intel_syntax) |
6439fc28 AM |
13959 | { |
13960 | while (*++p != '|') | |
7c52e0e8 L |
13961 | if (*p == '}' || *p == '\0') |
13962 | abort (); | |
6439fc28 | 13963 | } |
9306ca4a JB |
13964 | /* Fall through. */ |
13965 | case 'I': | |
13966 | alt = 1; | |
13967 | continue; | |
6439fc28 AM |
13968 | case '|': |
13969 | while (*++p != '}') | |
13970 | { | |
13971 | if (*p == '\0') | |
13972 | abort (); | |
13973 | } | |
13974 | break; | |
13975 | case '}': | |
13976 | break; | |
252b5132 | 13977 | case 'A': |
db6eb5be AM |
13978 | if (intel_syntax) |
13979 | break; | |
7967e09e | 13980 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13981 | *obufp++ = 'b'; |
13982 | break; | |
13983 | case 'B': | |
4b06377f L |
13984 | if (l == 0 && len == 1) |
13985 | { | |
13986 | case_B: | |
13987 | if (intel_syntax) | |
13988 | break; | |
13989 | if (sizeflag & SUFFIX_ALWAYS) | |
13990 | *obufp++ = 'b'; | |
13991 | } | |
13992 | else | |
13993 | { | |
13994 | if (l != 1 | |
13995 | || len != 2 | |
13996 | || last[0] != 'L') | |
13997 | { | |
13998 | SAVE_LAST (*p); | |
13999 | break; | |
14000 | } | |
14001 | ||
14002 | if (address_mode == mode_64bit | |
14003 | && !(prefixes & PREFIX_ADDR)) | |
14004 | { | |
14005 | *obufp++ = 'a'; | |
14006 | *obufp++ = 'b'; | |
14007 | *obufp++ = 's'; | |
14008 | } | |
14009 | ||
14010 | goto case_B; | |
14011 | } | |
252b5132 | 14012 | break; |
9306ca4a JB |
14013 | case 'C': |
14014 | if (intel_syntax && !alt) | |
14015 | break; | |
14016 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14017 | { | |
14018 | if (sizeflag & DFLAG) | |
14019 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14020 | else | |
14021 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14022 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14023 | } | |
14024 | break; | |
ed7841b3 JB |
14025 | case 'D': |
14026 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14027 | break; | |
161a04f6 | 14028 | USED_REX (REX_W); |
7967e09e | 14029 | if (modrm.mod == 3) |
ed7841b3 | 14030 | { |
161a04f6 | 14031 | if (rex & REX_W) |
ed7841b3 | 14032 | *obufp++ = 'q'; |
ed7841b3 | 14033 | else |
f16cd0d5 L |
14034 | { |
14035 | if (sizeflag & DFLAG) | |
14036 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14037 | else | |
14038 | *obufp++ = 'w'; | |
14039 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14040 | } | |
ed7841b3 JB |
14041 | } |
14042 | else | |
14043 | *obufp++ = 'w'; | |
14044 | break; | |
252b5132 | 14045 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14046 | if (address_mode == mode_64bit) |
c1a64871 JH |
14047 | { |
14048 | if (sizeflag & AFLAG) | |
14049 | *obufp++ = 'r'; | |
14050 | else | |
14051 | *obufp++ = 'e'; | |
14052 | } | |
14053 | else | |
14054 | if (sizeflag & AFLAG) | |
14055 | *obufp++ = 'e'; | |
3ffd33cf AM |
14056 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14057 | break; | |
14058 | case 'F': | |
db6eb5be AM |
14059 | if (intel_syntax) |
14060 | break; | |
e396998b | 14061 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14062 | { |
14063 | if (sizeflag & AFLAG) | |
cb712a9e | 14064 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14065 | else |
cb712a9e | 14066 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14067 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14068 | } | |
252b5132 | 14069 | break; |
52fd6d94 JB |
14070 | case 'G': |
14071 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14072 | break; | |
161a04f6 | 14073 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14074 | *obufp++ = 'l'; |
14075 | else | |
14076 | *obufp++ = 'w'; | |
161a04f6 | 14077 | if (!(rex & REX_W)) |
52fd6d94 JB |
14078 | used_prefixes |= (prefixes & PREFIX_DATA); |
14079 | break; | |
5dd0794d | 14080 | case 'H': |
db6eb5be AM |
14081 | if (intel_syntax) |
14082 | break; | |
5dd0794d AM |
14083 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14084 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14085 | { | |
14086 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14087 | *obufp++ = ','; | |
14088 | *obufp++ = 'p'; | |
14089 | if (prefixes & PREFIX_DS) | |
14090 | *obufp++ = 't'; | |
14091 | else | |
14092 | *obufp++ = 'n'; | |
14093 | } | |
14094 | break; | |
9306ca4a JB |
14095 | case 'J': |
14096 | if (intel_syntax) | |
14097 | break; | |
14098 | *obufp++ = 'l'; | |
14099 | break; | |
42903f7f L |
14100 | case 'K': |
14101 | USED_REX (REX_W); | |
14102 | if (rex & REX_W) | |
14103 | *obufp++ = 'q'; | |
14104 | else | |
14105 | *obufp++ = 'd'; | |
14106 | break; | |
6dd5059a | 14107 | case 'Z': |
04d824a4 JB |
14108 | if (l != 0 || len != 1) |
14109 | { | |
14110 | if (l != 1 || len != 2 || last[0] != 'X') | |
14111 | { | |
14112 | SAVE_LAST (*p); | |
14113 | break; | |
14114 | } | |
14115 | if (!need_vex || !vex.evex) | |
14116 | abort (); | |
14117 | if (intel_syntax | |
14118 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14119 | break; | |
14120 | switch (vex.length) | |
14121 | { | |
14122 | case 128: | |
14123 | *obufp++ = 'x'; | |
14124 | break; | |
14125 | case 256: | |
14126 | *obufp++ = 'y'; | |
14127 | break; | |
14128 | case 512: | |
14129 | *obufp++ = 'z'; | |
14130 | break; | |
14131 | default: | |
14132 | abort (); | |
14133 | } | |
14134 | break; | |
14135 | } | |
6dd5059a L |
14136 | if (intel_syntax) |
14137 | break; | |
14138 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14139 | { | |
14140 | *obufp++ = 'q'; | |
14141 | break; | |
14142 | } | |
14143 | /* Fall through. */ | |
98b528ac | 14144 | goto case_L; |
252b5132 | 14145 | case 'L': |
98b528ac L |
14146 | if (l != 0 || len != 1) |
14147 | { | |
14148 | SAVE_LAST (*p); | |
14149 | break; | |
14150 | } | |
14151 | case_L: | |
db6eb5be AM |
14152 | if (intel_syntax) |
14153 | break; | |
252b5132 RH |
14154 | if (sizeflag & SUFFIX_ALWAYS) |
14155 | *obufp++ = 'l'; | |
252b5132 | 14156 | break; |
9d141669 L |
14157 | case 'M': |
14158 | if (intel_mnemonic != cond) | |
14159 | *obufp++ = 'r'; | |
14160 | break; | |
252b5132 RH |
14161 | case 'N': |
14162 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14163 | *obufp++ = 'n'; | |
7d421014 ILT |
14164 | else |
14165 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14166 | break; |
52b15da3 | 14167 | case 'O': |
161a04f6 L |
14168 | USED_REX (REX_W); |
14169 | if (rex & REX_W) | |
6439fc28 | 14170 | *obufp++ = 'o'; |
a35ca55a JB |
14171 | else if (intel_syntax && (sizeflag & DFLAG)) |
14172 | *obufp++ = 'q'; | |
52b15da3 JH |
14173 | else |
14174 | *obufp++ = 'd'; | |
161a04f6 | 14175 | if (!(rex & REX_W)) |
a35ca55a | 14176 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14177 | break; |
07f5af7d L |
14178 | case '&': |
14179 | if (!intel_syntax | |
14180 | && address_mode == mode_64bit | |
14181 | && isa64 == intel64) | |
14182 | { | |
14183 | *obufp++ = 'q'; | |
14184 | break; | |
14185 | } | |
14186 | /* Fall through. */ | |
6439fc28 | 14187 | case 'T': |
d9e3625e L |
14188 | if (!intel_syntax |
14189 | && address_mode == mode_64bit | |
7bb15c6f | 14190 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14191 | { |
14192 | *obufp++ = 'q'; | |
14193 | break; | |
14194 | } | |
6608db57 | 14195 | /* Fall through. */ |
4b4c407a | 14196 | goto case_P; |
252b5132 | 14197 | case 'P': |
4b4c407a | 14198 | if (l == 0 && len == 1) |
d9e3625e | 14199 | { |
4b4c407a L |
14200 | case_P: |
14201 | if (intel_syntax) | |
d9e3625e | 14202 | { |
4b4c407a L |
14203 | if ((rex & REX_W) == 0 |
14204 | && (prefixes & PREFIX_DATA)) | |
14205 | { | |
14206 | if ((sizeflag & DFLAG) == 0) | |
14207 | *obufp++ = 'w'; | |
14208 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14209 | } | |
14210 | break; | |
14211 | } | |
14212 | if ((prefixes & PREFIX_DATA) | |
14213 | || (rex & REX_W) | |
14214 | || (sizeflag & SUFFIX_ALWAYS)) | |
14215 | { | |
14216 | USED_REX (REX_W); | |
14217 | if (rex & REX_W) | |
14218 | *obufp++ = 'q'; | |
14219 | else | |
14220 | { | |
14221 | if (sizeflag & DFLAG) | |
14222 | *obufp++ = 'l'; | |
14223 | else | |
14224 | *obufp++ = 'w'; | |
14225 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14226 | } | |
d9e3625e | 14227 | } |
d9e3625e | 14228 | } |
4b4c407a | 14229 | else |
252b5132 | 14230 | { |
4b4c407a L |
14231 | if (l != 1 || len != 2 || last[0] != 'L') |
14232 | { | |
14233 | SAVE_LAST (*p); | |
14234 | break; | |
14235 | } | |
14236 | ||
14237 | if ((prefixes & PREFIX_DATA) | |
14238 | || (rex & REX_W) | |
14239 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14240 | { |
4b4c407a L |
14241 | USED_REX (REX_W); |
14242 | if (rex & REX_W) | |
14243 | *obufp++ = 'q'; | |
14244 | else | |
14245 | { | |
14246 | if (sizeflag & DFLAG) | |
14247 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14248 | else | |
14249 | *obufp++ = 'w'; | |
14250 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14251 | } | |
52b15da3 | 14252 | } |
252b5132 RH |
14253 | } |
14254 | break; | |
6439fc28 | 14255 | case 'U': |
db6eb5be AM |
14256 | if (intel_syntax) |
14257 | break; | |
7bb15c6f | 14258 | if (address_mode == mode_64bit |
6c067bbb | 14259 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14260 | { |
7967e09e | 14261 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14262 | *obufp++ = 'q'; |
6439fc28 AM |
14263 | break; |
14264 | } | |
6608db57 | 14265 | /* Fall through. */ |
98b528ac | 14266 | goto case_Q; |
252b5132 | 14267 | case 'Q': |
98b528ac | 14268 | if (l == 0 && len == 1) |
252b5132 | 14269 | { |
98b528ac L |
14270 | case_Q: |
14271 | if (intel_syntax && !alt) | |
14272 | break; | |
14273 | USED_REX (REX_W); | |
14274 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14275 | { |
98b528ac L |
14276 | if (rex & REX_W) |
14277 | *obufp++ = 'q'; | |
52b15da3 | 14278 | else |
98b528ac L |
14279 | { |
14280 | if (sizeflag & DFLAG) | |
14281 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14282 | else | |
14283 | *obufp++ = 'w'; | |
f16cd0d5 | 14284 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14285 | } |
52b15da3 | 14286 | } |
98b528ac L |
14287 | } |
14288 | else | |
14289 | { | |
14290 | if (l != 1 || len != 2 || last[0] != 'L') | |
14291 | { | |
14292 | SAVE_LAST (*p); | |
14293 | break; | |
14294 | } | |
14295 | if (intel_syntax | |
14296 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14297 | break; | |
14298 | if ((rex & REX_W)) | |
14299 | { | |
14300 | USED_REX (REX_W); | |
14301 | *obufp++ = 'q'; | |
14302 | } | |
14303 | else | |
14304 | *obufp++ = 'l'; | |
252b5132 RH |
14305 | } |
14306 | break; | |
14307 | case 'R': | |
161a04f6 L |
14308 | USED_REX (REX_W); |
14309 | if (rex & REX_W) | |
a35ca55a JB |
14310 | *obufp++ = 'q'; |
14311 | else if (sizeflag & DFLAG) | |
c608c12e | 14312 | { |
a35ca55a | 14313 | if (intel_syntax) |
c608c12e | 14314 | *obufp++ = 'd'; |
c608c12e | 14315 | else |
a35ca55a | 14316 | *obufp++ = 'l'; |
c608c12e | 14317 | } |
252b5132 | 14318 | else |
a35ca55a JB |
14319 | *obufp++ = 'w'; |
14320 | if (intel_syntax && !p[1] | |
161a04f6 | 14321 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14322 | *obufp++ = 'e'; |
161a04f6 | 14323 | if (!(rex & REX_W)) |
52b15da3 | 14324 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14325 | break; |
1a114b12 | 14326 | case 'V': |
4b06377f | 14327 | if (l == 0 && len == 1) |
1a114b12 | 14328 | { |
4b06377f L |
14329 | if (intel_syntax) |
14330 | break; | |
7bb15c6f | 14331 | if (address_mode == mode_64bit |
6c067bbb | 14332 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14333 | { |
14334 | if (sizeflag & SUFFIX_ALWAYS) | |
14335 | *obufp++ = 'q'; | |
14336 | break; | |
14337 | } | |
14338 | } | |
14339 | else | |
14340 | { | |
14341 | if (l != 1 | |
14342 | || len != 2 | |
14343 | || last[0] != 'L') | |
14344 | { | |
14345 | SAVE_LAST (*p); | |
14346 | break; | |
14347 | } | |
14348 | ||
14349 | if (rex & REX_W) | |
14350 | { | |
14351 | *obufp++ = 'a'; | |
14352 | *obufp++ = 'b'; | |
14353 | *obufp++ = 's'; | |
14354 | } | |
1a114b12 JB |
14355 | } |
14356 | /* Fall through. */ | |
4b06377f | 14357 | goto case_S; |
252b5132 | 14358 | case 'S': |
4b06377f | 14359 | if (l == 0 && len == 1) |
252b5132 | 14360 | { |
4b06377f L |
14361 | case_S: |
14362 | if (intel_syntax) | |
14363 | break; | |
14364 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14365 | { |
4b06377f L |
14366 | if (rex & REX_W) |
14367 | *obufp++ = 'q'; | |
52b15da3 | 14368 | else |
4b06377f L |
14369 | { |
14370 | if (sizeflag & DFLAG) | |
14371 | *obufp++ = 'l'; | |
14372 | else | |
14373 | *obufp++ = 'w'; | |
14374 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14375 | } | |
14376 | } | |
14377 | } | |
14378 | else | |
14379 | { | |
14380 | if (l != 1 | |
14381 | || len != 2 | |
14382 | || last[0] != 'L') | |
14383 | { | |
14384 | SAVE_LAST (*p); | |
14385 | break; | |
52b15da3 | 14386 | } |
4b06377f L |
14387 | |
14388 | if (address_mode == mode_64bit | |
14389 | && !(prefixes & PREFIX_ADDR)) | |
14390 | { | |
14391 | *obufp++ = 'a'; | |
14392 | *obufp++ = 'b'; | |
14393 | *obufp++ = 's'; | |
14394 | } | |
14395 | ||
14396 | goto case_S; | |
252b5132 | 14397 | } |
252b5132 | 14398 | break; |
041bd2e0 | 14399 | case 'X': |
c0f3af97 L |
14400 | if (l != 0 || len != 1) |
14401 | { | |
14402 | SAVE_LAST (*p); | |
14403 | break; | |
14404 | } | |
14405 | if (need_vex && vex.prefix) | |
14406 | { | |
14407 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14408 | *obufp++ = 'd'; | |
14409 | else | |
14410 | *obufp++ = 's'; | |
14411 | } | |
041bd2e0 | 14412 | else |
f16cd0d5 L |
14413 | { |
14414 | if (prefixes & PREFIX_DATA) | |
14415 | *obufp++ = 'd'; | |
14416 | else | |
14417 | *obufp++ = 's'; | |
14418 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14419 | } | |
041bd2e0 | 14420 | break; |
76f227a5 | 14421 | case 'Y': |
c0f3af97 | 14422 | if (l == 0 && len == 1) |
9646c87b | 14423 | abort (); |
c0f3af97 L |
14424 | else |
14425 | { | |
14426 | if (l != 1 || len != 2 || last[0] != 'X') | |
14427 | { | |
14428 | SAVE_LAST (*p); | |
14429 | break; | |
14430 | } | |
14431 | if (!need_vex) | |
14432 | abort (); | |
14433 | if (intel_syntax | |
04d824a4 | 14434 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14435 | break; |
14436 | switch (vex.length) | |
14437 | { | |
14438 | case 128: | |
14439 | *obufp++ = 'x'; | |
14440 | break; | |
14441 | case 256: | |
14442 | *obufp++ = 'y'; | |
14443 | break; | |
04d824a4 JB |
14444 | case 512: |
14445 | if (!vex.evex) | |
c0f3af97 | 14446 | default: |
04d824a4 | 14447 | abort (); |
c0f3af97 | 14448 | } |
76f227a5 JH |
14449 | } |
14450 | break; | |
252b5132 | 14451 | case 'W': |
0bfee649 | 14452 | if (l == 0 && len == 1) |
a35ca55a | 14453 | { |
0bfee649 L |
14454 | /* operand size flag for cwtl, cbtw */ |
14455 | USED_REX (REX_W); | |
14456 | if (rex & REX_W) | |
14457 | { | |
14458 | if (intel_syntax) | |
14459 | *obufp++ = 'd'; | |
14460 | else | |
14461 | *obufp++ = 'l'; | |
14462 | } | |
14463 | else if (sizeflag & DFLAG) | |
14464 | *obufp++ = 'w'; | |
a35ca55a | 14465 | else |
0bfee649 L |
14466 | *obufp++ = 'b'; |
14467 | if (!(rex & REX_W)) | |
14468 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14469 | } |
252b5132 | 14470 | else |
0bfee649 | 14471 | { |
6c30d220 L |
14472 | if (l != 1 |
14473 | || len != 2 | |
14474 | || (last[0] != 'X' | |
14475 | && last[0] != 'L')) | |
0bfee649 L |
14476 | { |
14477 | SAVE_LAST (*p); | |
14478 | break; | |
14479 | } | |
14480 | if (!need_vex) | |
14481 | abort (); | |
6c30d220 L |
14482 | if (last[0] == 'X') |
14483 | *obufp++ = vex.w ? 'd': 's'; | |
14484 | else | |
14485 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14486 | } |
252b5132 | 14487 | break; |
a72d2af2 L |
14488 | case '^': |
14489 | if (intel_syntax) | |
14490 | break; | |
14491 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14492 | { | |
14493 | if (sizeflag & DFLAG) | |
14494 | *obufp++ = 'l'; | |
14495 | else | |
14496 | *obufp++ = 'w'; | |
14497 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14498 | } | |
14499 | break; | |
5db04b09 L |
14500 | case '@': |
14501 | if (intel_syntax) | |
14502 | break; | |
14503 | if (address_mode == mode_64bit | |
14504 | && (isa64 == intel64 | |
14505 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14506 | *obufp++ = 'q'; | |
14507 | else if ((prefixes & PREFIX_DATA)) | |
14508 | { | |
14509 | if (!(sizeflag & DFLAG)) | |
14510 | *obufp++ = 'w'; | |
14511 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14512 | } | |
14513 | break; | |
252b5132 | 14514 | } |
9306ca4a | 14515 | alt = 0; |
252b5132 RH |
14516 | } |
14517 | *obufp = 0; | |
ea397f5b | 14518 | mnemonicendp = obufp; |
6439fc28 | 14519 | return 0; |
252b5132 RH |
14520 | } |
14521 | ||
14522 | static void | |
26ca5450 | 14523 | oappend (const char *s) |
252b5132 | 14524 | { |
ea397f5b | 14525 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14526 | } |
14527 | ||
14528 | static void | |
26ca5450 | 14529 | append_seg (void) |
252b5132 | 14530 | { |
285ca992 L |
14531 | /* Only print the active segment register. */ |
14532 | if (!active_seg_prefix) | |
14533 | return; | |
14534 | ||
14535 | used_prefixes |= active_seg_prefix; | |
14536 | switch (active_seg_prefix) | |
7d421014 | 14537 | { |
285ca992 | 14538 | case PREFIX_CS: |
9ce09ba2 | 14539 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14540 | break; |
14541 | case PREFIX_DS: | |
9ce09ba2 | 14542 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14543 | break; |
14544 | case PREFIX_SS: | |
9ce09ba2 | 14545 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14546 | break; |
14547 | case PREFIX_ES: | |
9ce09ba2 | 14548 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14549 | break; |
14550 | case PREFIX_FS: | |
9ce09ba2 | 14551 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14552 | break; |
14553 | case PREFIX_GS: | |
9ce09ba2 | 14554 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14555 | break; |
14556 | default: | |
14557 | break; | |
7d421014 | 14558 | } |
252b5132 RH |
14559 | } |
14560 | ||
14561 | static void | |
26ca5450 | 14562 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14563 | { |
14564 | if (!intel_syntax) | |
14565 | oappend ("*"); | |
14566 | OP_E (bytemode, sizeflag); | |
14567 | } | |
14568 | ||
52b15da3 | 14569 | static void |
26ca5450 | 14570 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14571 | { |
cb712a9e | 14572 | if (address_mode == mode_64bit) |
52b15da3 JH |
14573 | { |
14574 | if (hex) | |
14575 | { | |
14576 | char tmp[30]; | |
14577 | int i; | |
14578 | buf[0] = '0'; | |
14579 | buf[1] = 'x'; | |
14580 | sprintf_vma (tmp, disp); | |
6608db57 | 14581 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14582 | strcpy (buf + 2, tmp + i); |
14583 | } | |
14584 | else | |
14585 | { | |
14586 | bfd_signed_vma v = disp; | |
14587 | char tmp[30]; | |
14588 | int i; | |
14589 | if (v < 0) | |
14590 | { | |
14591 | *(buf++) = '-'; | |
14592 | v = -disp; | |
6608db57 | 14593 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14594 | if (v < 0) |
14595 | { | |
14596 | strcpy (buf, "9223372036854775808"); | |
14597 | return; | |
14598 | } | |
14599 | } | |
14600 | if (!v) | |
14601 | { | |
14602 | strcpy (buf, "0"); | |
14603 | return; | |
14604 | } | |
14605 | ||
14606 | i = 0; | |
14607 | tmp[29] = 0; | |
14608 | while (v) | |
14609 | { | |
6608db57 | 14610 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14611 | v /= 10; |
14612 | i++; | |
14613 | } | |
14614 | strcpy (buf, tmp + 29 - i); | |
14615 | } | |
14616 | } | |
14617 | else | |
14618 | { | |
14619 | if (hex) | |
14620 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14621 | else | |
14622 | sprintf (buf, "%d", (int) disp); | |
14623 | } | |
14624 | } | |
14625 | ||
5d669648 L |
14626 | /* Put DISP in BUF as signed hex number. */ |
14627 | ||
14628 | static void | |
14629 | print_displacement (char *buf, bfd_vma disp) | |
14630 | { | |
14631 | bfd_signed_vma val = disp; | |
14632 | char tmp[30]; | |
14633 | int i, j = 0; | |
14634 | ||
14635 | if (val < 0) | |
14636 | { | |
14637 | buf[j++] = '-'; | |
14638 | val = -disp; | |
14639 | ||
14640 | /* Check for possible overflow. */ | |
14641 | if (val < 0) | |
14642 | { | |
14643 | switch (address_mode) | |
14644 | { | |
14645 | case mode_64bit: | |
14646 | strcpy (buf + j, "0x8000000000000000"); | |
14647 | break; | |
14648 | case mode_32bit: | |
14649 | strcpy (buf + j, "0x80000000"); | |
14650 | break; | |
14651 | case mode_16bit: | |
14652 | strcpy (buf + j, "0x8000"); | |
14653 | break; | |
14654 | } | |
14655 | return; | |
14656 | } | |
14657 | } | |
14658 | ||
14659 | buf[j++] = '0'; | |
14660 | buf[j++] = 'x'; | |
14661 | ||
0af1713e | 14662 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14663 | for (i = 0; tmp[i] == '0'; i++) |
14664 | continue; | |
14665 | if (tmp[i] == '\0') | |
14666 | i--; | |
14667 | strcpy (buf + j, tmp + i); | |
14668 | } | |
14669 | ||
3f31e633 JB |
14670 | static void |
14671 | intel_operand_size (int bytemode, int sizeflag) | |
14672 | { | |
43234a1e L |
14673 | if (vex.evex |
14674 | && vex.b | |
14675 | && (bytemode == x_mode | |
14676 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14677 | { | |
14678 | if (vex.w) | |
14679 | oappend ("QWORD PTR "); | |
14680 | else | |
14681 | oappend ("DWORD PTR "); | |
14682 | return; | |
14683 | } | |
3f31e633 JB |
14684 | switch (bytemode) |
14685 | { | |
14686 | case b_mode: | |
b6169b20 | 14687 | case b_swap_mode: |
42903f7f | 14688 | case dqb_mode: |
1ba585e8 | 14689 | case db_mode: |
3f31e633 JB |
14690 | oappend ("BYTE PTR "); |
14691 | break; | |
14692 | case w_mode: | |
1ba585e8 | 14693 | case dw_mode: |
3f31e633 JB |
14694 | case dqw_mode: |
14695 | oappend ("WORD PTR "); | |
14696 | break; | |
07f5af7d L |
14697 | case indir_v_mode: |
14698 | if (address_mode == mode_64bit && isa64 == intel64) | |
14699 | { | |
14700 | oappend ("QWORD PTR "); | |
14701 | break; | |
14702 | } | |
1a0670f3 | 14703 | /* Fall through. */ |
1a114b12 | 14704 | case stack_v_mode: |
7bb15c6f | 14705 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14706 | { |
14707 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14708 | break; |
14709 | } | |
1a0670f3 | 14710 | /* Fall through. */ |
3f31e633 | 14711 | case v_mode: |
b6169b20 | 14712 | case v_swap_mode: |
3f31e633 | 14713 | case dq_mode: |
161a04f6 L |
14714 | USED_REX (REX_W); |
14715 | if (rex & REX_W) | |
3f31e633 | 14716 | oappend ("QWORD PTR "); |
3f31e633 | 14717 | else |
f16cd0d5 L |
14718 | { |
14719 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14720 | oappend ("DWORD PTR "); | |
14721 | else | |
14722 | oappend ("WORD PTR "); | |
14723 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14724 | } | |
3f31e633 | 14725 | break; |
52fd6d94 | 14726 | case z_mode: |
161a04f6 | 14727 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14728 | *obufp++ = 'D'; |
14729 | oappend ("WORD PTR "); | |
161a04f6 | 14730 | if (!(rex & REX_W)) |
52fd6d94 JB |
14731 | used_prefixes |= (prefixes & PREFIX_DATA); |
14732 | break; | |
34b772a6 JB |
14733 | case a_mode: |
14734 | if (sizeflag & DFLAG) | |
14735 | oappend ("QWORD PTR "); | |
14736 | else | |
14737 | oappend ("DWORD PTR "); | |
14738 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14739 | break; | |
3f31e633 | 14740 | case d_mode: |
539f890d L |
14741 | case d_scalar_mode: |
14742 | case d_scalar_swap_mode: | |
fa99fab2 | 14743 | case d_swap_mode: |
42903f7f | 14744 | case dqd_mode: |
3f31e633 JB |
14745 | oappend ("DWORD PTR "); |
14746 | break; | |
14747 | case q_mode: | |
539f890d L |
14748 | case q_scalar_mode: |
14749 | case q_scalar_swap_mode: | |
b6169b20 | 14750 | case q_swap_mode: |
3f31e633 JB |
14751 | oappend ("QWORD PTR "); |
14752 | break; | |
14753 | case m_mode: | |
cb712a9e | 14754 | if (address_mode == mode_64bit) |
3f31e633 JB |
14755 | oappend ("QWORD PTR "); |
14756 | else | |
14757 | oappend ("DWORD PTR "); | |
14758 | break; | |
14759 | case f_mode: | |
14760 | if (sizeflag & DFLAG) | |
14761 | oappend ("FWORD PTR "); | |
14762 | else | |
14763 | oappend ("DWORD PTR "); | |
14764 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14765 | break; | |
14766 | case t_mode: | |
14767 | oappend ("TBYTE PTR "); | |
14768 | break; | |
14769 | case x_mode: | |
b6169b20 | 14770 | case x_swap_mode: |
43234a1e L |
14771 | case evex_x_gscat_mode: |
14772 | case evex_x_nobcst_mode: | |
53467f57 IT |
14773 | case b_scalar_mode: |
14774 | case w_scalar_mode: | |
c0f3af97 L |
14775 | if (need_vex) |
14776 | { | |
14777 | switch (vex.length) | |
14778 | { | |
14779 | case 128: | |
14780 | oappend ("XMMWORD PTR "); | |
14781 | break; | |
14782 | case 256: | |
14783 | oappend ("YMMWORD PTR "); | |
14784 | break; | |
43234a1e L |
14785 | case 512: |
14786 | oappend ("ZMMWORD PTR "); | |
14787 | break; | |
c0f3af97 L |
14788 | default: |
14789 | abort (); | |
14790 | } | |
14791 | } | |
14792 | else | |
14793 | oappend ("XMMWORD PTR "); | |
14794 | break; | |
14795 | case xmm_mode: | |
3f31e633 JB |
14796 | oappend ("XMMWORD PTR "); |
14797 | break; | |
43234a1e L |
14798 | case ymm_mode: |
14799 | oappend ("YMMWORD PTR "); | |
14800 | break; | |
c0f3af97 | 14801 | case xmmq_mode: |
43234a1e | 14802 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14803 | if (!need_vex) |
14804 | abort (); | |
14805 | ||
14806 | switch (vex.length) | |
14807 | { | |
14808 | case 128: | |
14809 | oappend ("QWORD PTR "); | |
14810 | break; | |
14811 | case 256: | |
14812 | oappend ("XMMWORD PTR "); | |
14813 | break; | |
43234a1e L |
14814 | case 512: |
14815 | oappend ("YMMWORD PTR "); | |
14816 | break; | |
c0f3af97 L |
14817 | default: |
14818 | abort (); | |
14819 | } | |
14820 | break; | |
6c30d220 L |
14821 | case xmm_mb_mode: |
14822 | if (!need_vex) | |
14823 | abort (); | |
14824 | ||
14825 | switch (vex.length) | |
14826 | { | |
14827 | case 128: | |
14828 | case 256: | |
43234a1e | 14829 | case 512: |
6c30d220 L |
14830 | oappend ("BYTE PTR "); |
14831 | break; | |
14832 | default: | |
14833 | abort (); | |
14834 | } | |
14835 | break; | |
14836 | case xmm_mw_mode: | |
14837 | if (!need_vex) | |
14838 | abort (); | |
14839 | ||
14840 | switch (vex.length) | |
14841 | { | |
14842 | case 128: | |
14843 | case 256: | |
43234a1e | 14844 | case 512: |
6c30d220 L |
14845 | oappend ("WORD PTR "); |
14846 | break; | |
14847 | default: | |
14848 | abort (); | |
14849 | } | |
14850 | break; | |
14851 | case xmm_md_mode: | |
14852 | if (!need_vex) | |
14853 | abort (); | |
14854 | ||
14855 | switch (vex.length) | |
14856 | { | |
14857 | case 128: | |
14858 | case 256: | |
43234a1e | 14859 | case 512: |
6c30d220 L |
14860 | oappend ("DWORD PTR "); |
14861 | break; | |
14862 | default: | |
14863 | abort (); | |
14864 | } | |
14865 | break; | |
14866 | case xmm_mq_mode: | |
14867 | if (!need_vex) | |
14868 | abort (); | |
14869 | ||
14870 | switch (vex.length) | |
14871 | { | |
14872 | case 128: | |
14873 | case 256: | |
43234a1e | 14874 | case 512: |
6c30d220 L |
14875 | oappend ("QWORD PTR "); |
14876 | break; | |
14877 | default: | |
14878 | abort (); | |
14879 | } | |
14880 | break; | |
14881 | case xmmdw_mode: | |
14882 | if (!need_vex) | |
14883 | abort (); | |
14884 | ||
14885 | switch (vex.length) | |
14886 | { | |
14887 | case 128: | |
14888 | oappend ("WORD PTR "); | |
14889 | break; | |
14890 | case 256: | |
14891 | oappend ("DWORD PTR "); | |
14892 | break; | |
43234a1e L |
14893 | case 512: |
14894 | oappend ("QWORD PTR "); | |
14895 | break; | |
6c30d220 L |
14896 | default: |
14897 | abort (); | |
14898 | } | |
14899 | break; | |
14900 | case xmmqd_mode: | |
14901 | if (!need_vex) | |
14902 | abort (); | |
14903 | ||
14904 | switch (vex.length) | |
14905 | { | |
14906 | case 128: | |
14907 | oappend ("DWORD PTR "); | |
14908 | break; | |
14909 | case 256: | |
14910 | oappend ("QWORD PTR "); | |
14911 | break; | |
43234a1e L |
14912 | case 512: |
14913 | oappend ("XMMWORD PTR "); | |
14914 | break; | |
6c30d220 L |
14915 | default: |
14916 | abort (); | |
14917 | } | |
14918 | break; | |
c0f3af97 L |
14919 | case ymmq_mode: |
14920 | if (!need_vex) | |
14921 | abort (); | |
14922 | ||
14923 | switch (vex.length) | |
14924 | { | |
14925 | case 128: | |
14926 | oappend ("QWORD PTR "); | |
14927 | break; | |
14928 | case 256: | |
14929 | oappend ("YMMWORD PTR "); | |
14930 | break; | |
43234a1e L |
14931 | case 512: |
14932 | oappend ("ZMMWORD PTR "); | |
14933 | break; | |
c0f3af97 L |
14934 | default: |
14935 | abort (); | |
14936 | } | |
14937 | break; | |
6c30d220 L |
14938 | case ymmxmm_mode: |
14939 | if (!need_vex) | |
14940 | abort (); | |
14941 | ||
14942 | switch (vex.length) | |
14943 | { | |
14944 | case 128: | |
14945 | case 256: | |
14946 | oappend ("XMMWORD PTR "); | |
14947 | break; | |
14948 | default: | |
14949 | abort (); | |
14950 | } | |
14951 | break; | |
fb9c77c7 L |
14952 | case o_mode: |
14953 | oappend ("OWORD PTR "); | |
14954 | break; | |
43234a1e | 14955 | case xmm_mdq_mode: |
0bfee649 | 14956 | case vex_w_dq_mode: |
1c480963 | 14957 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14958 | if (!need_vex) |
14959 | abort (); | |
14960 | ||
14961 | if (vex.w) | |
14962 | oappend ("QWORD PTR "); | |
14963 | else | |
14964 | oappend ("DWORD PTR "); | |
14965 | break; | |
43234a1e L |
14966 | case vex_vsib_d_w_dq_mode: |
14967 | case vex_vsib_q_w_dq_mode: | |
14968 | if (!need_vex) | |
14969 | abort (); | |
14970 | ||
14971 | if (!vex.evex) | |
14972 | { | |
14973 | if (vex.w) | |
14974 | oappend ("QWORD PTR "); | |
14975 | else | |
14976 | oappend ("DWORD PTR "); | |
14977 | } | |
14978 | else | |
14979 | { | |
b28d1bda IT |
14980 | switch (vex.length) |
14981 | { | |
14982 | case 128: | |
14983 | oappend ("XMMWORD PTR "); | |
14984 | break; | |
14985 | case 256: | |
14986 | oappend ("YMMWORD PTR "); | |
14987 | break; | |
14988 | case 512: | |
14989 | oappend ("ZMMWORD PTR "); | |
14990 | break; | |
14991 | default: | |
14992 | abort (); | |
14993 | } | |
43234a1e L |
14994 | } |
14995 | break; | |
5fc35d96 IT |
14996 | case vex_vsib_q_w_d_mode: |
14997 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14998 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14999 | abort (); |
15000 | ||
b28d1bda IT |
15001 | switch (vex.length) |
15002 | { | |
15003 | case 128: | |
15004 | oappend ("QWORD PTR "); | |
15005 | break; | |
15006 | case 256: | |
15007 | oappend ("XMMWORD PTR "); | |
15008 | break; | |
15009 | case 512: | |
15010 | oappend ("YMMWORD PTR "); | |
15011 | break; | |
15012 | default: | |
15013 | abort (); | |
15014 | } | |
5fc35d96 IT |
15015 | |
15016 | break; | |
1ba585e8 IT |
15017 | case mask_bd_mode: |
15018 | if (!need_vex || vex.length != 128) | |
15019 | abort (); | |
15020 | if (vex.w) | |
15021 | oappend ("DWORD PTR "); | |
15022 | else | |
15023 | oappend ("BYTE PTR "); | |
15024 | break; | |
43234a1e L |
15025 | case mask_mode: |
15026 | if (!need_vex) | |
15027 | abort (); | |
1ba585e8 IT |
15028 | if (vex.w) |
15029 | oappend ("QWORD PTR "); | |
15030 | else | |
15031 | oappend ("WORD PTR "); | |
43234a1e | 15032 | break; |
6c75cc62 | 15033 | case v_bnd_mode: |
3f31e633 JB |
15034 | default: |
15035 | break; | |
15036 | } | |
15037 | } | |
15038 | ||
252b5132 | 15039 | static void |
c0f3af97 | 15040 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15041 | { |
c0f3af97 L |
15042 | int reg = modrm.rm; |
15043 | const char **names; | |
252b5132 | 15044 | |
c0f3af97 L |
15045 | USED_REX (REX_B); |
15046 | if ((rex & REX_B)) | |
15047 | reg += 8; | |
252b5132 | 15048 | |
b6169b20 | 15049 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 15050 | && (bytemode == b_swap_mode |
9f79e886 | 15051 | || bytemode == bnd_swap_mode |
60227d64 | 15052 | || bytemode == v_swap_mode)) |
b6169b20 L |
15053 | swap_operand (); |
15054 | ||
c0f3af97 | 15055 | switch (bytemode) |
252b5132 | 15056 | { |
c0f3af97 | 15057 | case b_mode: |
b6169b20 | 15058 | case b_swap_mode: |
c0f3af97 L |
15059 | USED_REX (0); |
15060 | if (rex) | |
15061 | names = names8rex; | |
15062 | else | |
15063 | names = names8; | |
15064 | break; | |
15065 | case w_mode: | |
15066 | names = names16; | |
15067 | break; | |
15068 | case d_mode: | |
1ba585e8 IT |
15069 | case dw_mode: |
15070 | case db_mode: | |
c0f3af97 L |
15071 | names = names32; |
15072 | break; | |
15073 | case q_mode: | |
15074 | names = names64; | |
15075 | break; | |
15076 | case m_mode: | |
6c75cc62 | 15077 | case v_bnd_mode: |
c0f3af97 L |
15078 | names = address_mode == mode_64bit ? names64 : names32; |
15079 | break; | |
7e8b059b | 15080 | case bnd_mode: |
9f79e886 | 15081 | case bnd_swap_mode: |
0d96e4df L |
15082 | if (reg > 0x3) |
15083 | { | |
15084 | oappend ("(bad)"); | |
15085 | return; | |
15086 | } | |
7e8b059b L |
15087 | names = names_bnd; |
15088 | break; | |
07f5af7d L |
15089 | case indir_v_mode: |
15090 | if (address_mode == mode_64bit && isa64 == intel64) | |
15091 | { | |
15092 | names = names64; | |
15093 | break; | |
15094 | } | |
1a0670f3 | 15095 | /* Fall through. */ |
c0f3af97 | 15096 | case stack_v_mode: |
7bb15c6f | 15097 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15098 | { |
c0f3af97 | 15099 | names = names64; |
252b5132 | 15100 | break; |
252b5132 | 15101 | } |
c0f3af97 | 15102 | bytemode = v_mode; |
1a0670f3 | 15103 | /* Fall through. */ |
c0f3af97 | 15104 | case v_mode: |
b6169b20 | 15105 | case v_swap_mode: |
c0f3af97 L |
15106 | case dq_mode: |
15107 | case dqb_mode: | |
15108 | case dqd_mode: | |
15109 | case dqw_mode: | |
15110 | USED_REX (REX_W); | |
15111 | if (rex & REX_W) | |
15112 | names = names64; | |
c0f3af97 | 15113 | else |
f16cd0d5 | 15114 | { |
7bb15c6f | 15115 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15116 | || (bytemode != v_mode |
15117 | && bytemode != v_swap_mode)) | |
15118 | names = names32; | |
15119 | else | |
15120 | names = names16; | |
15121 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15122 | } | |
c0f3af97 | 15123 | break; |
de89d0a3 IT |
15124 | case va_mode: |
15125 | names = (address_mode == mode_64bit | |
15126 | ? names64 : names32); | |
15127 | if (!(prefixes & PREFIX_ADDR)) | |
15128 | names = (address_mode == mode_16bit | |
15129 | ? names16 : names); | |
15130 | else | |
15131 | { | |
15132 | /* Remove "addr16/addr32". */ | |
15133 | all_prefixes[last_addr_prefix] = 0; | |
15134 | names = (address_mode != mode_32bit | |
15135 | ? names32 : names16); | |
15136 | used_prefixes |= PREFIX_ADDR; | |
15137 | } | |
15138 | break; | |
1ba585e8 | 15139 | case mask_bd_mode: |
43234a1e | 15140 | case mask_mode: |
9889cbb1 L |
15141 | if (reg > 0x7) |
15142 | { | |
15143 | oappend ("(bad)"); | |
15144 | return; | |
15145 | } | |
43234a1e L |
15146 | names = names_mask; |
15147 | break; | |
c0f3af97 L |
15148 | case 0: |
15149 | return; | |
15150 | default: | |
15151 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15152 | return; |
15153 | } | |
c0f3af97 L |
15154 | oappend (names[reg]); |
15155 | } | |
15156 | ||
15157 | static void | |
c1e679ec | 15158 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15159 | { |
15160 | bfd_vma disp = 0; | |
15161 | int add = (rex & REX_B) ? 8 : 0; | |
15162 | int riprel = 0; | |
43234a1e L |
15163 | int shift; |
15164 | ||
15165 | if (vex.evex) | |
15166 | { | |
15167 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15168 | if (vex.b | |
15169 | && bytemode != x_mode | |
90a915bf | 15170 | && bytemode != xmmq_mode |
43234a1e L |
15171 | && bytemode != evex_half_bcst_xmmq_mode) |
15172 | { | |
15173 | BadOp (); | |
15174 | return; | |
15175 | } | |
15176 | switch (bytemode) | |
15177 | { | |
1ba585e8 IT |
15178 | case dqw_mode: |
15179 | case dw_mode: | |
1ba585e8 IT |
15180 | shift = 1; |
15181 | break; | |
15182 | case dqb_mode: | |
15183 | case db_mode: | |
15184 | shift = 0; | |
15185 | break; | |
43234a1e | 15186 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15187 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15188 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15189 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15190 | case evex_x_gscat_mode: |
15191 | case xmm_mdq_mode: | |
15192 | shift = vex.w ? 3 : 2; | |
15193 | break; | |
43234a1e L |
15194 | case x_mode: |
15195 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15196 | case xmmq_mode: |
43234a1e L |
15197 | if (vex.b) |
15198 | { | |
15199 | shift = vex.w ? 3 : 2; | |
15200 | break; | |
15201 | } | |
1a0670f3 | 15202 | /* Fall through. */ |
43234a1e L |
15203 | case xmmqd_mode: |
15204 | case xmmdw_mode: | |
43234a1e L |
15205 | case ymmq_mode: |
15206 | case evex_x_nobcst_mode: | |
15207 | case x_swap_mode: | |
15208 | switch (vex.length) | |
15209 | { | |
15210 | case 128: | |
15211 | shift = 4; | |
15212 | break; | |
15213 | case 256: | |
15214 | shift = 5; | |
15215 | break; | |
15216 | case 512: | |
15217 | shift = 6; | |
15218 | break; | |
15219 | default: | |
15220 | abort (); | |
15221 | } | |
15222 | break; | |
15223 | case ymm_mode: | |
15224 | shift = 5; | |
15225 | break; | |
15226 | case xmm_mode: | |
15227 | shift = 4; | |
15228 | break; | |
15229 | case xmm_mq_mode: | |
15230 | case q_mode: | |
15231 | case q_scalar_mode: | |
15232 | case q_swap_mode: | |
15233 | case q_scalar_swap_mode: | |
15234 | shift = 3; | |
15235 | break; | |
15236 | case dqd_mode: | |
15237 | case xmm_md_mode: | |
15238 | case d_mode: | |
15239 | case d_scalar_mode: | |
15240 | case d_swap_mode: | |
15241 | case d_scalar_swap_mode: | |
15242 | shift = 2; | |
15243 | break; | |
53467f57 | 15244 | case w_scalar_mode: |
43234a1e L |
15245 | case xmm_mw_mode: |
15246 | shift = 1; | |
15247 | break; | |
53467f57 | 15248 | case b_scalar_mode: |
43234a1e L |
15249 | case xmm_mb_mode: |
15250 | shift = 0; | |
15251 | break; | |
15252 | default: | |
15253 | abort (); | |
15254 | } | |
15255 | /* Make necessary corrections to shift for modes that need it. | |
15256 | For these modes we currently have shift 4, 5 or 6 depending on | |
15257 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15258 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15259 | xmmq_mode). In case of broadcast enabled the corrections | |
15260 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15261 | if (!vex.b |
15262 | && (bytemode == xmmq_mode | |
15263 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15264 | shift -= 1; |
15265 | else if (bytemode == xmmqd_mode) | |
15266 | shift -= 2; | |
15267 | else if (bytemode == xmmdw_mode) | |
15268 | shift -= 3; | |
b28d1bda IT |
15269 | else if (bytemode == ymmq_mode && vex.length == 128) |
15270 | shift -= 1; | |
43234a1e L |
15271 | } |
15272 | else | |
15273 | shift = 0; | |
252b5132 | 15274 | |
c0f3af97 | 15275 | USED_REX (REX_B); |
3f31e633 JB |
15276 | if (intel_syntax) |
15277 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15278 | append_seg (); |
15279 | ||
5d669648 | 15280 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15281 | { |
5d669648 L |
15282 | /* 32/64 bit address mode */ |
15283 | int havedisp; | |
252b5132 RH |
15284 | int havesib; |
15285 | int havebase; | |
0f7da397 | 15286 | int haveindex; |
20afcfb7 | 15287 | int needindex; |
82c18208 | 15288 | int base, rbase; |
91d6fa6a | 15289 | int vindex = 0; |
252b5132 | 15290 | int scale = 0; |
7e8b059b L |
15291 | int addr32flag = !((sizeflag & AFLAG) |
15292 | || bytemode == v_bnd_mode | |
9f79e886 JB |
15293 | || bytemode == bnd_mode |
15294 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
15295 | const char **indexes64 = names64; |
15296 | const char **indexes32 = names32; | |
252b5132 RH |
15297 | |
15298 | havesib = 0; | |
15299 | havebase = 1; | |
0f7da397 | 15300 | haveindex = 0; |
7967e09e | 15301 | base = modrm.rm; |
252b5132 RH |
15302 | |
15303 | if (base == 4) | |
15304 | { | |
15305 | havesib = 1; | |
dfc8cf43 | 15306 | vindex = sib.index; |
161a04f6 L |
15307 | USED_REX (REX_X); |
15308 | if (rex & REX_X) | |
91d6fa6a | 15309 | vindex += 8; |
6c30d220 L |
15310 | switch (bytemode) |
15311 | { | |
15312 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15313 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15314 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15315 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15316 | if (!need_vex) |
15317 | abort (); | |
43234a1e L |
15318 | if (vex.evex) |
15319 | { | |
15320 | if (!vex.v) | |
15321 | vindex += 16; | |
15322 | } | |
6c30d220 L |
15323 | |
15324 | haveindex = 1; | |
15325 | switch (vex.length) | |
15326 | { | |
15327 | case 128: | |
7bb15c6f | 15328 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15329 | break; |
15330 | case 256: | |
5fc35d96 IT |
15331 | if (!vex.w |
15332 | || bytemode == vex_vsib_q_w_dq_mode | |
15333 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15334 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15335 | else |
7bb15c6f | 15336 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15337 | break; |
43234a1e | 15338 | case 512: |
5fc35d96 IT |
15339 | if (!vex.w |
15340 | || bytemode == vex_vsib_q_w_dq_mode | |
15341 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15342 | indexes64 = indexes32 = names_zmm; |
15343 | else | |
15344 | indexes64 = indexes32 = names_ymm; | |
15345 | break; | |
6c30d220 L |
15346 | default: |
15347 | abort (); | |
15348 | } | |
15349 | break; | |
15350 | default: | |
15351 | haveindex = vindex != 4; | |
15352 | break; | |
15353 | } | |
15354 | scale = sib.scale; | |
15355 | base = sib.base; | |
252b5132 RH |
15356 | codep++; |
15357 | } | |
82c18208 | 15358 | rbase = base + add; |
252b5132 | 15359 | |
7967e09e | 15360 | switch (modrm.mod) |
252b5132 RH |
15361 | { |
15362 | case 0: | |
82c18208 | 15363 | if (base == 5) |
252b5132 RH |
15364 | { |
15365 | havebase = 0; | |
cb712a9e | 15366 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15367 | riprel = 1; |
15368 | disp = get32s (); | |
252b5132 RH |
15369 | } |
15370 | break; | |
15371 | case 1: | |
15372 | FETCH_DATA (the_info, codep + 1); | |
15373 | disp = *codep++; | |
15374 | if ((disp & 0x80) != 0) | |
15375 | disp -= 0x100; | |
43234a1e L |
15376 | if (vex.evex && shift > 0) |
15377 | disp <<= shift; | |
252b5132 RH |
15378 | break; |
15379 | case 2: | |
52b15da3 | 15380 | disp = get32s (); |
252b5132 RH |
15381 | break; |
15382 | } | |
15383 | ||
20afcfb7 L |
15384 | /* In 32bit mode, we need index register to tell [offset] from |
15385 | [eiz*1 + offset]. */ | |
15386 | needindex = (havesib | |
15387 | && !havebase | |
15388 | && !haveindex | |
15389 | && address_mode == mode_32bit); | |
15390 | havedisp = (havebase | |
15391 | || needindex | |
15392 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15393 | |
252b5132 | 15394 | if (!intel_syntax) |
82c18208 | 15395 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15396 | { |
5d669648 L |
15397 | if (havedisp || riprel) |
15398 | print_displacement (scratchbuf, disp); | |
15399 | else | |
15400 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15401 | oappend (scratchbuf); |
52b15da3 JH |
15402 | if (riprel) |
15403 | { | |
15404 | set_op (disp, 1); | |
28596323 | 15405 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15406 | } |
db6eb5be | 15407 | } |
2da11e11 | 15408 | |
7e8b059b L |
15409 | if ((havebase || haveindex || riprel) |
15410 | && (bytemode != v_bnd_mode) | |
9f79e886 JB |
15411 | && (bytemode != bnd_mode) |
15412 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
15413 | used_prefixes |= PREFIX_ADDR; |
15414 | ||
5d669648 | 15415 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15416 | { |
252b5132 | 15417 | *obufp++ = open_char; |
52b15da3 | 15418 | if (intel_syntax && riprel) |
185b1163 L |
15419 | { |
15420 | set_op (disp, 1); | |
28596323 | 15421 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15422 | } |
db6eb5be | 15423 | *obufp = '\0'; |
252b5132 | 15424 | if (havebase) |
7e8b059b | 15425 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15426 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15427 | if (havesib) |
15428 | { | |
db51cc60 L |
15429 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15430 | print index to tell base + index from base. */ | |
15431 | if (scale != 0 | |
20afcfb7 | 15432 | || needindex |
db51cc60 L |
15433 | || haveindex |
15434 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15435 | { |
9306ca4a | 15436 | if (!intel_syntax || havebase) |
db6eb5be | 15437 | { |
9306ca4a JB |
15438 | *obufp++ = separator_char; |
15439 | *obufp = '\0'; | |
db6eb5be | 15440 | } |
db51cc60 | 15441 | if (haveindex) |
7e8b059b | 15442 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15443 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15444 | else |
7e8b059b | 15445 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15446 | ? index64 : index32); |
15447 | ||
db6eb5be AM |
15448 | *obufp++ = scale_char; |
15449 | *obufp = '\0'; | |
15450 | sprintf (scratchbuf, "%d", 1 << scale); | |
15451 | oappend (scratchbuf); | |
15452 | } | |
252b5132 | 15453 | } |
185b1163 | 15454 | if (intel_syntax |
82c18208 | 15455 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15456 | { |
db51cc60 | 15457 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15458 | { |
15459 | *obufp++ = '+'; | |
15460 | *obufp = '\0'; | |
15461 | } | |
05203043 | 15462 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15463 | { |
15464 | *obufp++ = '-'; | |
15465 | *obufp = '\0'; | |
15466 | disp = - (bfd_signed_vma) disp; | |
15467 | } | |
15468 | ||
db51cc60 L |
15469 | if (havedisp) |
15470 | print_displacement (scratchbuf, disp); | |
15471 | else | |
15472 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15473 | oappend (scratchbuf); |
15474 | } | |
252b5132 RH |
15475 | |
15476 | *obufp++ = close_char; | |
db6eb5be | 15477 | *obufp = '\0'; |
252b5132 RH |
15478 | } |
15479 | else if (intel_syntax) | |
db6eb5be | 15480 | { |
82c18208 | 15481 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15482 | { |
285ca992 | 15483 | if (!active_seg_prefix) |
252b5132 | 15484 | { |
d708bcba | 15485 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15486 | oappend (":"); |
15487 | } | |
52b15da3 | 15488 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15489 | oappend (scratchbuf); |
15490 | } | |
15491 | } | |
252b5132 RH |
15492 | } |
15493 | else | |
f16cd0d5 L |
15494 | { |
15495 | /* 16 bit address mode */ | |
15496 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15497 | switch (modrm.mod) |
252b5132 RH |
15498 | { |
15499 | case 0: | |
7967e09e | 15500 | if (modrm.rm == 6) |
252b5132 RH |
15501 | { |
15502 | disp = get16 (); | |
15503 | if ((disp & 0x8000) != 0) | |
15504 | disp -= 0x10000; | |
15505 | } | |
15506 | break; | |
15507 | case 1: | |
15508 | FETCH_DATA (the_info, codep + 1); | |
15509 | disp = *codep++; | |
15510 | if ((disp & 0x80) != 0) | |
15511 | disp -= 0x100; | |
65f3ed04 JB |
15512 | if (vex.evex && shift > 0) |
15513 | disp <<= shift; | |
252b5132 RH |
15514 | break; |
15515 | case 2: | |
15516 | disp = get16 (); | |
15517 | if ((disp & 0x8000) != 0) | |
15518 | disp -= 0x10000; | |
15519 | break; | |
15520 | } | |
15521 | ||
15522 | if (!intel_syntax) | |
7967e09e | 15523 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15524 | { |
5d669648 | 15525 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15526 | oappend (scratchbuf); |
15527 | } | |
252b5132 | 15528 | |
7967e09e | 15529 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15530 | { |
15531 | *obufp++ = open_char; | |
db6eb5be | 15532 | *obufp = '\0'; |
7967e09e | 15533 | oappend (index16[modrm.rm]); |
5d669648 L |
15534 | if (intel_syntax |
15535 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15536 | { |
5d669648 | 15537 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15538 | { |
15539 | *obufp++ = '+'; | |
15540 | *obufp = '\0'; | |
15541 | } | |
7967e09e | 15542 | else if (modrm.mod != 1) |
3d456fa1 JB |
15543 | { |
15544 | *obufp++ = '-'; | |
15545 | *obufp = '\0'; | |
15546 | disp = - (bfd_signed_vma) disp; | |
15547 | } | |
15548 | ||
5d669648 | 15549 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15550 | oappend (scratchbuf); |
15551 | } | |
15552 | ||
db6eb5be AM |
15553 | *obufp++ = close_char; |
15554 | *obufp = '\0'; | |
252b5132 | 15555 | } |
3d456fa1 JB |
15556 | else if (intel_syntax) |
15557 | { | |
285ca992 | 15558 | if (!active_seg_prefix) |
3d456fa1 JB |
15559 | { |
15560 | oappend (names_seg[ds_reg - es_reg]); | |
15561 | oappend (":"); | |
15562 | } | |
15563 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15564 | oappend (scratchbuf); | |
15565 | } | |
252b5132 | 15566 | } |
43234a1e L |
15567 | if (vex.evex && vex.b |
15568 | && (bytemode == x_mode | |
90a915bf | 15569 | || bytemode == xmmq_mode |
43234a1e L |
15570 | || bytemode == evex_half_bcst_xmmq_mode)) |
15571 | { | |
90a915bf IT |
15572 | if (vex.w |
15573 | || bytemode == xmmq_mode | |
15574 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15575 | { |
15576 | switch (vex.length) | |
15577 | { | |
15578 | case 128: | |
15579 | oappend ("{1to2}"); | |
15580 | break; | |
15581 | case 256: | |
15582 | oappend ("{1to4}"); | |
15583 | break; | |
15584 | case 512: | |
15585 | oappend ("{1to8}"); | |
15586 | break; | |
15587 | default: | |
15588 | abort (); | |
15589 | } | |
15590 | } | |
43234a1e | 15591 | else |
b28d1bda IT |
15592 | { |
15593 | switch (vex.length) | |
15594 | { | |
15595 | case 128: | |
15596 | oappend ("{1to4}"); | |
15597 | break; | |
15598 | case 256: | |
15599 | oappend ("{1to8}"); | |
15600 | break; | |
15601 | case 512: | |
15602 | oappend ("{1to16}"); | |
15603 | break; | |
15604 | default: | |
15605 | abort (); | |
15606 | } | |
15607 | } | |
43234a1e | 15608 | } |
252b5132 RH |
15609 | } |
15610 | ||
c0f3af97 | 15611 | static void |
8b3f93e7 | 15612 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15613 | { |
15614 | /* Skip mod/rm byte. */ | |
15615 | MODRM_CHECK; | |
15616 | codep++; | |
15617 | ||
15618 | if (modrm.mod == 3) | |
15619 | OP_E_register (bytemode, sizeflag); | |
15620 | else | |
c1e679ec | 15621 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15622 | } |
15623 | ||
252b5132 | 15624 | static void |
26ca5450 | 15625 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15626 | { |
52b15da3 | 15627 | int add = 0; |
161a04f6 L |
15628 | USED_REX (REX_R); |
15629 | if (rex & REX_R) | |
52b15da3 | 15630 | add += 8; |
252b5132 RH |
15631 | switch (bytemode) |
15632 | { | |
15633 | case b_mode: | |
52b15da3 JH |
15634 | USED_REX (0); |
15635 | if (rex) | |
7967e09e | 15636 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15637 | else |
7967e09e | 15638 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15639 | break; |
15640 | case w_mode: | |
7967e09e | 15641 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15642 | break; |
15643 | case d_mode: | |
1ba585e8 IT |
15644 | case db_mode: |
15645 | case dw_mode: | |
7967e09e | 15646 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15647 | break; |
15648 | case q_mode: | |
7967e09e | 15649 | oappend (names64[modrm.reg + add]); |
252b5132 | 15650 | break; |
7e8b059b | 15651 | case bnd_mode: |
0d96e4df L |
15652 | if (modrm.reg > 0x3) |
15653 | { | |
15654 | oappend ("(bad)"); | |
15655 | return; | |
15656 | } | |
7e8b059b L |
15657 | oappend (names_bnd[modrm.reg]); |
15658 | break; | |
252b5132 | 15659 | case v_mode: |
9306ca4a | 15660 | case dq_mode: |
42903f7f L |
15661 | case dqb_mode: |
15662 | case dqd_mode: | |
9306ca4a | 15663 | case dqw_mode: |
161a04f6 L |
15664 | USED_REX (REX_W); |
15665 | if (rex & REX_W) | |
7967e09e | 15666 | oappend (names64[modrm.reg + add]); |
252b5132 | 15667 | else |
f16cd0d5 L |
15668 | { |
15669 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15670 | oappend (names32[modrm.reg + add]); | |
15671 | else | |
15672 | oappend (names16[modrm.reg + add]); | |
15673 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15674 | } | |
252b5132 | 15675 | break; |
90700ea2 | 15676 | case m_mode: |
cb712a9e | 15677 | if (address_mode == mode_64bit) |
7967e09e | 15678 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15679 | else |
7967e09e | 15680 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15681 | break; |
1ba585e8 | 15682 | case mask_bd_mode: |
43234a1e | 15683 | case mask_mode: |
9889cbb1 L |
15684 | if ((modrm.reg + add) > 0x7) |
15685 | { | |
15686 | oappend ("(bad)"); | |
15687 | return; | |
15688 | } | |
43234a1e L |
15689 | oappend (names_mask[modrm.reg + add]); |
15690 | break; | |
252b5132 RH |
15691 | default: |
15692 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15693 | break; | |
15694 | } | |
15695 | } | |
15696 | ||
52b15da3 | 15697 | static bfd_vma |
26ca5450 | 15698 | get64 (void) |
52b15da3 | 15699 | { |
5dd0794d | 15700 | bfd_vma x; |
52b15da3 | 15701 | #ifdef BFD64 |
5dd0794d AM |
15702 | unsigned int a; |
15703 | unsigned int b; | |
15704 | ||
52b15da3 JH |
15705 | FETCH_DATA (the_info, codep + 8); |
15706 | a = *codep++ & 0xff; | |
15707 | a |= (*codep++ & 0xff) << 8; | |
15708 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15709 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15710 | b = *codep++ & 0xff; |
52b15da3 JH |
15711 | b |= (*codep++ & 0xff) << 8; |
15712 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15713 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15714 | x = a + ((bfd_vma) b << 32); |
15715 | #else | |
6608db57 | 15716 | abort (); |
5dd0794d | 15717 | x = 0; |
52b15da3 JH |
15718 | #endif |
15719 | return x; | |
15720 | } | |
15721 | ||
15722 | static bfd_signed_vma | |
26ca5450 | 15723 | get32 (void) |
252b5132 | 15724 | { |
52b15da3 | 15725 | bfd_signed_vma x = 0; |
252b5132 RH |
15726 | |
15727 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15728 | x = *codep++ & (bfd_signed_vma) 0xff; |
15729 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15730 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15731 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15732 | return x; | |
15733 | } | |
15734 | ||
15735 | static bfd_signed_vma | |
26ca5450 | 15736 | get32s (void) |
52b15da3 JH |
15737 | { |
15738 | bfd_signed_vma x = 0; | |
15739 | ||
15740 | FETCH_DATA (the_info, codep + 4); | |
15741 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15742 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15743 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15744 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15745 | ||
15746 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15747 | ||
252b5132 RH |
15748 | return x; |
15749 | } | |
15750 | ||
15751 | static int | |
26ca5450 | 15752 | get16 (void) |
252b5132 RH |
15753 | { |
15754 | int x = 0; | |
15755 | ||
15756 | FETCH_DATA (the_info, codep + 2); | |
15757 | x = *codep++ & 0xff; | |
15758 | x |= (*codep++ & 0xff) << 8; | |
15759 | return x; | |
15760 | } | |
15761 | ||
15762 | static void | |
26ca5450 | 15763 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15764 | { |
15765 | op_index[op_ad] = op_ad; | |
cb712a9e | 15766 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15767 | { |
15768 | op_address[op_ad] = op; | |
15769 | op_riprel[op_ad] = riprel; | |
15770 | } | |
15771 | else | |
15772 | { | |
15773 | /* Mask to get a 32-bit address. */ | |
15774 | op_address[op_ad] = op & 0xffffffff; | |
15775 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15776 | } | |
252b5132 RH |
15777 | } |
15778 | ||
15779 | static void | |
26ca5450 | 15780 | OP_REG (int code, int sizeflag) |
252b5132 | 15781 | { |
2da11e11 | 15782 | const char *s; |
9b60702d | 15783 | int add; |
de882298 RM |
15784 | |
15785 | switch (code) | |
15786 | { | |
15787 | case es_reg: case ss_reg: case cs_reg: | |
15788 | case ds_reg: case fs_reg: case gs_reg: | |
15789 | oappend (names_seg[code - es_reg]); | |
15790 | return; | |
15791 | } | |
15792 | ||
161a04f6 L |
15793 | USED_REX (REX_B); |
15794 | if (rex & REX_B) | |
52b15da3 | 15795 | add = 8; |
9b60702d L |
15796 | else |
15797 | add = 0; | |
52b15da3 JH |
15798 | |
15799 | switch (code) | |
15800 | { | |
52b15da3 JH |
15801 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15802 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15803 | s = names16[code - ax_reg + add]; | |
15804 | break; | |
52b15da3 JH |
15805 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15806 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15807 | USED_REX (0); | |
15808 | if (rex) | |
15809 | s = names8rex[code - al_reg + add]; | |
15810 | else | |
15811 | s = names8[code - al_reg]; | |
15812 | break; | |
6439fc28 AM |
15813 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15814 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15815 | if (address_mode == mode_64bit |
6c067bbb | 15816 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15817 | { |
15818 | s = names64[code - rAX_reg + add]; | |
15819 | break; | |
15820 | } | |
15821 | code += eAX_reg - rAX_reg; | |
6608db57 | 15822 | /* Fall through. */ |
52b15da3 JH |
15823 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15824 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15825 | USED_REX (REX_W); |
15826 | if (rex & REX_W) | |
52b15da3 | 15827 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15828 | else |
f16cd0d5 L |
15829 | { |
15830 | if (sizeflag & DFLAG) | |
15831 | s = names32[code - eAX_reg + add]; | |
15832 | else | |
15833 | s = names16[code - eAX_reg + add]; | |
15834 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15835 | } | |
52b15da3 | 15836 | break; |
52b15da3 JH |
15837 | default: |
15838 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15839 | break; | |
15840 | } | |
15841 | oappend (s); | |
15842 | } | |
15843 | ||
15844 | static void | |
26ca5450 | 15845 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15846 | { |
15847 | const char *s; | |
252b5132 RH |
15848 | |
15849 | switch (code) | |
15850 | { | |
15851 | case indir_dx_reg: | |
d708bcba | 15852 | if (intel_syntax) |
52fd6d94 | 15853 | s = "dx"; |
d708bcba | 15854 | else |
db6eb5be | 15855 | s = "(%dx)"; |
252b5132 RH |
15856 | break; |
15857 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15858 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15859 | s = names16[code - ax_reg]; | |
15860 | break; | |
15861 | case es_reg: case ss_reg: case cs_reg: | |
15862 | case ds_reg: case fs_reg: case gs_reg: | |
15863 | s = names_seg[code - es_reg]; | |
15864 | break; | |
15865 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15866 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15867 | USED_REX (0); |
15868 | if (rex) | |
15869 | s = names8rex[code - al_reg]; | |
15870 | else | |
15871 | s = names8[code - al_reg]; | |
252b5132 RH |
15872 | break; |
15873 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15874 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15875 | USED_REX (REX_W); |
15876 | if (rex & REX_W) | |
52b15da3 | 15877 | s = names64[code - eAX_reg]; |
252b5132 | 15878 | else |
f16cd0d5 L |
15879 | { |
15880 | if (sizeflag & DFLAG) | |
15881 | s = names32[code - eAX_reg]; | |
15882 | else | |
15883 | s = names16[code - eAX_reg]; | |
15884 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15885 | } | |
252b5132 | 15886 | break; |
52fd6d94 | 15887 | case z_mode_ax_reg: |
161a04f6 | 15888 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15889 | s = *names32; |
15890 | else | |
15891 | s = *names16; | |
161a04f6 | 15892 | if (!(rex & REX_W)) |
52fd6d94 JB |
15893 | used_prefixes |= (prefixes & PREFIX_DATA); |
15894 | break; | |
252b5132 RH |
15895 | default: |
15896 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15897 | break; | |
15898 | } | |
15899 | oappend (s); | |
15900 | } | |
15901 | ||
15902 | static void | |
26ca5450 | 15903 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15904 | { |
52b15da3 JH |
15905 | bfd_signed_vma op; |
15906 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15907 | |
15908 | switch (bytemode) | |
15909 | { | |
15910 | case b_mode: | |
15911 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15912 | op = *codep++; |
15913 | mask = 0xff; | |
15914 | break; | |
15915 | case q_mode: | |
cb712a9e | 15916 | if (address_mode == mode_64bit) |
6439fc28 AM |
15917 | { |
15918 | op = get32s (); | |
15919 | break; | |
15920 | } | |
6608db57 | 15921 | /* Fall through. */ |
252b5132 | 15922 | case v_mode: |
161a04f6 L |
15923 | USED_REX (REX_W); |
15924 | if (rex & REX_W) | |
52b15da3 | 15925 | op = get32s (); |
252b5132 | 15926 | else |
52b15da3 | 15927 | { |
f16cd0d5 L |
15928 | if (sizeflag & DFLAG) |
15929 | { | |
15930 | op = get32 (); | |
15931 | mask = 0xffffffff; | |
15932 | } | |
15933 | else | |
15934 | { | |
15935 | op = get16 (); | |
15936 | mask = 0xfffff; | |
15937 | } | |
15938 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15939 | } |
252b5132 RH |
15940 | break; |
15941 | case w_mode: | |
52b15da3 | 15942 | mask = 0xfffff; |
252b5132 RH |
15943 | op = get16 (); |
15944 | break; | |
9306ca4a JB |
15945 | case const_1_mode: |
15946 | if (intel_syntax) | |
6c067bbb | 15947 | oappend ("1"); |
9306ca4a | 15948 | return; |
252b5132 RH |
15949 | default: |
15950 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15951 | return; | |
15952 | } | |
15953 | ||
52b15da3 JH |
15954 | op &= mask; |
15955 | scratchbuf[0] = '$'; | |
d708bcba | 15956 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15957 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15958 | scratchbuf[0] = '\0'; |
15959 | } | |
15960 | ||
15961 | static void | |
26ca5450 | 15962 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15963 | { |
15964 | bfd_signed_vma op; | |
15965 | bfd_signed_vma mask = -1; | |
15966 | ||
cb712a9e | 15967 | if (address_mode != mode_64bit) |
6439fc28 AM |
15968 | { |
15969 | OP_I (bytemode, sizeflag); | |
15970 | return; | |
15971 | } | |
15972 | ||
52b15da3 JH |
15973 | switch (bytemode) |
15974 | { | |
15975 | case b_mode: | |
15976 | FETCH_DATA (the_info, codep + 1); | |
15977 | op = *codep++; | |
15978 | mask = 0xff; | |
15979 | break; | |
15980 | case v_mode: | |
161a04f6 L |
15981 | USED_REX (REX_W); |
15982 | if (rex & REX_W) | |
52b15da3 | 15983 | op = get64 (); |
52b15da3 JH |
15984 | else |
15985 | { | |
f16cd0d5 L |
15986 | if (sizeflag & DFLAG) |
15987 | { | |
15988 | op = get32 (); | |
15989 | mask = 0xffffffff; | |
15990 | } | |
15991 | else | |
15992 | { | |
15993 | op = get16 (); | |
15994 | mask = 0xfffff; | |
15995 | } | |
15996 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15997 | } |
52b15da3 JH |
15998 | break; |
15999 | case w_mode: | |
16000 | mask = 0xfffff; | |
16001 | op = get16 (); | |
16002 | break; | |
16003 | default: | |
16004 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16005 | return; | |
16006 | } | |
16007 | ||
16008 | op &= mask; | |
16009 | scratchbuf[0] = '$'; | |
d708bcba | 16010 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16011 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16012 | scratchbuf[0] = '\0'; |
16013 | } | |
16014 | ||
16015 | static void | |
26ca5450 | 16016 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16017 | { |
52b15da3 | 16018 | bfd_signed_vma op; |
252b5132 RH |
16019 | |
16020 | switch (bytemode) | |
16021 | { | |
16022 | case b_mode: | |
e3949f17 | 16023 | case b_T_mode: |
252b5132 RH |
16024 | FETCH_DATA (the_info, codep + 1); |
16025 | op = *codep++; | |
16026 | if ((op & 0x80) != 0) | |
16027 | op -= 0x100; | |
e3949f17 L |
16028 | if (bytemode == b_T_mode) |
16029 | { | |
16030 | if (address_mode != mode_64bit | |
7bb15c6f | 16031 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16032 | { |
6c067bbb RM |
16033 | /* The operand-size prefix is overridden by a REX prefix. */ |
16034 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16035 | op &= 0xffffffff; |
16036 | else | |
16037 | op &= 0xffff; | |
16038 | } | |
16039 | } | |
16040 | else | |
16041 | { | |
16042 | if (!(rex & REX_W)) | |
16043 | { | |
16044 | if (sizeflag & DFLAG) | |
16045 | op &= 0xffffffff; | |
16046 | else | |
16047 | op &= 0xffff; | |
16048 | } | |
16049 | } | |
252b5132 RH |
16050 | break; |
16051 | case v_mode: | |
7bb15c6f RM |
16052 | /* The operand-size prefix is overridden by a REX prefix. */ |
16053 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16054 | op = get32s (); |
252b5132 | 16055 | else |
d9e3625e | 16056 | op = get16 (); |
252b5132 RH |
16057 | break; |
16058 | default: | |
16059 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16060 | return; | |
16061 | } | |
52b15da3 JH |
16062 | |
16063 | scratchbuf[0] = '$'; | |
16064 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16065 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16066 | } |
16067 | ||
16068 | static void | |
26ca5450 | 16069 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16070 | { |
52b15da3 | 16071 | bfd_vma disp; |
7081ff04 | 16072 | bfd_vma mask = -1; |
65ca155d | 16073 | bfd_vma segment = 0; |
252b5132 RH |
16074 | |
16075 | switch (bytemode) | |
16076 | { | |
16077 | case b_mode: | |
16078 | FETCH_DATA (the_info, codep + 1); | |
16079 | disp = *codep++; | |
16080 | if ((disp & 0x80) != 0) | |
16081 | disp -= 0x100; | |
16082 | break; | |
16083 | case v_mode: | |
5db04b09 L |
16084 | if (isa64 == amd64) |
16085 | USED_REX (REX_W); | |
16086 | if ((sizeflag & DFLAG) | |
16087 | || (address_mode == mode_64bit | |
16088 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16089 | disp = get32s (); |
252b5132 RH |
16090 | else |
16091 | { | |
16092 | disp = get16 (); | |
206717e8 L |
16093 | if ((disp & 0x8000) != 0) |
16094 | disp -= 0x10000; | |
65ca155d L |
16095 | /* In 16bit mode, address is wrapped around at 64k within |
16096 | the same segment. Otherwise, a data16 prefix on a jump | |
16097 | instruction means that the pc is masked to 16 bits after | |
16098 | the displacement is added! */ | |
16099 | mask = 0xffff; | |
16100 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16101 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16102 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16103 | } |
5db04b09 L |
16104 | if (address_mode != mode_64bit |
16105 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16106 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16107 | break; |
16108 | default: | |
16109 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16110 | return; | |
16111 | } | |
42d5f9c6 | 16112 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16113 | set_op (disp, 0); |
16114 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16115 | oappend (scratchbuf); |
16116 | } | |
16117 | ||
252b5132 | 16118 | static void |
ed7841b3 | 16119 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16120 | { |
ed7841b3 | 16121 | if (bytemode == w_mode) |
7967e09e | 16122 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16123 | else |
7967e09e | 16124 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16125 | } |
16126 | ||
16127 | static void | |
26ca5450 | 16128 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16129 | { |
16130 | int seg, offset; | |
16131 | ||
c608c12e | 16132 | if (sizeflag & DFLAG) |
252b5132 | 16133 | { |
c608c12e AM |
16134 | offset = get32 (); |
16135 | seg = get16 (); | |
252b5132 | 16136 | } |
c608c12e AM |
16137 | else |
16138 | { | |
16139 | offset = get16 (); | |
16140 | seg = get16 (); | |
16141 | } | |
7d421014 | 16142 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16143 | if (intel_syntax) |
3f31e633 | 16144 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16145 | else |
16146 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16147 | oappend (scratchbuf); |
252b5132 RH |
16148 | } |
16149 | ||
252b5132 | 16150 | static void |
3f31e633 | 16151 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16152 | { |
52b15da3 | 16153 | bfd_vma off; |
252b5132 | 16154 | |
3f31e633 JB |
16155 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16156 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16157 | append_seg (); |
16158 | ||
cb712a9e | 16159 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16160 | off = get32 (); |
16161 | else | |
16162 | off = get16 (); | |
16163 | ||
16164 | if (intel_syntax) | |
16165 | { | |
285ca992 | 16166 | if (!active_seg_prefix) |
252b5132 | 16167 | { |
d708bcba | 16168 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16169 | oappend (":"); |
16170 | } | |
16171 | } | |
52b15da3 JH |
16172 | print_operand_value (scratchbuf, 1, off); |
16173 | oappend (scratchbuf); | |
16174 | } | |
6439fc28 | 16175 | |
52b15da3 | 16176 | static void |
3f31e633 | 16177 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16178 | { |
16179 | bfd_vma off; | |
16180 | ||
539e75ad L |
16181 | if (address_mode != mode_64bit |
16182 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16183 | { |
16184 | OP_OFF (bytemode, sizeflag); | |
16185 | return; | |
16186 | } | |
16187 | ||
3f31e633 JB |
16188 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16189 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16190 | append_seg (); |
16191 | ||
6608db57 | 16192 | off = get64 (); |
52b15da3 JH |
16193 | |
16194 | if (intel_syntax) | |
16195 | { | |
285ca992 | 16196 | if (!active_seg_prefix) |
52b15da3 | 16197 | { |
d708bcba | 16198 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16199 | oappend (":"); |
16200 | } | |
16201 | } | |
16202 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16203 | oappend (scratchbuf); |
16204 | } | |
16205 | ||
16206 | static void | |
26ca5450 | 16207 | ptr_reg (int code, int sizeflag) |
252b5132 | 16208 | { |
2da11e11 | 16209 | const char *s; |
d708bcba | 16210 | |
1d9f512f | 16211 | *obufp++ = open_char; |
20f0a1fc | 16212 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16213 | if (address_mode == mode_64bit) |
c1a64871 JH |
16214 | { |
16215 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16216 | s = names32[code - eAX_reg]; |
c1a64871 | 16217 | else |
db6eb5be | 16218 | s = names64[code - eAX_reg]; |
c1a64871 | 16219 | } |
52b15da3 | 16220 | else if (sizeflag & AFLAG) |
252b5132 RH |
16221 | s = names32[code - eAX_reg]; |
16222 | else | |
16223 | s = names16[code - eAX_reg]; | |
16224 | oappend (s); | |
1d9f512f AM |
16225 | *obufp++ = close_char; |
16226 | *obufp = 0; | |
252b5132 RH |
16227 | } |
16228 | ||
16229 | static void | |
26ca5450 | 16230 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16231 | { |
9306ca4a | 16232 | if (intel_syntax) |
52fd6d94 JB |
16233 | { |
16234 | switch (codep[-1]) | |
16235 | { | |
16236 | case 0x6d: /* insw/insl */ | |
16237 | intel_operand_size (z_mode, sizeflag); | |
16238 | break; | |
16239 | case 0xa5: /* movsw/movsl/movsq */ | |
16240 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16241 | case 0xab: /* stosw/stosl */ | |
16242 | case 0xaf: /* scasw/scasl */ | |
16243 | intel_operand_size (v_mode, sizeflag); | |
16244 | break; | |
16245 | default: | |
16246 | intel_operand_size (b_mode, sizeflag); | |
16247 | } | |
16248 | } | |
9ce09ba2 | 16249 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16250 | ptr_reg (code, sizeflag); |
16251 | } | |
16252 | ||
16253 | static void | |
26ca5450 | 16254 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16255 | { |
9306ca4a | 16256 | if (intel_syntax) |
52fd6d94 JB |
16257 | { |
16258 | switch (codep[-1]) | |
16259 | { | |
16260 | case 0x6f: /* outsw/outsl */ | |
16261 | intel_operand_size (z_mode, sizeflag); | |
16262 | break; | |
16263 | case 0xa5: /* movsw/movsl/movsq */ | |
16264 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16265 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16266 | intel_operand_size (v_mode, sizeflag); | |
16267 | break; | |
16268 | default: | |
16269 | intel_operand_size (b_mode, sizeflag); | |
16270 | } | |
16271 | } | |
285ca992 L |
16272 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16273 | default segment register DS is printed. */ | |
16274 | if (!active_seg_prefix) | |
16275 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16276 | append_seg (); |
252b5132 RH |
16277 | ptr_reg (code, sizeflag); |
16278 | } | |
16279 | ||
252b5132 | 16280 | static void |
26ca5450 | 16281 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16282 | { |
9b60702d | 16283 | int add; |
161a04f6 | 16284 | if (rex & REX_R) |
c4a530c5 | 16285 | { |
161a04f6 | 16286 | USED_REX (REX_R); |
c4a530c5 JB |
16287 | add = 8; |
16288 | } | |
cb712a9e | 16289 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16290 | { |
f16cd0d5 | 16291 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16292 | used_prefixes |= PREFIX_LOCK; |
16293 | add = 8; | |
16294 | } | |
9b60702d L |
16295 | else |
16296 | add = 0; | |
7967e09e | 16297 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16298 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16299 | } |
16300 | ||
252b5132 | 16301 | static void |
26ca5450 | 16302 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16303 | { |
9b60702d | 16304 | int add; |
161a04f6 L |
16305 | USED_REX (REX_R); |
16306 | if (rex & REX_R) | |
52b15da3 | 16307 | add = 8; |
9b60702d L |
16308 | else |
16309 | add = 0; | |
d708bcba | 16310 | if (intel_syntax) |
7967e09e | 16311 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16312 | else |
7967e09e | 16313 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16314 | oappend (scratchbuf); |
16315 | } | |
16316 | ||
252b5132 | 16317 | static void |
26ca5450 | 16318 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16319 | { |
7967e09e | 16320 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16321 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16322 | } |
16323 | ||
16324 | static void | |
6f74c397 | 16325 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16326 | { |
68f34464 L |
16327 | /* Skip mod/rm byte. */ |
16328 | MODRM_CHECK; | |
16329 | codep++; | |
16330 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16331 | } |
16332 | ||
16333 | static void | |
26ca5450 | 16334 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16335 | { |
b9733481 L |
16336 | int reg = modrm.reg; |
16337 | const char **names; | |
16338 | ||
041bd2e0 JH |
16339 | used_prefixes |= (prefixes & PREFIX_DATA); |
16340 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16341 | { |
b9733481 | 16342 | names = names_xmm; |
161a04f6 L |
16343 | USED_REX (REX_R); |
16344 | if (rex & REX_R) | |
b9733481 | 16345 | reg += 8; |
20f0a1fc | 16346 | } |
041bd2e0 | 16347 | else |
b9733481 L |
16348 | names = names_mm; |
16349 | oappend (names[reg]); | |
252b5132 RH |
16350 | } |
16351 | ||
c608c12e | 16352 | static void |
c0f3af97 | 16353 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16354 | { |
b9733481 L |
16355 | int reg = modrm.reg; |
16356 | const char **names; | |
16357 | ||
161a04f6 L |
16358 | USED_REX (REX_R); |
16359 | if (rex & REX_R) | |
b9733481 | 16360 | reg += 8; |
43234a1e L |
16361 | if (vex.evex) |
16362 | { | |
16363 | if (!vex.r) | |
16364 | reg += 16; | |
16365 | } | |
16366 | ||
539f890d L |
16367 | if (need_vex |
16368 | && bytemode != xmm_mode | |
43234a1e L |
16369 | && bytemode != xmmq_mode |
16370 | && bytemode != evex_half_bcst_xmmq_mode | |
16371 | && bytemode != ymm_mode | |
539f890d | 16372 | && bytemode != scalar_mode) |
c0f3af97 L |
16373 | { |
16374 | switch (vex.length) | |
16375 | { | |
16376 | case 128: | |
b9733481 | 16377 | names = names_xmm; |
c0f3af97 L |
16378 | break; |
16379 | case 256: | |
5fc35d96 IT |
16380 | if (vex.w |
16381 | || (bytemode != vex_vsib_q_w_dq_mode | |
16382 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16383 | names = names_ymm; |
16384 | else | |
16385 | names = names_xmm; | |
c0f3af97 | 16386 | break; |
43234a1e L |
16387 | case 512: |
16388 | names = names_zmm; | |
16389 | break; | |
c0f3af97 L |
16390 | default: |
16391 | abort (); | |
16392 | } | |
16393 | } | |
43234a1e L |
16394 | else if (bytemode == xmmq_mode |
16395 | || bytemode == evex_half_bcst_xmmq_mode) | |
16396 | { | |
16397 | switch (vex.length) | |
16398 | { | |
16399 | case 128: | |
16400 | case 256: | |
16401 | names = names_xmm; | |
16402 | break; | |
16403 | case 512: | |
16404 | names = names_ymm; | |
16405 | break; | |
16406 | default: | |
16407 | abort (); | |
16408 | } | |
16409 | } | |
16410 | else if (bytemode == ymm_mode) | |
16411 | names = names_ymm; | |
c0f3af97 | 16412 | else |
b9733481 L |
16413 | names = names_xmm; |
16414 | oappend (names[reg]); | |
c608c12e AM |
16415 | } |
16416 | ||
252b5132 | 16417 | static void |
26ca5450 | 16418 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16419 | { |
b9733481 L |
16420 | int reg; |
16421 | const char **names; | |
16422 | ||
7967e09e | 16423 | if (modrm.mod != 3) |
252b5132 | 16424 | { |
b6169b20 L |
16425 | if (intel_syntax |
16426 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16427 | { |
16428 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16429 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16430 | } |
252b5132 RH |
16431 | OP_E (bytemode, sizeflag); |
16432 | return; | |
16433 | } | |
16434 | ||
b6169b20 L |
16435 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16436 | swap_operand (); | |
16437 | ||
6608db57 | 16438 | /* Skip mod/rm byte. */ |
4bba6815 | 16439 | MODRM_CHECK; |
252b5132 | 16440 | codep++; |
041bd2e0 | 16441 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16442 | reg = modrm.rm; |
041bd2e0 | 16443 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16444 | { |
b9733481 | 16445 | names = names_xmm; |
161a04f6 L |
16446 | USED_REX (REX_B); |
16447 | if (rex & REX_B) | |
b9733481 | 16448 | reg += 8; |
20f0a1fc | 16449 | } |
041bd2e0 | 16450 | else |
b9733481 L |
16451 | names = names_mm; |
16452 | oappend (names[reg]); | |
252b5132 RH |
16453 | } |
16454 | ||
246c51aa L |
16455 | /* cvt* are the only instructions in sse2 which have |
16456 | both SSE and MMX operands and also have 0x66 prefix | |
16457 | in their opcode. 0x66 was originally used to differentiate | |
16458 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16459 | cvt* separately using OP_EMC and OP_MXC */ |
16460 | static void | |
16461 | OP_EMC (int bytemode, int sizeflag) | |
16462 | { | |
7967e09e | 16463 | if (modrm.mod != 3) |
4d9567e0 MM |
16464 | { |
16465 | if (intel_syntax && bytemode == v_mode) | |
16466 | { | |
16467 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16468 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16469 | } |
4d9567e0 MM |
16470 | OP_E (bytemode, sizeflag); |
16471 | return; | |
16472 | } | |
246c51aa | 16473 | |
4d9567e0 MM |
16474 | /* Skip mod/rm byte. */ |
16475 | MODRM_CHECK; | |
16476 | codep++; | |
16477 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16478 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16479 | } |
16480 | ||
16481 | static void | |
16482 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16483 | { | |
16484 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16485 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16486 | } |
16487 | ||
c608c12e | 16488 | static void |
26ca5450 | 16489 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16490 | { |
b9733481 L |
16491 | int reg; |
16492 | const char **names; | |
d6f574e0 L |
16493 | |
16494 | /* Skip mod/rm byte. */ | |
16495 | MODRM_CHECK; | |
16496 | codep++; | |
16497 | ||
7967e09e | 16498 | if (modrm.mod != 3) |
c608c12e | 16499 | { |
c1e679ec | 16500 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16501 | return; |
16502 | } | |
d6f574e0 | 16503 | |
b9733481 | 16504 | reg = modrm.rm; |
161a04f6 L |
16505 | USED_REX (REX_B); |
16506 | if (rex & REX_B) | |
b9733481 | 16507 | reg += 8; |
43234a1e L |
16508 | if (vex.evex) |
16509 | { | |
16510 | USED_REX (REX_X); | |
16511 | if ((rex & REX_X)) | |
16512 | reg += 16; | |
16513 | } | |
c608c12e | 16514 | |
b6169b20 | 16515 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16516 | && (bytemode == x_swap_mode |
16517 | || bytemode == d_swap_mode | |
7bb15c6f | 16518 | || bytemode == d_scalar_swap_mode |
539f890d L |
16519 | || bytemode == q_swap_mode |
16520 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16521 | swap_operand (); |
16522 | ||
c0f3af97 L |
16523 | if (need_vex |
16524 | && bytemode != xmm_mode | |
6c30d220 L |
16525 | && bytemode != xmmdw_mode |
16526 | && bytemode != xmmqd_mode | |
16527 | && bytemode != xmm_mb_mode | |
16528 | && bytemode != xmm_mw_mode | |
16529 | && bytemode != xmm_md_mode | |
16530 | && bytemode != xmm_mq_mode | |
43234a1e | 16531 | && bytemode != xmm_mdq_mode |
539f890d | 16532 | && bytemode != xmmq_mode |
43234a1e L |
16533 | && bytemode != evex_half_bcst_xmmq_mode |
16534 | && bytemode != ymm_mode | |
539f890d | 16535 | && bytemode != d_scalar_mode |
7bb15c6f | 16536 | && bytemode != d_scalar_swap_mode |
539f890d | 16537 | && bytemode != q_scalar_mode |
1c480963 L |
16538 | && bytemode != q_scalar_swap_mode |
16539 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16540 | { |
16541 | switch (vex.length) | |
16542 | { | |
16543 | case 128: | |
b9733481 | 16544 | names = names_xmm; |
c0f3af97 L |
16545 | break; |
16546 | case 256: | |
b9733481 | 16547 | names = names_ymm; |
c0f3af97 | 16548 | break; |
43234a1e L |
16549 | case 512: |
16550 | names = names_zmm; | |
16551 | break; | |
c0f3af97 L |
16552 | default: |
16553 | abort (); | |
16554 | } | |
16555 | } | |
43234a1e L |
16556 | else if (bytemode == xmmq_mode |
16557 | || bytemode == evex_half_bcst_xmmq_mode) | |
16558 | { | |
16559 | switch (vex.length) | |
16560 | { | |
16561 | case 128: | |
16562 | case 256: | |
16563 | names = names_xmm; | |
16564 | break; | |
16565 | case 512: | |
16566 | names = names_ymm; | |
16567 | break; | |
16568 | default: | |
16569 | abort (); | |
16570 | } | |
16571 | } | |
16572 | else if (bytemode == ymm_mode) | |
16573 | names = names_ymm; | |
c0f3af97 | 16574 | else |
b9733481 L |
16575 | names = names_xmm; |
16576 | oappend (names[reg]); | |
c608c12e AM |
16577 | } |
16578 | ||
252b5132 | 16579 | static void |
26ca5450 | 16580 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16581 | { |
7967e09e | 16582 | if (modrm.mod == 3) |
2da11e11 AM |
16583 | OP_EM (bytemode, sizeflag); |
16584 | else | |
6608db57 | 16585 | BadOp (); |
252b5132 RH |
16586 | } |
16587 | ||
992aaec9 | 16588 | static void |
26ca5450 | 16589 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16590 | { |
7967e09e | 16591 | if (modrm.mod == 3) |
992aaec9 AM |
16592 | OP_EX (bytemode, sizeflag); |
16593 | else | |
6608db57 | 16594 | BadOp (); |
992aaec9 AM |
16595 | } |
16596 | ||
cc0ec051 AM |
16597 | static void |
16598 | OP_M (int bytemode, int sizeflag) | |
16599 | { | |
7967e09e | 16600 | if (modrm.mod == 3) |
75413a22 L |
16601 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16602 | BadOp (); | |
cc0ec051 AM |
16603 | else |
16604 | OP_E (bytemode, sizeflag); | |
16605 | } | |
16606 | ||
16607 | static void | |
16608 | OP_0f07 (int bytemode, int sizeflag) | |
16609 | { | |
7967e09e | 16610 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16611 | BadOp (); |
16612 | else | |
16613 | OP_E (bytemode, sizeflag); | |
16614 | } | |
16615 | ||
46e883c5 | 16616 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16617 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16618 | |
cc0ec051 | 16619 | static void |
46e883c5 | 16620 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16621 | { |
8b38ad71 L |
16622 | if ((prefixes & PREFIX_DATA) != 0 |
16623 | || (rex != 0 | |
16624 | && rex != 0x48 | |
16625 | && address_mode == mode_64bit)) | |
46e883c5 L |
16626 | OP_REG (bytemode, sizeflag); |
16627 | else | |
16628 | strcpy (obuf, "nop"); | |
16629 | } | |
16630 | ||
16631 | static void | |
16632 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16633 | { | |
8b38ad71 L |
16634 | if ((prefixes & PREFIX_DATA) != 0 |
16635 | || (rex != 0 | |
16636 | && rex != 0x48 | |
16637 | && address_mode == mode_64bit)) | |
46e883c5 | 16638 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16639 | } |
16640 | ||
84037f8c | 16641 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16642 | /* 00 */ NULL, NULL, NULL, NULL, |
16643 | /* 04 */ NULL, NULL, NULL, NULL, | |
16644 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16645 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16646 | /* 10 */ NULL, NULL, NULL, NULL, |
16647 | /* 14 */ NULL, NULL, NULL, NULL, | |
16648 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16649 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16650 | /* 20 */ NULL, NULL, NULL, NULL, |
16651 | /* 24 */ NULL, NULL, NULL, NULL, | |
16652 | /* 28 */ NULL, NULL, NULL, NULL, | |
16653 | /* 2C */ NULL, NULL, NULL, NULL, | |
16654 | /* 30 */ NULL, NULL, NULL, NULL, | |
16655 | /* 34 */ NULL, NULL, NULL, NULL, | |
16656 | /* 38 */ NULL, NULL, NULL, NULL, | |
16657 | /* 3C */ NULL, NULL, NULL, NULL, | |
16658 | /* 40 */ NULL, NULL, NULL, NULL, | |
16659 | /* 44 */ NULL, NULL, NULL, NULL, | |
16660 | /* 48 */ NULL, NULL, NULL, NULL, | |
16661 | /* 4C */ NULL, NULL, NULL, NULL, | |
16662 | /* 50 */ NULL, NULL, NULL, NULL, | |
16663 | /* 54 */ NULL, NULL, NULL, NULL, | |
16664 | /* 58 */ NULL, NULL, NULL, NULL, | |
16665 | /* 5C */ NULL, NULL, NULL, NULL, | |
16666 | /* 60 */ NULL, NULL, NULL, NULL, | |
16667 | /* 64 */ NULL, NULL, NULL, NULL, | |
16668 | /* 68 */ NULL, NULL, NULL, NULL, | |
16669 | /* 6C */ NULL, NULL, NULL, NULL, | |
16670 | /* 70 */ NULL, NULL, NULL, NULL, | |
16671 | /* 74 */ NULL, NULL, NULL, NULL, | |
16672 | /* 78 */ NULL, NULL, NULL, NULL, | |
16673 | /* 7C */ NULL, NULL, NULL, NULL, | |
16674 | /* 80 */ NULL, NULL, NULL, NULL, | |
16675 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16676 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16677 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16678 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16679 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16680 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16681 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16682 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16683 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16684 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16685 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16686 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16687 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16688 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16689 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16690 | /* C0 */ NULL, NULL, NULL, NULL, | |
16691 | /* C4 */ NULL, NULL, NULL, NULL, | |
16692 | /* C8 */ NULL, NULL, NULL, NULL, | |
16693 | /* CC */ NULL, NULL, NULL, NULL, | |
16694 | /* D0 */ NULL, NULL, NULL, NULL, | |
16695 | /* D4 */ NULL, NULL, NULL, NULL, | |
16696 | /* D8 */ NULL, NULL, NULL, NULL, | |
16697 | /* DC */ NULL, NULL, NULL, NULL, | |
16698 | /* E0 */ NULL, NULL, NULL, NULL, | |
16699 | /* E4 */ NULL, NULL, NULL, NULL, | |
16700 | /* E8 */ NULL, NULL, NULL, NULL, | |
16701 | /* EC */ NULL, NULL, NULL, NULL, | |
16702 | /* F0 */ NULL, NULL, NULL, NULL, | |
16703 | /* F4 */ NULL, NULL, NULL, NULL, | |
16704 | /* F8 */ NULL, NULL, NULL, NULL, | |
16705 | /* FC */ NULL, NULL, NULL, NULL, | |
16706 | }; | |
16707 | ||
16708 | static void | |
26ca5450 | 16709 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16710 | { |
16711 | const char *mnemonic; | |
16712 | ||
16713 | FETCH_DATA (the_info, codep + 1); | |
16714 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16715 | place where an 8-bit immediate would normally go. ie. the last | |
16716 | byte of the instruction. */ | |
ea397f5b | 16717 | obufp = mnemonicendp; |
c608c12e | 16718 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16719 | if (mnemonic) |
2da11e11 | 16720 | oappend (mnemonic); |
252b5132 RH |
16721 | else |
16722 | { | |
16723 | /* Since a variable sized modrm/sib chunk is between the start | |
16724 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16725 | all the modrm processing first, and don't know until now that | |
16726 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16727 | op_out[0][0] = '\0'; |
16728 | op_out[1][0] = '\0'; | |
6608db57 | 16729 | BadOp (); |
252b5132 | 16730 | } |
ea397f5b | 16731 | mnemonicendp = obufp; |
252b5132 | 16732 | } |
c608c12e | 16733 | |
ea397f5b L |
16734 | static struct op simd_cmp_op[] = |
16735 | { | |
16736 | { STRING_COMMA_LEN ("eq") }, | |
16737 | { STRING_COMMA_LEN ("lt") }, | |
16738 | { STRING_COMMA_LEN ("le") }, | |
16739 | { STRING_COMMA_LEN ("unord") }, | |
16740 | { STRING_COMMA_LEN ("neq") }, | |
16741 | { STRING_COMMA_LEN ("nlt") }, | |
16742 | { STRING_COMMA_LEN ("nle") }, | |
16743 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16744 | }; |
16745 | ||
16746 | static void | |
ad19981d | 16747 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16748 | { |
16749 | unsigned int cmp_type; | |
16750 | ||
16751 | FETCH_DATA (the_info, codep + 1); | |
16752 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16753 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16754 | { |
ad19981d | 16755 | char suffix [3]; |
ea397f5b | 16756 | char *p = mnemonicendp - 2; |
ad19981d L |
16757 | suffix[0] = p[0]; |
16758 | suffix[1] = p[1]; | |
16759 | suffix[2] = '\0'; | |
ea397f5b L |
16760 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16761 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16762 | } |
16763 | else | |
16764 | { | |
ad19981d L |
16765 | /* We have a reserved extension byte. Output it directly. */ |
16766 | scratchbuf[0] = '$'; | |
16767 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16768 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16769 | scratchbuf[0] = '\0'; |
c608c12e AM |
16770 | } |
16771 | } | |
16772 | ||
9916071f AP |
16773 | static void |
16774 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16775 | int sizeflag ATTRIBUTE_UNUSED) | |
16776 | { | |
16777 | /* mwaitx %eax,%ecx,%ebx */ | |
16778 | if (!intel_syntax) | |
16779 | { | |
16780 | const char **names = (address_mode == mode_64bit | |
16781 | ? names64 : names32); | |
16782 | strcpy (op_out[0], names[0]); | |
16783 | strcpy (op_out[1], names[1]); | |
16784 | strcpy (op_out[2], names[3]); | |
16785 | two_source_ops = 1; | |
16786 | } | |
16787 | /* Skip mod/rm byte. */ | |
16788 | MODRM_CHECK; | |
16789 | codep++; | |
16790 | } | |
16791 | ||
ca164297 | 16792 | static void |
b844680a L |
16793 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16794 | int sizeflag ATTRIBUTE_UNUSED) | |
16795 | { | |
16796 | /* mwait %eax,%ecx */ | |
16797 | if (!intel_syntax) | |
16798 | { | |
16799 | const char **names = (address_mode == mode_64bit | |
16800 | ? names64 : names32); | |
16801 | strcpy (op_out[0], names[0]); | |
16802 | strcpy (op_out[1], names[1]); | |
16803 | two_source_ops = 1; | |
16804 | } | |
16805 | /* Skip mod/rm byte. */ | |
16806 | MODRM_CHECK; | |
16807 | codep++; | |
16808 | } | |
16809 | ||
16810 | static void | |
16811 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16812 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16813 | { |
b844680a L |
16814 | /* monitor %eax,%ecx,%edx" */ |
16815 | if (!intel_syntax) | |
ca164297 | 16816 | { |
b844680a | 16817 | const char **op1_names; |
cb712a9e L |
16818 | const char **names = (address_mode == mode_64bit |
16819 | ? names64 : names32); | |
1d9f512f | 16820 | |
b844680a L |
16821 | if (!(prefixes & PREFIX_ADDR)) |
16822 | op1_names = (address_mode == mode_16bit | |
16823 | ? names16 : names); | |
ca164297 L |
16824 | else |
16825 | { | |
b844680a | 16826 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16827 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16828 | op1_names = (address_mode != mode_32bit |
16829 | ? names32 : names16); | |
16830 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16831 | } |
b844680a L |
16832 | strcpy (op_out[0], op1_names[0]); |
16833 | strcpy (op_out[1], names[1]); | |
16834 | strcpy (op_out[2], names[2]); | |
16835 | two_source_ops = 1; | |
ca164297 | 16836 | } |
b844680a L |
16837 | /* Skip mod/rm byte. */ |
16838 | MODRM_CHECK; | |
16839 | codep++; | |
30123838 JB |
16840 | } |
16841 | ||
6608db57 KH |
16842 | static void |
16843 | BadOp (void) | |
2da11e11 | 16844 | { |
6608db57 KH |
16845 | /* Throw away prefixes and 1st. opcode byte. */ |
16846 | codep = insn_codep + 1; | |
2da11e11 AM |
16847 | oappend ("(bad)"); |
16848 | } | |
4cc91dba | 16849 | |
35c52694 L |
16850 | static void |
16851 | REP_Fixup (int bytemode, int sizeflag) | |
16852 | { | |
16853 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16854 | lods and stos. */ | |
35c52694 | 16855 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16856 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16857 | |
16858 | switch (bytemode) | |
16859 | { | |
16860 | case al_reg: | |
16861 | case eAX_reg: | |
16862 | case indir_dx_reg: | |
16863 | OP_IMREG (bytemode, sizeflag); | |
16864 | break; | |
16865 | case eDI_reg: | |
16866 | OP_ESreg (bytemode, sizeflag); | |
16867 | break; | |
16868 | case eSI_reg: | |
16869 | OP_DSreg (bytemode, sizeflag); | |
16870 | break; | |
16871 | default: | |
16872 | abort (); | |
16873 | break; | |
16874 | } | |
16875 | } | |
f5804c90 | 16876 | |
7e8b059b L |
16877 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16878 | "bnd". */ | |
16879 | ||
16880 | static void | |
16881 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16882 | { | |
16883 | if (prefixes & PREFIX_REPNZ) | |
16884 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16885 | } | |
16886 | ||
04ef582a L |
16887 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16888 | "notrack". */ | |
16889 | ||
16890 | static void | |
16891 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16892 | int sizeflag ATTRIBUTE_UNUSED) | |
16893 | { | |
9fef80d6 | 16894 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16895 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16896 | { | |
4e9ac44a | 16897 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16898 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16899 | active_seg_prefix = 0; |
16900 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16901 | } | |
16902 | } | |
16903 | ||
42164a71 L |
16904 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16905 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16906 | */ | |
16907 | ||
16908 | static void | |
16909 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16910 | { | |
16911 | if (modrm.mod != 3 | |
16912 | && (prefixes & PREFIX_LOCK) != 0) | |
16913 | { | |
16914 | if (prefixes & PREFIX_REPZ) | |
16915 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16916 | if (prefixes & PREFIX_REPNZ) | |
16917 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16918 | } | |
16919 | ||
16920 | OP_E (bytemode, sizeflag); | |
16921 | } | |
16922 | ||
16923 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16924 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16925 | */ | |
16926 | ||
16927 | static void | |
16928 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16929 | { | |
16930 | if (modrm.mod != 3) | |
16931 | { | |
16932 | if (prefixes & PREFIX_REPZ) | |
16933 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16934 | if (prefixes & PREFIX_REPNZ) | |
16935 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16936 | } | |
16937 | ||
16938 | OP_E (bytemode, sizeflag); | |
16939 | } | |
16940 | ||
16941 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16942 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16943 | ||
16944 | static void | |
16945 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16946 | { | |
16947 | if (modrm.mod != 3 | |
16948 | && last_repz_prefix > last_repnz_prefix | |
16949 | && (prefixes & PREFIX_REPZ) != 0) | |
16950 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16951 | ||
16952 | OP_E (bytemode, sizeflag); | |
16953 | } | |
16954 | ||
f5804c90 L |
16955 | static void |
16956 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16957 | { | |
161a04f6 L |
16958 | USED_REX (REX_W); |
16959 | if (rex & REX_W) | |
f5804c90 L |
16960 | { |
16961 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16962 | char *p = mnemonicendp - 2; |
16963 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16964 | bytemode = o_mode; |
f5804c90 | 16965 | } |
42164a71 L |
16966 | else if ((prefixes & PREFIX_LOCK) != 0) |
16967 | { | |
16968 | if (prefixes & PREFIX_REPZ) | |
16969 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16970 | if (prefixes & PREFIX_REPNZ) | |
16971 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16972 | } | |
16973 | ||
f5804c90 L |
16974 | OP_M (bytemode, sizeflag); |
16975 | } | |
42903f7f L |
16976 | |
16977 | static void | |
16978 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16979 | { | |
b9733481 L |
16980 | const char **names; |
16981 | ||
c0f3af97 L |
16982 | if (need_vex) |
16983 | { | |
16984 | switch (vex.length) | |
16985 | { | |
16986 | case 128: | |
b9733481 | 16987 | names = names_xmm; |
c0f3af97 L |
16988 | break; |
16989 | case 256: | |
b9733481 | 16990 | names = names_ymm; |
c0f3af97 L |
16991 | break; |
16992 | default: | |
16993 | abort (); | |
16994 | } | |
16995 | } | |
16996 | else | |
b9733481 L |
16997 | names = names_xmm; |
16998 | oappend (names[reg]); | |
42903f7f | 16999 | } |
381d071f L |
17000 | |
17001 | static void | |
17002 | CRC32_Fixup (int bytemode, int sizeflag) | |
17003 | { | |
17004 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 17005 | char *p = mnemonicendp; |
381d071f L |
17006 | |
17007 | switch (bytemode) | |
17008 | { | |
17009 | case b_mode: | |
20592a94 | 17010 | if (intel_syntax) |
ea397f5b | 17011 | goto skip; |
20592a94 | 17012 | |
381d071f L |
17013 | *p++ = 'b'; |
17014 | break; | |
17015 | case v_mode: | |
20592a94 | 17016 | if (intel_syntax) |
ea397f5b | 17017 | goto skip; |
20592a94 | 17018 | |
381d071f L |
17019 | USED_REX (REX_W); |
17020 | if (rex & REX_W) | |
17021 | *p++ = 'q'; | |
7bb15c6f | 17022 | else |
f16cd0d5 L |
17023 | { |
17024 | if (sizeflag & DFLAG) | |
17025 | *p++ = 'l'; | |
17026 | else | |
17027 | *p++ = 'w'; | |
17028 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17029 | } | |
381d071f L |
17030 | break; |
17031 | default: | |
17032 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17033 | break; | |
17034 | } | |
ea397f5b | 17035 | mnemonicendp = p; |
381d071f L |
17036 | *p = '\0'; |
17037 | ||
ea397f5b | 17038 | skip: |
381d071f L |
17039 | if (modrm.mod == 3) |
17040 | { | |
17041 | int add; | |
17042 | ||
17043 | /* Skip mod/rm byte. */ | |
17044 | MODRM_CHECK; | |
17045 | codep++; | |
17046 | ||
17047 | USED_REX (REX_B); | |
17048 | add = (rex & REX_B) ? 8 : 0; | |
17049 | if (bytemode == b_mode) | |
17050 | { | |
17051 | USED_REX (0); | |
17052 | if (rex) | |
17053 | oappend (names8rex[modrm.rm + add]); | |
17054 | else | |
17055 | oappend (names8[modrm.rm + add]); | |
17056 | } | |
17057 | else | |
17058 | { | |
17059 | USED_REX (REX_W); | |
17060 | if (rex & REX_W) | |
17061 | oappend (names64[modrm.rm + add]); | |
17062 | else if ((prefixes & PREFIX_DATA)) | |
17063 | oappend (names16[modrm.rm + add]); | |
17064 | else | |
17065 | oappend (names32[modrm.rm + add]); | |
17066 | } | |
17067 | } | |
17068 | else | |
9344ff29 | 17069 | OP_E (bytemode, sizeflag); |
381d071f | 17070 | } |
85f10a01 | 17071 | |
eacc9c89 L |
17072 | static void |
17073 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17074 | { | |
17075 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17076 | USED_REX (REX_W); | |
17077 | if (rex & REX_W) | |
17078 | { | |
17079 | char *p = mnemonicendp; | |
17080 | *p++ = '6'; | |
17081 | *p++ = '4'; | |
17082 | *p = '\0'; | |
17083 | mnemonicendp = p; | |
17084 | } | |
17085 | OP_M (bytemode, sizeflag); | |
17086 | } | |
17087 | ||
15c7c1d8 JB |
17088 | static void |
17089 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
17090 | { | |
17091 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
17092 | if (!intel_syntax) | |
17093 | { | |
17094 | char *p = mnemonicendp; | |
17095 | ||
17096 | USED_REX (REX_W); | |
17097 | if (rex & REX_W) | |
17098 | *p++ = 'q'; | |
17099 | else if (sizeflag & SUFFIX_ALWAYS) | |
17100 | *p++ = 'l'; | |
17101 | ||
17102 | *p = '\0'; | |
17103 | mnemonicendp = p; | |
17104 | } | |
17105 | ||
17106 | OP_EX (bytemode, sizeflag); | |
17107 | } | |
17108 | ||
c0f3af97 L |
17109 | /* Display the destination register operand for instructions with |
17110 | VEX. */ | |
17111 | ||
17112 | static void | |
17113 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17114 | { | |
539f890d | 17115 | int reg; |
b9733481 L |
17116 | const char **names; |
17117 | ||
c0f3af97 L |
17118 | if (!need_vex) |
17119 | abort (); | |
17120 | ||
17121 | if (!need_vex_reg) | |
17122 | return; | |
17123 | ||
539f890d | 17124 | reg = vex.register_specifier; |
5f847646 JB |
17125 | if (address_mode != mode_64bit) |
17126 | reg &= 7; | |
17127 | else if (vex.evex && !vex.v) | |
17128 | reg += 16; | |
43234a1e | 17129 | |
539f890d L |
17130 | if (bytemode == vex_scalar_mode) |
17131 | { | |
17132 | oappend (names_xmm[reg]); | |
17133 | return; | |
17134 | } | |
17135 | ||
c0f3af97 L |
17136 | switch (vex.length) |
17137 | { | |
17138 | case 128: | |
17139 | switch (bytemode) | |
17140 | { | |
17141 | case vex_mode: | |
17142 | case vex128_mode: | |
6c30d220 | 17143 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17144 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17145 | names = names_xmm; |
17146 | break; | |
17147 | case dq_mode: | |
390a6789 | 17148 | if (rex & REX_W) |
cb21baef L |
17149 | names = names64; |
17150 | else | |
17151 | names = names32; | |
c0f3af97 | 17152 | break; |
1ba585e8 | 17153 | case mask_bd_mode: |
43234a1e | 17154 | case mask_mode: |
9889cbb1 L |
17155 | if (reg > 0x7) |
17156 | { | |
17157 | oappend ("(bad)"); | |
17158 | return; | |
17159 | } | |
43234a1e L |
17160 | names = names_mask; |
17161 | break; | |
c0f3af97 L |
17162 | default: |
17163 | abort (); | |
17164 | return; | |
17165 | } | |
c0f3af97 L |
17166 | break; |
17167 | case 256: | |
17168 | switch (bytemode) | |
17169 | { | |
17170 | case vex_mode: | |
17171 | case vex256_mode: | |
6c30d220 L |
17172 | names = names_ymm; |
17173 | break; | |
17174 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17175 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17176 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17177 | break; |
1ba585e8 | 17178 | case mask_bd_mode: |
43234a1e | 17179 | case mask_mode: |
9889cbb1 L |
17180 | if (reg > 0x7) |
17181 | { | |
17182 | oappend ("(bad)"); | |
17183 | return; | |
17184 | } | |
43234a1e L |
17185 | names = names_mask; |
17186 | break; | |
c0f3af97 | 17187 | default: |
a37a2806 NC |
17188 | /* See PR binutils/20893 for a reproducer. */ |
17189 | oappend ("(bad)"); | |
c0f3af97 L |
17190 | return; |
17191 | } | |
c0f3af97 | 17192 | break; |
43234a1e L |
17193 | case 512: |
17194 | names = names_zmm; | |
17195 | break; | |
c0f3af97 L |
17196 | default: |
17197 | abort (); | |
17198 | break; | |
17199 | } | |
539f890d | 17200 | oappend (names[reg]); |
c0f3af97 L |
17201 | } |
17202 | ||
922d8de8 DR |
17203 | /* Get the VEX immediate byte without moving codep. */ |
17204 | ||
17205 | static unsigned char | |
ccc5981b | 17206 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17207 | { |
17208 | int bytes_before_imm = 0; | |
17209 | ||
922d8de8 DR |
17210 | if (modrm.mod != 3) |
17211 | { | |
17212 | /* There are SIB/displacement bytes. */ | |
17213 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17214 | { |
922d8de8 | 17215 | /* 32/64 bit address mode */ |
6c067bbb | 17216 | int base = modrm.rm; |
922d8de8 DR |
17217 | |
17218 | /* Check SIB byte. */ | |
6c067bbb RM |
17219 | if (base == 4) |
17220 | { | |
17221 | FETCH_DATA (the_info, codep + 1); | |
17222 | base = *codep & 7; | |
17223 | /* When decoding the third source, don't increase | |
17224 | bytes_before_imm as this has already been incremented | |
17225 | by one in OP_E_memory while decoding the second | |
17226 | source operand. */ | |
17227 | if (opnum == 0) | |
17228 | bytes_before_imm++; | |
17229 | } | |
17230 | ||
17231 | /* Don't increase bytes_before_imm when decoding the third source, | |
17232 | it has already been incremented by OP_E_memory while decoding | |
17233 | the second source operand. */ | |
17234 | if (opnum == 0) | |
17235 | { | |
17236 | switch (modrm.mod) | |
17237 | { | |
17238 | case 0: | |
17239 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17240 | SIB == 5, there is a 4 byte displacement. */ | |
17241 | if (base != 5) | |
17242 | /* No displacement. */ | |
17243 | break; | |
1a0670f3 | 17244 | /* Fall through. */ |
6c067bbb RM |
17245 | case 2: |
17246 | /* 4 byte displacement. */ | |
17247 | bytes_before_imm += 4; | |
17248 | break; | |
17249 | case 1: | |
17250 | /* 1 byte displacement. */ | |
17251 | bytes_before_imm++; | |
17252 | break; | |
17253 | } | |
17254 | } | |
17255 | } | |
922d8de8 | 17256 | else |
02e647f9 SP |
17257 | { |
17258 | /* 16 bit address mode */ | |
6c067bbb RM |
17259 | /* Don't increase bytes_before_imm when decoding the third source, |
17260 | it has already been incremented by OP_E_memory while decoding | |
17261 | the second source operand. */ | |
17262 | if (opnum == 0) | |
17263 | { | |
02e647f9 SP |
17264 | switch (modrm.mod) |
17265 | { | |
17266 | case 0: | |
17267 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17268 | if (modrm.rm != 6) | |
17269 | /* No displacement. */ | |
17270 | break; | |
1a0670f3 | 17271 | /* Fall through. */ |
02e647f9 SP |
17272 | case 2: |
17273 | /* 2 byte displacement. */ | |
17274 | bytes_before_imm += 2; | |
17275 | break; | |
17276 | case 1: | |
17277 | /* 1 byte displacement: when decoding the third source, | |
17278 | don't increase bytes_before_imm as this has already | |
17279 | been incremented by one in OP_E_memory while decoding | |
17280 | the second source operand. */ | |
17281 | if (opnum == 0) | |
17282 | bytes_before_imm++; | |
ccc5981b | 17283 | |
02e647f9 SP |
17284 | break; |
17285 | } | |
922d8de8 DR |
17286 | } |
17287 | } | |
17288 | } | |
17289 | ||
17290 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17291 | return codep [bytes_before_imm]; | |
17292 | } | |
17293 | ||
17294 | static void | |
17295 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17296 | { | |
b9733481 L |
17297 | const char **names; |
17298 | ||
922d8de8 DR |
17299 | if (reg == -1 && modrm.mod != 3) |
17300 | { | |
17301 | OP_E_memory (bytemode, sizeflag); | |
17302 | return; | |
17303 | } | |
17304 | else | |
17305 | { | |
17306 | if (reg == -1) | |
17307 | { | |
17308 | reg = modrm.rm; | |
17309 | USED_REX (REX_B); | |
17310 | if (rex & REX_B) | |
17311 | reg += 8; | |
17312 | } | |
5f847646 JB |
17313 | if (address_mode != mode_64bit) |
17314 | reg &= 7; | |
922d8de8 DR |
17315 | } |
17316 | ||
17317 | switch (vex.length) | |
17318 | { | |
17319 | case 128: | |
b9733481 | 17320 | names = names_xmm; |
922d8de8 DR |
17321 | break; |
17322 | case 256: | |
b9733481 | 17323 | names = names_ymm; |
922d8de8 DR |
17324 | break; |
17325 | default: | |
17326 | abort (); | |
17327 | } | |
b9733481 | 17328 | oappend (names[reg]); |
922d8de8 DR |
17329 | } |
17330 | ||
a683cc34 SP |
17331 | static void |
17332 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17333 | { | |
17334 | int reg = -1; | |
17335 | static unsigned char vex_imm8; | |
17336 | ||
17337 | if (vex_w_done == 0) | |
17338 | { | |
17339 | vex_w_done = 1; | |
17340 | ||
17341 | /* Skip mod/rm byte. */ | |
17342 | MODRM_CHECK; | |
17343 | codep++; | |
17344 | ||
17345 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17346 | ||
17347 | if (vex.w) | |
17348 | reg = vex_imm8 >> 4; | |
17349 | ||
17350 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17351 | } | |
17352 | else if (vex_w_done == 1) | |
17353 | { | |
17354 | vex_w_done = 2; | |
17355 | ||
17356 | if (!vex.w) | |
17357 | reg = vex_imm8 >> 4; | |
17358 | ||
17359 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17360 | } | |
17361 | else | |
17362 | { | |
17363 | /* Output the imm8 directly. */ | |
17364 | scratchbuf[0] = '$'; | |
17365 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17366 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17367 | scratchbuf[0] = '\0'; |
17368 | codep++; | |
17369 | } | |
17370 | } | |
17371 | ||
5dd85c99 SP |
17372 | static void |
17373 | OP_Vex_2src (int bytemode, int sizeflag) | |
17374 | { | |
17375 | if (modrm.mod == 3) | |
17376 | { | |
b9733481 | 17377 | int reg = modrm.rm; |
5dd85c99 | 17378 | USED_REX (REX_B); |
b9733481 L |
17379 | if (rex & REX_B) |
17380 | reg += 8; | |
17381 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17382 | } |
17383 | else | |
17384 | { | |
17385 | if (intel_syntax | |
17386 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17387 | { | |
17388 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17389 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17390 | } | |
17391 | OP_E (bytemode, sizeflag); | |
17392 | } | |
17393 | } | |
17394 | ||
17395 | static void | |
17396 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17397 | { | |
17398 | if (modrm.mod == 3) | |
17399 | { | |
17400 | /* Skip mod/rm byte. */ | |
17401 | MODRM_CHECK; | |
17402 | codep++; | |
17403 | } | |
17404 | ||
17405 | if (vex.w) | |
5f847646 JB |
17406 | { |
17407 | unsigned int reg = vex.register_specifier; | |
17408 | ||
17409 | if (address_mode != mode_64bit) | |
17410 | reg &= 7; | |
17411 | oappend (names_xmm[reg]); | |
17412 | } | |
5dd85c99 SP |
17413 | else |
17414 | OP_Vex_2src (bytemode, sizeflag); | |
17415 | } | |
17416 | ||
17417 | static void | |
17418 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17419 | { | |
17420 | if (vex.w) | |
17421 | OP_Vex_2src (bytemode, sizeflag); | |
17422 | else | |
5f847646 JB |
17423 | { |
17424 | unsigned int reg = vex.register_specifier; | |
17425 | ||
17426 | if (address_mode != mode_64bit) | |
17427 | reg &= 7; | |
17428 | oappend (names_xmm[reg]); | |
17429 | } | |
5dd85c99 SP |
17430 | } |
17431 | ||
922d8de8 DR |
17432 | static void |
17433 | OP_EX_VexW (int bytemode, int sizeflag) | |
17434 | { | |
17435 | int reg = -1; | |
17436 | ||
17437 | if (!vex_w_done) | |
17438 | { | |
41effecb SP |
17439 | /* Skip mod/rm byte. */ |
17440 | MODRM_CHECK; | |
17441 | codep++; | |
17442 | ||
922d8de8 | 17443 | if (vex.w) |
ccc5981b | 17444 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17445 | } |
17446 | else | |
17447 | { | |
17448 | if (!vex.w) | |
ccc5981b | 17449 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17450 | } |
17451 | ||
17452 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 17453 | |
3a2430e0 JB |
17454 | if (vex_w_done) |
17455 | codep++; | |
17456 | vex_w_done = 1; | |
922d8de8 DR |
17457 | } |
17458 | ||
c0f3af97 L |
17459 | static void |
17460 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17461 | { | |
17462 | int reg; | |
b9733481 L |
17463 | const char **names; |
17464 | ||
c0f3af97 L |
17465 | FETCH_DATA (the_info, codep + 1); |
17466 | reg = *codep++; | |
17467 | ||
17468 | if (bytemode != x_mode) | |
17469 | abort (); | |
17470 | ||
c0f3af97 | 17471 | reg >>= 4; |
5f847646 JB |
17472 | if (address_mode != mode_64bit) |
17473 | reg &= 7; | |
dae39acc | 17474 | |
c0f3af97 L |
17475 | switch (vex.length) |
17476 | { | |
17477 | case 128: | |
b9733481 | 17478 | names = names_xmm; |
c0f3af97 L |
17479 | break; |
17480 | case 256: | |
b9733481 | 17481 | names = names_ymm; |
c0f3af97 L |
17482 | break; |
17483 | default: | |
17484 | abort (); | |
17485 | } | |
b9733481 | 17486 | oappend (names[reg]); |
c0f3af97 L |
17487 | } |
17488 | ||
922d8de8 DR |
17489 | static void |
17490 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17491 | { | |
17492 | /* Turn off the REX.W bit since it is used for swapping operands | |
17493 | now. */ | |
17494 | rex &= ~REX_W; | |
17495 | OP_XMM (bytemode, sizeflag); | |
17496 | } | |
17497 | ||
c0f3af97 L |
17498 | static void |
17499 | OP_EX_Vex (int bytemode, int sizeflag) | |
17500 | { | |
17501 | if (modrm.mod != 3) | |
17502 | { | |
17503 | if (vex.register_specifier != 0) | |
17504 | BadOp (); | |
17505 | need_vex_reg = 0; | |
17506 | } | |
17507 | OP_EX (bytemode, sizeflag); | |
17508 | } | |
17509 | ||
17510 | static void | |
17511 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17512 | { | |
17513 | if (modrm.mod != 3) | |
17514 | { | |
17515 | if (vex.register_specifier != 0) | |
17516 | BadOp (); | |
17517 | need_vex_reg = 0; | |
17518 | } | |
17519 | OP_XMM (bytemode, sizeflag); | |
17520 | } | |
17521 | ||
17522 | static void | |
17523 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17524 | { | |
17525 | switch (vex.length) | |
17526 | { | |
17527 | case 128: | |
ea397f5b | 17528 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17529 | break; |
17530 | case 256: | |
ea397f5b | 17531 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17532 | break; |
17533 | default: | |
17534 | abort (); | |
17535 | } | |
17536 | } | |
17537 | ||
ea397f5b L |
17538 | static struct op vex_cmp_op[] = |
17539 | { | |
17540 | { STRING_COMMA_LEN ("eq") }, | |
17541 | { STRING_COMMA_LEN ("lt") }, | |
17542 | { STRING_COMMA_LEN ("le") }, | |
17543 | { STRING_COMMA_LEN ("unord") }, | |
17544 | { STRING_COMMA_LEN ("neq") }, | |
17545 | { STRING_COMMA_LEN ("nlt") }, | |
17546 | { STRING_COMMA_LEN ("nle") }, | |
17547 | { STRING_COMMA_LEN ("ord") }, | |
17548 | { STRING_COMMA_LEN ("eq_uq") }, | |
17549 | { STRING_COMMA_LEN ("nge") }, | |
17550 | { STRING_COMMA_LEN ("ngt") }, | |
17551 | { STRING_COMMA_LEN ("false") }, | |
17552 | { STRING_COMMA_LEN ("neq_oq") }, | |
17553 | { STRING_COMMA_LEN ("ge") }, | |
17554 | { STRING_COMMA_LEN ("gt") }, | |
17555 | { STRING_COMMA_LEN ("true") }, | |
17556 | { STRING_COMMA_LEN ("eq_os") }, | |
17557 | { STRING_COMMA_LEN ("lt_oq") }, | |
17558 | { STRING_COMMA_LEN ("le_oq") }, | |
17559 | { STRING_COMMA_LEN ("unord_s") }, | |
17560 | { STRING_COMMA_LEN ("neq_us") }, | |
17561 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17562 | { STRING_COMMA_LEN ("nle_uq") }, | |
17563 | { STRING_COMMA_LEN ("ord_s") }, | |
17564 | { STRING_COMMA_LEN ("eq_us") }, | |
17565 | { STRING_COMMA_LEN ("nge_uq") }, | |
17566 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17567 | { STRING_COMMA_LEN ("false_os") }, | |
17568 | { STRING_COMMA_LEN ("neq_os") }, | |
17569 | { STRING_COMMA_LEN ("ge_oq") }, | |
17570 | { STRING_COMMA_LEN ("gt_oq") }, | |
17571 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17572 | }; |
17573 | ||
17574 | static void | |
17575 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17576 | { | |
17577 | unsigned int cmp_type; | |
17578 | ||
17579 | FETCH_DATA (the_info, codep + 1); | |
17580 | cmp_type = *codep++ & 0xff; | |
17581 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17582 | { | |
17583 | char suffix [3]; | |
ea397f5b | 17584 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17585 | suffix[0] = p[0]; |
17586 | suffix[1] = p[1]; | |
17587 | suffix[2] = '\0'; | |
ea397f5b L |
17588 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17589 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17590 | } |
17591 | else | |
17592 | { | |
17593 | /* We have a reserved extension byte. Output it directly. */ | |
17594 | scratchbuf[0] = '$'; | |
17595 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17596 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17597 | scratchbuf[0] = '\0'; |
17598 | } | |
17599 | } | |
17600 | ||
43234a1e L |
17601 | static void |
17602 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17603 | int sizeflag ATTRIBUTE_UNUSED) | |
17604 | { | |
17605 | unsigned int cmp_type; | |
17606 | ||
17607 | if (!vex.evex) | |
17608 | abort (); | |
17609 | ||
17610 | FETCH_DATA (the_info, codep + 1); | |
17611 | cmp_type = *codep++ & 0xff; | |
17612 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17613 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17614 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17615 | && cmp_type != 3 | |
17616 | && cmp_type != 7) | |
17617 | { | |
17618 | char suffix [3]; | |
17619 | char *p = mnemonicendp - 2; | |
17620 | ||
17621 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17622 | if (p[0] == 'p') | |
17623 | { | |
17624 | p++; | |
17625 | suffix[0] = p[0]; | |
17626 | suffix[1] = '\0'; | |
17627 | } | |
17628 | else | |
17629 | { | |
17630 | suffix[0] = p[0]; | |
17631 | suffix[1] = p[1]; | |
17632 | suffix[2] = '\0'; | |
17633 | } | |
17634 | ||
17635 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17636 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17637 | } | |
be92cb14 JB |
17638 | else |
17639 | { | |
17640 | /* We have a reserved extension byte. Output it directly. */ | |
17641 | scratchbuf[0] = '$'; | |
17642 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
17643 | oappend_maybe_intel (scratchbuf); | |
17644 | scratchbuf[0] = '\0'; | |
17645 | } | |
17646 | } | |
17647 | ||
17648 | static const struct op xop_cmp_op[] = | |
17649 | { | |
17650 | { STRING_COMMA_LEN ("lt") }, | |
17651 | { STRING_COMMA_LEN ("le") }, | |
17652 | { STRING_COMMA_LEN ("gt") }, | |
17653 | { STRING_COMMA_LEN ("ge") }, | |
17654 | { STRING_COMMA_LEN ("eq") }, | |
17655 | { STRING_COMMA_LEN ("neq") }, | |
17656 | { STRING_COMMA_LEN ("false") }, | |
17657 | { STRING_COMMA_LEN ("true") } | |
17658 | }; | |
17659 | ||
17660 | static void | |
17661 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17662 | int sizeflag ATTRIBUTE_UNUSED) | |
17663 | { | |
17664 | unsigned int cmp_type; | |
17665 | ||
17666 | FETCH_DATA (the_info, codep + 1); | |
17667 | cmp_type = *codep++ & 0xff; | |
17668 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
17669 | { | |
17670 | char suffix[3]; | |
17671 | char *p = mnemonicendp - 2; | |
17672 | ||
17673 | /* vpcom* can have both one- and two-lettered suffix. */ | |
17674 | if (p[0] == 'm') | |
17675 | { | |
17676 | p++; | |
17677 | suffix[0] = p[0]; | |
17678 | suffix[1] = '\0'; | |
17679 | } | |
17680 | else | |
17681 | { | |
17682 | suffix[0] = p[0]; | |
17683 | suffix[1] = p[1]; | |
17684 | suffix[2] = '\0'; | |
17685 | } | |
17686 | ||
17687 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
17688 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
17689 | } | |
43234a1e L |
17690 | else |
17691 | { | |
17692 | /* We have a reserved extension byte. Output it directly. */ | |
17693 | scratchbuf[0] = '$'; | |
17694 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17695 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17696 | scratchbuf[0] = '\0'; |
17697 | } | |
17698 | } | |
17699 | ||
ea397f5b L |
17700 | static const struct op pclmul_op[] = |
17701 | { | |
17702 | { STRING_COMMA_LEN ("lql") }, | |
17703 | { STRING_COMMA_LEN ("hql") }, | |
17704 | { STRING_COMMA_LEN ("lqh") }, | |
17705 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17706 | }; |
17707 | ||
17708 | static void | |
17709 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17710 | int sizeflag ATTRIBUTE_UNUSED) | |
17711 | { | |
17712 | unsigned int pclmul_type; | |
17713 | ||
17714 | FETCH_DATA (the_info, codep + 1); | |
17715 | pclmul_type = *codep++ & 0xff; | |
17716 | switch (pclmul_type) | |
17717 | { | |
17718 | case 0x10: | |
17719 | pclmul_type = 2; | |
17720 | break; | |
17721 | case 0x11: | |
17722 | pclmul_type = 3; | |
17723 | break; | |
17724 | default: | |
17725 | break; | |
7bb15c6f | 17726 | } |
c0f3af97 L |
17727 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17728 | { | |
17729 | char suffix [4]; | |
ea397f5b | 17730 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17731 | suffix[0] = p[0]; |
17732 | suffix[1] = p[1]; | |
17733 | suffix[2] = p[2]; | |
17734 | suffix[3] = '\0'; | |
ea397f5b L |
17735 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17736 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17737 | } |
17738 | else | |
17739 | { | |
17740 | /* We have a reserved extension byte. Output it directly. */ | |
17741 | scratchbuf[0] = '$'; | |
17742 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17743 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17744 | scratchbuf[0] = '\0'; |
17745 | } | |
17746 | } | |
17747 | ||
f1f8f695 L |
17748 | static void |
17749 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17750 | { | |
17751 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17752 | char *p = mnemonicendp; |
f1f8f695 L |
17753 | |
17754 | switch (bytemode) | |
17755 | { | |
17756 | case v_mode: | |
17757 | if (intel_syntax) | |
ea397f5b | 17758 | goto skip; |
f1f8f695 L |
17759 | |
17760 | USED_REX (REX_W); | |
17761 | if (sizeflag & SUFFIX_ALWAYS) | |
17762 | { | |
17763 | if (rex & REX_W) | |
17764 | *p++ = 'q'; | |
f1f8f695 | 17765 | else |
f16cd0d5 L |
17766 | { |
17767 | if (sizeflag & DFLAG) | |
17768 | *p++ = 'l'; | |
17769 | else | |
17770 | *p++ = 'w'; | |
17771 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17772 | } | |
f1f8f695 | 17773 | } |
f1f8f695 L |
17774 | break; |
17775 | default: | |
17776 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17777 | break; | |
17778 | } | |
ea397f5b | 17779 | mnemonicendp = p; |
f1f8f695 L |
17780 | *p = '\0'; |
17781 | ||
ea397f5b | 17782 | skip: |
f1f8f695 L |
17783 | OP_M (bytemode, sizeflag); |
17784 | } | |
f88c9eb0 SP |
17785 | |
17786 | static void | |
17787 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17788 | { | |
17789 | int reg; | |
17790 | const char **names; | |
17791 | ||
17792 | /* Skip mod/rm byte. */ | |
17793 | MODRM_CHECK; | |
17794 | codep++; | |
17795 | ||
390a6789 | 17796 | if (rex & REX_W) |
f88c9eb0 | 17797 | names = names64; |
f88c9eb0 | 17798 | else |
ce7d077e | 17799 | names = names32; |
f88c9eb0 SP |
17800 | |
17801 | reg = modrm.rm; | |
17802 | USED_REX (REX_B); | |
17803 | if (rex & REX_B) | |
17804 | reg += 8; | |
17805 | ||
17806 | oappend (names[reg]); | |
17807 | } | |
17808 | ||
17809 | static void | |
17810 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17811 | { | |
17812 | const char **names; | |
5f847646 | 17813 | unsigned int reg = vex.register_specifier; |
f88c9eb0 | 17814 | |
390a6789 | 17815 | if (rex & REX_W) |
f88c9eb0 | 17816 | names = names64; |
f88c9eb0 | 17817 | else |
ce7d077e | 17818 | names = names32; |
f88c9eb0 | 17819 | |
5f847646 JB |
17820 | if (address_mode != mode_64bit) |
17821 | reg &= 7; | |
17822 | oappend (names[reg]); | |
f88c9eb0 | 17823 | } |
43234a1e L |
17824 | |
17825 | static void | |
17826 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17827 | { | |
17828 | if (!vex.evex | |
1ba585e8 | 17829 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17830 | abort (); |
17831 | ||
17832 | USED_REX (REX_R); | |
17833 | if ((rex & REX_R) != 0 || !vex.r) | |
17834 | { | |
17835 | BadOp (); | |
17836 | return; | |
17837 | } | |
17838 | ||
17839 | oappend (names_mask [modrm.reg]); | |
17840 | } | |
17841 | ||
17842 | static void | |
17843 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17844 | { | |
17845 | if (!vex.evex | |
17846 | || (bytemode != evex_rounding_mode | |
17847 | && bytemode != evex_sae_mode)) | |
17848 | abort (); | |
17849 | if (modrm.mod == 3 && vex.b) | |
17850 | switch (bytemode) | |
17851 | { | |
17852 | case evex_rounding_mode: | |
17853 | oappend (names_rounding[vex.ll]); | |
17854 | break; | |
17855 | case evex_sae_mode: | |
17856 | oappend ("{sae}"); | |
17857 | break; | |
17858 | default: | |
17859 | break; | |
17860 | } | |
17861 | } |